xref: /openbmc/u-boot/drivers/net/armada100_fec.h (revision e8f80a5a)
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * (C) Copyright 2011
4  * eInfochips Ltd. <www.einfochips.com>
5  * Written-by: Ajay Bhargav <contact@8051projects.net>
6  *
7  * (C) Copyright 2010
8  * Marvell Semiconductor <www.marvell.com>
9  * Contributor: Mahavir Jain <mjain@marvell.com>
10  */
11 
12 #ifndef __ARMADA100_FEC_H__
13 #define __ARMADA100_FEC_H__
14 
15 #define PORT_NUM		0x0
16 
17 /* RX & TX descriptor command */
18 #define BUF_OWNED_BY_DMA        (1<<31)
19 
20 /* RX descriptor status */
21 #define RX_EN_INT               (1<<23)
22 #define RX_FIRST_DESC           (1<<17)
23 #define RX_LAST_DESC            (1<<16)
24 #define RX_ERROR                (1<<15)
25 
26 /* TX descriptor command */
27 #define TX_EN_INT               (1<<23)
28 #define TX_GEN_CRC              (1<<22)
29 #define TX_ZERO_PADDING         (1<<18)
30 #define TX_FIRST_DESC           (1<<17)
31 #define TX_LAST_DESC            (1<<16)
32 #define TX_ERROR                (1<<15)
33 
34 /* smi register */
35 #define SMI_BUSY                (1<<28)	/* 0 - Write, 1 - Read  */
36 #define SMI_R_VALID             (1<<27)	/* 0 - Write, 1 - Read  */
37 #define SMI_OP_W                (0<<26)	/* Write operation      */
38 #define SMI_OP_R                (1<<26)	/* Read operation */
39 
40 #define HASH_ADD                0
41 #define HASH_DELETE             1
42 #define HASH_ADDR_TABLE_SIZE    0x4000	/* 16K (1/2K address - PCR_HS == 1) */
43 #define HOP_NUMBER              12
44 
45 #define PHY_WAIT_ITERATIONS     1000	/* 1000 iterations * 10uS = 10mS max */
46 #define PHY_WAIT_MICRO_SECONDS  10
47 
48 #define ETH_HW_IP_ALIGN         2	/* hw aligns IP header */
49 #define ETH_EXTRA_HEADER        (6+6+2+4)
50 					/* dest+src addr+protocol id+crc */
51 #define MAX_PKT_SIZE            1536
52 
53 
54 /* Bit definitions of the SDMA Config Reg */
55 #define SDCR_BSZ_OFF            12
56 #define SDCR_BSZ8               (3<<SDCR_BSZ_OFF)
57 #define SDCR_BSZ4               (2<<SDCR_BSZ_OFF)
58 #define SDCR_BSZ2               (1<<SDCR_BSZ_OFF)
59 #define SDCR_BSZ1               (0<<SDCR_BSZ_OFF)
60 #define SDCR_BLMR               (1<<6)
61 #define SDCR_BLMT               (1<<7)
62 #define SDCR_RIFB               (1<<9)
63 #define SDCR_RC_OFF             2
64 #define SDCR_RC_MAX_RETRANS     (0xf << SDCR_RC_OFF)
65 
66 /* SDMA_CMD */
67 #define SDMA_CMD_AT             (1<<31)
68 #define SDMA_CMD_TXDL           (1<<24)
69 #define SDMA_CMD_TXDH           (1<<23)
70 #define SDMA_CMD_AR             (1<<15)
71 #define SDMA_CMD_ERD            (1<<7)
72 
73 
74 /* Bit definitions of the Port Config Reg */
75 #define PCR_HS                  (1<<12)
76 #define PCR_EN                  (1<<7)
77 #define PCR_PM                  (1<<0)
78 
79 /* Bit definitions of the Port Config Extend Reg */
80 #define PCXR_2BSM               (1<<28)
81 #define PCXR_DSCP_EN            (1<<21)
82 #define PCXR_MFL_1518           (0<<14)
83 #define PCXR_MFL_1536           (1<<14)
84 #define PCXR_MFL_2048           (2<<14)
85 #define PCXR_MFL_64K            (3<<14)
86 #define PCXR_FLP                (1<<11)
87 #define PCXR_PRIO_TX_OFF        3
88 #define PCXR_TX_HIGH_PRI        (7<<PCXR_PRIO_TX_OFF)
89 
90 /*
91  *  * Bit definitions of the Interrupt Cause Reg
92  *   * and Interrupt MASK Reg is the same
93  *    */
94 #define ICR_RXBUF               (1<<0)
95 #define ICR_TXBUF_H             (1<<2)
96 #define ICR_TXBUF_L             (1<<3)
97 #define ICR_TXEND_H             (1<<6)
98 #define ICR_TXEND_L             (1<<7)
99 #define ICR_RXERR               (1<<8)
100 #define ICR_TXERR_H             (1<<10)
101 #define ICR_TXERR_L             (1<<11)
102 #define ICR_TX_UDR              (1<<13)
103 #define ICR_MII_CH              (1<<28)
104 
105 #define ALL_INTS (ICR_TXBUF_H  | ICR_TXBUF_L  | ICR_TX_UDR |\
106 				ICR_TXERR_H  | ICR_TXERR_L |\
107 				ICR_TXEND_H  | ICR_TXEND_L |\
108 				ICR_RXBUF | ICR_RXERR  | ICR_MII_CH)
109 
110 #define PHY_MASK               0x0000001f
111 
112 #define to_darmdfec(_kd) container_of(_kd, struct armdfec_device, dev)
113 /* Size of a Tx/Rx descriptor used in chain list data structure */
114 #define ARMDFEC_RXQ_DESC_ALIGNED_SIZE \
115 	(((sizeof(struct rx_desc) / PKTALIGN) + 1) * PKTALIGN)
116 
117 #define RX_BUF_OFFSET		0x2
118 #define RXQ			0x0	/* RX Queue 0 */
119 #define TXQ			0x1	/* TX Queue 1 */
120 
121 struct addr_table_entry_t {
122 	u32 lo;
123 	u32 hi;
124 };
125 
126 /* Bit fields of a Hash Table Entry */
127 enum hash_table_entry {
128 	HTEVALID = 1,
129 	HTESKIP = 2,
130 	HTERD = 4,
131 	HTERDBIT = 2
132 };
133 
134 struct tx_desc {
135 	u32 cmd_sts;		/* Command/status field */
136 	u16 reserved;
137 	u16 byte_cnt;		/* buffer byte count */
138 	u8 *buf_ptr;		/* pointer to buffer for this descriptor */
139 	struct tx_desc *nextdesc_p;	/* Pointer to next descriptor */
140 };
141 
142 struct rx_desc {
143 	u32 cmd_sts;		/* Descriptor command status */
144 	u16 byte_cnt;		/* Descriptor buffer byte count */
145 	u16 buf_size;		/* Buffer size */
146 	u8 *buf_ptr;		/* Descriptor buffer pointer */
147 	struct rx_desc *nxtdesc_p;	/* Next descriptor pointer */
148 };
149 
150 /*
151  * Armada100 Fast Ethernet controller Registers
152  * Refer Datasheet Appendix A.22
153  */
154 struct armdfec_reg {
155 	u32 phyadr;			/* PHY Address */
156 	u32 pad1[3];
157 	u32 smi;			/* SMI */
158 	u32 pad2[0xFB];
159 	u32 pconf;			/* Port configuration */
160 	u32 pad3;
161 	u32 pconf_ext;			/* Port configuration extend */
162 	u32 pad4;
163 	u32 pcmd;			/* Port Command */
164 	u32 pad5;
165 	u32 pstatus;			/* Port Status */
166 	u32 pad6;
167 	u32 spar;			/* Serial Parameters */
168 	u32 pad7;
169 	u32 htpr;			/* Hash table pointer */
170 	u32 pad8;
171 	u32 fcsal;			/* Flow control source address low */
172 	u32 pad9;
173 	u32 fcsah;			/* Flow control source address high */
174 	u32 pad10;
175 	u32 sdma_conf;			/* SDMA configuration */
176 	u32 pad11;
177 	u32 sdma_cmd;			/* SDMA command */
178 	u32 pad12;
179 	u32 ic;				/* Interrupt cause */
180 	u32 iwc;			/* Interrupt write to clear */
181 	u32 im;				/* Interrupt mask */
182 	u32 pad13;
183 	u32 *eth_idscpp[4];		/* Eth0 IP Differentiated Services Code
184 					   Point to Priority 0 Low */
185 	u32 eth_vlan_p;			/* Eth0 VLAN Priority Tag to Priority */
186 	u32 pad14[3];
187 	struct rx_desc *rxfdp[4];	/* Ethernet First Rx Descriptor
188 					   Pointer */
189 	u32 pad15[4];
190 	struct rx_desc *rxcdp[4];	/* Ethernet Current Rx Descriptor
191 					   Pointer */
192 	u32 pad16[0x0C];
193 	struct tx_desc *txcdp[2];	/* Ethernet Current Tx Descriptor
194 					   Pointer */
195 };
196 
197 struct armdfec_device {
198 	struct eth_device dev;
199 	struct armdfec_reg *regs;
200 	struct tx_desc *p_txdesc;
201 	struct rx_desc *p_rxdesc;
202 	struct rx_desc *p_rxdesc_curr;
203 	u8 *p_rxbuf;
204 	u8 *p_aligned_txbuf;
205 	u8 *htpr;		/* hash pointer */
206 };
207 
208 #endif /* __ARMADA100_FEC_H__ */
209