1 /* Support for generating ACPI tables and passing them to Guests
2 *
3 * ARM virt ACPI generation
4 *
5 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>
6 * Copyright (C) 2006 Fabrice Bellard
7 * Copyright (C) 2013 Red Hat Inc
8 *
9 * Author: Michael S. Tsirkin <mst@redhat.com>
10 *
11 * Copyright (c) 2015 HUAWEI TECHNOLOGIES CO.,LTD.
12 *
13 * Author: Shannon Zhao <zhaoshenglong@huawei.com>
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
19
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24
25 * You should have received a copy of the GNU General Public License along
26 * with this program; if not, see <http://www.gnu.org/licenses/>.
27 */
28
29 #include "qemu/osdep.h"
30 #include "qapi/error.h"
31 #include "qemu/bitmap.h"
32 #include "qemu/error-report.h"
33 #include "trace.h"
34 #include "hw/core/cpu.h"
35 #include "hw/acpi/acpi-defs.h"
36 #include "hw/acpi/acpi.h"
37 #include "hw/acpi/pcihp.h"
38 #include "hw/nvram/fw_cfg_acpi.h"
39 #include "hw/acpi/bios-linker-loader.h"
40 #include "hw/acpi/aml-build.h"
41 #include "hw/acpi/utils.h"
42 #include "hw/acpi/pci.h"
43 #include "hw/acpi/cxl.h"
44 #include "hw/acpi/memory_hotplug.h"
45 #include "hw/acpi/generic_event_device.h"
46 #include "hw/acpi/tpm.h"
47 #include "hw/acpi/hmat.h"
48 #include "hw/cxl/cxl.h"
49 #include "hw/pci/pcie_host.h"
50 #include "hw/pci/pci.h"
51 #include "hw/pci/pci_bus.h"
52 #include "hw/pci-host/gpex.h"
53 #include "hw/arm/virt.h"
54 #include "hw/intc/arm_gicv3_its_common.h"
55 #include "hw/mem/nvdimm.h"
56 #include "hw/platform-bus.h"
57 #include "system/numa.h"
58 #include "system/reset.h"
59 #include "system/tpm.h"
60 #include "migration/vmstate.h"
61 #include "hw/acpi/ghes.h"
62 #include "hw/acpi/viot.h"
63 #include "hw/virtio/virtio-acpi.h"
64 #include "target/arm/multiprocessing.h"
65
66 #define ARM_SPI_BASE 32
67
68 #define ACPI_BUILD_TABLE_SIZE 0x20000
69
acpi_dsdt_add_cpus(Aml * scope,VirtMachineState * vms)70 static void acpi_dsdt_add_cpus(Aml *scope, VirtMachineState *vms)
71 {
72 MachineState *ms = MACHINE(vms);
73 uint16_t i;
74
75 for (i = 0; i < ms->smp.cpus; i++) {
76 Aml *dev = aml_device("C%.03X", i);
77 aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0007")));
78 aml_append(dev, aml_name_decl("_UID", aml_int(i)));
79 aml_append(scope, dev);
80 }
81 }
82
acpi_dsdt_add_uart(Aml * scope,const MemMapEntry * uart_memmap,uint32_t uart_irq,int uartidx)83 static void acpi_dsdt_add_uart(Aml *scope, const MemMapEntry *uart_memmap,
84 uint32_t uart_irq, int uartidx)
85 {
86 Aml *dev = aml_device("COM%d", uartidx);
87 aml_append(dev, aml_name_decl("_HID", aml_string("ARMH0011")));
88 aml_append(dev, aml_name_decl("_UID", aml_int(uartidx)));
89
90 Aml *crs = aml_resource_template();
91 aml_append(crs, aml_memory32_fixed(uart_memmap->base,
92 uart_memmap->size, AML_READ_WRITE));
93 aml_append(crs,
94 aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
95 AML_EXCLUSIVE, &uart_irq, 1));
96 aml_append(dev, aml_name_decl("_CRS", crs));
97
98 aml_append(scope, dev);
99 }
100
acpi_dsdt_add_flash(Aml * scope,const MemMapEntry * flash_memmap)101 static void acpi_dsdt_add_flash(Aml *scope, const MemMapEntry *flash_memmap)
102 {
103 Aml *dev, *crs;
104 hwaddr base = flash_memmap->base;
105 hwaddr size = flash_memmap->size / 2;
106
107 dev = aml_device("FLS0");
108 aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0015")));
109 aml_append(dev, aml_name_decl("_UID", aml_int(0)));
110
111 crs = aml_resource_template();
112 aml_append(crs, aml_memory32_fixed(base, size, AML_READ_WRITE));
113 aml_append(dev, aml_name_decl("_CRS", crs));
114 aml_append(scope, dev);
115
116 dev = aml_device("FLS1");
117 aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0015")));
118 aml_append(dev, aml_name_decl("_UID", aml_int(1)));
119 crs = aml_resource_template();
120 aml_append(crs, aml_memory32_fixed(base + size, size, AML_READ_WRITE));
121 aml_append(dev, aml_name_decl("_CRS", crs));
122 aml_append(scope, dev);
123 }
124
build_acpi0017(Aml * table)125 static void build_acpi0017(Aml *table)
126 {
127 Aml *dev, *scope, *method;
128
129 scope = aml_scope("_SB");
130 dev = aml_device("CXLM");
131 aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0017")));
132
133 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
134 aml_append(method, aml_return(aml_int(0x0B)));
135 aml_append(dev, method);
136 build_cxl_dsm_method(dev);
137
138 aml_append(scope, dev);
139 aml_append(table, scope);
140 }
141
acpi_dsdt_add_pci(Aml * scope,const MemMapEntry * memmap,uint32_t irq,VirtMachineState * vms)142 static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap,
143 uint32_t irq, VirtMachineState *vms)
144 {
145 int ecam_id = VIRT_ECAM_ID(vms->highmem_ecam);
146 bool cxl_present = false;
147 PCIBus *bus = vms->bus;
148 bool acpi_pcihp = false;
149
150 if (vms->acpi_dev) {
151 acpi_pcihp = object_property_get_bool(OBJECT(vms->acpi_dev),
152 ACPI_PM_PROP_ACPI_PCIHP_BRIDGE,
153 NULL);
154 }
155
156 struct GPEXConfig cfg = {
157 .mmio32 = memmap[VIRT_PCIE_MMIO],
158 .pio = memmap[VIRT_PCIE_PIO],
159 .ecam = memmap[ecam_id],
160 .irq = irq,
161 .bus = vms->bus,
162 .pci_native_hotplug = !acpi_pcihp,
163 };
164
165 if (vms->highmem_mmio) {
166 cfg.mmio64 = memmap[VIRT_HIGH_PCIE_MMIO];
167 }
168
169 acpi_dsdt_add_gpex(scope, &cfg);
170 QLIST_FOREACH(bus, &vms->bus->child, sibling) {
171 if (pci_bus_is_cxl(bus)) {
172 cxl_present = true;
173 }
174 }
175 if (cxl_present) {
176 build_acpi0017(scope);
177 }
178 }
179
acpi_dsdt_add_gpio(Aml * scope,const MemMapEntry * gpio_memmap,uint32_t gpio_irq)180 static void acpi_dsdt_add_gpio(Aml *scope, const MemMapEntry *gpio_memmap,
181 uint32_t gpio_irq)
182 {
183 Aml *dev = aml_device("GPO0");
184 aml_append(dev, aml_name_decl("_HID", aml_string("ARMH0061")));
185 aml_append(dev, aml_name_decl("_UID", aml_int(0)));
186
187 Aml *crs = aml_resource_template();
188 aml_append(crs, aml_memory32_fixed(gpio_memmap->base, gpio_memmap->size,
189 AML_READ_WRITE));
190 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
191 AML_EXCLUSIVE, &gpio_irq, 1));
192 aml_append(dev, aml_name_decl("_CRS", crs));
193
194 Aml *aei = aml_resource_template();
195
196 const uint32_t pin = GPIO_PIN_POWER_BUTTON;
197 aml_append(aei, aml_gpio_int(AML_CONSUMER, AML_EDGE, AML_ACTIVE_HIGH,
198 AML_EXCLUSIVE, AML_PULL_UP, 0, &pin, 1,
199 "GPO0", NULL, 0));
200 aml_append(dev, aml_name_decl("_AEI", aei));
201
202 /* _E03 is handle for power button */
203 Aml *method = aml_method("_E03", 0, AML_NOTSERIALIZED);
204 aml_append(method, aml_notify(aml_name(ACPI_POWER_BUTTON_DEVICE),
205 aml_int(0x80)));
206 aml_append(dev, method);
207 aml_append(scope, dev);
208 }
209
210 #ifdef CONFIG_TPM
acpi_dsdt_add_tpm(Aml * scope,VirtMachineState * vms)211 static void acpi_dsdt_add_tpm(Aml *scope, VirtMachineState *vms)
212 {
213 PlatformBusDevice *pbus = PLATFORM_BUS_DEVICE(vms->platform_bus_dev);
214 hwaddr pbus_base = vms->memmap[VIRT_PLATFORM_BUS].base;
215 SysBusDevice *sbdev = SYS_BUS_DEVICE(tpm_find());
216 MemoryRegion *sbdev_mr;
217 hwaddr tpm_base;
218
219 if (!sbdev) {
220 return;
221 }
222
223 tpm_base = platform_bus_get_mmio_addr(pbus, sbdev, 0);
224 assert(tpm_base != -1);
225
226 tpm_base += pbus_base;
227
228 sbdev_mr = sysbus_mmio_get_region(sbdev, 0);
229
230 Aml *dev = aml_device("TPM0");
231 aml_append(dev, aml_name_decl("_HID", aml_string("MSFT0101")));
232 aml_append(dev, aml_name_decl("_STR", aml_string("TPM 2.0 Device")));
233 aml_append(dev, aml_name_decl("_UID", aml_int(0)));
234
235 Aml *crs = aml_resource_template();
236 aml_append(crs,
237 aml_memory32_fixed(tpm_base,
238 (uint32_t)memory_region_size(sbdev_mr),
239 AML_READ_WRITE));
240 aml_append(dev, aml_name_decl("_CRS", crs));
241 aml_append(scope, dev);
242 }
243 #endif
244
245 #define ID_MAPPING_ENTRY_SIZE 20
246 #define SMMU_V3_ENTRY_SIZE 68
247 #define ROOT_COMPLEX_ENTRY_SIZE 36
248 #define IORT_NODE_OFFSET 48
249
250 /*
251 * Append an ID mapping entry as described by "Table 4 ID mapping format" in
252 * "IO Remapping Table System Software on ARM Platforms", Chapter 3.
253 * Document number: ARM DEN 0049E.f, Apr 2024
254 *
255 * Note that @id_count gets internally subtracted by one, following the spec.
256 */
build_iort_id_mapping(GArray * table_data,uint32_t input_base,uint32_t id_count,uint32_t out_ref)257 static void build_iort_id_mapping(GArray *table_data, uint32_t input_base,
258 uint32_t id_count, uint32_t out_ref)
259 {
260 build_append_int_noprefix(table_data, input_base, 4); /* Input base */
261 /* Number of IDs - The number of IDs in the range minus one */
262 build_append_int_noprefix(table_data, id_count - 1, 4);
263 build_append_int_noprefix(table_data, input_base, 4); /* Output base */
264 build_append_int_noprefix(table_data, out_ref, 4); /* Output Reference */
265 /* Flags */
266 build_append_int_noprefix(table_data, 0 /* Single mapping (disabled) */, 4);
267 }
268
269 struct AcpiIortIdMapping {
270 uint32_t input_base;
271 uint32_t id_count;
272 };
273 typedef struct AcpiIortIdMapping AcpiIortIdMapping;
274
275 /* Build the iort ID mapping to SMMUv3 for a given PCI host bridge */
276 static int
iort_host_bridges(Object * obj,void * opaque)277 iort_host_bridges(Object *obj, void *opaque)
278 {
279 GArray *idmap_blob = opaque;
280
281 if (object_dynamic_cast(obj, TYPE_PCI_HOST_BRIDGE)) {
282 PCIBus *bus = PCI_HOST_BRIDGE(obj)->bus;
283
284 if (bus && !pci_bus_bypass_iommu(bus)) {
285 int min_bus, max_bus;
286
287 pci_bus_range(bus, &min_bus, &max_bus);
288
289 AcpiIortIdMapping idmap = {
290 .input_base = min_bus << 8,
291 .id_count = (max_bus - min_bus + 1) << 8,
292 };
293 g_array_append_val(idmap_blob, idmap);
294 }
295 }
296
297 return 0;
298 }
299
iort_idmap_compare(gconstpointer a,gconstpointer b)300 static int iort_idmap_compare(gconstpointer a, gconstpointer b)
301 {
302 AcpiIortIdMapping *idmap_a = (AcpiIortIdMapping *)a;
303 AcpiIortIdMapping *idmap_b = (AcpiIortIdMapping *)b;
304
305 return idmap_a->input_base - idmap_b->input_base;
306 }
307
308 /* Compute ID ranges (RIDs) from RC that are directed to the ITS Group node */
create_rc_its_idmaps(GArray * its_idmaps,GArray * smmu_idmaps)309 static void create_rc_its_idmaps(GArray *its_idmaps, GArray *smmu_idmaps)
310 {
311 AcpiIortIdMapping *idmap;
312 AcpiIortIdMapping next_range = {0};
313
314 /*
315 * Based on the RID ranges that are directed to the SMMU, determine the
316 * bypassed RID ranges, i.e., the ones that are directed to the ITS Group
317 * node and do not pass through the SMMU, by subtracting the SMMU-bound
318 * ranges from the full RID range (0x0000–0xFFFF).
319 */
320 for (int i = 0; i < smmu_idmaps->len; i++) {
321 idmap = &g_array_index(smmu_idmaps, AcpiIortIdMapping, i);
322
323 if (next_range.input_base < idmap->input_base) {
324 next_range.id_count = idmap->input_base - next_range.input_base;
325 g_array_append_val(its_idmaps, next_range);
326 }
327
328 next_range.input_base = idmap->input_base + idmap->id_count;
329 }
330
331 /*
332 * Append the last RC -> ITS ID mapping.
333 *
334 * RIDs are 16-bit, according to the PCI Express 2.0 Base Specification, rev
335 * 0.9, section 2.2.6.2, "Transaction Descriptor - Transaction ID Field",
336 * hence the end of the range is 0x10000.
337 */
338 if (next_range.input_base < 0x10000) {
339 next_range.id_count = 0x10000 - next_range.input_base;
340 g_array_append_val(its_idmaps, next_range);
341 }
342 }
343
344
345 /*
346 * Input Output Remapping Table (IORT)
347 * Conforms to "IO Remapping Table System Software on ARM Platforms",
348 * Document number: ARM DEN 0049E.b, Feb 2021
349 */
350 static void
build_iort(GArray * table_data,BIOSLinker * linker,VirtMachineState * vms)351 build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
352 {
353 int i, nb_nodes, rc_mapping_count;
354 size_t node_size, smmu_offset = 0;
355 uint32_t id = 0;
356 GArray *rc_smmu_idmaps = g_array_new(false, true, sizeof(AcpiIortIdMapping));
357 GArray *rc_its_idmaps = g_array_new(false, true, sizeof(AcpiIortIdMapping));
358
359 AcpiTable table = { .sig = "IORT", .rev = 3, .oem_id = vms->oem_id,
360 .oem_table_id = vms->oem_table_id };
361 /* Table 2 The IORT */
362 acpi_table_begin(&table, table_data);
363
364 if (vms->iommu == VIRT_IOMMU_SMMUV3) {
365 object_child_foreach_recursive(object_get_root(),
366 iort_host_bridges, rc_smmu_idmaps);
367
368 /* Sort the smmu idmap by input_base */
369 g_array_sort(rc_smmu_idmaps, iort_idmap_compare);
370
371 nb_nodes = 2; /* RC and SMMUv3 */
372 rc_mapping_count = rc_smmu_idmaps->len;
373
374 if (vms->its) {
375 /*
376 * Knowing the ID ranges from the RC to the SMMU, it's possible to
377 * determine the ID ranges from RC that go directly to ITS.
378 */
379 create_rc_its_idmaps(rc_its_idmaps, rc_smmu_idmaps);
380
381 nb_nodes++; /* ITS */
382 rc_mapping_count += rc_its_idmaps->len;
383 }
384 } else {
385 if (vms->its) {
386 nb_nodes = 2; /* RC and ITS */
387 rc_mapping_count = 1; /* Direct map to ITS */
388 } else {
389 nb_nodes = 1; /* RC only */
390 rc_mapping_count = 0; /* No output mapping */
391 }
392 }
393 /* Number of IORT Nodes */
394 build_append_int_noprefix(table_data, nb_nodes, 4);
395
396 /* Offset to Array of IORT Nodes */
397 build_append_int_noprefix(table_data, IORT_NODE_OFFSET, 4);
398 build_append_int_noprefix(table_data, 0, 4); /* Reserved */
399
400 if (vms->its) {
401 /* Table 12 ITS Group Format */
402 build_append_int_noprefix(table_data, 0 /* ITS Group */, 1); /* Type */
403 node_size = 20 /* fixed header size */ + 4 /* 1 GIC ITS Identifier */;
404 build_append_int_noprefix(table_data, node_size, 2); /* Length */
405 build_append_int_noprefix(table_data, 1, 1); /* Revision */
406 build_append_int_noprefix(table_data, id++, 4); /* Identifier */
407 build_append_int_noprefix(table_data, 0, 4); /* Number of ID mappings */
408 build_append_int_noprefix(table_data, 0, 4); /* Reference to ID Array */
409 build_append_int_noprefix(table_data, 1, 4); /* Number of ITSs */
410 /* GIC ITS Identifier Array */
411 build_append_int_noprefix(table_data, 0 /* MADT translation_id */, 4);
412 }
413
414 if (vms->iommu == VIRT_IOMMU_SMMUV3) {
415 int irq = vms->irqmap[VIRT_SMMU] + ARM_SPI_BASE;
416 int smmu_mapping_count, offset_to_id_array;
417
418 if (vms->its) {
419 smmu_mapping_count = 1; /* ITS Group node */
420 offset_to_id_array = SMMU_V3_ENTRY_SIZE; /* Just after the header */
421 } else {
422 smmu_mapping_count = 0; /* No ID mappings */
423 offset_to_id_array = 0; /* No ID mappings array */
424 }
425 smmu_offset = table_data->len - table.table_offset;
426 /* Table 9 SMMUv3 Format */
427 build_append_int_noprefix(table_data, 4 /* SMMUv3 */, 1); /* Type */
428 node_size = SMMU_V3_ENTRY_SIZE +
429 (ID_MAPPING_ENTRY_SIZE * smmu_mapping_count);
430 build_append_int_noprefix(table_data, node_size, 2); /* Length */
431 build_append_int_noprefix(table_data, 4, 1); /* Revision */
432 build_append_int_noprefix(table_data, id++, 4); /* Identifier */
433 /* Number of ID mappings */
434 build_append_int_noprefix(table_data, smmu_mapping_count, 4);
435 /* Reference to ID Array */
436 build_append_int_noprefix(table_data, offset_to_id_array, 4);
437 /* Base address */
438 build_append_int_noprefix(table_data, vms->memmap[VIRT_SMMU].base, 8);
439 /* Flags */
440 build_append_int_noprefix(table_data, 1 /* COHACC Override */, 4);
441 build_append_int_noprefix(table_data, 0, 4); /* Reserved */
442 build_append_int_noprefix(table_data, 0, 8); /* VATOS address */
443 /* Model */
444 build_append_int_noprefix(table_data, 0 /* Generic SMMU-v3 */, 4);
445 build_append_int_noprefix(table_data, irq, 4); /* Event */
446 build_append_int_noprefix(table_data, irq + 1, 4); /* PRI */
447 build_append_int_noprefix(table_data, irq + 3, 4); /* GERR */
448 build_append_int_noprefix(table_data, irq + 2, 4); /* Sync */
449 build_append_int_noprefix(table_data, 0, 4); /* Proximity domain */
450 /* DeviceID mapping index (ignored since interrupts are GSIV based) */
451 build_append_int_noprefix(table_data, 0, 4);
452 /* Array of ID mappings */
453 if (smmu_mapping_count) {
454 /* Output IORT node is the ITS Group node (the first node). */
455 build_iort_id_mapping(table_data, 0, 0x10000, IORT_NODE_OFFSET);
456 }
457 }
458
459 /* Table 17 Root Complex Node */
460 build_append_int_noprefix(table_data, 2 /* Root complex */, 1); /* Type */
461 node_size = ROOT_COMPLEX_ENTRY_SIZE +
462 ID_MAPPING_ENTRY_SIZE * rc_mapping_count;
463 build_append_int_noprefix(table_data, node_size, 2); /* Length */
464 build_append_int_noprefix(table_data, 3, 1); /* Revision */
465 build_append_int_noprefix(table_data, id++, 4); /* Identifier */
466 /* Number of ID mappings */
467 build_append_int_noprefix(table_data, rc_mapping_count, 4);
468 /* Reference to ID Array */
469 build_append_int_noprefix(table_data, ROOT_COMPLEX_ENTRY_SIZE, 4);
470
471 /* Table 14 Memory access properties */
472 /* CCA: Cache Coherent Attribute */
473 build_append_int_noprefix(table_data, 1 /* fully coherent */, 4);
474 build_append_int_noprefix(table_data, 0, 1); /* AH: Note Allocation Hints */
475 build_append_int_noprefix(table_data, 0, 2); /* Reserved */
476 /* Table 15 Memory Access Flags */
477 build_append_int_noprefix(table_data, 0x3 /* CCA = CPM = DACS = 1 */, 1);
478
479 build_append_int_noprefix(table_data, 0, 4); /* ATS Attribute */
480 /* MCFG pci_segment */
481 build_append_int_noprefix(table_data, 0, 4); /* PCI Segment number */
482
483 /* Memory address size limit */
484 build_append_int_noprefix(table_data, 64, 1);
485
486 build_append_int_noprefix(table_data, 0, 3); /* Reserved */
487
488 /* Output Reference */
489 if (vms->iommu == VIRT_IOMMU_SMMUV3) {
490 AcpiIortIdMapping *range;
491
492 /*
493 * Map RIDs (input) from RC to SMMUv3 nodes: RC -> SMMUv3.
494 *
495 * N.B.: The mapping from SMMUv3 to ITS Group node (SMMUv3 -> ITS) is
496 * defined in the SMMUv3 table, where all SMMUv3 IDs are mapped to the
497 * ITS Group node, if ITS is available.
498 */
499 for (i = 0; i < rc_smmu_idmaps->len; i++) {
500 range = &g_array_index(rc_smmu_idmaps, AcpiIortIdMapping, i);
501 /* Output IORT node is the SMMUv3 node. */
502 build_iort_id_mapping(table_data, range->input_base,
503 range->id_count, smmu_offset);
504 }
505
506 if (vms->its) {
507 /*
508 * Map bypassed (don't go through the SMMU) RIDs (input) to
509 * ITS Group node directly: RC -> ITS.
510 */
511 for (i = 0; i < rc_its_idmaps->len; i++) {
512 range = &g_array_index(rc_its_idmaps, AcpiIortIdMapping, i);
513 /* Output IORT node is the ITS Group node (the first node). */
514 build_iort_id_mapping(table_data, range->input_base,
515 range->id_count, IORT_NODE_OFFSET);
516 }
517 }
518 } else {
519 /*
520 * Map all RIDs (input) to ITS Group node directly, since there is no
521 * SMMU: RC -> ITS.
522 * Output IORT node is the ITS Group node (the first node).
523 */
524 build_iort_id_mapping(table_data, 0, 0x10000, IORT_NODE_OFFSET);
525 }
526
527 acpi_table_end(linker, &table);
528 g_array_free(rc_smmu_idmaps, true);
529 g_array_free(rc_its_idmaps, true);
530 }
531
532 /*
533 * Serial Port Console Redirection Table (SPCR)
534 * Rev: 1.07
535 */
536 static void
spcr_setup(GArray * table_data,BIOSLinker * linker,VirtMachineState * vms)537 spcr_setup(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
538 {
539 AcpiSpcrData serial = {
540 .interface_type = 3, /* ARM PL011 UART */
541 .base_addr.id = AML_AS_SYSTEM_MEMORY,
542 .base_addr.width = 32,
543 .base_addr.offset = 0,
544 .base_addr.size = 3,
545 .base_addr.addr = vms->memmap[VIRT_UART0].base,
546 .interrupt_type = (1 << 3),/* Bit[3] ARMH GIC interrupt*/
547 .pc_interrupt = 0, /* IRQ */
548 .interrupt = (vms->irqmap[VIRT_UART0] + ARM_SPI_BASE),
549 .baud_rate = 3, /* 9600 */
550 .parity = 0, /* No Parity */
551 .stop_bits = 1, /* 1 Stop bit */
552 .flow_control = 1 << 1, /* RTS/CTS hardware flow control */
553 .terminal_type = 0, /* VT100 */
554 .language = 0, /* Language */
555 .pci_device_id = 0xffff, /* not a PCI device*/
556 .pci_vendor_id = 0xffff, /* not a PCI device*/
557 .pci_bus = 0,
558 .pci_device = 0,
559 .pci_function = 0,
560 .pci_flags = 0,
561 .pci_segment = 0,
562 };
563 /*
564 * Passing NULL as the SPCR Table for Revision 2 doesn't support
565 * NameSpaceString.
566 */
567 build_spcr(table_data, linker, &serial, 2, vms->oem_id, vms->oem_table_id,
568 NULL);
569 }
570
571 /*
572 * ACPI spec, Revision 5.1
573 * 5.2.16 System Resource Affinity Table (SRAT)
574 */
575 static void
build_srat(GArray * table_data,BIOSLinker * linker,VirtMachineState * vms)576 build_srat(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
577 {
578 int i;
579 uint64_t mem_base;
580 MachineClass *mc = MACHINE_GET_CLASS(vms);
581 MachineState *ms = MACHINE(vms);
582 const CPUArchIdList *cpu_list = mc->possible_cpu_arch_ids(ms);
583 AcpiTable table = { .sig = "SRAT", .rev = 3, .oem_id = vms->oem_id,
584 .oem_table_id = vms->oem_table_id };
585
586 acpi_table_begin(&table, table_data);
587 build_append_int_noprefix(table_data, 1, 4); /* Reserved */
588 build_append_int_noprefix(table_data, 0, 8); /* Reserved */
589
590 for (i = 0; i < cpu_list->len; ++i) {
591 uint32_t nodeid = cpu_list->cpus[i].props.node_id;
592 /*
593 * 5.2.16.4 GICC Affinity Structure
594 */
595 build_append_int_noprefix(table_data, 3, 1); /* Type */
596 build_append_int_noprefix(table_data, 18, 1); /* Length */
597 build_append_int_noprefix(table_data, nodeid, 4); /* Proximity Domain */
598 build_append_int_noprefix(table_data, i, 4); /* ACPI Processor UID */
599 /* Flags, Table 5-76 */
600 build_append_int_noprefix(table_data, 1 /* Enabled */, 4);
601 build_append_int_noprefix(table_data, 0, 4); /* Clock Domain */
602 }
603
604 mem_base = vms->memmap[VIRT_MEM].base;
605 for (i = 0; i < ms->numa_state->num_nodes; ++i) {
606 if (ms->numa_state->nodes[i].node_mem > 0) {
607 build_srat_memory(table_data, mem_base,
608 ms->numa_state->nodes[i].node_mem, i,
609 MEM_AFFINITY_ENABLED);
610 mem_base += ms->numa_state->nodes[i].node_mem;
611 }
612 }
613
614 build_srat_generic_affinity_structures(table_data);
615
616 if (ms->nvdimms_state->is_enabled) {
617 nvdimm_build_srat(table_data);
618 }
619
620 if (ms->device_memory) {
621 build_srat_memory(table_data, ms->device_memory->base,
622 memory_region_size(&ms->device_memory->mr),
623 ms->numa_state->num_nodes - 1,
624 MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED);
625 }
626
627 acpi_table_end(linker, &table);
628 }
629
630 /*
631 * ACPI spec, Revision 6.5
632 * 5.2.25 Generic Timer Description Table (GTDT)
633 */
634 static void
build_gtdt(GArray * table_data,BIOSLinker * linker,VirtMachineState * vms)635 build_gtdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
636 {
637 /*
638 * Table 5-117 Flag Definitions
639 * set only "Timer interrupt Mode" and assume "Timer Interrupt
640 * polarity" bit as '0: Interrupt is Active high'
641 */
642 const uint32_t irqflags = 0; /* Interrupt is Level triggered */
643 AcpiTable table = { .sig = "GTDT", .rev = 3, .oem_id = vms->oem_id,
644 .oem_table_id = vms->oem_table_id };
645
646 acpi_table_begin(&table, table_data);
647
648 /* CntControlBase Physical Address */
649 build_append_int_noprefix(table_data, 0xFFFFFFFFFFFFFFFF, 8);
650 build_append_int_noprefix(table_data, 0, 4); /* Reserved */
651 /*
652 * FIXME: clarify comment:
653 * The interrupt values are the same with the device tree when adding 16
654 */
655 /* Secure EL1 timer GSIV */
656 build_append_int_noprefix(table_data, ARCH_TIMER_S_EL1_IRQ, 4);
657 /* Secure EL1 timer Flags */
658 build_append_int_noprefix(table_data, irqflags, 4);
659 /* Non-Secure EL1 timer GSIV */
660 build_append_int_noprefix(table_data, ARCH_TIMER_NS_EL1_IRQ, 4);
661 /* Non-Secure EL1 timer Flags */
662 build_append_int_noprefix(table_data, irqflags |
663 1UL << 2, /* Always-on Capability */
664 4);
665 /* Virtual timer GSIV */
666 build_append_int_noprefix(table_data, ARCH_TIMER_VIRT_IRQ, 4);
667 /* Virtual Timer Flags */
668 build_append_int_noprefix(table_data, irqflags, 4);
669 /* Non-Secure EL2 timer GSIV */
670 build_append_int_noprefix(table_data, ARCH_TIMER_NS_EL2_IRQ, 4);
671 /* Non-Secure EL2 timer Flags */
672 build_append_int_noprefix(table_data, irqflags, 4);
673 /* CntReadBase Physical address */
674 build_append_int_noprefix(table_data, 0xFFFFFFFFFFFFFFFF, 8);
675 /* Platform Timer Count */
676 build_append_int_noprefix(table_data, 0, 4);
677 /* Platform Timer Offset */
678 build_append_int_noprefix(table_data, 0, 4);
679 if (vms->ns_el2_virt_timer_irq) {
680 /* Virtual EL2 Timer GSIV */
681 build_append_int_noprefix(table_data, ARCH_TIMER_NS_EL2_VIRT_IRQ, 4);
682 /* Virtual EL2 Timer Flags */
683 build_append_int_noprefix(table_data, irqflags, 4);
684 } else {
685 build_append_int_noprefix(table_data, 0, 4);
686 build_append_int_noprefix(table_data, 0, 4);
687 }
688 acpi_table_end(linker, &table);
689 }
690
691 /* Debug Port Table 2 (DBG2) */
692 static void
build_dbg2(GArray * table_data,BIOSLinker * linker,VirtMachineState * vms)693 build_dbg2(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
694 {
695 AcpiTable table = { .sig = "DBG2", .rev = 0, .oem_id = vms->oem_id,
696 .oem_table_id = vms->oem_table_id };
697 int dbg2devicelength;
698 const char name[] = "COM0";
699 const int namespace_length = sizeof(name);
700
701 acpi_table_begin(&table, table_data);
702
703 dbg2devicelength = 22 + /* BaseAddressRegister[] offset */
704 12 + /* BaseAddressRegister[] */
705 4 + /* AddressSize[] */
706 namespace_length /* NamespaceString[] */;
707
708 /* OffsetDbgDeviceInfo */
709 build_append_int_noprefix(table_data, 44, 4);
710 /* NumberDbgDeviceInfo */
711 build_append_int_noprefix(table_data, 1, 4);
712
713 /* Table 2. Debug Device Information structure format */
714 build_append_int_noprefix(table_data, 0, 1); /* Revision */
715 build_append_int_noprefix(table_data, dbg2devicelength, 2); /* Length */
716 /* NumberofGenericAddressRegisters */
717 build_append_int_noprefix(table_data, 1, 1);
718 /* NameSpaceStringLength */
719 build_append_int_noprefix(table_data, namespace_length, 2);
720 build_append_int_noprefix(table_data, 38, 2); /* NameSpaceStringOffset */
721 build_append_int_noprefix(table_data, 0, 2); /* OemDataLength */
722 /* OemDataOffset (0 means no OEM data) */
723 build_append_int_noprefix(table_data, 0, 2);
724
725 /* Port Type */
726 build_append_int_noprefix(table_data, 0x8000 /* Serial */, 2);
727 /* Port Subtype */
728 build_append_int_noprefix(table_data, 0x3 /* ARM PL011 UART */, 2);
729 build_append_int_noprefix(table_data, 0, 2); /* Reserved */
730 /* BaseAddressRegisterOffset */
731 build_append_int_noprefix(table_data, 22, 2);
732 /* AddressSizeOffset */
733 build_append_int_noprefix(table_data, 34, 2);
734
735 /* BaseAddressRegister[] */
736 build_append_gas(table_data, AML_AS_SYSTEM_MEMORY, 32, 0, 3,
737 vms->memmap[VIRT_UART0].base);
738
739 /* AddressSize[] */
740 build_append_int_noprefix(table_data,
741 vms->memmap[VIRT_UART0].size, 4);
742
743 /* NamespaceString[] */
744 g_array_append_vals(table_data, name, namespace_length);
745
746 acpi_table_end(linker, &table);
747 };
748
749 /*
750 * ACPI spec, Revision 6.0 Errata A
751 * 5.2.12 Multiple APIC Description Table (MADT)
752 */
build_append_gicr(GArray * table_data,uint64_t base,uint32_t size)753 static void build_append_gicr(GArray *table_data, uint64_t base, uint32_t size)
754 {
755 build_append_int_noprefix(table_data, 0xE, 1); /* Type */
756 build_append_int_noprefix(table_data, 16, 1); /* Length */
757 build_append_int_noprefix(table_data, 0, 2); /* Reserved */
758 /* Discovery Range Base Address */
759 build_append_int_noprefix(table_data, base, 8);
760 build_append_int_noprefix(table_data, size, 4); /* Discovery Range Length */
761 }
762
763 static void
build_madt(GArray * table_data,BIOSLinker * linker,VirtMachineState * vms)764 build_madt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
765 {
766 int i;
767 const MemMapEntry *memmap = vms->memmap;
768 AcpiTable table = { .sig = "APIC", .rev = 4, .oem_id = vms->oem_id,
769 .oem_table_id = vms->oem_table_id };
770
771 acpi_table_begin(&table, table_data);
772 /* Local Interrupt Controller Address */
773 build_append_int_noprefix(table_data, 0, 4);
774 build_append_int_noprefix(table_data, 0, 4); /* Flags */
775
776 /* 5.2.12.15 GIC Distributor Structure */
777 build_append_int_noprefix(table_data, 0xC, 1); /* Type */
778 build_append_int_noprefix(table_data, 24, 1); /* Length */
779 build_append_int_noprefix(table_data, 0, 2); /* Reserved */
780 build_append_int_noprefix(table_data, 0, 4); /* GIC ID */
781 /* Physical Base Address */
782 build_append_int_noprefix(table_data, memmap[VIRT_GIC_DIST].base, 8);
783 build_append_int_noprefix(table_data, 0, 4); /* System Vector Base */
784 /* GIC version */
785 build_append_int_noprefix(table_data, vms->gic_version, 1);
786 build_append_int_noprefix(table_data, 0, 3); /* Reserved */
787
788 for (i = 0; i < MACHINE(vms)->smp.cpus; i++) {
789 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(i));
790 uint64_t physical_base_address = 0, gich = 0, gicv = 0;
791 uint32_t vgic_interrupt = vms->virt ? ARCH_GIC_MAINT_IRQ : 0;
792 uint32_t pmu_interrupt = arm_feature(&armcpu->env, ARM_FEATURE_PMU) ?
793 VIRTUAL_PMU_IRQ : 0;
794
795 if (vms->gic_version == VIRT_GIC_VERSION_2) {
796 physical_base_address = memmap[VIRT_GIC_CPU].base;
797 gicv = memmap[VIRT_GIC_VCPU].base;
798 gich = memmap[VIRT_GIC_HYP].base;
799 }
800
801 /* 5.2.12.14 GIC Structure */
802 build_append_int_noprefix(table_data, 0xB, 1); /* Type */
803 build_append_int_noprefix(table_data, 80, 1); /* Length */
804 build_append_int_noprefix(table_data, 0, 2); /* Reserved */
805 build_append_int_noprefix(table_data, i, 4); /* GIC ID */
806 build_append_int_noprefix(table_data, i, 4); /* ACPI Processor UID */
807 /* Flags */
808 build_append_int_noprefix(table_data, 1, 4); /* Enabled */
809 /* Parking Protocol Version */
810 build_append_int_noprefix(table_data, 0, 4);
811 /* Performance Interrupt GSIV */
812 build_append_int_noprefix(table_data, pmu_interrupt, 4);
813 build_append_int_noprefix(table_data, 0, 8); /* Parked Address */
814 /* Physical Base Address */
815 build_append_int_noprefix(table_data, physical_base_address, 8);
816 build_append_int_noprefix(table_data, gicv, 8); /* GICV */
817 build_append_int_noprefix(table_data, gich, 8); /* GICH */
818 /* VGIC Maintenance interrupt */
819 build_append_int_noprefix(table_data, vgic_interrupt, 4);
820 build_append_int_noprefix(table_data, 0, 8); /* GICR Base Address*/
821 /* MPIDR */
822 build_append_int_noprefix(table_data, arm_cpu_mp_affinity(armcpu), 8);
823 /* Processor Power Efficiency Class */
824 build_append_int_noprefix(table_data, 0, 1);
825 /* Reserved */
826 build_append_int_noprefix(table_data, 0, 3);
827 }
828
829 if (vms->gic_version != VIRT_GIC_VERSION_2) {
830 build_append_gicr(table_data, memmap[VIRT_GIC_REDIST].base,
831 memmap[VIRT_GIC_REDIST].size);
832 if (virt_gicv3_redist_region_count(vms) == 2) {
833 build_append_gicr(table_data, memmap[VIRT_HIGH_GIC_REDIST2].base,
834 memmap[VIRT_HIGH_GIC_REDIST2].size);
835 }
836
837 if (vms->its) {
838 /*
839 * ACPI spec, Revision 6.0 Errata A
840 * (original 6.0 definition has invalid Length)
841 * 5.2.12.18 GIC ITS Structure
842 */
843 build_append_int_noprefix(table_data, 0xF, 1); /* Type */
844 build_append_int_noprefix(table_data, 20, 1); /* Length */
845 build_append_int_noprefix(table_data, 0, 2); /* Reserved */
846 build_append_int_noprefix(table_data, 0, 4); /* GIC ITS ID */
847 /* Physical Base Address */
848 build_append_int_noprefix(table_data, memmap[VIRT_GIC_ITS].base, 8);
849 build_append_int_noprefix(table_data, 0, 4); /* Reserved */
850 }
851 } else {
852 const uint16_t spi_base = vms->irqmap[VIRT_GIC_V2M] + ARM_SPI_BASE;
853
854 /* 5.2.12.16 GIC MSI Frame Structure */
855 build_append_int_noprefix(table_data, 0xD, 1); /* Type */
856 build_append_int_noprefix(table_data, 24, 1); /* Length */
857 build_append_int_noprefix(table_data, 0, 2); /* Reserved */
858 build_append_int_noprefix(table_data, 0, 4); /* GIC MSI Frame ID */
859 /* Physical Base Address */
860 build_append_int_noprefix(table_data, memmap[VIRT_GIC_V2M].base, 8);
861 build_append_int_noprefix(table_data, 1, 4); /* Flags */
862 /* SPI Count */
863 build_append_int_noprefix(table_data, NUM_GICV2M_SPIS, 2);
864 build_append_int_noprefix(table_data, spi_base, 2); /* SPI Base */
865 }
866 acpi_table_end(linker, &table);
867 }
868
869 /* FADT */
build_fadt_rev6(GArray * table_data,BIOSLinker * linker,VirtMachineState * vms,unsigned dsdt_tbl_offset)870 static void build_fadt_rev6(GArray *table_data, BIOSLinker *linker,
871 VirtMachineState *vms, unsigned dsdt_tbl_offset)
872 {
873 /* ACPI v6.3 */
874 AcpiFadtData fadt = {
875 .rev = 6,
876 .minor_ver = 3,
877 .flags = 1 << ACPI_FADT_F_HW_REDUCED_ACPI,
878 .xdsdt_tbl_offset = &dsdt_tbl_offset,
879 };
880
881 switch (vms->psci_conduit) {
882 case QEMU_PSCI_CONDUIT_DISABLED:
883 fadt.arm_boot_arch = 0;
884 break;
885 case QEMU_PSCI_CONDUIT_HVC:
886 fadt.arm_boot_arch = ACPI_FADT_ARM_PSCI_COMPLIANT |
887 ACPI_FADT_ARM_PSCI_USE_HVC;
888 break;
889 case QEMU_PSCI_CONDUIT_SMC:
890 fadt.arm_boot_arch = ACPI_FADT_ARM_PSCI_COMPLIANT;
891 break;
892 default:
893 g_assert_not_reached();
894 }
895
896 build_fadt(table_data, linker, &fadt, vms->oem_id, vms->oem_table_id);
897 }
898
899 /* DSDT */
900 static void
build_dsdt(GArray * table_data,BIOSLinker * linker,VirtMachineState * vms)901 build_dsdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
902 {
903 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
904 Aml *scope, *dsdt;
905 MachineState *ms = MACHINE(vms);
906 const MemMapEntry *memmap = vms->memmap;
907 const int *irqmap = vms->irqmap;
908 AcpiTable table = { .sig = "DSDT", .rev = 2, .oem_id = vms->oem_id,
909 .oem_table_id = vms->oem_table_id };
910 Aml *pci0_scope;
911
912 acpi_table_begin(&table, table_data);
913 dsdt = init_aml_allocator();
914
915 /* When booting the VM with UEFI, UEFI takes ownership of the RTC hardware.
916 * While UEFI can use libfdt to disable the RTC device node in the DTB that
917 * it passes to the OS, it cannot modify AML. Therefore, we won't generate
918 * the RTC ACPI device at all when using UEFI.
919 */
920 scope = aml_scope("\\_SB");
921 acpi_dsdt_add_cpus(scope, vms);
922 acpi_dsdt_add_uart(scope, &memmap[VIRT_UART0],
923 (irqmap[VIRT_UART0] + ARM_SPI_BASE), 0);
924 if (vms->second_ns_uart_present) {
925 acpi_dsdt_add_uart(scope, &memmap[VIRT_UART1],
926 (irqmap[VIRT_UART1] + ARM_SPI_BASE), 1);
927 }
928 if (vmc->acpi_expose_flash) {
929 acpi_dsdt_add_flash(scope, &memmap[VIRT_FLASH]);
930 }
931 fw_cfg_acpi_dsdt_add(scope, &memmap[VIRT_FW_CFG]);
932 virtio_acpi_dsdt_add(scope, memmap[VIRT_MMIO].base, memmap[VIRT_MMIO].size,
933 (irqmap[VIRT_MMIO] + ARM_SPI_BASE),
934 0, NUM_VIRTIO_TRANSPORTS);
935 acpi_dsdt_add_pci(scope, memmap, irqmap[VIRT_PCIE] + ARM_SPI_BASE, vms);
936 if (vms->acpi_dev) {
937 build_ged_aml(scope, "\\_SB."GED_DEVICE,
938 HOTPLUG_HANDLER(vms->acpi_dev),
939 irqmap[VIRT_ACPI_GED] + ARM_SPI_BASE, AML_SYSTEM_MEMORY,
940 memmap[VIRT_ACPI_GED].base);
941 } else {
942 acpi_dsdt_add_gpio(scope, &memmap[VIRT_GPIO],
943 (irqmap[VIRT_GPIO] + ARM_SPI_BASE));
944 }
945
946 if (vms->acpi_dev) {
947 uint32_t event = object_property_get_uint(OBJECT(vms->acpi_dev),
948 "ged-event", &error_abort);
949
950 if (event & ACPI_GED_MEM_HOTPLUG_EVT) {
951 build_memory_hotplug_aml(scope, ms->ram_slots, "\\_SB", NULL,
952 AML_SYSTEM_MEMORY,
953 memmap[VIRT_PCDIMM_ACPI].base);
954 }
955 }
956
957 acpi_dsdt_add_power_button(scope);
958 #ifdef CONFIG_TPM
959 acpi_dsdt_add_tpm(scope, vms);
960 #endif
961
962 aml_append(dsdt, scope);
963
964 pci0_scope = aml_scope("\\_SB.PCI0");
965
966 aml_append(pci0_scope, build_pci_bridge_edsm());
967 build_append_pci_bus_devices(pci0_scope, vms->bus);
968 if (object_property_find(OBJECT(vms->bus), ACPI_PCIHP_PROP_BSEL)) {
969 build_append_pcihp_slots(pci0_scope, vms->bus);
970 }
971
972 if (vms->acpi_dev) {
973 bool acpi_pcihp;
974
975 acpi_pcihp = object_property_get_bool(OBJECT(vms->acpi_dev),
976 ACPI_PM_PROP_ACPI_PCIHP_BRIDGE,
977 NULL);
978
979 if (acpi_pcihp) {
980 build_acpi_pci_hotplug(dsdt, AML_SYSTEM_MEMORY,
981 memmap[VIRT_ACPI_PCIHP].base);
982 build_append_pcihp_resources(pci0_scope,
983 memmap[VIRT_ACPI_PCIHP].base,
984 memmap[VIRT_ACPI_PCIHP].size);
985
986 build_append_notification_callback(pci0_scope, vms->bus);
987 }
988 }
989 aml_append(dsdt, pci0_scope);
990
991 /* copy AML table into ACPI tables blob */
992 g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len);
993
994 acpi_table_end(linker, &table);
995 free_aml_allocator();
996 }
997
998 typedef
999 struct AcpiBuildState {
1000 /* Copy of table in RAM (for patching). */
1001 MemoryRegion *table_mr;
1002 MemoryRegion *rsdp_mr;
1003 MemoryRegion *linker_mr;
1004 /* Is table patched? */
1005 bool patched;
1006 } AcpiBuildState;
1007
acpi_align_size(GArray * blob,unsigned align)1008 static void acpi_align_size(GArray *blob, unsigned align)
1009 {
1010 /*
1011 * Align size to multiple of given size. This reduces the chance
1012 * we need to change size in the future (breaking cross version migration).
1013 */
1014 g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align));
1015 }
1016
1017 static
virt_acpi_build(VirtMachineState * vms,AcpiBuildTables * tables)1018 void virt_acpi_build(VirtMachineState *vms, AcpiBuildTables *tables)
1019 {
1020 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
1021 GArray *table_offsets;
1022 unsigned dsdt, xsdt;
1023 GArray *tables_blob = tables->table_data;
1024 MachineState *ms = MACHINE(vms);
1025
1026 table_offsets = g_array_new(false, true /* clear */,
1027 sizeof(uint32_t));
1028
1029 bios_linker_loader_alloc(tables->linker,
1030 ACPI_BUILD_TABLE_FILE, tables_blob,
1031 64, false /* high memory */);
1032
1033 /* DSDT is pointed to by FADT */
1034 dsdt = tables_blob->len;
1035 build_dsdt(tables_blob, tables->linker, vms);
1036
1037 /* FADT MADT PPTT GTDT MCFG SPCR DBG2 pointed to by RSDT */
1038 acpi_add_table(table_offsets, tables_blob);
1039 build_fadt_rev6(tables_blob, tables->linker, vms, dsdt);
1040
1041 acpi_add_table(table_offsets, tables_blob);
1042 build_madt(tables_blob, tables->linker, vms);
1043
1044 if (!vmc->no_cpu_topology) {
1045 acpi_add_table(table_offsets, tables_blob);
1046 build_pptt(tables_blob, tables->linker, ms,
1047 vms->oem_id, vms->oem_table_id);
1048 }
1049
1050 acpi_add_table(table_offsets, tables_blob);
1051 build_gtdt(tables_blob, tables->linker, vms);
1052
1053 acpi_add_table(table_offsets, tables_blob);
1054 {
1055 AcpiMcfgInfo mcfg = {
1056 .base = vms->memmap[VIRT_ECAM_ID(vms->highmem_ecam)].base,
1057 .size = vms->memmap[VIRT_ECAM_ID(vms->highmem_ecam)].size,
1058 };
1059 build_mcfg(tables_blob, tables->linker, &mcfg, vms->oem_id,
1060 vms->oem_table_id);
1061 }
1062
1063 acpi_add_table(table_offsets, tables_blob);
1064
1065 if (ms->acpi_spcr_enabled) {
1066 spcr_setup(tables_blob, tables->linker, vms);
1067 }
1068
1069 acpi_add_table(table_offsets, tables_blob);
1070 build_dbg2(tables_blob, tables->linker, vms);
1071
1072 if (vms->ras) {
1073 acpi_add_table(table_offsets, tables_blob);
1074 acpi_build_hest(tables_blob, tables->hardware_errors, tables->linker,
1075 vms->oem_id, vms->oem_table_id);
1076 }
1077
1078 if (ms->numa_state->num_nodes > 0) {
1079 acpi_add_table(table_offsets, tables_blob);
1080 build_srat(tables_blob, tables->linker, vms);
1081 if (ms->numa_state->have_numa_distance) {
1082 acpi_add_table(table_offsets, tables_blob);
1083 build_slit(tables_blob, tables->linker, ms, vms->oem_id,
1084 vms->oem_table_id);
1085 }
1086
1087 if (ms->numa_state->hmat_enabled) {
1088 acpi_add_table(table_offsets, tables_blob);
1089 build_hmat(tables_blob, tables->linker, ms->numa_state,
1090 vms->oem_id, vms->oem_table_id);
1091 }
1092 }
1093
1094 if (vms->cxl_devices_state.is_enabled) {
1095 cxl_build_cedt(table_offsets, tables_blob, tables->linker,
1096 vms->oem_id, vms->oem_table_id, &vms->cxl_devices_state);
1097 }
1098
1099 if (ms->nvdimms_state->is_enabled) {
1100 nvdimm_build_acpi(table_offsets, tables_blob, tables->linker,
1101 ms->nvdimms_state, ms->ram_slots, vms->oem_id,
1102 vms->oem_table_id);
1103 }
1104
1105 acpi_add_table(table_offsets, tables_blob);
1106 build_iort(tables_blob, tables->linker, vms);
1107
1108 #ifdef CONFIG_TPM
1109 if (tpm_get_version(tpm_find()) == TPM_VERSION_2_0) {
1110 acpi_add_table(table_offsets, tables_blob);
1111 build_tpm2(tables_blob, tables->linker, tables->tcpalog, vms->oem_id,
1112 vms->oem_table_id);
1113 }
1114 #endif
1115
1116 if (vms->iommu == VIRT_IOMMU_VIRTIO) {
1117 acpi_add_table(table_offsets, tables_blob);
1118 build_viot(ms, tables_blob, tables->linker, vms->virtio_iommu_bdf,
1119 vms->oem_id, vms->oem_table_id);
1120 }
1121
1122 /* XSDT is pointed to by RSDP */
1123 xsdt = tables_blob->len;
1124 build_xsdt(tables_blob, tables->linker, table_offsets, vms->oem_id,
1125 vms->oem_table_id);
1126
1127 /* RSDP is in FSEG memory, so allocate it separately */
1128 {
1129 AcpiRsdpData rsdp_data = {
1130 .revision = 2,
1131 .oem_id = vms->oem_id,
1132 .xsdt_tbl_offset = &xsdt,
1133 .rsdt_tbl_offset = NULL,
1134 };
1135 build_rsdp(tables->rsdp, tables->linker, &rsdp_data);
1136 }
1137
1138 /*
1139 * The align size is 128, warn if 64k is not enough therefore
1140 * the align size could be resized.
1141 */
1142 if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) {
1143 warn_report("ACPI table size %u exceeds %d bytes,"
1144 " migration may not work",
1145 tables_blob->len, ACPI_BUILD_TABLE_SIZE / 2);
1146 error_printf("Try removing CPUs, NUMA nodes, memory slots"
1147 " or PCI bridges.\n");
1148 }
1149 acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE);
1150
1151
1152 /* Cleanup memory that's no longer used. */
1153 g_array_free(table_offsets, true);
1154 }
1155
acpi_ram_update(MemoryRegion * mr,GArray * data)1156 static void acpi_ram_update(MemoryRegion *mr, GArray *data)
1157 {
1158 uint32_t size = acpi_data_len(data);
1159
1160 /* Make sure RAM size is correct - in case it got changed
1161 * e.g. by migration */
1162 memory_region_ram_resize(mr, size, &error_abort);
1163
1164 memcpy(memory_region_get_ram_ptr(mr), data->data, size);
1165 memory_region_set_dirty(mr, 0, size);
1166 }
1167
virt_acpi_build_update(void * build_opaque)1168 static void virt_acpi_build_update(void *build_opaque)
1169 {
1170 AcpiBuildState *build_state = build_opaque;
1171 AcpiBuildTables tables;
1172
1173 /* No state to update or already patched? Nothing to do. */
1174 if (!build_state || build_state->patched) {
1175 return;
1176 }
1177 build_state->patched = true;
1178
1179 acpi_build_tables_init(&tables);
1180
1181 virt_acpi_build(VIRT_MACHINE(qdev_get_machine()), &tables);
1182
1183 acpi_ram_update(build_state->table_mr, tables.table_data);
1184 acpi_ram_update(build_state->rsdp_mr, tables.rsdp);
1185 acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob);
1186
1187 acpi_build_tables_cleanup(&tables, true);
1188 }
1189
virt_acpi_build_reset(void * build_opaque)1190 static void virt_acpi_build_reset(void *build_opaque)
1191 {
1192 AcpiBuildState *build_state = build_opaque;
1193 build_state->patched = false;
1194 }
1195
1196 static const VMStateDescription vmstate_virt_acpi_build = {
1197 .name = "virt_acpi_build",
1198 .version_id = 1,
1199 .minimum_version_id = 1,
1200 .fields = (const VMStateField[]) {
1201 VMSTATE_BOOL(patched, AcpiBuildState),
1202 VMSTATE_END_OF_LIST()
1203 },
1204 };
1205
virt_acpi_setup(VirtMachineState * vms)1206 void virt_acpi_setup(VirtMachineState *vms)
1207 {
1208 AcpiBuildTables tables;
1209 AcpiBuildState *build_state;
1210 AcpiGedState *acpi_ged_state;
1211
1212 if (!vms->fw_cfg) {
1213 trace_virt_acpi_setup();
1214 return;
1215 }
1216
1217 if (!virt_is_acpi_enabled(vms)) {
1218 trace_virt_acpi_setup();
1219 return;
1220 }
1221
1222 build_state = g_malloc0(sizeof *build_state);
1223
1224 acpi_build_tables_init(&tables);
1225 virt_acpi_build(vms, &tables);
1226
1227 /* Now expose it all to Guest */
1228 build_state->table_mr = acpi_add_rom_blob(virt_acpi_build_update,
1229 build_state, tables.table_data,
1230 ACPI_BUILD_TABLE_FILE);
1231 assert(build_state->table_mr != NULL);
1232
1233 build_state->linker_mr = acpi_add_rom_blob(virt_acpi_build_update,
1234 build_state,
1235 tables.linker->cmd_blob,
1236 ACPI_BUILD_LOADER_FILE);
1237
1238 fw_cfg_add_file(vms->fw_cfg, ACPI_BUILD_TPMLOG_FILE, tables.tcpalog->data,
1239 acpi_data_len(tables.tcpalog));
1240
1241 if (vms->ras) {
1242 assert(vms->acpi_dev);
1243 acpi_ged_state = ACPI_GED(vms->acpi_dev);
1244 acpi_ghes_add_fw_cfg(&acpi_ged_state->ghes_state,
1245 vms->fw_cfg, tables.hardware_errors);
1246 }
1247
1248 build_state->rsdp_mr = acpi_add_rom_blob(virt_acpi_build_update,
1249 build_state, tables.rsdp,
1250 ACPI_BUILD_RSDP_FILE);
1251
1252 qemu_register_reset(virt_acpi_build_reset, build_state);
1253 virt_acpi_build_reset(build_state);
1254 vmstate_register(NULL, 0, &vmstate_virt_acpi_build, build_state);
1255
1256 /* Cleanup tables but don't free the memory: we track it
1257 * in build_state.
1258 */
1259 acpi_build_tables_cleanup(&tables, false);
1260 }
1261