1 /*
2 * NeXT Cube System Driver
3 *
4 * Copyright (c) 2011 Bryce Lanham
5 * Copyright (c) 2024 Mark Cave-Ayland
6 *
7 * This code is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published
9 * by the Free Software Foundation; either version 2 of the License,
10 * or (at your option) any later version.
11 */
12
13 #include "qemu/osdep.h"
14 #include "exec/hwaddr.h"
15 #include "system/system.h"
16 #include "system/qtest.h"
17 #include "hw/irq.h"
18 #include "hw/m68k/next-cube.h"
19 #include "hw/boards.h"
20 #include "hw/loader.h"
21 #include "hw/scsi/esp.h"
22 #include "hw/sysbus.h"
23 #include "qom/object.h"
24 #include "hw/char/escc.h" /* ZILOG 8530 Serial Emulation */
25 #include "hw/block/fdc.h"
26 #include "hw/misc/empty_slot.h"
27 #include "hw/qdev-properties.h"
28 #include "qapi/error.h"
29 #include "qemu/error-report.h"
30 #include "ui/console.h"
31 #include "target/m68k/cpu.h"
32 #include "migration/vmstate.h"
33
34 /* #define DEBUG_NEXT */
35 #ifdef DEBUG_NEXT
36 #define DPRINTF(fmt, ...) \
37 do { printf("NeXT: " fmt , ## __VA_ARGS__); } while (0)
38 #else
39 #define DPRINTF(fmt, ...) do { } while (0)
40 #endif
41
42 #define ENTRY 0x0100001e
43 #define RAM_SIZE 0x4000000
44 #define ROM_FILE "Rev_2.5_v66.bin"
45
46
47 #define TYPE_NEXT_RTC "next-rtc"
48 OBJECT_DECLARE_SIMPLE_TYPE(NeXTRTC, NEXT_RTC)
49
50 struct NeXTRTC {
51 SysBusDevice parent_obj;
52
53 int8_t phase;
54 uint8_t ram[32];
55 uint8_t command;
56 uint8_t value;
57 uint8_t status;
58 uint8_t control;
59 uint8_t retval;
60
61 qemu_irq data_out_irq;
62 qemu_irq power_irq;
63 };
64
65 #define TYPE_NEXT_SCSI "next-scsi"
66 OBJECT_DECLARE_SIMPLE_TYPE(NeXTSCSI, NEXT_SCSI)
67
68 /* NeXT SCSI Controller */
69 struct NeXTSCSI {
70 SysBusDevice parent_obj;
71
72 MemoryRegion scsi_mem;
73
74 SysBusESPState sysbus_esp;
75
76 MemoryRegion scsi_csr_mem;
77 uint8_t scsi_csr_1;
78 uint8_t scsi_csr_2;
79 };
80
81 #define TYPE_NEXT_PC "next-pc"
82 OBJECT_DECLARE_SIMPLE_TYPE(NeXTPC, NEXT_PC)
83
84 /* NeXT Peripheral Controller */
85 struct NeXTPC {
86 SysBusDevice parent_obj;
87
88 M68kCPU *cpu;
89
90 MemoryRegion floppy_mem;
91 MemoryRegion timer_mem;
92 MemoryRegion dummyen_mem;
93 MemoryRegion mmiomem;
94 MemoryRegion scrmem;
95
96 uint32_t scr1;
97 uint32_t scr2;
98 uint32_t old_scr2;
99 uint32_t int_mask;
100 uint32_t int_status;
101 uint32_t led;
102
103 NeXTSCSI next_scsi;
104
105 qemu_irq scsi_reset;
106 qemu_irq scsi_dma;
107
108 ESCCState escc;
109
110 NeXTRTC rtc;
111 qemu_irq rtc_data_irq;
112 qemu_irq rtc_cmd_reset_irq;
113 };
114
115 typedef struct next_dma {
116 uint32_t csr;
117
118 uint32_t saved_next;
119 uint32_t saved_limit;
120 uint32_t saved_start;
121 uint32_t saved_stop;
122
123 uint32_t next;
124 uint32_t limit;
125 uint32_t start;
126 uint32_t stop;
127
128 uint32_t next_initbuf;
129 uint32_t size;
130 } next_dma;
131
132 #define TYPE_NEXT_MACHINE MACHINE_TYPE_NAME("next-cube")
133 OBJECT_DECLARE_SIMPLE_TYPE(NeXTState, NEXT_MACHINE)
134
135 struct NeXTState {
136 MachineState parent;
137
138 MemoryRegion rom;
139 MemoryRegion rom2;
140 MemoryRegion dmamem;
141 MemoryRegion bmapm1;
142 MemoryRegion bmapm2;
143
144 next_dma dma[10];
145 };
146
147 /* Thanks to NeXT forums for this */
148 /*
149 static const uint8_t rtc_ram3[32] = {
150 0x94, 0x0f, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00,
151 0x00, 0x00, 0xfb, 0x6d, 0x00, 0x00, 0x7B, 0x00,
152 0x00, 0x00, 0x65, 0x6e, 0x00, 0x00, 0x00, 0x00,
153 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x13
154 };
155 */
156 static const uint8_t rtc_ram2[32] = {
157 0x94, 0x0f, 0x40, 0x03, 0x00, 0x00, 0x00, 0x00,
158 0x00, 0x00, 0xfb, 0x6d, 0x00, 0x00, 0x4b, 0x00,
159 0x41, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00,
160 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x84, 0x7e,
161 };
162
163 #define SCR2_RTCLK 0x2
164 #define SCR2_RTDATA 0x4
165 #define SCR2_TOBCD(x) (((x / 10) << 4) + (x % 10))
166
next_scr2_led_update(NeXTPC * s)167 static void next_scr2_led_update(NeXTPC *s)
168 {
169 if (s->scr2 & 0x1) {
170 DPRINTF("fault!\n");
171 s->led++;
172 if (s->led == 10) {
173 DPRINTF("LED flashing, possible fault!\n");
174 s->led = 0;
175 }
176 }
177 }
178
next_scr2_rtc_update(NeXTPC * s)179 static void next_scr2_rtc_update(NeXTPC *s)
180 {
181 uint8_t old_scr2_rtc, scr2_rtc;
182
183 old_scr2_rtc = extract32(s->old_scr2, 8, 8);
184 scr2_rtc = extract32(s->scr2, 8, 8);
185
186 if (scr2_rtc & 0x1) {
187 /* DPRINTF("RTC %x phase %i\n", scr2_2, rtc->phase); */
188 /* If we are in going down clock... do something */
189 if (((old_scr2_rtc & SCR2_RTCLK) != (scr2_rtc & SCR2_RTCLK)) &&
190 ((scr2_rtc & SCR2_RTCLK) == 0)) {
191 if (scr2_rtc & SCR2_RTDATA) {
192 qemu_irq_raise(s->rtc_data_irq);
193 } else {
194 qemu_irq_lower(s->rtc_data_irq);
195 }
196 }
197 } else {
198 /* else end or abort */
199 qemu_irq_raise(s->rtc_cmd_reset_irq);
200 }
201 }
202
next_mmio_read(void * opaque,hwaddr addr,unsigned size)203 static uint64_t next_mmio_read(void *opaque, hwaddr addr, unsigned size)
204 {
205 NeXTPC *s = NEXT_PC(opaque);
206 uint64_t val;
207
208 switch (addr) {
209 case 0x2000: /* 0x2007000 */
210 /* DPRINTF("Read INT status: %x\n", s->int_status); */
211 val = s->int_status;
212 break;
213
214 case 0x2800: /* 0x2007800 */
215 DPRINTF("MMIO Read INT mask: %x\n", s->int_mask);
216 val = s->int_mask;
217 break;
218
219 case 0x7000 ... 0x7003: /* 0x200c000 */
220 val = extract32(s->scr1, (4 - (addr - 0x7000) - size) << 3,
221 size << 3);
222 break;
223
224 case 0x8000 ... 0x8003: /* 0x200d000 */
225 val = extract32(s->scr2, (4 - (addr - 0x8000) - size) << 3,
226 size << 3);
227 break;
228
229 default:
230 val = 0;
231 DPRINTF("MMIO Read @ 0x%"HWADDR_PRIx" size %d\n", addr, size);
232 break;
233 }
234
235 return val;
236 }
237
next_mmio_write(void * opaque,hwaddr addr,uint64_t val,unsigned size)238 static void next_mmio_write(void *opaque, hwaddr addr, uint64_t val,
239 unsigned size)
240 {
241 NeXTPC *s = NEXT_PC(opaque);
242
243 switch (addr) {
244 case 0x2000: /* 0x2007000 */
245 DPRINTF("INT Status old: %x new: %x\n", s->int_status,
246 (unsigned int)val);
247 s->int_status = val;
248 break;
249
250 case 0x2800: /* 0x2007800 */
251 DPRINTF("INT Mask old: %x new: %x\n", s->int_mask, (unsigned int)val);
252 s->int_mask = val;
253 break;
254
255 case 0x7000 ... 0x7003: /* 0x200c000 */
256 DPRINTF("SCR1 Write: %x\n", (unsigned int)val);
257 s->scr1 = deposit32(s->scr1, (4 - (addr - 0x7000) - size) << 3,
258 size << 3, val);
259 break;
260
261 case 0x8000 ... 0x8003: /* 0x200d000 */
262 s->scr2 = deposit32(s->scr2, (4 - (addr - 0x8000) - size) << 3,
263 size << 3, val);
264 next_scr2_led_update(s);
265 next_scr2_rtc_update(s);
266 s->old_scr2 = s->scr2;
267 break;
268
269 default:
270 DPRINTF("MMIO Write @ 0x%"HWADDR_PRIx " with 0x%x size %u\n", addr,
271 (unsigned int)val, size);
272 }
273 }
274
275 static const MemoryRegionOps next_mmio_ops = {
276 .read = next_mmio_read,
277 .write = next_mmio_write,
278 .valid.min_access_size = 1,
279 .valid.max_access_size = 4,
280 .endianness = DEVICE_BIG_ENDIAN,
281 };
282
283 #define SCSICSR_ENABLE 0x01
284 #define SCSICSR_RESET 0x02 /* reset scsi dma */
285 #define SCSICSR_FIFOFL 0x04
286 #define SCSICSR_DMADIR 0x08 /* if set, scsi to mem */
287 #define SCSICSR_CPUDMA 0x10 /* if set, dma enabled */
288 #define SCSICSR_INTMASK 0x20 /* if set, interrupt enabled */
289
290 #define NEXTDMA_SCSI(x) (0x10 + x)
291 #define NEXTDMA_FD(x) (0x10 + x)
292 #define NEXTDMA_ENTX(x) (0x110 + x)
293 #define NEXTDMA_ENRX(x) (0x150 + x)
294 #define NEXTDMA_CSR 0x0
295 #define NEXTDMA_NEXT 0x4000
296 #define NEXTDMA_LIMIT 0x4004
297 #define NEXTDMA_START 0x4008
298 #define NEXTDMA_STOP 0x400c
299 #define NEXTDMA_NEXT_INIT 0x4200
300 #define NEXTDMA_SIZE 0x4204
301
next_dma_write(void * opaque,hwaddr addr,uint64_t val,unsigned int size)302 static void next_dma_write(void *opaque, hwaddr addr, uint64_t val,
303 unsigned int size)
304 {
305 NeXTState *next_state = NEXT_MACHINE(opaque);
306
307 switch (addr) {
308 case NEXTDMA_ENRX(NEXTDMA_CSR):
309 if (val & DMA_DEV2M) {
310 next_state->dma[NEXTDMA_ENRX].csr |= DMA_DEV2M;
311 }
312
313 if (val & DMA_SETENABLE) {
314 /* DPRINTF("SCSI DMA ENABLE\n"); */
315 next_state->dma[NEXTDMA_ENRX].csr |= DMA_ENABLE;
316 }
317 if (val & DMA_SETSUPDATE) {
318 next_state->dma[NEXTDMA_ENRX].csr |= DMA_SUPDATE;
319 }
320 if (val & DMA_CLRCOMPLETE) {
321 next_state->dma[NEXTDMA_ENRX].csr &= ~DMA_COMPLETE;
322 }
323
324 if (val & DMA_RESET) {
325 next_state->dma[NEXTDMA_ENRX].csr &= ~(DMA_COMPLETE | DMA_SUPDATE |
326 DMA_ENABLE | DMA_DEV2M);
327 }
328 /* DPRINTF("RXCSR \tWrite: %x\n",value); */
329 break;
330
331 case NEXTDMA_ENRX(NEXTDMA_NEXT_INIT):
332 next_state->dma[NEXTDMA_ENRX].next_initbuf = val;
333 break;
334
335 case NEXTDMA_ENRX(NEXTDMA_NEXT):
336 next_state->dma[NEXTDMA_ENRX].next = val;
337 break;
338
339 case NEXTDMA_ENRX(NEXTDMA_LIMIT):
340 next_state->dma[NEXTDMA_ENRX].limit = val;
341 break;
342
343 case NEXTDMA_SCSI(NEXTDMA_CSR):
344 if (val & DMA_DEV2M) {
345 next_state->dma[NEXTDMA_SCSI].csr |= DMA_DEV2M;
346 }
347 if (val & DMA_SETENABLE) {
348 /* DPRINTF("SCSI DMA ENABLE\n"); */
349 next_state->dma[NEXTDMA_SCSI].csr |= DMA_ENABLE;
350 }
351 if (val & DMA_SETSUPDATE) {
352 next_state->dma[NEXTDMA_SCSI].csr |= DMA_SUPDATE;
353 }
354 if (val & DMA_CLRCOMPLETE) {
355 next_state->dma[NEXTDMA_SCSI].csr &= ~DMA_COMPLETE;
356 }
357
358 if (val & DMA_RESET) {
359 next_state->dma[NEXTDMA_SCSI].csr &= ~(DMA_COMPLETE | DMA_SUPDATE |
360 DMA_ENABLE | DMA_DEV2M);
361 /* DPRINTF("SCSI DMA RESET\n"); */
362 }
363 /* DPRINTF("RXCSR \tWrite: %x\n",value); */
364 break;
365
366 case NEXTDMA_SCSI(NEXTDMA_NEXT):
367 next_state->dma[NEXTDMA_SCSI].next = val;
368 break;
369
370 case NEXTDMA_SCSI(NEXTDMA_LIMIT):
371 next_state->dma[NEXTDMA_SCSI].limit = val;
372 break;
373
374 case NEXTDMA_SCSI(NEXTDMA_START):
375 next_state->dma[NEXTDMA_SCSI].start = val;
376 break;
377
378 case NEXTDMA_SCSI(NEXTDMA_STOP):
379 next_state->dma[NEXTDMA_SCSI].stop = val;
380 break;
381
382 case NEXTDMA_SCSI(NEXTDMA_NEXT_INIT):
383 next_state->dma[NEXTDMA_SCSI].next_initbuf = val;
384 break;
385
386 default:
387 DPRINTF("DMA write @ %x w/ %x\n", (unsigned)addr, (unsigned)val);
388 }
389 }
390
next_dma_read(void * opaque,hwaddr addr,unsigned int size)391 static uint64_t next_dma_read(void *opaque, hwaddr addr, unsigned int size)
392 {
393 NeXTState *next_state = NEXT_MACHINE(opaque);
394 uint64_t val;
395
396 switch (addr) {
397 case NEXTDMA_SCSI(NEXTDMA_CSR):
398 DPRINTF("SCSI DMA CSR READ\n");
399 val = next_state->dma[NEXTDMA_SCSI].csr;
400 break;
401
402 case NEXTDMA_ENRX(NEXTDMA_CSR):
403 val = next_state->dma[NEXTDMA_ENRX].csr;
404 break;
405
406 case NEXTDMA_ENRX(NEXTDMA_NEXT_INIT):
407 val = next_state->dma[NEXTDMA_ENRX].next_initbuf;
408 break;
409
410 case NEXTDMA_ENRX(NEXTDMA_NEXT):
411 val = next_state->dma[NEXTDMA_ENRX].next;
412 break;
413
414 case NEXTDMA_ENRX(NEXTDMA_LIMIT):
415 val = next_state->dma[NEXTDMA_ENRX].limit;
416 break;
417
418 case NEXTDMA_SCSI(NEXTDMA_NEXT):
419 val = next_state->dma[NEXTDMA_SCSI].next;
420 break;
421
422 case NEXTDMA_SCSI(NEXTDMA_NEXT_INIT):
423 val = next_state->dma[NEXTDMA_SCSI].next_initbuf;
424 break;
425
426 case NEXTDMA_SCSI(NEXTDMA_LIMIT):
427 val = next_state->dma[NEXTDMA_SCSI].limit;
428 break;
429
430 case NEXTDMA_SCSI(NEXTDMA_START):
431 val = next_state->dma[NEXTDMA_SCSI].start;
432 break;
433
434 case NEXTDMA_SCSI(NEXTDMA_STOP):
435 val = next_state->dma[NEXTDMA_SCSI].stop;
436 break;
437
438 default:
439 DPRINTF("DMA read @ %x\n", (unsigned int)addr);
440 val = 0;
441 }
442
443 /*
444 * once the csr's are done, subtract 0x3FEC from the addr, and that will
445 * normalize the upper registers
446 */
447
448 return val;
449 }
450
451 static const MemoryRegionOps next_dma_ops = {
452 .read = next_dma_read,
453 .write = next_dma_write,
454 .impl.min_access_size = 4,
455 .valid.min_access_size = 4,
456 .valid.max_access_size = 4,
457 .endianness = DEVICE_BIG_ENDIAN,
458 };
459
next_irq(void * opaque,int number,int level)460 static void next_irq(void *opaque, int number, int level)
461 {
462 NeXTPC *s = NEXT_PC(opaque);
463 M68kCPU *cpu = s->cpu;
464 int shift = 0;
465
466 /* first switch sets interrupt status */
467 /* DPRINTF("IRQ %i\n",number); */
468 switch (number) {
469 /* level 3 - floppy, kbd/mouse, power, ether rx/tx, scsi, clock */
470 case NEXT_FD_I:
471 shift = 7;
472 break;
473 case NEXT_KBD_I:
474 shift = 3;
475 break;
476 case NEXT_PWR_I:
477 shift = 2;
478 break;
479 case NEXT_ENRX_I:
480 shift = 9;
481 break;
482 case NEXT_ENTX_I:
483 shift = 10;
484 break;
485 case NEXT_SCSI_I:
486 shift = 12;
487 break;
488 case NEXT_CLK_I:
489 shift = 5;
490 break;
491
492 /* level 5 - scc (serial) */
493 case NEXT_SCC_I:
494 shift = 17;
495 break;
496
497 /* level 6 - audio etherrx/tx dma */
498 case NEXT_ENTX_DMA_I:
499 shift = 28;
500 break;
501 case NEXT_ENRX_DMA_I:
502 shift = 27;
503 break;
504 case NEXT_SCSI_DMA_I:
505 shift = 26;
506 break;
507 case NEXT_SND_I:
508 shift = 23;
509 break;
510 case NEXT_SCC_DMA_I:
511 shift = 21;
512 break;
513
514 }
515 /*
516 * this HAS to be wrong, the interrupt handlers in mach and together
517 * int_status and int_mask and return if there is a hit
518 */
519 if (s->int_mask & (1 << shift)) {
520 DPRINTF("%x interrupt masked @ %x\n", 1 << shift, cpu->env.pc);
521 /* return; */
522 }
523
524 /* second switch triggers the correct interrupt */
525 if (level) {
526 s->int_status |= 1 << shift;
527
528 switch (number) {
529 /* level 3 - floppy, kbd/mouse, power, ether rx/tx, scsi, clock */
530 case NEXT_FD_I:
531 case NEXT_KBD_I:
532 case NEXT_PWR_I:
533 case NEXT_ENRX_I:
534 case NEXT_ENTX_I:
535 case NEXT_SCSI_I:
536 case NEXT_CLK_I:
537 m68k_set_irq_level(cpu, 3, 27);
538 break;
539
540 /* level 5 - scc (serial) */
541 case NEXT_SCC_I:
542 m68k_set_irq_level(cpu, 5, 29);
543 break;
544
545 /* level 6 - audio etherrx/tx dma */
546 case NEXT_ENTX_DMA_I:
547 case NEXT_ENRX_DMA_I:
548 case NEXT_SCSI_DMA_I:
549 case NEXT_SND_I:
550 case NEXT_SCC_DMA_I:
551 m68k_set_irq_level(cpu, 6, 30);
552 break;
553 }
554 } else {
555 s->int_status &= ~(1 << shift);
556 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
557 }
558 }
559
nextdma_write(void * opaque,uint8_t * buf,int size,int type)560 static void nextdma_write(void *opaque, uint8_t *buf, int size, int type)
561 {
562 uint32_t base_addr;
563 int irq = 0;
564 uint8_t align = 16;
565 NeXTState *next_state = NEXT_MACHINE(qdev_get_machine());
566
567 if (type == NEXTDMA_ENRX || type == NEXTDMA_ENTX) {
568 align = 32;
569 }
570 /* Most DMA is supposedly 16 byte aligned */
571 if ((size % align) != 0) {
572 size -= size % align;
573 size += align;
574 }
575
576 /*
577 * prom sets the dma start using initbuf while the bootloader uses next
578 * so we check to see if initbuf is 0
579 */
580 if (next_state->dma[type].next_initbuf == 0) {
581 base_addr = next_state->dma[type].next;
582 } else {
583 base_addr = next_state->dma[type].next_initbuf;
584 }
585
586 cpu_physical_memory_write(base_addr, buf, size);
587
588 next_state->dma[type].next_initbuf = 0;
589
590 /* saved limit is checked to calculate packet size by both, rom and netbsd */
591 next_state->dma[type].saved_limit = (next_state->dma[type].next + size);
592 next_state->dma[type].saved_next = (next_state->dma[type].next);
593
594 /*
595 * 32 bytes under savedbase seems to be some kind of register
596 * of which the purpose is unknown as of yet
597 */
598 /* stl_phys(s->rx_dma.base-32,0xFFFFFFFF); */
599
600 if (!(next_state->dma[type].csr & DMA_SUPDATE)) {
601 next_state->dma[type].next = next_state->dma[type].start;
602 next_state->dma[type].limit = next_state->dma[type].stop;
603 }
604
605 /* Set dma registers and raise an irq */
606 next_state->dma[type].csr |= DMA_COMPLETE; /* DON'T CHANGE THIS! */
607
608 switch (type) {
609 case NEXTDMA_SCSI:
610 irq = NEXT_SCSI_DMA_I;
611 break;
612 }
613
614 next_irq(opaque, irq, 1);
615 next_irq(opaque, irq, 0);
616 }
617
nextscsi_read(void * opaque,uint8_t * buf,int len)618 static void nextscsi_read(void *opaque, uint8_t *buf, int len)
619 {
620 DPRINTF("SCSI READ: %x\n", len);
621 abort();
622 }
623
nextscsi_write(void * opaque,uint8_t * buf,int size)624 static void nextscsi_write(void *opaque, uint8_t *buf, int size)
625 {
626 DPRINTF("SCSI WRITE: %i\n", size);
627 nextdma_write(opaque, buf, size, NEXTDMA_SCSI);
628 }
629
next_scsi_csr_write(void * opaque,hwaddr addr,uint64_t val,unsigned size)630 static void next_scsi_csr_write(void *opaque, hwaddr addr, uint64_t val,
631 unsigned size)
632 {
633 NeXTSCSI *s = NEXT_SCSI(opaque);
634 NeXTPC *pc = NEXT_PC(container_of(s, NeXTPC, next_scsi));
635
636 switch (addr) {
637 case 0:
638 if (val & SCSICSR_FIFOFL) {
639 DPRINTF("SCSICSR FIFO Flush\n");
640 /* will have to add another irq to the esp if this is needed */
641 /* esp_puflush_fifo(esp_g); */
642 }
643
644 if (val & SCSICSR_ENABLE) {
645 DPRINTF("SCSICSR Enable\n");
646 /*
647 * qemu_irq_raise(s->scsi_dma);
648 * s->scsi_csr_1 = 0xc0;
649 * s->scsi_csr_1 |= 0x1;
650 * qemu_irq_pulse(s->scsi_dma);
651 */
652 }
653 /*
654 * else
655 * s->scsi_csr_1 &= ~SCSICSR_ENABLE;
656 */
657
658 if (val & SCSICSR_RESET) {
659 DPRINTF("SCSICSR Reset\n");
660 /* I think this should set DMADIR. CPUDMA and INTMASK to 0 */
661 qemu_irq_raise(pc->scsi_reset);
662 s->scsi_csr_1 &= ~(SCSICSR_INTMASK | 0x80 | 0x1);
663 qemu_irq_lower(pc->scsi_reset);
664 }
665 if (val & SCSICSR_DMADIR) {
666 DPRINTF("SCSICSR DMAdir\n");
667 }
668 if (val & SCSICSR_CPUDMA) {
669 DPRINTF("SCSICSR CPUDMA\n");
670 /* qemu_irq_raise(s->scsi_dma); */
671 pc->int_status |= 0x4000000;
672 } else {
673 /* fprintf(stderr,"SCSICSR CPUDMA disabled\n"); */
674 pc->int_status &= ~(0x4000000);
675 /* qemu_irq_lower(s->scsi_dma); */
676 }
677 if (val & SCSICSR_INTMASK) {
678 DPRINTF("SCSICSR INTMASK\n");
679 /*
680 * int_mask &= ~0x1000;
681 * s->scsi_csr_1 |= val;
682 * s->scsi_csr_1 &= ~SCSICSR_INTMASK;
683 * if (s->scsi_queued) {
684 * s->scsi_queued = 0;
685 * next_irq(s, NEXT_SCSI_I, level);
686 * }
687 */
688 } else {
689 /* int_mask |= 0x1000; */
690 }
691 if (val & 0x80) {
692 /* int_mask |= 0x1000; */
693 /* s->scsi_csr_1 |= 0x80; */
694 }
695 DPRINTF("SCSICSR1 Write: %"PRIx64 "\n", val);
696 s->scsi_csr_1 = val;
697 break;
698
699 case 1:
700 DPRINTF("SCSICSR2 Write: %"PRIx64 "\n", val);
701 s->scsi_csr_2 = val;
702 break;
703
704 default:
705 g_assert_not_reached();
706 }
707 }
708
next_scsi_csr_read(void * opaque,hwaddr addr,unsigned size)709 static uint64_t next_scsi_csr_read(void *opaque, hwaddr addr, unsigned size)
710 {
711 NeXTSCSI *s = NEXT_SCSI(opaque);
712 uint64_t val;
713
714 switch (addr) {
715 case 0:
716 DPRINTF("SCSI 4020 STATUS READ %X\n", s->scsi_csr_1);
717 val = s->scsi_csr_1;
718 break;
719
720 case 1:
721 DPRINTF("SCSI 4021 STATUS READ %X\n", s->scsi_csr_2);
722 val = s->scsi_csr_2;
723 break;
724
725 default:
726 g_assert_not_reached();
727 }
728
729 return val;
730 }
731
732 static const MemoryRegionOps next_scsi_csr_ops = {
733 .read = next_scsi_csr_read,
734 .write = next_scsi_csr_write,
735 .valid.min_access_size = 1,
736 .valid.max_access_size = 1,
737 .endianness = DEVICE_BIG_ENDIAN,
738 };
739
next_scsi_init(Object * obj)740 static void next_scsi_init(Object *obj)
741 {
742 NeXTSCSI *s = NEXT_SCSI(obj);
743 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
744
745 object_initialize_child(obj, "esp", &s->sysbus_esp, TYPE_SYSBUS_ESP);
746
747 memory_region_init_io(&s->scsi_csr_mem, obj, &next_scsi_csr_ops,
748 s, "csrs", 2);
749
750 memory_region_init(&s->scsi_mem, obj, "next.scsi", 0x40);
751 sysbus_init_mmio(sbd, &s->scsi_mem);
752 }
753
next_scsi_realize(DeviceState * dev,Error ** errp)754 static void next_scsi_realize(DeviceState *dev, Error **errp)
755 {
756 NeXTSCSI *s = NEXT_SCSI(dev);
757 SysBusESPState *sysbus_esp;
758 SysBusDevice *sbd;
759 ESPState *esp;
760 NeXTPC *pcdev;
761
762 pcdev = NEXT_PC(container_of(s, NeXTPC, next_scsi));
763
764 /* ESP */
765 sysbus_esp = SYSBUS_ESP(&s->sysbus_esp);
766 esp = &sysbus_esp->esp;
767 esp->dma_memory_read = nextscsi_read;
768 esp->dma_memory_write = nextscsi_write;
769 esp->dma_opaque = pcdev;
770 sysbus_esp->it_shift = 0;
771 esp->dma_enabled = 1;
772 sbd = SYS_BUS_DEVICE(sysbus_esp);
773 if (!sysbus_realize(sbd, errp)) {
774 return;
775 }
776 memory_region_add_subregion(&s->scsi_mem, 0x0,
777 sysbus_mmio_get_region(sbd, 0));
778
779 /* SCSI CSRs */
780 memory_region_add_subregion(&s->scsi_mem, 0x20, &s->scsi_csr_mem);
781
782 scsi_bus_legacy_handle_cmdline(&s->sysbus_esp.esp.bus);
783 }
784
785 static const VMStateDescription next_scsi_vmstate = {
786 .name = "next-scsi",
787 .version_id = 0,
788 .minimum_version_id = 0,
789 .fields = (const VMStateField[]) {
790 VMSTATE_UINT8(scsi_csr_1, NeXTSCSI),
791 VMSTATE_UINT8(scsi_csr_2, NeXTSCSI),
792 VMSTATE_END_OF_LIST()
793 },
794 };
795
next_scsi_class_init(ObjectClass * klass,void * data)796 static void next_scsi_class_init(ObjectClass *klass, void *data)
797 {
798 DeviceClass *dc = DEVICE_CLASS(klass);
799
800 dc->desc = "NeXT SCSI Controller";
801 dc->realize = next_scsi_realize;
802 dc->vmsd = &next_scsi_vmstate;
803 }
804
805 static const TypeInfo next_scsi_info = {
806 .name = TYPE_NEXT_SCSI,
807 .parent = TYPE_SYS_BUS_DEVICE,
808 .instance_init = next_scsi_init,
809 .instance_size = sizeof(NeXTSCSI),
810 .class_init = next_scsi_class_init,
811 };
812
next_floppy_write(void * opaque,hwaddr addr,uint64_t val,unsigned size)813 static void next_floppy_write(void *opaque, hwaddr addr, uint64_t val,
814 unsigned size)
815 {
816 switch (addr) {
817 case 0:
818 DPRINTF("FDCSR Write: %"PRIx64 "\n", val);
819 if (val == 0x0) {
820 /* qemu_irq_raise(s->fd_irq[0]); */
821 }
822 break;
823
824 default:
825 g_assert_not_reached();
826 }
827 }
828
next_floppy_read(void * opaque,hwaddr addr,unsigned size)829 static uint64_t next_floppy_read(void *opaque, hwaddr addr, unsigned size)
830 {
831 uint64_t val;
832
833 switch (addr) {
834 case 0:
835 DPRINTF("FD read @ %x\n", (unsigned int)addr);
836 val = 0x40 | 0x04 | 0x2 | 0x1;
837 break;
838
839 default:
840 g_assert_not_reached();
841 }
842
843 return val;
844 }
845
846 static const MemoryRegionOps next_floppy_ops = {
847 .read = next_floppy_read,
848 .write = next_floppy_write,
849 .valid.min_access_size = 1,
850 .valid.max_access_size = 4,
851 .endianness = DEVICE_BIG_ENDIAN,
852 };
853
next_timer_write(void * opaque,hwaddr addr,uint64_t val,unsigned size)854 static void next_timer_write(void *opaque, hwaddr addr, uint64_t val,
855 unsigned size)
856 {
857 switch (addr) {
858 case 0 ... 3:
859 /* Hardware timer latch - not implemented yet */
860 break;
861
862 default:
863 g_assert_not_reached();
864 }
865 }
866
next_timer_read(void * opaque,hwaddr addr,unsigned size)867 static uint64_t next_timer_read(void *opaque, hwaddr addr, unsigned size)
868 {
869 uint64_t val;
870
871 switch (addr) {
872 case 0 ... 3:
873 /*
874 * These 4 registers are the hardware timer, not sure which register
875 * is the latch instead of data, but no problems so far.
876 *
877 * Hack: We need to have the LSB change consistently to make it work
878 */
879 val = extract32(clock(), (4 - addr - size) << 3,
880 size << 3);
881 break;
882
883 default:
884 g_assert_not_reached();
885 }
886
887 return val;
888 }
889
890 static const MemoryRegionOps next_timer_ops = {
891 .read = next_timer_read,
892 .write = next_timer_write,
893 .valid.min_access_size = 1,
894 .valid.max_access_size = 4,
895 .endianness = DEVICE_BIG_ENDIAN,
896 };
897
next_dummy_en_write(void * opaque,hwaddr addr,uint64_t val,unsigned size)898 static void next_dummy_en_write(void *opaque, hwaddr addr, uint64_t val,
899 unsigned size)
900 {
901 /* Do nothing */
902 return;
903 }
904
next_dummy_en_read(void * opaque,hwaddr addr,unsigned size)905 static uint64_t next_dummy_en_read(void *opaque, hwaddr addr, unsigned size)
906 {
907 uint64_t val;
908
909 switch (addr) {
910 case 0:
911 /* For now return dummy byte to allow the Ethernet test to timeout */
912 val = 0xff;
913 break;
914
915 default:
916 val = 0;
917 }
918
919 return val;
920 }
921
922 static const MemoryRegionOps next_dummy_en_ops = {
923 .read = next_dummy_en_read,
924 .write = next_dummy_en_write,
925 .valid.min_access_size = 1,
926 .valid.max_access_size = 4,
927 .endianness = DEVICE_BIG_ENDIAN,
928 };
929
next_rtc_cmd_is_write(uint8_t cmd)930 static bool next_rtc_cmd_is_write(uint8_t cmd)
931 {
932 return (cmd >= 0x80 && cmd <= 0x9f) ||
933 (cmd == 0xb1);
934 }
935
next_rtc_data_in_irq(void * opaque,int n,int level)936 static void next_rtc_data_in_irq(void *opaque, int n, int level)
937 {
938 NeXTRTC *rtc = NEXT_RTC(opaque);
939
940 if (rtc->phase < 8) {
941 rtc->command = (rtc->command << 1) | level;
942
943 if (rtc->phase == 7 && !next_rtc_cmd_is_write(rtc->command)) {
944 if (rtc->command <= 0x1f) {
945 /* RAM registers */
946 rtc->retval = rtc->ram[rtc->command];
947 }
948 if ((rtc->command >= 0x20) && (rtc->command <= 0x2f)) {
949 /* RTC */
950 time_t time_h = time(NULL);
951 struct tm *info = localtime(&time_h);
952 rtc->retval = 0;
953
954 switch (rtc->command) {
955 case 0x20:
956 rtc->retval = SCR2_TOBCD(info->tm_sec);
957 break;
958 case 0x21:
959 rtc->retval = SCR2_TOBCD(info->tm_min);
960 break;
961 case 0x22:
962 rtc->retval = SCR2_TOBCD(info->tm_hour);
963 break;
964 case 0x24:
965 rtc->retval = SCR2_TOBCD(info->tm_mday);
966 break;
967 case 0x25:
968 rtc->retval = SCR2_TOBCD((info->tm_mon + 1));
969 break;
970 case 0x26:
971 rtc->retval = SCR2_TOBCD((info->tm_year - 100));
972 break;
973 }
974 }
975 if (rtc->command == 0x30) {
976 /* read the status 0x30 */
977 rtc->retval = rtc->status;
978 }
979 if (rtc->command == 0x31) {
980 /* read the control 0x31 */
981 rtc->retval = rtc->control;
982 }
983 }
984 }
985 if (rtc->phase >= 8 && rtc->phase < 16) {
986 if (next_rtc_cmd_is_write(rtc->command)) {
987 /* Shift in value to write */
988 rtc->value = (rtc->value << 1) | level;
989 } else {
990 /* Shift out value to read */
991 if (rtc->retval & (0x80 >> (rtc->phase - 8))) {
992 qemu_irq_raise(rtc->data_out_irq);
993 } else {
994 qemu_irq_lower(rtc->data_out_irq);
995 }
996 }
997 }
998
999 rtc->phase++;
1000 if (rtc->phase == 16 && next_rtc_cmd_is_write(rtc->command)) {
1001 if (rtc->command >= 0x80 && rtc->command <= 0x9f) {
1002 /* RAM registers */
1003 rtc->ram[rtc->command - 0x80] = rtc->value;
1004 }
1005 if (rtc->command == 0xb1) {
1006 /* write to 0x30 register */
1007 if (rtc->value & 0x04) {
1008 /* clear FTU */
1009 rtc->status = rtc->status & (~0x18);
1010 qemu_irq_lower(rtc->power_irq);
1011 }
1012 }
1013 }
1014 }
1015
next_rtc_cmd_reset_irq(void * opaque,int n,int level)1016 static void next_rtc_cmd_reset_irq(void *opaque, int n, int level)
1017 {
1018 NeXTRTC *rtc = NEXT_RTC(opaque);
1019
1020 if (level) {
1021 rtc->phase = 0;
1022 rtc->command = 0;
1023 rtc->value = 0;
1024 }
1025 }
1026
next_rtc_reset_hold(Object * obj,ResetType type)1027 static void next_rtc_reset_hold(Object *obj, ResetType type)
1028 {
1029 NeXTRTC *rtc = NEXT_RTC(obj);
1030
1031 rtc->status = 0x90;
1032
1033 /* Load RTC RAM - TODO: provide possibility to load contents from file */
1034 memcpy(rtc->ram, rtc_ram2, 32);
1035 }
1036
next_rtc_init(Object * obj)1037 static void next_rtc_init(Object *obj)
1038 {
1039 NeXTRTC *rtc = NEXT_RTC(obj);
1040
1041 qdev_init_gpio_in_named(DEVICE(obj), next_rtc_data_in_irq,
1042 "rtc-data-in", 1);
1043 qdev_init_gpio_out_named(DEVICE(obj), &rtc->data_out_irq,
1044 "rtc-data-out", 1);
1045 qdev_init_gpio_in_named(DEVICE(obj), next_rtc_cmd_reset_irq,
1046 "rtc-cmd-reset", 1);
1047 qdev_init_gpio_out_named(DEVICE(obj), &rtc->power_irq,
1048 "rtc-power-out", 1);
1049 }
1050
1051 static const VMStateDescription next_rtc_vmstate = {
1052 .name = "next-rtc",
1053 .version_id = 3,
1054 .minimum_version_id = 3,
1055 .fields = (const VMStateField[]) {
1056 VMSTATE_INT8(phase, NeXTRTC),
1057 VMSTATE_UINT8_ARRAY(ram, NeXTRTC, 32),
1058 VMSTATE_UINT8(command, NeXTRTC),
1059 VMSTATE_UINT8(value, NeXTRTC),
1060 VMSTATE_UINT8(status, NeXTRTC),
1061 VMSTATE_UINT8(control, NeXTRTC),
1062 VMSTATE_UINT8(retval, NeXTRTC),
1063 VMSTATE_END_OF_LIST()
1064 },
1065 };
1066
next_rtc_class_init(ObjectClass * klass,void * data)1067 static void next_rtc_class_init(ObjectClass *klass, void *data)
1068 {
1069 DeviceClass *dc = DEVICE_CLASS(klass);
1070 ResettableClass *rc = RESETTABLE_CLASS(klass);
1071
1072 dc->desc = "NeXT RTC";
1073 dc->vmsd = &next_rtc_vmstate;
1074 rc->phases.hold = next_rtc_reset_hold;
1075 }
1076
1077 static const TypeInfo next_rtc_info = {
1078 .name = TYPE_NEXT_RTC,
1079 .parent = TYPE_SYS_BUS_DEVICE,
1080 .instance_init = next_rtc_init,
1081 .instance_size = sizeof(NeXTRTC),
1082 .class_init = next_rtc_class_init,
1083 };
1084
next_pc_rtc_data_in_irq(void * opaque,int n,int level)1085 static void next_pc_rtc_data_in_irq(void *opaque, int n, int level)
1086 {
1087 NeXTPC *s = NEXT_PC(opaque);
1088 uint8_t scr2_2 = extract32(s->scr2, 8, 8);
1089
1090 if (level) {
1091 scr2_2 |= SCR2_RTDATA;
1092 } else {
1093 scr2_2 &= ~SCR2_RTDATA;
1094 }
1095
1096 s->scr2 = deposit32(s->scr2, 8, 8, scr2_2);
1097 }
1098
next_pc_reset_hold(Object * obj,ResetType type)1099 static void next_pc_reset_hold(Object *obj, ResetType type)
1100 {
1101 NeXTPC *s = NEXT_PC(obj);
1102
1103 /* Set internal registers to initial values */
1104 /* 0x0000XX00 << vital bits */
1105 s->scr1 = 0x00011102;
1106 s->scr2 = 0x00ff0c80;
1107 s->old_scr2 = s->scr2;
1108 }
1109
next_pc_realize(DeviceState * dev,Error ** errp)1110 static void next_pc_realize(DeviceState *dev, Error **errp)
1111 {
1112 NeXTPC *s = NEXT_PC(dev);
1113 SysBusDevice *sbd;
1114 DeviceState *d;
1115
1116 /* SCSI */
1117 sbd = SYS_BUS_DEVICE(&s->next_scsi);
1118 if (!sysbus_realize(sbd, errp)) {
1119 return;
1120 }
1121
1122 d = DEVICE(object_resolve_path_component(OBJECT(&s->next_scsi), "esp"));
1123 sysbus_connect_irq(SYS_BUS_DEVICE(d), 0,
1124 qdev_get_gpio_in(DEVICE(s), NEXT_SCSI_I));
1125
1126 s->scsi_reset = qdev_get_gpio_in(d, 0);
1127 s->scsi_dma = qdev_get_gpio_in(d, 1);
1128
1129 /* ESCC */
1130 d = DEVICE(&s->escc);
1131 qdev_prop_set_uint32(d, "disabled", 0);
1132 qdev_prop_set_uint32(d, "frequency", 9600 * 384);
1133 qdev_prop_set_uint32(d, "it_shift", 0);
1134 qdev_prop_set_bit(d, "bit_swap", true);
1135 qdev_prop_set_chr(d, "chrB", serial_hd(1));
1136 qdev_prop_set_chr(d, "chrA", serial_hd(0));
1137 qdev_prop_set_uint32(d, "chnBtype", escc_serial);
1138 qdev_prop_set_uint32(d, "chnAtype", escc_serial);
1139
1140 sbd = SYS_BUS_DEVICE(d);
1141 if (!sysbus_realize(sbd, errp)) {
1142 return;
1143 }
1144 sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(dev, NEXT_SCC_I));
1145 sysbus_connect_irq(sbd, 1, qdev_get_gpio_in(dev, NEXT_SCC_DMA_I));
1146
1147 /* RTC */
1148 d = DEVICE(&s->rtc);
1149 if (!sysbus_realize(SYS_BUS_DEVICE(d), errp)) {
1150 return;
1151 }
1152 /* Data from NeXTPC to RTC */
1153 qdev_connect_gpio_out_named(dev, "rtc-data-out", 0,
1154 qdev_get_gpio_in_named(d, "rtc-data-in", 0));
1155 /* Data from RTC to NeXTPC */
1156 qdev_connect_gpio_out_named(d, "rtc-data-out", 0,
1157 qdev_get_gpio_in_named(dev,
1158 "rtc-data-in", 0));
1159 qdev_connect_gpio_out_named(dev, "rtc-cmd-reset", 0,
1160 qdev_get_gpio_in_named(d, "rtc-cmd-reset", 0));
1161 qdev_connect_gpio_out_named(d, "rtc-power-out", 0,
1162 qdev_get_gpio_in(dev, NEXT_PWR_I));
1163 }
1164
next_pc_init(Object * obj)1165 static void next_pc_init(Object *obj)
1166 {
1167 NeXTPC *s = NEXT_PC(obj);
1168 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
1169
1170 qdev_init_gpio_in(DEVICE(obj), next_irq, NEXT_NUM_IRQS);
1171
1172 memory_region_init_io(&s->mmiomem, OBJECT(s), &next_mmio_ops, s,
1173 "next.mmio", 0x9000);
1174 sysbus_init_mmio(sbd, &s->mmiomem);
1175
1176 memory_region_init_io(&s->dummyen_mem, OBJECT(s), &next_dummy_en_ops, s,
1177 "next.en", 0x20);
1178 sysbus_init_mmio(sbd, &s->dummyen_mem);
1179
1180 object_initialize_child(obj, "next-scsi", &s->next_scsi, TYPE_NEXT_SCSI);
1181 sysbus_init_mmio(sbd,
1182 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->next_scsi), 0));
1183
1184 memory_region_init_io(&s->floppy_mem, OBJECT(s), &next_floppy_ops, s,
1185 "next.floppy", 4);
1186 sysbus_init_mmio(sbd, &s->floppy_mem);
1187
1188 object_initialize_child(obj, "escc", &s->escc, TYPE_ESCC);
1189 sysbus_init_mmio(sbd,
1190 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->escc), 0));
1191
1192 memory_region_init_io(&s->timer_mem, OBJECT(s), &next_timer_ops, s,
1193 "next.timer", 4);
1194 sysbus_init_mmio(sbd, &s->timer_mem);
1195
1196 object_initialize_child(obj, "rtc", &s->rtc, TYPE_NEXT_RTC);
1197
1198 qdev_init_gpio_in_named(DEVICE(obj), next_pc_rtc_data_in_irq,
1199 "rtc-data-in", 1);
1200 qdev_init_gpio_out_named(DEVICE(obj), &s->rtc_data_irq,
1201 "rtc-data-out", 1);
1202 qdev_init_gpio_out_named(DEVICE(obj), &s->rtc_cmd_reset_irq,
1203 "rtc-cmd-reset", 1);
1204 }
1205
1206 /*
1207 * If the m68k CPU implemented its inbound irq lines as GPIO lines
1208 * rather than via the m68k_set_irq_level() function we would not need
1209 * this cpu link property and could instead provide outbound IRQ lines
1210 * that the board could wire up to the CPU.
1211 */
1212 static const Property next_pc_properties[] = {
1213 DEFINE_PROP_LINK("cpu", NeXTPC, cpu, TYPE_M68K_CPU, M68kCPU *),
1214 };
1215
1216 static const VMStateDescription next_pc_vmstate = {
1217 .name = "next-pc",
1218 .version_id = 4,
1219 .minimum_version_id = 4,
1220 .fields = (const VMStateField[]) {
1221 VMSTATE_UINT32(scr1, NeXTPC),
1222 VMSTATE_UINT32(scr2, NeXTPC),
1223 VMSTATE_UINT32(old_scr2, NeXTPC),
1224 VMSTATE_UINT32(int_mask, NeXTPC),
1225 VMSTATE_UINT32(int_status, NeXTPC),
1226 VMSTATE_UINT32(led, NeXTPC),
1227 VMSTATE_END_OF_LIST()
1228 },
1229 };
1230
next_pc_class_init(ObjectClass * klass,void * data)1231 static void next_pc_class_init(ObjectClass *klass, void *data)
1232 {
1233 DeviceClass *dc = DEVICE_CLASS(klass);
1234 ResettableClass *rc = RESETTABLE_CLASS(klass);
1235
1236 dc->desc = "NeXT Peripheral Controller";
1237 dc->realize = next_pc_realize;
1238 device_class_set_props(dc, next_pc_properties);
1239 dc->vmsd = &next_pc_vmstate;
1240 rc->phases.hold = next_pc_reset_hold;
1241 }
1242
1243 static const TypeInfo next_pc_info = {
1244 .name = TYPE_NEXT_PC,
1245 .parent = TYPE_SYS_BUS_DEVICE,
1246 .instance_init = next_pc_init,
1247 .instance_size = sizeof(NeXTPC),
1248 .class_init = next_pc_class_init,
1249 };
1250
next_cube_init(MachineState * machine)1251 static void next_cube_init(MachineState *machine)
1252 {
1253 NeXTState *m = NEXT_MACHINE(machine);
1254 M68kCPU *cpu;
1255 CPUM68KState *env;
1256 MemoryRegion *sysmem = get_system_memory();
1257 const char *bios_name = machine->firmware ?: ROM_FILE;
1258 DeviceState *pcdev;
1259
1260 /* Initialize the cpu core */
1261 cpu = M68K_CPU(cpu_create(machine->cpu_type));
1262 if (!cpu) {
1263 error_report("Unable to find m68k CPU definition");
1264 exit(1);
1265 }
1266 env = &cpu->env;
1267
1268 /* Initialize CPU registers. */
1269 env->vbr = 0;
1270 env->sr = 0x2700;
1271
1272 /* Peripheral Controller */
1273 pcdev = qdev_new(TYPE_NEXT_PC);
1274 object_property_set_link(OBJECT(pcdev), "cpu", OBJECT(cpu), &error_abort);
1275 sysbus_realize_and_unref(SYS_BUS_DEVICE(pcdev), &error_fatal);
1276
1277 /* 64MB RAM starting at 0x04000000 */
1278 memory_region_add_subregion(sysmem, 0x04000000, machine->ram);
1279
1280 /* Framebuffer */
1281 sysbus_create_simple(TYPE_NEXTFB, 0x0B000000, NULL);
1282
1283 /* MMIO */
1284 sysbus_mmio_map(SYS_BUS_DEVICE(pcdev), 0, 0x02005000);
1285
1286 /* BMAP IO - acts as a catch-all for now */
1287 sysbus_mmio_map(SYS_BUS_DEVICE(pcdev), 1, 0x02100000);
1288
1289 /* en network (dummy) */
1290 sysbus_mmio_map(SYS_BUS_DEVICE(pcdev), 1, 0x02106000);
1291
1292 /* unknown: Brightness control register? */
1293 empty_slot_init("next.unknown.0", 0x02110000, 0x10);
1294 /* unknown: Magneto-Optical drive controller? */
1295 empty_slot_init("next.unknown.1", 0x02112000, 0x10);
1296
1297 /* SCSI */
1298 sysbus_mmio_map(SYS_BUS_DEVICE(pcdev), 2, 0x02114000);
1299 /* Floppy */
1300 sysbus_mmio_map(SYS_BUS_DEVICE(pcdev), 3, 0x02114108);
1301 /* ESCC */
1302 sysbus_mmio_map(SYS_BUS_DEVICE(pcdev), 4, 0x02118000);
1303
1304 /* unknown: Serial clock configuration register? */
1305 empty_slot_init("next.unknown.2", 0x02118004, 0x10);
1306
1307 /* Timer */
1308 sysbus_mmio_map(SYS_BUS_DEVICE(pcdev), 5, 0x0211a000);
1309
1310 /* BMAP memory */
1311 memory_region_init_ram_flags_nomigrate(&m->bmapm1, NULL, "next.bmapmem",
1312 64, RAM_SHARED, &error_fatal);
1313 memory_region_add_subregion(sysmem, 0x020c0000, &m->bmapm1);
1314 /* The Rev_2.5_v66.bin firmware accesses it at 0x820c0020, too */
1315 memory_region_init_alias(&m->bmapm2, NULL, "next.bmapmem2", &m->bmapm1,
1316 0x0, 64);
1317 memory_region_add_subregion(sysmem, 0x820c0000, &m->bmapm2);
1318
1319 /* KBD */
1320 sysbus_create_simple(TYPE_NEXTKBD, 0x0200e000, NULL);
1321
1322 /* Load ROM here */
1323 memory_region_init_rom(&m->rom, NULL, "next.rom", 0x20000, &error_fatal);
1324 memory_region_add_subregion(sysmem, 0x01000000, &m->rom);
1325 memory_region_init_alias(&m->rom2, NULL, "next.rom2", &m->rom, 0x0,
1326 0x20000);
1327 memory_region_add_subregion(sysmem, 0x0, &m->rom2);
1328 if (load_image_targphys(bios_name, 0x01000000, 0x20000) < 8) {
1329 if (!qtest_enabled()) {
1330 error_report("Failed to load firmware '%s'.", bios_name);
1331 }
1332 } else {
1333 uint8_t *ptr;
1334 /* Initial PC is always at offset 4 in firmware binaries */
1335 ptr = rom_ptr(0x01000004, 4);
1336 g_assert(ptr != NULL);
1337 env->pc = ldl_be_p(ptr);
1338 if (env->pc >= 0x01020000) {
1339 error_report("'%s' does not seem to be a valid firmware image.",
1340 bios_name);
1341 exit(1);
1342 }
1343 }
1344
1345 /* DMA */
1346 memory_region_init_io(&m->dmamem, NULL, &next_dma_ops, machine,
1347 "next.dma", 0x5000);
1348 memory_region_add_subregion(sysmem, 0x02000000, &m->dmamem);
1349 }
1350
next_machine_class_init(ObjectClass * oc,void * data)1351 static void next_machine_class_init(ObjectClass *oc, void *data)
1352 {
1353 MachineClass *mc = MACHINE_CLASS(oc);
1354
1355 mc->desc = "NeXT Cube";
1356 mc->init = next_cube_init;
1357 mc->block_default_type = IF_SCSI;
1358 mc->default_ram_size = RAM_SIZE;
1359 mc->default_ram_id = "next.ram";
1360 mc->default_cpu_type = M68K_CPU_TYPE_NAME("m68040");
1361 mc->no_cdrom = true;
1362 }
1363
1364 static const TypeInfo next_typeinfo = {
1365 .name = TYPE_NEXT_MACHINE,
1366 .parent = TYPE_MACHINE,
1367 .class_init = next_machine_class_init,
1368 .instance_size = sizeof(NeXTState),
1369 };
1370
next_register_type(void)1371 static void next_register_type(void)
1372 {
1373 type_register_static(&next_typeinfo);
1374 type_register_static(&next_pc_info);
1375 type_register_static(&next_scsi_info);
1376 type_register_static(&next_rtc_info);
1377 }
1378
1379 type_init(next_register_type)
1380