xref: /openbmc/linux/drivers/usb/gadget/udc/mv_udc.h (revision 229e3682)
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright (C) 2011 Marvell International Ltd. All rights reserved.
4  */
5 
6 #ifndef __MV_UDC_H
7 #define __MV_UDC_H
8 
9 #define VUSBHS_MAX_PORTS	8
10 
11 #define DQH_ALIGNMENT		2048
12 #define DTD_ALIGNMENT		64
13 #define DMA_BOUNDARY		4096
14 
15 #define EP_DIR_IN	1
16 #define EP_DIR_OUT	0
17 
18 #define DMA_ADDR_INVALID	(~(dma_addr_t)0)
19 
20 #define EP0_MAX_PKT_SIZE	64
21 /* ep0 transfer state */
22 #define WAIT_FOR_SETUP		0
23 #define DATA_STATE_XMIT		1
24 #define DATA_STATE_NEED_ZLP	2
25 #define WAIT_FOR_OUT_STATUS	3
26 #define DATA_STATE_RECV		4
27 
28 #define CAPLENGTH_MASK		(0xff)
29 #define DCCPARAMS_DEN_MASK	(0x1f)
30 
31 #define HCSPARAMS_PPC		(0x10)
32 
33 /* Frame Index Register Bit Masks */
34 #define USB_FRINDEX_MASKS	0x3fff
35 
36 /* Command Register Bit Masks */
37 #define USBCMD_RUN_STOP				(0x00000001)
38 #define USBCMD_CTRL_RESET			(0x00000002)
39 #define USBCMD_SETUP_TRIPWIRE_SET		(0x00002000)
40 #define USBCMD_SETUP_TRIPWIRE_CLEAR		(~USBCMD_SETUP_TRIPWIRE_SET)
41 
42 #define USBCMD_ATDTW_TRIPWIRE_SET		(0x00004000)
43 #define USBCMD_ATDTW_TRIPWIRE_CLEAR		(~USBCMD_ATDTW_TRIPWIRE_SET)
44 
45 /* bit 15,3,2 are for frame list size */
46 #define USBCMD_FRAME_SIZE_1024			(0x00000000) /* 000 */
47 #define USBCMD_FRAME_SIZE_512			(0x00000004) /* 001 */
48 #define USBCMD_FRAME_SIZE_256			(0x00000008) /* 010 */
49 #define USBCMD_FRAME_SIZE_128			(0x0000000C) /* 011 */
50 #define USBCMD_FRAME_SIZE_64			(0x00008000) /* 100 */
51 #define USBCMD_FRAME_SIZE_32			(0x00008004) /* 101 */
52 #define USBCMD_FRAME_SIZE_16			(0x00008008) /* 110 */
53 #define USBCMD_FRAME_SIZE_8			(0x0000800C) /* 111 */
54 
55 #define EPCTRL_TX_ALL_MASK			(0xFFFF0000)
56 #define EPCTRL_RX_ALL_MASK			(0x0000FFFF)
57 
58 #define EPCTRL_TX_DATA_TOGGLE_RST		(0x00400000)
59 #define EPCTRL_TX_EP_STALL			(0x00010000)
60 #define EPCTRL_RX_EP_STALL			(0x00000001)
61 #define EPCTRL_RX_DATA_TOGGLE_RST		(0x00000040)
62 #define EPCTRL_RX_ENABLE			(0x00000080)
63 #define EPCTRL_TX_ENABLE			(0x00800000)
64 #define EPCTRL_CONTROL				(0x00000000)
65 #define EPCTRL_ISOCHRONOUS			(0x00040000)
66 #define EPCTRL_BULK				(0x00080000)
67 #define EPCTRL_INT				(0x000C0000)
68 #define EPCTRL_TX_TYPE				(0x000C0000)
69 #define EPCTRL_RX_TYPE				(0x0000000C)
70 #define EPCTRL_DATA_TOGGLE_INHIBIT		(0x00000020)
71 #define EPCTRL_TX_EP_TYPE_SHIFT			(18)
72 #define EPCTRL_RX_EP_TYPE_SHIFT			(2)
73 
74 #define EPCOMPLETE_MAX_ENDPOINTS		(16)
75 
76 /* endpoint list address bit masks */
77 #define USB_EP_LIST_ADDRESS_MASK              0xfffff800
78 
79 #define PORTSCX_W1C_BITS			0x2a
80 #define PORTSCX_PORT_RESET			0x00000100
81 #define PORTSCX_PORT_POWER			0x00001000
82 #define PORTSCX_FORCE_FULL_SPEED_CONNECT	0x01000000
83 #define PORTSCX_PAR_XCVR_SELECT			0xC0000000
84 #define PORTSCX_PORT_FORCE_RESUME		0x00000040
85 #define PORTSCX_PORT_SUSPEND			0x00000080
86 #define PORTSCX_PORT_SPEED_FULL			0x00000000
87 #define PORTSCX_PORT_SPEED_LOW			0x04000000
88 #define PORTSCX_PORT_SPEED_HIGH			0x08000000
89 #define PORTSCX_PORT_SPEED_MASK			0x0C000000
90 
91 /* USB MODE Register Bit Masks */
92 #define USBMODE_CTRL_MODE_IDLE			0x00000000
93 #define USBMODE_CTRL_MODE_DEVICE		0x00000002
94 #define USBMODE_CTRL_MODE_HOST			0x00000003
95 #define USBMODE_CTRL_MODE_RSV			0x00000001
96 #define USBMODE_SETUP_LOCK_OFF			0x00000008
97 #define USBMODE_STREAM_DISABLE			0x00000010
98 
99 /* USB STS Register Bit Masks */
100 #define USBSTS_INT			0x00000001
101 #define USBSTS_ERR			0x00000002
102 #define USBSTS_PORT_CHANGE		0x00000004
103 #define USBSTS_FRM_LST_ROLL		0x00000008
104 #define USBSTS_SYS_ERR			0x00000010
105 #define USBSTS_IAA			0x00000020
106 #define USBSTS_RESET			0x00000040
107 #define USBSTS_SOF			0x00000080
108 #define USBSTS_SUSPEND			0x00000100
109 #define USBSTS_HC_HALTED		0x00001000
110 #define USBSTS_RCL			0x00002000
111 #define USBSTS_PERIODIC_SCHEDULE	0x00004000
112 #define USBSTS_ASYNC_SCHEDULE		0x00008000
113 
114 
115 /* Interrupt Enable Register Bit Masks */
116 #define USBINTR_INT_EN                          (0x00000001)
117 #define USBINTR_ERR_INT_EN                      (0x00000002)
118 #define USBINTR_PORT_CHANGE_DETECT_EN           (0x00000004)
119 
120 #define USBINTR_ASYNC_ADV_AAE                   (0x00000020)
121 #define USBINTR_ASYNC_ADV_AAE_ENABLE            (0x00000020)
122 #define USBINTR_ASYNC_ADV_AAE_DISABLE           (0xFFFFFFDF)
123 
124 #define USBINTR_RESET_EN                        (0x00000040)
125 #define USBINTR_SOF_UFRAME_EN                   (0x00000080)
126 #define USBINTR_DEVICE_SUSPEND                  (0x00000100)
127 
128 #define USB_DEVICE_ADDRESS_MASK			(0xfe000000)
129 #define USB_DEVICE_ADDRESS_BIT_SHIFT		(25)
130 
131 struct mv_cap_regs {
132 	u32	caplength_hciversion;
133 	u32	hcsparams;	/* HC structural parameters */
134 	u32	hccparams;	/* HC Capability Parameters*/
135 	u32	reserved[5];
136 	u32	dciversion;	/* DC version number and reserved 16 bits */
137 	u32	dccparams;	/* DC Capability Parameters */
138 };
139 
140 struct mv_op_regs {
141 	u32	usbcmd;		/* Command register */
142 	u32	usbsts;		/* Status register */
143 	u32	usbintr;	/* Interrupt enable */
144 	u32	frindex;	/* Frame index */
145 	u32	reserved1[1];
146 	u32	deviceaddr;	/* Device Address */
147 	u32	eplistaddr;	/* Endpoint List Address */
148 	u32	ttctrl;		/* HOST TT status and control */
149 	u32	burstsize;	/* Programmable Burst Size */
150 	u32	txfilltuning;	/* Host Transmit Pre-Buffer Packet Tuning */
151 	u32	reserved[4];
152 	u32	epnak;		/* Endpoint NAK */
153 	u32	epnaken;	/* Endpoint NAK Enable */
154 	u32	configflag;	/* Configured Flag register */
155 	u32	portsc[VUSBHS_MAX_PORTS]; /* Port Status/Control x, x = 1..8 */
156 	u32	otgsc;
157 	u32	usbmode;	/* USB Host/Device mode */
158 	u32	epsetupstat;	/* Endpoint Setup Status */
159 	u32	epprime;	/* Endpoint Initialize */
160 	u32	epflush;	/* Endpoint De-initialize */
161 	u32	epstatus;	/* Endpoint Status */
162 	u32	epcomplete;	/* Endpoint Interrupt On Complete */
163 	u32	epctrlx[16];	/* Endpoint Control, where x = 0.. 15 */
164 	u32	mcr;		/* Mux Control */
165 	u32	isr;		/* Interrupt Status */
166 	u32	ier;		/* Interrupt Enable */
167 };
168 
169 struct mv_udc {
170 	struct usb_gadget		gadget;
171 	struct usb_gadget_driver	*driver;
172 	spinlock_t			lock;
173 	struct completion		*done;
174 	struct platform_device		*dev;
175 	int				irq;
176 
177 	struct mv_cap_regs __iomem	*cap_regs;
178 	struct mv_op_regs __iomem	*op_regs;
179 	void __iomem                    *phy_regs;
180 	unsigned int			max_eps;
181 	struct mv_dqh			*ep_dqh;
182 	size_t				ep_dqh_size;
183 	dma_addr_t			ep_dqh_dma;
184 
185 	struct dma_pool			*dtd_pool;
186 	struct mv_ep			*eps;
187 
188 	struct mv_dtd			*dtd_head;
189 	struct mv_dtd			*dtd_tail;
190 	unsigned int			dtd_entries;
191 
192 	struct mv_req			*status_req;
193 	struct usb_ctrlrequest		local_setup_buff;
194 
195 	unsigned int		resume_state;	/* USB state to resume */
196 	unsigned int		usb_state;	/* USB current state */
197 	unsigned int		ep0_state;	/* Endpoint zero state */
198 	unsigned int		ep0_dir;
199 
200 	unsigned int		dev_addr;
201 	unsigned int		test_mode;
202 
203 	int			errors;
204 	unsigned		softconnect:1,
205 				vbus_active:1,
206 				remote_wakeup:1,
207 				softconnected:1,
208 				force_fs:1,
209 				clock_gating:1,
210 				active:1,
211 				stopped:1;      /* stop bit is setted */
212 
213 	struct work_struct	vbus_work;
214 	struct workqueue_struct *qwork;
215 
216 	struct usb_phy		*transceiver;
217 
218 	struct mv_usb_platform_data     *pdata;
219 
220 	/* some SOC has mutiple clock sources for USB*/
221 	struct clk      *clk;
222 };
223 
224 /* endpoint data structure */
225 struct mv_ep {
226 	struct usb_ep		ep;
227 	struct mv_udc		*udc;
228 	struct list_head	queue;
229 	struct mv_dqh		*dqh;
230 	u32			direction;
231 	char			name[14];
232 	unsigned		stopped:1,
233 				wedge:1,
234 				ep_type:2,
235 				ep_num:8;
236 };
237 
238 /* request data structure */
239 struct mv_req {
240 	struct usb_request	req;
241 	struct mv_dtd		*dtd, *head, *tail;
242 	struct mv_ep		*ep;
243 	struct list_head	queue;
244 	unsigned int            test_mode;
245 	unsigned		dtd_count;
246 	unsigned		mapped:1;
247 };
248 
249 #define EP_QUEUE_HEAD_MULT_POS			30
250 #define EP_QUEUE_HEAD_ZLT_SEL			0x20000000
251 #define EP_QUEUE_HEAD_MAX_PKT_LEN_POS		16
252 #define EP_QUEUE_HEAD_MAX_PKT_LEN(ep_info)	(((ep_info)>>16)&0x07ff)
253 #define EP_QUEUE_HEAD_IOS			0x00008000
254 #define EP_QUEUE_HEAD_NEXT_TERMINATE		0x00000001
255 #define EP_QUEUE_HEAD_IOC			0x00008000
256 #define EP_QUEUE_HEAD_MULTO			0x00000C00
257 #define EP_QUEUE_HEAD_STATUS_HALT		0x00000040
258 #define EP_QUEUE_HEAD_STATUS_ACTIVE		0x00000080
259 #define EP_QUEUE_CURRENT_OFFSET_MASK		0x00000FFF
260 #define EP_QUEUE_HEAD_NEXT_POINTER_MASK		0xFFFFFFE0
261 #define EP_QUEUE_FRINDEX_MASK			0x000007FF
262 #define EP_MAX_LENGTH_TRANSFER			0x4000
263 
264 struct mv_dqh {
265 	/* Bits 16..26 Bit 15 is Interrupt On Setup */
266 	u32	max_packet_length;
267 	u32	curr_dtd_ptr;		/* Current dTD Pointer */
268 	u32	next_dtd_ptr;		/* Next dTD Pointer */
269 	/* Total bytes (16..30), IOC (15), INT (8), STS (0-7) */
270 	u32	size_ioc_int_sts;
271 	u32	buff_ptr0;		/* Buffer pointer Page 0 (12-31) */
272 	u32	buff_ptr1;		/* Buffer pointer Page 1 (12-31) */
273 	u32	buff_ptr2;		/* Buffer pointer Page 2 (12-31) */
274 	u32	buff_ptr3;		/* Buffer pointer Page 3 (12-31) */
275 	u32	buff_ptr4;		/* Buffer pointer Page 4 (12-31) */
276 	u32	reserved1;
277 	/* 8 bytes of setup data that follows the Setup PID */
278 	u8	setup_buffer[8];
279 	u32	reserved2[4];
280 };
281 
282 
283 #define DTD_NEXT_TERMINATE		(0x00000001)
284 #define DTD_IOC				(0x00008000)
285 #define DTD_STATUS_ACTIVE		(0x00000080)
286 #define DTD_STATUS_HALTED		(0x00000040)
287 #define DTD_STATUS_DATA_BUFF_ERR	(0x00000020)
288 #define DTD_STATUS_TRANSACTION_ERR	(0x00000008)
289 #define DTD_RESERVED_FIELDS		(0x00007F00)
290 #define DTD_ERROR_MASK			(0x68)
291 #define DTD_ADDR_MASK			(0xFFFFFFE0)
292 #define DTD_PACKET_SIZE			0x7FFF0000
293 #define DTD_LENGTH_BIT_POS		(16)
294 
295 struct mv_dtd {
296 	u32	dtd_next;
297 	u32	size_ioc_sts;
298 	u32	buff_ptr0;		/* Buffer pointer Page 0 */
299 	u32	buff_ptr1;		/* Buffer pointer Page 1 */
300 	u32	buff_ptr2;		/* Buffer pointer Page 2 */
301 	u32	buff_ptr3;		/* Buffer pointer Page 3 */
302 	u32	buff_ptr4;		/* Buffer pointer Page 4 */
303 	u32	scratch_ptr;
304 	/* 32 bytes */
305 	dma_addr_t td_dma;		/* dma address for this td */
306 	struct mv_dtd *next_dtd_virt;
307 };
308 
309 #endif
310