1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2011
4 * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
5 *
6 * Copyright (C) 2009 TechNexion Ltd.
7 */
8
9 #include <common.h>
10 #include <netdev.h>
11 #include <malloc.h>
12 #include <fpga.h>
13 #include <video_fb.h>
14 #include <asm/io.h>
15 #include <asm/arch/mem.h>
16 #include <asm/arch/mux.h>
17 #include <asm/arch/sys_proto.h>
18 #include <asm/omap_gpio.h>
19 #include <asm/arch/mmc_host_def.h>
20 #include <asm/arch/dss.h>
21 #include <asm/arch/clock.h>
22 #include <i2c.h>
23 #include <spartan3.h>
24 #include <asm/gpio.h>
25 #ifdef CONFIG_USB_EHCI_HCD
26 #include <usb.h>
27 #include <asm/ehci-omap.h>
28 #endif
29 #include "mt_ventoux.h"
30
31 DECLARE_GLOBAL_DATA_PTR;
32
33 #define BUZZER 140
34 #define SPEAKER 141
35 #define USB1_PWR 127
36 #define USB2_PWR 149
37
38 #ifndef CONFIG_FPGA
39 #error "The Teejet mt_ventoux must have CONFIG_FPGA enabled"
40 #endif
41
42 #define FPGA_RESET 62
43 #define FPGA_PROG 116
44 #define FPGA_CCLK 117
45 #define FPGA_DIN 118
46 #define FPGA_INIT 119
47 #define FPGA_DONE 154
48
49 #define LCD_PWR 138
50 #define LCD_PON_PIN 139
51
52 #if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD)
53 static struct {
54 u32 xres;
55 u32 yres;
56 } panel_resolution[] = {
57 { 480, 272 },
58 { 800, 480 }
59 };
60
61 static struct panel_config lcd_cfg[] = {
62 {
63 .timing_h = PANEL_TIMING_H(40, 5, 2),
64 .timing_v = PANEL_TIMING_V(8, 8, 2),
65 .pol_freq = 0x00003000, /* Pol Freq */
66 .divisor = 0x00010033, /* 9 Mhz Pixel Clock */
67 .panel_type = 0x01, /* TFT */
68 .data_lines = 0x03, /* 24 Bit RGB */
69 .load_mode = 0x02, /* Frame Mode */
70 .panel_color = 0,
71 .gfx_format = GFXFORMAT_RGB24_UNPACKED,
72 },
73 {
74 .timing_h = PANEL_TIMING_H(20, 192, 4),
75 .timing_v = PANEL_TIMING_V(2, 20, 10),
76 .pol_freq = 0x00004000, /* Pol Freq */
77 .divisor = 0x0001000E, /* 36Mhz Pixel Clock */
78 .panel_type = 0x01, /* TFT */
79 .data_lines = 0x03, /* 24 Bit RGB */
80 .load_mode = 0x02, /* Frame Mode */
81 .panel_color = 0,
82 .gfx_format = GFXFORMAT_RGB24_UNPACKED,
83 }
84 };
85 #endif
86
87 /* Timing definitions for FPGA */
88 static const u32 gpmc_fpga[] = {
89 FPGA_GPMC_CONFIG1,
90 FPGA_GPMC_CONFIG2,
91 FPGA_GPMC_CONFIG3,
92 FPGA_GPMC_CONFIG4,
93 FPGA_GPMC_CONFIG5,
94 FPGA_GPMC_CONFIG6,
95 };
96
97 #ifdef CONFIG_USB_EHCI_HCD
98 static struct omap_usbhs_board_data usbhs_bdata = {
99 .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
100 .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
101 .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
102 };
103
ehci_hcd_init(int index,enum usb_init_type init,struct ehci_hccr ** hccr,struct ehci_hcor ** hcor)104 int ehci_hcd_init(int index, enum usb_init_type init,
105 struct ehci_hccr **hccr, struct ehci_hcor **hcor)
106 {
107 return omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
108 }
109
ehci_hcd_stop(int index)110 int ehci_hcd_stop(int index)
111 {
112 return omap_ehci_hcd_stop();
113 }
114 #endif
115
116
fpga_reset(int nassert)117 static inline void fpga_reset(int nassert)
118 {
119 gpio_set_value(FPGA_RESET, !nassert);
120 }
121
fpga_pgm_fn(int nassert,int nflush,int cookie)122 int fpga_pgm_fn(int nassert, int nflush, int cookie)
123 {
124 debug("%s:%d: FPGA PROGRAM ", __func__, __LINE__);
125
126 gpio_set_value(FPGA_PROG, !nassert);
127
128 return nassert;
129 }
130
fpga_init_fn(int cookie)131 int fpga_init_fn(int cookie)
132 {
133 return !gpio_get_value(FPGA_INIT);
134 }
135
fpga_done_fn(int cookie)136 int fpga_done_fn(int cookie)
137 {
138 return gpio_get_value(FPGA_DONE);
139 }
140
fpga_pre_config_fn(int cookie)141 int fpga_pre_config_fn(int cookie)
142 {
143 debug("%s:%d: FPGA pre-configuration\n", __func__, __LINE__);
144
145 /* Setting GPIOs for programming Mode */
146 gpio_request(FPGA_RESET, "FPGA_RESET");
147 gpio_direction_output(FPGA_RESET, 1);
148 gpio_request(FPGA_PROG, "FPGA_PROG");
149 gpio_direction_output(FPGA_PROG, 1);
150 gpio_request(FPGA_CCLK, "FPGA_CCLK");
151 gpio_direction_output(FPGA_CCLK, 1);
152 gpio_request(FPGA_DIN, "FPGA_DIN");
153 gpio_direction_output(FPGA_DIN, 0);
154 gpio_request(FPGA_INIT, "FPGA_INIT");
155 gpio_direction_input(FPGA_INIT);
156 gpio_request(FPGA_DONE, "FPGA_DONE");
157 gpio_direction_input(FPGA_DONE);
158
159 /* Be sure that signal are deasserted */
160 gpio_set_value(FPGA_RESET, 1);
161 gpio_set_value(FPGA_PROG, 1);
162
163 return 0;
164 }
165
fpga_post_config_fn(int cookie)166 int fpga_post_config_fn(int cookie)
167 {
168 debug("%s:%d: FPGA post-configuration\n", __func__, __LINE__);
169
170 fpga_reset(true);
171 udelay(100);
172 fpga_reset(false);
173
174 return 0;
175 }
176
177 /* Write program to the FPGA */
fpga_wr_fn(int nassert_write,int flush,int cookie)178 int fpga_wr_fn(int nassert_write, int flush, int cookie)
179 {
180 gpio_set_value(FPGA_DIN, nassert_write);
181
182 return nassert_write;
183 }
184
fpga_clk_fn(int assert_clk,int flush,int cookie)185 int fpga_clk_fn(int assert_clk, int flush, int cookie)
186 {
187 gpio_set_value(FPGA_CCLK, assert_clk);
188
189 return assert_clk;
190 }
191
192 xilinx_spartan3_slave_serial_fns mt_ventoux_fpga_fns = {
193 fpga_pre_config_fn,
194 fpga_pgm_fn,
195 fpga_clk_fn,
196 fpga_init_fn,
197 fpga_done_fn,
198 fpga_wr_fn,
199 fpga_post_config_fn,
200 };
201
202 xilinx_desc fpga = XILINX_XC6SLX4_DESC(slave_serial,
203 (void *)&mt_ventoux_fpga_fns, 0);
204
205 /* Initialize the FPGA */
mt_ventoux_init_fpga(void)206 static void mt_ventoux_init_fpga(void)
207 {
208 fpga_pre_config_fn(0);
209
210 /* Setting CS1 for FPGA access */
211 enable_gpmc_cs_config(gpmc_fpga, &gpmc_cfg->cs[1],
212 FPGA_BASE_ADDR, GPMC_SIZE_128M);
213
214 fpga_init();
215 fpga_add(fpga_xilinx, &fpga);
216 }
217
218 /*
219 * Routine: board_init
220 * Description: Early hardware init.
221 */
board_init(void)222 int board_init(void)
223 {
224 gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
225
226 /* boot param addr */
227 gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
228
229 mt_ventoux_init_fpga();
230
231 /* GPIO_140: speaker #mute */
232 MUX_VAL(CP(MCBSP3_DX), (IEN | PTU | EN | M4))
233 /* GPIO_141: Buzz Hi */
234 MUX_VAL(CP(MCBSP3_DR), (IEN | PTU | EN | M4))
235
236 /* Turning off the buzzer */
237 gpio_request(BUZZER, "BUZZER_MUTE");
238 gpio_request(SPEAKER, "SPEAKER");
239 gpio_direction_output(BUZZER, 0);
240 gpio_direction_output(SPEAKER, 0);
241
242 /* Activate USB power */
243 gpio_request(USB1_PWR, "USB1_PWR");
244 gpio_request(USB2_PWR, "USB2_PWR");
245 gpio_direction_output(USB1_PWR, 1);
246 gpio_direction_output(USB2_PWR, 1);
247
248 return 0;
249 }
250
251 #ifndef CONFIG_SPL_BUILD
misc_init_r(void)252 int misc_init_r(void)
253 {
254 char *eth_addr;
255 struct tam3517_module_info info;
256 int ret;
257
258 TAM3517_READ_EEPROM(&info, ret);
259 omap_die_id_display();
260
261 if (ret)
262 return 0;
263 eth_addr = env_get("ethaddr");
264 if (!eth_addr)
265 TAM3517_READ_MAC_FROM_EEPROM(&info);
266
267 TAM3517_PRINT_SOM_INFO(&info);
268 return 0;
269 }
270 #endif
271
272 /*
273 * Routine: set_muxconf_regs
274 * Description: Setting up the configuration Mux registers specific to the
275 * hardware. Many pins need to be moved from protect to primary
276 * mode.
277 */
set_muxconf_regs(void)278 void set_muxconf_regs(void)
279 {
280 MUX_MT_VENTOUX();
281 }
282
283 /*
284 * Initializes on-chip ethernet controllers.
285 * to override, implement board_eth_init()
286 */
board_eth_init(bd_t * bis)287 int board_eth_init(bd_t *bis)
288 {
289 davinci_emac_initialize();
290 return 0;
291 }
292
293 #if defined(CONFIG_MMC_OMAP_HS) && \
294 !defined(CONFIG_SPL_BUILD)
board_mmc_init(bd_t * bis)295 int board_mmc_init(bd_t *bis)
296 {
297 return omap_mmc_init(0, 0, 0, -1, -1);
298 }
299 #endif
300
301 #if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD)
board_video_init(void)302 int board_video_init(void)
303 {
304 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
305 struct panel_config *panel = &lcd_cfg[0];
306 char *s;
307 u32 index = 0;
308
309 void *fb;
310
311 fb = (void *)0x88000000;
312
313 s = env_get("panel");
314 if (s) {
315 index = simple_strtoul(s, NULL, 10);
316 if (index < ARRAY_SIZE(lcd_cfg))
317 panel = &lcd_cfg[index];
318 else
319 return 0;
320 }
321
322 panel->frame_buffer = fb;
323 printf("Panel: %dx%d\n", panel_resolution[index].xres,
324 panel_resolution[index].yres);
325 panel->lcd_size = (panel_resolution[index].yres - 1) << 16 |
326 (panel_resolution[index].xres - 1);
327
328 gpio_request(LCD_PWR, "LCD Power");
329 gpio_request(LCD_PON_PIN, "LCD Pon");
330 gpio_direction_output(LCD_PWR, 0);
331 gpio_direction_output(LCD_PON_PIN, 1);
332
333
334 setbits_le32(&prcm_base->fclken_dss, FCK_DSS_ON);
335 setbits_le32(&prcm_base->iclken_dss, ICK_DSS_ON);
336
337 omap3_dss_panel_config(panel);
338 omap3_dss_enable();
339
340 return 0;
341 }
342 #endif
343