1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (c) 2011 The Chromium OS Authors.
4 * (C) Copyright 2011 NVIDIA Corporation <www.nvidia.com>
5 * (C) Copyright 2006 Detlev Zundel, dzu@denx.de
6 * (C) Copyright 2006 DENX Software Engineering
7 */
8
9 #include <common.h>
10 #include <asm/io.h>
11 #include <memalign.h>
12 #include <nand.h>
13 #include <asm/arch/clock.h>
14 #include <asm/arch/funcmux.h>
15 #include <asm/arch-tegra/clk_rst.h>
16 #include <linux/errno.h>
17 #include <asm/gpio.h>
18 #include <fdtdec.h>
19 #include <bouncebuf.h>
20 #include <dm.h>
21 #include "tegra_nand.h"
22
23 DECLARE_GLOBAL_DATA_PTR;
24
25 #define NAND_CMD_TIMEOUT_MS 10
26
27 #define SKIPPED_SPARE_BYTES 4
28
29 /* ECC bytes to be generated for tag data */
30 #define TAG_ECC_BYTES 4
31
32 static const struct udevice_id tegra_nand_dt_ids[] = {
33 {
34 .compatible = "nvidia,tegra20-nand",
35 },
36 { /* sentinel */ }
37 };
38
39 /* 64 byte oob block info for large page (== 2KB) device
40 *
41 * OOB flash layout for Tegra with Reed-Solomon 4 symbol correct ECC:
42 * Skipped bytes(4)
43 * Main area Ecc(36)
44 * Tag data(20)
45 * Tag data Ecc(4)
46 *
47 * Yaffs2 will use 16 tag bytes.
48 */
49 static struct nand_ecclayout eccoob = {
50 .eccbytes = 36,
51 .eccpos = {
52 4, 5, 6, 7, 8, 9, 10, 11, 12,
53 13, 14, 15, 16, 17, 18, 19, 20, 21,
54 22, 23, 24, 25, 26, 27, 28, 29, 30,
55 31, 32, 33, 34, 35, 36, 37, 38, 39,
56 },
57 .oobavail = 20,
58 .oobfree = {
59 {
60 .offset = 40,
61 .length = 20,
62 },
63 }
64 };
65
66 enum {
67 ECC_OK,
68 ECC_TAG_ERROR = 1 << 0,
69 ECC_DATA_ERROR = 1 << 1
70 };
71
72 /* Timing parameters */
73 enum {
74 FDT_NAND_MAX_TRP_TREA,
75 FDT_NAND_TWB,
76 FDT_NAND_MAX_TCR_TAR_TRR,
77 FDT_NAND_TWHR,
78 FDT_NAND_MAX_TCS_TCH_TALS_TALH,
79 FDT_NAND_TWH,
80 FDT_NAND_TWP,
81 FDT_NAND_TRH,
82 FDT_NAND_TADL,
83
84 FDT_NAND_TIMING_COUNT
85 };
86
87 /* Information about an attached NAND chip */
88 struct fdt_nand {
89 struct nand_ctlr *reg;
90 int enabled; /* 1 to enable, 0 to disable */
91 struct gpio_desc wp_gpio; /* write-protect GPIO */
92 s32 width; /* bit width, normally 8 */
93 u32 timing[FDT_NAND_TIMING_COUNT];
94 };
95
96 struct nand_drv {
97 struct nand_ctlr *reg;
98 struct fdt_nand config;
99 };
100
101 struct tegra_nand_info {
102 struct udevice *dev;
103 struct nand_drv nand_ctrl;
104 struct nand_chip nand_chip;
105 };
106
107 /**
108 * Wait for command completion
109 *
110 * @param reg nand_ctlr structure
111 * @return
112 * 1 - Command completed
113 * 0 - Timeout
114 */
nand_waitfor_cmd_completion(struct nand_ctlr * reg)115 static int nand_waitfor_cmd_completion(struct nand_ctlr *reg)
116 {
117 u32 reg_val;
118 int running;
119 int i;
120
121 for (i = 0; i < NAND_CMD_TIMEOUT_MS * 1000; i++) {
122 if ((readl(®->command) & CMD_GO) ||
123 !(readl(®->status) & STATUS_RBSY0) ||
124 !(readl(®->isr) & ISR_IS_CMD_DONE)) {
125 udelay(1);
126 continue;
127 }
128 reg_val = readl(®->dma_mst_ctrl);
129 /*
130 * If DMA_MST_CTRL_EN_A_ENABLE or DMA_MST_CTRL_EN_B_ENABLE
131 * is set, that means DMA engine is running.
132 *
133 * Then we have to wait until DMA_MST_CTRL_IS_DMA_DONE
134 * is cleared, indicating DMA transfer completion.
135 */
136 running = reg_val & (DMA_MST_CTRL_EN_A_ENABLE |
137 DMA_MST_CTRL_EN_B_ENABLE);
138 if (!running || (reg_val & DMA_MST_CTRL_IS_DMA_DONE))
139 return 1;
140 udelay(1);
141 }
142 return 0;
143 }
144
145 /**
146 * Read one byte from the chip
147 *
148 * @param mtd MTD device structure
149 * @return data byte
150 *
151 * Read function for 8bit bus-width
152 */
read_byte(struct mtd_info * mtd)153 static uint8_t read_byte(struct mtd_info *mtd)
154 {
155 struct nand_chip *chip = mtd_to_nand(mtd);
156 struct nand_drv *info;
157
158 info = (struct nand_drv *)nand_get_controller_data(chip);
159
160 writel(CMD_GO | CMD_PIO | CMD_RX | CMD_CE0 | CMD_A_VALID,
161 &info->reg->command);
162 if (!nand_waitfor_cmd_completion(info->reg))
163 printf("Command timeout\n");
164
165 return (uint8_t)readl(&info->reg->resp);
166 }
167
168 /**
169 * Read len bytes from the chip into a buffer
170 *
171 * @param mtd MTD device structure
172 * @param buf buffer to store data to
173 * @param len number of bytes to read
174 *
175 * Read function for 8bit bus-width
176 */
read_buf(struct mtd_info * mtd,uint8_t * buf,int len)177 static void read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
178 {
179 int i, s;
180 unsigned int reg;
181 struct nand_chip *chip = mtd_to_nand(mtd);
182 struct nand_drv *info = (struct nand_drv *)nand_get_controller_data(chip);
183
184 for (i = 0; i < len; i += 4) {
185 s = (len - i) > 4 ? 4 : len - i;
186 writel(CMD_PIO | CMD_RX | CMD_A_VALID | CMD_CE0 |
187 ((s - 1) << CMD_TRANS_SIZE_SHIFT) | CMD_GO,
188 &info->reg->command);
189 if (!nand_waitfor_cmd_completion(info->reg))
190 puts("Command timeout during read_buf\n");
191 reg = readl(&info->reg->resp);
192 memcpy(buf + i, ®, s);
193 }
194 }
195
196 /**
197 * Check NAND status to see if it is ready or not
198 *
199 * @param mtd MTD device structure
200 * @return
201 * 1 - ready
202 * 0 - not ready
203 */
nand_dev_ready(struct mtd_info * mtd)204 static int nand_dev_ready(struct mtd_info *mtd)
205 {
206 struct nand_chip *chip = mtd_to_nand(mtd);
207 int reg_val;
208 struct nand_drv *info;
209
210 info = (struct nand_drv *)nand_get_controller_data(chip);
211
212 reg_val = readl(&info->reg->status);
213 if (reg_val & STATUS_RBSY0)
214 return 1;
215 else
216 return 0;
217 }
218
219 /* Dummy implementation: we don't support multiple chips */
nand_select_chip(struct mtd_info * mtd,int chipnr)220 static void nand_select_chip(struct mtd_info *mtd, int chipnr)
221 {
222 switch (chipnr) {
223 case -1:
224 case 0:
225 break;
226
227 default:
228 BUG();
229 }
230 }
231
232 /**
233 * Clear all interrupt status bits
234 *
235 * @param reg nand_ctlr structure
236 */
nand_clear_interrupt_status(struct nand_ctlr * reg)237 static void nand_clear_interrupt_status(struct nand_ctlr *reg)
238 {
239 u32 reg_val;
240
241 /* Clear interrupt status */
242 reg_val = readl(®->isr);
243 writel(reg_val, ®->isr);
244 }
245
246 /**
247 * Send command to NAND device
248 *
249 * @param mtd MTD device structure
250 * @param command the command to be sent
251 * @param column the column address for this command, -1 if none
252 * @param page_addr the page address for this command, -1 if none
253 */
nand_command(struct mtd_info * mtd,unsigned int command,int column,int page_addr)254 static void nand_command(struct mtd_info *mtd, unsigned int command,
255 int column, int page_addr)
256 {
257 struct nand_chip *chip = mtd_to_nand(mtd);
258 struct nand_drv *info;
259
260 info = (struct nand_drv *)nand_get_controller_data(chip);
261
262 /*
263 * Write out the command to the device.
264 *
265 * Only command NAND_CMD_RESET or NAND_CMD_READID will come
266 * here before mtd->writesize is initialized.
267 */
268
269 /* Emulate NAND_CMD_READOOB */
270 if (command == NAND_CMD_READOOB) {
271 assert(mtd->writesize != 0);
272 column += mtd->writesize;
273 command = NAND_CMD_READ0;
274 }
275
276 /* Adjust columns for 16 bit bus-width */
277 if (column != -1 && (chip->options & NAND_BUSWIDTH_16))
278 column >>= 1;
279
280 nand_clear_interrupt_status(info->reg);
281
282 /* Stop DMA engine, clear DMA completion status */
283 writel(DMA_MST_CTRL_EN_A_DISABLE
284 | DMA_MST_CTRL_EN_B_DISABLE
285 | DMA_MST_CTRL_IS_DMA_DONE,
286 &info->reg->dma_mst_ctrl);
287
288 /*
289 * Program and erase have their own busy handlers
290 * status and sequential in needs no delay
291 */
292 switch (command) {
293 case NAND_CMD_READID:
294 writel(NAND_CMD_READID, &info->reg->cmd_reg1);
295 writel(column & 0xFF, &info->reg->addr_reg1);
296 writel(CMD_GO | CMD_CLE | CMD_ALE | CMD_CE0,
297 &info->reg->command);
298 break;
299 case NAND_CMD_PARAM:
300 writel(NAND_CMD_PARAM, &info->reg->cmd_reg1);
301 writel(column & 0xFF, &info->reg->addr_reg1);
302 writel(CMD_GO | CMD_CLE | CMD_ALE | CMD_CE0,
303 &info->reg->command);
304 break;
305 case NAND_CMD_READ0:
306 writel(NAND_CMD_READ0, &info->reg->cmd_reg1);
307 writel(NAND_CMD_READSTART, &info->reg->cmd_reg2);
308 writel((page_addr << 16) | (column & 0xFFFF),
309 &info->reg->addr_reg1);
310 writel(page_addr >> 16, &info->reg->addr_reg2);
311 return;
312 case NAND_CMD_SEQIN:
313 writel(NAND_CMD_SEQIN, &info->reg->cmd_reg1);
314 writel(NAND_CMD_PAGEPROG, &info->reg->cmd_reg2);
315 writel((page_addr << 16) | (column & 0xFFFF),
316 &info->reg->addr_reg1);
317 writel(page_addr >> 16,
318 &info->reg->addr_reg2);
319 return;
320 case NAND_CMD_PAGEPROG:
321 return;
322 case NAND_CMD_ERASE1:
323 writel(NAND_CMD_ERASE1, &info->reg->cmd_reg1);
324 writel(NAND_CMD_ERASE2, &info->reg->cmd_reg2);
325 writel(page_addr, &info->reg->addr_reg1);
326 writel(CMD_GO | CMD_CLE | CMD_ALE |
327 CMD_SEC_CMD | CMD_CE0 | CMD_ALE_BYTES3,
328 &info->reg->command);
329 break;
330 case NAND_CMD_ERASE2:
331 return;
332 case NAND_CMD_STATUS:
333 writel(NAND_CMD_STATUS, &info->reg->cmd_reg1);
334 writel(CMD_GO | CMD_CLE | CMD_PIO | CMD_RX
335 | ((1 - 0) << CMD_TRANS_SIZE_SHIFT)
336 | CMD_CE0,
337 &info->reg->command);
338 break;
339 case NAND_CMD_RESET:
340 writel(NAND_CMD_RESET, &info->reg->cmd_reg1);
341 writel(CMD_GO | CMD_CLE | CMD_CE0,
342 &info->reg->command);
343 break;
344 case NAND_CMD_RNDOUT:
345 default:
346 printf("%s: Unsupported command %d\n", __func__, command);
347 return;
348 }
349 if (!nand_waitfor_cmd_completion(info->reg))
350 printf("Command 0x%02X timeout\n", command);
351 }
352
353 /**
354 * Check whether the pointed buffer are all 0xff (blank).
355 *
356 * @param buf data buffer for blank check
357 * @param len length of the buffer in byte
358 * @return
359 * 1 - blank
360 * 0 - non-blank
361 */
blank_check(u8 * buf,int len)362 static int blank_check(u8 *buf, int len)
363 {
364 int i;
365
366 for (i = 0; i < len; i++)
367 if (buf[i] != 0xFF)
368 return 0;
369 return 1;
370 }
371
372 /**
373 * After a DMA transfer for read, we call this function to see whether there
374 * is any uncorrectable error on the pointed data buffer or oob buffer.
375 *
376 * @param reg nand_ctlr structure
377 * @param databuf data buffer
378 * @param a_len data buffer length
379 * @param oobbuf oob buffer
380 * @param b_len oob buffer length
381 * @return
382 * ECC_OK - no ECC error or correctable ECC error
383 * ECC_TAG_ERROR - uncorrectable tag ECC error
384 * ECC_DATA_ERROR - uncorrectable data ECC error
385 * ECC_DATA_ERROR + ECC_TAG_ERROR - uncorrectable data+tag ECC error
386 */
check_ecc_error(struct nand_ctlr * reg,u8 * databuf,int a_len,u8 * oobbuf,int b_len)387 static int check_ecc_error(struct nand_ctlr *reg, u8 *databuf,
388 int a_len, u8 *oobbuf, int b_len)
389 {
390 int return_val = ECC_OK;
391 u32 reg_val;
392
393 if (!(readl(®->isr) & ISR_IS_ECC_ERR))
394 return ECC_OK;
395
396 /*
397 * Area A is used for the data block (databuf). Area B is used for
398 * the spare block (oobbuf)
399 */
400 reg_val = readl(®->dec_status);
401 if ((reg_val & DEC_STATUS_A_ECC_FAIL) && databuf) {
402 reg_val = readl(®->bch_dec_status_buf);
403 /*
404 * If uncorrectable error occurs on data area, then see whether
405 * they are all FF. If all are FF, it's a blank page.
406 * Not error.
407 */
408 if ((reg_val & BCH_DEC_STATUS_FAIL_SEC_FLAG_MASK) &&
409 !blank_check(databuf, a_len))
410 return_val |= ECC_DATA_ERROR;
411 }
412
413 if ((reg_val & DEC_STATUS_B_ECC_FAIL) && oobbuf) {
414 reg_val = readl(®->bch_dec_status_buf);
415 /*
416 * If uncorrectable error occurs on tag area, then see whether
417 * they are all FF. If all are FF, it's a blank page.
418 * Not error.
419 */
420 if ((reg_val & BCH_DEC_STATUS_FAIL_TAG_MASK) &&
421 !blank_check(oobbuf, b_len))
422 return_val |= ECC_TAG_ERROR;
423 }
424
425 return return_val;
426 }
427
428 /**
429 * Set GO bit to send command to device
430 *
431 * @param reg nand_ctlr structure
432 */
start_command(struct nand_ctlr * reg)433 static void start_command(struct nand_ctlr *reg)
434 {
435 u32 reg_val;
436
437 reg_val = readl(®->command);
438 reg_val |= CMD_GO;
439 writel(reg_val, ®->command);
440 }
441
442 /**
443 * Clear command GO bit, DMA GO bit, and DMA completion status
444 *
445 * @param reg nand_ctlr structure
446 */
stop_command(struct nand_ctlr * reg)447 static void stop_command(struct nand_ctlr *reg)
448 {
449 /* Stop command */
450 writel(0, ®->command);
451
452 /* Stop DMA engine and clear DMA completion status */
453 writel(DMA_MST_CTRL_GO_DISABLE
454 | DMA_MST_CTRL_IS_DMA_DONE,
455 ®->dma_mst_ctrl);
456 }
457
458 /**
459 * Set up NAND bus width and page size
460 *
461 * @param info nand_info structure
462 * @param *reg_val address of reg_val
463 * @return 0 if ok, -1 on error
464 */
set_bus_width_page_size(struct mtd_info * our_mtd,struct fdt_nand * config,u32 * reg_val)465 static int set_bus_width_page_size(struct mtd_info *our_mtd,
466 struct fdt_nand *config, u32 *reg_val)
467 {
468 if (config->width == 8)
469 *reg_val = CFG_BUS_WIDTH_8BIT;
470 else if (config->width == 16)
471 *reg_val = CFG_BUS_WIDTH_16BIT;
472 else {
473 debug("%s: Unsupported bus width %d\n", __func__,
474 config->width);
475 return -1;
476 }
477
478 if (our_mtd->writesize == 512)
479 *reg_val |= CFG_PAGE_SIZE_512;
480 else if (our_mtd->writesize == 2048)
481 *reg_val |= CFG_PAGE_SIZE_2048;
482 else if (our_mtd->writesize == 4096)
483 *reg_val |= CFG_PAGE_SIZE_4096;
484 else {
485 debug("%s: Unsupported page size %d\n", __func__,
486 our_mtd->writesize);
487 return -1;
488 }
489
490 return 0;
491 }
492
493 /**
494 * Page read/write function
495 *
496 * @param mtd mtd info structure
497 * @param chip nand chip info structure
498 * @param buf data buffer
499 * @param page page number
500 * @param with_ecc 1 to enable ECC, 0 to disable ECC
501 * @param is_writing 0 for read, 1 for write
502 * @return 0 when successfully completed
503 * -EIO when command timeout
504 */
nand_rw_page(struct mtd_info * mtd,struct nand_chip * chip,uint8_t * buf,int page,int with_ecc,int is_writing)505 static int nand_rw_page(struct mtd_info *mtd, struct nand_chip *chip,
506 uint8_t *buf, int page, int with_ecc, int is_writing)
507 {
508 u32 reg_val;
509 int tag_size;
510 struct nand_oobfree *free = chip->ecc.layout->oobfree;
511 /* 4*128=512 (byte) is the value that our HW can support. */
512 ALLOC_CACHE_ALIGN_BUFFER(u32, tag_buf, 128);
513 char *tag_ptr;
514 struct nand_drv *info;
515 struct fdt_nand *config;
516 unsigned int bbflags;
517 struct bounce_buffer bbstate, bbstate_oob;
518
519 if ((uintptr_t)buf & 0x03) {
520 printf("buf %p has to be 4-byte aligned\n", buf);
521 return -EINVAL;
522 }
523
524 info = (struct nand_drv *)nand_get_controller_data(chip);
525 config = &info->config;
526 if (set_bus_width_page_size(mtd, config, ®_val))
527 return -EINVAL;
528
529 /* Need to be 4-byte aligned */
530 tag_ptr = (char *)tag_buf;
531
532 stop_command(info->reg);
533
534 if (is_writing)
535 bbflags = GEN_BB_READ;
536 else
537 bbflags = GEN_BB_WRITE;
538
539 bounce_buffer_start(&bbstate, (void *)buf, 1 << chip->page_shift,
540 bbflags);
541 writel((1 << chip->page_shift) - 1, &info->reg->dma_cfg_a);
542 writel(virt_to_phys(bbstate.bounce_buffer), &info->reg->data_block_ptr);
543
544 /* Set ECC selection, configure ECC settings */
545 if (with_ecc) {
546 if (is_writing)
547 memcpy(tag_ptr, chip->oob_poi + free->offset,
548 chip->ecc.layout->oobavail + TAG_ECC_BYTES);
549 tag_size = chip->ecc.layout->oobavail + TAG_ECC_BYTES;
550 reg_val |= (CFG_SKIP_SPARE_SEL_4
551 | CFG_SKIP_SPARE_ENABLE
552 | CFG_HW_ECC_CORRECTION_ENABLE
553 | CFG_ECC_EN_TAG_DISABLE
554 | CFG_HW_ECC_SEL_RS
555 | CFG_HW_ECC_ENABLE
556 | CFG_TVAL4
557 | (tag_size - 1));
558
559 if (!is_writing)
560 tag_size += SKIPPED_SPARE_BYTES;
561 bounce_buffer_start(&bbstate_oob, (void *)tag_ptr, tag_size,
562 bbflags);
563 } else {
564 tag_size = mtd->oobsize;
565 reg_val |= (CFG_SKIP_SPARE_DISABLE
566 | CFG_HW_ECC_CORRECTION_DISABLE
567 | CFG_ECC_EN_TAG_DISABLE
568 | CFG_HW_ECC_DISABLE
569 | (tag_size - 1));
570 bounce_buffer_start(&bbstate_oob, (void *)chip->oob_poi,
571 tag_size, bbflags);
572 }
573 writel(reg_val, &info->reg->config);
574 writel(virt_to_phys(bbstate_oob.bounce_buffer), &info->reg->tag_ptr);
575 writel(BCH_CONFIG_BCH_ECC_DISABLE, &info->reg->bch_config);
576 writel(tag_size - 1, &info->reg->dma_cfg_b);
577
578 nand_clear_interrupt_status(info->reg);
579
580 reg_val = CMD_CLE | CMD_ALE
581 | CMD_SEC_CMD
582 | (CMD_ALE_BYTES5 << CMD_ALE_BYTE_SIZE_SHIFT)
583 | CMD_A_VALID
584 | CMD_B_VALID
585 | (CMD_TRANS_SIZE_PAGE << CMD_TRANS_SIZE_SHIFT)
586 | CMD_CE0;
587 if (!is_writing)
588 reg_val |= (CMD_AFT_DAT_DISABLE | CMD_RX);
589 else
590 reg_val |= (CMD_AFT_DAT_ENABLE | CMD_TX);
591 writel(reg_val, &info->reg->command);
592
593 /* Setup DMA engine */
594 reg_val = DMA_MST_CTRL_GO_ENABLE
595 | DMA_MST_CTRL_BURST_8WORDS
596 | DMA_MST_CTRL_EN_A_ENABLE
597 | DMA_MST_CTRL_EN_B_ENABLE;
598
599 if (!is_writing)
600 reg_val |= DMA_MST_CTRL_DIR_READ;
601 else
602 reg_val |= DMA_MST_CTRL_DIR_WRITE;
603
604 writel(reg_val, &info->reg->dma_mst_ctrl);
605
606 start_command(info->reg);
607
608 if (!nand_waitfor_cmd_completion(info->reg)) {
609 if (!is_writing)
610 printf("Read Page 0x%X timeout ", page);
611 else
612 printf("Write Page 0x%X timeout ", page);
613 if (with_ecc)
614 printf("with ECC");
615 else
616 printf("without ECC");
617 printf("\n");
618 return -EIO;
619 }
620
621 bounce_buffer_stop(&bbstate_oob);
622 bounce_buffer_stop(&bbstate);
623
624 if (with_ecc && !is_writing) {
625 memcpy(chip->oob_poi, tag_ptr,
626 SKIPPED_SPARE_BYTES);
627 memcpy(chip->oob_poi + free->offset,
628 tag_ptr + SKIPPED_SPARE_BYTES,
629 chip->ecc.layout->oobavail);
630 reg_val = (u32)check_ecc_error(info->reg, (u8 *)buf,
631 1 << chip->page_shift,
632 (u8 *)(tag_ptr + SKIPPED_SPARE_BYTES),
633 chip->ecc.layout->oobavail);
634 if (reg_val & ECC_TAG_ERROR)
635 printf("Read Page 0x%X tag ECC error\n", page);
636 if (reg_val & ECC_DATA_ERROR)
637 printf("Read Page 0x%X data ECC error\n",
638 page);
639 if (reg_val & (ECC_DATA_ERROR | ECC_TAG_ERROR))
640 return -EIO;
641 }
642 return 0;
643 }
644
645 /**
646 * Hardware ecc based page read function
647 *
648 * @param mtd mtd info structure
649 * @param chip nand chip info structure
650 * @param buf buffer to store read data
651 * @param page page number to read
652 * @return 0 when successfully completed
653 * -EIO when command timeout
654 */
nand_read_page_hwecc(struct mtd_info * mtd,struct nand_chip * chip,uint8_t * buf,int oob_required,int page)655 static int nand_read_page_hwecc(struct mtd_info *mtd,
656 struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
657 {
658 return nand_rw_page(mtd, chip, buf, page, 1, 0);
659 }
660
661 /**
662 * Hardware ecc based page write function
663 *
664 * @param mtd mtd info structure
665 * @param chip nand chip info structure
666 * @param buf data buffer
667 */
nand_write_page_hwecc(struct mtd_info * mtd,struct nand_chip * chip,const uint8_t * buf,int oob_required,int page)668 static int nand_write_page_hwecc(struct mtd_info *mtd,
669 struct nand_chip *chip, const uint8_t *buf, int oob_required,
670 int page)
671 {
672 nand_rw_page(mtd, chip, (uint8_t *)buf, page, 1, 1);
673 return 0;
674 }
675
676
677 /**
678 * Read raw page data without ecc
679 *
680 * @param mtd mtd info structure
681 * @param chip nand chip info structure
682 * @param buf buffer to store read data
683 * @param page page number to read
684 * @return 0 when successfully completed
685 * -EINVAL when chip->oob_poi is not double-word aligned
686 * -EIO when command timeout
687 */
nand_read_page_raw(struct mtd_info * mtd,struct nand_chip * chip,uint8_t * buf,int oob_required,int page)688 static int nand_read_page_raw(struct mtd_info *mtd,
689 struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
690 {
691 return nand_rw_page(mtd, chip, buf, page, 0, 0);
692 }
693
694 /**
695 * Raw page write function
696 *
697 * @param mtd mtd info structure
698 * @param chip nand chip info structure
699 * @param buf data buffer
700 */
nand_write_page_raw(struct mtd_info * mtd,struct nand_chip * chip,const uint8_t * buf,int oob_required,int page)701 static int nand_write_page_raw(struct mtd_info *mtd,
702 struct nand_chip *chip, const uint8_t *buf,
703 int oob_required, int page)
704 {
705 nand_rw_page(mtd, chip, (uint8_t *)buf, page, 0, 1);
706 return 0;
707 }
708
709 /**
710 * OOB data read/write function
711 *
712 * @param mtd mtd info structure
713 * @param chip nand chip info structure
714 * @param page page number to read
715 * @param with_ecc 1 to enable ECC, 0 to disable ECC
716 * @param is_writing 0 for read, 1 for write
717 * @return 0 when successfully completed
718 * -EINVAL when chip->oob_poi is not double-word aligned
719 * -EIO when command timeout
720 */
nand_rw_oob(struct mtd_info * mtd,struct nand_chip * chip,int page,int with_ecc,int is_writing)721 static int nand_rw_oob(struct mtd_info *mtd, struct nand_chip *chip,
722 int page, int with_ecc, int is_writing)
723 {
724 u32 reg_val;
725 int tag_size;
726 struct nand_oobfree *free = chip->ecc.layout->oobfree;
727 struct nand_drv *info;
728 unsigned int bbflags;
729 struct bounce_buffer bbstate_oob;
730
731 if (((int)chip->oob_poi) & 0x03)
732 return -EINVAL;
733 info = (struct nand_drv *)nand_get_controller_data(chip);
734 if (set_bus_width_page_size(mtd, &info->config, ®_val))
735 return -EINVAL;
736
737 stop_command(info->reg);
738
739 /* Set ECC selection */
740 tag_size = mtd->oobsize;
741 if (with_ecc)
742 reg_val |= CFG_ECC_EN_TAG_ENABLE;
743 else
744 reg_val |= (CFG_ECC_EN_TAG_DISABLE);
745
746 reg_val |= ((tag_size - 1) |
747 CFG_SKIP_SPARE_DISABLE |
748 CFG_HW_ECC_CORRECTION_DISABLE |
749 CFG_HW_ECC_DISABLE);
750 writel(reg_val, &info->reg->config);
751
752 if (is_writing && with_ecc)
753 tag_size -= TAG_ECC_BYTES;
754
755 if (is_writing)
756 bbflags = GEN_BB_READ;
757 else
758 bbflags = GEN_BB_WRITE;
759
760 bounce_buffer_start(&bbstate_oob, (void *)chip->oob_poi, tag_size,
761 bbflags);
762 writel(virt_to_phys(bbstate_oob.bounce_buffer), &info->reg->tag_ptr);
763
764 writel(BCH_CONFIG_BCH_ECC_DISABLE, &info->reg->bch_config);
765
766 writel(tag_size - 1, &info->reg->dma_cfg_b);
767
768 nand_clear_interrupt_status(info->reg);
769
770 reg_val = CMD_CLE | CMD_ALE
771 | CMD_SEC_CMD
772 | (CMD_ALE_BYTES5 << CMD_ALE_BYTE_SIZE_SHIFT)
773 | CMD_B_VALID
774 | CMD_CE0;
775 if (!is_writing)
776 reg_val |= (CMD_AFT_DAT_DISABLE | CMD_RX);
777 else
778 reg_val |= (CMD_AFT_DAT_ENABLE | CMD_TX);
779 writel(reg_val, &info->reg->command);
780
781 /* Setup DMA engine */
782 reg_val = DMA_MST_CTRL_GO_ENABLE
783 | DMA_MST_CTRL_BURST_8WORDS
784 | DMA_MST_CTRL_EN_B_ENABLE;
785 if (!is_writing)
786 reg_val |= DMA_MST_CTRL_DIR_READ;
787 else
788 reg_val |= DMA_MST_CTRL_DIR_WRITE;
789
790 writel(reg_val, &info->reg->dma_mst_ctrl);
791
792 start_command(info->reg);
793
794 if (!nand_waitfor_cmd_completion(info->reg)) {
795 if (!is_writing)
796 printf("Read OOB of Page 0x%X timeout\n", page);
797 else
798 printf("Write OOB of Page 0x%X timeout\n", page);
799 return -EIO;
800 }
801
802 bounce_buffer_stop(&bbstate_oob);
803
804 if (with_ecc && !is_writing) {
805 reg_val = (u32)check_ecc_error(info->reg, 0, 0,
806 (u8 *)(chip->oob_poi + free->offset),
807 chip->ecc.layout->oobavail);
808 if (reg_val & ECC_TAG_ERROR)
809 printf("Read OOB of Page 0x%X tag ECC error\n", page);
810 }
811 return 0;
812 }
813
814 /**
815 * OOB data read function
816 *
817 * @param mtd mtd info structure
818 * @param chip nand chip info structure
819 * @param page page number to read
820 */
nand_read_oob(struct mtd_info * mtd,struct nand_chip * chip,int page)821 static int nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
822 int page)
823 {
824 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
825 nand_rw_oob(mtd, chip, page, 0, 0);
826 return 0;
827 }
828
829 /**
830 * OOB data write function
831 *
832 * @param mtd mtd info structure
833 * @param chip nand chip info structure
834 * @param page page number to write
835 * @return 0 when successfully completed
836 * -EINVAL when chip->oob_poi is not double-word aligned
837 * -EIO when command timeout
838 */
nand_write_oob(struct mtd_info * mtd,struct nand_chip * chip,int page)839 static int nand_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
840 int page)
841 {
842 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
843
844 return nand_rw_oob(mtd, chip, page, 0, 1);
845 }
846
847 /**
848 * Set up NAND memory timings according to the provided parameters
849 *
850 * @param timing Timing parameters
851 * @param reg NAND controller register address
852 */
setup_timing(unsigned timing[FDT_NAND_TIMING_COUNT],struct nand_ctlr * reg)853 static void setup_timing(unsigned timing[FDT_NAND_TIMING_COUNT],
854 struct nand_ctlr *reg)
855 {
856 u32 reg_val, clk_rate, clk_period, time_val;
857
858 clk_rate = (u32)clock_get_periph_rate(PERIPH_ID_NDFLASH,
859 CLOCK_ID_PERIPH) / 1000000;
860 clk_period = 1000 / clk_rate;
861 reg_val = ((timing[FDT_NAND_MAX_TRP_TREA] / clk_period) <<
862 TIMING_TRP_RESP_CNT_SHIFT) & TIMING_TRP_RESP_CNT_MASK;
863 reg_val |= ((timing[FDT_NAND_TWB] / clk_period) <<
864 TIMING_TWB_CNT_SHIFT) & TIMING_TWB_CNT_MASK;
865 time_val = timing[FDT_NAND_MAX_TCR_TAR_TRR] / clk_period;
866 if (time_val > 2)
867 reg_val |= ((time_val - 2) << TIMING_TCR_TAR_TRR_CNT_SHIFT) &
868 TIMING_TCR_TAR_TRR_CNT_MASK;
869 reg_val |= ((timing[FDT_NAND_TWHR] / clk_period) <<
870 TIMING_TWHR_CNT_SHIFT) & TIMING_TWHR_CNT_MASK;
871 time_val = timing[FDT_NAND_MAX_TCS_TCH_TALS_TALH] / clk_period;
872 if (time_val > 1)
873 reg_val |= ((time_val - 1) << TIMING_TCS_CNT_SHIFT) &
874 TIMING_TCS_CNT_MASK;
875 reg_val |= ((timing[FDT_NAND_TWH] / clk_period) <<
876 TIMING_TWH_CNT_SHIFT) & TIMING_TWH_CNT_MASK;
877 reg_val |= ((timing[FDT_NAND_TWP] / clk_period) <<
878 TIMING_TWP_CNT_SHIFT) & TIMING_TWP_CNT_MASK;
879 reg_val |= ((timing[FDT_NAND_TRH] / clk_period) <<
880 TIMING_TRH_CNT_SHIFT) & TIMING_TRH_CNT_MASK;
881 reg_val |= ((timing[FDT_NAND_MAX_TRP_TREA] / clk_period) <<
882 TIMING_TRP_CNT_SHIFT) & TIMING_TRP_CNT_MASK;
883 writel(reg_val, ®->timing);
884
885 reg_val = 0;
886 time_val = timing[FDT_NAND_TADL] / clk_period;
887 if (time_val > 2)
888 reg_val = (time_val - 2) & TIMING2_TADL_CNT_MASK;
889 writel(reg_val, ®->timing2);
890 }
891
892 /**
893 * Decode NAND parameters from the device tree
894 *
895 * @param dev Driver model device
896 * @param config Device tree NAND configuration
897 * @return 0 if ok, -ve on error (FDT_ERR_...)
898 */
fdt_decode_nand(struct udevice * dev,struct fdt_nand * config)899 static int fdt_decode_nand(struct udevice *dev, struct fdt_nand *config)
900 {
901 int err;
902
903 config->reg = (struct nand_ctlr *)dev_read_addr(dev);
904 config->enabled = dev_read_enabled(dev);
905 config->width = dev_read_u32_default(dev, "nvidia,nand-width", 8);
906 err = gpio_request_by_name(dev, "nvidia,wp-gpios", 0, &config->wp_gpio,
907 GPIOD_IS_OUT);
908 if (err)
909 return err;
910 err = dev_read_u32_array(dev, "nvidia,timing", config->timing,
911 FDT_NAND_TIMING_COUNT);
912 if (err < 0)
913 return err;
914
915 return 0;
916 }
917
tegra_probe(struct udevice * dev)918 static int tegra_probe(struct udevice *dev)
919 {
920 struct tegra_nand_info *tegra = dev_get_priv(dev);
921 struct nand_chip *nand = &tegra->nand_chip;
922 struct nand_drv *info = &tegra->nand_ctrl;
923 struct fdt_nand *config = &info->config;
924 struct mtd_info *our_mtd;
925 int ret;
926
927 if (fdt_decode_nand(dev, config)) {
928 printf("Could not decode nand-flash in device tree\n");
929 return -1;
930 }
931 if (!config->enabled)
932 return -1;
933 info->reg = config->reg;
934 nand->ecc.mode = NAND_ECC_HW;
935 nand->ecc.layout = &eccoob;
936
937 nand->options = LP_OPTIONS;
938 nand->cmdfunc = nand_command;
939 nand->read_byte = read_byte;
940 nand->read_buf = read_buf;
941 nand->ecc.read_page = nand_read_page_hwecc;
942 nand->ecc.write_page = nand_write_page_hwecc;
943 nand->ecc.read_page_raw = nand_read_page_raw;
944 nand->ecc.write_page_raw = nand_write_page_raw;
945 nand->ecc.read_oob = nand_read_oob;
946 nand->ecc.write_oob = nand_write_oob;
947 nand->ecc.strength = 1;
948 nand->select_chip = nand_select_chip;
949 nand->dev_ready = nand_dev_ready;
950 nand_set_controller_data(nand, &tegra->nand_ctrl);
951
952 /* Disable subpage writes as we do not provide ecc->hwctl */
953 nand->options |= NAND_NO_SUBPAGE_WRITE;
954
955 /* Adjust controller clock rate */
956 clock_start_periph_pll(PERIPH_ID_NDFLASH, CLOCK_ID_PERIPH, 52000000);
957
958 /* Adjust timing for NAND device */
959 setup_timing(config->timing, info->reg);
960
961 dm_gpio_set_value(&config->wp_gpio, 1);
962
963 our_mtd = nand_to_mtd(nand);
964 ret = nand_scan_ident(our_mtd, CONFIG_SYS_NAND_MAX_CHIPS, NULL);
965 if (ret)
966 return ret;
967
968 nand->ecc.size = our_mtd->writesize;
969 nand->ecc.bytes = our_mtd->oobsize;
970
971 ret = nand_scan_tail(our_mtd);
972 if (ret)
973 return ret;
974
975 ret = nand_register(0, our_mtd);
976 if (ret) {
977 dev_err(dev, "Failed to register MTD: %d\n", ret);
978 return ret;
979 }
980
981 return 0;
982 }
983
984 U_BOOT_DRIVER(tegra_nand) = {
985 .name = "tegra-nand",
986 .id = UCLASS_MTD,
987 .of_match = tegra_nand_dt_ids,
988 .probe = tegra_probe,
989 .priv_auto_alloc_size = sizeof(struct tegra_nand_info),
990 };
991
board_nand_init(void)992 void board_nand_init(void)
993 {
994 struct udevice *dev;
995 int ret;
996
997 ret = uclass_get_device_by_driver(UCLASS_MTD,
998 DM_GET_DRIVER(tegra_nand), &dev);
999 if (ret && ret != -ENODEV)
1000 pr_err("Failed to initialize %s. (error %d)\n", dev->name,
1001 ret);
1002 }
1003