1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (c) 2007 Sascha Hauer <s.hauer@pengutronix.de>
4 */
5
6 #include <common.h>
7 #include <dm.h>
8 #include <errno.h>
9 #include <watchdog.h>
10 #include <asm/arch/imx-regs.h>
11 #include <asm/arch/clock.h>
12 #include <dm/platform_data/serial_mxc.h>
13 #include <serial.h>
14 #include <linux/compiler.h>
15
16 /* UART Control Register Bit Fields.*/
17 #define URXD_CHARRDY (1<<15)
18 #define URXD_ERR (1<<14)
19 #define URXD_OVRRUN (1<<13)
20 #define URXD_FRMERR (1<<12)
21 #define URXD_BRK (1<<11)
22 #define URXD_PRERR (1<<10)
23 #define URXD_RX_DATA (0xFF)
24 #define UCR1_ADEN (1<<15) /* Auto dectect interrupt */
25 #define UCR1_ADBR (1<<14) /* Auto detect baud rate */
26 #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
27 #define UCR1_IDEN (1<<12) /* Idle condition interrupt */
28 #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
29 #define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */
30 #define UCR1_IREN (1<<7) /* Infrared interface enable */
31 #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
32 #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
33 #define UCR1_SNDBRK (1<<4) /* Send break */
34 #define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
35 #define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */
36 #define UCR1_DOZE (1<<1) /* Doze */
37 #define UCR1_UARTEN (1<<0) /* UART enabled */
38 #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
39 #define UCR2_IRTS (1<<14) /* Ignore RTS pin */
40 #define UCR2_CTSC (1<<13) /* CTS pin control */
41 #define UCR2_CTS (1<<12) /* Clear to send */
42 #define UCR2_ESCEN (1<<11) /* Escape enable */
43 #define UCR2_PREN (1<<8) /* Parity enable */
44 #define UCR2_PROE (1<<7) /* Parity odd/even */
45 #define UCR2_STPB (1<<6) /* Stop */
46 #define UCR2_WS (1<<5) /* Word size */
47 #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
48 #define UCR2_TXEN (1<<2) /* Transmitter enabled */
49 #define UCR2_RXEN (1<<1) /* Receiver enabled */
50 #define UCR2_SRST (1<<0) /* SW reset */
51 #define UCR3_DTREN (1<<13) /* DTR interrupt enable */
52 #define UCR3_PARERREN (1<<12) /* Parity enable */
53 #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
54 #define UCR3_DSR (1<<10) /* Data set ready */
55 #define UCR3_DCD (1<<9) /* Data carrier detect */
56 #define UCR3_RI (1<<8) /* Ring indicator */
57 #define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */
58 #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
59 #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
60 #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
61 #define UCR3_REF25 (1<<3) /* Ref freq 25 MHz */
62 #define UCR3_REF30 (1<<2) /* Ref Freq 30 MHz */
63 #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
64 #define UCR3_BPEN (1<<0) /* Preset registers enable */
65 #define UCR4_CTSTL_32 (32<<10) /* CTS trigger level (32 chars) */
66 #define UCR4_INVR (1<<9) /* Inverted infrared reception */
67 #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
68 #define UCR4_WKEN (1<<7) /* Wake interrupt enable */
69 #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
70 #define UCR4_IRSC (1<<5) /* IR special case */
71 #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
72 #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
73 #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
74 #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
75 #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
76 #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
77 #define UFCR_RFDIV_SHF 7 /* Reference freq divider shift */
78 #define RFDIV 4 /* divide input clock by 2 */
79 #define UFCR_DCEDTE (1<<6) /* DTE mode select */
80 #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
81 #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
82 #define USR1_RTSS (1<<14) /* RTS pin status */
83 #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
84 #define USR1_RTSD (1<<12) /* RTS delta */
85 #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
86 #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
87 #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
88 #define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */
89 #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
90 #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
91 #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
92 #define USR2_ADET (1<<15) /* Auto baud rate detect complete */
93 #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
94 #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
95 #define USR2_IDLE (1<<12) /* Idle condition */
96 #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
97 #define USR2_WAKE (1<<7) /* Wake */
98 #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
99 #define USR2_TXDC (1<<3) /* Transmitter complete */
100 #define USR2_BRCD (1<<2) /* Break condition */
101 #define USR2_ORE (1<<1) /* Overrun error */
102 #define USR2_RDR (1<<0) /* Recv data ready */
103 #define UTS_FRCPERR (1<<13) /* Force parity error */
104 #define UTS_LOOP (1<<12) /* Loop tx and rx */
105 #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
106 #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
107 #define UTS_TXFULL (1<<4) /* TxFIFO full */
108 #define UTS_RXFULL (1<<3) /* RxFIFO full */
109 #define UTS_SOFTRS (1<<0) /* Software reset */
110 #define TXTL 2 /* reset default */
111 #define RXTL 1 /* reset default */
112
113 DECLARE_GLOBAL_DATA_PTR;
114
115 struct mxc_uart {
116 u32 rxd;
117 u32 spare0[15];
118
119 u32 txd;
120 u32 spare1[15];
121
122 u32 cr1;
123 u32 cr2;
124 u32 cr3;
125 u32 cr4;
126
127 u32 fcr;
128 u32 sr1;
129 u32 sr2;
130 u32 esc;
131
132 u32 tim;
133 u32 bir;
134 u32 bmr;
135 u32 brc;
136
137 u32 onems;
138 u32 ts;
139 };
140
_mxc_serial_init(struct mxc_uart * base,int use_dte)141 static void _mxc_serial_init(struct mxc_uart *base, int use_dte)
142 {
143 writel(0, &base->cr1);
144 writel(0, &base->cr2);
145
146 while (!(readl(&base->cr2) & UCR2_SRST));
147
148 if (use_dte)
149 writel(0x404 | UCR3_ADNIMP, &base->cr3);
150 else
151 writel(0x704 | UCR3_ADNIMP, &base->cr3);
152
153 writel(0x704 | UCR3_ADNIMP, &base->cr3);
154 writel(0x8000, &base->cr4);
155 writel(0x2b, &base->esc);
156 writel(0, &base->tim);
157
158 writel(0, &base->ts);
159 }
160
_mxc_serial_setbrg(struct mxc_uart * base,unsigned long clk,unsigned long baudrate,bool use_dte)161 static void _mxc_serial_setbrg(struct mxc_uart *base, unsigned long clk,
162 unsigned long baudrate, bool use_dte)
163 {
164 u32 tmp;
165
166 tmp = RFDIV << UFCR_RFDIV_SHF;
167 if (use_dte)
168 tmp |= UFCR_DCEDTE;
169 else
170 tmp |= (TXTL << UFCR_TXTL_SHF) | (RXTL << UFCR_RXTL_SHF);
171 writel(tmp, &base->fcr);
172
173 writel(0xf, &base->bir);
174 writel(clk / (2 * baudrate), &base->bmr);
175
176 writel(UCR2_WS | UCR2_IRTS | UCR2_RXEN | UCR2_TXEN | UCR2_SRST,
177 &base->cr2);
178 writel(UCR1_UARTEN, &base->cr1);
179 }
180
181 #if !CONFIG_IS_ENABLED(DM_SERIAL)
182
183 #ifndef CONFIG_MXC_UART_BASE
184 #error "define CONFIG_MXC_UART_BASE to use the MXC UART driver"
185 #endif
186
187 #define mxc_base ((struct mxc_uart *)CONFIG_MXC_UART_BASE)
188
mxc_serial_setbrg(void)189 static void mxc_serial_setbrg(void)
190 {
191 u32 clk = imx_get_uartclk();
192
193 if (!gd->baudrate)
194 gd->baudrate = CONFIG_BAUDRATE;
195
196 _mxc_serial_setbrg(mxc_base, clk, gd->baudrate, false);
197 }
198
mxc_serial_getc(void)199 static int mxc_serial_getc(void)
200 {
201 while (readl(&mxc_base->ts) & UTS_RXEMPTY)
202 WATCHDOG_RESET();
203 return (readl(&mxc_base->rxd) & URXD_RX_DATA); /* mask out status from upper word */
204 }
205
mxc_serial_putc(const char c)206 static void mxc_serial_putc(const char c)
207 {
208 /* If \n, also do \r */
209 if (c == '\n')
210 serial_putc('\r');
211
212 writel(c, &mxc_base->txd);
213
214 /* wait for transmitter to be ready */
215 while (!(readl(&mxc_base->ts) & UTS_TXEMPTY))
216 WATCHDOG_RESET();
217 }
218
219 /* Test whether a character is in the RX buffer */
mxc_serial_tstc(void)220 static int mxc_serial_tstc(void)
221 {
222 /* If receive fifo is empty, return false */
223 if (readl(&mxc_base->ts) & UTS_RXEMPTY)
224 return 0;
225 return 1;
226 }
227
228 /*
229 * Initialise the serial port with the given baudrate. The settings
230 * are always 8 data bits, no parity, 1 stop bit, no start bits.
231 */
mxc_serial_init(void)232 static int mxc_serial_init(void)
233 {
234 _mxc_serial_init(mxc_base, false);
235
236 serial_setbrg();
237
238 return 0;
239 }
240
241 static struct serial_device mxc_serial_drv = {
242 .name = "mxc_serial",
243 .start = mxc_serial_init,
244 .stop = NULL,
245 .setbrg = mxc_serial_setbrg,
246 .putc = mxc_serial_putc,
247 .puts = default_serial_puts,
248 .getc = mxc_serial_getc,
249 .tstc = mxc_serial_tstc,
250 };
251
mxc_serial_initialize(void)252 void mxc_serial_initialize(void)
253 {
254 serial_register(&mxc_serial_drv);
255 }
256
default_serial_console(void)257 __weak struct serial_device *default_serial_console(void)
258 {
259 return &mxc_serial_drv;
260 }
261 #endif
262
263 #if CONFIG_IS_ENABLED(DM_SERIAL)
264
mxc_serial_setbrg(struct udevice * dev,int baudrate)265 int mxc_serial_setbrg(struct udevice *dev, int baudrate)
266 {
267 struct mxc_serial_platdata *plat = dev->platdata;
268 u32 clk = imx_get_uartclk();
269
270 _mxc_serial_setbrg(plat->reg, clk, baudrate, plat->use_dte);
271
272 return 0;
273 }
274
mxc_serial_probe(struct udevice * dev)275 static int mxc_serial_probe(struct udevice *dev)
276 {
277 struct mxc_serial_platdata *plat = dev->platdata;
278
279 _mxc_serial_init(plat->reg, plat->use_dte);
280
281 return 0;
282 }
283
mxc_serial_getc(struct udevice * dev)284 static int mxc_serial_getc(struct udevice *dev)
285 {
286 struct mxc_serial_platdata *plat = dev->platdata;
287 struct mxc_uart *const uart = plat->reg;
288
289 if (readl(&uart->ts) & UTS_RXEMPTY)
290 return -EAGAIN;
291
292 return readl(&uart->rxd) & URXD_RX_DATA;
293 }
294
mxc_serial_putc(struct udevice * dev,const char ch)295 static int mxc_serial_putc(struct udevice *dev, const char ch)
296 {
297 struct mxc_serial_platdata *plat = dev->platdata;
298 struct mxc_uart *const uart = plat->reg;
299
300 if (!(readl(&uart->ts) & UTS_TXEMPTY))
301 return -EAGAIN;
302
303 writel(ch, &uart->txd);
304
305 return 0;
306 }
307
mxc_serial_pending(struct udevice * dev,bool input)308 static int mxc_serial_pending(struct udevice *dev, bool input)
309 {
310 struct mxc_serial_platdata *plat = dev->platdata;
311 struct mxc_uart *const uart = plat->reg;
312 uint32_t sr2 = readl(&uart->sr2);
313
314 if (input)
315 return sr2 & USR2_RDR ? 1 : 0;
316 else
317 return sr2 & USR2_TXDC ? 0 : 1;
318 }
319
320 static const struct dm_serial_ops mxc_serial_ops = {
321 .putc = mxc_serial_putc,
322 .pending = mxc_serial_pending,
323 .getc = mxc_serial_getc,
324 .setbrg = mxc_serial_setbrg,
325 };
326
327 #if CONFIG_IS_ENABLED(OF_CONTROL)
mxc_serial_ofdata_to_platdata(struct udevice * dev)328 static int mxc_serial_ofdata_to_platdata(struct udevice *dev)
329 {
330 struct mxc_serial_platdata *plat = dev->platdata;
331 fdt_addr_t addr;
332
333 addr = devfdt_get_addr(dev);
334 if (addr == FDT_ADDR_T_NONE)
335 return -EINVAL;
336
337 plat->reg = (struct mxc_uart *)addr;
338
339 plat->use_dte = fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev),
340 "fsl,dte-mode");
341 return 0;
342 }
343
344 static const struct udevice_id mxc_serial_ids[] = {
345 { .compatible = "fsl,imx6ul-uart" },
346 { .compatible = "fsl,imx7d-uart" },
347 { .compatible = "fsl,imx6q-uart" },
348 { }
349 };
350 #endif
351
352 U_BOOT_DRIVER(serial_mxc) = {
353 .name = "serial_mxc",
354 .id = UCLASS_SERIAL,
355 #if CONFIG_IS_ENABLED(OF_CONTROL)
356 .of_match = mxc_serial_ids,
357 .ofdata_to_platdata = mxc_serial_ofdata_to_platdata,
358 .platdata_auto_alloc_size = sizeof(struct mxc_serial_platdata),
359 #endif
360 .probe = mxc_serial_probe,
361 .ops = &mxc_serial_ops,
362 #if !CONFIG_IS_ENABLED(OF_CONTROL)
363 .flags = DM_FLAG_PRE_RELOC,
364 #endif
365 };
366 #endif
367
368 #ifdef CONFIG_DEBUG_UART_MXC
369 #include <debug_uart.h>
370
_debug_uart_init(void)371 static inline void _debug_uart_init(void)
372 {
373 struct mxc_uart *base = (struct mxc_uart *)CONFIG_DEBUG_UART_BASE;
374
375 _mxc_serial_init(base, false);
376 _mxc_serial_setbrg(base, CONFIG_DEBUG_UART_CLOCK,
377 CONFIG_BAUDRATE, false);
378 }
379
_debug_uart_putc(int ch)380 static inline void _debug_uart_putc(int ch)
381 {
382 struct mxc_uart *base = (struct mxc_uart *)CONFIG_DEBUG_UART_BASE;
383
384 while (!(readl(&base->ts) & UTS_TXEMPTY))
385 WATCHDOG_RESET();
386
387 writel(ch, &base->txd);
388 }
389
390 DEBUG_UART_FUNCS
391
392 #endif
393