1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Video driver for Marvell Armada XP SoC
4 *
5 * Initialization of LCD interface and setup of SPLASH screen image
6 */
7
8 #include <common.h>
9 #include <dm.h>
10 #include <video.h>
11 #include <linux/mbus.h>
12 #include <asm/io.h>
13 #include <asm/arch/cpu.h>
14 #include <asm/arch/soc.h>
15
16 #define MVEBU_LCD_WIN_CONTROL(w) (0xf000 + ((w) << 4))
17 #define MVEBU_LCD_WIN_BASE(w) (0xf004 + ((w) << 4))
18 #define MVEBU_LCD_WIN_REMAP(w) (0xf00c + ((w) << 4))
19
20 #define MVEBU_LCD_CFG_DMA_START_ADDR_0 0x00cc
21 #define MVEBU_LCD_CFG_DMA_START_ADDR_1 0x00dc
22
23 #define MVEBU_LCD_CFG_GRA_START_ADDR0 0x00f4
24 #define MVEBU_LCD_CFG_GRA_START_ADDR1 0x00f8
25 #define MVEBU_LCD_CFG_GRA_PITCH 0x00fc
26 #define MVEBU_LCD_SPU_GRA_OVSA_HPXL_VLN 0x0100
27 #define MVEBU_LCD_SPU_GRA_HPXL_VLN 0x0104
28 #define MVEBU_LCD_SPU_GZM_HPXL_VLN 0x0108
29 #define MVEBU_LCD_SPU_HWC_OVSA_HPXL_VLN 0x010c
30 #define MVEBU_LCD_SPU_HWC_HPXL_VLN 0x0110
31 #define MVEBU_LCD_SPUT_V_H_TOTAL 0x0114
32 #define MVEBU_LCD_SPU_V_H_ACTIVE 0x0118
33 #define MVEBU_LCD_SPU_H_PORCH 0x011c
34 #define MVEBU_LCD_SPU_V_PORCH 0x0120
35 #define MVEBU_LCD_SPU_BLANKCOLOR 0x0124
36 #define MVEBU_LCD_SPU_ALPHA_COLOR1 0x0128
37 #define MVEBU_LCD_SPU_ALPHA_COLOR2 0x012c
38 #define MVEBU_LCD_SPU_COLORKEY_Y 0x0130
39 #define MVEBU_LCD_SPU_COLORKEY_U 0x0134
40 #define MVEBU_LCD_SPU_COLORKEY_V 0x0138
41 #define MVEBU_LCD_CFG_RDREG4F 0x013c
42 #define MVEBU_LCD_SPU_SPI_RXDATA 0x0140
43 #define MVEBU_LCD_SPU_ISA_RXDATA 0x0144
44 #define MVEBU_LCD_SPU_DBG_ISA 0x0148
45
46 #define MVEBU_LCD_SPU_HWC_RDDAT 0x0158
47 #define MVEBU_LCD_SPU_GAMMA_RDDAT 0x015c
48 #define MVEBU_LCD_SPU_PALETTE_RDDAT 0x0160
49 #define MVEBU_LCD_SPU_IOPAD_IN 0x0178
50 #define MVEBU_LCD_FRAME_COUNT 0x017c
51 #define MVEBU_LCD_SPU_DMA_CTRL0 0x0190
52 #define MVEBU_LCD_SPU_DMA_CTRL1 0x0194
53 #define MVEBU_LCD_SPU_SRAM_CTRL 0x0198
54 #define MVEBU_LCD_SPU_SRAM_WRDAT 0x019c
55 #define MVEBU_LCD_SPU_SRAM_PARA0 0x01a0
56 #define MVEBU_LCD_SPU_SRAM_PARA1 0x01a4
57 #define MVEBU_LCD_CFG_SCLK_DIV 0x01a8
58 #define MVEBU_LCD_SPU_CONTRAST 0x01ac
59 #define MVEBU_LCD_SPU_SATURATION 0x01b0
60 #define MVEBU_LCD_SPU_CBSH_HUE 0x01b4
61 #define MVEBU_LCD_SPU_DUMB_CTRL 0x01b8
62 #define MVEBU_LCD_SPU_IOPAD_CONTROL 0x01bc
63 #define MVEBU_LCD_SPU_IRQ_ENA_2 0x01d8
64 #define MVEBU_LCD_SPU_IRQ_ISR_2 0x01dc
65 #define MVEBU_LCD_SPU_IRQ_ENA 0x01c0
66 #define MVEBU_LCD_SPU_IRQ_ISR 0x01c4
67 #define MVEBU_LCD_ADLL_CTRL 0x01c8
68 #define MVEBU_LCD_CLK_DIS 0x01cc
69 #define MVEBU_LCD_VGA_HVSYNC_DELAY 0x01d4
70 #define MVEBU_LCD_CLK_CFG_0 0xf0a0
71 #define MVEBU_LCD_CLK_CFG_1 0xf0a4
72 #define MVEBU_LCD_LVDS_CLK_CFG 0xf0ac
73
74 #define MVEBU_LVDS_PADS_REG (MVEBU_SYSTEM_REG_BASE + 0xf0)
75
76 enum {
77 /* Maximum LCD size we support */
78 LCD_MAX_WIDTH = 640,
79 LCD_MAX_HEIGHT = 480,
80 LCD_MAX_LOG2_BPP = VIDEO_BPP16,
81 };
82
83 struct mvebu_lcd_info {
84 u32 fb_base;
85 int x_res;
86 int y_res;
87 int x_fp;
88 int y_fp;
89 int x_bp;
90 int y_bp;
91 };
92
93 struct mvebu_video_priv {
94 uintptr_t regs;
95 };
96
97 /* Setup Mbus Bridge Windows for LCD */
mvebu_lcd_conf_mbus_registers(uintptr_t regs)98 static void mvebu_lcd_conf_mbus_registers(uintptr_t regs)
99 {
100 const struct mbus_dram_target_info *dram;
101 int i;
102
103 dram = mvebu_mbus_dram_info();
104
105 /* Disable windows, set size/base/remap to 0 */
106 for (i = 0; i < 6; i++) {
107 writel(0, regs + MVEBU_LCD_WIN_CONTROL(i));
108 writel(0, regs + MVEBU_LCD_WIN_BASE(i));
109 writel(0, regs + MVEBU_LCD_WIN_REMAP(i));
110 }
111
112 /* Write LCD bridge window registers */
113 for (i = 0; i < dram->num_cs; i++) {
114 const struct mbus_dram_window *cs = dram->cs + i;
115 writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) |
116 (dram->mbus_dram_target_id << 4) | 1,
117 regs + MVEBU_LCD_WIN_CONTROL(i));
118
119 writel(cs->base & 0xffff0000, regs + MVEBU_LCD_WIN_BASE(i));
120 }
121 }
122
123 /* Initialize LCD registers */
mvebu_lcd_register_init(struct mvebu_lcd_info * lcd_info,uintptr_t regs)124 static void mvebu_lcd_register_init(struct mvebu_lcd_info *lcd_info,
125 uintptr_t regs)
126 {
127 /* Local variable for easier handling */
128 int x = lcd_info->x_res;
129 int y = lcd_info->y_res;
130 u32 val;
131
132 /* Setup Mbus Bridge Windows */
133 mvebu_lcd_conf_mbus_registers(regs);
134
135 /*
136 * Set LVDS Pads Control Register
137 * wr 0 182F0 FFE00000
138 */
139 clrbits_le32(MVEBU_LVDS_PADS_REG, 0x1f << 16);
140
141 /*
142 * Set the LCD_CFG_GRA_START_ADDR0/1 Registers
143 * This is supposed to point to the "physical" memory at memory
144 * end (currently 1GB-64MB but also may be 2GB-64MB).
145 * See also the Window 0 settings!
146 */
147 writel(lcd_info->fb_base, regs + MVEBU_LCD_CFG_GRA_START_ADDR0);
148 writel(lcd_info->fb_base, regs + MVEBU_LCD_CFG_GRA_START_ADDR1);
149
150 /*
151 * Set the LCD_CFG_GRA_PITCH Register
152 * Bits 31-28: Duty Cycle of Backlight. value/16=High (0x8=Mid Setting)
153 * Bits 25-16: Backlight divider from 32kHz Clock
154 * (here 16=0x10 for 1kHz)
155 * Bits 15-00: Line Length in Bytes
156 * 240*2 (for RGB1555)=480=0x1E0
157 */
158 writel(0x80100000 + 2 * x, regs + MVEBU_LCD_CFG_GRA_PITCH);
159
160 /*
161 * Set the LCD_SPU_GRA_OVSA_HPXL_VLN Register
162 * Bits 31-16: Vertical start of graphical overlay on screen
163 * Bits 15-00: Horizontal start of graphical overlay on screen
164 */
165 writel(0x00000000, regs + MVEBU_LCD_SPU_GRA_OVSA_HPXL_VLN);
166
167 /*
168 * Set the LCD_SPU_GRA_HPXL_VLN Register
169 * Bits 31-16: Vertical size of graphical overlay 320=0x140
170 * Bits 15-00: Horizontal size of graphical overlay 240=0xF0
171 * Values before zooming
172 */
173 writel((y << 16) | x, regs + MVEBU_LCD_SPU_GRA_HPXL_VLN);
174
175 /*
176 * Set the LCD_SPU_GZM_HPXL_VLN Register
177 * Bits 31-16: Vertical size of graphical overlay 320=0x140
178 * Bits 15-00: Horizontal size of graphical overlay 240=0xF0
179 * Values after zooming
180 */
181 writel((y << 16) | x, regs + MVEBU_LCD_SPU_GZM_HPXL_VLN);
182
183 /*
184 * Set the LCD_SPU_HWC_OVSA_HPXL_VLN Register
185 * Bits 31-16: Vertical position of HW Cursor 320=0x140
186 * Bits 15-00: Horizontal position of HW Cursor 240=0xF0
187 */
188 writel((y << 16) | x, regs + MVEBU_LCD_SPU_HWC_OVSA_HPXL_VLN);
189
190 /*
191 * Set the LCD_SPU_HWC_OVSA_HPXL_VLN Register
192 * Bits 31-16: Vertical size of HW Cursor
193 * Bits 15-00: Horizontal size of HW Cursor
194 */
195 writel(0x00000000, regs + MVEBU_LCD_SPU_HWC_HPXL_VLN);
196
197 /*
198 * Set the LCD_SPU_HWC_OVSA_HPXL_VLN Register
199 * Bits 31-16: Screen total vertical lines:
200 * VSYNC = 1
201 * Vertical Front Porch = 2
202 * Vertical Lines = 320
203 * Vertical Back Porch = 2
204 * SUM = 325 = 0x0145
205 * Bits 15-00: Screen total horizontal pixels:
206 * HSYNC = 1
207 * Horizontal Front Porch = 44
208 * Horizontal Lines = 240
209 * Horizontal Back Porch = 2
210 * SUM = 287 = 0x011F
211 * Note: For the display the backporch is between SYNC and
212 * the start of the pixels.
213 * This is not certain for the Marvell (!?)
214 */
215 val = ((y + lcd_info->y_fp + lcd_info->y_bp + 1) << 16) |
216 (x + lcd_info->x_fp + lcd_info->x_bp + 1);
217 writel(val, regs + MVEBU_LCD_SPUT_V_H_TOTAL);
218
219 /*
220 * Set the LCD_SPU_V_H_ACTIVE Register
221 * Bits 31-16: Screen active vertical lines 320=0x140
222 * Bits 15-00: Screen active horizontakl pixels 240=0x00F0
223 */
224 writel((y << 16) | x, regs + MVEBU_LCD_SPU_V_H_ACTIVE);
225
226 /*
227 * Set the LCD_SPU_H_PORCH Register
228 * Bits 31-16: Screen horizontal backporch 44=0x2c
229 * Bits 15-00: Screen horizontal frontporch 2=0x02
230 * Note: The terms "front" and "back" for the Marvell seem to be
231 * exactly opposite to the display.
232 */
233 writel((lcd_info->x_fp << 16) | lcd_info->x_bp,
234 regs + MVEBU_LCD_SPU_H_PORCH);
235
236 /*
237 * Set the LCD_SPU_V_PORCH Register
238 * Bits 31-16: Screen vertical backporch 2=0x02
239 * Bits 15-00: Screen vertical frontporch 2=0x02
240 * Note: The terms "front" and "back" for the Marvell seem to be exactly
241 * opposite to the display.
242 */
243 writel((lcd_info->y_fp << 16) | lcd_info->y_bp,
244 regs + MVEBU_LCD_SPU_V_PORCH);
245
246 /*
247 * Set the LCD_SPU_BLANKCOLOR Register
248 * This should be black = 0
249 * For tests this is magenta=00FF00FF
250 */
251 writel(0x00FF00FF, regs + MVEBU_LCD_SPU_BLANKCOLOR);
252
253 /*
254 * Registers in the range of 0x0128 to 0x012C are colors for the cursor
255 * Registers in the range of 0x0130 to 0x0138 are colors for video
256 * color keying
257 */
258
259 /*
260 * Set the LCD_SPU_RDREG4F Register
261 * Bits 31-12: Reservd
262 * Bit 11: SRAM Wait
263 * Bit 10: Smart display fast TX (must be 1)
264 * Bit 9: DMA Arbitration Video/Graphics overlay: 0=interleaved
265 * Bit 8: FIFO watermark for DMA: 0=disable
266 * Bits 07-00: Empty 8B FIFO entries to trigger DMA, default=0x80
267 */
268 writel(0x00000780, regs + MVEBU_LCD_CFG_RDREG4F);
269
270 /*
271 * Set the LCD_SPU_DMACTRL 0 Register
272 * Bit 31: Disable overlay blending 1=disable
273 * Bit 30: Gamma correction enable, 0=disable
274 * Bit 29: Video Contrast/Saturation/Hue Adjust enable, 0=disable
275 * Bit 28: Color palette enable, 0=disable
276 * Bit 27: DMA AXI Arbiter, 1=default
277 * Bit 26: HW Cursor 1-bit mode
278 * Bit 25: HW Cursor or 1- or 2-bit mode
279 * Bit 24: HW Cursor enabled, 0=disable
280 * Bits 23-20: Graphics Memory Color Format: 0x1=RGB1555
281 * Bits 19-16: Video Memory Color Format: 0x1=RGB1555
282 * Bit 15: Memory Toggle between frame 0 and 1: 0=disable
283 * Bit 14: Graphics horizontal scaling enable: 0=disable
284 * Bit 13: Graphics test mode: 0=disable
285 * Bit 12: Graphics SWAP R and B: 0=disable
286 * Bit 11: Graphics SWAP U and V: 0=disable
287 * Bit 10: Graphics SWAP Y and U/V: 0=disable
288 * Bit 09: Graphic YUV to RGB Conversion: 0=disable
289 * Bit 08: Graphic Transfer: 1=enable
290 * Bit 07: Memory Toggle: 0=disable
291 * Bit 06: Video horizontal scaling enable: 0=disable
292 * Bit 05: Video test mode: 0=disable
293 * Bit 04: Video SWAP R and B: 0=disable
294 * Bit 03: Video SWAP U and V: 0=disable
295 * Bit 02: Video SWAP Y and U/V: 0=disable
296 * Bit 01: Video YUV to RGB Conversion: 0=disable
297 * Bit 00: Video Transfer: 0=disable
298 */
299 writel(0x88111100, regs + MVEBU_LCD_SPU_DMA_CTRL0);
300
301 /*
302 * Set the LCD_SPU_DMA_CTRL1 Register
303 * Bit 31: Manual DMA Trigger = 0
304 * Bits 30-28: DMA Trigger Source: 0x2 VSYNC
305 * Bit 28: VSYNC_INV: 0=Rising Edge, 1=Falling Edge
306 * Bits 26-24: Color Key Mode: 0=disable
307 * Bit 23: Fill low bits: 0=fill with zeroes
308 * Bit 22: Reserved
309 * Bit 21: Gated Clock: 0=disable
310 * Bit 20: Power Save enable: 0=disable
311 * Bits 19-18: Reserved
312 * Bits 17-16: Configure Video/Graphic Path: 0x1: Graphic path alpha.
313 * Bits 15-08: Configure Alpha: 0x00.
314 * Bits 07-00: Reserved.
315 */
316 writel(0x20010000, regs + MVEBU_LCD_SPU_DMA_CTRL1);
317
318 /*
319 * Set the LCD_SPU_SRAM_CTRL Register
320 * Reset to default = 0000C000
321 * Bits 15-14: SRAM control: init=0x3, Read=0, Write=2
322 * Bits 11-08: SRAM address ID: 0=gamma_yr, 1=gammy_ug, 2=gamma_vb,
323 * 3=palette, 15=cursor
324 */
325 writel(0x0000C000, regs + MVEBU_LCD_SPU_SRAM_CTRL);
326
327 /*
328 * LCD_SPU_SRAM_WRDAT register: 019C
329 * LCD_SPU_SRAM_PARA0 register: 01A0
330 * LCD_SPU_SRAM_PARA1 register: 01A4 - Cursor control/Power settings
331 */
332 writel(0x00000000, regs + MVEBU_LCD_SPU_SRAM_PARA1);
333
334
335 /* Clock settings in the at 01A8 and in the range F0A0 see below */
336
337 /*
338 * Set LCD_SPU_CONTRAST
339 * Bits 31-16: Brightness sign ext. 8-bit value +255 to -255: default=0
340 * Bits 15-00: Contrast sign ext. 8-bit value +255 to -255: default=0
341 */
342 writel(0x00000000, regs + MVEBU_LCD_SPU_CONTRAST);
343
344 /*
345 * Set LCD_SPU_SATURATION
346 * Bits 31-16: Multiplier signed 4.12 fixed point value
347 * Bits 15-00: Saturation signed 4.12 fixed point value
348 */
349 writel(0x10001000, regs + MVEBU_LCD_SPU_SATURATION);
350
351 /*
352 * Set LCD_SPU_HUE
353 * Bits 31-16: Sine signed 2.14 fixed point value
354 * Bits 15-00: Cosine signed 2.14 fixed point value
355 */
356 writel(0x00000000, regs + MVEBU_LCD_SPU_CBSH_HUE);
357
358 /*
359 * Set LCD_SPU_DUMB_CTRL
360 * Bits 31-28: LCD Type: 3=18 bit RGB | 6=24 bit RGB888
361 * Bits 27-12: Reserved
362 * Bit 11: LCD DMA Pipeline Enable: 1=Enable
363 * Bits 10-09: Reserved
364 * Bit 8: LCD GPIO pin (??)
365 * Bit 7: Reverse RGB
366 * Bit 6: Invert composite blank signal DE/EN (??)
367 * Bit 5: Invert composite sync signal
368 * Bit 4: Invert Pixel Valid Enable DE/EN (??)
369 * Bit 3: Invert VSYNC
370 * Bit 2: Invert HSYNC
371 * Bit 1: Invert Pixel Clock
372 * Bit 0: Enable LCD Panel: 1=Enable
373 * Question: Do we have to disable Smart and Dumb LCD
374 * and separately enable LVDS?
375 */
376 writel(0x6000080F, regs + MVEBU_LCD_SPU_DUMB_CTRL);
377
378 /*
379 * Set LCD_SPU_IOPAD_CTRL
380 * Bits 31-20: Reserved
381 * Bits 19-18: Vertical Interpolation: 0=Disable
382 * Bits 17-16: Reserved
383 * Bit 15: Graphics Vertical Mirror enable: 0=disable
384 * Bit 14: Reserved
385 * Bit 13: Video Vertical Mirror enable: 0=disable
386 * Bit 12: Reserved
387 * Bit 11: Command Vertical Mirror enable: 0=disable
388 * Bit 10: Reserved
389 * Bits 09-08: YUV to RGB Color space conversion: 0 (Not used)
390 * Bits 07-04: AXI Bus Master: 0x4: no crossing of 4k boundary,
391 * 128 Bytes burst
392 * Bits 03-00: LCD pins: ??? 0=24-bit Dump panel ??
393 */
394 writel(0x000000C0, regs + MVEBU_LCD_SPU_IOPAD_CONTROL);
395
396 /*
397 * Set SUP_IRQ_ENA_2: Disable all interrupts
398 */
399 writel(0x00000000, regs + MVEBU_LCD_SPU_IRQ_ENA_2);
400
401 /*
402 * Set SUP_IRQ_ENA: Disable all interrupts.
403 */
404 writel(0x00000000, regs + MVEBU_LCD_SPU_IRQ_ENA);
405
406 /*
407 * Set up ADDL Control Register
408 * Bits 31-29: 0x0 = Fastest Delay Line (default)
409 * 0x3 = Slowest Delay Line (default)
410 * Bit 28: Calibration done status.
411 * Bit 27: Reserved
412 * Bit 26: Set Pixel Clock to ADDL output
413 * Bit 25: Reduce CAL Enable
414 * Bits 24-22: Manual calibration value.
415 * Bit 21: Manual calibration enable.
416 * Bit 20: Restart Auto Cal
417 * Bits 19-16: Calibration Threshold voltage, default= 0x2
418 * Bite 15-14: Reserved
419 * Bits 13-11: Divisor for ADDL Clock: 0x1=/2, 0x3=/8, 0x5=/16
420 * Bit 10: Power Down ADDL module, default = 1!
421 * Bits 09-08: Test point configuration: 0x2=Bias, 0x3=High-z
422 * Bit 07: Reset ADDL
423 * Bit 06: Invert ADLL Clock
424 * Bits 05-00: Delay taps, 0x3F=Half Cycle, 0x00=No delay
425 * Note: ADLL is used for a VGA interface with DAC - not used here
426 */
427 writel(0x00000000, regs + MVEBU_LCD_ADLL_CTRL);
428
429 /*
430 * Set the LCD_CLK_DIS Register:
431 * Bits 3 and 4 must be 1
432 */
433 writel(0x00000018, regs + MVEBU_LCD_CLK_DIS);
434
435 /*
436 * Set the LCD_VGA_HSYNC/VSYNC Delay Register:
437 * Bits 03-00: Sets the delay for the HSYNC and VSYNC signals
438 */
439 writel(0x00000000, regs + MVEBU_LCD_VGA_HVSYNC_DELAY);
440
441 /*
442 * Clock registers
443 * See page 475 in the functional spec.
444 */
445
446 /* Step 1 and 2: Disable the PLL */
447
448 /*
449 * Disable PLL, see "LCD Clock Configuration 1 Register" below
450 */
451 writel(0x8FF40007, regs + MVEBU_LCD_CLK_CFG_1);
452
453 /*
454 * Powerdown, see "LCD Clock Configuration 0 Register" below
455 */
456 writel(0x94000174, regs + MVEBU_LCD_CLK_CFG_0);
457
458 /*
459 * Set the LCD_CFG_SCLK_DIV Register
460 * This is set fix to 0x40000001 for the LVDS output:
461 * Bits 31-30: SCLCK Source: 0=AXIBus, 1=AHBus, 2=PLLDivider0
462 * Bits 15-01: Clock Divider: Bypass for LVDS=0x0001
463 * See page 475 in section 28.5.
464 */
465 writel(0x80000001, regs + MVEBU_LCD_CFG_SCLK_DIV);
466
467 /*
468 * Set the LCD Clock Configuration 0 Register:
469 * Bit 31: Powerdown: 0=Power up
470 * Bits 30-29: Reserved
471 * Bits 28-26: PLL_KDIV: This encodes K
472 * K=16 => 0x5
473 * Bits 25-17: PLL_MDIV: This is M-1:
474 * M=1 => 0x0
475 * Bits 16-13: VCO band: 0x1 for 700-920MHz
476 * Bits 12-04: PLL_NDIV: This is N-1 and corresponds to R1_CTRL!
477 * N=28=0x1C => 0x1B
478 * Bits 03-00: R1_CTRL (for N=28 => 0x4)
479 */
480 writel(0x940021B4, regs + MVEBU_LCD_CLK_CFG_0);
481
482 /*
483 * Set the LCD Clock Configuration 1 Register:
484 * Bits 31-19: Reserved
485 * Bit 18: Select PLL: Core PLL, 1=Dedicated PPL
486 * Bit 17: Clock Output Enable: 0=disable, 1=enable
487 * Bit 16: Select RefClk: 0=RefClk (25MHz), 1=External
488 * Bit 15: Half-Div, Device Clock by DIV+0.5*Half-Dev
489 * Bits 14-13: Reserved
490 * Bits 12-00: PLL Full Divider [Note: Assumed to be the Post-Divider
491 * M' for LVDS=7!]
492 */
493 writel(0x8FF40007, regs + MVEBU_LCD_CLK_CFG_1);
494
495 /*
496 * Set the LVDS Clock Configuration Register:
497 * Bit 31: Clock Gating for the input clock to the LVDS
498 * Bit 30: LVDS Serializer enable: 1=Enabled
499 * Bits 29-11: Reserved
500 * Bit 11-08: LVDS Clock delay: 0x02 (default): by 2 pixel clock/7
501 * Bits 07-02: Reserved
502 * Bit 01: 24bbp Option: 0=Option_1,1=Option2
503 * Bit 00: 1=24bbp Panel: 0=18bpp Panel
504 * Note: Bits 0 and must be verified with the help of the
505 * Interface/display
506 */
507 writel(0xC0000201, regs + MVEBU_LCD_LVDS_CLK_CFG);
508
509 /*
510 * Power up PLL (Clock Config 0)
511 */
512 writel(0x140021B4, regs + MVEBU_LCD_CLK_CFG_0);
513
514 /* wait 10 ms */
515 mdelay(10);
516
517 /*
518 * Enable PLL (Clock Config 1)
519 */
520 writel(0x8FF60007, regs + MVEBU_LCD_CLK_CFG_1);
521 }
522
mvebu_video_probe(struct udevice * dev)523 static int mvebu_video_probe(struct udevice *dev)
524 {
525 struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
526 struct video_priv *uc_priv = dev_get_uclass_priv(dev);
527 struct mvebu_video_priv *priv = dev_get_priv(dev);
528 struct mvebu_lcd_info lcd_info;
529 struct display_timing timings;
530 u32 fb_start, fb_end;
531 int ret;
532
533 priv->regs = dev_read_addr(dev);
534 if (priv->regs == FDT_ADDR_T_NONE) {
535 dev_err(dev, "failed to get LCD address\n");
536 return -ENXIO;
537 }
538
539 ret = ofnode_decode_display_timing(dev_ofnode(dev), 0, &timings);
540 if (ret) {
541 dev_err(dev, "failed to get any display timings\n");
542 return -EINVAL;
543 }
544
545 /* Use DT timing (resolution) in internal info struct */
546 lcd_info.fb_base = plat->base;
547 lcd_info.x_res = timings.hactive.typ;
548 lcd_info.x_fp = timings.hfront_porch.typ;
549 lcd_info.x_bp = timings.hback_porch.typ;
550 lcd_info.y_res = timings.vactive.typ;
551 lcd_info.y_fp = timings.vfront_porch.typ;
552 lcd_info.y_bp = timings.vback_porch.typ;
553
554 /* Initialize the LCD controller */
555 mvebu_lcd_register_init(&lcd_info, priv->regs);
556
557 /* Enable dcache for the frame buffer */
558 fb_start = plat->base & ~(MMU_SECTION_SIZE - 1);
559 fb_end = plat->base + plat->size;
560 fb_end = ALIGN(fb_end, 1 << MMU_SECTION_SHIFT);
561 mmu_set_region_dcache_behaviour(fb_start, fb_end - fb_start,
562 DCACHE_WRITEBACK);
563 video_set_flush_dcache(dev, true);
564
565 uc_priv->xsize = lcd_info.x_res;
566 uc_priv->ysize = lcd_info.y_res;
567 uc_priv->bpix = VIDEO_BPP16; /* Uses RGB555 format */
568
569 return 0;
570 }
571
mvebu_video_bind(struct udevice * dev)572 static int mvebu_video_bind(struct udevice *dev)
573 {
574 struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
575
576 plat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT *
577 (1 << LCD_MAX_LOG2_BPP) / 8;
578
579 return 0;
580 }
581
582 static const struct udevice_id mvebu_video_ids[] = {
583 { .compatible = "marvell,armada-xp-lcd" },
584 { }
585 };
586
587 U_BOOT_DRIVER(mvebu_video) = {
588 .name = "mvebu_video",
589 .id = UCLASS_VIDEO,
590 .of_match = mvebu_video_ids,
591 .bind = mvebu_video_bind,
592 .probe = mvebu_video_probe,
593 .priv_auto_alloc_size = sizeof(struct mvebu_video_priv),
594 };
595