xref: /openbmc/linux/drivers/gpio/gpio-mvebu.c (revision 644ee702)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * GPIO driver for Marvell SoCs
4  *
5  * Copyright (C) 2012 Marvell
6  *
7  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
8  * Andrew Lunn <andrew@lunn.ch>
9  * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
10  *
11  * This driver is a fairly straightforward GPIO driver for the
12  * complete family of Marvell EBU SoC platforms (Orion, Dove,
13  * Kirkwood, Discovery, Armada 370/XP). The only complexity of this
14  * driver is the different register layout that exists between the
15  * non-SMP platforms (Orion, Dove, Kirkwood, Armada 370) and the SMP
16  * platforms (MV78200 from the Discovery family and the Armada
17  * XP). Therefore, this driver handles three variants of the GPIO
18  * block:
19  * - the basic variant, called "orion-gpio", with the simplest
20  *   register set. Used on Orion, Dove, Kirkwoord, Armada 370 and
21  *   non-SMP Discovery systems
22  * - the mv78200 variant for MV78200 Discovery systems. This variant
23  *   turns the edge mask and level mask registers into CPU0 edge
24  *   mask/level mask registers, and adds CPU1 edge mask/level mask
25  *   registers.
26  * - the armadaxp variant for Armada XP systems. This variant keeps
27  *   the normal cause/edge mask/level mask registers when the global
28  *   interrupts are used, but adds per-CPU cause/edge mask/level mask
29  *   registers n a separate memory area for the per-CPU GPIO
30  *   interrupts.
31  */
32 
33 #include <linux/bitops.h>
34 #include <linux/clk.h>
35 #include <linux/err.h>
36 #include <linux/gpio/driver.h>
37 #include <linux/gpio/consumer.h>
38 #include <linux/gpio/machine.h>
39 #include <linux/init.h>
40 #include <linux/io.h>
41 #include <linux/irq.h>
42 #include <linux/irqchip/chained_irq.h>
43 #include <linux/irqdomain.h>
44 #include <linux/mfd/syscon.h>
45 #include <linux/of_device.h>
46 #include <linux/pinctrl/consumer.h>
47 #include <linux/platform_device.h>
48 #include <linux/pwm.h>
49 #include <linux/regmap.h>
50 #include <linux/slab.h>
51 
52 /*
53  * GPIO unit register offsets.
54  */
55 #define GPIO_OUT_OFF			0x0000
56 #define GPIO_IO_CONF_OFF		0x0004
57 #define GPIO_BLINK_EN_OFF		0x0008
58 #define GPIO_IN_POL_OFF			0x000c
59 #define GPIO_DATA_IN_OFF		0x0010
60 #define GPIO_EDGE_CAUSE_OFF		0x0014
61 #define GPIO_EDGE_MASK_OFF		0x0018
62 #define GPIO_LEVEL_MASK_OFF		0x001c
63 #define GPIO_BLINK_CNT_SELECT_OFF	0x0020
64 
65 /*
66  * PWM register offsets.
67  */
68 #define PWM_BLINK_ON_DURATION_OFF	0x0
69 #define PWM_BLINK_OFF_DURATION_OFF	0x4
70 #define PWM_BLINK_COUNTER_B_OFF		0x8
71 
72 /* Armada 8k variant gpios register offsets */
73 #define AP80X_GPIO0_OFF_A8K		0x1040
74 #define CP11X_GPIO0_OFF_A8K		0x100
75 #define CP11X_GPIO1_OFF_A8K		0x140
76 
77 /* The MV78200 has per-CPU registers for edge mask and level mask */
78 #define GPIO_EDGE_MASK_MV78200_OFF(cpu)	  ((cpu) ? 0x30 : 0x18)
79 #define GPIO_LEVEL_MASK_MV78200_OFF(cpu)  ((cpu) ? 0x34 : 0x1C)
80 
81 /*
82  * The Armada XP has per-CPU registers for interrupt cause, interrupt
83  * mask and interrupt level mask. Those are in percpu_regs range.
84  */
85 #define GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu) ((cpu) * 0x4)
86 #define GPIO_EDGE_MASK_ARMADAXP_OFF(cpu)  (0x10 + (cpu) * 0x4)
87 #define GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu) (0x20 + (cpu) * 0x4)
88 
89 #define MVEBU_GPIO_SOC_VARIANT_ORION	0x1
90 #define MVEBU_GPIO_SOC_VARIANT_MV78200	0x2
91 #define MVEBU_GPIO_SOC_VARIANT_ARMADAXP 0x3
92 #define MVEBU_GPIO_SOC_VARIANT_A8K	0x4
93 
94 #define MVEBU_MAX_GPIO_PER_BANK		32
95 
96 struct mvebu_pwm {
97 	struct regmap		*regs;
98 	u32			 offset;
99 	unsigned long		 clk_rate;
100 	struct gpio_desc	*gpiod;
101 	struct pwm_chip		 chip;
102 	spinlock_t		 lock;
103 	struct mvebu_gpio_chip	*mvchip;
104 
105 	/* Used to preserve GPIO/PWM registers across suspend/resume */
106 	u32			 blink_select;
107 	u32			 blink_on_duration;
108 	u32			 blink_off_duration;
109 };
110 
111 struct mvebu_gpio_chip {
112 	struct gpio_chip   chip;
113 	struct regmap     *regs;
114 	u32		   offset;
115 	struct regmap     *percpu_regs;
116 	int		   irqbase;
117 	struct irq_domain *domain;
118 	int		   soc_variant;
119 
120 	/* Used for PWM support */
121 	struct clk	  *clk;
122 	struct mvebu_pwm  *mvpwm;
123 
124 	/* Used to preserve GPIO registers across suspend/resume */
125 	u32		   out_reg;
126 	u32		   io_conf_reg;
127 	u32		   blink_en_reg;
128 	u32		   in_pol_reg;
129 	u32		   edge_mask_regs[4];
130 	u32		   level_mask_regs[4];
131 };
132 
133 /*
134  * Functions returning addresses of individual registers for a given
135  * GPIO controller.
136  */
137 
mvebu_gpioreg_edge_cause(struct mvebu_gpio_chip * mvchip,struct regmap ** map,unsigned int * offset)138 static void mvebu_gpioreg_edge_cause(struct mvebu_gpio_chip *mvchip,
139 			 struct regmap **map, unsigned int *offset)
140 {
141 	int cpu;
142 
143 	switch (mvchip->soc_variant) {
144 	case MVEBU_GPIO_SOC_VARIANT_ORION:
145 	case MVEBU_GPIO_SOC_VARIANT_MV78200:
146 	case MVEBU_GPIO_SOC_VARIANT_A8K:
147 		*map = mvchip->regs;
148 		*offset = GPIO_EDGE_CAUSE_OFF + mvchip->offset;
149 		break;
150 	case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
151 		cpu = smp_processor_id();
152 		*map = mvchip->percpu_regs;
153 		*offset = GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu);
154 		break;
155 	default:
156 		BUG();
157 	}
158 }
159 
160 static u32
mvebu_gpio_read_edge_cause(struct mvebu_gpio_chip * mvchip)161 mvebu_gpio_read_edge_cause(struct mvebu_gpio_chip *mvchip)
162 {
163 	struct regmap *map;
164 	unsigned int offset;
165 	u32 val;
166 
167 	mvebu_gpioreg_edge_cause(mvchip, &map, &offset);
168 	regmap_read(map, offset, &val);
169 
170 	return val;
171 }
172 
173 static void
mvebu_gpio_write_edge_cause(struct mvebu_gpio_chip * mvchip,u32 val)174 mvebu_gpio_write_edge_cause(struct mvebu_gpio_chip *mvchip, u32 val)
175 {
176 	struct regmap *map;
177 	unsigned int offset;
178 
179 	mvebu_gpioreg_edge_cause(mvchip, &map, &offset);
180 	regmap_write(map, offset, val);
181 }
182 
183 static inline void
mvebu_gpioreg_edge_mask(struct mvebu_gpio_chip * mvchip,struct regmap ** map,unsigned int * offset)184 mvebu_gpioreg_edge_mask(struct mvebu_gpio_chip *mvchip,
185 			struct regmap **map, unsigned int *offset)
186 {
187 	int cpu;
188 
189 	switch (mvchip->soc_variant) {
190 	case MVEBU_GPIO_SOC_VARIANT_ORION:
191 	case MVEBU_GPIO_SOC_VARIANT_A8K:
192 		*map = mvchip->regs;
193 		*offset = GPIO_EDGE_MASK_OFF + mvchip->offset;
194 		break;
195 	case MVEBU_GPIO_SOC_VARIANT_MV78200:
196 		cpu = smp_processor_id();
197 		*map = mvchip->regs;
198 		*offset = GPIO_EDGE_MASK_MV78200_OFF(cpu);
199 		break;
200 	case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
201 		cpu = smp_processor_id();
202 		*map = mvchip->percpu_regs;
203 		*offset = GPIO_EDGE_MASK_ARMADAXP_OFF(cpu);
204 		break;
205 	default:
206 		BUG();
207 	}
208 }
209 
210 static u32
mvebu_gpio_read_edge_mask(struct mvebu_gpio_chip * mvchip)211 mvebu_gpio_read_edge_mask(struct mvebu_gpio_chip *mvchip)
212 {
213 	struct regmap *map;
214 	unsigned int offset;
215 	u32 val;
216 
217 	mvebu_gpioreg_edge_mask(mvchip, &map, &offset);
218 	regmap_read(map, offset, &val);
219 
220 	return val;
221 }
222 
223 static void
mvebu_gpio_write_edge_mask(struct mvebu_gpio_chip * mvchip,u32 val)224 mvebu_gpio_write_edge_mask(struct mvebu_gpio_chip *mvchip, u32 val)
225 {
226 	struct regmap *map;
227 	unsigned int offset;
228 
229 	mvebu_gpioreg_edge_mask(mvchip, &map, &offset);
230 	regmap_write(map, offset, val);
231 }
232 
233 static void
mvebu_gpioreg_level_mask(struct mvebu_gpio_chip * mvchip,struct regmap ** map,unsigned int * offset)234 mvebu_gpioreg_level_mask(struct mvebu_gpio_chip *mvchip,
235 			 struct regmap **map, unsigned int *offset)
236 {
237 	int cpu;
238 
239 	switch (mvchip->soc_variant) {
240 	case MVEBU_GPIO_SOC_VARIANT_ORION:
241 	case MVEBU_GPIO_SOC_VARIANT_A8K:
242 		*map = mvchip->regs;
243 		*offset = GPIO_LEVEL_MASK_OFF + mvchip->offset;
244 		break;
245 	case MVEBU_GPIO_SOC_VARIANT_MV78200:
246 		cpu = smp_processor_id();
247 		*map = mvchip->regs;
248 		*offset = GPIO_LEVEL_MASK_MV78200_OFF(cpu);
249 		break;
250 	case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
251 		cpu = smp_processor_id();
252 		*map = mvchip->percpu_regs;
253 		*offset = GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu);
254 		break;
255 	default:
256 		BUG();
257 	}
258 }
259 
260 static u32
mvebu_gpio_read_level_mask(struct mvebu_gpio_chip * mvchip)261 mvebu_gpio_read_level_mask(struct mvebu_gpio_chip *mvchip)
262 {
263 	struct regmap *map;
264 	unsigned int offset;
265 	u32 val;
266 
267 	mvebu_gpioreg_level_mask(mvchip, &map, &offset);
268 	regmap_read(map, offset, &val);
269 
270 	return val;
271 }
272 
273 static void
mvebu_gpio_write_level_mask(struct mvebu_gpio_chip * mvchip,u32 val)274 mvebu_gpio_write_level_mask(struct mvebu_gpio_chip *mvchip, u32 val)
275 {
276 	struct regmap *map;
277 	unsigned int offset;
278 
279 	mvebu_gpioreg_level_mask(mvchip, &map, &offset);
280 	regmap_write(map, offset, val);
281 }
282 
283 /*
284  * Functions returning offsets of individual registers for a given
285  * PWM controller.
286  */
mvebu_pwmreg_blink_on_duration(struct mvebu_pwm * mvpwm)287 static unsigned int mvebu_pwmreg_blink_on_duration(struct mvebu_pwm *mvpwm)
288 {
289 	return mvpwm->offset + PWM_BLINK_ON_DURATION_OFF;
290 }
291 
mvebu_pwmreg_blink_off_duration(struct mvebu_pwm * mvpwm)292 static unsigned int mvebu_pwmreg_blink_off_duration(struct mvebu_pwm *mvpwm)
293 {
294 	return mvpwm->offset + PWM_BLINK_OFF_DURATION_OFF;
295 }
296 
297 /*
298  * Functions implementing the gpio_chip methods
299  */
mvebu_gpio_set(struct gpio_chip * chip,unsigned int pin,int value)300 static void mvebu_gpio_set(struct gpio_chip *chip, unsigned int pin, int value)
301 {
302 	struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
303 
304 	regmap_update_bits(mvchip->regs, GPIO_OUT_OFF + mvchip->offset,
305 			   BIT(pin), value ? BIT(pin) : 0);
306 }
307 
mvebu_gpio_get(struct gpio_chip * chip,unsigned int pin)308 static int mvebu_gpio_get(struct gpio_chip *chip, unsigned int pin)
309 {
310 	struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
311 	u32 u;
312 
313 	regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &u);
314 
315 	if (u & BIT(pin)) {
316 		u32 data_in, in_pol;
317 
318 		regmap_read(mvchip->regs, GPIO_DATA_IN_OFF + mvchip->offset,
319 			    &data_in);
320 		regmap_read(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset,
321 			    &in_pol);
322 		u = data_in ^ in_pol;
323 	} else {
324 		regmap_read(mvchip->regs, GPIO_OUT_OFF + mvchip->offset, &u);
325 	}
326 
327 	return (u >> pin) & 1;
328 }
329 
mvebu_gpio_blink(struct gpio_chip * chip,unsigned int pin,int value)330 static void mvebu_gpio_blink(struct gpio_chip *chip, unsigned int pin,
331 			     int value)
332 {
333 	struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
334 
335 	regmap_update_bits(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset,
336 			   BIT(pin), value ? BIT(pin) : 0);
337 }
338 
mvebu_gpio_direction_input(struct gpio_chip * chip,unsigned int pin)339 static int mvebu_gpio_direction_input(struct gpio_chip *chip, unsigned int pin)
340 {
341 	struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
342 	int ret;
343 
344 	/*
345 	 * Check with the pinctrl driver whether this pin is usable as
346 	 * an input GPIO
347 	 */
348 	ret = pinctrl_gpio_direction_input(chip->base + pin);
349 	if (ret)
350 		return ret;
351 
352 	regmap_update_bits(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset,
353 			   BIT(pin), BIT(pin));
354 
355 	return 0;
356 }
357 
mvebu_gpio_direction_output(struct gpio_chip * chip,unsigned int pin,int value)358 static int mvebu_gpio_direction_output(struct gpio_chip *chip, unsigned int pin,
359 				       int value)
360 {
361 	struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
362 	int ret;
363 
364 	/*
365 	 * Check with the pinctrl driver whether this pin is usable as
366 	 * an output GPIO
367 	 */
368 	ret = pinctrl_gpio_direction_output(chip->base + pin);
369 	if (ret)
370 		return ret;
371 
372 	mvebu_gpio_blink(chip, pin, 0);
373 	mvebu_gpio_set(chip, pin, value);
374 
375 	regmap_update_bits(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset,
376 			   BIT(pin), 0);
377 
378 	return 0;
379 }
380 
mvebu_gpio_get_direction(struct gpio_chip * chip,unsigned int pin)381 static int mvebu_gpio_get_direction(struct gpio_chip *chip, unsigned int pin)
382 {
383 	struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
384 	u32 u;
385 
386 	regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &u);
387 
388 	if (u & BIT(pin))
389 		return GPIO_LINE_DIRECTION_IN;
390 
391 	return GPIO_LINE_DIRECTION_OUT;
392 }
393 
mvebu_gpio_to_irq(struct gpio_chip * chip,unsigned int pin)394 static int mvebu_gpio_to_irq(struct gpio_chip *chip, unsigned int pin)
395 {
396 	struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
397 
398 	return irq_create_mapping(mvchip->domain, pin);
399 }
400 
401 /*
402  * Functions implementing the irq_chip methods
403  */
mvebu_gpio_irq_ack(struct irq_data * d)404 static void mvebu_gpio_irq_ack(struct irq_data *d)
405 {
406 	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
407 	struct mvebu_gpio_chip *mvchip = gc->private;
408 	u32 mask = d->mask;
409 
410 	irq_gc_lock(gc);
411 	mvebu_gpio_write_edge_cause(mvchip, ~mask);
412 	irq_gc_unlock(gc);
413 }
414 
mvebu_gpio_edge_irq_mask(struct irq_data * d)415 static void mvebu_gpio_edge_irq_mask(struct irq_data *d)
416 {
417 	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
418 	struct mvebu_gpio_chip *mvchip = gc->private;
419 	struct irq_chip_type *ct = irq_data_get_chip_type(d);
420 	u32 mask = d->mask;
421 
422 	irq_gc_lock(gc);
423 	ct->mask_cache_priv &= ~mask;
424 	mvebu_gpio_write_edge_mask(mvchip, ct->mask_cache_priv);
425 	irq_gc_unlock(gc);
426 }
427 
mvebu_gpio_edge_irq_unmask(struct irq_data * d)428 static void mvebu_gpio_edge_irq_unmask(struct irq_data *d)
429 {
430 	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
431 	struct mvebu_gpio_chip *mvchip = gc->private;
432 	struct irq_chip_type *ct = irq_data_get_chip_type(d);
433 	u32 mask = d->mask;
434 
435 	irq_gc_lock(gc);
436 	mvebu_gpio_write_edge_cause(mvchip, ~mask);
437 	ct->mask_cache_priv |= mask;
438 	mvebu_gpio_write_edge_mask(mvchip, ct->mask_cache_priv);
439 	irq_gc_unlock(gc);
440 }
441 
mvebu_gpio_level_irq_mask(struct irq_data * d)442 static void mvebu_gpio_level_irq_mask(struct irq_data *d)
443 {
444 	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
445 	struct mvebu_gpio_chip *mvchip = gc->private;
446 	struct irq_chip_type *ct = irq_data_get_chip_type(d);
447 	u32 mask = d->mask;
448 
449 	irq_gc_lock(gc);
450 	ct->mask_cache_priv &= ~mask;
451 	mvebu_gpio_write_level_mask(mvchip, ct->mask_cache_priv);
452 	irq_gc_unlock(gc);
453 }
454 
mvebu_gpio_level_irq_unmask(struct irq_data * d)455 static void mvebu_gpio_level_irq_unmask(struct irq_data *d)
456 {
457 	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
458 	struct mvebu_gpio_chip *mvchip = gc->private;
459 	struct irq_chip_type *ct = irq_data_get_chip_type(d);
460 	u32 mask = d->mask;
461 
462 	irq_gc_lock(gc);
463 	ct->mask_cache_priv |= mask;
464 	mvebu_gpio_write_level_mask(mvchip, ct->mask_cache_priv);
465 	irq_gc_unlock(gc);
466 }
467 
468 /*****************************************************************************
469  * MVEBU GPIO IRQ
470  *
471  * GPIO_IN_POL register controls whether GPIO_DATA_IN will hold the same
472  * value of the line or the opposite value.
473  *
474  * Level IRQ handlers: DATA_IN is used directly as cause register.
475  *		       Interrupt are masked by LEVEL_MASK registers.
476  * Edge IRQ handlers:  Change in DATA_IN are latched in EDGE_CAUSE.
477  *		       Interrupt are masked by EDGE_MASK registers.
478  * Both-edge handlers: Similar to regular Edge handlers, but also swaps
479  *		       the polarity to catch the next line transaction.
480  *		       This is a race condition that might not perfectly
481  *		       work on some use cases.
482  *
483  * Every eight GPIO lines are grouped (OR'ed) before going up to main
484  * cause register.
485  *
486  *		      EDGE  cause    mask
487  *	  data-in   /--------| |-----| |----\
488  *     -----| |-----			     ---- to main cause reg
489  *	     X	    \----------------| |----/
490  *	  polarity    LEVEL	     mask
491  *
492  ****************************************************************************/
493 
mvebu_gpio_irq_set_type(struct irq_data * d,unsigned int type)494 static int mvebu_gpio_irq_set_type(struct irq_data *d, unsigned int type)
495 {
496 	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
497 	struct irq_chip_type *ct = irq_data_get_chip_type(d);
498 	struct mvebu_gpio_chip *mvchip = gc->private;
499 	int pin;
500 	u32 u;
501 
502 	pin = d->hwirq;
503 
504 	regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &u);
505 	if ((u & BIT(pin)) == 0)
506 		return -EINVAL;
507 
508 	type &= IRQ_TYPE_SENSE_MASK;
509 	if (type == IRQ_TYPE_NONE)
510 		return -EINVAL;
511 
512 	/* Check if we need to change chip and handler */
513 	if (!(ct->type & type))
514 		if (irq_setup_alt_chip(d, type))
515 			return -EINVAL;
516 
517 	/*
518 	 * Configure interrupt polarity.
519 	 */
520 	switch (type) {
521 	case IRQ_TYPE_EDGE_RISING:
522 	case IRQ_TYPE_LEVEL_HIGH:
523 		regmap_update_bits(mvchip->regs,
524 				   GPIO_IN_POL_OFF + mvchip->offset,
525 				   BIT(pin), 0);
526 		break;
527 	case IRQ_TYPE_EDGE_FALLING:
528 	case IRQ_TYPE_LEVEL_LOW:
529 		regmap_update_bits(mvchip->regs,
530 				   GPIO_IN_POL_OFF + mvchip->offset,
531 				   BIT(pin), BIT(pin));
532 		break;
533 	case IRQ_TYPE_EDGE_BOTH: {
534 		u32 data_in, in_pol, val;
535 
536 		regmap_read(mvchip->regs,
537 			    GPIO_IN_POL_OFF + mvchip->offset, &in_pol);
538 		regmap_read(mvchip->regs,
539 			    GPIO_DATA_IN_OFF + mvchip->offset, &data_in);
540 
541 		/*
542 		 * set initial polarity based on current input level
543 		 */
544 		if ((data_in ^ in_pol) & BIT(pin))
545 			val = BIT(pin); /* falling */
546 		else
547 			val = 0; /* raising */
548 
549 		regmap_update_bits(mvchip->regs,
550 				   GPIO_IN_POL_OFF + mvchip->offset,
551 				   BIT(pin), val);
552 		break;
553 	}
554 	}
555 	return 0;
556 }
557 
mvebu_gpio_irq_handler(struct irq_desc * desc)558 static void mvebu_gpio_irq_handler(struct irq_desc *desc)
559 {
560 	struct mvebu_gpio_chip *mvchip = irq_desc_get_handler_data(desc);
561 	struct irq_chip *chip = irq_desc_get_chip(desc);
562 	u32 cause, type, data_in, level_mask, edge_cause, edge_mask;
563 	int i;
564 
565 	if (mvchip == NULL)
566 		return;
567 
568 	chained_irq_enter(chip, desc);
569 
570 	regmap_read(mvchip->regs, GPIO_DATA_IN_OFF + mvchip->offset, &data_in);
571 	level_mask = mvebu_gpio_read_level_mask(mvchip);
572 	edge_cause = mvebu_gpio_read_edge_cause(mvchip);
573 	edge_mask  = mvebu_gpio_read_edge_mask(mvchip);
574 
575 	cause = (data_in & level_mask) | (edge_cause & edge_mask);
576 
577 	for (i = 0; i < mvchip->chip.ngpio; i++) {
578 		int irq;
579 
580 		irq = irq_find_mapping(mvchip->domain, i);
581 
582 		if (!(cause & BIT(i)))
583 			continue;
584 
585 		type = irq_get_trigger_type(irq);
586 		if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
587 			/* Swap polarity (race with GPIO line) */
588 			u32 polarity;
589 
590 			regmap_read(mvchip->regs,
591 				    GPIO_IN_POL_OFF + mvchip->offset,
592 				    &polarity);
593 			polarity ^= BIT(i);
594 			regmap_write(mvchip->regs,
595 				     GPIO_IN_POL_OFF + mvchip->offset,
596 				     polarity);
597 		}
598 
599 		generic_handle_irq(irq);
600 	}
601 
602 	chained_irq_exit(chip, desc);
603 }
604 
605 static const struct regmap_config mvebu_gpio_regmap_config = {
606 	.reg_bits = 32,
607 	.reg_stride = 4,
608 	.val_bits = 32,
609 	.fast_io = true,
610 };
611 
612 /*
613  * Functions implementing the pwm_chip methods
614  */
to_mvebu_pwm(struct pwm_chip * chip)615 static struct mvebu_pwm *to_mvebu_pwm(struct pwm_chip *chip)
616 {
617 	return container_of(chip, struct mvebu_pwm, chip);
618 }
619 
mvebu_pwm_request(struct pwm_chip * chip,struct pwm_device * pwm)620 static int mvebu_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
621 {
622 	struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip);
623 	struct mvebu_gpio_chip *mvchip = mvpwm->mvchip;
624 	struct gpio_desc *desc;
625 	unsigned long flags;
626 	int ret = 0;
627 
628 	spin_lock_irqsave(&mvpwm->lock, flags);
629 
630 	if (mvpwm->gpiod) {
631 		ret = -EBUSY;
632 	} else {
633 		desc = gpiochip_request_own_desc(&mvchip->chip,
634 						 pwm->hwpwm, "mvebu-pwm",
635 						 GPIO_ACTIVE_HIGH,
636 						 GPIOD_OUT_LOW);
637 		if (IS_ERR(desc)) {
638 			ret = PTR_ERR(desc);
639 			goto out;
640 		}
641 
642 		mvpwm->gpiod = desc;
643 	}
644 out:
645 	spin_unlock_irqrestore(&mvpwm->lock, flags);
646 	return ret;
647 }
648 
mvebu_pwm_free(struct pwm_chip * chip,struct pwm_device * pwm)649 static void mvebu_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
650 {
651 	struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip);
652 	unsigned long flags;
653 
654 	spin_lock_irqsave(&mvpwm->lock, flags);
655 	gpiochip_free_own_desc(mvpwm->gpiod);
656 	mvpwm->gpiod = NULL;
657 	spin_unlock_irqrestore(&mvpwm->lock, flags);
658 }
659 
mvebu_pwm_get_state(struct pwm_chip * chip,struct pwm_device * pwm,struct pwm_state * state)660 static int mvebu_pwm_get_state(struct pwm_chip *chip,
661 			       struct pwm_device *pwm,
662 			       struct pwm_state *state)
663 {
664 
665 	struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip);
666 	struct mvebu_gpio_chip *mvchip = mvpwm->mvchip;
667 	unsigned long long val;
668 	unsigned long flags;
669 	u32 u;
670 
671 	spin_lock_irqsave(&mvpwm->lock, flags);
672 
673 	regmap_read(mvpwm->regs, mvebu_pwmreg_blink_on_duration(mvpwm), &u);
674 	/* Hardware treats zero as 2^32. See mvebu_pwm_apply(). */
675 	if (u > 0)
676 		val = u;
677 	else
678 		val = UINT_MAX + 1ULL;
679 	state->duty_cycle = DIV_ROUND_UP_ULL(val * NSEC_PER_SEC,
680 			mvpwm->clk_rate);
681 
682 	regmap_read(mvpwm->regs, mvebu_pwmreg_blink_off_duration(mvpwm), &u);
683 	/* period = on + off duration */
684 	if (u > 0)
685 		val += u;
686 	else
687 		val += UINT_MAX + 1ULL;
688 	state->period = DIV_ROUND_UP_ULL(val * NSEC_PER_SEC, mvpwm->clk_rate);
689 
690 	regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, &u);
691 	if (u)
692 		state->enabled = true;
693 	else
694 		state->enabled = false;
695 
696 	spin_unlock_irqrestore(&mvpwm->lock, flags);
697 
698 	return 0;
699 }
700 
mvebu_pwm_apply(struct pwm_chip * chip,struct pwm_device * pwm,const struct pwm_state * state)701 static int mvebu_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
702 			   const struct pwm_state *state)
703 {
704 	struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip);
705 	struct mvebu_gpio_chip *mvchip = mvpwm->mvchip;
706 	unsigned long long val;
707 	unsigned long flags;
708 	unsigned int on, off;
709 
710 	if (state->polarity != PWM_POLARITY_NORMAL)
711 		return -EINVAL;
712 
713 	val = (unsigned long long) mvpwm->clk_rate * state->duty_cycle;
714 	do_div(val, NSEC_PER_SEC);
715 	if (val > UINT_MAX + 1ULL)
716 		return -EINVAL;
717 	/*
718 	 * Zero on/off values don't work as expected. Experimentation shows
719 	 * that zero value is treated as 2^32. This behavior is not documented.
720 	 */
721 	if (val == UINT_MAX + 1ULL)
722 		on = 0;
723 	else if (val)
724 		on = val;
725 	else
726 		on = 1;
727 
728 	val = (unsigned long long) mvpwm->clk_rate * state->period;
729 	do_div(val, NSEC_PER_SEC);
730 	val -= on;
731 	if (val > UINT_MAX + 1ULL)
732 		return -EINVAL;
733 	if (val == UINT_MAX + 1ULL)
734 		off = 0;
735 	else if (val)
736 		off = val;
737 	else
738 		off = 1;
739 
740 	spin_lock_irqsave(&mvpwm->lock, flags);
741 
742 	regmap_write(mvpwm->regs, mvebu_pwmreg_blink_on_duration(mvpwm), on);
743 	regmap_write(mvpwm->regs, mvebu_pwmreg_blink_off_duration(mvpwm), off);
744 	if (state->enabled)
745 		mvebu_gpio_blink(&mvchip->chip, pwm->hwpwm, 1);
746 	else
747 		mvebu_gpio_blink(&mvchip->chip, pwm->hwpwm, 0);
748 
749 	spin_unlock_irqrestore(&mvpwm->lock, flags);
750 
751 	return 0;
752 }
753 
754 static const struct pwm_ops mvebu_pwm_ops = {
755 	.request = mvebu_pwm_request,
756 	.free = mvebu_pwm_free,
757 	.get_state = mvebu_pwm_get_state,
758 	.apply = mvebu_pwm_apply,
759 	.owner = THIS_MODULE,
760 };
761 
mvebu_pwm_suspend(struct mvebu_gpio_chip * mvchip)762 static void __maybe_unused mvebu_pwm_suspend(struct mvebu_gpio_chip *mvchip)
763 {
764 	struct mvebu_pwm *mvpwm = mvchip->mvpwm;
765 
766 	regmap_read(mvchip->regs, GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset,
767 		    &mvpwm->blink_select);
768 	regmap_read(mvpwm->regs, mvebu_pwmreg_blink_on_duration(mvpwm),
769 		    &mvpwm->blink_on_duration);
770 	regmap_read(mvpwm->regs, mvebu_pwmreg_blink_off_duration(mvpwm),
771 		    &mvpwm->blink_off_duration);
772 }
773 
mvebu_pwm_resume(struct mvebu_gpio_chip * mvchip)774 static void __maybe_unused mvebu_pwm_resume(struct mvebu_gpio_chip *mvchip)
775 {
776 	struct mvebu_pwm *mvpwm = mvchip->mvpwm;
777 
778 	regmap_write(mvchip->regs, GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset,
779 		     mvpwm->blink_select);
780 	regmap_write(mvpwm->regs, mvebu_pwmreg_blink_on_duration(mvpwm),
781 		     mvpwm->blink_on_duration);
782 	regmap_write(mvpwm->regs, mvebu_pwmreg_blink_off_duration(mvpwm),
783 		     mvpwm->blink_off_duration);
784 }
785 
mvebu_pwm_probe(struct platform_device * pdev,struct mvebu_gpio_chip * mvchip,int id)786 static int mvebu_pwm_probe(struct platform_device *pdev,
787 			   struct mvebu_gpio_chip *mvchip,
788 			   int id)
789 {
790 	struct device *dev = &pdev->dev;
791 	struct mvebu_pwm *mvpwm;
792 	void __iomem *base;
793 	u32 offset;
794 	u32 set;
795 
796 	if (mvchip->soc_variant == MVEBU_GPIO_SOC_VARIANT_A8K) {
797 		int ret = of_property_read_u32(dev->of_node,
798 					       "marvell,pwm-offset", &offset);
799 		if (ret < 0)
800 			return 0;
801 	} else {
802 		/*
803 		 * There are only two sets of PWM configuration registers for
804 		 * all the GPIO lines on those SoCs which this driver reserves
805 		 * for the first two GPIO chips. So if the resource is missing
806 		 * we can't treat it as an error.
807 		 */
808 		if (!platform_get_resource_byname(pdev, IORESOURCE_MEM, "pwm"))
809 			return 0;
810 		offset = 0;
811 	}
812 
813 	if (IS_ERR(mvchip->clk))
814 		return PTR_ERR(mvchip->clk);
815 
816 	mvpwm = devm_kzalloc(dev, sizeof(struct mvebu_pwm), GFP_KERNEL);
817 	if (!mvpwm)
818 		return -ENOMEM;
819 	mvchip->mvpwm = mvpwm;
820 	mvpwm->mvchip = mvchip;
821 	mvpwm->offset = offset;
822 
823 	if (mvchip->soc_variant == MVEBU_GPIO_SOC_VARIANT_A8K) {
824 		mvpwm->regs = mvchip->regs;
825 
826 		switch (mvchip->offset) {
827 		case AP80X_GPIO0_OFF_A8K:
828 		case CP11X_GPIO0_OFF_A8K:
829 			/* Blink counter A */
830 			set = 0;
831 			break;
832 		case CP11X_GPIO1_OFF_A8K:
833 			/* Blink counter B */
834 			set = U32_MAX;
835 			mvpwm->offset += PWM_BLINK_COUNTER_B_OFF;
836 			break;
837 		default:
838 			return -EINVAL;
839 		}
840 	} else {
841 		base = devm_platform_ioremap_resource_byname(pdev, "pwm");
842 		if (IS_ERR(base))
843 			return PTR_ERR(base);
844 
845 		mvpwm->regs = devm_regmap_init_mmio(&pdev->dev, base,
846 						    &mvebu_gpio_regmap_config);
847 		if (IS_ERR(mvpwm->regs))
848 			return PTR_ERR(mvpwm->regs);
849 
850 		/*
851 		 * Use set A for lines of GPIO chip with id 0, B for GPIO chip
852 		 * with id 1. Don't allow further GPIO chips to be used for PWM.
853 		 */
854 		if (id == 0)
855 			set = 0;
856 		else if (id == 1)
857 			set = U32_MAX;
858 		else
859 			return -EINVAL;
860 	}
861 
862 	regmap_write(mvchip->regs,
863 		     GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset, set);
864 
865 	mvpwm->clk_rate = clk_get_rate(mvchip->clk);
866 	if (!mvpwm->clk_rate) {
867 		dev_err(dev, "failed to get clock rate\n");
868 		return -EINVAL;
869 	}
870 
871 	mvpwm->chip.dev = dev;
872 	mvpwm->chip.ops = &mvebu_pwm_ops;
873 	mvpwm->chip.npwm = mvchip->chip.ngpio;
874 
875 	spin_lock_init(&mvpwm->lock);
876 
877 	return devm_pwmchip_add(dev, &mvpwm->chip);
878 }
879 
880 #ifdef CONFIG_DEBUG_FS
881 #include <linux/seq_file.h>
882 
mvebu_gpio_dbg_show(struct seq_file * s,struct gpio_chip * chip)883 static void mvebu_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
884 {
885 	struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
886 	u32 out, io_conf, blink, in_pol, data_in, cause, edg_msk, lvl_msk;
887 	const char *label;
888 	int i;
889 
890 	regmap_read(mvchip->regs, GPIO_OUT_OFF + mvchip->offset, &out);
891 	regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &io_conf);
892 	regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, &blink);
893 	regmap_read(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset, &in_pol);
894 	regmap_read(mvchip->regs, GPIO_DATA_IN_OFF + mvchip->offset, &data_in);
895 	cause	= mvebu_gpio_read_edge_cause(mvchip);
896 	edg_msk	= mvebu_gpio_read_edge_mask(mvchip);
897 	lvl_msk	= mvebu_gpio_read_level_mask(mvchip);
898 
899 	for_each_requested_gpio(chip, i, label) {
900 		u32 msk;
901 		bool is_out;
902 
903 		msk = BIT(i);
904 		is_out = !(io_conf & msk);
905 
906 		seq_printf(s, " gpio-%-3d (%-20.20s)", chip->base + i, label);
907 
908 		if (is_out) {
909 			seq_printf(s, " out %s %s\n",
910 				   out & msk ? "hi" : "lo",
911 				   blink & msk ? "(blink )" : "");
912 			continue;
913 		}
914 
915 		seq_printf(s, " in  %s (act %s) - IRQ",
916 			   (data_in ^ in_pol) & msk  ? "hi" : "lo",
917 			   in_pol & msk ? "lo" : "hi");
918 		if (!((edg_msk | lvl_msk) & msk)) {
919 			seq_puts(s, " disabled\n");
920 			continue;
921 		}
922 		if (edg_msk & msk)
923 			seq_puts(s, " edge ");
924 		if (lvl_msk & msk)
925 			seq_puts(s, " level");
926 		seq_printf(s, " (%s)\n", cause & msk ? "pending" : "clear  ");
927 	}
928 }
929 #else
930 #define mvebu_gpio_dbg_show NULL
931 #endif
932 
933 static const struct of_device_id mvebu_gpio_of_match[] = {
934 	{
935 		.compatible = "marvell,orion-gpio",
936 		.data	    = (void *) MVEBU_GPIO_SOC_VARIANT_ORION,
937 	},
938 	{
939 		.compatible = "marvell,mv78200-gpio",
940 		.data	    = (void *) MVEBU_GPIO_SOC_VARIANT_MV78200,
941 	},
942 	{
943 		.compatible = "marvell,armadaxp-gpio",
944 		.data	    = (void *) MVEBU_GPIO_SOC_VARIANT_ARMADAXP,
945 	},
946 	{
947 		.compatible = "marvell,armada-370-gpio",
948 		.data	    = (void *) MVEBU_GPIO_SOC_VARIANT_ORION,
949 	},
950 	{
951 		.compatible = "marvell,armada-8k-gpio",
952 		.data       = (void *) MVEBU_GPIO_SOC_VARIANT_A8K,
953 	},
954 	{
955 		/* sentinel */
956 	},
957 };
958 
mvebu_gpio_suspend(struct platform_device * pdev,pm_message_t state)959 static int mvebu_gpio_suspend(struct platform_device *pdev, pm_message_t state)
960 {
961 	struct mvebu_gpio_chip *mvchip = platform_get_drvdata(pdev);
962 	int i;
963 
964 	regmap_read(mvchip->regs, GPIO_OUT_OFF + mvchip->offset,
965 		    &mvchip->out_reg);
966 	regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset,
967 		    &mvchip->io_conf_reg);
968 	regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset,
969 		    &mvchip->blink_en_reg);
970 	regmap_read(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset,
971 		    &mvchip->in_pol_reg);
972 
973 	switch (mvchip->soc_variant) {
974 	case MVEBU_GPIO_SOC_VARIANT_ORION:
975 	case MVEBU_GPIO_SOC_VARIANT_A8K:
976 		regmap_read(mvchip->regs, GPIO_EDGE_MASK_OFF + mvchip->offset,
977 			    &mvchip->edge_mask_regs[0]);
978 		regmap_read(mvchip->regs, GPIO_LEVEL_MASK_OFF + mvchip->offset,
979 			    &mvchip->level_mask_regs[0]);
980 		break;
981 	case MVEBU_GPIO_SOC_VARIANT_MV78200:
982 		for (i = 0; i < 2; i++) {
983 			regmap_read(mvchip->regs,
984 				    GPIO_EDGE_MASK_MV78200_OFF(i),
985 				    &mvchip->edge_mask_regs[i]);
986 			regmap_read(mvchip->regs,
987 				    GPIO_LEVEL_MASK_MV78200_OFF(i),
988 				    &mvchip->level_mask_regs[i]);
989 		}
990 		break;
991 	case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
992 		for (i = 0; i < 4; i++) {
993 			regmap_read(mvchip->regs,
994 				    GPIO_EDGE_MASK_ARMADAXP_OFF(i),
995 				    &mvchip->edge_mask_regs[i]);
996 			regmap_read(mvchip->regs,
997 				    GPIO_LEVEL_MASK_ARMADAXP_OFF(i),
998 				    &mvchip->level_mask_regs[i]);
999 		}
1000 		break;
1001 	default:
1002 		BUG();
1003 	}
1004 
1005 	if (IS_REACHABLE(CONFIG_PWM))
1006 		mvebu_pwm_suspend(mvchip);
1007 
1008 	return 0;
1009 }
1010 
mvebu_gpio_resume(struct platform_device * pdev)1011 static int mvebu_gpio_resume(struct platform_device *pdev)
1012 {
1013 	struct mvebu_gpio_chip *mvchip = platform_get_drvdata(pdev);
1014 	int i;
1015 
1016 	regmap_write(mvchip->regs, GPIO_OUT_OFF + mvchip->offset,
1017 		     mvchip->out_reg);
1018 	regmap_write(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset,
1019 		     mvchip->io_conf_reg);
1020 	regmap_write(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset,
1021 		     mvchip->blink_en_reg);
1022 	regmap_write(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset,
1023 		     mvchip->in_pol_reg);
1024 
1025 	switch (mvchip->soc_variant) {
1026 	case MVEBU_GPIO_SOC_VARIANT_ORION:
1027 	case MVEBU_GPIO_SOC_VARIANT_A8K:
1028 		regmap_write(mvchip->regs, GPIO_EDGE_MASK_OFF + mvchip->offset,
1029 			     mvchip->edge_mask_regs[0]);
1030 		regmap_write(mvchip->regs, GPIO_LEVEL_MASK_OFF + mvchip->offset,
1031 			     mvchip->level_mask_regs[0]);
1032 		break;
1033 	case MVEBU_GPIO_SOC_VARIANT_MV78200:
1034 		for (i = 0; i < 2; i++) {
1035 			regmap_write(mvchip->regs,
1036 				     GPIO_EDGE_MASK_MV78200_OFF(i),
1037 				     mvchip->edge_mask_regs[i]);
1038 			regmap_write(mvchip->regs,
1039 				     GPIO_LEVEL_MASK_MV78200_OFF(i),
1040 				     mvchip->level_mask_regs[i]);
1041 		}
1042 		break;
1043 	case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
1044 		for (i = 0; i < 4; i++) {
1045 			regmap_write(mvchip->regs,
1046 				     GPIO_EDGE_MASK_ARMADAXP_OFF(i),
1047 				     mvchip->edge_mask_regs[i]);
1048 			regmap_write(mvchip->regs,
1049 				     GPIO_LEVEL_MASK_ARMADAXP_OFF(i),
1050 				     mvchip->level_mask_regs[i]);
1051 		}
1052 		break;
1053 	default:
1054 		BUG();
1055 	}
1056 
1057 	if (IS_REACHABLE(CONFIG_PWM))
1058 		mvebu_pwm_resume(mvchip);
1059 
1060 	return 0;
1061 }
1062 
mvebu_gpio_probe_raw(struct platform_device * pdev,struct mvebu_gpio_chip * mvchip)1063 static int mvebu_gpio_probe_raw(struct platform_device *pdev,
1064 				struct mvebu_gpio_chip *mvchip)
1065 {
1066 	void __iomem *base;
1067 
1068 	base = devm_platform_ioremap_resource(pdev, 0);
1069 	if (IS_ERR(base))
1070 		return PTR_ERR(base);
1071 
1072 	mvchip->regs = devm_regmap_init_mmio(&pdev->dev, base,
1073 					     &mvebu_gpio_regmap_config);
1074 	if (IS_ERR(mvchip->regs))
1075 		return PTR_ERR(mvchip->regs);
1076 
1077 	/*
1078 	 * For the legacy SoCs, the regmap directly maps to the GPIO
1079 	 * registers, so no offset is needed.
1080 	 */
1081 	mvchip->offset = 0;
1082 
1083 	/*
1084 	 * The Armada XP has a second range of registers for the
1085 	 * per-CPU registers
1086 	 */
1087 	if (mvchip->soc_variant == MVEBU_GPIO_SOC_VARIANT_ARMADAXP) {
1088 		base = devm_platform_ioremap_resource(pdev, 1);
1089 		if (IS_ERR(base))
1090 			return PTR_ERR(base);
1091 
1092 		mvchip->percpu_regs =
1093 			devm_regmap_init_mmio(&pdev->dev, base,
1094 					      &mvebu_gpio_regmap_config);
1095 		if (IS_ERR(mvchip->percpu_regs))
1096 			return PTR_ERR(mvchip->percpu_regs);
1097 	}
1098 
1099 	return 0;
1100 }
1101 
mvebu_gpio_probe_syscon(struct platform_device * pdev,struct mvebu_gpio_chip * mvchip)1102 static int mvebu_gpio_probe_syscon(struct platform_device *pdev,
1103 				   struct mvebu_gpio_chip *mvchip)
1104 {
1105 	mvchip->regs = syscon_node_to_regmap(pdev->dev.parent->of_node);
1106 	if (IS_ERR(mvchip->regs))
1107 		return PTR_ERR(mvchip->regs);
1108 
1109 	if (of_property_read_u32(pdev->dev.of_node, "offset", &mvchip->offset))
1110 		return -EINVAL;
1111 
1112 	return 0;
1113 }
1114 
mvebu_gpio_remove_irq_domain(void * data)1115 static void mvebu_gpio_remove_irq_domain(void *data)
1116 {
1117 	struct irq_domain *domain = data;
1118 
1119 	irq_domain_remove(domain);
1120 }
1121 
mvebu_gpio_probe(struct platform_device * pdev)1122 static int mvebu_gpio_probe(struct platform_device *pdev)
1123 {
1124 	struct mvebu_gpio_chip *mvchip;
1125 	const struct of_device_id *match;
1126 	struct device_node *np = pdev->dev.of_node;
1127 	struct irq_chip_generic *gc;
1128 	struct irq_chip_type *ct;
1129 	unsigned int ngpios;
1130 	bool have_irqs;
1131 	int soc_variant;
1132 	int i, cpu, id;
1133 	int err;
1134 
1135 	match = of_match_device(mvebu_gpio_of_match, &pdev->dev);
1136 	if (match)
1137 		soc_variant = (unsigned long) match->data;
1138 	else
1139 		soc_variant = MVEBU_GPIO_SOC_VARIANT_ORION;
1140 
1141 	/* Some gpio controllers do not provide irq support */
1142 	err = platform_irq_count(pdev);
1143 	if (err < 0)
1144 		return err;
1145 
1146 	have_irqs = err != 0;
1147 
1148 	mvchip = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_gpio_chip),
1149 			      GFP_KERNEL);
1150 	if (!mvchip)
1151 		return -ENOMEM;
1152 
1153 	platform_set_drvdata(pdev, mvchip);
1154 
1155 	if (of_property_read_u32(pdev->dev.of_node, "ngpios", &ngpios)) {
1156 		dev_err(&pdev->dev, "Missing ngpios OF property\n");
1157 		return -ENODEV;
1158 	}
1159 
1160 	id = of_alias_get_id(pdev->dev.of_node, "gpio");
1161 	if (id < 0) {
1162 		dev_err(&pdev->dev, "Couldn't get OF id\n");
1163 		return id;
1164 	}
1165 
1166 	mvchip->clk = devm_clk_get(&pdev->dev, NULL);
1167 	/* Not all SoCs require a clock.*/
1168 	if (!IS_ERR(mvchip->clk))
1169 		clk_prepare_enable(mvchip->clk);
1170 
1171 	mvchip->soc_variant = soc_variant;
1172 	mvchip->chip.label = dev_name(&pdev->dev);
1173 	mvchip->chip.parent = &pdev->dev;
1174 	mvchip->chip.request = gpiochip_generic_request;
1175 	mvchip->chip.free = gpiochip_generic_free;
1176 	mvchip->chip.get_direction = mvebu_gpio_get_direction;
1177 	mvchip->chip.direction_input = mvebu_gpio_direction_input;
1178 	mvchip->chip.get = mvebu_gpio_get;
1179 	mvchip->chip.direction_output = mvebu_gpio_direction_output;
1180 	mvchip->chip.set = mvebu_gpio_set;
1181 	if (have_irqs)
1182 		mvchip->chip.to_irq = mvebu_gpio_to_irq;
1183 	mvchip->chip.base = id * MVEBU_MAX_GPIO_PER_BANK;
1184 	mvchip->chip.ngpio = ngpios;
1185 	mvchip->chip.can_sleep = false;
1186 	mvchip->chip.dbg_show = mvebu_gpio_dbg_show;
1187 
1188 	if (soc_variant == MVEBU_GPIO_SOC_VARIANT_A8K)
1189 		err = mvebu_gpio_probe_syscon(pdev, mvchip);
1190 	else
1191 		err = mvebu_gpio_probe_raw(pdev, mvchip);
1192 
1193 	if (err)
1194 		return err;
1195 
1196 	/*
1197 	 * Mask and clear GPIO interrupts.
1198 	 */
1199 	switch (soc_variant) {
1200 	case MVEBU_GPIO_SOC_VARIANT_ORION:
1201 	case MVEBU_GPIO_SOC_VARIANT_A8K:
1202 		regmap_write(mvchip->regs,
1203 			     GPIO_EDGE_CAUSE_OFF + mvchip->offset, 0);
1204 		regmap_write(mvchip->regs,
1205 			     GPIO_EDGE_MASK_OFF + mvchip->offset, 0);
1206 		regmap_write(mvchip->regs,
1207 			     GPIO_LEVEL_MASK_OFF + mvchip->offset, 0);
1208 		break;
1209 	case MVEBU_GPIO_SOC_VARIANT_MV78200:
1210 		regmap_write(mvchip->regs, GPIO_EDGE_CAUSE_OFF, 0);
1211 		for (cpu = 0; cpu < 2; cpu++) {
1212 			regmap_write(mvchip->regs,
1213 				     GPIO_EDGE_MASK_MV78200_OFF(cpu), 0);
1214 			regmap_write(mvchip->regs,
1215 				     GPIO_LEVEL_MASK_MV78200_OFF(cpu), 0);
1216 		}
1217 		break;
1218 	case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
1219 		regmap_write(mvchip->regs, GPIO_EDGE_CAUSE_OFF, 0);
1220 		regmap_write(mvchip->regs, GPIO_EDGE_MASK_OFF, 0);
1221 		regmap_write(mvchip->regs, GPIO_LEVEL_MASK_OFF, 0);
1222 		for (cpu = 0; cpu < 4; cpu++) {
1223 			regmap_write(mvchip->percpu_regs,
1224 				     GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu), 0);
1225 			regmap_write(mvchip->percpu_regs,
1226 				     GPIO_EDGE_MASK_ARMADAXP_OFF(cpu), 0);
1227 			regmap_write(mvchip->percpu_regs,
1228 				     GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu), 0);
1229 		}
1230 		break;
1231 	default:
1232 		BUG();
1233 	}
1234 
1235 	devm_gpiochip_add_data(&pdev->dev, &mvchip->chip, mvchip);
1236 
1237 	/* Some MVEBU SoCs have simple PWM support for GPIO lines */
1238 	if (IS_REACHABLE(CONFIG_PWM)) {
1239 		err = mvebu_pwm_probe(pdev, mvchip, id);
1240 		if (err)
1241 			return err;
1242 	}
1243 
1244 	/* Some gpio controllers do not provide irq support */
1245 	if (!have_irqs)
1246 		return 0;
1247 
1248 	mvchip->domain =
1249 	    irq_domain_add_linear(np, ngpios, &irq_generic_chip_ops, NULL);
1250 	if (!mvchip->domain) {
1251 		dev_err(&pdev->dev, "couldn't allocate irq domain %s (DT).\n",
1252 			mvchip->chip.label);
1253 		return -ENODEV;
1254 	}
1255 
1256 	err = devm_add_action_or_reset(&pdev->dev, mvebu_gpio_remove_irq_domain,
1257 				       mvchip->domain);
1258 	if (err)
1259 		return err;
1260 
1261 	err = irq_alloc_domain_generic_chips(
1262 	    mvchip->domain, ngpios, 2, np->name, handle_level_irq,
1263 	    IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_LEVEL, 0, 0);
1264 	if (err) {
1265 		dev_err(&pdev->dev, "couldn't allocate irq chips %s (DT).\n",
1266 			mvchip->chip.label);
1267 		return err;
1268 	}
1269 
1270 	/*
1271 	 * NOTE: The common accessors cannot be used because of the percpu
1272 	 * access to the mask registers
1273 	 */
1274 	gc = irq_get_domain_generic_chip(mvchip->domain, 0);
1275 	gc->private = mvchip;
1276 	ct = &gc->chip_types[0];
1277 	ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW;
1278 	ct->chip.irq_mask = mvebu_gpio_level_irq_mask;
1279 	ct->chip.irq_unmask = mvebu_gpio_level_irq_unmask;
1280 	ct->chip.irq_set_type = mvebu_gpio_irq_set_type;
1281 	ct->chip.name = mvchip->chip.label;
1282 
1283 	ct = &gc->chip_types[1];
1284 	ct->type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
1285 	ct->chip.irq_ack = mvebu_gpio_irq_ack;
1286 	ct->chip.irq_mask = mvebu_gpio_edge_irq_mask;
1287 	ct->chip.irq_unmask = mvebu_gpio_edge_irq_unmask;
1288 	ct->chip.irq_set_type = mvebu_gpio_irq_set_type;
1289 	ct->handler = handle_edge_irq;
1290 	ct->chip.name = mvchip->chip.label;
1291 
1292 	/*
1293 	 * Setup the interrupt handlers. Each chip can have up to 4
1294 	 * interrupt handlers, with each handler dealing with 8 GPIO
1295 	 * pins.
1296 	 */
1297 	for (i = 0; i < 4; i++) {
1298 		int irq = platform_get_irq_optional(pdev, i);
1299 
1300 		if (irq < 0)
1301 			continue;
1302 		irq_set_chained_handler_and_data(irq, mvebu_gpio_irq_handler,
1303 						 mvchip);
1304 	}
1305 
1306 	return 0;
1307 }
1308 
1309 static struct platform_driver mvebu_gpio_driver = {
1310 	.driver		= {
1311 		.name		= "mvebu-gpio",
1312 		.of_match_table = mvebu_gpio_of_match,
1313 	},
1314 	.probe		= mvebu_gpio_probe,
1315 	.suspend        = mvebu_gpio_suspend,
1316 	.resume         = mvebu_gpio_resume,
1317 };
1318 builtin_platform_driver(mvebu_gpio_driver);
1319