1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2000
4 * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it
5 *
6 * (C) Copyright 2000 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7 * Marius Groeger <mgroeger@sysgo.de>
8 *
9 * (C) Copyright 2003 Pengutronix e.K.
10 * Robert Schwebel <r.schwebel@pengutronix.de>
11 *
12 * (C) Copyright 2011 Marvell Inc.
13 * Lei Wen <leiwen@marvell.com>
14 *
15 * Back ported to the 8xx platform (from the 8260 platform) by
16 * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
17 */
18
19 #include <common.h>
20 #include <dm.h>
21 #include <i2c.h>
22 #include <asm/io.h>
23 #include "mv_i2c.h"
24
25 /* All transfers are described by this data structure */
26 struct mv_i2c_msg {
27 u8 condition;
28 u8 acknack;
29 u8 direction;
30 u8 data;
31 };
32
33 #ifdef CONFIG_ARMADA_3700
34 /* Armada 3700 has no padding between the registers */
35 struct mv_i2c {
36 u32 ibmr;
37 u32 idbr;
38 u32 icr;
39 u32 isr;
40 u32 isar;
41 };
42 #else
43 struct mv_i2c {
44 u32 ibmr;
45 u32 pad0;
46 u32 idbr;
47 u32 pad1;
48 u32 icr;
49 u32 pad2;
50 u32 isr;
51 u32 pad3;
52 u32 isar;
53 };
54 #endif
55
56 /*
57 * Dummy implementation that can be overwritten by a board
58 * specific function
59 */
i2c_clk_enable(void)60 __weak void i2c_clk_enable(void)
61 {
62 }
63
64 /*
65 * i2c_reset: - reset the host controller
66 *
67 */
i2c_reset(struct mv_i2c * base)68 static void i2c_reset(struct mv_i2c *base)
69 {
70 u32 icr_mode;
71
72 /* Save bus mode (standard or fast speed) for later use */
73 icr_mode = readl(&base->icr) & ICR_MODE_MASK;
74 writel(readl(&base->icr) & ~ICR_IUE, &base->icr); /* disable unit */
75 writel(readl(&base->icr) | ICR_UR, &base->icr); /* reset the unit */
76 udelay(100);
77 writel(readl(&base->icr) & ~ICR_IUE, &base->icr); /* disable unit */
78
79 i2c_clk_enable();
80
81 writel(CONFIG_SYS_I2C_SLAVE, &base->isar); /* set our slave address */
82 /* set control reg values */
83 writel(I2C_ICR_INIT | icr_mode, &base->icr);
84 writel(I2C_ISR_INIT, &base->isr); /* set clear interrupt bits */
85 writel(readl(&base->icr) | ICR_IUE, &base->icr); /* enable unit */
86 udelay(100);
87 }
88
89 /*
90 * i2c_isr_set_cleared: - wait until certain bits of the I2C status register
91 * are set and cleared
92 *
93 * @return: 1 in case of success, 0 means timeout (no match within 10 ms).
94 */
i2c_isr_set_cleared(struct mv_i2c * base,unsigned long set_mask,unsigned long cleared_mask)95 static int i2c_isr_set_cleared(struct mv_i2c *base, unsigned long set_mask,
96 unsigned long cleared_mask)
97 {
98 int timeout = 1000, isr;
99
100 do {
101 isr = readl(&base->isr);
102 udelay(10);
103 if (timeout-- < 0)
104 return 0;
105 } while (((isr & set_mask) != set_mask)
106 || ((isr & cleared_mask) != 0));
107
108 return 1;
109 }
110
111 /*
112 * i2c_transfer: - Transfer one byte over the i2c bus
113 *
114 * This function can tranfer a byte over the i2c bus in both directions.
115 * It is used by the public API functions.
116 *
117 * @return: 0: transfer successful
118 * -1: message is empty
119 * -2: transmit timeout
120 * -3: ACK missing
121 * -4: receive timeout
122 * -5: illegal parameters
123 * -6: bus is busy and couldn't be aquired
124 */
i2c_transfer(struct mv_i2c * base,struct mv_i2c_msg * msg)125 static int i2c_transfer(struct mv_i2c *base, struct mv_i2c_msg *msg)
126 {
127 int ret;
128
129 if (!msg)
130 goto transfer_error_msg_empty;
131
132 switch (msg->direction) {
133 case I2C_WRITE:
134 /* check if bus is not busy */
135 if (!i2c_isr_set_cleared(base, 0, ISR_IBB))
136 goto transfer_error_bus_busy;
137
138 /* start transmission */
139 writel(readl(&base->icr) & ~ICR_START, &base->icr);
140 writel(readl(&base->icr) & ~ICR_STOP, &base->icr);
141 writel(msg->data, &base->idbr);
142 if (msg->condition == I2C_COND_START)
143 writel(readl(&base->icr) | ICR_START, &base->icr);
144 if (msg->condition == I2C_COND_STOP)
145 writel(readl(&base->icr) | ICR_STOP, &base->icr);
146 if (msg->acknack == I2C_ACKNAK_SENDNAK)
147 writel(readl(&base->icr) | ICR_ACKNAK, &base->icr);
148 if (msg->acknack == I2C_ACKNAK_SENDACK)
149 writel(readl(&base->icr) & ~ICR_ACKNAK, &base->icr);
150 writel(readl(&base->icr) & ~ICR_ALDIE, &base->icr);
151 writel(readl(&base->icr) | ICR_TB, &base->icr);
152
153 /* transmit register empty? */
154 if (!i2c_isr_set_cleared(base, ISR_ITE, 0))
155 goto transfer_error_transmit_timeout;
156
157 /* clear 'transmit empty' state */
158 writel(readl(&base->isr) | ISR_ITE, &base->isr);
159
160 /* wait for ACK from slave */
161 if (msg->acknack == I2C_ACKNAK_WAITACK)
162 if (!i2c_isr_set_cleared(base, 0, ISR_ACKNAK))
163 goto transfer_error_ack_missing;
164 break;
165
166 case I2C_READ:
167
168 /* check if bus is not busy */
169 if (!i2c_isr_set_cleared(base, 0, ISR_IBB))
170 goto transfer_error_bus_busy;
171
172 /* start receive */
173 writel(readl(&base->icr) & ~ICR_START, &base->icr);
174 writel(readl(&base->icr) & ~ICR_STOP, &base->icr);
175 if (msg->condition == I2C_COND_START)
176 writel(readl(&base->icr) | ICR_START, &base->icr);
177 if (msg->condition == I2C_COND_STOP)
178 writel(readl(&base->icr) | ICR_STOP, &base->icr);
179 if (msg->acknack == I2C_ACKNAK_SENDNAK)
180 writel(readl(&base->icr) | ICR_ACKNAK, &base->icr);
181 if (msg->acknack == I2C_ACKNAK_SENDACK)
182 writel(readl(&base->icr) & ~ICR_ACKNAK, &base->icr);
183 writel(readl(&base->icr) & ~ICR_ALDIE, &base->icr);
184 writel(readl(&base->icr) | ICR_TB, &base->icr);
185
186 /* receive register full? */
187 if (!i2c_isr_set_cleared(base, ISR_IRF, 0))
188 goto transfer_error_receive_timeout;
189
190 msg->data = readl(&base->idbr);
191
192 /* clear 'receive empty' state */
193 writel(readl(&base->isr) | ISR_IRF, &base->isr);
194 break;
195 default:
196 goto transfer_error_illegal_param;
197 }
198
199 return 0;
200
201 transfer_error_msg_empty:
202 debug("i2c_transfer: error: 'msg' is empty\n");
203 ret = -1;
204 goto i2c_transfer_finish;
205
206 transfer_error_transmit_timeout:
207 debug("i2c_transfer: error: transmit timeout\n");
208 ret = -2;
209 goto i2c_transfer_finish;
210
211 transfer_error_ack_missing:
212 debug("i2c_transfer: error: ACK missing\n");
213 ret = -3;
214 goto i2c_transfer_finish;
215
216 transfer_error_receive_timeout:
217 debug("i2c_transfer: error: receive timeout\n");
218 ret = -4;
219 goto i2c_transfer_finish;
220
221 transfer_error_illegal_param:
222 debug("i2c_transfer: error: illegal parameters\n");
223 ret = -5;
224 goto i2c_transfer_finish;
225
226 transfer_error_bus_busy:
227 debug("i2c_transfer: error: bus is busy\n");
228 ret = -6;
229 goto i2c_transfer_finish;
230
231 i2c_transfer_finish:
232 debug("i2c_transfer: ISR: 0x%04x\n", readl(&base->isr));
233 i2c_reset(base);
234 return ret;
235 }
236
__i2c_read(struct mv_i2c * base,uchar chip,u8 * addr,int alen,uchar * buffer,int len)237 static int __i2c_read(struct mv_i2c *base, uchar chip, u8 *addr, int alen,
238 uchar *buffer, int len)
239 {
240 struct mv_i2c_msg msg;
241
242 debug("i2c_read(chip=0x%02x, addr=0x%02x, alen=0x%02x, "
243 "len=0x%02x)\n", chip, *addr, alen, len);
244
245 if (len == 0) {
246 printf("reading zero byte is invalid\n");
247 return -EINVAL;
248 }
249
250 i2c_reset(base);
251
252 /* dummy chip address write */
253 debug("i2c_read: dummy chip address write\n");
254 msg.condition = I2C_COND_START;
255 msg.acknack = I2C_ACKNAK_WAITACK;
256 msg.direction = I2C_WRITE;
257 msg.data = (chip << 1);
258 msg.data &= 0xFE;
259 if (i2c_transfer(base, &msg))
260 return -1;
261
262 /*
263 * send memory address bytes;
264 * alen defines how much bytes we have to send.
265 */
266 while (--alen >= 0) {
267 debug("i2c_read: send address byte %02x (alen=%d)\n",
268 *addr, alen);
269 msg.condition = I2C_COND_NORMAL;
270 msg.acknack = I2C_ACKNAK_WAITACK;
271 msg.direction = I2C_WRITE;
272 msg.data = addr[alen];
273 if (i2c_transfer(base, &msg))
274 return -1;
275 }
276
277 /* start read sequence */
278 debug("i2c_read: start read sequence\n");
279 msg.condition = I2C_COND_START;
280 msg.acknack = I2C_ACKNAK_WAITACK;
281 msg.direction = I2C_WRITE;
282 msg.data = (chip << 1);
283 msg.data |= 0x01;
284 if (i2c_transfer(base, &msg))
285 return -1;
286
287 /* read bytes; send NACK at last byte */
288 while (len--) {
289 if (len == 0) {
290 msg.condition = I2C_COND_STOP;
291 msg.acknack = I2C_ACKNAK_SENDNAK;
292 } else {
293 msg.condition = I2C_COND_NORMAL;
294 msg.acknack = I2C_ACKNAK_SENDACK;
295 }
296
297 msg.direction = I2C_READ;
298 msg.data = 0x00;
299 if (i2c_transfer(base, &msg))
300 return -1;
301
302 *buffer = msg.data;
303 debug("i2c_read: reading byte (%p)=0x%02x\n",
304 buffer, *buffer);
305 buffer++;
306 }
307
308 i2c_reset(base);
309
310 return 0;
311 }
312
__i2c_write(struct mv_i2c * base,uchar chip,u8 * addr,int alen,uchar * buffer,int len)313 static int __i2c_write(struct mv_i2c *base, uchar chip, u8 *addr, int alen,
314 uchar *buffer, int len)
315 {
316 struct mv_i2c_msg msg;
317
318 debug("i2c_write(chip=0x%02x, addr=0x%02x, alen=0x%02x, "
319 "len=0x%02x)\n", chip, *addr, alen, len);
320
321 i2c_reset(base);
322
323 /* chip address write */
324 debug("i2c_write: chip address write\n");
325 msg.condition = I2C_COND_START;
326 msg.acknack = I2C_ACKNAK_WAITACK;
327 msg.direction = I2C_WRITE;
328 msg.data = (chip << 1);
329 msg.data &= 0xFE;
330 if (i2c_transfer(base, &msg))
331 return -1;
332
333 /*
334 * send memory address bytes;
335 * alen defines how much bytes we have to send.
336 */
337 while (--alen >= 0) {
338 debug("i2c_read: send address byte %02x (alen=%d)\n",
339 *addr, alen);
340 msg.condition = I2C_COND_NORMAL;
341 msg.acknack = I2C_ACKNAK_WAITACK;
342 msg.direction = I2C_WRITE;
343 msg.data = addr[alen];
344 if (i2c_transfer(base, &msg))
345 return -1;
346 }
347
348 /* write bytes; send NACK at last byte */
349 while (len--) {
350 debug("i2c_write: writing byte (%p)=0x%02x\n",
351 buffer, *buffer);
352
353 if (len == 0)
354 msg.condition = I2C_COND_STOP;
355 else
356 msg.condition = I2C_COND_NORMAL;
357
358 msg.acknack = I2C_ACKNAK_WAITACK;
359 msg.direction = I2C_WRITE;
360 msg.data = *(buffer++);
361
362 if (i2c_transfer(base, &msg))
363 return -1;
364 }
365
366 i2c_reset(base);
367
368 return 0;
369 }
370
371 #ifndef CONFIG_DM_I2C
372
373 static struct mv_i2c *base_glob;
374
i2c_board_init(struct mv_i2c * base)375 static void i2c_board_init(struct mv_i2c *base)
376 {
377 #ifdef CONFIG_SYS_I2C_INIT_BOARD
378 u32 icr;
379 /*
380 * call board specific i2c bus reset routine before accessing the
381 * environment, which might be in a chip on that bus. For details
382 * about this problem see doc/I2C_Edge_Conditions.
383 *
384 * disable I2C controller first, otherwhise it thinks we want to
385 * talk to the slave port...
386 */
387 icr = readl(&base->icr);
388 writel(readl(&base->icr) & ~(ICR_SCLE | ICR_IUE), &base->icr);
389
390 i2c_init_board();
391
392 writel(icr, &base->icr);
393 #endif
394 }
395
396 #ifdef CONFIG_I2C_MULTI_BUS
397 static unsigned long i2c_regs[CONFIG_MV_I2C_NUM] = CONFIG_MV_I2C_REG;
398 static unsigned int bus_initialized[CONFIG_MV_I2C_NUM];
399 static unsigned int current_bus;
400
i2c_set_bus_num(unsigned int bus)401 int i2c_set_bus_num(unsigned int bus)
402 {
403 if ((bus < 0) || (bus >= CONFIG_MV_I2C_NUM)) {
404 printf("Bad bus: %d\n", bus);
405 return -1;
406 }
407
408 base_glob = (struct mv_i2c *)i2c_regs[bus];
409 current_bus = bus;
410
411 if (!bus_initialized[current_bus]) {
412 i2c_board_init(base_glob);
413 bus_initialized[current_bus] = 1;
414 }
415
416 return 0;
417 }
418
i2c_get_bus_num(void)419 unsigned int i2c_get_bus_num(void)
420 {
421 return current_bus;
422 }
423 #endif
424
425 /* API Functions */
i2c_init(int speed,int slaveaddr)426 void i2c_init(int speed, int slaveaddr)
427 {
428 u32 val;
429
430 #ifdef CONFIG_I2C_MULTI_BUS
431 current_bus = 0;
432 base_glob = (struct mv_i2c *)i2c_regs[current_bus];
433 #else
434 base_glob = (struct mv_i2c *)CONFIG_MV_I2C_REG;
435 #endif
436
437 if (speed > 100000)
438 val = ICR_FM;
439 else
440 val = ICR_SM;
441 clrsetbits_le32(&base_glob->icr, ICR_MODE_MASK, val);
442
443 i2c_board_init(base_glob);
444 }
445
__i2c_probe_chip(struct mv_i2c * base,uchar chip)446 static int __i2c_probe_chip(struct mv_i2c *base, uchar chip)
447 {
448 struct mv_i2c_msg msg;
449
450 i2c_reset(base);
451
452 msg.condition = I2C_COND_START;
453 msg.acknack = I2C_ACKNAK_WAITACK;
454 msg.direction = I2C_WRITE;
455 msg.data = (chip << 1) + 1;
456 if (i2c_transfer(base, &msg))
457 return -1;
458
459 msg.condition = I2C_COND_STOP;
460 msg.acknack = I2C_ACKNAK_SENDNAK;
461 msg.direction = I2C_READ;
462 msg.data = 0x00;
463 if (i2c_transfer(base, &msg))
464 return -1;
465
466 return 0;
467 }
468
469 /*
470 * i2c_probe: - Test if a chip answers for a given i2c address
471 *
472 * @chip: address of the chip which is searched for
473 * @return: 0 if a chip was found, -1 otherwhise
474 */
i2c_probe(uchar chip)475 int i2c_probe(uchar chip)
476 {
477 return __i2c_probe_chip(base_glob, chip);
478 }
479
480 /*
481 * i2c_read: - Read multiple bytes from an i2c device
482 *
483 * The higher level routines take into account that this function is only
484 * called with len < page length of the device (see configuration file)
485 *
486 * @chip: address of the chip which is to be read
487 * @addr: i2c data address within the chip
488 * @alen: length of the i2c data address (1..2 bytes)
489 * @buffer: where to write the data
490 * @len: how much byte do we want to read
491 * @return: 0 in case of success
492 */
i2c_read(uchar chip,uint addr,int alen,uchar * buffer,int len)493 int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
494 {
495 u8 addr_bytes[4];
496
497 addr_bytes[0] = (addr >> 0) & 0xFF;
498 addr_bytes[1] = (addr >> 8) & 0xFF;
499 addr_bytes[2] = (addr >> 16) & 0xFF;
500 addr_bytes[3] = (addr >> 24) & 0xFF;
501
502 return __i2c_read(base_glob, chip, addr_bytes, alen, buffer, len);
503 }
504
505 /*
506 * i2c_write: - Write multiple bytes to an i2c device
507 *
508 * The higher level routines take into account that this function is only
509 * called with len < page length of the device (see configuration file)
510 *
511 * @chip: address of the chip which is to be written
512 * @addr: i2c data address within the chip
513 * @alen: length of the i2c data address (1..2 bytes)
514 * @buffer: where to find the data to be written
515 * @len: how much byte do we want to read
516 * @return: 0 in case of success
517 */
i2c_write(uchar chip,uint addr,int alen,uchar * buffer,int len)518 int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
519 {
520 u8 addr_bytes[4];
521
522 addr_bytes[0] = (addr >> 0) & 0xFF;
523 addr_bytes[1] = (addr >> 8) & 0xFF;
524 addr_bytes[2] = (addr >> 16) & 0xFF;
525 addr_bytes[3] = (addr >> 24) & 0xFF;
526
527 return __i2c_write(base_glob, chip, addr_bytes, alen, buffer, len);
528 }
529
530 #else /* CONFIG_DM_I2C */
531
532 struct mv_i2c_priv {
533 struct mv_i2c *base;
534 };
535
mv_i2c_xfer(struct udevice * bus,struct i2c_msg * msg,int nmsgs)536 static int mv_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
537 {
538 struct mv_i2c_priv *i2c = dev_get_priv(bus);
539 struct i2c_msg *dmsg, *omsg, dummy;
540
541 memset(&dummy, 0, sizeof(struct i2c_msg));
542
543 /*
544 * We expect either two messages (one with an offset and one with the
545 * actual data) or one message (just data or offset/data combined)
546 */
547 if (nmsgs > 2 || nmsgs == 0) {
548 debug("%s: Only one or two messages are supported.", __func__);
549 return -1;
550 }
551
552 omsg = nmsgs == 1 ? &dummy : msg;
553 dmsg = nmsgs == 1 ? msg : msg + 1;
554
555 if (dmsg->flags & I2C_M_RD)
556 return __i2c_read(i2c->base, dmsg->addr, omsg->buf,
557 omsg->len, dmsg->buf, dmsg->len);
558 else
559 return __i2c_write(i2c->base, dmsg->addr, omsg->buf,
560 omsg->len, dmsg->buf, dmsg->len);
561 }
562
mv_i2c_set_bus_speed(struct udevice * bus,unsigned int speed)563 static int mv_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
564 {
565 struct mv_i2c_priv *priv = dev_get_priv(bus);
566 u32 val;
567
568 if (speed > 100000)
569 val = ICR_FM;
570 else
571 val = ICR_SM;
572 clrsetbits_le32(&priv->base->icr, ICR_MODE_MASK, val);
573
574 return 0;
575 }
576
mv_i2c_probe(struct udevice * bus)577 static int mv_i2c_probe(struct udevice *bus)
578 {
579 struct mv_i2c_priv *priv = dev_get_priv(bus);
580
581 priv->base = (void *)devfdt_get_addr_ptr(bus);
582
583 return 0;
584 }
585
586 static const struct dm_i2c_ops mv_i2c_ops = {
587 .xfer = mv_i2c_xfer,
588 .set_bus_speed = mv_i2c_set_bus_speed,
589 };
590
591 static const struct udevice_id mv_i2c_ids[] = {
592 { .compatible = "marvell,armada-3700-i2c" },
593 { }
594 };
595
596 U_BOOT_DRIVER(i2c_mv) = {
597 .name = "i2c_mv",
598 .id = UCLASS_I2C,
599 .of_match = mv_i2c_ids,
600 .probe = mv_i2c_probe,
601 .priv_auto_alloc_size = sizeof(struct mv_i2c_priv),
602 .ops = &mv_i2c_ops,
603 };
604 #endif /* CONFIG_DM_I2C */
605