1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Marvell 88e6xxx Ethernet switch single-chip support
4 *
5 * Copyright (c) 2008 Marvell Semiconductor
6 *
7 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
8 *
9 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
10 * Vivien Didelot <vivien.didelot@savoirfairelinux.com>
11 */
12
13 #include <linux/bitfield.h>
14 #include <linux/delay.h>
15 #include <linux/dsa/mv88e6xxx.h>
16 #include <linux/etherdevice.h>
17 #include <linux/ethtool.h>
18 #include <linux/if_bridge.h>
19 #include <linux/interrupt.h>
20 #include <linux/irq.h>
21 #include <linux/irqdomain.h>
22 #include <linux/jiffies.h>
23 #include <linux/list.h>
24 #include <linux/mdio.h>
25 #include <linux/module.h>
26 #include <linux/of.h>
27 #include <linux/of_irq.h>
28 #include <linux/of_mdio.h>
29 #include <linux/platform_data/mv88e6xxx.h>
30 #include <linux/netdevice.h>
31 #include <linux/gpio/consumer.h>
32 #include <linux/phylink.h>
33 #include <net/dsa.h>
34
35 #include "chip.h"
36 #include "devlink.h"
37 #include "global1.h"
38 #include "global2.h"
39 #include "hwtstamp.h"
40 #include "phy.h"
41 #include "port.h"
42 #include "ptp.h"
43 #include "serdes.h"
44 #include "smi.h"
45
assert_reg_lock(struct mv88e6xxx_chip * chip)46 static void assert_reg_lock(struct mv88e6xxx_chip *chip)
47 {
48 if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
49 dev_err(chip->dev, "Switch registers lock not held!\n");
50 dump_stack();
51 }
52 }
53
mv88e6xxx_read(struct mv88e6xxx_chip * chip,int addr,int reg,u16 * val)54 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val)
55 {
56 int err;
57
58 assert_reg_lock(chip);
59
60 err = mv88e6xxx_smi_read(chip, addr, reg, val);
61 if (err)
62 return err;
63
64 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
65 addr, reg, *val);
66
67 return 0;
68 }
69
mv88e6xxx_write(struct mv88e6xxx_chip * chip,int addr,int reg,u16 val)70 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val)
71 {
72 int err;
73
74 assert_reg_lock(chip);
75
76 err = mv88e6xxx_smi_write(chip, addr, reg, val);
77 if (err)
78 return err;
79
80 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
81 addr, reg, val);
82
83 return 0;
84 }
85
mv88e6xxx_wait_mask(struct mv88e6xxx_chip * chip,int addr,int reg,u16 mask,u16 val)86 int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg,
87 u16 mask, u16 val)
88 {
89 const unsigned long timeout = jiffies + msecs_to_jiffies(50);
90 u16 data;
91 int err;
92 int i;
93
94 /* There's no bus specific operation to wait for a mask. Even
95 * if the initial poll takes longer than 50ms, always do at
96 * least one more attempt.
97 */
98 for (i = 0; time_before(jiffies, timeout) || (i < 2); i++) {
99 err = mv88e6xxx_read(chip, addr, reg, &data);
100 if (err)
101 return err;
102
103 if ((data & mask) == val)
104 return 0;
105
106 if (i < 2)
107 cpu_relax();
108 else
109 usleep_range(1000, 2000);
110 }
111
112 err = mv88e6xxx_read(chip, addr, reg, &data);
113 if (err)
114 return err;
115
116 if ((data & mask) == val)
117 return 0;
118
119 dev_err(chip->dev, "Timeout while waiting for switch\n");
120 return -ETIMEDOUT;
121 }
122
mv88e6xxx_wait_bit(struct mv88e6xxx_chip * chip,int addr,int reg,int bit,int val)123 int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg,
124 int bit, int val)
125 {
126 return mv88e6xxx_wait_mask(chip, addr, reg, BIT(bit),
127 val ? BIT(bit) : 0x0000);
128 }
129
mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip * chip)130 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip)
131 {
132 struct mv88e6xxx_mdio_bus *mdio_bus;
133
134 mdio_bus = list_first_entry_or_null(&chip->mdios,
135 struct mv88e6xxx_mdio_bus, list);
136 if (!mdio_bus)
137 return NULL;
138
139 return mdio_bus->bus;
140 }
141
mv88e6xxx_g1_irq_mask(struct irq_data * d)142 static void mv88e6xxx_g1_irq_mask(struct irq_data *d)
143 {
144 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
145 unsigned int n = d->hwirq;
146
147 chip->g1_irq.masked |= (1 << n);
148 }
149
mv88e6xxx_g1_irq_unmask(struct irq_data * d)150 static void mv88e6xxx_g1_irq_unmask(struct irq_data *d)
151 {
152 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
153 unsigned int n = d->hwirq;
154
155 chip->g1_irq.masked &= ~(1 << n);
156 }
157
mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip * chip)158 static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip)
159 {
160 unsigned int nhandled = 0;
161 unsigned int sub_irq;
162 unsigned int n;
163 u16 reg;
164 u16 ctl1;
165 int err;
166
167 mv88e6xxx_reg_lock(chip);
168 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®);
169 mv88e6xxx_reg_unlock(chip);
170
171 if (err)
172 goto out;
173
174 do {
175 for (n = 0; n < chip->g1_irq.nirqs; ++n) {
176 if (reg & (1 << n)) {
177 sub_irq = irq_find_mapping(chip->g1_irq.domain,
178 n);
179 handle_nested_irq(sub_irq);
180 ++nhandled;
181 }
182 }
183
184 mv88e6xxx_reg_lock(chip);
185 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &ctl1);
186 if (err)
187 goto unlock;
188 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®);
189 unlock:
190 mv88e6xxx_reg_unlock(chip);
191 if (err)
192 goto out;
193 ctl1 &= GENMASK(chip->g1_irq.nirqs, 0);
194 } while (reg & ctl1);
195
196 out:
197 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
198 }
199
mv88e6xxx_g1_irq_thread_fn(int irq,void * dev_id)200 static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id)
201 {
202 struct mv88e6xxx_chip *chip = dev_id;
203
204 return mv88e6xxx_g1_irq_thread_work(chip);
205 }
206
mv88e6xxx_g1_irq_bus_lock(struct irq_data * d)207 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d)
208 {
209 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
210
211 mv88e6xxx_reg_lock(chip);
212 }
213
mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data * d)214 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d)
215 {
216 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
217 u16 mask = GENMASK(chip->g1_irq.nirqs, 0);
218 u16 reg;
219 int err;
220
221 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, ®);
222 if (err)
223 goto out;
224
225 reg &= ~mask;
226 reg |= (~chip->g1_irq.masked & mask);
227
228 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg);
229 if (err)
230 goto out;
231
232 out:
233 mv88e6xxx_reg_unlock(chip);
234 }
235
236 static const struct irq_chip mv88e6xxx_g1_irq_chip = {
237 .name = "mv88e6xxx-g1",
238 .irq_mask = mv88e6xxx_g1_irq_mask,
239 .irq_unmask = mv88e6xxx_g1_irq_unmask,
240 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock,
241 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock,
242 };
243
mv88e6xxx_g1_irq_domain_map(struct irq_domain * d,unsigned int irq,irq_hw_number_t hwirq)244 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d,
245 unsigned int irq,
246 irq_hw_number_t hwirq)
247 {
248 struct mv88e6xxx_chip *chip = d->host_data;
249
250 irq_set_chip_data(irq, d->host_data);
251 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq);
252 irq_set_noprobe(irq);
253
254 return 0;
255 }
256
257 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = {
258 .map = mv88e6xxx_g1_irq_domain_map,
259 .xlate = irq_domain_xlate_twocell,
260 };
261
262 /* To be called with reg_lock held */
mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip * chip)263 static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip)
264 {
265 int irq, virq;
266 u16 mask;
267
268 mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
269 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
270 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
271
272 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) {
273 virq = irq_find_mapping(chip->g1_irq.domain, irq);
274 irq_dispose_mapping(virq);
275 }
276
277 irq_domain_remove(chip->g1_irq.domain);
278 }
279
mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip * chip)280 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip)
281 {
282 /*
283 * free_irq must be called without reg_lock taken because the irq
284 * handler takes this lock, too.
285 */
286 free_irq(chip->irq, chip);
287
288 mv88e6xxx_reg_lock(chip);
289 mv88e6xxx_g1_irq_free_common(chip);
290 mv88e6xxx_reg_unlock(chip);
291 }
292
mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip * chip)293 static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip)
294 {
295 int err, irq, virq;
296 u16 reg, mask;
297
298 chip->g1_irq.nirqs = chip->info->g1_irqs;
299 chip->g1_irq.domain = irq_domain_add_simple(
300 NULL, chip->g1_irq.nirqs, 0,
301 &mv88e6xxx_g1_irq_domain_ops, chip);
302 if (!chip->g1_irq.domain)
303 return -ENOMEM;
304
305 for (irq = 0; irq < chip->g1_irq.nirqs; irq++)
306 irq_create_mapping(chip->g1_irq.domain, irq);
307
308 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip;
309 chip->g1_irq.masked = ~0;
310
311 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
312 if (err)
313 goto out_mapping;
314
315 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
316
317 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
318 if (err)
319 goto out_disable;
320
321 /* Reading the interrupt status clears (most of) them */
322 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®);
323 if (err)
324 goto out_disable;
325
326 return 0;
327
328 out_disable:
329 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
330 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
331
332 out_mapping:
333 for (irq = 0; irq < 16; irq++) {
334 virq = irq_find_mapping(chip->g1_irq.domain, irq);
335 irq_dispose_mapping(virq);
336 }
337
338 irq_domain_remove(chip->g1_irq.domain);
339
340 return err;
341 }
342
mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip * chip)343 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip)
344 {
345 static struct lock_class_key lock_key;
346 static struct lock_class_key request_key;
347 int err;
348
349 err = mv88e6xxx_g1_irq_setup_common(chip);
350 if (err)
351 return err;
352
353 /* These lock classes tells lockdep that global 1 irqs are in
354 * a different category than their parent GPIO, so it won't
355 * report false recursion.
356 */
357 irq_set_lockdep_class(chip->irq, &lock_key, &request_key);
358
359 snprintf(chip->irq_name, sizeof(chip->irq_name),
360 "mv88e6xxx-%s", dev_name(chip->dev));
361
362 mv88e6xxx_reg_unlock(chip);
363 err = request_threaded_irq(chip->irq, NULL,
364 mv88e6xxx_g1_irq_thread_fn,
365 IRQF_ONESHOT | IRQF_SHARED,
366 chip->irq_name, chip);
367 mv88e6xxx_reg_lock(chip);
368 if (err)
369 mv88e6xxx_g1_irq_free_common(chip);
370
371 return err;
372 }
373
mv88e6xxx_irq_poll(struct kthread_work * work)374 static void mv88e6xxx_irq_poll(struct kthread_work *work)
375 {
376 struct mv88e6xxx_chip *chip = container_of(work,
377 struct mv88e6xxx_chip,
378 irq_poll_work.work);
379 mv88e6xxx_g1_irq_thread_work(chip);
380
381 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work,
382 msecs_to_jiffies(100));
383 }
384
mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip * chip)385 static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip)
386 {
387 int err;
388
389 err = mv88e6xxx_g1_irq_setup_common(chip);
390 if (err)
391 return err;
392
393 kthread_init_delayed_work(&chip->irq_poll_work,
394 mv88e6xxx_irq_poll);
395
396 chip->kworker = kthread_create_worker(0, "%s", dev_name(chip->dev));
397 if (IS_ERR(chip->kworker))
398 return PTR_ERR(chip->kworker);
399
400 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work,
401 msecs_to_jiffies(100));
402
403 return 0;
404 }
405
mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip * chip)406 static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip)
407 {
408 kthread_cancel_delayed_work_sync(&chip->irq_poll_work);
409 kthread_destroy_worker(chip->kworker);
410
411 mv88e6xxx_reg_lock(chip);
412 mv88e6xxx_g1_irq_free_common(chip);
413 mv88e6xxx_reg_unlock(chip);
414 }
415
mv88e6xxx_port_config_interface(struct mv88e6xxx_chip * chip,int port,phy_interface_t interface)416 static int mv88e6xxx_port_config_interface(struct mv88e6xxx_chip *chip,
417 int port, phy_interface_t interface)
418 {
419 int err;
420
421 if (chip->info->ops->port_set_rgmii_delay) {
422 err = chip->info->ops->port_set_rgmii_delay(chip, port,
423 interface);
424 if (err && err != -EOPNOTSUPP)
425 return err;
426 }
427
428 if (chip->info->ops->port_set_cmode) {
429 err = chip->info->ops->port_set_cmode(chip, port,
430 interface);
431 if (err && err != -EOPNOTSUPP)
432 return err;
433 }
434
435 return 0;
436 }
437
mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip * chip,int port,int link,int speed,int duplex,int pause,phy_interface_t mode)438 static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port,
439 int link, int speed, int duplex, int pause,
440 phy_interface_t mode)
441 {
442 int err;
443
444 if (!chip->info->ops->port_set_link)
445 return 0;
446
447 /* Port's MAC control must not be changed unless the link is down */
448 err = chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN);
449 if (err)
450 return err;
451
452 if (chip->info->ops->port_set_speed_duplex) {
453 err = chip->info->ops->port_set_speed_duplex(chip, port,
454 speed, duplex);
455 if (err && err != -EOPNOTSUPP)
456 goto restore_link;
457 }
458
459 if (chip->info->ops->port_set_pause) {
460 err = chip->info->ops->port_set_pause(chip, port, pause);
461 if (err)
462 goto restore_link;
463 }
464
465 err = mv88e6xxx_port_config_interface(chip, port, mode);
466 restore_link:
467 if (chip->info->ops->port_set_link(chip, port, link))
468 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port);
469
470 return err;
471 }
472
mv88e6xxx_phy_is_internal(struct mv88e6xxx_chip * chip,int port)473 static int mv88e6xxx_phy_is_internal(struct mv88e6xxx_chip *chip, int port)
474 {
475 return port >= chip->info->internal_phys_offset &&
476 port < chip->info->num_internal_phys +
477 chip->info->internal_phys_offset;
478 }
479
mv88e6xxx_port_ppu_updates(struct mv88e6xxx_chip * chip,int port)480 static int mv88e6xxx_port_ppu_updates(struct mv88e6xxx_chip *chip, int port)
481 {
482 u16 reg;
483 int err;
484
485 /* The 88e6250 family does not have the PHY detect bit. Instead,
486 * report whether the port is internal.
487 */
488 if (chip->info->family == MV88E6XXX_FAMILY_6250)
489 return mv88e6xxx_phy_is_internal(chip, port);
490
491 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®);
492 if (err) {
493 dev_err(chip->dev,
494 "p%d: %s: failed to read port status\n",
495 port, __func__);
496 return err;
497 }
498
499 return !!(reg & MV88E6XXX_PORT_STS_PHY_DETECT);
500 }
501
502 static const u8 mv88e6185_phy_interface_modes[] = {
503 [MV88E6185_PORT_STS_CMODE_GMII_FD] = PHY_INTERFACE_MODE_GMII,
504 [MV88E6185_PORT_STS_CMODE_MII_100_FD_PS] = PHY_INTERFACE_MODE_MII,
505 [MV88E6185_PORT_STS_CMODE_MII_100] = PHY_INTERFACE_MODE_MII,
506 [MV88E6185_PORT_STS_CMODE_MII_10] = PHY_INTERFACE_MODE_MII,
507 [MV88E6185_PORT_STS_CMODE_SERDES] = PHY_INTERFACE_MODE_1000BASEX,
508 [MV88E6185_PORT_STS_CMODE_1000BASE_X] = PHY_INTERFACE_MODE_1000BASEX,
509 [MV88E6185_PORT_STS_CMODE_PHY] = PHY_INTERFACE_MODE_SGMII,
510 };
511
mv88e6095_phylink_get_caps(struct mv88e6xxx_chip * chip,int port,struct phylink_config * config)512 static void mv88e6095_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
513 struct phylink_config *config)
514 {
515 u8 cmode = chip->ports[port].cmode;
516
517 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100;
518
519 if (mv88e6xxx_phy_is_internal(chip, port)) {
520 __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces);
521 } else {
522 if (cmode < ARRAY_SIZE(mv88e6185_phy_interface_modes) &&
523 mv88e6185_phy_interface_modes[cmode])
524 __set_bit(mv88e6185_phy_interface_modes[cmode],
525 config->supported_interfaces);
526
527 config->mac_capabilities |= MAC_1000FD;
528 }
529 }
530
mv88e6185_phylink_get_caps(struct mv88e6xxx_chip * chip,int port,struct phylink_config * config)531 static void mv88e6185_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
532 struct phylink_config *config)
533 {
534 u8 cmode = chip->ports[port].cmode;
535
536 if (cmode < ARRAY_SIZE(mv88e6185_phy_interface_modes) &&
537 mv88e6185_phy_interface_modes[cmode])
538 __set_bit(mv88e6185_phy_interface_modes[cmode],
539 config->supported_interfaces);
540
541 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
542 MAC_1000FD;
543 }
544
545 static const u8 mv88e6xxx_phy_interface_modes[] = {
546 [MV88E6XXX_PORT_STS_CMODE_MII_PHY] = PHY_INTERFACE_MODE_REVMII,
547 [MV88E6XXX_PORT_STS_CMODE_MII] = PHY_INTERFACE_MODE_MII,
548 [MV88E6XXX_PORT_STS_CMODE_GMII] = PHY_INTERFACE_MODE_GMII,
549 [MV88E6XXX_PORT_STS_CMODE_RMII_PHY] = PHY_INTERFACE_MODE_REVRMII,
550 [MV88E6XXX_PORT_STS_CMODE_RMII] = PHY_INTERFACE_MODE_RMII,
551 [MV88E6XXX_PORT_STS_CMODE_100BASEX] = PHY_INTERFACE_MODE_100BASEX,
552 [MV88E6XXX_PORT_STS_CMODE_1000BASEX] = PHY_INTERFACE_MODE_1000BASEX,
553 [MV88E6XXX_PORT_STS_CMODE_SGMII] = PHY_INTERFACE_MODE_SGMII,
554 /* higher interface modes are not needed here, since ports supporting
555 * them are writable, and so the supported interfaces are filled in the
556 * corresponding .phylink_set_interfaces() implementation below
557 */
558 };
559
mv88e6xxx_translate_cmode(u8 cmode,unsigned long * supported)560 static void mv88e6xxx_translate_cmode(u8 cmode, unsigned long *supported)
561 {
562 if (cmode < ARRAY_SIZE(mv88e6xxx_phy_interface_modes) &&
563 mv88e6xxx_phy_interface_modes[cmode])
564 __set_bit(mv88e6xxx_phy_interface_modes[cmode], supported);
565 else if (cmode == MV88E6XXX_PORT_STS_CMODE_RGMII)
566 phy_interface_set_rgmii(supported);
567 }
568
569 static void
mv88e6250_setup_supported_interfaces(struct mv88e6xxx_chip * chip,int port,struct phylink_config * config)570 mv88e6250_setup_supported_interfaces(struct mv88e6xxx_chip *chip, int port,
571 struct phylink_config *config)
572 {
573 unsigned long *supported = config->supported_interfaces;
574 int err;
575 u16 reg;
576
577 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®);
578 if (err) {
579 dev_err(chip->dev, "p%d: failed to read port status\n", port);
580 return;
581 }
582
583 switch (reg & MV88E6250_PORT_STS_PORTMODE_MASK) {
584 case MV88E6250_PORT_STS_PORTMODE_MII_10_HALF_PHY:
585 case MV88E6250_PORT_STS_PORTMODE_MII_100_HALF_PHY:
586 case MV88E6250_PORT_STS_PORTMODE_MII_10_FULL_PHY:
587 case MV88E6250_PORT_STS_PORTMODE_MII_100_FULL_PHY:
588 __set_bit(PHY_INTERFACE_MODE_REVMII, supported);
589 break;
590
591 case MV88E6250_PORT_STS_PORTMODE_MII_HALF:
592 case MV88E6250_PORT_STS_PORTMODE_MII_FULL:
593 __set_bit(PHY_INTERFACE_MODE_MII, supported);
594 break;
595
596 case MV88E6250_PORT_STS_PORTMODE_MII_DUAL_100_RMII_FULL_PHY:
597 case MV88E6250_PORT_STS_PORTMODE_MII_200_RMII_FULL_PHY:
598 case MV88E6250_PORT_STS_PORTMODE_MII_10_100_RMII_HALF_PHY:
599 case MV88E6250_PORT_STS_PORTMODE_MII_10_100_RMII_FULL_PHY:
600 __set_bit(PHY_INTERFACE_MODE_REVRMII, supported);
601 break;
602
603 case MV88E6250_PORT_STS_PORTMODE_MII_DUAL_100_RMII_FULL:
604 case MV88E6250_PORT_STS_PORTMODE_MII_10_100_RMII_FULL:
605 __set_bit(PHY_INTERFACE_MODE_RMII, supported);
606 break;
607
608 case MV88E6250_PORT_STS_PORTMODE_MII_100_RGMII:
609 __set_bit(PHY_INTERFACE_MODE_RGMII, supported);
610 break;
611
612 default:
613 dev_err(chip->dev,
614 "p%d: invalid port mode in status register: %04x\n",
615 port, reg);
616 }
617 }
618
mv88e6250_phylink_get_caps(struct mv88e6xxx_chip * chip,int port,struct phylink_config * config)619 static void mv88e6250_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
620 struct phylink_config *config)
621 {
622 if (!mv88e6xxx_phy_is_internal(chip, port))
623 mv88e6250_setup_supported_interfaces(chip, port, config);
624
625 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100;
626 }
627
mv88e6351_phylink_get_caps(struct mv88e6xxx_chip * chip,int port,struct phylink_config * config)628 static void mv88e6351_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
629 struct phylink_config *config)
630 {
631 unsigned long *supported = config->supported_interfaces;
632
633 /* Translate the default cmode */
634 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
635
636 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
637 MAC_1000FD;
638 }
639
mv88e6352_get_port4_serdes_cmode(struct mv88e6xxx_chip * chip)640 static int mv88e6352_get_port4_serdes_cmode(struct mv88e6xxx_chip *chip)
641 {
642 u16 reg, val;
643 int err;
644
645 err = mv88e6xxx_port_read(chip, 4, MV88E6XXX_PORT_STS, ®);
646 if (err)
647 return err;
648
649 /* If PHY_DETECT is zero, then we are not in auto-media mode */
650 if (!(reg & MV88E6XXX_PORT_STS_PHY_DETECT))
651 return 0xf;
652
653 val = reg & ~MV88E6XXX_PORT_STS_PHY_DETECT;
654 err = mv88e6xxx_port_write(chip, 4, MV88E6XXX_PORT_STS, val);
655 if (err)
656 return err;
657
658 err = mv88e6xxx_port_read(chip, 4, MV88E6XXX_PORT_STS, &val);
659 if (err)
660 return err;
661
662 /* Restore PHY_DETECT value */
663 err = mv88e6xxx_port_write(chip, 4, MV88E6XXX_PORT_STS, reg);
664 if (err)
665 return err;
666
667 return val & MV88E6XXX_PORT_STS_CMODE_MASK;
668 }
669
mv88e6352_phylink_get_caps(struct mv88e6xxx_chip * chip,int port,struct phylink_config * config)670 static void mv88e6352_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
671 struct phylink_config *config)
672 {
673 unsigned long *supported = config->supported_interfaces;
674 int err, cmode;
675
676 /* Translate the default cmode */
677 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
678
679 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
680 MAC_1000FD;
681
682 /* Port 4 supports automedia if the serdes is associated with it. */
683 if (port == 4) {
684 err = mv88e6352_g2_scratch_port_has_serdes(chip, port);
685 if (err < 0)
686 dev_err(chip->dev, "p%d: failed to read scratch\n",
687 port);
688 if (err <= 0)
689 return;
690
691 cmode = mv88e6352_get_port4_serdes_cmode(chip);
692 if (cmode < 0)
693 dev_err(chip->dev, "p%d: failed to read serdes cmode\n",
694 port);
695 else
696 mv88e6xxx_translate_cmode(cmode, supported);
697 }
698 }
699
mv88e632x_phylink_get_caps(struct mv88e6xxx_chip * chip,int port,struct phylink_config * config)700 static void mv88e632x_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
701 struct phylink_config *config)
702 {
703 unsigned long *supported = config->supported_interfaces;
704
705 /* Translate the default cmode */
706 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
707
708 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
709 MAC_1000FD;
710 }
711
mv88e6341_phylink_get_caps(struct mv88e6xxx_chip * chip,int port,struct phylink_config * config)712 static void mv88e6341_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
713 struct phylink_config *config)
714 {
715 unsigned long *supported = config->supported_interfaces;
716
717 /* Translate the default cmode */
718 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
719
720 /* No ethtool bits for 200Mbps */
721 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
722 MAC_1000FD;
723
724 /* The C_Mode field is programmable on port 5 */
725 if (port == 5) {
726 __set_bit(PHY_INTERFACE_MODE_SGMII, supported);
727 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported);
728 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported);
729
730 config->mac_capabilities |= MAC_2500FD;
731 }
732 }
733
mv88e6390_phylink_get_caps(struct mv88e6xxx_chip * chip,int port,struct phylink_config * config)734 static void mv88e6390_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
735 struct phylink_config *config)
736 {
737 unsigned long *supported = config->supported_interfaces;
738
739 /* Translate the default cmode */
740 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
741
742 /* No ethtool bits for 200Mbps */
743 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
744 MAC_1000FD;
745
746 /* The C_Mode field is programmable on ports 9 and 10 */
747 if (port == 9 || port == 10) {
748 __set_bit(PHY_INTERFACE_MODE_SGMII, supported);
749 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported);
750 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported);
751
752 config->mac_capabilities |= MAC_2500FD;
753 }
754 }
755
mv88e6390x_phylink_get_caps(struct mv88e6xxx_chip * chip,int port,struct phylink_config * config)756 static void mv88e6390x_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
757 struct phylink_config *config)
758 {
759 unsigned long *supported = config->supported_interfaces;
760
761 mv88e6390_phylink_get_caps(chip, port, config);
762
763 /* For the 6x90X, ports 2-7 can be in automedia mode.
764 * (Note that 6x90 doesn't support RXAUI nor XAUI).
765 *
766 * Port 2 can also support 1000BASE-X in automedia mode if port 9 is
767 * configured for 1000BASE-X, SGMII or 2500BASE-X.
768 * Port 3-4 can also support 1000BASE-X in automedia mode if port 9 is
769 * configured for RXAUI, 1000BASE-X, SGMII or 2500BASE-X.
770 *
771 * Port 5 can also support 1000BASE-X in automedia mode if port 10 is
772 * configured for 1000BASE-X, SGMII or 2500BASE-X.
773 * Port 6-7 can also support 1000BASE-X in automedia mode if port 10 is
774 * configured for RXAUI, 1000BASE-X, SGMII or 2500BASE-X.
775 *
776 * For now, be permissive (as the old code was) and allow 1000BASE-X
777 * on ports 2..7.
778 */
779 if (port >= 2 && port <= 7)
780 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported);
781
782 /* The C_Mode field can also be programmed for 10G speeds */
783 if (port == 9 || port == 10) {
784 __set_bit(PHY_INTERFACE_MODE_XAUI, supported);
785 __set_bit(PHY_INTERFACE_MODE_RXAUI, supported);
786
787 config->mac_capabilities |= MAC_10000FD;
788 }
789 }
790
mv88e6393x_phylink_get_caps(struct mv88e6xxx_chip * chip,int port,struct phylink_config * config)791 static void mv88e6393x_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
792 struct phylink_config *config)
793 {
794 unsigned long *supported = config->supported_interfaces;
795 bool is_6191x =
796 chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6191X;
797 bool is_6361 =
798 chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6361;
799
800 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
801
802 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
803 MAC_1000FD;
804
805 /* The C_Mode field can be programmed for ports 0, 9 and 10 */
806 if (port == 0 || port == 9 || port == 10) {
807 __set_bit(PHY_INTERFACE_MODE_SGMII, supported);
808 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported);
809
810 /* 6191X supports >1G modes only on port 10 */
811 if (!is_6191x || port == 10) {
812 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported);
813 config->mac_capabilities |= MAC_2500FD;
814
815 /* 6361 only supports up to 2500BaseX */
816 if (!is_6361) {
817 __set_bit(PHY_INTERFACE_MODE_5GBASER, supported);
818 __set_bit(PHY_INTERFACE_MODE_10GBASER, supported);
819 __set_bit(PHY_INTERFACE_MODE_USXGMII, supported);
820 config->mac_capabilities |= MAC_5000FD |
821 MAC_10000FD;
822 }
823 }
824 }
825
826 if (port == 0) {
827 __set_bit(PHY_INTERFACE_MODE_RMII, supported);
828 __set_bit(PHY_INTERFACE_MODE_RGMII, supported);
829 __set_bit(PHY_INTERFACE_MODE_RGMII_ID, supported);
830 __set_bit(PHY_INTERFACE_MODE_RGMII_RXID, supported);
831 __set_bit(PHY_INTERFACE_MODE_RGMII_TXID, supported);
832 }
833 }
834
mv88e6xxx_get_caps(struct dsa_switch * ds,int port,struct phylink_config * config)835 static void mv88e6xxx_get_caps(struct dsa_switch *ds, int port,
836 struct phylink_config *config)
837 {
838 struct mv88e6xxx_chip *chip = ds->priv;
839
840 mv88e6xxx_reg_lock(chip);
841 chip->info->ops->phylink_get_caps(chip, port, config);
842 mv88e6xxx_reg_unlock(chip);
843
844 if (mv88e6xxx_phy_is_internal(chip, port)) {
845 __set_bit(PHY_INTERFACE_MODE_INTERNAL,
846 config->supported_interfaces);
847 /* Internal ports with no phy-mode need GMII for PHYLIB */
848 __set_bit(PHY_INTERFACE_MODE_GMII,
849 config->supported_interfaces);
850 }
851 }
852
mv88e6xxx_mac_select_pcs(struct dsa_switch * ds,int port,phy_interface_t interface)853 static struct phylink_pcs *mv88e6xxx_mac_select_pcs(struct dsa_switch *ds,
854 int port,
855 phy_interface_t interface)
856 {
857 struct mv88e6xxx_chip *chip = ds->priv;
858 struct phylink_pcs *pcs = ERR_PTR(-EOPNOTSUPP);
859
860 if (chip->info->ops->pcs_ops)
861 pcs = chip->info->ops->pcs_ops->pcs_select(chip, port,
862 interface);
863
864 return pcs;
865 }
866
mv88e6xxx_mac_prepare(struct dsa_switch * ds,int port,unsigned int mode,phy_interface_t interface)867 static int mv88e6xxx_mac_prepare(struct dsa_switch *ds, int port,
868 unsigned int mode, phy_interface_t interface)
869 {
870 struct mv88e6xxx_chip *chip = ds->priv;
871 int err = 0;
872
873 /* In inband mode, the link may come up at any time while the link
874 * is not forced down. Force the link down while we reconfigure the
875 * interface mode.
876 */
877 if (mode == MLO_AN_INBAND &&
878 chip->ports[port].interface != interface &&
879 chip->info->ops->port_set_link) {
880 mv88e6xxx_reg_lock(chip);
881 err = chip->info->ops->port_set_link(chip, port,
882 LINK_FORCED_DOWN);
883 mv88e6xxx_reg_unlock(chip);
884 }
885
886 return err;
887 }
888
mv88e6xxx_mac_config(struct dsa_switch * ds,int port,unsigned int mode,const struct phylink_link_state * state)889 static void mv88e6xxx_mac_config(struct dsa_switch *ds, int port,
890 unsigned int mode,
891 const struct phylink_link_state *state)
892 {
893 struct mv88e6xxx_chip *chip = ds->priv;
894 int err = 0;
895
896 mv88e6xxx_reg_lock(chip);
897
898 if (mode != MLO_AN_PHY || !mv88e6xxx_phy_is_internal(chip, port)) {
899 err = mv88e6xxx_port_config_interface(chip, port,
900 state->interface);
901 if (err && err != -EOPNOTSUPP)
902 goto err_unlock;
903 }
904
905 err_unlock:
906 mv88e6xxx_reg_unlock(chip);
907
908 if (err && err != -EOPNOTSUPP)
909 dev_err(ds->dev, "p%d: failed to configure MAC/PCS\n", port);
910 }
911
mv88e6xxx_mac_finish(struct dsa_switch * ds,int port,unsigned int mode,phy_interface_t interface)912 static int mv88e6xxx_mac_finish(struct dsa_switch *ds, int port,
913 unsigned int mode, phy_interface_t interface)
914 {
915 struct mv88e6xxx_chip *chip = ds->priv;
916 int err = 0;
917
918 /* Undo the forced down state above after completing configuration
919 * irrespective of its state on entry, which allows the link to come
920 * up in the in-band case where there is no separate SERDES. Also
921 * ensure that the link can come up if the PPU is in use and we are
922 * in PHY mode (we treat the PPU as an effective in-band mechanism.)
923 */
924 mv88e6xxx_reg_lock(chip);
925
926 if (chip->info->ops->port_set_link &&
927 ((mode == MLO_AN_INBAND &&
928 chip->ports[port].interface != interface) ||
929 (mode == MLO_AN_PHY && mv88e6xxx_port_ppu_updates(chip, port))))
930 err = chip->info->ops->port_set_link(chip, port, LINK_UNFORCED);
931
932 mv88e6xxx_reg_unlock(chip);
933
934 chip->ports[port].interface = interface;
935
936 return err;
937 }
938
mv88e6xxx_mac_link_down(struct dsa_switch * ds,int port,unsigned int mode,phy_interface_t interface)939 static void mv88e6xxx_mac_link_down(struct dsa_switch *ds, int port,
940 unsigned int mode,
941 phy_interface_t interface)
942 {
943 struct mv88e6xxx_chip *chip = ds->priv;
944 const struct mv88e6xxx_ops *ops;
945 int err = 0;
946
947 ops = chip->info->ops;
948
949 mv88e6xxx_reg_lock(chip);
950 /* Force the link down if we know the port may not be automatically
951 * updated by the switch or if we are using fixed-link mode.
952 */
953 if ((!mv88e6xxx_port_ppu_updates(chip, port) ||
954 mode == MLO_AN_FIXED) && ops->port_sync_link)
955 err = ops->port_sync_link(chip, port, mode, false);
956
957 if (!err && ops->port_set_speed_duplex)
958 err = ops->port_set_speed_duplex(chip, port, SPEED_UNFORCED,
959 DUPLEX_UNFORCED);
960 mv88e6xxx_reg_unlock(chip);
961
962 if (err)
963 dev_err(chip->dev,
964 "p%d: failed to force MAC link down\n", port);
965 }
966
mv88e6xxx_mac_link_up(struct dsa_switch * ds,int port,unsigned int mode,phy_interface_t interface,struct phy_device * phydev,int speed,int duplex,bool tx_pause,bool rx_pause)967 static void mv88e6xxx_mac_link_up(struct dsa_switch *ds, int port,
968 unsigned int mode, phy_interface_t interface,
969 struct phy_device *phydev,
970 int speed, int duplex,
971 bool tx_pause, bool rx_pause)
972 {
973 struct mv88e6xxx_chip *chip = ds->priv;
974 const struct mv88e6xxx_ops *ops;
975 int err = 0;
976
977 ops = chip->info->ops;
978
979 mv88e6xxx_reg_lock(chip);
980 /* Configure and force the link up if we know that the port may not
981 * automatically updated by the switch or if we are using fixed-link
982 * mode.
983 */
984 if (!mv88e6xxx_port_ppu_updates(chip, port) ||
985 mode == MLO_AN_FIXED) {
986 if (ops->port_set_speed_duplex) {
987 err = ops->port_set_speed_duplex(chip, port,
988 speed, duplex);
989 if (err && err != -EOPNOTSUPP)
990 goto error;
991 }
992
993 if (ops->port_sync_link)
994 err = ops->port_sync_link(chip, port, mode, true);
995 }
996 error:
997 mv88e6xxx_reg_unlock(chip);
998
999 if (err && err != -EOPNOTSUPP)
1000 dev_err(ds->dev,
1001 "p%d: failed to configure MAC link up\n", port);
1002 }
1003
mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip * chip,int port)1004 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
1005 {
1006 if (!chip->info->ops->stats_snapshot)
1007 return -EOPNOTSUPP;
1008
1009 return chip->info->ops->stats_snapshot(chip, port);
1010 }
1011
1012 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
1013 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, },
1014 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, },
1015 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, },
1016 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, },
1017 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, },
1018 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, },
1019 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, },
1020 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, },
1021 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, },
1022 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, },
1023 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, },
1024 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, },
1025 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, },
1026 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, },
1027 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, },
1028 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, },
1029 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, },
1030 { "excessive", 4, 0x11, STATS_TYPE_BANK0, },
1031 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, },
1032 { "deferred", 4, 0x05, STATS_TYPE_BANK0, },
1033 { "single", 4, 0x14, STATS_TYPE_BANK0, },
1034 { "multiple", 4, 0x17, STATS_TYPE_BANK0, },
1035 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, },
1036 { "late", 4, 0x1f, STATS_TYPE_BANK0, },
1037 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, },
1038 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, },
1039 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, },
1040 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, },
1041 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, },
1042 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, },
1043 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, },
1044 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, },
1045 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, },
1046 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, },
1047 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, },
1048 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, },
1049 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, },
1050 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, },
1051 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, },
1052 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, },
1053 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, },
1054 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, },
1055 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, },
1056 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, },
1057 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, },
1058 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, },
1059 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, },
1060 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, },
1061 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, },
1062 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, },
1063 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, },
1064 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, },
1065 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, },
1066 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, },
1067 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, },
1068 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, },
1069 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, },
1070 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, },
1071 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, },
1072 };
1073
_mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip * chip,struct mv88e6xxx_hw_stat * s,int port,u16 bank1_select,u16 histogram)1074 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
1075 struct mv88e6xxx_hw_stat *s,
1076 int port, u16 bank1_select,
1077 u16 histogram)
1078 {
1079 u32 low;
1080 u32 high = 0;
1081 u16 reg = 0;
1082 int err;
1083 u64 value;
1084
1085 switch (s->type) {
1086 case STATS_TYPE_PORT:
1087 err = mv88e6xxx_port_read(chip, port, s->reg, ®);
1088 if (err)
1089 return U64_MAX;
1090
1091 low = reg;
1092 if (s->size == 4) {
1093 err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®);
1094 if (err)
1095 return U64_MAX;
1096 low |= ((u32)reg) << 16;
1097 }
1098 break;
1099 case STATS_TYPE_BANK1:
1100 reg = bank1_select;
1101 fallthrough;
1102 case STATS_TYPE_BANK0:
1103 reg |= s->reg | histogram;
1104 mv88e6xxx_g1_stats_read(chip, reg, &low);
1105 if (s->size == 8)
1106 mv88e6xxx_g1_stats_read(chip, reg + 1, &high);
1107 break;
1108 default:
1109 return U64_MAX;
1110 }
1111 value = (((u64)high) << 32) | low;
1112 return value;
1113 }
1114
mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip * chip,uint8_t * data,int types)1115 static int mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip,
1116 uint8_t *data, int types)
1117 {
1118 struct mv88e6xxx_hw_stat *stat;
1119 int i, j;
1120
1121 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
1122 stat = &mv88e6xxx_hw_stats[i];
1123 if (stat->type & types) {
1124 memcpy(data + j * ETH_GSTRING_LEN, stat->string,
1125 ETH_GSTRING_LEN);
1126 j++;
1127 }
1128 }
1129
1130 return j;
1131 }
1132
mv88e6095_stats_get_strings(struct mv88e6xxx_chip * chip,uint8_t * data)1133 static int mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip,
1134 uint8_t *data)
1135 {
1136 return mv88e6xxx_stats_get_strings(chip, data,
1137 STATS_TYPE_BANK0 | STATS_TYPE_PORT);
1138 }
1139
mv88e6250_stats_get_strings(struct mv88e6xxx_chip * chip,uint8_t * data)1140 static int mv88e6250_stats_get_strings(struct mv88e6xxx_chip *chip,
1141 uint8_t *data)
1142 {
1143 return mv88e6xxx_stats_get_strings(chip, data, STATS_TYPE_BANK0);
1144 }
1145
mv88e6320_stats_get_strings(struct mv88e6xxx_chip * chip,uint8_t * data)1146 static int mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip,
1147 uint8_t *data)
1148 {
1149 return mv88e6xxx_stats_get_strings(chip, data,
1150 STATS_TYPE_BANK0 | STATS_TYPE_BANK1);
1151 }
1152
1153 static const uint8_t *mv88e6xxx_atu_vtu_stats_strings[] = {
1154 "atu_member_violation",
1155 "atu_miss_violation",
1156 "atu_full_violation",
1157 "vtu_member_violation",
1158 "vtu_miss_violation",
1159 };
1160
mv88e6xxx_atu_vtu_get_strings(uint8_t * data)1161 static void mv88e6xxx_atu_vtu_get_strings(uint8_t *data)
1162 {
1163 unsigned int i;
1164
1165 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); i++)
1166 strscpy(data + i * ETH_GSTRING_LEN,
1167 mv88e6xxx_atu_vtu_stats_strings[i],
1168 ETH_GSTRING_LEN);
1169 }
1170
mv88e6xxx_get_strings(struct dsa_switch * ds,int port,u32 stringset,uint8_t * data)1171 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
1172 u32 stringset, uint8_t *data)
1173 {
1174 struct mv88e6xxx_chip *chip = ds->priv;
1175 int count = 0;
1176
1177 if (stringset != ETH_SS_STATS)
1178 return;
1179
1180 mv88e6xxx_reg_lock(chip);
1181
1182 if (chip->info->ops->stats_get_strings)
1183 count = chip->info->ops->stats_get_strings(chip, data);
1184
1185 if (chip->info->ops->serdes_get_strings) {
1186 data += count * ETH_GSTRING_LEN;
1187 count = chip->info->ops->serdes_get_strings(chip, port, data);
1188 }
1189
1190 data += count * ETH_GSTRING_LEN;
1191 mv88e6xxx_atu_vtu_get_strings(data);
1192
1193 mv88e6xxx_reg_unlock(chip);
1194 }
1195
mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip * chip,int types)1196 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip,
1197 int types)
1198 {
1199 struct mv88e6xxx_hw_stat *stat;
1200 int i, j;
1201
1202 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
1203 stat = &mv88e6xxx_hw_stats[i];
1204 if (stat->type & types)
1205 j++;
1206 }
1207 return j;
1208 }
1209
mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip * chip)1210 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip)
1211 {
1212 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
1213 STATS_TYPE_PORT);
1214 }
1215
mv88e6250_stats_get_sset_count(struct mv88e6xxx_chip * chip)1216 static int mv88e6250_stats_get_sset_count(struct mv88e6xxx_chip *chip)
1217 {
1218 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0);
1219 }
1220
mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip * chip)1221 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip)
1222 {
1223 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
1224 STATS_TYPE_BANK1);
1225 }
1226
mv88e6xxx_get_sset_count(struct dsa_switch * ds,int port,int sset)1227 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds, int port, int sset)
1228 {
1229 struct mv88e6xxx_chip *chip = ds->priv;
1230 int serdes_count = 0;
1231 int count = 0;
1232
1233 if (sset != ETH_SS_STATS)
1234 return 0;
1235
1236 mv88e6xxx_reg_lock(chip);
1237 if (chip->info->ops->stats_get_sset_count)
1238 count = chip->info->ops->stats_get_sset_count(chip);
1239 if (count < 0)
1240 goto out;
1241
1242 if (chip->info->ops->serdes_get_sset_count)
1243 serdes_count = chip->info->ops->serdes_get_sset_count(chip,
1244 port);
1245 if (serdes_count < 0) {
1246 count = serdes_count;
1247 goto out;
1248 }
1249 count += serdes_count;
1250 count += ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings);
1251
1252 out:
1253 mv88e6xxx_reg_unlock(chip);
1254
1255 return count;
1256 }
1257
mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip * chip,int port,uint64_t * data,int types,u16 bank1_select,u16 histogram)1258 static int mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1259 uint64_t *data, int types,
1260 u16 bank1_select, u16 histogram)
1261 {
1262 struct mv88e6xxx_hw_stat *stat;
1263 int i, j;
1264
1265 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
1266 stat = &mv88e6xxx_hw_stats[i];
1267 if (stat->type & types) {
1268 mv88e6xxx_reg_lock(chip);
1269 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port,
1270 bank1_select,
1271 histogram);
1272 mv88e6xxx_reg_unlock(chip);
1273
1274 j++;
1275 }
1276 }
1277 return j;
1278 }
1279
mv88e6095_stats_get_stats(struct mv88e6xxx_chip * chip,int port,uint64_t * data)1280 static int mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1281 uint64_t *data)
1282 {
1283 return mv88e6xxx_stats_get_stats(chip, port, data,
1284 STATS_TYPE_BANK0 | STATS_TYPE_PORT,
1285 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
1286 }
1287
mv88e6250_stats_get_stats(struct mv88e6xxx_chip * chip,int port,uint64_t * data)1288 static int mv88e6250_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1289 uint64_t *data)
1290 {
1291 return mv88e6xxx_stats_get_stats(chip, port, data, STATS_TYPE_BANK0,
1292 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
1293 }
1294
mv88e6320_stats_get_stats(struct mv88e6xxx_chip * chip,int port,uint64_t * data)1295 static int mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1296 uint64_t *data)
1297 {
1298 return mv88e6xxx_stats_get_stats(chip, port, data,
1299 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
1300 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9,
1301 MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
1302 }
1303
mv88e6390_stats_get_stats(struct mv88e6xxx_chip * chip,int port,uint64_t * data)1304 static int mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1305 uint64_t *data)
1306 {
1307 return mv88e6xxx_stats_get_stats(chip, port, data,
1308 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
1309 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10,
1310 0);
1311 }
1312
mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip * chip,int port,uint64_t * data)1313 static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port,
1314 uint64_t *data)
1315 {
1316 *data++ = chip->ports[port].atu_member_violation;
1317 *data++ = chip->ports[port].atu_miss_violation;
1318 *data++ = chip->ports[port].atu_full_violation;
1319 *data++ = chip->ports[port].vtu_member_violation;
1320 *data++ = chip->ports[port].vtu_miss_violation;
1321 }
1322
mv88e6xxx_get_stats(struct mv88e6xxx_chip * chip,int port,uint64_t * data)1323 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port,
1324 uint64_t *data)
1325 {
1326 int count = 0;
1327
1328 if (chip->info->ops->stats_get_stats)
1329 count = chip->info->ops->stats_get_stats(chip, port, data);
1330
1331 mv88e6xxx_reg_lock(chip);
1332 if (chip->info->ops->serdes_get_stats) {
1333 data += count;
1334 count = chip->info->ops->serdes_get_stats(chip, port, data);
1335 }
1336 data += count;
1337 mv88e6xxx_atu_vtu_get_stats(chip, port, data);
1338 mv88e6xxx_reg_unlock(chip);
1339 }
1340
mv88e6xxx_get_ethtool_stats(struct dsa_switch * ds,int port,uint64_t * data)1341 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
1342 uint64_t *data)
1343 {
1344 struct mv88e6xxx_chip *chip = ds->priv;
1345 int ret;
1346
1347 mv88e6xxx_reg_lock(chip);
1348
1349 ret = mv88e6xxx_stats_snapshot(chip, port);
1350 mv88e6xxx_reg_unlock(chip);
1351
1352 if (ret < 0)
1353 return;
1354
1355 mv88e6xxx_get_stats(chip, port, data);
1356
1357 }
1358
mv88e6xxx_get_regs_len(struct dsa_switch * ds,int port)1359 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
1360 {
1361 struct mv88e6xxx_chip *chip = ds->priv;
1362 int len;
1363
1364 len = 32 * sizeof(u16);
1365 if (chip->info->ops->serdes_get_regs_len)
1366 len += chip->info->ops->serdes_get_regs_len(chip, port);
1367
1368 return len;
1369 }
1370
mv88e6xxx_get_regs(struct dsa_switch * ds,int port,struct ethtool_regs * regs,void * _p)1371 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
1372 struct ethtool_regs *regs, void *_p)
1373 {
1374 struct mv88e6xxx_chip *chip = ds->priv;
1375 int err;
1376 u16 reg;
1377 u16 *p = _p;
1378 int i;
1379
1380 regs->version = chip->info->prod_num;
1381
1382 memset(p, 0xff, 32 * sizeof(u16));
1383
1384 mv88e6xxx_reg_lock(chip);
1385
1386 for (i = 0; i < 32; i++) {
1387
1388 err = mv88e6xxx_port_read(chip, port, i, ®);
1389 if (!err)
1390 p[i] = reg;
1391 }
1392
1393 if (chip->info->ops->serdes_get_regs)
1394 chip->info->ops->serdes_get_regs(chip, port, &p[i]);
1395
1396 mv88e6xxx_reg_unlock(chip);
1397 }
1398
mv88e6xxx_get_mac_eee(struct dsa_switch * ds,int port,struct ethtool_eee * e)1399 static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port,
1400 struct ethtool_eee *e)
1401 {
1402 /* Nothing to do on the port's MAC */
1403 return 0;
1404 }
1405
mv88e6xxx_set_mac_eee(struct dsa_switch * ds,int port,struct ethtool_eee * e)1406 static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port,
1407 struct ethtool_eee *e)
1408 {
1409 /* Nothing to do on the port's MAC */
1410 return 0;
1411 }
1412
1413 /* Mask of the local ports allowed to receive frames from a given fabric port */
mv88e6xxx_port_vlan(struct mv88e6xxx_chip * chip,int dev,int port)1414 static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port)
1415 {
1416 struct dsa_switch *ds = chip->ds;
1417 struct dsa_switch_tree *dst = ds->dst;
1418 struct dsa_port *dp, *other_dp;
1419 bool found = false;
1420 u16 pvlan;
1421
1422 /* dev is a physical switch */
1423 if (dev <= dst->last_switch) {
1424 list_for_each_entry(dp, &dst->ports, list) {
1425 if (dp->ds->index == dev && dp->index == port) {
1426 /* dp might be a DSA link or a user port, so it
1427 * might or might not have a bridge.
1428 * Use the "found" variable for both cases.
1429 */
1430 found = true;
1431 break;
1432 }
1433 }
1434 /* dev is a virtual bridge */
1435 } else {
1436 list_for_each_entry(dp, &dst->ports, list) {
1437 unsigned int bridge_num = dsa_port_bridge_num_get(dp);
1438
1439 if (!bridge_num)
1440 continue;
1441
1442 if (bridge_num + dst->last_switch != dev)
1443 continue;
1444
1445 found = true;
1446 break;
1447 }
1448 }
1449
1450 /* Prevent frames from unknown switch or virtual bridge */
1451 if (!found)
1452 return 0;
1453
1454 /* Frames from DSA links and CPU ports can egress any local port */
1455 if (dp->type == DSA_PORT_TYPE_CPU || dp->type == DSA_PORT_TYPE_DSA)
1456 return mv88e6xxx_port_mask(chip);
1457
1458 pvlan = 0;
1459
1460 /* Frames from standalone user ports can only egress on the
1461 * upstream port.
1462 */
1463 if (!dsa_port_bridge_dev_get(dp))
1464 return BIT(dsa_switch_upstream_port(ds));
1465
1466 /* Frames from bridged user ports can egress any local DSA
1467 * links and CPU ports, as well as any local member of their
1468 * bridge group.
1469 */
1470 dsa_switch_for_each_port(other_dp, ds)
1471 if (other_dp->type == DSA_PORT_TYPE_CPU ||
1472 other_dp->type == DSA_PORT_TYPE_DSA ||
1473 dsa_port_bridge_same(dp, other_dp))
1474 pvlan |= BIT(other_dp->index);
1475
1476 return pvlan;
1477 }
1478
mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip * chip,int port)1479 static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port)
1480 {
1481 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port);
1482
1483 /* prevent frames from going back out of the port they came in on */
1484 output_ports &= ~BIT(port);
1485
1486 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports);
1487 }
1488
mv88e6xxx_port_stp_state_set(struct dsa_switch * ds,int port,u8 state)1489 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
1490 u8 state)
1491 {
1492 struct mv88e6xxx_chip *chip = ds->priv;
1493 int err;
1494
1495 mv88e6xxx_reg_lock(chip);
1496 err = mv88e6xxx_port_set_state(chip, port, state);
1497 mv88e6xxx_reg_unlock(chip);
1498
1499 if (err)
1500 dev_err(ds->dev, "p%d: failed to update state\n", port);
1501 }
1502
mv88e6xxx_pri_setup(struct mv88e6xxx_chip * chip)1503 static int mv88e6xxx_pri_setup(struct mv88e6xxx_chip *chip)
1504 {
1505 int err;
1506
1507 if (chip->info->ops->ieee_pri_map) {
1508 err = chip->info->ops->ieee_pri_map(chip);
1509 if (err)
1510 return err;
1511 }
1512
1513 if (chip->info->ops->ip_pri_map) {
1514 err = chip->info->ops->ip_pri_map(chip);
1515 if (err)
1516 return err;
1517 }
1518
1519 return 0;
1520 }
1521
mv88e6xxx_devmap_setup(struct mv88e6xxx_chip * chip)1522 static int mv88e6xxx_devmap_setup(struct mv88e6xxx_chip *chip)
1523 {
1524 struct dsa_switch *ds = chip->ds;
1525 int target, port;
1526 int err;
1527
1528 if (!chip->info->global2_addr)
1529 return 0;
1530
1531 /* Initialize the routing port to the 32 possible target devices */
1532 for (target = 0; target < 32; target++) {
1533 port = dsa_routing_port(ds, target);
1534 if (port == ds->num_ports)
1535 port = 0x1f;
1536
1537 err = mv88e6xxx_g2_device_mapping_write(chip, target, port);
1538 if (err)
1539 return err;
1540 }
1541
1542 if (chip->info->ops->set_cascade_port) {
1543 port = MV88E6XXX_CASCADE_PORT_MULTIPLE;
1544 err = chip->info->ops->set_cascade_port(chip, port);
1545 if (err)
1546 return err;
1547 }
1548
1549 err = mv88e6xxx_g1_set_device_number(chip, chip->ds->index);
1550 if (err)
1551 return err;
1552
1553 return 0;
1554 }
1555
mv88e6xxx_trunk_setup(struct mv88e6xxx_chip * chip)1556 static int mv88e6xxx_trunk_setup(struct mv88e6xxx_chip *chip)
1557 {
1558 /* Clear all trunk masks and mapping */
1559 if (chip->info->global2_addr)
1560 return mv88e6xxx_g2_trunk_clear(chip);
1561
1562 return 0;
1563 }
1564
mv88e6xxx_rmu_setup(struct mv88e6xxx_chip * chip)1565 static int mv88e6xxx_rmu_setup(struct mv88e6xxx_chip *chip)
1566 {
1567 if (chip->info->ops->rmu_disable)
1568 return chip->info->ops->rmu_disable(chip);
1569
1570 return 0;
1571 }
1572
mv88e6xxx_pot_setup(struct mv88e6xxx_chip * chip)1573 static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip)
1574 {
1575 if (chip->info->ops->pot_clear)
1576 return chip->info->ops->pot_clear(chip);
1577
1578 return 0;
1579 }
1580
mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip * chip)1581 static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip)
1582 {
1583 if (chip->info->ops->mgmt_rsvd2cpu)
1584 return chip->info->ops->mgmt_rsvd2cpu(chip);
1585
1586 return 0;
1587 }
1588
mv88e6xxx_atu_setup(struct mv88e6xxx_chip * chip)1589 static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip)
1590 {
1591 int err;
1592
1593 err = mv88e6xxx_g1_atu_flush(chip, 0, true);
1594 if (err)
1595 return err;
1596
1597 /* The chips that have a "learn2all" bit in Global1, ATU
1598 * Control are precisely those whose port registers have a
1599 * Message Port bit in Port Control 1 and hence implement
1600 * ->port_setup_message_port.
1601 */
1602 if (chip->info->ops->port_setup_message_port) {
1603 err = mv88e6xxx_g1_atu_set_learn2all(chip, true);
1604 if (err)
1605 return err;
1606 }
1607
1608 return mv88e6xxx_g1_atu_set_age_time(chip, 300000);
1609 }
1610
mv88e6xxx_irl_setup(struct mv88e6xxx_chip * chip)1611 static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip)
1612 {
1613 int port;
1614 int err;
1615
1616 if (!chip->info->ops->irl_init_all)
1617 return 0;
1618
1619 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
1620 /* Disable ingress rate limiting by resetting all per port
1621 * ingress rate limit resources to their initial state.
1622 */
1623 err = chip->info->ops->irl_init_all(chip, port);
1624 if (err)
1625 return err;
1626 }
1627
1628 return 0;
1629 }
1630
mv88e6xxx_mac_setup(struct mv88e6xxx_chip * chip)1631 static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip)
1632 {
1633 if (chip->info->ops->set_switch_mac) {
1634 u8 addr[ETH_ALEN];
1635
1636 eth_random_addr(addr);
1637
1638 return chip->info->ops->set_switch_mac(chip, addr);
1639 }
1640
1641 return 0;
1642 }
1643
mv88e6xxx_pvt_map(struct mv88e6xxx_chip * chip,int dev,int port)1644 static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port)
1645 {
1646 struct dsa_switch_tree *dst = chip->ds->dst;
1647 struct dsa_switch *ds;
1648 struct dsa_port *dp;
1649 u16 pvlan = 0;
1650
1651 if (!mv88e6xxx_has_pvt(chip))
1652 return 0;
1653
1654 /* Skip the local source device, which uses in-chip port VLAN */
1655 if (dev != chip->ds->index) {
1656 pvlan = mv88e6xxx_port_vlan(chip, dev, port);
1657
1658 ds = dsa_switch_find(dst->index, dev);
1659 dp = ds ? dsa_to_port(ds, port) : NULL;
1660 if (dp && dp->lag) {
1661 /* As the PVT is used to limit flooding of
1662 * FORWARD frames, which use the LAG ID as the
1663 * source port, we must translate dev/port to
1664 * the special "LAG device" in the PVT, using
1665 * the LAG ID (one-based) as the port number
1666 * (zero-based).
1667 */
1668 dev = MV88E6XXX_G2_PVT_ADDR_DEV_TRUNK;
1669 port = dsa_port_lag_id_get(dp) - 1;
1670 }
1671 }
1672
1673 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan);
1674 }
1675
mv88e6xxx_pvt_setup(struct mv88e6xxx_chip * chip)1676 static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip)
1677 {
1678 int dev, port;
1679 int err;
1680
1681 if (!mv88e6xxx_has_pvt(chip))
1682 return 0;
1683
1684 /* Clear 5 Bit Port for usage with Marvell Link Street devices:
1685 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev.
1686 */
1687 err = mv88e6xxx_g2_misc_4_bit_port(chip);
1688 if (err)
1689 return err;
1690
1691 for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) {
1692 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) {
1693 err = mv88e6xxx_pvt_map(chip, dev, port);
1694 if (err)
1695 return err;
1696 }
1697 }
1698
1699 return 0;
1700 }
1701
mv88e6xxx_port_fast_age_fid(struct mv88e6xxx_chip * chip,int port,u16 fid)1702 static int mv88e6xxx_port_fast_age_fid(struct mv88e6xxx_chip *chip, int port,
1703 u16 fid)
1704 {
1705 if (dsa_to_port(chip->ds, port)->lag)
1706 /* Hardware is incapable of fast-aging a LAG through a
1707 * regular ATU move operation. Until we have something
1708 * more fancy in place this is a no-op.
1709 */
1710 return -EOPNOTSUPP;
1711
1712 return mv88e6xxx_g1_atu_remove(chip, fid, port, false);
1713 }
1714
mv88e6xxx_port_fast_age(struct dsa_switch * ds,int port)1715 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port)
1716 {
1717 struct mv88e6xxx_chip *chip = ds->priv;
1718 int err;
1719
1720 mv88e6xxx_reg_lock(chip);
1721 err = mv88e6xxx_port_fast_age_fid(chip, port, 0);
1722 mv88e6xxx_reg_unlock(chip);
1723
1724 if (err)
1725 dev_err(chip->ds->dev, "p%d: failed to flush ATU: %d\n",
1726 port, err);
1727 }
1728
mv88e6xxx_vtu_setup(struct mv88e6xxx_chip * chip)1729 static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip)
1730 {
1731 if (!mv88e6xxx_max_vid(chip))
1732 return 0;
1733
1734 return mv88e6xxx_g1_vtu_flush(chip);
1735 }
1736
mv88e6xxx_vtu_get(struct mv88e6xxx_chip * chip,u16 vid,struct mv88e6xxx_vtu_entry * entry)1737 static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid,
1738 struct mv88e6xxx_vtu_entry *entry)
1739 {
1740 int err;
1741
1742 if (!chip->info->ops->vtu_getnext)
1743 return -EOPNOTSUPP;
1744
1745 entry->vid = vid ? vid - 1 : mv88e6xxx_max_vid(chip);
1746 entry->valid = false;
1747
1748 err = chip->info->ops->vtu_getnext(chip, entry);
1749
1750 if (entry->vid != vid)
1751 entry->valid = false;
1752
1753 return err;
1754 }
1755
mv88e6xxx_vtu_walk(struct mv88e6xxx_chip * chip,int (* cb)(struct mv88e6xxx_chip * chip,const struct mv88e6xxx_vtu_entry * entry,void * priv),void * priv)1756 int mv88e6xxx_vtu_walk(struct mv88e6xxx_chip *chip,
1757 int (*cb)(struct mv88e6xxx_chip *chip,
1758 const struct mv88e6xxx_vtu_entry *entry,
1759 void *priv),
1760 void *priv)
1761 {
1762 struct mv88e6xxx_vtu_entry entry = {
1763 .vid = mv88e6xxx_max_vid(chip),
1764 .valid = false,
1765 };
1766 int err;
1767
1768 if (!chip->info->ops->vtu_getnext)
1769 return -EOPNOTSUPP;
1770
1771 do {
1772 err = chip->info->ops->vtu_getnext(chip, &entry);
1773 if (err)
1774 return err;
1775
1776 if (!entry.valid)
1777 break;
1778
1779 err = cb(chip, &entry, priv);
1780 if (err)
1781 return err;
1782 } while (entry.vid < mv88e6xxx_max_vid(chip));
1783
1784 return 0;
1785 }
1786
mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip * chip,struct mv88e6xxx_vtu_entry * entry)1787 static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
1788 struct mv88e6xxx_vtu_entry *entry)
1789 {
1790 if (!chip->info->ops->vtu_loadpurge)
1791 return -EOPNOTSUPP;
1792
1793 return chip->info->ops->vtu_loadpurge(chip, entry);
1794 }
1795
mv88e6xxx_fid_map_vlan(struct mv88e6xxx_chip * chip,const struct mv88e6xxx_vtu_entry * entry,void * _fid_bitmap)1796 static int mv88e6xxx_fid_map_vlan(struct mv88e6xxx_chip *chip,
1797 const struct mv88e6xxx_vtu_entry *entry,
1798 void *_fid_bitmap)
1799 {
1800 unsigned long *fid_bitmap = _fid_bitmap;
1801
1802 set_bit(entry->fid, fid_bitmap);
1803 return 0;
1804 }
1805
mv88e6xxx_fid_map(struct mv88e6xxx_chip * chip,unsigned long * fid_bitmap)1806 int mv88e6xxx_fid_map(struct mv88e6xxx_chip *chip, unsigned long *fid_bitmap)
1807 {
1808 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1809
1810 /* Every FID has an associated VID, so walking the VTU
1811 * will discover the full set of FIDs in use.
1812 */
1813 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_fid_map_vlan, fid_bitmap);
1814 }
1815
mv88e6xxx_atu_new(struct mv88e6xxx_chip * chip,u16 * fid)1816 static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid)
1817 {
1818 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
1819 int err;
1820
1821 err = mv88e6xxx_fid_map(chip, fid_bitmap);
1822 if (err)
1823 return err;
1824
1825 *fid = find_first_zero_bit(fid_bitmap, MV88E6XXX_N_FID);
1826 if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
1827 return -ENOSPC;
1828
1829 /* Clear the database */
1830 return mv88e6xxx_g1_atu_flush(chip, *fid, true);
1831 }
1832
mv88e6xxx_stu_loadpurge(struct mv88e6xxx_chip * chip,struct mv88e6xxx_stu_entry * entry)1833 static int mv88e6xxx_stu_loadpurge(struct mv88e6xxx_chip *chip,
1834 struct mv88e6xxx_stu_entry *entry)
1835 {
1836 if (!chip->info->ops->stu_loadpurge)
1837 return -EOPNOTSUPP;
1838
1839 return chip->info->ops->stu_loadpurge(chip, entry);
1840 }
1841
mv88e6xxx_stu_setup(struct mv88e6xxx_chip * chip)1842 static int mv88e6xxx_stu_setup(struct mv88e6xxx_chip *chip)
1843 {
1844 struct mv88e6xxx_stu_entry stu = {
1845 .valid = true,
1846 .sid = 0
1847 };
1848
1849 if (!mv88e6xxx_has_stu(chip))
1850 return 0;
1851
1852 /* Make sure that SID 0 is always valid. This is used by VTU
1853 * entries that do not make use of the STU, e.g. when creating
1854 * a VLAN upper on a port that is also part of a VLAN
1855 * filtering bridge.
1856 */
1857 return mv88e6xxx_stu_loadpurge(chip, &stu);
1858 }
1859
mv88e6xxx_sid_get(struct mv88e6xxx_chip * chip,u8 * sid)1860 static int mv88e6xxx_sid_get(struct mv88e6xxx_chip *chip, u8 *sid)
1861 {
1862 DECLARE_BITMAP(busy, MV88E6XXX_N_SID) = { 0 };
1863 struct mv88e6xxx_mst *mst;
1864
1865 __set_bit(0, busy);
1866
1867 list_for_each_entry(mst, &chip->msts, node)
1868 __set_bit(mst->stu.sid, busy);
1869
1870 *sid = find_first_zero_bit(busy, MV88E6XXX_N_SID);
1871
1872 return (*sid >= mv88e6xxx_max_sid(chip)) ? -ENOSPC : 0;
1873 }
1874
mv88e6xxx_mst_put(struct mv88e6xxx_chip * chip,u8 sid)1875 static int mv88e6xxx_mst_put(struct mv88e6xxx_chip *chip, u8 sid)
1876 {
1877 struct mv88e6xxx_mst *mst, *tmp;
1878 int err;
1879
1880 if (!sid)
1881 return 0;
1882
1883 list_for_each_entry_safe(mst, tmp, &chip->msts, node) {
1884 if (mst->stu.sid != sid)
1885 continue;
1886
1887 if (!refcount_dec_and_test(&mst->refcnt))
1888 return 0;
1889
1890 mst->stu.valid = false;
1891 err = mv88e6xxx_stu_loadpurge(chip, &mst->stu);
1892 if (err) {
1893 refcount_set(&mst->refcnt, 1);
1894 return err;
1895 }
1896
1897 list_del(&mst->node);
1898 kfree(mst);
1899 return 0;
1900 }
1901
1902 return -ENOENT;
1903 }
1904
mv88e6xxx_mst_get(struct mv88e6xxx_chip * chip,struct net_device * br,u16 msti,u8 * sid)1905 static int mv88e6xxx_mst_get(struct mv88e6xxx_chip *chip, struct net_device *br,
1906 u16 msti, u8 *sid)
1907 {
1908 struct mv88e6xxx_mst *mst;
1909 int err, i;
1910
1911 if (!mv88e6xxx_has_stu(chip)) {
1912 err = -EOPNOTSUPP;
1913 goto err;
1914 }
1915
1916 if (!msti) {
1917 *sid = 0;
1918 return 0;
1919 }
1920
1921 list_for_each_entry(mst, &chip->msts, node) {
1922 if (mst->br == br && mst->msti == msti) {
1923 refcount_inc(&mst->refcnt);
1924 *sid = mst->stu.sid;
1925 return 0;
1926 }
1927 }
1928
1929 err = mv88e6xxx_sid_get(chip, sid);
1930 if (err)
1931 goto err;
1932
1933 mst = kzalloc(sizeof(*mst), GFP_KERNEL);
1934 if (!mst) {
1935 err = -ENOMEM;
1936 goto err;
1937 }
1938
1939 INIT_LIST_HEAD(&mst->node);
1940 refcount_set(&mst->refcnt, 1);
1941 mst->br = br;
1942 mst->msti = msti;
1943 mst->stu.valid = true;
1944 mst->stu.sid = *sid;
1945
1946 /* The bridge starts out all ports in the disabled state. But
1947 * a STU state of disabled means to go by the port-global
1948 * state. So we set all user port's initial state to blocking,
1949 * to match the bridge's behavior.
1950 */
1951 for (i = 0; i < mv88e6xxx_num_ports(chip); i++)
1952 mst->stu.state[i] = dsa_is_user_port(chip->ds, i) ?
1953 MV88E6XXX_PORT_CTL0_STATE_BLOCKING :
1954 MV88E6XXX_PORT_CTL0_STATE_DISABLED;
1955
1956 err = mv88e6xxx_stu_loadpurge(chip, &mst->stu);
1957 if (err)
1958 goto err_free;
1959
1960 list_add_tail(&mst->node, &chip->msts);
1961 return 0;
1962
1963 err_free:
1964 kfree(mst);
1965 err:
1966 return err;
1967 }
1968
mv88e6xxx_port_mst_state_set(struct dsa_switch * ds,int port,const struct switchdev_mst_state * st)1969 static int mv88e6xxx_port_mst_state_set(struct dsa_switch *ds, int port,
1970 const struct switchdev_mst_state *st)
1971 {
1972 struct dsa_port *dp = dsa_to_port(ds, port);
1973 struct mv88e6xxx_chip *chip = ds->priv;
1974 struct mv88e6xxx_mst *mst;
1975 u8 state;
1976 int err;
1977
1978 if (!mv88e6xxx_has_stu(chip))
1979 return -EOPNOTSUPP;
1980
1981 switch (st->state) {
1982 case BR_STATE_DISABLED:
1983 case BR_STATE_BLOCKING:
1984 case BR_STATE_LISTENING:
1985 state = MV88E6XXX_PORT_CTL0_STATE_BLOCKING;
1986 break;
1987 case BR_STATE_LEARNING:
1988 state = MV88E6XXX_PORT_CTL0_STATE_LEARNING;
1989 break;
1990 case BR_STATE_FORWARDING:
1991 state = MV88E6XXX_PORT_CTL0_STATE_FORWARDING;
1992 break;
1993 default:
1994 return -EINVAL;
1995 }
1996
1997 list_for_each_entry(mst, &chip->msts, node) {
1998 if (mst->br == dsa_port_bridge_dev_get(dp) &&
1999 mst->msti == st->msti) {
2000 if (mst->stu.state[port] == state)
2001 return 0;
2002
2003 mst->stu.state[port] = state;
2004 mv88e6xxx_reg_lock(chip);
2005 err = mv88e6xxx_stu_loadpurge(chip, &mst->stu);
2006 mv88e6xxx_reg_unlock(chip);
2007 return err;
2008 }
2009 }
2010
2011 return -ENOENT;
2012 }
2013
mv88e6xxx_port_check_hw_vlan(struct dsa_switch * ds,int port,u16 vid)2014 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
2015 u16 vid)
2016 {
2017 struct dsa_port *dp = dsa_to_port(ds, port), *other_dp;
2018 struct mv88e6xxx_chip *chip = ds->priv;
2019 struct mv88e6xxx_vtu_entry vlan;
2020 int err;
2021
2022 /* DSA and CPU ports have to be members of multiple vlans */
2023 if (dsa_port_is_dsa(dp) || dsa_port_is_cpu(dp))
2024 return 0;
2025
2026 err = mv88e6xxx_vtu_get(chip, vid, &vlan);
2027 if (err)
2028 return err;
2029
2030 if (!vlan.valid)
2031 return 0;
2032
2033 dsa_switch_for_each_user_port(other_dp, ds) {
2034 struct net_device *other_br;
2035
2036 if (vlan.member[other_dp->index] ==
2037 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
2038 continue;
2039
2040 if (dsa_port_bridge_same(dp, other_dp))
2041 break; /* same bridge, check next VLAN */
2042
2043 other_br = dsa_port_bridge_dev_get(other_dp);
2044 if (!other_br)
2045 continue;
2046
2047 dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n",
2048 port, vlan.vid, other_dp->index, netdev_name(other_br));
2049 return -EOPNOTSUPP;
2050 }
2051
2052 return 0;
2053 }
2054
mv88e6xxx_port_commit_pvid(struct mv88e6xxx_chip * chip,int port)2055 static int mv88e6xxx_port_commit_pvid(struct mv88e6xxx_chip *chip, int port)
2056 {
2057 struct dsa_port *dp = dsa_to_port(chip->ds, port);
2058 struct net_device *br = dsa_port_bridge_dev_get(dp);
2059 struct mv88e6xxx_port *p = &chip->ports[port];
2060 u16 pvid = MV88E6XXX_VID_STANDALONE;
2061 bool drop_untagged = false;
2062 int err;
2063
2064 if (br) {
2065 if (br_vlan_enabled(br)) {
2066 pvid = p->bridge_pvid.vid;
2067 drop_untagged = !p->bridge_pvid.valid;
2068 } else {
2069 pvid = MV88E6XXX_VID_BRIDGED;
2070 }
2071 }
2072
2073 err = mv88e6xxx_port_set_pvid(chip, port, pvid);
2074 if (err)
2075 return err;
2076
2077 return mv88e6xxx_port_drop_untagged(chip, port, drop_untagged);
2078 }
2079
mv88e6xxx_port_vlan_filtering(struct dsa_switch * ds,int port,bool vlan_filtering,struct netlink_ext_ack * extack)2080 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
2081 bool vlan_filtering,
2082 struct netlink_ext_ack *extack)
2083 {
2084 struct mv88e6xxx_chip *chip = ds->priv;
2085 u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE :
2086 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED;
2087 int err;
2088
2089 if (!mv88e6xxx_max_vid(chip))
2090 return -EOPNOTSUPP;
2091
2092 mv88e6xxx_reg_lock(chip);
2093
2094 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode);
2095 if (err)
2096 goto unlock;
2097
2098 err = mv88e6xxx_port_commit_pvid(chip, port);
2099 if (err)
2100 goto unlock;
2101
2102 unlock:
2103 mv88e6xxx_reg_unlock(chip);
2104
2105 return err;
2106 }
2107
2108 static int
mv88e6xxx_port_vlan_prepare(struct dsa_switch * ds,int port,const struct switchdev_obj_port_vlan * vlan)2109 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
2110 const struct switchdev_obj_port_vlan *vlan)
2111 {
2112 struct mv88e6xxx_chip *chip = ds->priv;
2113 int err;
2114
2115 if (!mv88e6xxx_max_vid(chip))
2116 return -EOPNOTSUPP;
2117
2118 /* If the requested port doesn't belong to the same bridge as the VLAN
2119 * members, do not support it (yet) and fallback to software VLAN.
2120 */
2121 mv88e6xxx_reg_lock(chip);
2122 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid);
2123 mv88e6xxx_reg_unlock(chip);
2124
2125 return err;
2126 }
2127
mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip * chip,int port,const unsigned char * addr,u16 vid,u8 state)2128 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port,
2129 const unsigned char *addr, u16 vid,
2130 u8 state)
2131 {
2132 struct mv88e6xxx_atu_entry entry;
2133 struct mv88e6xxx_vtu_entry vlan;
2134 u16 fid;
2135 int err;
2136
2137 /* Ports have two private address databases: one for when the port is
2138 * standalone and one for when the port is under a bridge and the
2139 * 802.1Q mode is disabled. When the port is standalone, DSA wants its
2140 * address database to remain 100% empty, so we never load an ATU entry
2141 * into a standalone port's database. Therefore, translate the null
2142 * VLAN ID into the port's database used for VLAN-unaware bridging.
2143 */
2144 if (vid == 0) {
2145 fid = MV88E6XXX_FID_BRIDGED;
2146 } else {
2147 err = mv88e6xxx_vtu_get(chip, vid, &vlan);
2148 if (err)
2149 return err;
2150
2151 /* switchdev expects -EOPNOTSUPP to honor software VLANs */
2152 if (!vlan.valid)
2153 return -EOPNOTSUPP;
2154
2155 fid = vlan.fid;
2156 }
2157
2158 entry.state = 0;
2159 ether_addr_copy(entry.mac, addr);
2160 eth_addr_dec(entry.mac);
2161
2162 err = mv88e6xxx_g1_atu_getnext(chip, fid, &entry);
2163 if (err)
2164 return err;
2165
2166 /* Initialize a fresh ATU entry if it isn't found */
2167 if (!entry.state || !ether_addr_equal(entry.mac, addr)) {
2168 memset(&entry, 0, sizeof(entry));
2169 ether_addr_copy(entry.mac, addr);
2170 }
2171
2172 /* Purge the ATU entry only if no port is using it anymore */
2173 if (!state) {
2174 entry.portvec &= ~BIT(port);
2175 if (!entry.portvec)
2176 entry.state = 0;
2177 } else {
2178 if (state == MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC)
2179 entry.portvec = BIT(port);
2180 else
2181 entry.portvec |= BIT(port);
2182
2183 entry.state = state;
2184 }
2185
2186 return mv88e6xxx_g1_atu_loadpurge(chip, fid, &entry);
2187 }
2188
mv88e6xxx_policy_apply(struct mv88e6xxx_chip * chip,int port,const struct mv88e6xxx_policy * policy)2189 static int mv88e6xxx_policy_apply(struct mv88e6xxx_chip *chip, int port,
2190 const struct mv88e6xxx_policy *policy)
2191 {
2192 enum mv88e6xxx_policy_mapping mapping = policy->mapping;
2193 enum mv88e6xxx_policy_action action = policy->action;
2194 const u8 *addr = policy->addr;
2195 u16 vid = policy->vid;
2196 u8 state;
2197 int err;
2198 int id;
2199
2200 if (!chip->info->ops->port_set_policy)
2201 return -EOPNOTSUPP;
2202
2203 switch (mapping) {
2204 case MV88E6XXX_POLICY_MAPPING_DA:
2205 case MV88E6XXX_POLICY_MAPPING_SA:
2206 if (action == MV88E6XXX_POLICY_ACTION_NORMAL)
2207 state = 0; /* Dissociate the port and address */
2208 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD &&
2209 is_multicast_ether_addr(addr))
2210 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY;
2211 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD &&
2212 is_unicast_ether_addr(addr))
2213 state = MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY;
2214 else
2215 return -EOPNOTSUPP;
2216
2217 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
2218 state);
2219 if (err)
2220 return err;
2221 break;
2222 default:
2223 return -EOPNOTSUPP;
2224 }
2225
2226 /* Skip the port's policy clearing if the mapping is still in use */
2227 if (action == MV88E6XXX_POLICY_ACTION_NORMAL)
2228 idr_for_each_entry(&chip->policies, policy, id)
2229 if (policy->port == port &&
2230 policy->mapping == mapping &&
2231 policy->action != action)
2232 return 0;
2233
2234 return chip->info->ops->port_set_policy(chip, port, mapping, action);
2235 }
2236
mv88e6xxx_policy_insert(struct mv88e6xxx_chip * chip,int port,struct ethtool_rx_flow_spec * fs)2237 static int mv88e6xxx_policy_insert(struct mv88e6xxx_chip *chip, int port,
2238 struct ethtool_rx_flow_spec *fs)
2239 {
2240 struct ethhdr *mac_entry = &fs->h_u.ether_spec;
2241 struct ethhdr *mac_mask = &fs->m_u.ether_spec;
2242 enum mv88e6xxx_policy_mapping mapping;
2243 enum mv88e6xxx_policy_action action;
2244 struct mv88e6xxx_policy *policy;
2245 u16 vid = 0;
2246 u8 *addr;
2247 int err;
2248 int id;
2249
2250 if (fs->location != RX_CLS_LOC_ANY)
2251 return -EINVAL;
2252
2253 if (fs->ring_cookie == RX_CLS_FLOW_DISC)
2254 action = MV88E6XXX_POLICY_ACTION_DISCARD;
2255 else
2256 return -EOPNOTSUPP;
2257
2258 switch (fs->flow_type & ~FLOW_EXT) {
2259 case ETHER_FLOW:
2260 if (!is_zero_ether_addr(mac_mask->h_dest) &&
2261 is_zero_ether_addr(mac_mask->h_source)) {
2262 mapping = MV88E6XXX_POLICY_MAPPING_DA;
2263 addr = mac_entry->h_dest;
2264 } else if (is_zero_ether_addr(mac_mask->h_dest) &&
2265 !is_zero_ether_addr(mac_mask->h_source)) {
2266 mapping = MV88E6XXX_POLICY_MAPPING_SA;
2267 addr = mac_entry->h_source;
2268 } else {
2269 /* Cannot support DA and SA mapping in the same rule */
2270 return -EOPNOTSUPP;
2271 }
2272 break;
2273 default:
2274 return -EOPNOTSUPP;
2275 }
2276
2277 if ((fs->flow_type & FLOW_EXT) && fs->m_ext.vlan_tci) {
2278 if (fs->m_ext.vlan_tci != htons(0xffff))
2279 return -EOPNOTSUPP;
2280 vid = be16_to_cpu(fs->h_ext.vlan_tci) & VLAN_VID_MASK;
2281 }
2282
2283 idr_for_each_entry(&chip->policies, policy, id) {
2284 if (policy->port == port && policy->mapping == mapping &&
2285 policy->action == action && policy->vid == vid &&
2286 ether_addr_equal(policy->addr, addr))
2287 return -EEXIST;
2288 }
2289
2290 policy = devm_kzalloc(chip->dev, sizeof(*policy), GFP_KERNEL);
2291 if (!policy)
2292 return -ENOMEM;
2293
2294 fs->location = 0;
2295 err = idr_alloc_u32(&chip->policies, policy, &fs->location, 0xffffffff,
2296 GFP_KERNEL);
2297 if (err) {
2298 devm_kfree(chip->dev, policy);
2299 return err;
2300 }
2301
2302 memcpy(&policy->fs, fs, sizeof(*fs));
2303 ether_addr_copy(policy->addr, addr);
2304 policy->mapping = mapping;
2305 policy->action = action;
2306 policy->port = port;
2307 policy->vid = vid;
2308
2309 err = mv88e6xxx_policy_apply(chip, port, policy);
2310 if (err) {
2311 idr_remove(&chip->policies, fs->location);
2312 devm_kfree(chip->dev, policy);
2313 return err;
2314 }
2315
2316 return 0;
2317 }
2318
mv88e6xxx_get_rxnfc(struct dsa_switch * ds,int port,struct ethtool_rxnfc * rxnfc,u32 * rule_locs)2319 static int mv88e6xxx_get_rxnfc(struct dsa_switch *ds, int port,
2320 struct ethtool_rxnfc *rxnfc, u32 *rule_locs)
2321 {
2322 struct ethtool_rx_flow_spec *fs = &rxnfc->fs;
2323 struct mv88e6xxx_chip *chip = ds->priv;
2324 struct mv88e6xxx_policy *policy;
2325 int err;
2326 int id;
2327
2328 mv88e6xxx_reg_lock(chip);
2329
2330 switch (rxnfc->cmd) {
2331 case ETHTOOL_GRXCLSRLCNT:
2332 rxnfc->data = 0;
2333 rxnfc->data |= RX_CLS_LOC_SPECIAL;
2334 rxnfc->rule_cnt = 0;
2335 idr_for_each_entry(&chip->policies, policy, id)
2336 if (policy->port == port)
2337 rxnfc->rule_cnt++;
2338 err = 0;
2339 break;
2340 case ETHTOOL_GRXCLSRULE:
2341 err = -ENOENT;
2342 policy = idr_find(&chip->policies, fs->location);
2343 if (policy) {
2344 memcpy(fs, &policy->fs, sizeof(*fs));
2345 err = 0;
2346 }
2347 break;
2348 case ETHTOOL_GRXCLSRLALL:
2349 rxnfc->data = 0;
2350 rxnfc->rule_cnt = 0;
2351 idr_for_each_entry(&chip->policies, policy, id)
2352 if (policy->port == port)
2353 rule_locs[rxnfc->rule_cnt++] = id;
2354 err = 0;
2355 break;
2356 default:
2357 err = -EOPNOTSUPP;
2358 break;
2359 }
2360
2361 mv88e6xxx_reg_unlock(chip);
2362
2363 return err;
2364 }
2365
mv88e6xxx_set_rxnfc(struct dsa_switch * ds,int port,struct ethtool_rxnfc * rxnfc)2366 static int mv88e6xxx_set_rxnfc(struct dsa_switch *ds, int port,
2367 struct ethtool_rxnfc *rxnfc)
2368 {
2369 struct ethtool_rx_flow_spec *fs = &rxnfc->fs;
2370 struct mv88e6xxx_chip *chip = ds->priv;
2371 struct mv88e6xxx_policy *policy;
2372 int err;
2373
2374 mv88e6xxx_reg_lock(chip);
2375
2376 switch (rxnfc->cmd) {
2377 case ETHTOOL_SRXCLSRLINS:
2378 err = mv88e6xxx_policy_insert(chip, port, fs);
2379 break;
2380 case ETHTOOL_SRXCLSRLDEL:
2381 err = -ENOENT;
2382 policy = idr_remove(&chip->policies, fs->location);
2383 if (policy) {
2384 policy->action = MV88E6XXX_POLICY_ACTION_NORMAL;
2385 err = mv88e6xxx_policy_apply(chip, port, policy);
2386 devm_kfree(chip->dev, policy);
2387 }
2388 break;
2389 default:
2390 err = -EOPNOTSUPP;
2391 break;
2392 }
2393
2394 mv88e6xxx_reg_unlock(chip);
2395
2396 return err;
2397 }
2398
mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip * chip,int port,u16 vid)2399 static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port,
2400 u16 vid)
2401 {
2402 u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC;
2403 u8 broadcast[ETH_ALEN];
2404
2405 eth_broadcast_addr(broadcast);
2406
2407 return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state);
2408 }
2409
mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip * chip,u16 vid)2410 static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid)
2411 {
2412 int port;
2413 int err;
2414
2415 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
2416 struct dsa_port *dp = dsa_to_port(chip->ds, port);
2417 struct net_device *brport;
2418
2419 if (dsa_is_unused_port(chip->ds, port))
2420 continue;
2421
2422 brport = dsa_port_to_bridge_port(dp);
2423 if (brport && !br_port_flag_is_set(brport, BR_BCAST_FLOOD))
2424 /* Skip bridged user ports where broadcast
2425 * flooding is disabled.
2426 */
2427 continue;
2428
2429 err = mv88e6xxx_port_add_broadcast(chip, port, vid);
2430 if (err)
2431 return err;
2432 }
2433
2434 return 0;
2435 }
2436
2437 struct mv88e6xxx_port_broadcast_sync_ctx {
2438 int port;
2439 bool flood;
2440 };
2441
2442 static int
mv88e6xxx_port_broadcast_sync_vlan(struct mv88e6xxx_chip * chip,const struct mv88e6xxx_vtu_entry * vlan,void * _ctx)2443 mv88e6xxx_port_broadcast_sync_vlan(struct mv88e6xxx_chip *chip,
2444 const struct mv88e6xxx_vtu_entry *vlan,
2445 void *_ctx)
2446 {
2447 struct mv88e6xxx_port_broadcast_sync_ctx *ctx = _ctx;
2448 u8 broadcast[ETH_ALEN];
2449 u8 state;
2450
2451 if (ctx->flood)
2452 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC;
2453 else
2454 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_UNUSED;
2455
2456 eth_broadcast_addr(broadcast);
2457
2458 return mv88e6xxx_port_db_load_purge(chip, ctx->port, broadcast,
2459 vlan->vid, state);
2460 }
2461
mv88e6xxx_port_broadcast_sync(struct mv88e6xxx_chip * chip,int port,bool flood)2462 static int mv88e6xxx_port_broadcast_sync(struct mv88e6xxx_chip *chip, int port,
2463 bool flood)
2464 {
2465 struct mv88e6xxx_port_broadcast_sync_ctx ctx = {
2466 .port = port,
2467 .flood = flood,
2468 };
2469 struct mv88e6xxx_vtu_entry vid0 = {
2470 .vid = 0,
2471 };
2472 int err;
2473
2474 /* Update the port's private database... */
2475 err = mv88e6xxx_port_broadcast_sync_vlan(chip, &vid0, &ctx);
2476 if (err)
2477 return err;
2478
2479 /* ...and the database for all VLANs. */
2480 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_broadcast_sync_vlan,
2481 &ctx);
2482 }
2483
mv88e6xxx_port_vlan_join(struct mv88e6xxx_chip * chip,int port,u16 vid,u8 member,bool warn)2484 static int mv88e6xxx_port_vlan_join(struct mv88e6xxx_chip *chip, int port,
2485 u16 vid, u8 member, bool warn)
2486 {
2487 const u8 non_member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
2488 struct mv88e6xxx_vtu_entry vlan;
2489 int i, err;
2490
2491 err = mv88e6xxx_vtu_get(chip, vid, &vlan);
2492 if (err)
2493 return err;
2494
2495 if (!vlan.valid) {
2496 memset(&vlan, 0, sizeof(vlan));
2497
2498 if (vid == MV88E6XXX_VID_STANDALONE)
2499 vlan.policy = true;
2500
2501 err = mv88e6xxx_atu_new(chip, &vlan.fid);
2502 if (err)
2503 return err;
2504
2505 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
2506 if (i == port)
2507 vlan.member[i] = member;
2508 else
2509 vlan.member[i] = non_member;
2510
2511 vlan.vid = vid;
2512 vlan.valid = true;
2513
2514 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
2515 if (err)
2516 return err;
2517
2518 err = mv88e6xxx_broadcast_setup(chip, vlan.vid);
2519 if (err)
2520 return err;
2521 } else if (vlan.member[port] != member) {
2522 vlan.member[port] = member;
2523
2524 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
2525 if (err)
2526 return err;
2527 } else if (warn) {
2528 dev_info(chip->dev, "p%d: already a member of VLAN %d\n",
2529 port, vid);
2530 }
2531
2532 return 0;
2533 }
2534
mv88e6xxx_port_vlan_add(struct dsa_switch * ds,int port,const struct switchdev_obj_port_vlan * vlan,struct netlink_ext_ack * extack)2535 static int mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
2536 const struct switchdev_obj_port_vlan *vlan,
2537 struct netlink_ext_ack *extack)
2538 {
2539 struct mv88e6xxx_chip *chip = ds->priv;
2540 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
2541 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
2542 struct mv88e6xxx_port *p = &chip->ports[port];
2543 bool warn;
2544 u8 member;
2545 int err;
2546
2547 if (!vlan->vid)
2548 return 0;
2549
2550 err = mv88e6xxx_port_vlan_prepare(ds, port, vlan);
2551 if (err)
2552 return err;
2553
2554 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
2555 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED;
2556 else if (untagged)
2557 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED;
2558 else
2559 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED;
2560
2561 /* net/dsa/slave.c will call dsa_port_vlan_add() for the affected port
2562 * and then the CPU port. Do not warn for duplicates for the CPU port.
2563 */
2564 warn = !dsa_is_cpu_port(ds, port) && !dsa_is_dsa_port(ds, port);
2565
2566 mv88e6xxx_reg_lock(chip);
2567
2568 err = mv88e6xxx_port_vlan_join(chip, port, vlan->vid, member, warn);
2569 if (err) {
2570 dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port,
2571 vlan->vid, untagged ? 'u' : 't');
2572 goto out;
2573 }
2574
2575 if (pvid) {
2576 p->bridge_pvid.vid = vlan->vid;
2577 p->bridge_pvid.valid = true;
2578
2579 err = mv88e6xxx_port_commit_pvid(chip, port);
2580 if (err)
2581 goto out;
2582 } else if (vlan->vid && p->bridge_pvid.vid == vlan->vid) {
2583 /* The old pvid was reinstalled as a non-pvid VLAN */
2584 p->bridge_pvid.valid = false;
2585
2586 err = mv88e6xxx_port_commit_pvid(chip, port);
2587 if (err)
2588 goto out;
2589 }
2590
2591 out:
2592 mv88e6xxx_reg_unlock(chip);
2593
2594 return err;
2595 }
2596
mv88e6xxx_port_vlan_leave(struct mv88e6xxx_chip * chip,int port,u16 vid)2597 static int mv88e6xxx_port_vlan_leave(struct mv88e6xxx_chip *chip,
2598 int port, u16 vid)
2599 {
2600 struct mv88e6xxx_vtu_entry vlan;
2601 int i, err;
2602
2603 if (!vid)
2604 return 0;
2605
2606 err = mv88e6xxx_vtu_get(chip, vid, &vlan);
2607 if (err)
2608 return err;
2609
2610 /* If the VLAN doesn't exist in hardware or the port isn't a member,
2611 * tell switchdev that this VLAN is likely handled in software.
2612 */
2613 if (!vlan.valid ||
2614 vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
2615 return -EOPNOTSUPP;
2616
2617 vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
2618
2619 /* keep the VLAN unless all ports are excluded */
2620 vlan.valid = false;
2621 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
2622 if (vlan.member[i] !=
2623 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
2624 vlan.valid = true;
2625 break;
2626 }
2627 }
2628
2629 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
2630 if (err)
2631 return err;
2632
2633 if (!vlan.valid) {
2634 err = mv88e6xxx_mst_put(chip, vlan.sid);
2635 if (err)
2636 return err;
2637 }
2638
2639 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false);
2640 }
2641
mv88e6xxx_port_vlan_del(struct dsa_switch * ds,int port,const struct switchdev_obj_port_vlan * vlan)2642 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
2643 const struct switchdev_obj_port_vlan *vlan)
2644 {
2645 struct mv88e6xxx_chip *chip = ds->priv;
2646 struct mv88e6xxx_port *p = &chip->ports[port];
2647 int err = 0;
2648 u16 pvid;
2649
2650 if (!mv88e6xxx_max_vid(chip))
2651 return -EOPNOTSUPP;
2652
2653 /* The ATU removal procedure needs the FID to be mapped in the VTU,
2654 * but FDB deletion runs concurrently with VLAN deletion. Flush the DSA
2655 * switchdev workqueue to ensure that all FDB entries are deleted
2656 * before we remove the VLAN.
2657 */
2658 dsa_flush_workqueue();
2659
2660 mv88e6xxx_reg_lock(chip);
2661
2662 err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
2663 if (err)
2664 goto unlock;
2665
2666 err = mv88e6xxx_port_vlan_leave(chip, port, vlan->vid);
2667 if (err)
2668 goto unlock;
2669
2670 if (vlan->vid == pvid) {
2671 p->bridge_pvid.valid = false;
2672
2673 err = mv88e6xxx_port_commit_pvid(chip, port);
2674 if (err)
2675 goto unlock;
2676 }
2677
2678 unlock:
2679 mv88e6xxx_reg_unlock(chip);
2680
2681 return err;
2682 }
2683
mv88e6xxx_port_vlan_fast_age(struct dsa_switch * ds,int port,u16 vid)2684 static int mv88e6xxx_port_vlan_fast_age(struct dsa_switch *ds, int port, u16 vid)
2685 {
2686 struct mv88e6xxx_chip *chip = ds->priv;
2687 struct mv88e6xxx_vtu_entry vlan;
2688 int err;
2689
2690 mv88e6xxx_reg_lock(chip);
2691
2692 err = mv88e6xxx_vtu_get(chip, vid, &vlan);
2693 if (err)
2694 goto unlock;
2695
2696 err = mv88e6xxx_port_fast_age_fid(chip, port, vlan.fid);
2697
2698 unlock:
2699 mv88e6xxx_reg_unlock(chip);
2700
2701 return err;
2702 }
2703
mv88e6xxx_vlan_msti_set(struct dsa_switch * ds,struct dsa_bridge bridge,const struct switchdev_vlan_msti * msti)2704 static int mv88e6xxx_vlan_msti_set(struct dsa_switch *ds,
2705 struct dsa_bridge bridge,
2706 const struct switchdev_vlan_msti *msti)
2707 {
2708 struct mv88e6xxx_chip *chip = ds->priv;
2709 struct mv88e6xxx_vtu_entry vlan;
2710 u8 old_sid, new_sid;
2711 int err;
2712
2713 if (!mv88e6xxx_has_stu(chip))
2714 return -EOPNOTSUPP;
2715
2716 mv88e6xxx_reg_lock(chip);
2717
2718 err = mv88e6xxx_vtu_get(chip, msti->vid, &vlan);
2719 if (err)
2720 goto unlock;
2721
2722 if (!vlan.valid) {
2723 err = -EINVAL;
2724 goto unlock;
2725 }
2726
2727 old_sid = vlan.sid;
2728
2729 err = mv88e6xxx_mst_get(chip, bridge.dev, msti->msti, &new_sid);
2730 if (err)
2731 goto unlock;
2732
2733 if (new_sid != old_sid) {
2734 vlan.sid = new_sid;
2735
2736 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
2737 if (err) {
2738 mv88e6xxx_mst_put(chip, new_sid);
2739 goto unlock;
2740 }
2741 }
2742
2743 err = mv88e6xxx_mst_put(chip, old_sid);
2744
2745 unlock:
2746 mv88e6xxx_reg_unlock(chip);
2747 return err;
2748 }
2749
mv88e6xxx_port_fdb_add(struct dsa_switch * ds,int port,const unsigned char * addr,u16 vid,struct dsa_db db)2750 static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
2751 const unsigned char *addr, u16 vid,
2752 struct dsa_db db)
2753 {
2754 struct mv88e6xxx_chip *chip = ds->priv;
2755 int err;
2756
2757 mv88e6xxx_reg_lock(chip);
2758 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
2759 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
2760 mv88e6xxx_reg_unlock(chip);
2761
2762 return err;
2763 }
2764
mv88e6xxx_port_fdb_del(struct dsa_switch * ds,int port,const unsigned char * addr,u16 vid,struct dsa_db db)2765 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
2766 const unsigned char *addr, u16 vid,
2767 struct dsa_db db)
2768 {
2769 struct mv88e6xxx_chip *chip = ds->priv;
2770 int err;
2771
2772 mv88e6xxx_reg_lock(chip);
2773 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 0);
2774 mv88e6xxx_reg_unlock(chip);
2775
2776 return err;
2777 }
2778
mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip * chip,u16 fid,u16 vid,int port,dsa_fdb_dump_cb_t * cb,void * data)2779 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip,
2780 u16 fid, u16 vid, int port,
2781 dsa_fdb_dump_cb_t *cb, void *data)
2782 {
2783 struct mv88e6xxx_atu_entry addr;
2784 bool is_static;
2785 int err;
2786
2787 addr.state = 0;
2788 eth_broadcast_addr(addr.mac);
2789
2790 do {
2791 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr);
2792 if (err)
2793 return err;
2794
2795 if (!addr.state)
2796 break;
2797
2798 if (addr.trunk || (addr.portvec & BIT(port)) == 0)
2799 continue;
2800
2801 if (!is_unicast_ether_addr(addr.mac))
2802 continue;
2803
2804 is_static = (addr.state ==
2805 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
2806 err = cb(addr.mac, vid, is_static, data);
2807 if (err)
2808 return err;
2809 } while (!is_broadcast_ether_addr(addr.mac));
2810
2811 return err;
2812 }
2813
2814 struct mv88e6xxx_port_db_dump_vlan_ctx {
2815 int port;
2816 dsa_fdb_dump_cb_t *cb;
2817 void *data;
2818 };
2819
mv88e6xxx_port_db_dump_vlan(struct mv88e6xxx_chip * chip,const struct mv88e6xxx_vtu_entry * entry,void * _data)2820 static int mv88e6xxx_port_db_dump_vlan(struct mv88e6xxx_chip *chip,
2821 const struct mv88e6xxx_vtu_entry *entry,
2822 void *_data)
2823 {
2824 struct mv88e6xxx_port_db_dump_vlan_ctx *ctx = _data;
2825
2826 return mv88e6xxx_port_db_dump_fid(chip, entry->fid, entry->vid,
2827 ctx->port, ctx->cb, ctx->data);
2828 }
2829
mv88e6xxx_port_db_dump(struct mv88e6xxx_chip * chip,int port,dsa_fdb_dump_cb_t * cb,void * data)2830 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port,
2831 dsa_fdb_dump_cb_t *cb, void *data)
2832 {
2833 struct mv88e6xxx_port_db_dump_vlan_ctx ctx = {
2834 .port = port,
2835 .cb = cb,
2836 .data = data,
2837 };
2838 u16 fid;
2839 int err;
2840
2841 /* Dump port's default Filtering Information Database (VLAN ID 0) */
2842 err = mv88e6xxx_port_get_fid(chip, port, &fid);
2843 if (err)
2844 return err;
2845
2846 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data);
2847 if (err)
2848 return err;
2849
2850 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_db_dump_vlan, &ctx);
2851 }
2852
mv88e6xxx_port_fdb_dump(struct dsa_switch * ds,int port,dsa_fdb_dump_cb_t * cb,void * data)2853 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
2854 dsa_fdb_dump_cb_t *cb, void *data)
2855 {
2856 struct mv88e6xxx_chip *chip = ds->priv;
2857 int err;
2858
2859 mv88e6xxx_reg_lock(chip);
2860 err = mv88e6xxx_port_db_dump(chip, port, cb, data);
2861 mv88e6xxx_reg_unlock(chip);
2862
2863 return err;
2864 }
2865
mv88e6xxx_bridge_map(struct mv88e6xxx_chip * chip,struct dsa_bridge bridge)2866 static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip,
2867 struct dsa_bridge bridge)
2868 {
2869 struct dsa_switch *ds = chip->ds;
2870 struct dsa_switch_tree *dst = ds->dst;
2871 struct dsa_port *dp;
2872 int err;
2873
2874 list_for_each_entry(dp, &dst->ports, list) {
2875 if (dsa_port_offloads_bridge(dp, &bridge)) {
2876 if (dp->ds == ds) {
2877 /* This is a local bridge group member,
2878 * remap its Port VLAN Map.
2879 */
2880 err = mv88e6xxx_port_vlan_map(chip, dp->index);
2881 if (err)
2882 return err;
2883 } else {
2884 /* This is an external bridge group member,
2885 * remap its cross-chip Port VLAN Table entry.
2886 */
2887 err = mv88e6xxx_pvt_map(chip, dp->ds->index,
2888 dp->index);
2889 if (err)
2890 return err;
2891 }
2892 }
2893 }
2894
2895 return 0;
2896 }
2897
2898 /* Treat the software bridge as a virtual single-port switch behind the
2899 * CPU and map in the PVT. First dst->last_switch elements are taken by
2900 * physical switches, so start from beyond that range.
2901 */
mv88e6xxx_map_virtual_bridge_to_pvt(struct dsa_switch * ds,unsigned int bridge_num)2902 static int mv88e6xxx_map_virtual_bridge_to_pvt(struct dsa_switch *ds,
2903 unsigned int bridge_num)
2904 {
2905 u8 dev = bridge_num + ds->dst->last_switch;
2906 struct mv88e6xxx_chip *chip = ds->priv;
2907
2908 return mv88e6xxx_pvt_map(chip, dev, 0);
2909 }
2910
mv88e6xxx_port_bridge_join(struct dsa_switch * ds,int port,struct dsa_bridge bridge,bool * tx_fwd_offload,struct netlink_ext_ack * extack)2911 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
2912 struct dsa_bridge bridge,
2913 bool *tx_fwd_offload,
2914 struct netlink_ext_ack *extack)
2915 {
2916 struct mv88e6xxx_chip *chip = ds->priv;
2917 int err;
2918
2919 mv88e6xxx_reg_lock(chip);
2920
2921 err = mv88e6xxx_bridge_map(chip, bridge);
2922 if (err)
2923 goto unlock;
2924
2925 err = mv88e6xxx_port_set_map_da(chip, port, true);
2926 if (err)
2927 goto unlock;
2928
2929 err = mv88e6xxx_port_commit_pvid(chip, port);
2930 if (err)
2931 goto unlock;
2932
2933 if (mv88e6xxx_has_pvt(chip)) {
2934 err = mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num);
2935 if (err)
2936 goto unlock;
2937
2938 *tx_fwd_offload = true;
2939 }
2940
2941 unlock:
2942 mv88e6xxx_reg_unlock(chip);
2943
2944 return err;
2945 }
2946
mv88e6xxx_port_bridge_leave(struct dsa_switch * ds,int port,struct dsa_bridge bridge)2947 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port,
2948 struct dsa_bridge bridge)
2949 {
2950 struct mv88e6xxx_chip *chip = ds->priv;
2951 int err;
2952
2953 mv88e6xxx_reg_lock(chip);
2954
2955 if (bridge.tx_fwd_offload &&
2956 mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num))
2957 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n");
2958
2959 if (mv88e6xxx_bridge_map(chip, bridge) ||
2960 mv88e6xxx_port_vlan_map(chip, port))
2961 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n");
2962
2963 err = mv88e6xxx_port_set_map_da(chip, port, false);
2964 if (err)
2965 dev_err(ds->dev,
2966 "port %d failed to restore map-DA: %pe\n",
2967 port, ERR_PTR(err));
2968
2969 err = mv88e6xxx_port_commit_pvid(chip, port);
2970 if (err)
2971 dev_err(ds->dev,
2972 "port %d failed to restore standalone pvid: %pe\n",
2973 port, ERR_PTR(err));
2974
2975 mv88e6xxx_reg_unlock(chip);
2976 }
2977
mv88e6xxx_crosschip_bridge_join(struct dsa_switch * ds,int tree_index,int sw_index,int port,struct dsa_bridge bridge,struct netlink_ext_ack * extack)2978 static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds,
2979 int tree_index, int sw_index,
2980 int port, struct dsa_bridge bridge,
2981 struct netlink_ext_ack *extack)
2982 {
2983 struct mv88e6xxx_chip *chip = ds->priv;
2984 int err;
2985
2986 if (tree_index != ds->dst->index)
2987 return 0;
2988
2989 mv88e6xxx_reg_lock(chip);
2990 err = mv88e6xxx_pvt_map(chip, sw_index, port);
2991 err = err ? : mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num);
2992 mv88e6xxx_reg_unlock(chip);
2993
2994 return err;
2995 }
2996
mv88e6xxx_crosschip_bridge_leave(struct dsa_switch * ds,int tree_index,int sw_index,int port,struct dsa_bridge bridge)2997 static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds,
2998 int tree_index, int sw_index,
2999 int port, struct dsa_bridge bridge)
3000 {
3001 struct mv88e6xxx_chip *chip = ds->priv;
3002
3003 if (tree_index != ds->dst->index)
3004 return;
3005
3006 mv88e6xxx_reg_lock(chip);
3007 if (mv88e6xxx_pvt_map(chip, sw_index, port) ||
3008 mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num))
3009 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n");
3010 mv88e6xxx_reg_unlock(chip);
3011 }
3012
mv88e6xxx_software_reset(struct mv88e6xxx_chip * chip)3013 static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip)
3014 {
3015 if (chip->info->ops->reset)
3016 return chip->info->ops->reset(chip);
3017
3018 return 0;
3019 }
3020
mv88e6xxx_hardware_reset(struct mv88e6xxx_chip * chip)3021 static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip)
3022 {
3023 struct gpio_desc *gpiod = chip->reset;
3024 int err;
3025
3026 /* If there is a GPIO connected to the reset pin, toggle it */
3027 if (gpiod) {
3028 /* If the switch has just been reset and not yet completed
3029 * loading EEPROM, the reset may interrupt the I2C transaction
3030 * mid-byte, causing the first EEPROM read after the reset
3031 * from the wrong location resulting in the switch booting
3032 * to wrong mode and inoperable.
3033 * For this reason, switch families with EEPROM support
3034 * generally wait for EEPROM loads to complete as their pre-
3035 * and post-reset handlers.
3036 */
3037 if (chip->info->ops->hardware_reset_pre) {
3038 err = chip->info->ops->hardware_reset_pre(chip);
3039 if (err)
3040 dev_err(chip->dev, "pre-reset error: %d\n", err);
3041 }
3042
3043 gpiod_set_value_cansleep(gpiod, 1);
3044 usleep_range(10000, 20000);
3045 gpiod_set_value_cansleep(gpiod, 0);
3046 usleep_range(10000, 20000);
3047
3048 if (chip->info->ops->hardware_reset_post) {
3049 err = chip->info->ops->hardware_reset_post(chip);
3050 if (err)
3051 dev_err(chip->dev, "post-reset error: %d\n", err);
3052 }
3053 }
3054 }
3055
mv88e6xxx_disable_ports(struct mv88e6xxx_chip * chip)3056 static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip)
3057 {
3058 int i, err;
3059
3060 /* Set all ports to the Disabled state */
3061 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
3062 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED);
3063 if (err)
3064 return err;
3065 }
3066
3067 /* Wait for transmit queues to drain,
3068 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps.
3069 */
3070 usleep_range(2000, 4000);
3071
3072 return 0;
3073 }
3074
mv88e6xxx_switch_reset(struct mv88e6xxx_chip * chip)3075 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
3076 {
3077 int err;
3078
3079 err = mv88e6xxx_disable_ports(chip);
3080 if (err)
3081 return err;
3082
3083 mv88e6xxx_hardware_reset(chip);
3084
3085 return mv88e6xxx_software_reset(chip);
3086 }
3087
mv88e6xxx_set_port_mode(struct mv88e6xxx_chip * chip,int port,enum mv88e6xxx_frame_mode frame,enum mv88e6xxx_egress_mode egress,u16 etype)3088 static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port,
3089 enum mv88e6xxx_frame_mode frame,
3090 enum mv88e6xxx_egress_mode egress, u16 etype)
3091 {
3092 int err;
3093
3094 if (!chip->info->ops->port_set_frame_mode)
3095 return -EOPNOTSUPP;
3096
3097 err = mv88e6xxx_port_set_egress_mode(chip, port, egress);
3098 if (err)
3099 return err;
3100
3101 err = chip->info->ops->port_set_frame_mode(chip, port, frame);
3102 if (err)
3103 return err;
3104
3105 if (chip->info->ops->port_set_ether_type)
3106 return chip->info->ops->port_set_ether_type(chip, port, etype);
3107
3108 return 0;
3109 }
3110
mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip * chip,int port)3111 static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port)
3112 {
3113 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL,
3114 MV88E6XXX_EGRESS_MODE_UNMODIFIED,
3115 MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
3116 }
3117
mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip * chip,int port)3118 static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port)
3119 {
3120 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA,
3121 MV88E6XXX_EGRESS_MODE_UNMODIFIED,
3122 MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
3123 }
3124
mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip * chip,int port)3125 static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port)
3126 {
3127 return mv88e6xxx_set_port_mode(chip, port,
3128 MV88E6XXX_FRAME_MODE_ETHERTYPE,
3129 MV88E6XXX_EGRESS_MODE_ETHERTYPE,
3130 ETH_P_EDSA);
3131 }
3132
mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip * chip,int port)3133 static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port)
3134 {
3135 if (dsa_is_dsa_port(chip->ds, port))
3136 return mv88e6xxx_set_port_mode_dsa(chip, port);
3137
3138 if (dsa_is_user_port(chip->ds, port))
3139 return mv88e6xxx_set_port_mode_normal(chip, port);
3140
3141 /* Setup CPU port mode depending on its supported tag format */
3142 if (chip->tag_protocol == DSA_TAG_PROTO_DSA)
3143 return mv88e6xxx_set_port_mode_dsa(chip, port);
3144
3145 if (chip->tag_protocol == DSA_TAG_PROTO_EDSA)
3146 return mv88e6xxx_set_port_mode_edsa(chip, port);
3147
3148 return -EINVAL;
3149 }
3150
mv88e6xxx_setup_message_port(struct mv88e6xxx_chip * chip,int port)3151 static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port)
3152 {
3153 bool message = dsa_is_dsa_port(chip->ds, port);
3154
3155 return mv88e6xxx_port_set_message_port(chip, port, message);
3156 }
3157
mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip * chip,int port)3158 static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port)
3159 {
3160 int err;
3161
3162 if (chip->info->ops->port_set_ucast_flood) {
3163 err = chip->info->ops->port_set_ucast_flood(chip, port, true);
3164 if (err)
3165 return err;
3166 }
3167 if (chip->info->ops->port_set_mcast_flood) {
3168 err = chip->info->ops->port_set_mcast_flood(chip, port, true);
3169 if (err)
3170 return err;
3171 }
3172
3173 return 0;
3174 }
3175
mv88e6xxx_set_egress_port(struct mv88e6xxx_chip * chip,enum mv88e6xxx_egress_direction direction,int port)3176 static int mv88e6xxx_set_egress_port(struct mv88e6xxx_chip *chip,
3177 enum mv88e6xxx_egress_direction direction,
3178 int port)
3179 {
3180 int err;
3181
3182 if (!chip->info->ops->set_egress_port)
3183 return -EOPNOTSUPP;
3184
3185 err = chip->info->ops->set_egress_port(chip, direction, port);
3186 if (err)
3187 return err;
3188
3189 if (direction == MV88E6XXX_EGRESS_DIR_INGRESS)
3190 chip->ingress_dest_port = port;
3191 else
3192 chip->egress_dest_port = port;
3193
3194 return 0;
3195 }
3196
mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip * chip,int port)3197 static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port)
3198 {
3199 struct dsa_switch *ds = chip->ds;
3200 int upstream_port;
3201 int err;
3202
3203 upstream_port = dsa_upstream_port(ds, port);
3204 if (chip->info->ops->port_set_upstream_port) {
3205 err = chip->info->ops->port_set_upstream_port(chip, port,
3206 upstream_port);
3207 if (err)
3208 return err;
3209 }
3210
3211 if (port == upstream_port) {
3212 if (chip->info->ops->set_cpu_port) {
3213 err = chip->info->ops->set_cpu_port(chip,
3214 upstream_port);
3215 if (err)
3216 return err;
3217 }
3218
3219 err = mv88e6xxx_set_egress_port(chip,
3220 MV88E6XXX_EGRESS_DIR_INGRESS,
3221 upstream_port);
3222 if (err && err != -EOPNOTSUPP)
3223 return err;
3224
3225 err = mv88e6xxx_set_egress_port(chip,
3226 MV88E6XXX_EGRESS_DIR_EGRESS,
3227 upstream_port);
3228 if (err && err != -EOPNOTSUPP)
3229 return err;
3230 }
3231
3232 return 0;
3233 }
3234
mv88e6xxx_setup_port(struct mv88e6xxx_chip * chip,int port)3235 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
3236 {
3237 struct device_node *phy_handle = NULL;
3238 struct dsa_switch *ds = chip->ds;
3239 struct dsa_port *dp;
3240 int tx_amp;
3241 int err;
3242 u16 reg;
3243
3244 chip->ports[port].chip = chip;
3245 chip->ports[port].port = port;
3246
3247 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED,
3248 SPEED_UNFORCED, DUPLEX_UNFORCED,
3249 PAUSE_ON, PHY_INTERFACE_MODE_NA);
3250 if (err)
3251 return err;
3252
3253 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
3254 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
3255 * tunneling, determine priority by looking at 802.1p and IP
3256 * priority fields (IP prio has precedence), and set STP state
3257 * to Forwarding.
3258 *
3259 * If this is the CPU link, use DSA or EDSA tagging depending
3260 * on which tagging mode was configured.
3261 *
3262 * If this is a link to another switch, use DSA tagging mode.
3263 *
3264 * If this is the upstream port for this switch, enable
3265 * forwarding of unknown unicasts and multicasts.
3266 */
3267 reg = MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP |
3268 MV88E6XXX_PORT_CTL0_STATE_FORWARDING;
3269 /* Forward any IPv4 IGMP or IPv6 MLD frames received
3270 * by a USER port to the CPU port to allow snooping.
3271 */
3272 if (dsa_is_user_port(ds, port))
3273 reg |= MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP;
3274
3275 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
3276 if (err)
3277 return err;
3278
3279 err = mv88e6xxx_setup_port_mode(chip, port);
3280 if (err)
3281 return err;
3282
3283 err = mv88e6xxx_setup_egress_floods(chip, port);
3284 if (err)
3285 return err;
3286
3287 /* Port Control 2: don't force a good FCS, set the MTU size to
3288 * 10222 bytes, disable 802.1q tags checking, don't discard
3289 * tagged or untagged frames on this port, skip destination
3290 * address lookup on user ports, disable ARP mirroring and don't
3291 * send a copy of all transmitted/received frames on this port
3292 * to the CPU.
3293 */
3294 err = mv88e6xxx_port_set_map_da(chip, port, !dsa_is_user_port(ds, port));
3295 if (err)
3296 return err;
3297
3298 err = mv88e6xxx_setup_upstream_port(chip, port);
3299 if (err)
3300 return err;
3301
3302 /* On chips that support it, set all downstream DSA ports'
3303 * VLAN policy to TRAP. In combination with loading
3304 * MV88E6XXX_VID_STANDALONE as a policy entry in the VTU, this
3305 * provides a better isolation barrier between standalone
3306 * ports, as the ATU is bypassed on any intermediate switches
3307 * between the incoming port and the CPU.
3308 */
3309 if (dsa_is_downstream_port(ds, port) &&
3310 chip->info->ops->port_set_policy) {
3311 err = chip->info->ops->port_set_policy(chip, port,
3312 MV88E6XXX_POLICY_MAPPING_VTU,
3313 MV88E6XXX_POLICY_ACTION_TRAP);
3314 if (err)
3315 return err;
3316 }
3317
3318 /* User ports start out in standalone mode and 802.1Q is
3319 * therefore disabled. On DSA ports, all valid VIDs are always
3320 * loaded in the VTU - therefore, enable 802.1Q in order to take
3321 * advantage of VLAN policy on chips that supports it.
3322 */
3323 err = mv88e6xxx_port_set_8021q_mode(chip, port,
3324 dsa_is_user_port(ds, port) ?
3325 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED :
3326 MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE);
3327 if (err)
3328 return err;
3329
3330 /* Bind MV88E6XXX_VID_STANDALONE to MV88E6XXX_FID_STANDALONE by
3331 * virtue of the fact that mv88e6xxx_atu_new() will pick it as
3332 * the first free FID. This will be used as the private PVID for
3333 * unbridged ports. Shared (DSA and CPU) ports must also be
3334 * members of this VID, in order to trap all frames assigned to
3335 * it to the CPU.
3336 */
3337 err = mv88e6xxx_port_vlan_join(chip, port, MV88E6XXX_VID_STANDALONE,
3338 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED,
3339 false);
3340 if (err)
3341 return err;
3342
3343 /* Associate MV88E6XXX_VID_BRIDGED with MV88E6XXX_FID_BRIDGED in the
3344 * ATU by virtue of the fact that mv88e6xxx_atu_new() will pick it as
3345 * the first free FID after MV88E6XXX_FID_STANDALONE. This will be used
3346 * as the private PVID on ports under a VLAN-unaware bridge.
3347 * Shared (DSA and CPU) ports must also be members of it, to translate
3348 * the VID from the DSA tag into MV88E6XXX_FID_BRIDGED, instead of
3349 * relying on their port default FID.
3350 */
3351 err = mv88e6xxx_port_vlan_join(chip, port, MV88E6XXX_VID_BRIDGED,
3352 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED,
3353 false);
3354 if (err)
3355 return err;
3356
3357 if (chip->info->ops->port_set_jumbo_size) {
3358 err = chip->info->ops->port_set_jumbo_size(chip, port, 10218);
3359 if (err)
3360 return err;
3361 }
3362
3363 /* Port Association Vector: disable automatic address learning
3364 * on all user ports since they start out in standalone
3365 * mode. When joining a bridge, learning will be configured to
3366 * match the bridge port settings. Enable learning on all
3367 * DSA/CPU ports. NOTE: FROM_CPU frames always bypass the
3368 * learning process.
3369 *
3370 * Disable HoldAt1, IntOnAgeOut, LockedPort, IgnoreWrongData,
3371 * and RefreshLocked. I.e. setup standard automatic learning.
3372 */
3373 if (dsa_is_user_port(ds, port))
3374 reg = 0;
3375 else
3376 reg = 1 << port;
3377
3378 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR,
3379 reg);
3380 if (err)
3381 return err;
3382
3383 /* Egress rate control 2: disable egress rate control. */
3384 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2,
3385 0x0000);
3386 if (err)
3387 return err;
3388
3389 if (chip->info->ops->port_pause_limit) {
3390 err = chip->info->ops->port_pause_limit(chip, port, 0, 0);
3391 if (err)
3392 return err;
3393 }
3394
3395 if (chip->info->ops->port_disable_learn_limit) {
3396 err = chip->info->ops->port_disable_learn_limit(chip, port);
3397 if (err)
3398 return err;
3399 }
3400
3401 if (chip->info->ops->port_disable_pri_override) {
3402 err = chip->info->ops->port_disable_pri_override(chip, port);
3403 if (err)
3404 return err;
3405 }
3406
3407 if (chip->info->ops->port_tag_remap) {
3408 err = chip->info->ops->port_tag_remap(chip, port);
3409 if (err)
3410 return err;
3411 }
3412
3413 if (chip->info->ops->port_egress_rate_limiting) {
3414 err = chip->info->ops->port_egress_rate_limiting(chip, port);
3415 if (err)
3416 return err;
3417 }
3418
3419 if (chip->info->ops->port_setup_message_port) {
3420 err = chip->info->ops->port_setup_message_port(chip, port);
3421 if (err)
3422 return err;
3423 }
3424
3425 if (chip->info->ops->serdes_set_tx_amplitude) {
3426 dp = dsa_to_port(ds, port);
3427 if (dp)
3428 phy_handle = of_parse_phandle(dp->dn, "phy-handle", 0);
3429
3430 if (phy_handle && !of_property_read_u32(phy_handle,
3431 "tx-p2p-microvolt",
3432 &tx_amp))
3433 err = chip->info->ops->serdes_set_tx_amplitude(chip,
3434 port, tx_amp);
3435 if (phy_handle) {
3436 of_node_put(phy_handle);
3437 if (err)
3438 return err;
3439 }
3440 }
3441
3442 /* Port based VLAN map: give each port the same default address
3443 * database, and allow bidirectional communication between the
3444 * CPU and DSA port(s), and the other ports.
3445 */
3446 err = mv88e6xxx_port_set_fid(chip, port, MV88E6XXX_FID_STANDALONE);
3447 if (err)
3448 return err;
3449
3450 err = mv88e6xxx_port_vlan_map(chip, port);
3451 if (err)
3452 return err;
3453
3454 /* Default VLAN ID and priority: don't set a default VLAN
3455 * ID, and set the default packet priority to zero.
3456 */
3457 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0);
3458 }
3459
mv88e6xxx_get_max_mtu(struct dsa_switch * ds,int port)3460 static int mv88e6xxx_get_max_mtu(struct dsa_switch *ds, int port)
3461 {
3462 struct mv88e6xxx_chip *chip = ds->priv;
3463
3464 if (chip->info->ops->port_set_jumbo_size)
3465 return 10240 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN;
3466 else if (chip->info->ops->set_max_frame_size)
3467 return 1632 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN;
3468 return ETH_DATA_LEN;
3469 }
3470
mv88e6xxx_change_mtu(struct dsa_switch * ds,int port,int new_mtu)3471 static int mv88e6xxx_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
3472 {
3473 struct mv88e6xxx_chip *chip = ds->priv;
3474 int ret = 0;
3475
3476 /* For families where we don't know how to alter the MTU,
3477 * just accept any value up to ETH_DATA_LEN
3478 */
3479 if (!chip->info->ops->port_set_jumbo_size &&
3480 !chip->info->ops->set_max_frame_size) {
3481 if (new_mtu > ETH_DATA_LEN)
3482 return -EINVAL;
3483
3484 return 0;
3485 }
3486
3487 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
3488 new_mtu += EDSA_HLEN;
3489
3490 mv88e6xxx_reg_lock(chip);
3491 if (chip->info->ops->port_set_jumbo_size)
3492 ret = chip->info->ops->port_set_jumbo_size(chip, port, new_mtu);
3493 else if (chip->info->ops->set_max_frame_size &&
3494 dsa_is_cpu_port(ds, port))
3495 ret = chip->info->ops->set_max_frame_size(chip, new_mtu);
3496 mv88e6xxx_reg_unlock(chip);
3497
3498 return ret;
3499 }
3500
mv88e6xxx_set_ageing_time(struct dsa_switch * ds,unsigned int ageing_time)3501 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
3502 unsigned int ageing_time)
3503 {
3504 struct mv88e6xxx_chip *chip = ds->priv;
3505 int err;
3506
3507 mv88e6xxx_reg_lock(chip);
3508 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time);
3509 mv88e6xxx_reg_unlock(chip);
3510
3511 return err;
3512 }
3513
mv88e6xxx_stats_setup(struct mv88e6xxx_chip * chip)3514 static int mv88e6xxx_stats_setup(struct mv88e6xxx_chip *chip)
3515 {
3516 int err;
3517
3518 /* Initialize the statistics unit */
3519 if (chip->info->ops->stats_set_histogram) {
3520 err = chip->info->ops->stats_set_histogram(chip);
3521 if (err)
3522 return err;
3523 }
3524
3525 return mv88e6xxx_g1_stats_clear(chip);
3526 }
3527
3528 /* Check if the errata has already been applied. */
mv88e6390_setup_errata_applied(struct mv88e6xxx_chip * chip)3529 static bool mv88e6390_setup_errata_applied(struct mv88e6xxx_chip *chip)
3530 {
3531 int port;
3532 int err;
3533 u16 val;
3534
3535 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
3536 err = mv88e6xxx_port_hidden_read(chip, 0xf, port, 0, &val);
3537 if (err) {
3538 dev_err(chip->dev,
3539 "Error reading hidden register: %d\n", err);
3540 return false;
3541 }
3542 if (val != 0x01c0)
3543 return false;
3544 }
3545
3546 return true;
3547 }
3548
3549 /* The 6390 copper ports have an errata which require poking magic
3550 * values into undocumented hidden registers and then performing a
3551 * software reset.
3552 */
mv88e6390_setup_errata(struct mv88e6xxx_chip * chip)3553 static int mv88e6390_setup_errata(struct mv88e6xxx_chip *chip)
3554 {
3555 int port;
3556 int err;
3557
3558 if (mv88e6390_setup_errata_applied(chip))
3559 return 0;
3560
3561 /* Set the ports into blocking mode */
3562 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
3563 err = mv88e6xxx_port_set_state(chip, port, BR_STATE_DISABLED);
3564 if (err)
3565 return err;
3566 }
3567
3568 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
3569 err = mv88e6xxx_port_hidden_write(chip, 0xf, port, 0, 0x01c0);
3570 if (err)
3571 return err;
3572 }
3573
3574 return mv88e6xxx_software_reset(chip);
3575 }
3576
3577 /* prod_id for switch families which do not have a PHY model number */
3578 static const u16 family_prod_id_table[] = {
3579 [MV88E6XXX_FAMILY_6341] = MV88E6XXX_PORT_SWITCH_ID_PROD_6341,
3580 [MV88E6XXX_FAMILY_6390] = MV88E6XXX_PORT_SWITCH_ID_PROD_6390,
3581 [MV88E6XXX_FAMILY_6393] = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X,
3582 };
3583
mv88e6xxx_mdio_read(struct mii_bus * bus,int phy,int reg)3584 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg)
3585 {
3586 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
3587 struct mv88e6xxx_chip *chip = mdio_bus->chip;
3588 u16 prod_id;
3589 u16 val;
3590 int err;
3591
3592 if (!chip->info->ops->phy_read)
3593 return -EOPNOTSUPP;
3594
3595 mv88e6xxx_reg_lock(chip);
3596 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val);
3597 mv88e6xxx_reg_unlock(chip);
3598
3599 /* Some internal PHYs don't have a model number. */
3600 if (reg == MII_PHYSID2 && !(val & 0x3f0) &&
3601 chip->info->family < ARRAY_SIZE(family_prod_id_table)) {
3602 prod_id = family_prod_id_table[chip->info->family];
3603 if (prod_id)
3604 val |= prod_id >> 4;
3605 }
3606
3607 return err ? err : val;
3608 }
3609
mv88e6xxx_mdio_read_c45(struct mii_bus * bus,int phy,int devad,int reg)3610 static int mv88e6xxx_mdio_read_c45(struct mii_bus *bus, int phy, int devad,
3611 int reg)
3612 {
3613 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
3614 struct mv88e6xxx_chip *chip = mdio_bus->chip;
3615 u16 val;
3616 int err;
3617
3618 if (!chip->info->ops->phy_read_c45)
3619 return 0xffff;
3620
3621 mv88e6xxx_reg_lock(chip);
3622 err = chip->info->ops->phy_read_c45(chip, bus, phy, devad, reg, &val);
3623 mv88e6xxx_reg_unlock(chip);
3624
3625 return err ? err : val;
3626 }
3627
mv88e6xxx_mdio_write(struct mii_bus * bus,int phy,int reg,u16 val)3628 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
3629 {
3630 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
3631 struct mv88e6xxx_chip *chip = mdio_bus->chip;
3632 int err;
3633
3634 if (!chip->info->ops->phy_write)
3635 return -EOPNOTSUPP;
3636
3637 mv88e6xxx_reg_lock(chip);
3638 err = chip->info->ops->phy_write(chip, bus, phy, reg, val);
3639 mv88e6xxx_reg_unlock(chip);
3640
3641 return err;
3642 }
3643
mv88e6xxx_mdio_write_c45(struct mii_bus * bus,int phy,int devad,int reg,u16 val)3644 static int mv88e6xxx_mdio_write_c45(struct mii_bus *bus, int phy, int devad,
3645 int reg, u16 val)
3646 {
3647 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
3648 struct mv88e6xxx_chip *chip = mdio_bus->chip;
3649 int err;
3650
3651 if (!chip->info->ops->phy_write_c45)
3652 return -EOPNOTSUPP;
3653
3654 mv88e6xxx_reg_lock(chip);
3655 err = chip->info->ops->phy_write_c45(chip, bus, phy, devad, reg, val);
3656 mv88e6xxx_reg_unlock(chip);
3657
3658 return err;
3659 }
3660
mv88e6xxx_mdio_register(struct mv88e6xxx_chip * chip,struct device_node * np,bool external)3661 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
3662 struct device_node *np,
3663 bool external)
3664 {
3665 static int index;
3666 struct mv88e6xxx_mdio_bus *mdio_bus;
3667 struct mii_bus *bus;
3668 int err;
3669
3670 if (external) {
3671 mv88e6xxx_reg_lock(chip);
3672 err = mv88e6xxx_g2_scratch_gpio_set_smi(chip, true);
3673 mv88e6xxx_reg_unlock(chip);
3674
3675 if (err)
3676 return err;
3677 }
3678
3679 bus = mdiobus_alloc_size(sizeof(*mdio_bus));
3680 if (!bus)
3681 return -ENOMEM;
3682
3683 mdio_bus = bus->priv;
3684 mdio_bus->bus = bus;
3685 mdio_bus->chip = chip;
3686 INIT_LIST_HEAD(&mdio_bus->list);
3687 mdio_bus->external = external;
3688
3689 if (np) {
3690 bus->name = np->full_name;
3691 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np);
3692 } else {
3693 bus->name = "mv88e6xxx SMI";
3694 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
3695 }
3696
3697 bus->read = mv88e6xxx_mdio_read;
3698 bus->write = mv88e6xxx_mdio_write;
3699 bus->read_c45 = mv88e6xxx_mdio_read_c45;
3700 bus->write_c45 = mv88e6xxx_mdio_write_c45;
3701 bus->parent = chip->dev;
3702 bus->phy_mask = ~GENMASK(chip->info->phy_base_addr +
3703 mv88e6xxx_num_ports(chip) - 1,
3704 chip->info->phy_base_addr);
3705
3706 if (!external) {
3707 err = mv88e6xxx_g2_irq_mdio_setup(chip, bus);
3708 if (err)
3709 goto out;
3710 }
3711
3712 err = of_mdiobus_register(bus, np);
3713 if (err) {
3714 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
3715 mv88e6xxx_g2_irq_mdio_free(chip, bus);
3716 goto out;
3717 }
3718
3719 if (external)
3720 list_add_tail(&mdio_bus->list, &chip->mdios);
3721 else
3722 list_add(&mdio_bus->list, &chip->mdios);
3723
3724 return 0;
3725
3726 out:
3727 mdiobus_free(bus);
3728 return err;
3729 }
3730
mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip * chip)3731 static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip)
3732
3733 {
3734 struct mv88e6xxx_mdio_bus *mdio_bus, *p;
3735 struct mii_bus *bus;
3736
3737 list_for_each_entry_safe(mdio_bus, p, &chip->mdios, list) {
3738 bus = mdio_bus->bus;
3739
3740 if (!mdio_bus->external)
3741 mv88e6xxx_g2_irq_mdio_free(chip, bus);
3742
3743 mdiobus_unregister(bus);
3744 mdiobus_free(bus);
3745 }
3746 }
3747
mv88e6xxx_mdios_register(struct mv88e6xxx_chip * chip)3748 static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip)
3749 {
3750 struct device_node *np = chip->dev->of_node;
3751 struct device_node *child;
3752 int err;
3753
3754 /* Always register one mdio bus for the internal/default mdio
3755 * bus. This maybe represented in the device tree, but is
3756 * optional.
3757 */
3758 child = of_get_child_by_name(np, "mdio");
3759 err = mv88e6xxx_mdio_register(chip, child, false);
3760 of_node_put(child);
3761 if (err)
3762 return err;
3763
3764 /* Walk the device tree, and see if there are any other nodes
3765 * which say they are compatible with the external mdio
3766 * bus.
3767 */
3768 for_each_available_child_of_node(np, child) {
3769 if (of_device_is_compatible(
3770 child, "marvell,mv88e6xxx-mdio-external")) {
3771 err = mv88e6xxx_mdio_register(chip, child, true);
3772 if (err) {
3773 mv88e6xxx_mdios_unregister(chip);
3774 of_node_put(child);
3775 return err;
3776 }
3777 }
3778 }
3779
3780 return 0;
3781 }
3782
mv88e6xxx_teardown(struct dsa_switch * ds)3783 static void mv88e6xxx_teardown(struct dsa_switch *ds)
3784 {
3785 struct mv88e6xxx_chip *chip = ds->priv;
3786
3787 mv88e6xxx_teardown_devlink_params(ds);
3788 dsa_devlink_resources_unregister(ds);
3789 mv88e6xxx_teardown_devlink_regions_global(ds);
3790 mv88e6xxx_mdios_unregister(chip);
3791 }
3792
mv88e6xxx_setup(struct dsa_switch * ds)3793 static int mv88e6xxx_setup(struct dsa_switch *ds)
3794 {
3795 struct mv88e6xxx_chip *chip = ds->priv;
3796 u8 cmode;
3797 int err;
3798 int i;
3799
3800 err = mv88e6xxx_mdios_register(chip);
3801 if (err)
3802 return err;
3803
3804 chip->ds = ds;
3805 ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip);
3806
3807 /* Since virtual bridges are mapped in the PVT, the number we support
3808 * depends on the physical switch topology. We need to let DSA figure
3809 * that out and therefore we cannot set this at dsa_register_switch()
3810 * time.
3811 */
3812 if (mv88e6xxx_has_pvt(chip))
3813 ds->max_num_bridges = MV88E6XXX_MAX_PVT_SWITCHES -
3814 ds->dst->last_switch - 1;
3815
3816 mv88e6xxx_reg_lock(chip);
3817
3818 if (chip->info->ops->setup_errata) {
3819 err = chip->info->ops->setup_errata(chip);
3820 if (err)
3821 goto unlock;
3822 }
3823
3824 /* Cache the cmode of each port. */
3825 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
3826 if (chip->info->ops->port_get_cmode) {
3827 err = chip->info->ops->port_get_cmode(chip, i, &cmode);
3828 if (err)
3829 goto unlock;
3830
3831 chip->ports[i].cmode = cmode;
3832 }
3833 }
3834
3835 err = mv88e6xxx_vtu_setup(chip);
3836 if (err)
3837 goto unlock;
3838
3839 /* Must be called after mv88e6xxx_vtu_setup (which flushes the
3840 * VTU, thereby also flushing the STU).
3841 */
3842 err = mv88e6xxx_stu_setup(chip);
3843 if (err)
3844 goto unlock;
3845
3846 /* Setup Switch Port Registers */
3847 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
3848 if (dsa_is_unused_port(ds, i))
3849 continue;
3850
3851 /* Prevent the use of an invalid port. */
3852 if (mv88e6xxx_is_invalid_port(chip, i)) {
3853 dev_err(chip->dev, "port %d is invalid\n", i);
3854 err = -EINVAL;
3855 goto unlock;
3856 }
3857
3858 err = mv88e6xxx_setup_port(chip, i);
3859 if (err)
3860 goto unlock;
3861 }
3862
3863 err = mv88e6xxx_irl_setup(chip);
3864 if (err)
3865 goto unlock;
3866
3867 err = mv88e6xxx_mac_setup(chip);
3868 if (err)
3869 goto unlock;
3870
3871 err = mv88e6xxx_phy_setup(chip);
3872 if (err)
3873 goto unlock;
3874
3875 err = mv88e6xxx_pvt_setup(chip);
3876 if (err)
3877 goto unlock;
3878
3879 err = mv88e6xxx_atu_setup(chip);
3880 if (err)
3881 goto unlock;
3882
3883 err = mv88e6xxx_broadcast_setup(chip, 0);
3884 if (err)
3885 goto unlock;
3886
3887 err = mv88e6xxx_pot_setup(chip);
3888 if (err)
3889 goto unlock;
3890
3891 err = mv88e6xxx_rmu_setup(chip);
3892 if (err)
3893 goto unlock;
3894
3895 err = mv88e6xxx_rsvd2cpu_setup(chip);
3896 if (err)
3897 goto unlock;
3898
3899 err = mv88e6xxx_trunk_setup(chip);
3900 if (err)
3901 goto unlock;
3902
3903 err = mv88e6xxx_devmap_setup(chip);
3904 if (err)
3905 goto unlock;
3906
3907 err = mv88e6xxx_pri_setup(chip);
3908 if (err)
3909 goto unlock;
3910
3911 /* Setup PTP Hardware Clock and timestamping */
3912 if (chip->info->ptp_support) {
3913 err = mv88e6xxx_ptp_setup(chip);
3914 if (err)
3915 goto unlock;
3916
3917 err = mv88e6xxx_hwtstamp_setup(chip);
3918 if (err)
3919 goto unlock;
3920 }
3921
3922 err = mv88e6xxx_stats_setup(chip);
3923 if (err)
3924 goto unlock;
3925
3926 unlock:
3927 mv88e6xxx_reg_unlock(chip);
3928
3929 if (err)
3930 goto out_mdios;
3931
3932 /* Have to be called without holding the register lock, since
3933 * they take the devlink lock, and we later take the locks in
3934 * the reverse order when getting/setting parameters or
3935 * resource occupancy.
3936 */
3937 err = mv88e6xxx_setup_devlink_resources(ds);
3938 if (err)
3939 goto out_mdios;
3940
3941 err = mv88e6xxx_setup_devlink_params(ds);
3942 if (err)
3943 goto out_resources;
3944
3945 err = mv88e6xxx_setup_devlink_regions_global(ds);
3946 if (err)
3947 goto out_params;
3948
3949 return 0;
3950
3951 out_params:
3952 mv88e6xxx_teardown_devlink_params(ds);
3953 out_resources:
3954 dsa_devlink_resources_unregister(ds);
3955 out_mdios:
3956 mv88e6xxx_mdios_unregister(chip);
3957
3958 return err;
3959 }
3960
mv88e6xxx_port_setup(struct dsa_switch * ds,int port)3961 static int mv88e6xxx_port_setup(struct dsa_switch *ds, int port)
3962 {
3963 struct mv88e6xxx_chip *chip = ds->priv;
3964 int err;
3965
3966 if (chip->info->ops->pcs_ops &&
3967 chip->info->ops->pcs_ops->pcs_init) {
3968 err = chip->info->ops->pcs_ops->pcs_init(chip, port);
3969 if (err)
3970 return err;
3971 }
3972
3973 return mv88e6xxx_setup_devlink_regions_port(ds, port);
3974 }
3975
mv88e6xxx_port_teardown(struct dsa_switch * ds,int port)3976 static void mv88e6xxx_port_teardown(struct dsa_switch *ds, int port)
3977 {
3978 struct mv88e6xxx_chip *chip = ds->priv;
3979
3980 mv88e6xxx_teardown_devlink_regions_port(ds, port);
3981
3982 if (chip->info->ops->pcs_ops &&
3983 chip->info->ops->pcs_ops->pcs_teardown)
3984 chip->info->ops->pcs_ops->pcs_teardown(chip, port);
3985 }
3986
mv88e6xxx_get_eeprom_len(struct dsa_switch * ds)3987 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
3988 {
3989 struct mv88e6xxx_chip *chip = ds->priv;
3990
3991 return chip->eeprom_len;
3992 }
3993
mv88e6xxx_get_eeprom(struct dsa_switch * ds,struct ethtool_eeprom * eeprom,u8 * data)3994 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
3995 struct ethtool_eeprom *eeprom, u8 *data)
3996 {
3997 struct mv88e6xxx_chip *chip = ds->priv;
3998 int err;
3999
4000 if (!chip->info->ops->get_eeprom)
4001 return -EOPNOTSUPP;
4002
4003 mv88e6xxx_reg_lock(chip);
4004 err = chip->info->ops->get_eeprom(chip, eeprom, data);
4005 mv88e6xxx_reg_unlock(chip);
4006
4007 if (err)
4008 return err;
4009
4010 eeprom->magic = 0xc3ec4951;
4011
4012 return 0;
4013 }
4014
mv88e6xxx_set_eeprom(struct dsa_switch * ds,struct ethtool_eeprom * eeprom,u8 * data)4015 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
4016 struct ethtool_eeprom *eeprom, u8 *data)
4017 {
4018 struct mv88e6xxx_chip *chip = ds->priv;
4019 int err;
4020
4021 if (!chip->info->ops->set_eeprom)
4022 return -EOPNOTSUPP;
4023
4024 if (eeprom->magic != 0xc3ec4951)
4025 return -EINVAL;
4026
4027 mv88e6xxx_reg_lock(chip);
4028 err = chip->info->ops->set_eeprom(chip, eeprom, data);
4029 mv88e6xxx_reg_unlock(chip);
4030
4031 return err;
4032 }
4033
4034 static const struct mv88e6xxx_ops mv88e6085_ops = {
4035 /* MV88E6XXX_FAMILY_6097 */
4036 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4037 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4038 .irl_init_all = mv88e6352_g2_irl_init_all,
4039 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
4040 .phy_read = mv88e6185_phy_ppu_read,
4041 .phy_write = mv88e6185_phy_ppu_write,
4042 .port_set_link = mv88e6xxx_port_set_link,
4043 .port_sync_link = mv88e6xxx_port_sync_link,
4044 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4045 .port_tag_remap = mv88e6095_port_tag_remap,
4046 .port_set_policy = mv88e6352_port_set_policy,
4047 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4048 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4049 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4050 .port_set_ether_type = mv88e6351_port_set_ether_type,
4051 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4052 .port_pause_limit = mv88e6097_port_pause_limit,
4053 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4054 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4055 .port_get_cmode = mv88e6185_port_get_cmode,
4056 .port_setup_message_port = mv88e6xxx_setup_message_port,
4057 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4058 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4059 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4060 .stats_get_strings = mv88e6095_stats_get_strings,
4061 .stats_get_stats = mv88e6095_stats_get_stats,
4062 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4063 .set_egress_port = mv88e6095_g1_set_egress_port,
4064 .watchdog_ops = &mv88e6097_watchdog_ops,
4065 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4066 .pot_clear = mv88e6xxx_g2_pot_clear,
4067 .ppu_enable = mv88e6185_g1_ppu_enable,
4068 .ppu_disable = mv88e6185_g1_ppu_disable,
4069 .reset = mv88e6185_g1_reset,
4070 .rmu_disable = mv88e6085_g1_rmu_disable,
4071 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4072 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4073 .stu_getnext = mv88e6352_g1_stu_getnext,
4074 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4075 .phylink_get_caps = mv88e6185_phylink_get_caps,
4076 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
4077 };
4078
4079 static const struct mv88e6xxx_ops mv88e6095_ops = {
4080 /* MV88E6XXX_FAMILY_6095 */
4081 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4082 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4083 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
4084 .phy_read = mv88e6185_phy_ppu_read,
4085 .phy_write = mv88e6185_phy_ppu_write,
4086 .port_set_link = mv88e6xxx_port_set_link,
4087 .port_sync_link = mv88e6185_port_sync_link,
4088 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4089 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
4090 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown,
4091 .port_set_mcast_flood = mv88e6185_port_set_default_forward,
4092 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
4093 .port_get_cmode = mv88e6185_port_get_cmode,
4094 .port_setup_message_port = mv88e6xxx_setup_message_port,
4095 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4096 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4097 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4098 .stats_get_strings = mv88e6095_stats_get_strings,
4099 .stats_get_stats = mv88e6095_stats_get_stats,
4100 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
4101 .ppu_enable = mv88e6185_g1_ppu_enable,
4102 .ppu_disable = mv88e6185_g1_ppu_disable,
4103 .reset = mv88e6185_g1_reset,
4104 .vtu_getnext = mv88e6185_g1_vtu_getnext,
4105 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
4106 .phylink_get_caps = mv88e6095_phylink_get_caps,
4107 .pcs_ops = &mv88e6185_pcs_ops,
4108 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
4109 };
4110
4111 static const struct mv88e6xxx_ops mv88e6097_ops = {
4112 /* MV88E6XXX_FAMILY_6097 */
4113 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4114 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4115 .irl_init_all = mv88e6352_g2_irl_init_all,
4116 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4117 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4118 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4119 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4120 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4121 .port_set_link = mv88e6xxx_port_set_link,
4122 .port_sync_link = mv88e6185_port_sync_link,
4123 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4124 .port_tag_remap = mv88e6095_port_tag_remap,
4125 .port_set_policy = mv88e6352_port_set_policy,
4126 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4127 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4128 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4129 .port_set_ether_type = mv88e6351_port_set_ether_type,
4130 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
4131 .port_pause_limit = mv88e6097_port_pause_limit,
4132 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4133 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4134 .port_get_cmode = mv88e6185_port_get_cmode,
4135 .port_setup_message_port = mv88e6xxx_setup_message_port,
4136 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4137 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4138 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4139 .stats_get_strings = mv88e6095_stats_get_strings,
4140 .stats_get_stats = mv88e6095_stats_get_stats,
4141 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4142 .set_egress_port = mv88e6095_g1_set_egress_port,
4143 .watchdog_ops = &mv88e6097_watchdog_ops,
4144 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4145 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4146 .pot_clear = mv88e6xxx_g2_pot_clear,
4147 .reset = mv88e6352_g1_reset,
4148 .rmu_disable = mv88e6085_g1_rmu_disable,
4149 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4150 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4151 .phylink_get_caps = mv88e6095_phylink_get_caps,
4152 .pcs_ops = &mv88e6185_pcs_ops,
4153 .stu_getnext = mv88e6352_g1_stu_getnext,
4154 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4155 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
4156 };
4157
4158 static const struct mv88e6xxx_ops mv88e6123_ops = {
4159 /* MV88E6XXX_FAMILY_6165 */
4160 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4161 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4162 .irl_init_all = mv88e6352_g2_irl_init_all,
4163 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4164 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4165 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4166 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4167 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4168 .port_set_link = mv88e6xxx_port_set_link,
4169 .port_sync_link = mv88e6xxx_port_sync_link,
4170 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4171 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
4172 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4173 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4174 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4175 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4176 .port_get_cmode = mv88e6185_port_get_cmode,
4177 .port_setup_message_port = mv88e6xxx_setup_message_port,
4178 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4179 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4180 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4181 .stats_get_strings = mv88e6095_stats_get_strings,
4182 .stats_get_stats = mv88e6095_stats_get_stats,
4183 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4184 .set_egress_port = mv88e6095_g1_set_egress_port,
4185 .watchdog_ops = &mv88e6097_watchdog_ops,
4186 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4187 .pot_clear = mv88e6xxx_g2_pot_clear,
4188 .reset = mv88e6352_g1_reset,
4189 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4190 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4191 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4192 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4193 .stu_getnext = mv88e6352_g1_stu_getnext,
4194 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4195 .phylink_get_caps = mv88e6185_phylink_get_caps,
4196 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
4197 };
4198
4199 static const struct mv88e6xxx_ops mv88e6131_ops = {
4200 /* MV88E6XXX_FAMILY_6185 */
4201 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4202 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4203 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
4204 .phy_read = mv88e6185_phy_ppu_read,
4205 .phy_write = mv88e6185_phy_ppu_write,
4206 .port_set_link = mv88e6xxx_port_set_link,
4207 .port_sync_link = mv88e6xxx_port_sync_link,
4208 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4209 .port_tag_remap = mv88e6095_port_tag_remap,
4210 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4211 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown,
4212 .port_set_mcast_flood = mv88e6185_port_set_default_forward,
4213 .port_set_ether_type = mv88e6351_port_set_ether_type,
4214 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
4215 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4216 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4217 .port_pause_limit = mv88e6097_port_pause_limit,
4218 .port_set_pause = mv88e6185_port_set_pause,
4219 .port_get_cmode = mv88e6185_port_get_cmode,
4220 .port_setup_message_port = mv88e6xxx_setup_message_port,
4221 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4222 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4223 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4224 .stats_get_strings = mv88e6095_stats_get_strings,
4225 .stats_get_stats = mv88e6095_stats_get_stats,
4226 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4227 .set_egress_port = mv88e6095_g1_set_egress_port,
4228 .watchdog_ops = &mv88e6097_watchdog_ops,
4229 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
4230 .ppu_enable = mv88e6185_g1_ppu_enable,
4231 .set_cascade_port = mv88e6185_g1_set_cascade_port,
4232 .ppu_disable = mv88e6185_g1_ppu_disable,
4233 .reset = mv88e6185_g1_reset,
4234 .vtu_getnext = mv88e6185_g1_vtu_getnext,
4235 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
4236 .phylink_get_caps = mv88e6185_phylink_get_caps,
4237 };
4238
4239 static const struct mv88e6xxx_ops mv88e6141_ops = {
4240 /* MV88E6XXX_FAMILY_6341 */
4241 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4242 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4243 .irl_init_all = mv88e6352_g2_irl_init_all,
4244 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4245 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4246 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4247 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4248 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4249 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4250 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4251 .port_set_link = mv88e6xxx_port_set_link,
4252 .port_sync_link = mv88e6xxx_port_sync_link,
4253 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4254 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex,
4255 .port_max_speed_mode = mv88e6341_port_max_speed_mode,
4256 .port_tag_remap = mv88e6095_port_tag_remap,
4257 .port_set_policy = mv88e6352_port_set_policy,
4258 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4259 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4260 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4261 .port_set_ether_type = mv88e6351_port_set_ether_type,
4262 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4263 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4264 .port_pause_limit = mv88e6097_port_pause_limit,
4265 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4266 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4267 .port_get_cmode = mv88e6352_port_get_cmode,
4268 .port_set_cmode = mv88e6341_port_set_cmode,
4269 .port_setup_message_port = mv88e6xxx_setup_message_port,
4270 .stats_snapshot = mv88e6390_g1_stats_snapshot,
4271 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4272 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4273 .stats_get_strings = mv88e6320_stats_get_strings,
4274 .stats_get_stats = mv88e6390_stats_get_stats,
4275 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4276 .set_egress_port = mv88e6390_g1_set_egress_port,
4277 .watchdog_ops = &mv88e6390_watchdog_ops,
4278 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4279 .pot_clear = mv88e6xxx_g2_pot_clear,
4280 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
4281 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
4282 .reset = mv88e6352_g1_reset,
4283 .rmu_disable = mv88e6390_g1_rmu_disable,
4284 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4285 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4286 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4287 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4288 .stu_getnext = mv88e6352_g1_stu_getnext,
4289 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4290 .serdes_get_lane = mv88e6341_serdes_get_lane,
4291 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4292 .gpio_ops = &mv88e6352_gpio_ops,
4293 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
4294 .serdes_get_strings = mv88e6390_serdes_get_strings,
4295 .serdes_get_stats = mv88e6390_serdes_get_stats,
4296 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4297 .serdes_get_regs = mv88e6390_serdes_get_regs,
4298 .phylink_get_caps = mv88e6341_phylink_get_caps,
4299 .pcs_ops = &mv88e6390_pcs_ops,
4300 };
4301
4302 static const struct mv88e6xxx_ops mv88e6161_ops = {
4303 /* MV88E6XXX_FAMILY_6165 */
4304 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4305 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4306 .irl_init_all = mv88e6352_g2_irl_init_all,
4307 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4308 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4309 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4310 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4311 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4312 .port_set_link = mv88e6xxx_port_set_link,
4313 .port_sync_link = mv88e6xxx_port_sync_link,
4314 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4315 .port_tag_remap = mv88e6095_port_tag_remap,
4316 .port_set_policy = mv88e6352_port_set_policy,
4317 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4318 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4319 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4320 .port_set_ether_type = mv88e6351_port_set_ether_type,
4321 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4322 .port_pause_limit = mv88e6097_port_pause_limit,
4323 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4324 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4325 .port_get_cmode = mv88e6185_port_get_cmode,
4326 .port_setup_message_port = mv88e6xxx_setup_message_port,
4327 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4328 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4329 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4330 .stats_get_strings = mv88e6095_stats_get_strings,
4331 .stats_get_stats = mv88e6095_stats_get_stats,
4332 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4333 .set_egress_port = mv88e6095_g1_set_egress_port,
4334 .watchdog_ops = &mv88e6097_watchdog_ops,
4335 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4336 .pot_clear = mv88e6xxx_g2_pot_clear,
4337 .reset = mv88e6352_g1_reset,
4338 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4339 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4340 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4341 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4342 .stu_getnext = mv88e6352_g1_stu_getnext,
4343 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4344 .avb_ops = &mv88e6165_avb_ops,
4345 .ptp_ops = &mv88e6165_ptp_ops,
4346 .phylink_get_caps = mv88e6185_phylink_get_caps,
4347 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
4348 };
4349
4350 static const struct mv88e6xxx_ops mv88e6165_ops = {
4351 /* MV88E6XXX_FAMILY_6165 */
4352 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4353 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4354 .irl_init_all = mv88e6352_g2_irl_init_all,
4355 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4356 .phy_read = mv88e6165_phy_read,
4357 .phy_write = mv88e6165_phy_write,
4358 .port_set_link = mv88e6xxx_port_set_link,
4359 .port_sync_link = mv88e6xxx_port_sync_link,
4360 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4361 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4362 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4363 .port_get_cmode = mv88e6185_port_get_cmode,
4364 .port_setup_message_port = mv88e6xxx_setup_message_port,
4365 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4366 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4367 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4368 .stats_get_strings = mv88e6095_stats_get_strings,
4369 .stats_get_stats = mv88e6095_stats_get_stats,
4370 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4371 .set_egress_port = mv88e6095_g1_set_egress_port,
4372 .watchdog_ops = &mv88e6097_watchdog_ops,
4373 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4374 .pot_clear = mv88e6xxx_g2_pot_clear,
4375 .reset = mv88e6352_g1_reset,
4376 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4377 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4378 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4379 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4380 .stu_getnext = mv88e6352_g1_stu_getnext,
4381 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4382 .avb_ops = &mv88e6165_avb_ops,
4383 .ptp_ops = &mv88e6165_ptp_ops,
4384 .phylink_get_caps = mv88e6185_phylink_get_caps,
4385 };
4386
4387 static const struct mv88e6xxx_ops mv88e6171_ops = {
4388 /* MV88E6XXX_FAMILY_6351 */
4389 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4390 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4391 .irl_init_all = mv88e6352_g2_irl_init_all,
4392 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4393 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4394 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4395 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4396 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4397 .port_set_link = mv88e6xxx_port_set_link,
4398 .port_sync_link = mv88e6xxx_port_sync_link,
4399 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4400 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4401 .port_tag_remap = mv88e6095_port_tag_remap,
4402 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4403 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4404 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4405 .port_set_ether_type = mv88e6351_port_set_ether_type,
4406 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4407 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4408 .port_pause_limit = mv88e6097_port_pause_limit,
4409 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4410 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4411 .port_get_cmode = mv88e6352_port_get_cmode,
4412 .port_setup_message_port = mv88e6xxx_setup_message_port,
4413 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4414 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4415 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4416 .stats_get_strings = mv88e6095_stats_get_strings,
4417 .stats_get_stats = mv88e6095_stats_get_stats,
4418 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4419 .set_egress_port = mv88e6095_g1_set_egress_port,
4420 .watchdog_ops = &mv88e6097_watchdog_ops,
4421 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4422 .pot_clear = mv88e6xxx_g2_pot_clear,
4423 .reset = mv88e6352_g1_reset,
4424 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4425 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4426 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4427 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4428 .stu_getnext = mv88e6352_g1_stu_getnext,
4429 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4430 .phylink_get_caps = mv88e6351_phylink_get_caps,
4431 };
4432
4433 static const struct mv88e6xxx_ops mv88e6172_ops = {
4434 /* MV88E6XXX_FAMILY_6352 */
4435 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4436 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4437 .irl_init_all = mv88e6352_g2_irl_init_all,
4438 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4439 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4440 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4441 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4442 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4443 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4444 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4445 .port_set_link = mv88e6xxx_port_set_link,
4446 .port_sync_link = mv88e6xxx_port_sync_link,
4447 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4448 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
4449 .port_tag_remap = mv88e6095_port_tag_remap,
4450 .port_set_policy = mv88e6352_port_set_policy,
4451 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4452 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4453 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4454 .port_set_ether_type = mv88e6351_port_set_ether_type,
4455 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4456 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4457 .port_pause_limit = mv88e6097_port_pause_limit,
4458 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4459 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4460 .port_get_cmode = mv88e6352_port_get_cmode,
4461 .port_setup_message_port = mv88e6xxx_setup_message_port,
4462 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4463 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4464 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4465 .stats_get_strings = mv88e6095_stats_get_strings,
4466 .stats_get_stats = mv88e6095_stats_get_stats,
4467 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4468 .set_egress_port = mv88e6095_g1_set_egress_port,
4469 .watchdog_ops = &mv88e6097_watchdog_ops,
4470 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4471 .pot_clear = mv88e6xxx_g2_pot_clear,
4472 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
4473 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
4474 .reset = mv88e6352_g1_reset,
4475 .rmu_disable = mv88e6352_g1_rmu_disable,
4476 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4477 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4478 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4479 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4480 .stu_getnext = mv88e6352_g1_stu_getnext,
4481 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4482 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
4483 .serdes_get_regs = mv88e6352_serdes_get_regs,
4484 .gpio_ops = &mv88e6352_gpio_ops,
4485 .phylink_get_caps = mv88e6352_phylink_get_caps,
4486 .pcs_ops = &mv88e6352_pcs_ops,
4487 };
4488
4489 static const struct mv88e6xxx_ops mv88e6175_ops = {
4490 /* MV88E6XXX_FAMILY_6351 */
4491 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4492 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4493 .irl_init_all = mv88e6352_g2_irl_init_all,
4494 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4495 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4496 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4497 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4498 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4499 .port_set_link = mv88e6xxx_port_set_link,
4500 .port_sync_link = mv88e6xxx_port_sync_link,
4501 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4502 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4503 .port_tag_remap = mv88e6095_port_tag_remap,
4504 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4505 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4506 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4507 .port_set_ether_type = mv88e6351_port_set_ether_type,
4508 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4509 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4510 .port_pause_limit = mv88e6097_port_pause_limit,
4511 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4512 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4513 .port_get_cmode = mv88e6352_port_get_cmode,
4514 .port_setup_message_port = mv88e6xxx_setup_message_port,
4515 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4516 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4517 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4518 .stats_get_strings = mv88e6095_stats_get_strings,
4519 .stats_get_stats = mv88e6095_stats_get_stats,
4520 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4521 .set_egress_port = mv88e6095_g1_set_egress_port,
4522 .watchdog_ops = &mv88e6097_watchdog_ops,
4523 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4524 .pot_clear = mv88e6xxx_g2_pot_clear,
4525 .reset = mv88e6352_g1_reset,
4526 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4527 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4528 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4529 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4530 .stu_getnext = mv88e6352_g1_stu_getnext,
4531 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4532 .phylink_get_caps = mv88e6351_phylink_get_caps,
4533 };
4534
4535 static const struct mv88e6xxx_ops mv88e6176_ops = {
4536 /* MV88E6XXX_FAMILY_6352 */
4537 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4538 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4539 .irl_init_all = mv88e6352_g2_irl_init_all,
4540 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4541 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4542 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4543 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4544 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4545 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4546 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4547 .port_set_link = mv88e6xxx_port_set_link,
4548 .port_sync_link = mv88e6xxx_port_sync_link,
4549 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4550 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
4551 .port_tag_remap = mv88e6095_port_tag_remap,
4552 .port_set_policy = mv88e6352_port_set_policy,
4553 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4554 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4555 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4556 .port_set_ether_type = mv88e6351_port_set_ether_type,
4557 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4558 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4559 .port_pause_limit = mv88e6097_port_pause_limit,
4560 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4561 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4562 .port_get_cmode = mv88e6352_port_get_cmode,
4563 .port_setup_message_port = mv88e6xxx_setup_message_port,
4564 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4565 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4566 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4567 .stats_get_strings = mv88e6095_stats_get_strings,
4568 .stats_get_stats = mv88e6095_stats_get_stats,
4569 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4570 .set_egress_port = mv88e6095_g1_set_egress_port,
4571 .watchdog_ops = &mv88e6097_watchdog_ops,
4572 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4573 .pot_clear = mv88e6xxx_g2_pot_clear,
4574 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
4575 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
4576 .reset = mv88e6352_g1_reset,
4577 .rmu_disable = mv88e6352_g1_rmu_disable,
4578 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4579 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4580 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4581 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4582 .stu_getnext = mv88e6352_g1_stu_getnext,
4583 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4584 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
4585 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
4586 .serdes_get_regs = mv88e6352_serdes_get_regs,
4587 .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude,
4588 .gpio_ops = &mv88e6352_gpio_ops,
4589 .phylink_get_caps = mv88e6352_phylink_get_caps,
4590 .pcs_ops = &mv88e6352_pcs_ops,
4591 };
4592
4593 static const struct mv88e6xxx_ops mv88e6185_ops = {
4594 /* MV88E6XXX_FAMILY_6185 */
4595 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4596 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4597 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
4598 .phy_read = mv88e6185_phy_ppu_read,
4599 .phy_write = mv88e6185_phy_ppu_write,
4600 .port_set_link = mv88e6xxx_port_set_link,
4601 .port_sync_link = mv88e6185_port_sync_link,
4602 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4603 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
4604 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown,
4605 .port_set_mcast_flood = mv88e6185_port_set_default_forward,
4606 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
4607 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
4608 .port_set_pause = mv88e6185_port_set_pause,
4609 .port_get_cmode = mv88e6185_port_get_cmode,
4610 .port_setup_message_port = mv88e6xxx_setup_message_port,
4611 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4612 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4613 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4614 .stats_get_strings = mv88e6095_stats_get_strings,
4615 .stats_get_stats = mv88e6095_stats_get_stats,
4616 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4617 .set_egress_port = mv88e6095_g1_set_egress_port,
4618 .watchdog_ops = &mv88e6097_watchdog_ops,
4619 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
4620 .set_cascade_port = mv88e6185_g1_set_cascade_port,
4621 .ppu_enable = mv88e6185_g1_ppu_enable,
4622 .ppu_disable = mv88e6185_g1_ppu_disable,
4623 .reset = mv88e6185_g1_reset,
4624 .vtu_getnext = mv88e6185_g1_vtu_getnext,
4625 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
4626 .phylink_get_caps = mv88e6185_phylink_get_caps,
4627 .pcs_ops = &mv88e6185_pcs_ops,
4628 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
4629 };
4630
4631 static const struct mv88e6xxx_ops mv88e6190_ops = {
4632 /* MV88E6XXX_FAMILY_6390 */
4633 .setup_errata = mv88e6390_setup_errata,
4634 .irl_init_all = mv88e6390_g2_irl_init_all,
4635 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4636 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4637 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4638 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4639 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4640 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4641 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4642 .port_set_link = mv88e6xxx_port_set_link,
4643 .port_sync_link = mv88e6xxx_port_sync_link,
4644 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4645 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
4646 .port_max_speed_mode = mv88e6390_port_max_speed_mode,
4647 .port_tag_remap = mv88e6390_port_tag_remap,
4648 .port_set_policy = mv88e6352_port_set_policy,
4649 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4650 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4651 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4652 .port_set_ether_type = mv88e6351_port_set_ether_type,
4653 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4654 .port_pause_limit = mv88e6390_port_pause_limit,
4655 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4656 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4657 .port_get_cmode = mv88e6352_port_get_cmode,
4658 .port_set_cmode = mv88e6390_port_set_cmode,
4659 .port_setup_message_port = mv88e6xxx_setup_message_port,
4660 .stats_snapshot = mv88e6390_g1_stats_snapshot,
4661 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4662 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4663 .stats_get_strings = mv88e6320_stats_get_strings,
4664 .stats_get_stats = mv88e6390_stats_get_stats,
4665 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4666 .set_egress_port = mv88e6390_g1_set_egress_port,
4667 .watchdog_ops = &mv88e6390_watchdog_ops,
4668 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4669 .pot_clear = mv88e6xxx_g2_pot_clear,
4670 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
4671 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
4672 .reset = mv88e6352_g1_reset,
4673 .rmu_disable = mv88e6390_g1_rmu_disable,
4674 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4675 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4676 .vtu_getnext = mv88e6390_g1_vtu_getnext,
4677 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4678 .stu_getnext = mv88e6390_g1_stu_getnext,
4679 .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
4680 .serdes_get_lane = mv88e6390_serdes_get_lane,
4681 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4682 .serdes_get_strings = mv88e6390_serdes_get_strings,
4683 .serdes_get_stats = mv88e6390_serdes_get_stats,
4684 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4685 .serdes_get_regs = mv88e6390_serdes_get_regs,
4686 .gpio_ops = &mv88e6352_gpio_ops,
4687 .phylink_get_caps = mv88e6390_phylink_get_caps,
4688 .pcs_ops = &mv88e6390_pcs_ops,
4689 };
4690
4691 static const struct mv88e6xxx_ops mv88e6190x_ops = {
4692 /* MV88E6XXX_FAMILY_6390 */
4693 .setup_errata = mv88e6390_setup_errata,
4694 .irl_init_all = mv88e6390_g2_irl_init_all,
4695 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4696 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4697 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4698 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4699 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4700 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4701 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4702 .port_set_link = mv88e6xxx_port_set_link,
4703 .port_sync_link = mv88e6xxx_port_sync_link,
4704 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4705 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex,
4706 .port_max_speed_mode = mv88e6390x_port_max_speed_mode,
4707 .port_tag_remap = mv88e6390_port_tag_remap,
4708 .port_set_policy = mv88e6352_port_set_policy,
4709 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4710 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4711 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4712 .port_set_ether_type = mv88e6351_port_set_ether_type,
4713 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4714 .port_pause_limit = mv88e6390_port_pause_limit,
4715 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4716 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4717 .port_get_cmode = mv88e6352_port_get_cmode,
4718 .port_set_cmode = mv88e6390x_port_set_cmode,
4719 .port_setup_message_port = mv88e6xxx_setup_message_port,
4720 .stats_snapshot = mv88e6390_g1_stats_snapshot,
4721 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4722 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4723 .stats_get_strings = mv88e6320_stats_get_strings,
4724 .stats_get_stats = mv88e6390_stats_get_stats,
4725 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4726 .set_egress_port = mv88e6390_g1_set_egress_port,
4727 .watchdog_ops = &mv88e6390_watchdog_ops,
4728 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4729 .pot_clear = mv88e6xxx_g2_pot_clear,
4730 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
4731 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
4732 .reset = mv88e6352_g1_reset,
4733 .rmu_disable = mv88e6390_g1_rmu_disable,
4734 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4735 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4736 .vtu_getnext = mv88e6390_g1_vtu_getnext,
4737 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4738 .stu_getnext = mv88e6390_g1_stu_getnext,
4739 .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
4740 .serdes_get_lane = mv88e6390x_serdes_get_lane,
4741 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4742 .serdes_get_strings = mv88e6390_serdes_get_strings,
4743 .serdes_get_stats = mv88e6390_serdes_get_stats,
4744 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4745 .serdes_get_regs = mv88e6390_serdes_get_regs,
4746 .gpio_ops = &mv88e6352_gpio_ops,
4747 .phylink_get_caps = mv88e6390x_phylink_get_caps,
4748 .pcs_ops = &mv88e6390_pcs_ops,
4749 };
4750
4751 static const struct mv88e6xxx_ops mv88e6191_ops = {
4752 /* MV88E6XXX_FAMILY_6390 */
4753 .setup_errata = mv88e6390_setup_errata,
4754 .irl_init_all = mv88e6390_g2_irl_init_all,
4755 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4756 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4757 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4758 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4759 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4760 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4761 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4762 .port_set_link = mv88e6xxx_port_set_link,
4763 .port_sync_link = mv88e6xxx_port_sync_link,
4764 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4765 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
4766 .port_max_speed_mode = mv88e6390_port_max_speed_mode,
4767 .port_tag_remap = mv88e6390_port_tag_remap,
4768 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4769 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4770 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4771 .port_set_ether_type = mv88e6351_port_set_ether_type,
4772 .port_pause_limit = mv88e6390_port_pause_limit,
4773 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4774 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4775 .port_get_cmode = mv88e6352_port_get_cmode,
4776 .port_set_cmode = mv88e6390_port_set_cmode,
4777 .port_setup_message_port = mv88e6xxx_setup_message_port,
4778 .stats_snapshot = mv88e6390_g1_stats_snapshot,
4779 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4780 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4781 .stats_get_strings = mv88e6320_stats_get_strings,
4782 .stats_get_stats = mv88e6390_stats_get_stats,
4783 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4784 .set_egress_port = mv88e6390_g1_set_egress_port,
4785 .watchdog_ops = &mv88e6390_watchdog_ops,
4786 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4787 .pot_clear = mv88e6xxx_g2_pot_clear,
4788 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
4789 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
4790 .reset = mv88e6352_g1_reset,
4791 .rmu_disable = mv88e6390_g1_rmu_disable,
4792 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4793 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4794 .vtu_getnext = mv88e6390_g1_vtu_getnext,
4795 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4796 .stu_getnext = mv88e6390_g1_stu_getnext,
4797 .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
4798 .serdes_get_lane = mv88e6390_serdes_get_lane,
4799 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4800 .serdes_get_strings = mv88e6390_serdes_get_strings,
4801 .serdes_get_stats = mv88e6390_serdes_get_stats,
4802 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4803 .serdes_get_regs = mv88e6390_serdes_get_regs,
4804 .avb_ops = &mv88e6390_avb_ops,
4805 .ptp_ops = &mv88e6352_ptp_ops,
4806 .phylink_get_caps = mv88e6390_phylink_get_caps,
4807 .pcs_ops = &mv88e6390_pcs_ops,
4808 };
4809
4810 static const struct mv88e6xxx_ops mv88e6240_ops = {
4811 /* MV88E6XXX_FAMILY_6352 */
4812 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4813 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4814 .irl_init_all = mv88e6352_g2_irl_init_all,
4815 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4816 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4817 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4818 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4819 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4820 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4821 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4822 .port_set_link = mv88e6xxx_port_set_link,
4823 .port_sync_link = mv88e6xxx_port_sync_link,
4824 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4825 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
4826 .port_tag_remap = mv88e6095_port_tag_remap,
4827 .port_set_policy = mv88e6352_port_set_policy,
4828 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4829 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4830 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4831 .port_set_ether_type = mv88e6351_port_set_ether_type,
4832 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4833 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4834 .port_pause_limit = mv88e6097_port_pause_limit,
4835 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4836 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4837 .port_get_cmode = mv88e6352_port_get_cmode,
4838 .port_setup_message_port = mv88e6xxx_setup_message_port,
4839 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4840 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4841 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4842 .stats_get_strings = mv88e6095_stats_get_strings,
4843 .stats_get_stats = mv88e6095_stats_get_stats,
4844 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4845 .set_egress_port = mv88e6095_g1_set_egress_port,
4846 .watchdog_ops = &mv88e6097_watchdog_ops,
4847 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4848 .pot_clear = mv88e6xxx_g2_pot_clear,
4849 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
4850 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
4851 .reset = mv88e6352_g1_reset,
4852 .rmu_disable = mv88e6352_g1_rmu_disable,
4853 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4854 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4855 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4856 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4857 .stu_getnext = mv88e6352_g1_stu_getnext,
4858 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4859 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
4860 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
4861 .serdes_get_regs = mv88e6352_serdes_get_regs,
4862 .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude,
4863 .gpio_ops = &mv88e6352_gpio_ops,
4864 .avb_ops = &mv88e6352_avb_ops,
4865 .ptp_ops = &mv88e6352_ptp_ops,
4866 .phylink_get_caps = mv88e6352_phylink_get_caps,
4867 .pcs_ops = &mv88e6352_pcs_ops,
4868 };
4869
4870 static const struct mv88e6xxx_ops mv88e6250_ops = {
4871 /* MV88E6XXX_FAMILY_6250 */
4872 .ieee_pri_map = mv88e6250_g1_ieee_pri_map,
4873 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4874 .irl_init_all = mv88e6352_g2_irl_init_all,
4875 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4876 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4877 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4878 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4879 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4880 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4881 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4882 .port_set_link = mv88e6xxx_port_set_link,
4883 .port_sync_link = mv88e6xxx_port_sync_link,
4884 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4885 .port_set_speed_duplex = mv88e6250_port_set_speed_duplex,
4886 .port_tag_remap = mv88e6095_port_tag_remap,
4887 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4888 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4889 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4890 .port_set_ether_type = mv88e6351_port_set_ether_type,
4891 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4892 .port_pause_limit = mv88e6097_port_pause_limit,
4893 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4894 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4895 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4896 .stats_get_sset_count = mv88e6250_stats_get_sset_count,
4897 .stats_get_strings = mv88e6250_stats_get_strings,
4898 .stats_get_stats = mv88e6250_stats_get_stats,
4899 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4900 .set_egress_port = mv88e6095_g1_set_egress_port,
4901 .watchdog_ops = &mv88e6250_watchdog_ops,
4902 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4903 .pot_clear = mv88e6xxx_g2_pot_clear,
4904 .hardware_reset_pre = mv88e6250_g1_wait_eeprom_done_prereset,
4905 .hardware_reset_post = mv88e6xxx_g1_wait_eeprom_done,
4906 .reset = mv88e6250_g1_reset,
4907 .vtu_getnext = mv88e6185_g1_vtu_getnext,
4908 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
4909 .avb_ops = &mv88e6352_avb_ops,
4910 .ptp_ops = &mv88e6250_ptp_ops,
4911 .phylink_get_caps = mv88e6250_phylink_get_caps,
4912 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
4913 };
4914
4915 static const struct mv88e6xxx_ops mv88e6290_ops = {
4916 /* MV88E6XXX_FAMILY_6390 */
4917 .setup_errata = mv88e6390_setup_errata,
4918 .irl_init_all = mv88e6390_g2_irl_init_all,
4919 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4920 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4921 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4922 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4923 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4924 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4925 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4926 .port_set_link = mv88e6xxx_port_set_link,
4927 .port_sync_link = mv88e6xxx_port_sync_link,
4928 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4929 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
4930 .port_max_speed_mode = mv88e6390_port_max_speed_mode,
4931 .port_tag_remap = mv88e6390_port_tag_remap,
4932 .port_set_policy = mv88e6352_port_set_policy,
4933 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4934 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4935 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4936 .port_set_ether_type = mv88e6351_port_set_ether_type,
4937 .port_pause_limit = mv88e6390_port_pause_limit,
4938 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4939 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4940 .port_get_cmode = mv88e6352_port_get_cmode,
4941 .port_set_cmode = mv88e6390_port_set_cmode,
4942 .port_setup_message_port = mv88e6xxx_setup_message_port,
4943 .stats_snapshot = mv88e6390_g1_stats_snapshot,
4944 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4945 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4946 .stats_get_strings = mv88e6320_stats_get_strings,
4947 .stats_get_stats = mv88e6390_stats_get_stats,
4948 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4949 .set_egress_port = mv88e6390_g1_set_egress_port,
4950 .watchdog_ops = &mv88e6390_watchdog_ops,
4951 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4952 .pot_clear = mv88e6xxx_g2_pot_clear,
4953 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
4954 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
4955 .reset = mv88e6352_g1_reset,
4956 .rmu_disable = mv88e6390_g1_rmu_disable,
4957 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4958 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4959 .vtu_getnext = mv88e6390_g1_vtu_getnext,
4960 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4961 .stu_getnext = mv88e6390_g1_stu_getnext,
4962 .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
4963 .serdes_get_lane = mv88e6390_serdes_get_lane,
4964 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4965 .serdes_get_strings = mv88e6390_serdes_get_strings,
4966 .serdes_get_stats = mv88e6390_serdes_get_stats,
4967 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4968 .serdes_get_regs = mv88e6390_serdes_get_regs,
4969 .gpio_ops = &mv88e6352_gpio_ops,
4970 .avb_ops = &mv88e6390_avb_ops,
4971 .ptp_ops = &mv88e6390_ptp_ops,
4972 .phylink_get_caps = mv88e6390_phylink_get_caps,
4973 .pcs_ops = &mv88e6390_pcs_ops,
4974 };
4975
4976 static const struct mv88e6xxx_ops mv88e6320_ops = {
4977 /* MV88E6XXX_FAMILY_6320 */
4978 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4979 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4980 .irl_init_all = mv88e6352_g2_irl_init_all,
4981 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4982 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4983 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4984 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4985 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4986 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4987 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4988 .port_set_link = mv88e6xxx_port_set_link,
4989 .port_sync_link = mv88e6xxx_port_sync_link,
4990 .port_set_rgmii_delay = mv88e6320_port_set_rgmii_delay,
4991 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4992 .port_tag_remap = mv88e6095_port_tag_remap,
4993 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4994 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4995 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4996 .port_set_ether_type = mv88e6351_port_set_ether_type,
4997 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4998 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4999 .port_pause_limit = mv88e6097_port_pause_limit,
5000 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5001 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5002 .port_get_cmode = mv88e6352_port_get_cmode,
5003 .port_setup_message_port = mv88e6xxx_setup_message_port,
5004 .stats_snapshot = mv88e6320_g1_stats_snapshot,
5005 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
5006 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
5007 .stats_get_strings = mv88e6320_stats_get_strings,
5008 .stats_get_stats = mv88e6320_stats_get_stats,
5009 .set_cpu_port = mv88e6095_g1_set_cpu_port,
5010 .set_egress_port = mv88e6095_g1_set_egress_port,
5011 .watchdog_ops = &mv88e6390_watchdog_ops,
5012 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
5013 .pot_clear = mv88e6xxx_g2_pot_clear,
5014 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
5015 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
5016 .reset = mv88e6352_g1_reset,
5017 .vtu_getnext = mv88e6185_g1_vtu_getnext,
5018 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
5019 .gpio_ops = &mv88e6352_gpio_ops,
5020 .avb_ops = &mv88e6352_avb_ops,
5021 .ptp_ops = &mv88e6352_ptp_ops,
5022 .phylink_get_caps = mv88e632x_phylink_get_caps,
5023 };
5024
5025 static const struct mv88e6xxx_ops mv88e6321_ops = {
5026 /* MV88E6XXX_FAMILY_6320 */
5027 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
5028 .ip_pri_map = mv88e6085_g1_ip_pri_map,
5029 .irl_init_all = mv88e6352_g2_irl_init_all,
5030 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
5031 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
5032 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5033 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5034 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5035 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5036 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5037 .port_set_link = mv88e6xxx_port_set_link,
5038 .port_sync_link = mv88e6xxx_port_sync_link,
5039 .port_set_rgmii_delay = mv88e6320_port_set_rgmii_delay,
5040 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
5041 .port_tag_remap = mv88e6095_port_tag_remap,
5042 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5043 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5044 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5045 .port_set_ether_type = mv88e6351_port_set_ether_type,
5046 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5047 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5048 .port_pause_limit = mv88e6097_port_pause_limit,
5049 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5050 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5051 .port_get_cmode = mv88e6352_port_get_cmode,
5052 .port_setup_message_port = mv88e6xxx_setup_message_port,
5053 .stats_snapshot = mv88e6320_g1_stats_snapshot,
5054 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
5055 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
5056 .stats_get_strings = mv88e6320_stats_get_strings,
5057 .stats_get_stats = mv88e6320_stats_get_stats,
5058 .set_cpu_port = mv88e6095_g1_set_cpu_port,
5059 .set_egress_port = mv88e6095_g1_set_egress_port,
5060 .watchdog_ops = &mv88e6390_watchdog_ops,
5061 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
5062 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
5063 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
5064 .reset = mv88e6352_g1_reset,
5065 .vtu_getnext = mv88e6185_g1_vtu_getnext,
5066 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
5067 .gpio_ops = &mv88e6352_gpio_ops,
5068 .avb_ops = &mv88e6352_avb_ops,
5069 .ptp_ops = &mv88e6352_ptp_ops,
5070 .phylink_get_caps = mv88e632x_phylink_get_caps,
5071 };
5072
5073 static const struct mv88e6xxx_ops mv88e6341_ops = {
5074 /* MV88E6XXX_FAMILY_6341 */
5075 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
5076 .ip_pri_map = mv88e6085_g1_ip_pri_map,
5077 .irl_init_all = mv88e6352_g2_irl_init_all,
5078 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
5079 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
5080 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5081 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5082 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5083 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5084 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5085 .port_set_link = mv88e6xxx_port_set_link,
5086 .port_sync_link = mv88e6xxx_port_sync_link,
5087 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
5088 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex,
5089 .port_max_speed_mode = mv88e6341_port_max_speed_mode,
5090 .port_tag_remap = mv88e6095_port_tag_remap,
5091 .port_set_policy = mv88e6352_port_set_policy,
5092 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5093 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5094 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5095 .port_set_ether_type = mv88e6351_port_set_ether_type,
5096 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5097 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5098 .port_pause_limit = mv88e6097_port_pause_limit,
5099 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5100 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5101 .port_get_cmode = mv88e6352_port_get_cmode,
5102 .port_set_cmode = mv88e6341_port_set_cmode,
5103 .port_setup_message_port = mv88e6xxx_setup_message_port,
5104 .stats_snapshot = mv88e6390_g1_stats_snapshot,
5105 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
5106 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
5107 .stats_get_strings = mv88e6320_stats_get_strings,
5108 .stats_get_stats = mv88e6390_stats_get_stats,
5109 .set_cpu_port = mv88e6390_g1_set_cpu_port,
5110 .set_egress_port = mv88e6390_g1_set_egress_port,
5111 .watchdog_ops = &mv88e6390_watchdog_ops,
5112 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
5113 .pot_clear = mv88e6xxx_g2_pot_clear,
5114 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
5115 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
5116 .reset = mv88e6352_g1_reset,
5117 .rmu_disable = mv88e6390_g1_rmu_disable,
5118 .atu_get_hash = mv88e6165_g1_atu_get_hash,
5119 .atu_set_hash = mv88e6165_g1_atu_set_hash,
5120 .vtu_getnext = mv88e6352_g1_vtu_getnext,
5121 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
5122 .stu_getnext = mv88e6352_g1_stu_getnext,
5123 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
5124 .serdes_get_lane = mv88e6341_serdes_get_lane,
5125 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
5126 .gpio_ops = &mv88e6352_gpio_ops,
5127 .avb_ops = &mv88e6390_avb_ops,
5128 .ptp_ops = &mv88e6352_ptp_ops,
5129 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
5130 .serdes_get_strings = mv88e6390_serdes_get_strings,
5131 .serdes_get_stats = mv88e6390_serdes_get_stats,
5132 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
5133 .serdes_get_regs = mv88e6390_serdes_get_regs,
5134 .phylink_get_caps = mv88e6341_phylink_get_caps,
5135 .pcs_ops = &mv88e6390_pcs_ops,
5136 };
5137
5138 static const struct mv88e6xxx_ops mv88e6350_ops = {
5139 /* MV88E6XXX_FAMILY_6351 */
5140 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
5141 .ip_pri_map = mv88e6085_g1_ip_pri_map,
5142 .irl_init_all = mv88e6352_g2_irl_init_all,
5143 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5144 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5145 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5146 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5147 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5148 .port_set_link = mv88e6xxx_port_set_link,
5149 .port_sync_link = mv88e6xxx_port_sync_link,
5150 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
5151 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
5152 .port_tag_remap = mv88e6095_port_tag_remap,
5153 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5154 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5155 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5156 .port_set_ether_type = mv88e6351_port_set_ether_type,
5157 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5158 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5159 .port_pause_limit = mv88e6097_port_pause_limit,
5160 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5161 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5162 .port_get_cmode = mv88e6352_port_get_cmode,
5163 .port_setup_message_port = mv88e6xxx_setup_message_port,
5164 .stats_snapshot = mv88e6320_g1_stats_snapshot,
5165 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
5166 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
5167 .stats_get_strings = mv88e6095_stats_get_strings,
5168 .stats_get_stats = mv88e6095_stats_get_stats,
5169 .set_cpu_port = mv88e6095_g1_set_cpu_port,
5170 .set_egress_port = mv88e6095_g1_set_egress_port,
5171 .watchdog_ops = &mv88e6097_watchdog_ops,
5172 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
5173 .pot_clear = mv88e6xxx_g2_pot_clear,
5174 .reset = mv88e6352_g1_reset,
5175 .atu_get_hash = mv88e6165_g1_atu_get_hash,
5176 .atu_set_hash = mv88e6165_g1_atu_set_hash,
5177 .vtu_getnext = mv88e6352_g1_vtu_getnext,
5178 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
5179 .stu_getnext = mv88e6352_g1_stu_getnext,
5180 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
5181 .phylink_get_caps = mv88e6351_phylink_get_caps,
5182 };
5183
5184 static const struct mv88e6xxx_ops mv88e6351_ops = {
5185 /* MV88E6XXX_FAMILY_6351 */
5186 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
5187 .ip_pri_map = mv88e6085_g1_ip_pri_map,
5188 .irl_init_all = mv88e6352_g2_irl_init_all,
5189 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5190 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5191 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5192 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5193 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5194 .port_set_link = mv88e6xxx_port_set_link,
5195 .port_sync_link = mv88e6xxx_port_sync_link,
5196 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
5197 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
5198 .port_tag_remap = mv88e6095_port_tag_remap,
5199 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5200 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5201 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5202 .port_set_ether_type = mv88e6351_port_set_ether_type,
5203 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5204 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5205 .port_pause_limit = mv88e6097_port_pause_limit,
5206 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5207 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5208 .port_get_cmode = mv88e6352_port_get_cmode,
5209 .port_setup_message_port = mv88e6xxx_setup_message_port,
5210 .stats_snapshot = mv88e6320_g1_stats_snapshot,
5211 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
5212 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
5213 .stats_get_strings = mv88e6095_stats_get_strings,
5214 .stats_get_stats = mv88e6095_stats_get_stats,
5215 .set_cpu_port = mv88e6095_g1_set_cpu_port,
5216 .set_egress_port = mv88e6095_g1_set_egress_port,
5217 .watchdog_ops = &mv88e6097_watchdog_ops,
5218 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
5219 .pot_clear = mv88e6xxx_g2_pot_clear,
5220 .reset = mv88e6352_g1_reset,
5221 .atu_get_hash = mv88e6165_g1_atu_get_hash,
5222 .atu_set_hash = mv88e6165_g1_atu_set_hash,
5223 .vtu_getnext = mv88e6352_g1_vtu_getnext,
5224 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
5225 .stu_getnext = mv88e6352_g1_stu_getnext,
5226 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
5227 .avb_ops = &mv88e6352_avb_ops,
5228 .ptp_ops = &mv88e6352_ptp_ops,
5229 .phylink_get_caps = mv88e6351_phylink_get_caps,
5230 };
5231
5232 static const struct mv88e6xxx_ops mv88e6352_ops = {
5233 /* MV88E6XXX_FAMILY_6352 */
5234 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
5235 .ip_pri_map = mv88e6085_g1_ip_pri_map,
5236 .irl_init_all = mv88e6352_g2_irl_init_all,
5237 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
5238 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
5239 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5240 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5241 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5242 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5243 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5244 .port_set_link = mv88e6xxx_port_set_link,
5245 .port_sync_link = mv88e6xxx_port_sync_link,
5246 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
5247 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
5248 .port_tag_remap = mv88e6095_port_tag_remap,
5249 .port_set_policy = mv88e6352_port_set_policy,
5250 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5251 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5252 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5253 .port_set_ether_type = mv88e6351_port_set_ether_type,
5254 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5255 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5256 .port_pause_limit = mv88e6097_port_pause_limit,
5257 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5258 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5259 .port_get_cmode = mv88e6352_port_get_cmode,
5260 .port_setup_message_port = mv88e6xxx_setup_message_port,
5261 .stats_snapshot = mv88e6320_g1_stats_snapshot,
5262 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
5263 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
5264 .stats_get_strings = mv88e6095_stats_get_strings,
5265 .stats_get_stats = mv88e6095_stats_get_stats,
5266 .set_cpu_port = mv88e6095_g1_set_cpu_port,
5267 .set_egress_port = mv88e6095_g1_set_egress_port,
5268 .watchdog_ops = &mv88e6097_watchdog_ops,
5269 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
5270 .pot_clear = mv88e6xxx_g2_pot_clear,
5271 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
5272 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
5273 .reset = mv88e6352_g1_reset,
5274 .rmu_disable = mv88e6352_g1_rmu_disable,
5275 .atu_get_hash = mv88e6165_g1_atu_get_hash,
5276 .atu_set_hash = mv88e6165_g1_atu_set_hash,
5277 .vtu_getnext = mv88e6352_g1_vtu_getnext,
5278 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
5279 .stu_getnext = mv88e6352_g1_stu_getnext,
5280 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
5281 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
5282 .gpio_ops = &mv88e6352_gpio_ops,
5283 .avb_ops = &mv88e6352_avb_ops,
5284 .ptp_ops = &mv88e6352_ptp_ops,
5285 .serdes_get_sset_count = mv88e6352_serdes_get_sset_count,
5286 .serdes_get_strings = mv88e6352_serdes_get_strings,
5287 .serdes_get_stats = mv88e6352_serdes_get_stats,
5288 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
5289 .serdes_get_regs = mv88e6352_serdes_get_regs,
5290 .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude,
5291 .phylink_get_caps = mv88e6352_phylink_get_caps,
5292 .pcs_ops = &mv88e6352_pcs_ops,
5293 };
5294
5295 static const struct mv88e6xxx_ops mv88e6390_ops = {
5296 /* MV88E6XXX_FAMILY_6390 */
5297 .setup_errata = mv88e6390_setup_errata,
5298 .irl_init_all = mv88e6390_g2_irl_init_all,
5299 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
5300 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
5301 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5302 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5303 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5304 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5305 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5306 .port_set_link = mv88e6xxx_port_set_link,
5307 .port_sync_link = mv88e6xxx_port_sync_link,
5308 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
5309 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
5310 .port_max_speed_mode = mv88e6390_port_max_speed_mode,
5311 .port_tag_remap = mv88e6390_port_tag_remap,
5312 .port_set_policy = mv88e6352_port_set_policy,
5313 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5314 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5315 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5316 .port_set_ether_type = mv88e6351_port_set_ether_type,
5317 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5318 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5319 .port_pause_limit = mv88e6390_port_pause_limit,
5320 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5321 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5322 .port_get_cmode = mv88e6352_port_get_cmode,
5323 .port_set_cmode = mv88e6390_port_set_cmode,
5324 .port_setup_message_port = mv88e6xxx_setup_message_port,
5325 .stats_snapshot = mv88e6390_g1_stats_snapshot,
5326 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
5327 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
5328 .stats_get_strings = mv88e6320_stats_get_strings,
5329 .stats_get_stats = mv88e6390_stats_get_stats,
5330 .set_cpu_port = mv88e6390_g1_set_cpu_port,
5331 .set_egress_port = mv88e6390_g1_set_egress_port,
5332 .watchdog_ops = &mv88e6390_watchdog_ops,
5333 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
5334 .pot_clear = mv88e6xxx_g2_pot_clear,
5335 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
5336 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
5337 .reset = mv88e6352_g1_reset,
5338 .rmu_disable = mv88e6390_g1_rmu_disable,
5339 .atu_get_hash = mv88e6165_g1_atu_get_hash,
5340 .atu_set_hash = mv88e6165_g1_atu_set_hash,
5341 .vtu_getnext = mv88e6390_g1_vtu_getnext,
5342 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
5343 .stu_getnext = mv88e6390_g1_stu_getnext,
5344 .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
5345 .serdes_get_lane = mv88e6390_serdes_get_lane,
5346 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
5347 .gpio_ops = &mv88e6352_gpio_ops,
5348 .avb_ops = &mv88e6390_avb_ops,
5349 .ptp_ops = &mv88e6390_ptp_ops,
5350 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
5351 .serdes_get_strings = mv88e6390_serdes_get_strings,
5352 .serdes_get_stats = mv88e6390_serdes_get_stats,
5353 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
5354 .serdes_get_regs = mv88e6390_serdes_get_regs,
5355 .phylink_get_caps = mv88e6390_phylink_get_caps,
5356 .pcs_ops = &mv88e6390_pcs_ops,
5357 };
5358
5359 static const struct mv88e6xxx_ops mv88e6390x_ops = {
5360 /* MV88E6XXX_FAMILY_6390 */
5361 .setup_errata = mv88e6390_setup_errata,
5362 .irl_init_all = mv88e6390_g2_irl_init_all,
5363 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
5364 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
5365 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5366 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5367 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5368 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5369 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5370 .port_set_link = mv88e6xxx_port_set_link,
5371 .port_sync_link = mv88e6xxx_port_sync_link,
5372 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
5373 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex,
5374 .port_max_speed_mode = mv88e6390x_port_max_speed_mode,
5375 .port_tag_remap = mv88e6390_port_tag_remap,
5376 .port_set_policy = mv88e6352_port_set_policy,
5377 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5378 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5379 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5380 .port_set_ether_type = mv88e6351_port_set_ether_type,
5381 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5382 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5383 .port_pause_limit = mv88e6390_port_pause_limit,
5384 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5385 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5386 .port_get_cmode = mv88e6352_port_get_cmode,
5387 .port_set_cmode = mv88e6390x_port_set_cmode,
5388 .port_setup_message_port = mv88e6xxx_setup_message_port,
5389 .stats_snapshot = mv88e6390_g1_stats_snapshot,
5390 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
5391 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
5392 .stats_get_strings = mv88e6320_stats_get_strings,
5393 .stats_get_stats = mv88e6390_stats_get_stats,
5394 .set_cpu_port = mv88e6390_g1_set_cpu_port,
5395 .set_egress_port = mv88e6390_g1_set_egress_port,
5396 .watchdog_ops = &mv88e6390_watchdog_ops,
5397 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
5398 .pot_clear = mv88e6xxx_g2_pot_clear,
5399 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
5400 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
5401 .reset = mv88e6352_g1_reset,
5402 .rmu_disable = mv88e6390_g1_rmu_disable,
5403 .atu_get_hash = mv88e6165_g1_atu_get_hash,
5404 .atu_set_hash = mv88e6165_g1_atu_set_hash,
5405 .vtu_getnext = mv88e6390_g1_vtu_getnext,
5406 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
5407 .stu_getnext = mv88e6390_g1_stu_getnext,
5408 .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
5409 .serdes_get_lane = mv88e6390x_serdes_get_lane,
5410 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
5411 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
5412 .serdes_get_strings = mv88e6390_serdes_get_strings,
5413 .serdes_get_stats = mv88e6390_serdes_get_stats,
5414 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
5415 .serdes_get_regs = mv88e6390_serdes_get_regs,
5416 .gpio_ops = &mv88e6352_gpio_ops,
5417 .avb_ops = &mv88e6390_avb_ops,
5418 .ptp_ops = &mv88e6390_ptp_ops,
5419 .phylink_get_caps = mv88e6390x_phylink_get_caps,
5420 .pcs_ops = &mv88e6390_pcs_ops,
5421 };
5422
5423 static const struct mv88e6xxx_ops mv88e6393x_ops = {
5424 /* MV88E6XXX_FAMILY_6393 */
5425 .irl_init_all = mv88e6390_g2_irl_init_all,
5426 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
5427 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
5428 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5429 .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5430 .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5431 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5432 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5433 .port_set_link = mv88e6xxx_port_set_link,
5434 .port_sync_link = mv88e6xxx_port_sync_link,
5435 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
5436 .port_set_speed_duplex = mv88e6393x_port_set_speed_duplex,
5437 .port_max_speed_mode = mv88e6393x_port_max_speed_mode,
5438 .port_tag_remap = mv88e6390_port_tag_remap,
5439 .port_set_policy = mv88e6393x_port_set_policy,
5440 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5441 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5442 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5443 .port_set_ether_type = mv88e6393x_port_set_ether_type,
5444 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5445 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5446 .port_pause_limit = mv88e6390_port_pause_limit,
5447 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5448 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5449 .port_get_cmode = mv88e6352_port_get_cmode,
5450 .port_set_cmode = mv88e6393x_port_set_cmode,
5451 .port_setup_message_port = mv88e6xxx_setup_message_port,
5452 .port_set_upstream_port = mv88e6393x_port_set_upstream_port,
5453 .stats_snapshot = mv88e6390_g1_stats_snapshot,
5454 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
5455 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
5456 .stats_get_strings = mv88e6320_stats_get_strings,
5457 .stats_get_stats = mv88e6390_stats_get_stats,
5458 /* .set_cpu_port is missing because this family does not support a global
5459 * CPU port, only per port CPU port which is set via
5460 * .port_set_upstream_port method.
5461 */
5462 .set_egress_port = mv88e6393x_set_egress_port,
5463 .watchdog_ops = &mv88e6393x_watchdog_ops,
5464 .mgmt_rsvd2cpu = mv88e6393x_port_mgmt_rsvd2cpu,
5465 .pot_clear = mv88e6xxx_g2_pot_clear,
5466 .hardware_reset_pre = mv88e6xxx_g2_eeprom_wait,
5467 .hardware_reset_post = mv88e6xxx_g2_eeprom_wait,
5468 .reset = mv88e6352_g1_reset,
5469 .rmu_disable = mv88e6390_g1_rmu_disable,
5470 .atu_get_hash = mv88e6165_g1_atu_get_hash,
5471 .atu_set_hash = mv88e6165_g1_atu_set_hash,
5472 .vtu_getnext = mv88e6390_g1_vtu_getnext,
5473 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
5474 .stu_getnext = mv88e6390_g1_stu_getnext,
5475 .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
5476 .serdes_get_lane = mv88e6393x_serdes_get_lane,
5477 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
5478 /* TODO: serdes stats */
5479 .gpio_ops = &mv88e6352_gpio_ops,
5480 .avb_ops = &mv88e6390_avb_ops,
5481 .ptp_ops = &mv88e6352_ptp_ops,
5482 .phylink_get_caps = mv88e6393x_phylink_get_caps,
5483 .pcs_ops = &mv88e6393x_pcs_ops,
5484 };
5485
5486 static const struct mv88e6xxx_info mv88e6xxx_table[] = {
5487 [MV88E6020] = {
5488 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6020,
5489 .family = MV88E6XXX_FAMILY_6250,
5490 .name = "Marvell 88E6020",
5491 .num_databases = 64,
5492 /* Ports 2-4 are not routed to pins
5493 * => usable ports 0, 1, 5, 6
5494 */
5495 .num_ports = 7,
5496 .num_internal_phys = 2,
5497 .invalid_port_mask = BIT(2) | BIT(3) | BIT(4),
5498 .max_vid = 4095,
5499 .port_base_addr = 0x8,
5500 .phy_base_addr = 0x0,
5501 .global1_addr = 0xf,
5502 .global2_addr = 0x7,
5503 .age_time_coeff = 15000,
5504 .g1_irqs = 9,
5505 .g2_irqs = 5,
5506 .atu_move_port_mask = 0xf,
5507 .dual_chip = true,
5508 .ops = &mv88e6250_ops,
5509 },
5510
5511 [MV88E6071] = {
5512 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6071,
5513 .family = MV88E6XXX_FAMILY_6250,
5514 .name = "Marvell 88E6071",
5515 .num_databases = 64,
5516 .num_ports = 7,
5517 .num_internal_phys = 5,
5518 .max_vid = 4095,
5519 .port_base_addr = 0x08,
5520 .phy_base_addr = 0x00,
5521 .global1_addr = 0x0f,
5522 .global2_addr = 0x07,
5523 .age_time_coeff = 15000,
5524 .g1_irqs = 9,
5525 .g2_irqs = 5,
5526 .atu_move_port_mask = 0xf,
5527 .dual_chip = true,
5528 .ops = &mv88e6250_ops,
5529 },
5530
5531 [MV88E6085] = {
5532 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085,
5533 .family = MV88E6XXX_FAMILY_6097,
5534 .name = "Marvell 88E6085",
5535 .num_databases = 4096,
5536 .num_macs = 8192,
5537 .num_ports = 10,
5538 .num_internal_phys = 5,
5539 .max_vid = 4095,
5540 .max_sid = 63,
5541 .port_base_addr = 0x10,
5542 .phy_base_addr = 0x0,
5543 .global1_addr = 0x1b,
5544 .global2_addr = 0x1c,
5545 .age_time_coeff = 15000,
5546 .g1_irqs = 8,
5547 .g2_irqs = 10,
5548 .atu_move_port_mask = 0xf,
5549 .pvt = true,
5550 .multi_chip = true,
5551 .ops = &mv88e6085_ops,
5552 },
5553
5554 [MV88E6095] = {
5555 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095,
5556 .family = MV88E6XXX_FAMILY_6095,
5557 .name = "Marvell 88E6095/88E6095F",
5558 .num_databases = 256,
5559 .num_macs = 8192,
5560 .num_ports = 11,
5561 .num_internal_phys = 0,
5562 .max_vid = 4095,
5563 .port_base_addr = 0x10,
5564 .phy_base_addr = 0x0,
5565 .global1_addr = 0x1b,
5566 .global2_addr = 0x1c,
5567 .age_time_coeff = 15000,
5568 .g1_irqs = 8,
5569 .atu_move_port_mask = 0xf,
5570 .multi_chip = true,
5571 .ops = &mv88e6095_ops,
5572 },
5573
5574 [MV88E6097] = {
5575 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097,
5576 .family = MV88E6XXX_FAMILY_6097,
5577 .name = "Marvell 88E6097/88E6097F",
5578 .num_databases = 4096,
5579 .num_macs = 8192,
5580 .num_ports = 11,
5581 .num_internal_phys = 8,
5582 .max_vid = 4095,
5583 .max_sid = 63,
5584 .port_base_addr = 0x10,
5585 .phy_base_addr = 0x0,
5586 .global1_addr = 0x1b,
5587 .global2_addr = 0x1c,
5588 .age_time_coeff = 15000,
5589 .g1_irqs = 8,
5590 .g2_irqs = 10,
5591 .atu_move_port_mask = 0xf,
5592 .pvt = true,
5593 .multi_chip = true,
5594 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5595 .ops = &mv88e6097_ops,
5596 },
5597
5598 [MV88E6123] = {
5599 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123,
5600 .family = MV88E6XXX_FAMILY_6165,
5601 .name = "Marvell 88E6123",
5602 .num_databases = 4096,
5603 .num_macs = 1024,
5604 .num_ports = 3,
5605 .num_internal_phys = 5,
5606 .max_vid = 4095,
5607 .max_sid = 63,
5608 .port_base_addr = 0x10,
5609 .phy_base_addr = 0x0,
5610 .global1_addr = 0x1b,
5611 .global2_addr = 0x1c,
5612 .age_time_coeff = 15000,
5613 .g1_irqs = 9,
5614 .g2_irqs = 10,
5615 .atu_move_port_mask = 0xf,
5616 .pvt = true,
5617 .multi_chip = true,
5618 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5619 .ops = &mv88e6123_ops,
5620 },
5621
5622 [MV88E6131] = {
5623 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131,
5624 .family = MV88E6XXX_FAMILY_6185,
5625 .name = "Marvell 88E6131",
5626 .num_databases = 256,
5627 .num_macs = 8192,
5628 .num_ports = 8,
5629 .num_internal_phys = 0,
5630 .max_vid = 4095,
5631 .port_base_addr = 0x10,
5632 .phy_base_addr = 0x0,
5633 .global1_addr = 0x1b,
5634 .global2_addr = 0x1c,
5635 .age_time_coeff = 15000,
5636 .g1_irqs = 9,
5637 .atu_move_port_mask = 0xf,
5638 .multi_chip = true,
5639 .ops = &mv88e6131_ops,
5640 },
5641
5642 [MV88E6141] = {
5643 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141,
5644 .family = MV88E6XXX_FAMILY_6341,
5645 .name = "Marvell 88E6141",
5646 .num_databases = 256,
5647 .num_macs = 2048,
5648 .num_ports = 6,
5649 .num_internal_phys = 5,
5650 .num_gpio = 11,
5651 .max_vid = 4095,
5652 .max_sid = 63,
5653 .port_base_addr = 0x10,
5654 .phy_base_addr = 0x10,
5655 .global1_addr = 0x1b,
5656 .global2_addr = 0x1c,
5657 .age_time_coeff = 3750,
5658 .atu_move_port_mask = 0x1f,
5659 .g1_irqs = 9,
5660 .g2_irqs = 10,
5661 .pvt = true,
5662 .multi_chip = true,
5663 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5664 .ops = &mv88e6141_ops,
5665 },
5666
5667 [MV88E6161] = {
5668 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161,
5669 .family = MV88E6XXX_FAMILY_6165,
5670 .name = "Marvell 88E6161",
5671 .num_databases = 4096,
5672 .num_macs = 1024,
5673 .num_ports = 6,
5674 .num_internal_phys = 5,
5675 .max_vid = 4095,
5676 .max_sid = 63,
5677 .port_base_addr = 0x10,
5678 .phy_base_addr = 0x0,
5679 .global1_addr = 0x1b,
5680 .global2_addr = 0x1c,
5681 .age_time_coeff = 15000,
5682 .g1_irqs = 9,
5683 .g2_irqs = 10,
5684 .atu_move_port_mask = 0xf,
5685 .pvt = true,
5686 .multi_chip = true,
5687 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5688 .ptp_support = true,
5689 .ops = &mv88e6161_ops,
5690 },
5691
5692 [MV88E6165] = {
5693 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165,
5694 .family = MV88E6XXX_FAMILY_6165,
5695 .name = "Marvell 88E6165",
5696 .num_databases = 4096,
5697 .num_macs = 8192,
5698 .num_ports = 6,
5699 .num_internal_phys = 0,
5700 .max_vid = 4095,
5701 .max_sid = 63,
5702 .port_base_addr = 0x10,
5703 .phy_base_addr = 0x0,
5704 .global1_addr = 0x1b,
5705 .global2_addr = 0x1c,
5706 .age_time_coeff = 15000,
5707 .g1_irqs = 9,
5708 .g2_irqs = 10,
5709 .atu_move_port_mask = 0xf,
5710 .pvt = true,
5711 .multi_chip = true,
5712 .ptp_support = true,
5713 .ops = &mv88e6165_ops,
5714 },
5715
5716 [MV88E6171] = {
5717 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171,
5718 .family = MV88E6XXX_FAMILY_6351,
5719 .name = "Marvell 88E6171",
5720 .num_databases = 4096,
5721 .num_macs = 8192,
5722 .num_ports = 7,
5723 .num_internal_phys = 5,
5724 .max_vid = 4095,
5725 .max_sid = 63,
5726 .port_base_addr = 0x10,
5727 .phy_base_addr = 0x0,
5728 .global1_addr = 0x1b,
5729 .global2_addr = 0x1c,
5730 .age_time_coeff = 15000,
5731 .g1_irqs = 9,
5732 .g2_irqs = 10,
5733 .atu_move_port_mask = 0xf,
5734 .pvt = true,
5735 .multi_chip = true,
5736 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5737 .ops = &mv88e6171_ops,
5738 },
5739
5740 [MV88E6172] = {
5741 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172,
5742 .family = MV88E6XXX_FAMILY_6352,
5743 .name = "Marvell 88E6172",
5744 .num_databases = 4096,
5745 .num_macs = 8192,
5746 .num_ports = 7,
5747 .num_internal_phys = 5,
5748 .num_gpio = 15,
5749 .max_vid = 4095,
5750 .max_sid = 63,
5751 .port_base_addr = 0x10,
5752 .phy_base_addr = 0x0,
5753 .global1_addr = 0x1b,
5754 .global2_addr = 0x1c,
5755 .age_time_coeff = 15000,
5756 .g1_irqs = 9,
5757 .g2_irqs = 10,
5758 .atu_move_port_mask = 0xf,
5759 .pvt = true,
5760 .multi_chip = true,
5761 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5762 .ops = &mv88e6172_ops,
5763 },
5764
5765 [MV88E6175] = {
5766 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175,
5767 .family = MV88E6XXX_FAMILY_6351,
5768 .name = "Marvell 88E6175",
5769 .num_databases = 4096,
5770 .num_macs = 8192,
5771 .num_ports = 7,
5772 .num_internal_phys = 5,
5773 .max_vid = 4095,
5774 .max_sid = 63,
5775 .port_base_addr = 0x10,
5776 .phy_base_addr = 0x0,
5777 .global1_addr = 0x1b,
5778 .global2_addr = 0x1c,
5779 .age_time_coeff = 15000,
5780 .g1_irqs = 9,
5781 .g2_irqs = 10,
5782 .atu_move_port_mask = 0xf,
5783 .pvt = true,
5784 .multi_chip = true,
5785 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5786 .ops = &mv88e6175_ops,
5787 },
5788
5789 [MV88E6176] = {
5790 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176,
5791 .family = MV88E6XXX_FAMILY_6352,
5792 .name = "Marvell 88E6176",
5793 .num_databases = 4096,
5794 .num_macs = 8192,
5795 .num_ports = 7,
5796 .num_internal_phys = 5,
5797 .num_gpio = 15,
5798 .max_vid = 4095,
5799 .max_sid = 63,
5800 .port_base_addr = 0x10,
5801 .phy_base_addr = 0x0,
5802 .global1_addr = 0x1b,
5803 .global2_addr = 0x1c,
5804 .age_time_coeff = 15000,
5805 .g1_irqs = 9,
5806 .g2_irqs = 10,
5807 .atu_move_port_mask = 0xf,
5808 .pvt = true,
5809 .multi_chip = true,
5810 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5811 .ops = &mv88e6176_ops,
5812 },
5813
5814 [MV88E6185] = {
5815 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185,
5816 .family = MV88E6XXX_FAMILY_6185,
5817 .name = "Marvell 88E6185",
5818 .num_databases = 256,
5819 .num_macs = 8192,
5820 .num_ports = 10,
5821 .num_internal_phys = 0,
5822 .max_vid = 4095,
5823 .port_base_addr = 0x10,
5824 .phy_base_addr = 0x0,
5825 .global1_addr = 0x1b,
5826 .global2_addr = 0x1c,
5827 .age_time_coeff = 15000,
5828 .g1_irqs = 8,
5829 .atu_move_port_mask = 0xf,
5830 .multi_chip = true,
5831 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5832 .ops = &mv88e6185_ops,
5833 },
5834
5835 [MV88E6190] = {
5836 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190,
5837 .family = MV88E6XXX_FAMILY_6390,
5838 .name = "Marvell 88E6190",
5839 .num_databases = 4096,
5840 .num_macs = 16384,
5841 .num_ports = 11, /* 10 + Z80 */
5842 .num_internal_phys = 9,
5843 .num_gpio = 16,
5844 .max_vid = 8191,
5845 .max_sid = 63,
5846 .port_base_addr = 0x0,
5847 .phy_base_addr = 0x0,
5848 .global1_addr = 0x1b,
5849 .global2_addr = 0x1c,
5850 .age_time_coeff = 3750,
5851 .g1_irqs = 9,
5852 .g2_irqs = 14,
5853 .pvt = true,
5854 .multi_chip = true,
5855 .atu_move_port_mask = 0x1f,
5856 .ops = &mv88e6190_ops,
5857 },
5858
5859 [MV88E6190X] = {
5860 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X,
5861 .family = MV88E6XXX_FAMILY_6390,
5862 .name = "Marvell 88E6190X",
5863 .num_databases = 4096,
5864 .num_macs = 16384,
5865 .num_ports = 11, /* 10 + Z80 */
5866 .num_internal_phys = 9,
5867 .num_gpio = 16,
5868 .max_vid = 8191,
5869 .max_sid = 63,
5870 .port_base_addr = 0x0,
5871 .phy_base_addr = 0x0,
5872 .global1_addr = 0x1b,
5873 .global2_addr = 0x1c,
5874 .age_time_coeff = 3750,
5875 .g1_irqs = 9,
5876 .g2_irqs = 14,
5877 .atu_move_port_mask = 0x1f,
5878 .pvt = true,
5879 .multi_chip = true,
5880 .ops = &mv88e6190x_ops,
5881 },
5882
5883 [MV88E6191] = {
5884 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191,
5885 .family = MV88E6XXX_FAMILY_6390,
5886 .name = "Marvell 88E6191",
5887 .num_databases = 4096,
5888 .num_macs = 16384,
5889 .num_ports = 11, /* 10 + Z80 */
5890 .num_internal_phys = 9,
5891 .max_vid = 8191,
5892 .max_sid = 63,
5893 .port_base_addr = 0x0,
5894 .phy_base_addr = 0x0,
5895 .global1_addr = 0x1b,
5896 .global2_addr = 0x1c,
5897 .age_time_coeff = 3750,
5898 .g1_irqs = 9,
5899 .g2_irqs = 14,
5900 .atu_move_port_mask = 0x1f,
5901 .pvt = true,
5902 .multi_chip = true,
5903 .ptp_support = true,
5904 .ops = &mv88e6191_ops,
5905 },
5906
5907 [MV88E6191X] = {
5908 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191X,
5909 .family = MV88E6XXX_FAMILY_6393,
5910 .name = "Marvell 88E6191X",
5911 .num_databases = 4096,
5912 .num_ports = 11, /* 10 + Z80 */
5913 .num_internal_phys = 8,
5914 .internal_phys_offset = 1,
5915 .max_vid = 8191,
5916 .max_sid = 63,
5917 .port_base_addr = 0x0,
5918 .phy_base_addr = 0x0,
5919 .global1_addr = 0x1b,
5920 .global2_addr = 0x1c,
5921 .age_time_coeff = 3750,
5922 .g1_irqs = 10,
5923 .g2_irqs = 14,
5924 .atu_move_port_mask = 0x1f,
5925 .pvt = true,
5926 .multi_chip = true,
5927 .ptp_support = true,
5928 .ops = &mv88e6393x_ops,
5929 },
5930
5931 [MV88E6193X] = {
5932 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6193X,
5933 .family = MV88E6XXX_FAMILY_6393,
5934 .name = "Marvell 88E6193X",
5935 .num_databases = 4096,
5936 .num_ports = 11, /* 10 + Z80 */
5937 .num_internal_phys = 8,
5938 .internal_phys_offset = 1,
5939 .max_vid = 8191,
5940 .max_sid = 63,
5941 .port_base_addr = 0x0,
5942 .phy_base_addr = 0x0,
5943 .global1_addr = 0x1b,
5944 .global2_addr = 0x1c,
5945 .age_time_coeff = 3750,
5946 .g1_irqs = 10,
5947 .g2_irqs = 14,
5948 .atu_move_port_mask = 0x1f,
5949 .pvt = true,
5950 .multi_chip = true,
5951 .ptp_support = true,
5952 .ops = &mv88e6393x_ops,
5953 },
5954
5955 [MV88E6220] = {
5956 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6220,
5957 .family = MV88E6XXX_FAMILY_6250,
5958 .name = "Marvell 88E6220",
5959 .num_databases = 64,
5960
5961 /* Ports 2-4 are not routed to pins
5962 * => usable ports 0, 1, 5, 6
5963 */
5964 .num_ports = 7,
5965 .num_internal_phys = 2,
5966 .invalid_port_mask = BIT(2) | BIT(3) | BIT(4),
5967 .max_vid = 4095,
5968 .port_base_addr = 0x08,
5969 .phy_base_addr = 0x00,
5970 .global1_addr = 0x0f,
5971 .global2_addr = 0x07,
5972 .age_time_coeff = 15000,
5973 .g1_irqs = 9,
5974 .g2_irqs = 10,
5975 .atu_move_port_mask = 0xf,
5976 .dual_chip = true,
5977 .ptp_support = true,
5978 .ops = &mv88e6250_ops,
5979 },
5980
5981 [MV88E6240] = {
5982 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240,
5983 .family = MV88E6XXX_FAMILY_6352,
5984 .name = "Marvell 88E6240",
5985 .num_databases = 4096,
5986 .num_macs = 8192,
5987 .num_ports = 7,
5988 .num_internal_phys = 5,
5989 .num_gpio = 15,
5990 .max_vid = 4095,
5991 .max_sid = 63,
5992 .port_base_addr = 0x10,
5993 .phy_base_addr = 0x0,
5994 .global1_addr = 0x1b,
5995 .global2_addr = 0x1c,
5996 .age_time_coeff = 15000,
5997 .g1_irqs = 9,
5998 .g2_irqs = 10,
5999 .atu_move_port_mask = 0xf,
6000 .pvt = true,
6001 .multi_chip = true,
6002 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6003 .ptp_support = true,
6004 .ops = &mv88e6240_ops,
6005 },
6006
6007 [MV88E6250] = {
6008 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6250,
6009 .family = MV88E6XXX_FAMILY_6250,
6010 .name = "Marvell 88E6250",
6011 .num_databases = 64,
6012 .num_ports = 7,
6013 .num_internal_phys = 5,
6014 .max_vid = 4095,
6015 .port_base_addr = 0x08,
6016 .phy_base_addr = 0x00,
6017 .global1_addr = 0x0f,
6018 .global2_addr = 0x07,
6019 .age_time_coeff = 15000,
6020 .g1_irqs = 9,
6021 .g2_irqs = 10,
6022 .atu_move_port_mask = 0xf,
6023 .dual_chip = true,
6024 .ptp_support = true,
6025 .ops = &mv88e6250_ops,
6026 },
6027
6028 [MV88E6290] = {
6029 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290,
6030 .family = MV88E6XXX_FAMILY_6390,
6031 .name = "Marvell 88E6290",
6032 .num_databases = 4096,
6033 .num_ports = 11, /* 10 + Z80 */
6034 .num_internal_phys = 9,
6035 .num_gpio = 16,
6036 .max_vid = 8191,
6037 .max_sid = 63,
6038 .port_base_addr = 0x0,
6039 .phy_base_addr = 0x0,
6040 .global1_addr = 0x1b,
6041 .global2_addr = 0x1c,
6042 .age_time_coeff = 3750,
6043 .g1_irqs = 9,
6044 .g2_irqs = 14,
6045 .atu_move_port_mask = 0x1f,
6046 .pvt = true,
6047 .multi_chip = true,
6048 .ptp_support = true,
6049 .ops = &mv88e6290_ops,
6050 },
6051
6052 [MV88E6320] = {
6053 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320,
6054 .family = MV88E6XXX_FAMILY_6320,
6055 .name = "Marvell 88E6320",
6056 .num_databases = 4096,
6057 .num_macs = 8192,
6058 .num_ports = 7,
6059 .num_internal_phys = 5,
6060 .num_gpio = 15,
6061 .max_vid = 4095,
6062 .port_base_addr = 0x10,
6063 .phy_base_addr = 0x0,
6064 .global1_addr = 0x1b,
6065 .global2_addr = 0x1c,
6066 .age_time_coeff = 15000,
6067 .g1_irqs = 8,
6068 .g2_irqs = 10,
6069 .atu_move_port_mask = 0xf,
6070 .pvt = true,
6071 .multi_chip = true,
6072 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6073 .ptp_support = true,
6074 .ops = &mv88e6320_ops,
6075 },
6076
6077 [MV88E6321] = {
6078 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321,
6079 .family = MV88E6XXX_FAMILY_6320,
6080 .name = "Marvell 88E6321",
6081 .num_databases = 4096,
6082 .num_macs = 8192,
6083 .num_ports = 7,
6084 .num_internal_phys = 5,
6085 .num_gpio = 15,
6086 .max_vid = 4095,
6087 .port_base_addr = 0x10,
6088 .phy_base_addr = 0x0,
6089 .global1_addr = 0x1b,
6090 .global2_addr = 0x1c,
6091 .age_time_coeff = 15000,
6092 .g1_irqs = 8,
6093 .g2_irqs = 10,
6094 .atu_move_port_mask = 0xf,
6095 .multi_chip = true,
6096 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6097 .ptp_support = true,
6098 .ops = &mv88e6321_ops,
6099 },
6100
6101 [MV88E6341] = {
6102 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341,
6103 .family = MV88E6XXX_FAMILY_6341,
6104 .name = "Marvell 88E6341",
6105 .num_databases = 256,
6106 .num_macs = 2048,
6107 .num_internal_phys = 5,
6108 .num_ports = 6,
6109 .num_gpio = 11,
6110 .max_vid = 4095,
6111 .max_sid = 63,
6112 .port_base_addr = 0x10,
6113 .phy_base_addr = 0x10,
6114 .global1_addr = 0x1b,
6115 .global2_addr = 0x1c,
6116 .age_time_coeff = 3750,
6117 .atu_move_port_mask = 0x1f,
6118 .g1_irqs = 9,
6119 .g2_irqs = 10,
6120 .pvt = true,
6121 .multi_chip = true,
6122 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6123 .ptp_support = true,
6124 .ops = &mv88e6341_ops,
6125 },
6126
6127 [MV88E6350] = {
6128 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350,
6129 .family = MV88E6XXX_FAMILY_6351,
6130 .name = "Marvell 88E6350",
6131 .num_databases = 4096,
6132 .num_macs = 8192,
6133 .num_ports = 7,
6134 .num_internal_phys = 5,
6135 .max_vid = 4095,
6136 .max_sid = 63,
6137 .port_base_addr = 0x10,
6138 .phy_base_addr = 0x0,
6139 .global1_addr = 0x1b,
6140 .global2_addr = 0x1c,
6141 .age_time_coeff = 15000,
6142 .g1_irqs = 9,
6143 .g2_irqs = 10,
6144 .atu_move_port_mask = 0xf,
6145 .pvt = true,
6146 .multi_chip = true,
6147 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6148 .ops = &mv88e6350_ops,
6149 },
6150
6151 [MV88E6351] = {
6152 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351,
6153 .family = MV88E6XXX_FAMILY_6351,
6154 .name = "Marvell 88E6351",
6155 .num_databases = 4096,
6156 .num_macs = 8192,
6157 .num_ports = 7,
6158 .num_internal_phys = 5,
6159 .max_vid = 4095,
6160 .max_sid = 63,
6161 .port_base_addr = 0x10,
6162 .phy_base_addr = 0x0,
6163 .global1_addr = 0x1b,
6164 .global2_addr = 0x1c,
6165 .age_time_coeff = 15000,
6166 .g1_irqs = 9,
6167 .g2_irqs = 10,
6168 .atu_move_port_mask = 0xf,
6169 .pvt = true,
6170 .multi_chip = true,
6171 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6172 .ops = &mv88e6351_ops,
6173 },
6174
6175 [MV88E6352] = {
6176 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352,
6177 .family = MV88E6XXX_FAMILY_6352,
6178 .name = "Marvell 88E6352",
6179 .num_databases = 4096,
6180 .num_macs = 8192,
6181 .num_ports = 7,
6182 .num_internal_phys = 5,
6183 .num_gpio = 15,
6184 .max_vid = 4095,
6185 .max_sid = 63,
6186 .port_base_addr = 0x10,
6187 .phy_base_addr = 0x0,
6188 .global1_addr = 0x1b,
6189 .global2_addr = 0x1c,
6190 .age_time_coeff = 15000,
6191 .g1_irqs = 9,
6192 .g2_irqs = 10,
6193 .atu_move_port_mask = 0xf,
6194 .pvt = true,
6195 .multi_chip = true,
6196 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6197 .ptp_support = true,
6198 .ops = &mv88e6352_ops,
6199 },
6200 [MV88E6361] = {
6201 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6361,
6202 .family = MV88E6XXX_FAMILY_6393,
6203 .name = "Marvell 88E6361",
6204 .num_databases = 4096,
6205 .num_macs = 16384,
6206 .num_ports = 11,
6207 /* Ports 1, 2 and 8 are not routed */
6208 .invalid_port_mask = BIT(1) | BIT(2) | BIT(8),
6209 .num_internal_phys = 5,
6210 .internal_phys_offset = 3,
6211 .max_vid = 4095,
6212 .max_sid = 63,
6213 .port_base_addr = 0x0,
6214 .phy_base_addr = 0x0,
6215 .global1_addr = 0x1b,
6216 .global2_addr = 0x1c,
6217 .age_time_coeff = 3750,
6218 .g1_irqs = 10,
6219 .g2_irqs = 14,
6220 .atu_move_port_mask = 0x1f,
6221 .pvt = true,
6222 .multi_chip = true,
6223 .ptp_support = true,
6224 .ops = &mv88e6393x_ops,
6225 },
6226 [MV88E6390] = {
6227 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390,
6228 .family = MV88E6XXX_FAMILY_6390,
6229 .name = "Marvell 88E6390",
6230 .num_databases = 4096,
6231 .num_macs = 16384,
6232 .num_ports = 11, /* 10 + Z80 */
6233 .num_internal_phys = 9,
6234 .num_gpio = 16,
6235 .max_vid = 8191,
6236 .max_sid = 63,
6237 .port_base_addr = 0x0,
6238 .phy_base_addr = 0x0,
6239 .global1_addr = 0x1b,
6240 .global2_addr = 0x1c,
6241 .age_time_coeff = 3750,
6242 .g1_irqs = 9,
6243 .g2_irqs = 14,
6244 .atu_move_port_mask = 0x1f,
6245 .pvt = true,
6246 .multi_chip = true,
6247 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED,
6248 .ptp_support = true,
6249 .ops = &mv88e6390_ops,
6250 },
6251 [MV88E6390X] = {
6252 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X,
6253 .family = MV88E6XXX_FAMILY_6390,
6254 .name = "Marvell 88E6390X",
6255 .num_databases = 4096,
6256 .num_macs = 16384,
6257 .num_ports = 11, /* 10 + Z80 */
6258 .num_internal_phys = 9,
6259 .num_gpio = 16,
6260 .max_vid = 8191,
6261 .max_sid = 63,
6262 .port_base_addr = 0x0,
6263 .phy_base_addr = 0x0,
6264 .global1_addr = 0x1b,
6265 .global2_addr = 0x1c,
6266 .age_time_coeff = 3750,
6267 .g1_irqs = 9,
6268 .g2_irqs = 14,
6269 .atu_move_port_mask = 0x1f,
6270 .pvt = true,
6271 .multi_chip = true,
6272 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED,
6273 .ptp_support = true,
6274 .ops = &mv88e6390x_ops,
6275 },
6276
6277 [MV88E6393X] = {
6278 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X,
6279 .family = MV88E6XXX_FAMILY_6393,
6280 .name = "Marvell 88E6393X",
6281 .num_databases = 4096,
6282 .num_ports = 11, /* 10 + Z80 */
6283 .num_internal_phys = 8,
6284 .internal_phys_offset = 1,
6285 .max_vid = 8191,
6286 .max_sid = 63,
6287 .port_base_addr = 0x0,
6288 .phy_base_addr = 0x0,
6289 .global1_addr = 0x1b,
6290 .global2_addr = 0x1c,
6291 .age_time_coeff = 3750,
6292 .g1_irqs = 10,
6293 .g2_irqs = 14,
6294 .atu_move_port_mask = 0x1f,
6295 .pvt = true,
6296 .multi_chip = true,
6297 .ptp_support = true,
6298 .ops = &mv88e6393x_ops,
6299 },
6300 };
6301
mv88e6xxx_lookup_info(unsigned int prod_num)6302 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
6303 {
6304 int i;
6305
6306 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
6307 if (mv88e6xxx_table[i].prod_num == prod_num)
6308 return &mv88e6xxx_table[i];
6309
6310 return NULL;
6311 }
6312
mv88e6xxx_detect(struct mv88e6xxx_chip * chip)6313 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
6314 {
6315 const struct mv88e6xxx_info *info;
6316 unsigned int prod_num, rev;
6317 u16 id;
6318 int err;
6319
6320 mv88e6xxx_reg_lock(chip);
6321 err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id);
6322 mv88e6xxx_reg_unlock(chip);
6323 if (err)
6324 return err;
6325
6326 prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK;
6327 rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK;
6328
6329 info = mv88e6xxx_lookup_info(prod_num);
6330 if (!info)
6331 return -ENODEV;
6332
6333 /* Update the compatible info with the probed one */
6334 chip->info = info;
6335
6336 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
6337 chip->info->prod_num, chip->info->name, rev);
6338
6339 return 0;
6340 }
6341
mv88e6xxx_single_chip_detect(struct mv88e6xxx_chip * chip,struct mdio_device * mdiodev)6342 static int mv88e6xxx_single_chip_detect(struct mv88e6xxx_chip *chip,
6343 struct mdio_device *mdiodev)
6344 {
6345 int err;
6346
6347 /* dual_chip takes precedence over single/multi-chip modes */
6348 if (chip->info->dual_chip)
6349 return -EINVAL;
6350
6351 /* If the mdio addr is 16 indicating the first port address of a switch
6352 * (e.g. mv88e6*41) in single chip addressing mode the device may be
6353 * configured in single chip addressing mode. Setup the smi access as
6354 * single chip addressing mode and attempt to detect the model of the
6355 * switch, if this fails the device is not configured in single chip
6356 * addressing mode.
6357 */
6358 if (mdiodev->addr != 16)
6359 return -EINVAL;
6360
6361 err = mv88e6xxx_smi_init(chip, mdiodev->bus, 0);
6362 if (err)
6363 return err;
6364
6365 return mv88e6xxx_detect(chip);
6366 }
6367
mv88e6xxx_alloc_chip(struct device * dev)6368 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
6369 {
6370 struct mv88e6xxx_chip *chip;
6371
6372 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
6373 if (!chip)
6374 return NULL;
6375
6376 chip->dev = dev;
6377
6378 mutex_init(&chip->reg_lock);
6379 INIT_LIST_HEAD(&chip->mdios);
6380 idr_init(&chip->policies);
6381 INIT_LIST_HEAD(&chip->msts);
6382
6383 return chip;
6384 }
6385
mv88e6xxx_get_tag_protocol(struct dsa_switch * ds,int port,enum dsa_tag_protocol m)6386 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds,
6387 int port,
6388 enum dsa_tag_protocol m)
6389 {
6390 struct mv88e6xxx_chip *chip = ds->priv;
6391
6392 return chip->tag_protocol;
6393 }
6394
mv88e6xxx_change_tag_protocol(struct dsa_switch * ds,enum dsa_tag_protocol proto)6395 static int mv88e6xxx_change_tag_protocol(struct dsa_switch *ds,
6396 enum dsa_tag_protocol proto)
6397 {
6398 struct mv88e6xxx_chip *chip = ds->priv;
6399 enum dsa_tag_protocol old_protocol;
6400 struct dsa_port *cpu_dp;
6401 int err;
6402
6403 switch (proto) {
6404 case DSA_TAG_PROTO_EDSA:
6405 switch (chip->info->edsa_support) {
6406 case MV88E6XXX_EDSA_UNSUPPORTED:
6407 return -EPROTONOSUPPORT;
6408 case MV88E6XXX_EDSA_UNDOCUMENTED:
6409 dev_warn(chip->dev, "Relying on undocumented EDSA tagging behavior\n");
6410 fallthrough;
6411 case MV88E6XXX_EDSA_SUPPORTED:
6412 break;
6413 }
6414 break;
6415 case DSA_TAG_PROTO_DSA:
6416 break;
6417 default:
6418 return -EPROTONOSUPPORT;
6419 }
6420
6421 old_protocol = chip->tag_protocol;
6422 chip->tag_protocol = proto;
6423
6424 mv88e6xxx_reg_lock(chip);
6425 dsa_switch_for_each_cpu_port(cpu_dp, ds) {
6426 err = mv88e6xxx_setup_port_mode(chip, cpu_dp->index);
6427 if (err) {
6428 mv88e6xxx_reg_unlock(chip);
6429 goto unwind;
6430 }
6431 }
6432 mv88e6xxx_reg_unlock(chip);
6433
6434 return 0;
6435
6436 unwind:
6437 chip->tag_protocol = old_protocol;
6438
6439 mv88e6xxx_reg_lock(chip);
6440 dsa_switch_for_each_cpu_port_continue_reverse(cpu_dp, ds)
6441 mv88e6xxx_setup_port_mode(chip, cpu_dp->index);
6442 mv88e6xxx_reg_unlock(chip);
6443
6444 return err;
6445 }
6446
mv88e6xxx_port_mdb_add(struct dsa_switch * ds,int port,const struct switchdev_obj_port_mdb * mdb,struct dsa_db db)6447 static int mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port,
6448 const struct switchdev_obj_port_mdb *mdb,
6449 struct dsa_db db)
6450 {
6451 struct mv88e6xxx_chip *chip = ds->priv;
6452 int err;
6453
6454 mv88e6xxx_reg_lock(chip);
6455 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
6456 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC);
6457 mv88e6xxx_reg_unlock(chip);
6458
6459 return err;
6460 }
6461
mv88e6xxx_port_mdb_del(struct dsa_switch * ds,int port,const struct switchdev_obj_port_mdb * mdb,struct dsa_db db)6462 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port,
6463 const struct switchdev_obj_port_mdb *mdb,
6464 struct dsa_db db)
6465 {
6466 struct mv88e6xxx_chip *chip = ds->priv;
6467 int err;
6468
6469 mv88e6xxx_reg_lock(chip);
6470 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 0);
6471 mv88e6xxx_reg_unlock(chip);
6472
6473 return err;
6474 }
6475
mv88e6xxx_port_mirror_add(struct dsa_switch * ds,int port,struct dsa_mall_mirror_tc_entry * mirror,bool ingress,struct netlink_ext_ack * extack)6476 static int mv88e6xxx_port_mirror_add(struct dsa_switch *ds, int port,
6477 struct dsa_mall_mirror_tc_entry *mirror,
6478 bool ingress,
6479 struct netlink_ext_ack *extack)
6480 {
6481 enum mv88e6xxx_egress_direction direction = ingress ?
6482 MV88E6XXX_EGRESS_DIR_INGRESS :
6483 MV88E6XXX_EGRESS_DIR_EGRESS;
6484 struct mv88e6xxx_chip *chip = ds->priv;
6485 bool other_mirrors = false;
6486 int i;
6487 int err;
6488
6489 mutex_lock(&chip->reg_lock);
6490 if ((ingress ? chip->ingress_dest_port : chip->egress_dest_port) !=
6491 mirror->to_local_port) {
6492 for (i = 0; i < mv88e6xxx_num_ports(chip); i++)
6493 other_mirrors |= ingress ?
6494 chip->ports[i].mirror_ingress :
6495 chip->ports[i].mirror_egress;
6496
6497 /* Can't change egress port when other mirror is active */
6498 if (other_mirrors) {
6499 err = -EBUSY;
6500 goto out;
6501 }
6502
6503 err = mv88e6xxx_set_egress_port(chip, direction,
6504 mirror->to_local_port);
6505 if (err)
6506 goto out;
6507 }
6508
6509 err = mv88e6xxx_port_set_mirror(chip, port, direction, true);
6510 out:
6511 mutex_unlock(&chip->reg_lock);
6512
6513 return err;
6514 }
6515
mv88e6xxx_port_mirror_del(struct dsa_switch * ds,int port,struct dsa_mall_mirror_tc_entry * mirror)6516 static void mv88e6xxx_port_mirror_del(struct dsa_switch *ds, int port,
6517 struct dsa_mall_mirror_tc_entry *mirror)
6518 {
6519 enum mv88e6xxx_egress_direction direction = mirror->ingress ?
6520 MV88E6XXX_EGRESS_DIR_INGRESS :
6521 MV88E6XXX_EGRESS_DIR_EGRESS;
6522 struct mv88e6xxx_chip *chip = ds->priv;
6523 bool other_mirrors = false;
6524 int i;
6525
6526 mutex_lock(&chip->reg_lock);
6527 if (mv88e6xxx_port_set_mirror(chip, port, direction, false))
6528 dev_err(ds->dev, "p%d: failed to disable mirroring\n", port);
6529
6530 for (i = 0; i < mv88e6xxx_num_ports(chip); i++)
6531 other_mirrors |= mirror->ingress ?
6532 chip->ports[i].mirror_ingress :
6533 chip->ports[i].mirror_egress;
6534
6535 /* Reset egress port when no other mirror is active */
6536 if (!other_mirrors) {
6537 if (mv88e6xxx_set_egress_port(chip, direction,
6538 dsa_upstream_port(ds, port)))
6539 dev_err(ds->dev, "failed to set egress port\n");
6540 }
6541
6542 mutex_unlock(&chip->reg_lock);
6543 }
6544
mv88e6xxx_port_pre_bridge_flags(struct dsa_switch * ds,int port,struct switchdev_brport_flags flags,struct netlink_ext_ack * extack)6545 static int mv88e6xxx_port_pre_bridge_flags(struct dsa_switch *ds, int port,
6546 struct switchdev_brport_flags flags,
6547 struct netlink_ext_ack *extack)
6548 {
6549 struct mv88e6xxx_chip *chip = ds->priv;
6550 const struct mv88e6xxx_ops *ops;
6551
6552 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD |
6553 BR_BCAST_FLOOD | BR_PORT_LOCKED | BR_PORT_MAB))
6554 return -EINVAL;
6555
6556 ops = chip->info->ops;
6557
6558 if ((flags.mask & BR_FLOOD) && !ops->port_set_ucast_flood)
6559 return -EINVAL;
6560
6561 if ((flags.mask & BR_MCAST_FLOOD) && !ops->port_set_mcast_flood)
6562 return -EINVAL;
6563
6564 return 0;
6565 }
6566
mv88e6xxx_port_bridge_flags(struct dsa_switch * ds,int port,struct switchdev_brport_flags flags,struct netlink_ext_ack * extack)6567 static int mv88e6xxx_port_bridge_flags(struct dsa_switch *ds, int port,
6568 struct switchdev_brport_flags flags,
6569 struct netlink_ext_ack *extack)
6570 {
6571 struct mv88e6xxx_chip *chip = ds->priv;
6572 int err = 0;
6573
6574 mv88e6xxx_reg_lock(chip);
6575
6576 if (flags.mask & BR_LEARNING) {
6577 bool learning = !!(flags.val & BR_LEARNING);
6578 u16 pav = learning ? (1 << port) : 0;
6579
6580 err = mv88e6xxx_port_set_assoc_vector(chip, port, pav);
6581 if (err)
6582 goto out;
6583 }
6584
6585 if (flags.mask & BR_FLOOD) {
6586 bool unicast = !!(flags.val & BR_FLOOD);
6587
6588 err = chip->info->ops->port_set_ucast_flood(chip, port,
6589 unicast);
6590 if (err)
6591 goto out;
6592 }
6593
6594 if (flags.mask & BR_MCAST_FLOOD) {
6595 bool multicast = !!(flags.val & BR_MCAST_FLOOD);
6596
6597 err = chip->info->ops->port_set_mcast_flood(chip, port,
6598 multicast);
6599 if (err)
6600 goto out;
6601 }
6602
6603 if (flags.mask & BR_BCAST_FLOOD) {
6604 bool broadcast = !!(flags.val & BR_BCAST_FLOOD);
6605
6606 err = mv88e6xxx_port_broadcast_sync(chip, port, broadcast);
6607 if (err)
6608 goto out;
6609 }
6610
6611 if (flags.mask & BR_PORT_MAB) {
6612 bool mab = !!(flags.val & BR_PORT_MAB);
6613
6614 mv88e6xxx_port_set_mab(chip, port, mab);
6615 }
6616
6617 if (flags.mask & BR_PORT_LOCKED) {
6618 bool locked = !!(flags.val & BR_PORT_LOCKED);
6619
6620 err = mv88e6xxx_port_set_lock(chip, port, locked);
6621 if (err)
6622 goto out;
6623 }
6624 out:
6625 mv88e6xxx_reg_unlock(chip);
6626
6627 return err;
6628 }
6629
mv88e6xxx_lag_can_offload(struct dsa_switch * ds,struct dsa_lag lag,struct netdev_lag_upper_info * info,struct netlink_ext_ack * extack)6630 static bool mv88e6xxx_lag_can_offload(struct dsa_switch *ds,
6631 struct dsa_lag lag,
6632 struct netdev_lag_upper_info *info,
6633 struct netlink_ext_ack *extack)
6634 {
6635 struct mv88e6xxx_chip *chip = ds->priv;
6636 struct dsa_port *dp;
6637 int members = 0;
6638
6639 if (!mv88e6xxx_has_lag(chip)) {
6640 NL_SET_ERR_MSG_MOD(extack, "Chip does not support LAG offload");
6641 return false;
6642 }
6643
6644 if (!lag.id)
6645 return false;
6646
6647 dsa_lag_foreach_port(dp, ds->dst, &lag)
6648 /* Includes the port joining the LAG */
6649 members++;
6650
6651 if (members > 8) {
6652 NL_SET_ERR_MSG_MOD(extack,
6653 "Cannot offload more than 8 LAG ports");
6654 return false;
6655 }
6656
6657 /* We could potentially relax this to include active
6658 * backup in the future.
6659 */
6660 if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH) {
6661 NL_SET_ERR_MSG_MOD(extack,
6662 "Can only offload LAG using hash TX type");
6663 return false;
6664 }
6665
6666 /* Ideally we would also validate that the hash type matches
6667 * the hardware. Alas, this is always set to unknown on team
6668 * interfaces.
6669 */
6670 return true;
6671 }
6672
mv88e6xxx_lag_sync_map(struct dsa_switch * ds,struct dsa_lag lag)6673 static int mv88e6xxx_lag_sync_map(struct dsa_switch *ds, struct dsa_lag lag)
6674 {
6675 struct mv88e6xxx_chip *chip = ds->priv;
6676 struct dsa_port *dp;
6677 u16 map = 0;
6678 int id;
6679
6680 /* DSA LAG IDs are one-based, hardware is zero-based */
6681 id = lag.id - 1;
6682
6683 /* Build the map of all ports to distribute flows destined for
6684 * this LAG. This can be either a local user port, or a DSA
6685 * port if the LAG port is on a remote chip.
6686 */
6687 dsa_lag_foreach_port(dp, ds->dst, &lag)
6688 map |= BIT(dsa_towards_port(ds, dp->ds->index, dp->index));
6689
6690 return mv88e6xxx_g2_trunk_mapping_write(chip, id, map);
6691 }
6692
6693 static const u8 mv88e6xxx_lag_mask_table[8][8] = {
6694 /* Row number corresponds to the number of active members in a
6695 * LAG. Each column states which of the eight hash buckets are
6696 * mapped to the column:th port in the LAG.
6697 *
6698 * Example: In a LAG with three active ports, the second port
6699 * ([2][1]) would be selected for traffic mapped to buckets
6700 * 3,4,5 (0x38).
6701 */
6702 { 0xff, 0, 0, 0, 0, 0, 0, 0 },
6703 { 0x0f, 0xf0, 0, 0, 0, 0, 0, 0 },
6704 { 0x07, 0x38, 0xc0, 0, 0, 0, 0, 0 },
6705 { 0x03, 0x0c, 0x30, 0xc0, 0, 0, 0, 0 },
6706 { 0x03, 0x0c, 0x30, 0x40, 0x80, 0, 0, 0 },
6707 { 0x03, 0x0c, 0x10, 0x20, 0x40, 0x80, 0, 0 },
6708 { 0x03, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0 },
6709 { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 },
6710 };
6711
mv88e6xxx_lag_set_port_mask(u16 * mask,int port,int num_tx,int nth)6712 static void mv88e6xxx_lag_set_port_mask(u16 *mask, int port,
6713 int num_tx, int nth)
6714 {
6715 u8 active = 0;
6716 int i;
6717
6718 num_tx = num_tx <= 8 ? num_tx : 8;
6719 if (nth < num_tx)
6720 active = mv88e6xxx_lag_mask_table[num_tx - 1][nth];
6721
6722 for (i = 0; i < 8; i++) {
6723 if (BIT(i) & active)
6724 mask[i] |= BIT(port);
6725 }
6726 }
6727
mv88e6xxx_lag_sync_masks(struct dsa_switch * ds)6728 static int mv88e6xxx_lag_sync_masks(struct dsa_switch *ds)
6729 {
6730 struct mv88e6xxx_chip *chip = ds->priv;
6731 unsigned int id, num_tx;
6732 struct dsa_port *dp;
6733 struct dsa_lag *lag;
6734 int i, err, nth;
6735 u16 mask[8];
6736 u16 ivec;
6737
6738 /* Assume no port is a member of any LAG. */
6739 ivec = BIT(mv88e6xxx_num_ports(chip)) - 1;
6740
6741 /* Disable all masks for ports that _are_ members of a LAG. */
6742 dsa_switch_for_each_port(dp, ds) {
6743 if (!dp->lag)
6744 continue;
6745
6746 ivec &= ~BIT(dp->index);
6747 }
6748
6749 for (i = 0; i < 8; i++)
6750 mask[i] = ivec;
6751
6752 /* Enable the correct subset of masks for all LAG ports that
6753 * are in the Tx set.
6754 */
6755 dsa_lags_foreach_id(id, ds->dst) {
6756 lag = dsa_lag_by_id(ds->dst, id);
6757 if (!lag)
6758 continue;
6759
6760 num_tx = 0;
6761 dsa_lag_foreach_port(dp, ds->dst, lag) {
6762 if (dp->lag_tx_enabled)
6763 num_tx++;
6764 }
6765
6766 if (!num_tx)
6767 continue;
6768
6769 nth = 0;
6770 dsa_lag_foreach_port(dp, ds->dst, lag) {
6771 if (!dp->lag_tx_enabled)
6772 continue;
6773
6774 if (dp->ds == ds)
6775 mv88e6xxx_lag_set_port_mask(mask, dp->index,
6776 num_tx, nth);
6777
6778 nth++;
6779 }
6780 }
6781
6782 for (i = 0; i < 8; i++) {
6783 err = mv88e6xxx_g2_trunk_mask_write(chip, i, true, mask[i]);
6784 if (err)
6785 return err;
6786 }
6787
6788 return 0;
6789 }
6790
mv88e6xxx_lag_sync_masks_map(struct dsa_switch * ds,struct dsa_lag lag)6791 static int mv88e6xxx_lag_sync_masks_map(struct dsa_switch *ds,
6792 struct dsa_lag lag)
6793 {
6794 int err;
6795
6796 err = mv88e6xxx_lag_sync_masks(ds);
6797
6798 if (!err)
6799 err = mv88e6xxx_lag_sync_map(ds, lag);
6800
6801 return err;
6802 }
6803
mv88e6xxx_port_lag_change(struct dsa_switch * ds,int port)6804 static int mv88e6xxx_port_lag_change(struct dsa_switch *ds, int port)
6805 {
6806 struct mv88e6xxx_chip *chip = ds->priv;
6807 int err;
6808
6809 mv88e6xxx_reg_lock(chip);
6810 err = mv88e6xxx_lag_sync_masks(ds);
6811 mv88e6xxx_reg_unlock(chip);
6812 return err;
6813 }
6814
mv88e6xxx_port_lag_join(struct dsa_switch * ds,int port,struct dsa_lag lag,struct netdev_lag_upper_info * info,struct netlink_ext_ack * extack)6815 static int mv88e6xxx_port_lag_join(struct dsa_switch *ds, int port,
6816 struct dsa_lag lag,
6817 struct netdev_lag_upper_info *info,
6818 struct netlink_ext_ack *extack)
6819 {
6820 struct mv88e6xxx_chip *chip = ds->priv;
6821 int err, id;
6822
6823 if (!mv88e6xxx_lag_can_offload(ds, lag, info, extack))
6824 return -EOPNOTSUPP;
6825
6826 /* DSA LAG IDs are one-based */
6827 id = lag.id - 1;
6828
6829 mv88e6xxx_reg_lock(chip);
6830
6831 err = mv88e6xxx_port_set_trunk(chip, port, true, id);
6832 if (err)
6833 goto err_unlock;
6834
6835 err = mv88e6xxx_lag_sync_masks_map(ds, lag);
6836 if (err)
6837 goto err_clear_trunk;
6838
6839 mv88e6xxx_reg_unlock(chip);
6840 return 0;
6841
6842 err_clear_trunk:
6843 mv88e6xxx_port_set_trunk(chip, port, false, 0);
6844 err_unlock:
6845 mv88e6xxx_reg_unlock(chip);
6846 return err;
6847 }
6848
mv88e6xxx_port_lag_leave(struct dsa_switch * ds,int port,struct dsa_lag lag)6849 static int mv88e6xxx_port_lag_leave(struct dsa_switch *ds, int port,
6850 struct dsa_lag lag)
6851 {
6852 struct mv88e6xxx_chip *chip = ds->priv;
6853 int err_sync, err_trunk;
6854
6855 mv88e6xxx_reg_lock(chip);
6856 err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag);
6857 err_trunk = mv88e6xxx_port_set_trunk(chip, port, false, 0);
6858 mv88e6xxx_reg_unlock(chip);
6859 return err_sync ? : err_trunk;
6860 }
6861
mv88e6xxx_crosschip_lag_change(struct dsa_switch * ds,int sw_index,int port)6862 static int mv88e6xxx_crosschip_lag_change(struct dsa_switch *ds, int sw_index,
6863 int port)
6864 {
6865 struct mv88e6xxx_chip *chip = ds->priv;
6866 int err;
6867
6868 mv88e6xxx_reg_lock(chip);
6869 err = mv88e6xxx_lag_sync_masks(ds);
6870 mv88e6xxx_reg_unlock(chip);
6871 return err;
6872 }
6873
mv88e6xxx_crosschip_lag_join(struct dsa_switch * ds,int sw_index,int port,struct dsa_lag lag,struct netdev_lag_upper_info * info,struct netlink_ext_ack * extack)6874 static int mv88e6xxx_crosschip_lag_join(struct dsa_switch *ds, int sw_index,
6875 int port, struct dsa_lag lag,
6876 struct netdev_lag_upper_info *info,
6877 struct netlink_ext_ack *extack)
6878 {
6879 struct mv88e6xxx_chip *chip = ds->priv;
6880 int err;
6881
6882 if (!mv88e6xxx_lag_can_offload(ds, lag, info, extack))
6883 return -EOPNOTSUPP;
6884
6885 mv88e6xxx_reg_lock(chip);
6886
6887 err = mv88e6xxx_lag_sync_masks_map(ds, lag);
6888 if (err)
6889 goto unlock;
6890
6891 err = mv88e6xxx_pvt_map(chip, sw_index, port);
6892
6893 unlock:
6894 mv88e6xxx_reg_unlock(chip);
6895 return err;
6896 }
6897
mv88e6xxx_crosschip_lag_leave(struct dsa_switch * ds,int sw_index,int port,struct dsa_lag lag)6898 static int mv88e6xxx_crosschip_lag_leave(struct dsa_switch *ds, int sw_index,
6899 int port, struct dsa_lag lag)
6900 {
6901 struct mv88e6xxx_chip *chip = ds->priv;
6902 int err_sync, err_pvt;
6903
6904 mv88e6xxx_reg_lock(chip);
6905 err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag);
6906 err_pvt = mv88e6xxx_pvt_map(chip, sw_index, port);
6907 mv88e6xxx_reg_unlock(chip);
6908 return err_sync ? : err_pvt;
6909 }
6910
6911 static const struct dsa_switch_ops mv88e6xxx_switch_ops = {
6912 .get_tag_protocol = mv88e6xxx_get_tag_protocol,
6913 .change_tag_protocol = mv88e6xxx_change_tag_protocol,
6914 .setup = mv88e6xxx_setup,
6915 .teardown = mv88e6xxx_teardown,
6916 .port_setup = mv88e6xxx_port_setup,
6917 .port_teardown = mv88e6xxx_port_teardown,
6918 .phylink_get_caps = mv88e6xxx_get_caps,
6919 .phylink_mac_select_pcs = mv88e6xxx_mac_select_pcs,
6920 .phylink_mac_prepare = mv88e6xxx_mac_prepare,
6921 .phylink_mac_config = mv88e6xxx_mac_config,
6922 .phylink_mac_finish = mv88e6xxx_mac_finish,
6923 .phylink_mac_link_down = mv88e6xxx_mac_link_down,
6924 .phylink_mac_link_up = mv88e6xxx_mac_link_up,
6925 .get_strings = mv88e6xxx_get_strings,
6926 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats,
6927 .get_sset_count = mv88e6xxx_get_sset_count,
6928 .port_max_mtu = mv88e6xxx_get_max_mtu,
6929 .port_change_mtu = mv88e6xxx_change_mtu,
6930 .get_mac_eee = mv88e6xxx_get_mac_eee,
6931 .set_mac_eee = mv88e6xxx_set_mac_eee,
6932 .get_eeprom_len = mv88e6xxx_get_eeprom_len,
6933 .get_eeprom = mv88e6xxx_get_eeprom,
6934 .set_eeprom = mv88e6xxx_set_eeprom,
6935 .get_regs_len = mv88e6xxx_get_regs_len,
6936 .get_regs = mv88e6xxx_get_regs,
6937 .get_rxnfc = mv88e6xxx_get_rxnfc,
6938 .set_rxnfc = mv88e6xxx_set_rxnfc,
6939 .set_ageing_time = mv88e6xxx_set_ageing_time,
6940 .port_bridge_join = mv88e6xxx_port_bridge_join,
6941 .port_bridge_leave = mv88e6xxx_port_bridge_leave,
6942 .port_pre_bridge_flags = mv88e6xxx_port_pre_bridge_flags,
6943 .port_bridge_flags = mv88e6xxx_port_bridge_flags,
6944 .port_stp_state_set = mv88e6xxx_port_stp_state_set,
6945 .port_mst_state_set = mv88e6xxx_port_mst_state_set,
6946 .port_fast_age = mv88e6xxx_port_fast_age,
6947 .port_vlan_fast_age = mv88e6xxx_port_vlan_fast_age,
6948 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering,
6949 .port_vlan_add = mv88e6xxx_port_vlan_add,
6950 .port_vlan_del = mv88e6xxx_port_vlan_del,
6951 .vlan_msti_set = mv88e6xxx_vlan_msti_set,
6952 .port_fdb_add = mv88e6xxx_port_fdb_add,
6953 .port_fdb_del = mv88e6xxx_port_fdb_del,
6954 .port_fdb_dump = mv88e6xxx_port_fdb_dump,
6955 .port_mdb_add = mv88e6xxx_port_mdb_add,
6956 .port_mdb_del = mv88e6xxx_port_mdb_del,
6957 .port_mirror_add = mv88e6xxx_port_mirror_add,
6958 .port_mirror_del = mv88e6xxx_port_mirror_del,
6959 .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join,
6960 .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave,
6961 .port_hwtstamp_set = mv88e6xxx_port_hwtstamp_set,
6962 .port_hwtstamp_get = mv88e6xxx_port_hwtstamp_get,
6963 .port_txtstamp = mv88e6xxx_port_txtstamp,
6964 .port_rxtstamp = mv88e6xxx_port_rxtstamp,
6965 .get_ts_info = mv88e6xxx_get_ts_info,
6966 .devlink_param_get = mv88e6xxx_devlink_param_get,
6967 .devlink_param_set = mv88e6xxx_devlink_param_set,
6968 .devlink_info_get = mv88e6xxx_devlink_info_get,
6969 .port_lag_change = mv88e6xxx_port_lag_change,
6970 .port_lag_join = mv88e6xxx_port_lag_join,
6971 .port_lag_leave = mv88e6xxx_port_lag_leave,
6972 .crosschip_lag_change = mv88e6xxx_crosschip_lag_change,
6973 .crosschip_lag_join = mv88e6xxx_crosschip_lag_join,
6974 .crosschip_lag_leave = mv88e6xxx_crosschip_lag_leave,
6975 };
6976
mv88e6xxx_register_switch(struct mv88e6xxx_chip * chip)6977 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip)
6978 {
6979 struct device *dev = chip->dev;
6980 struct dsa_switch *ds;
6981
6982 ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL);
6983 if (!ds)
6984 return -ENOMEM;
6985
6986 ds->dev = dev;
6987 ds->num_ports = mv88e6xxx_num_ports(chip);
6988 ds->priv = chip;
6989 ds->dev = dev;
6990 ds->ops = &mv88e6xxx_switch_ops;
6991 ds->ageing_time_min = chip->info->age_time_coeff;
6992 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX;
6993
6994 /* Some chips support up to 32, but that requires enabling the
6995 * 5-bit port mode, which we do not support. 640k^W16 ought to
6996 * be enough for anyone.
6997 */
6998 ds->num_lag_ids = mv88e6xxx_has_lag(chip) ? 16 : 0;
6999
7000 dev_set_drvdata(dev, ds);
7001
7002 return dsa_register_switch(ds);
7003 }
7004
mv88e6xxx_unregister_switch(struct mv88e6xxx_chip * chip)7005 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
7006 {
7007 dsa_unregister_switch(chip->ds);
7008 }
7009
pdata_device_get_match_data(struct device * dev)7010 static const void *pdata_device_get_match_data(struct device *dev)
7011 {
7012 const struct of_device_id *matches = dev->driver->of_match_table;
7013 const struct dsa_mv88e6xxx_pdata *pdata = dev->platform_data;
7014
7015 for (; matches->name[0] || matches->type[0] || matches->compatible[0];
7016 matches++) {
7017 if (!strcmp(pdata->compatible, matches->compatible))
7018 return matches->data;
7019 }
7020 return NULL;
7021 }
7022
7023 /* There is no suspend to RAM support at DSA level yet, the switch configuration
7024 * would be lost after a power cycle so prevent it to be suspended.
7025 */
mv88e6xxx_suspend(struct device * dev)7026 static int __maybe_unused mv88e6xxx_suspend(struct device *dev)
7027 {
7028 return -EOPNOTSUPP;
7029 }
7030
mv88e6xxx_resume(struct device * dev)7031 static int __maybe_unused mv88e6xxx_resume(struct device *dev)
7032 {
7033 return 0;
7034 }
7035
7036 static SIMPLE_DEV_PM_OPS(mv88e6xxx_pm_ops, mv88e6xxx_suspend, mv88e6xxx_resume);
7037
mv88e6xxx_probe(struct mdio_device * mdiodev)7038 static int mv88e6xxx_probe(struct mdio_device *mdiodev)
7039 {
7040 struct dsa_mv88e6xxx_pdata *pdata = mdiodev->dev.platform_data;
7041 const struct mv88e6xxx_info *compat_info = NULL;
7042 struct device *dev = &mdiodev->dev;
7043 struct device_node *np = dev->of_node;
7044 struct mv88e6xxx_chip *chip;
7045 int port;
7046 int err;
7047
7048 if (!np && !pdata)
7049 return -EINVAL;
7050
7051 if (np)
7052 compat_info = of_device_get_match_data(dev);
7053
7054 if (pdata) {
7055 compat_info = pdata_device_get_match_data(dev);
7056
7057 if (!pdata->netdev)
7058 return -EINVAL;
7059
7060 for (port = 0; port < DSA_MAX_PORTS; port++) {
7061 if (!(pdata->enabled_ports & (1 << port)))
7062 continue;
7063 if (strcmp(pdata->cd.port_names[port], "cpu"))
7064 continue;
7065 pdata->cd.netdev[port] = &pdata->netdev->dev;
7066 break;
7067 }
7068 }
7069
7070 if (!compat_info)
7071 return -EINVAL;
7072
7073 chip = mv88e6xxx_alloc_chip(dev);
7074 if (!chip) {
7075 err = -ENOMEM;
7076 goto out;
7077 }
7078
7079 chip->info = compat_info;
7080
7081 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
7082 if (IS_ERR(chip->reset)) {
7083 err = PTR_ERR(chip->reset);
7084 goto out;
7085 }
7086 if (chip->reset)
7087 usleep_range(10000, 20000);
7088
7089 /* Detect if the device is configured in single chip addressing mode,
7090 * otherwise continue with address specific smi init/detection.
7091 */
7092 err = mv88e6xxx_single_chip_detect(chip, mdiodev);
7093 if (err) {
7094 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
7095 if (err)
7096 goto out;
7097
7098 err = mv88e6xxx_detect(chip);
7099 if (err)
7100 goto out;
7101 }
7102
7103 if (chip->info->edsa_support == MV88E6XXX_EDSA_SUPPORTED)
7104 chip->tag_protocol = DSA_TAG_PROTO_EDSA;
7105 else
7106 chip->tag_protocol = DSA_TAG_PROTO_DSA;
7107
7108 mv88e6xxx_phy_init(chip);
7109
7110 if (chip->info->ops->get_eeprom) {
7111 if (np)
7112 of_property_read_u32(np, "eeprom-length",
7113 &chip->eeprom_len);
7114 else
7115 chip->eeprom_len = pdata->eeprom_len;
7116 }
7117
7118 mv88e6xxx_reg_lock(chip);
7119 err = mv88e6xxx_switch_reset(chip);
7120 mv88e6xxx_reg_unlock(chip);
7121 if (err)
7122 goto out;
7123
7124 if (np) {
7125 chip->irq = of_irq_get(np, 0);
7126 if (chip->irq == -EPROBE_DEFER) {
7127 err = chip->irq;
7128 goto out;
7129 }
7130 }
7131
7132 if (pdata)
7133 chip->irq = pdata->irq;
7134
7135 /* Has to be performed before the MDIO bus is created, because
7136 * the PHYs will link their interrupts to these interrupt
7137 * controllers
7138 */
7139 mv88e6xxx_reg_lock(chip);
7140 if (chip->irq > 0)
7141 err = mv88e6xxx_g1_irq_setup(chip);
7142 else
7143 err = mv88e6xxx_irq_poll_setup(chip);
7144 mv88e6xxx_reg_unlock(chip);
7145
7146 if (err)
7147 goto out;
7148
7149 if (chip->info->g2_irqs > 0) {
7150 err = mv88e6xxx_g2_irq_setup(chip);
7151 if (err)
7152 goto out_g1_irq;
7153 }
7154
7155 err = mv88e6xxx_g1_atu_prob_irq_setup(chip);
7156 if (err)
7157 goto out_g2_irq;
7158
7159 err = mv88e6xxx_g1_vtu_prob_irq_setup(chip);
7160 if (err)
7161 goto out_g1_atu_prob_irq;
7162
7163 err = mv88e6xxx_register_switch(chip);
7164 if (err)
7165 goto out_g1_vtu_prob_irq;
7166
7167 return 0;
7168
7169 out_g1_vtu_prob_irq:
7170 mv88e6xxx_g1_vtu_prob_irq_free(chip);
7171 out_g1_atu_prob_irq:
7172 mv88e6xxx_g1_atu_prob_irq_free(chip);
7173 out_g2_irq:
7174 if (chip->info->g2_irqs > 0)
7175 mv88e6xxx_g2_irq_free(chip);
7176 out_g1_irq:
7177 if (chip->irq > 0)
7178 mv88e6xxx_g1_irq_free(chip);
7179 else
7180 mv88e6xxx_irq_poll_free(chip);
7181 out:
7182 if (pdata)
7183 dev_put(pdata->netdev);
7184
7185 return err;
7186 }
7187
mv88e6xxx_remove(struct mdio_device * mdiodev)7188 static void mv88e6xxx_remove(struct mdio_device *mdiodev)
7189 {
7190 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
7191 struct mv88e6xxx_chip *chip;
7192
7193 if (!ds)
7194 return;
7195
7196 chip = ds->priv;
7197
7198 if (chip->info->ptp_support) {
7199 mv88e6xxx_hwtstamp_free(chip);
7200 mv88e6xxx_ptp_free(chip);
7201 }
7202
7203 mv88e6xxx_phy_destroy(chip);
7204 mv88e6xxx_unregister_switch(chip);
7205
7206 mv88e6xxx_g1_vtu_prob_irq_free(chip);
7207 mv88e6xxx_g1_atu_prob_irq_free(chip);
7208
7209 if (chip->info->g2_irqs > 0)
7210 mv88e6xxx_g2_irq_free(chip);
7211
7212 if (chip->irq > 0)
7213 mv88e6xxx_g1_irq_free(chip);
7214 else
7215 mv88e6xxx_irq_poll_free(chip);
7216 }
7217
mv88e6xxx_shutdown(struct mdio_device * mdiodev)7218 static void mv88e6xxx_shutdown(struct mdio_device *mdiodev)
7219 {
7220 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
7221
7222 if (!ds)
7223 return;
7224
7225 dsa_switch_shutdown(ds);
7226
7227 dev_set_drvdata(&mdiodev->dev, NULL);
7228 }
7229
7230 static const struct of_device_id mv88e6xxx_of_match[] = {
7231 {
7232 .compatible = "marvell,mv88e6085",
7233 .data = &mv88e6xxx_table[MV88E6085],
7234 },
7235 {
7236 .compatible = "marvell,mv88e6190",
7237 .data = &mv88e6xxx_table[MV88E6190],
7238 },
7239 {
7240 .compatible = "marvell,mv88e6250",
7241 .data = &mv88e6xxx_table[MV88E6250],
7242 },
7243 { /* sentinel */ },
7244 };
7245
7246 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);
7247
7248 static struct mdio_driver mv88e6xxx_driver = {
7249 .probe = mv88e6xxx_probe,
7250 .remove = mv88e6xxx_remove,
7251 .shutdown = mv88e6xxx_shutdown,
7252 .mdiodrv.driver = {
7253 .name = "mv88e6085",
7254 .of_match_table = mv88e6xxx_of_match,
7255 .pm = &mv88e6xxx_pm_ops,
7256 },
7257 };
7258
7259 mdio_module_driver(mv88e6xxx_driver);
7260
7261 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
7262 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
7263 MODULE_LICENSE("GPL");
7264