1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (C) 2021 Felix Fietkau <nbd@nbd.name> */
3
4 #include <linux/kernel.h>
5 #include <linux/platform_device.h>
6 #include <linux/slab.h>
7 #include <linux/module.h>
8 #include <linux/bitfield.h>
9 #include <linux/dma-mapping.h>
10 #include <linux/skbuff.h>
11 #include <linux/of_platform.h>
12 #include <linux/of_address.h>
13 #include <linux/of_reserved_mem.h>
14 #include <linux/mfd/syscon.h>
15 #include <linux/debugfs.h>
16 #include <linux/soc/mediatek/mtk_wed.h>
17 #include <net/flow_offload.h>
18 #include <net/pkt_cls.h>
19 #include "mtk_eth_soc.h"
20 #include "mtk_wed_regs.h"
21 #include "mtk_wed.h"
22 #include "mtk_ppe.h"
23 #include "mtk_wed_wo.h"
24
25 #define MTK_PCIE_BASE(n) (0x1a143000 + (n) * 0x2000)
26
27 #define MTK_WED_PKT_SIZE 1900
28 #define MTK_WED_BUF_SIZE 2048
29 #define MTK_WED_BUF_PER_PAGE (PAGE_SIZE / 2048)
30 #define MTK_WED_RX_RING_SIZE 1536
31
32 #define MTK_WED_TX_RING_SIZE 2048
33 #define MTK_WED_WDMA_RING_SIZE 1024
34 #define MTK_WED_MAX_GROUP_SIZE 0x100
35 #define MTK_WED_VLD_GROUP_SIZE 0x40
36 #define MTK_WED_PER_GROUP_PKT 128
37
38 #define MTK_WED_FBUF_SIZE 128
39 #define MTK_WED_MIOD_CNT 16
40 #define MTK_WED_FB_CMD_CNT 1024
41 #define MTK_WED_RRO_QUE_CNT 8192
42 #define MTK_WED_MIOD_ENTRY_CNT 128
43
44 static struct mtk_wed_hw *hw_list[2];
45 static DEFINE_MUTEX(hw_lock);
46
47 struct mtk_wed_flow_block_priv {
48 struct mtk_wed_hw *hw;
49 struct net_device *dev;
50 };
51
52 static void
wed_m32(struct mtk_wed_device * dev,u32 reg,u32 mask,u32 val)53 wed_m32(struct mtk_wed_device *dev, u32 reg, u32 mask, u32 val)
54 {
55 regmap_update_bits(dev->hw->regs, reg, mask | val, val);
56 }
57
58 static void
wed_set(struct mtk_wed_device * dev,u32 reg,u32 mask)59 wed_set(struct mtk_wed_device *dev, u32 reg, u32 mask)
60 {
61 return wed_m32(dev, reg, 0, mask);
62 }
63
64 static void
wed_clr(struct mtk_wed_device * dev,u32 reg,u32 mask)65 wed_clr(struct mtk_wed_device *dev, u32 reg, u32 mask)
66 {
67 return wed_m32(dev, reg, mask, 0);
68 }
69
70 static void
wdma_m32(struct mtk_wed_device * dev,u32 reg,u32 mask,u32 val)71 wdma_m32(struct mtk_wed_device *dev, u32 reg, u32 mask, u32 val)
72 {
73 wdma_w32(dev, reg, (wdma_r32(dev, reg) & ~mask) | val);
74 }
75
76 static void
wdma_set(struct mtk_wed_device * dev,u32 reg,u32 mask)77 wdma_set(struct mtk_wed_device *dev, u32 reg, u32 mask)
78 {
79 wdma_m32(dev, reg, 0, mask);
80 }
81
82 static void
wdma_clr(struct mtk_wed_device * dev,u32 reg,u32 mask)83 wdma_clr(struct mtk_wed_device *dev, u32 reg, u32 mask)
84 {
85 wdma_m32(dev, reg, mask, 0);
86 }
87
88 static u32
wifi_r32(struct mtk_wed_device * dev,u32 reg)89 wifi_r32(struct mtk_wed_device *dev, u32 reg)
90 {
91 return readl(dev->wlan.base + reg);
92 }
93
94 static void
wifi_w32(struct mtk_wed_device * dev,u32 reg,u32 val)95 wifi_w32(struct mtk_wed_device *dev, u32 reg, u32 val)
96 {
97 writel(val, dev->wlan.base + reg);
98 }
99
100 static u32
mtk_wed_read_reset(struct mtk_wed_device * dev)101 mtk_wed_read_reset(struct mtk_wed_device *dev)
102 {
103 return wed_r32(dev, MTK_WED_RESET);
104 }
105
106 static u32
mtk_wdma_read_reset(struct mtk_wed_device * dev)107 mtk_wdma_read_reset(struct mtk_wed_device *dev)
108 {
109 return wdma_r32(dev, MTK_WDMA_GLO_CFG);
110 }
111
112 static int
mtk_wdma_rx_reset(struct mtk_wed_device * dev)113 mtk_wdma_rx_reset(struct mtk_wed_device *dev)
114 {
115 u32 status, mask = MTK_WDMA_GLO_CFG_RX_DMA_BUSY;
116 int i, ret;
117
118 wdma_clr(dev, MTK_WDMA_GLO_CFG, MTK_WDMA_GLO_CFG_RX_DMA_EN);
119 ret = readx_poll_timeout(mtk_wdma_read_reset, dev, status,
120 !(status & mask), 0, 10000);
121 if (ret)
122 dev_err(dev->hw->dev, "rx reset failed\n");
123
124 wdma_w32(dev, MTK_WDMA_RESET_IDX, MTK_WDMA_RESET_IDX_RX);
125 wdma_w32(dev, MTK_WDMA_RESET_IDX, 0);
126
127 for (i = 0; i < ARRAY_SIZE(dev->rx_wdma); i++) {
128 if (dev->rx_wdma[i].desc)
129 continue;
130
131 wdma_w32(dev,
132 MTK_WDMA_RING_RX(i) + MTK_WED_RING_OFS_CPU_IDX, 0);
133 }
134
135 return ret;
136 }
137
138 static void
mtk_wdma_tx_reset(struct mtk_wed_device * dev)139 mtk_wdma_tx_reset(struct mtk_wed_device *dev)
140 {
141 u32 status, mask = MTK_WDMA_GLO_CFG_TX_DMA_BUSY;
142 int i;
143
144 wdma_clr(dev, MTK_WDMA_GLO_CFG, MTK_WDMA_GLO_CFG_TX_DMA_EN);
145 if (readx_poll_timeout(mtk_wdma_read_reset, dev, status,
146 !(status & mask), 0, 10000))
147 dev_err(dev->hw->dev, "tx reset failed\n");
148
149 wdma_w32(dev, MTK_WDMA_RESET_IDX, MTK_WDMA_RESET_IDX_TX);
150 wdma_w32(dev, MTK_WDMA_RESET_IDX, 0);
151
152 for (i = 0; i < ARRAY_SIZE(dev->tx_wdma); i++)
153 wdma_w32(dev,
154 MTK_WDMA_RING_TX(i) + MTK_WED_RING_OFS_CPU_IDX, 0);
155 }
156
157 static void
mtk_wed_reset(struct mtk_wed_device * dev,u32 mask)158 mtk_wed_reset(struct mtk_wed_device *dev, u32 mask)
159 {
160 u32 status;
161
162 wed_w32(dev, MTK_WED_RESET, mask);
163 if (readx_poll_timeout(mtk_wed_read_reset, dev, status,
164 !(status & mask), 0, 1000))
165 WARN_ON_ONCE(1);
166 }
167
168 static u32
mtk_wed_wo_read_status(struct mtk_wed_device * dev)169 mtk_wed_wo_read_status(struct mtk_wed_device *dev)
170 {
171 return wed_r32(dev, MTK_WED_SCR0 + 4 * MTK_WED_DUMMY_CR_WO_STATUS);
172 }
173
174 static void
mtk_wed_wo_reset(struct mtk_wed_device * dev)175 mtk_wed_wo_reset(struct mtk_wed_device *dev)
176 {
177 struct mtk_wed_wo *wo = dev->hw->wed_wo;
178 u8 state = MTK_WED_WO_STATE_DISABLE;
179 void __iomem *reg;
180 u32 val;
181
182 mtk_wdma_tx_reset(dev);
183 mtk_wed_reset(dev, MTK_WED_RESET_WED);
184
185 if (mtk_wed_mcu_send_msg(wo, MTK_WED_MODULE_ID_WO,
186 MTK_WED_WO_CMD_CHANGE_STATE, &state,
187 sizeof(state), false))
188 return;
189
190 if (readx_poll_timeout(mtk_wed_wo_read_status, dev, val,
191 val == MTK_WED_WOIF_DISABLE_DONE,
192 100, MTK_WOCPU_TIMEOUT))
193 dev_err(dev->hw->dev, "failed to disable wed-wo\n");
194
195 reg = ioremap(MTK_WED_WO_CPU_MCUSYS_RESET_ADDR, 4);
196
197 val = readl(reg);
198 switch (dev->hw->index) {
199 case 0:
200 val |= MTK_WED_WO_CPU_WO0_MCUSYS_RESET_MASK;
201 writel(val, reg);
202 val &= ~MTK_WED_WO_CPU_WO0_MCUSYS_RESET_MASK;
203 writel(val, reg);
204 break;
205 case 1:
206 val |= MTK_WED_WO_CPU_WO1_MCUSYS_RESET_MASK;
207 writel(val, reg);
208 val &= ~MTK_WED_WO_CPU_WO1_MCUSYS_RESET_MASK;
209 writel(val, reg);
210 break;
211 default:
212 break;
213 }
214 iounmap(reg);
215 }
216
mtk_wed_fe_reset(void)217 void mtk_wed_fe_reset(void)
218 {
219 int i;
220
221 mutex_lock(&hw_lock);
222
223 for (i = 0; i < ARRAY_SIZE(hw_list); i++) {
224 struct mtk_wed_hw *hw = hw_list[i];
225 struct mtk_wed_device *dev;
226 int err;
227
228 if (!hw)
229 break;
230
231 dev = hw->wed_dev;
232 if (!dev || !dev->wlan.reset)
233 continue;
234
235 /* reset callback blocks until WLAN reset is completed */
236 err = dev->wlan.reset(dev);
237 if (err)
238 dev_err(dev->dev, "wlan reset failed: %d\n", err);
239 }
240
241 mutex_unlock(&hw_lock);
242 }
243
mtk_wed_fe_reset_complete(void)244 void mtk_wed_fe_reset_complete(void)
245 {
246 int i;
247
248 mutex_lock(&hw_lock);
249
250 for (i = 0; i < ARRAY_SIZE(hw_list); i++) {
251 struct mtk_wed_hw *hw = hw_list[i];
252 struct mtk_wed_device *dev;
253
254 if (!hw)
255 break;
256
257 dev = hw->wed_dev;
258 if (!dev || !dev->wlan.reset_complete)
259 continue;
260
261 dev->wlan.reset_complete(dev);
262 }
263
264 mutex_unlock(&hw_lock);
265 }
266
267 static struct mtk_wed_hw *
mtk_wed_assign(struct mtk_wed_device * dev)268 mtk_wed_assign(struct mtk_wed_device *dev)
269 {
270 struct mtk_wed_hw *hw;
271 int i;
272
273 if (dev->wlan.bus_type == MTK_WED_BUS_PCIE) {
274 hw = hw_list[pci_domain_nr(dev->wlan.pci_dev->bus)];
275 if (!hw)
276 return NULL;
277
278 if (!hw->wed_dev)
279 goto out;
280
281 if (hw->version == 1)
282 return NULL;
283
284 /* MT7986 WED devices do not have any pcie slot restrictions */
285 }
286 /* MT7986 PCIE or AXI */
287 for (i = 0; i < ARRAY_SIZE(hw_list); i++) {
288 hw = hw_list[i];
289 if (hw && !hw->wed_dev)
290 goto out;
291 }
292
293 return NULL;
294
295 out:
296 hw->wed_dev = dev;
297 return hw;
298 }
299
300 static int
mtk_wed_tx_buffer_alloc(struct mtk_wed_device * dev)301 mtk_wed_tx_buffer_alloc(struct mtk_wed_device *dev)
302 {
303 struct mtk_wdma_desc *desc;
304 dma_addr_t desc_phys;
305 void **page_list;
306 int token = dev->wlan.token_start;
307 int ring_size;
308 int n_pages;
309 int i, page_idx;
310
311 ring_size = dev->wlan.nbuf & ~(MTK_WED_BUF_PER_PAGE - 1);
312 n_pages = ring_size / MTK_WED_BUF_PER_PAGE;
313
314 page_list = kcalloc(n_pages, sizeof(*page_list), GFP_KERNEL);
315 if (!page_list)
316 return -ENOMEM;
317
318 dev->tx_buf_ring.size = ring_size;
319 dev->tx_buf_ring.pages = page_list;
320
321 desc = dma_alloc_coherent(dev->hw->dev, ring_size * sizeof(*desc),
322 &desc_phys, GFP_KERNEL);
323 if (!desc)
324 return -ENOMEM;
325
326 dev->tx_buf_ring.desc = desc;
327 dev->tx_buf_ring.desc_phys = desc_phys;
328
329 for (i = 0, page_idx = 0; i < ring_size; i += MTK_WED_BUF_PER_PAGE) {
330 dma_addr_t page_phys, buf_phys;
331 struct page *page;
332 void *buf;
333 int s;
334
335 page = __dev_alloc_pages(GFP_KERNEL, 0);
336 if (!page)
337 return -ENOMEM;
338
339 page_phys = dma_map_page(dev->hw->dev, page, 0, PAGE_SIZE,
340 DMA_BIDIRECTIONAL);
341 if (dma_mapping_error(dev->hw->dev, page_phys)) {
342 __free_page(page);
343 return -ENOMEM;
344 }
345
346 page_list[page_idx++] = page;
347 dma_sync_single_for_cpu(dev->hw->dev, page_phys, PAGE_SIZE,
348 DMA_BIDIRECTIONAL);
349
350 buf = page_to_virt(page);
351 buf_phys = page_phys;
352
353 for (s = 0; s < MTK_WED_BUF_PER_PAGE; s++) {
354 u32 txd_size;
355 u32 ctrl;
356
357 txd_size = dev->wlan.init_buf(buf, buf_phys, token++);
358
359 desc->buf0 = cpu_to_le32(buf_phys);
360 desc->buf1 = cpu_to_le32(buf_phys + txd_size);
361
362 if (dev->hw->version == 1)
363 ctrl = FIELD_PREP(MTK_WDMA_DESC_CTRL_LEN0, txd_size) |
364 FIELD_PREP(MTK_WDMA_DESC_CTRL_LEN1,
365 MTK_WED_BUF_SIZE - txd_size) |
366 MTK_WDMA_DESC_CTRL_LAST_SEG1;
367 else
368 ctrl = FIELD_PREP(MTK_WDMA_DESC_CTRL_LEN0, txd_size) |
369 FIELD_PREP(MTK_WDMA_DESC_CTRL_LEN1_V2,
370 MTK_WED_BUF_SIZE - txd_size) |
371 MTK_WDMA_DESC_CTRL_LAST_SEG0;
372 desc->ctrl = cpu_to_le32(ctrl);
373 desc->info = 0;
374 desc++;
375
376 buf += MTK_WED_BUF_SIZE;
377 buf_phys += MTK_WED_BUF_SIZE;
378 }
379
380 dma_sync_single_for_device(dev->hw->dev, page_phys, PAGE_SIZE,
381 DMA_BIDIRECTIONAL);
382 }
383
384 return 0;
385 }
386
387 static void
mtk_wed_free_tx_buffer(struct mtk_wed_device * dev)388 mtk_wed_free_tx_buffer(struct mtk_wed_device *dev)
389 {
390 struct mtk_wdma_desc *desc = dev->tx_buf_ring.desc;
391 void **page_list = dev->tx_buf_ring.pages;
392 int page_idx;
393 int i;
394
395 if (!page_list)
396 return;
397
398 if (!desc)
399 goto free_pagelist;
400
401 for (i = 0, page_idx = 0; i < dev->tx_buf_ring.size;
402 i += MTK_WED_BUF_PER_PAGE) {
403 void *page = page_list[page_idx++];
404 dma_addr_t buf_addr;
405
406 if (!page)
407 break;
408
409 buf_addr = le32_to_cpu(desc[i].buf0);
410 dma_unmap_page(dev->hw->dev, buf_addr, PAGE_SIZE,
411 DMA_BIDIRECTIONAL);
412 __free_page(page);
413 }
414
415 dma_free_coherent(dev->hw->dev, dev->tx_buf_ring.size * sizeof(*desc),
416 desc, dev->tx_buf_ring.desc_phys);
417
418 free_pagelist:
419 kfree(page_list);
420 }
421
422 static int
mtk_wed_rx_buffer_alloc(struct mtk_wed_device * dev)423 mtk_wed_rx_buffer_alloc(struct mtk_wed_device *dev)
424 {
425 struct mtk_rxbm_desc *desc;
426 dma_addr_t desc_phys;
427
428 dev->rx_buf_ring.size = dev->wlan.rx_nbuf;
429 desc = dma_alloc_coherent(dev->hw->dev,
430 dev->wlan.rx_nbuf * sizeof(*desc),
431 &desc_phys, GFP_KERNEL);
432 if (!desc)
433 return -ENOMEM;
434
435 dev->rx_buf_ring.desc = desc;
436 dev->rx_buf_ring.desc_phys = desc_phys;
437 dev->wlan.init_rx_buf(dev, dev->wlan.rx_npkt);
438
439 return 0;
440 }
441
442 static void
mtk_wed_free_rx_buffer(struct mtk_wed_device * dev)443 mtk_wed_free_rx_buffer(struct mtk_wed_device *dev)
444 {
445 struct mtk_rxbm_desc *desc = dev->rx_buf_ring.desc;
446
447 if (!desc)
448 return;
449
450 dev->wlan.release_rx_buf(dev);
451 dma_free_coherent(dev->hw->dev, dev->rx_buf_ring.size * sizeof(*desc),
452 desc, dev->rx_buf_ring.desc_phys);
453 }
454
455 static void
mtk_wed_rx_buffer_hw_init(struct mtk_wed_device * dev)456 mtk_wed_rx_buffer_hw_init(struct mtk_wed_device *dev)
457 {
458 wed_w32(dev, MTK_WED_RX_BM_RX_DMAD,
459 FIELD_PREP(MTK_WED_RX_BM_RX_DMAD_SDL0, dev->wlan.rx_size));
460 wed_w32(dev, MTK_WED_RX_BM_BASE, dev->rx_buf_ring.desc_phys);
461 wed_w32(dev, MTK_WED_RX_BM_INIT_PTR, MTK_WED_RX_BM_INIT_SW_TAIL |
462 FIELD_PREP(MTK_WED_RX_BM_SW_TAIL, dev->wlan.rx_npkt));
463 wed_w32(dev, MTK_WED_RX_BM_DYN_ALLOC_TH,
464 FIELD_PREP(MTK_WED_RX_BM_DYN_ALLOC_TH_H, 0xffff));
465 wed_set(dev, MTK_WED_CTRL, MTK_WED_CTRL_WED_RX_BM_EN);
466 }
467
468 static void
mtk_wed_free_ring(struct mtk_wed_device * dev,struct mtk_wed_ring * ring)469 mtk_wed_free_ring(struct mtk_wed_device *dev, struct mtk_wed_ring *ring)
470 {
471 if (!ring->desc)
472 return;
473
474 dma_free_coherent(dev->hw->dev, ring->size * ring->desc_size,
475 ring->desc, ring->desc_phys);
476 }
477
478 static void
mtk_wed_free_rx_rings(struct mtk_wed_device * dev)479 mtk_wed_free_rx_rings(struct mtk_wed_device *dev)
480 {
481 mtk_wed_free_rx_buffer(dev);
482 mtk_wed_free_ring(dev, &dev->rro.ring);
483 }
484
485 static void
mtk_wed_free_tx_rings(struct mtk_wed_device * dev)486 mtk_wed_free_tx_rings(struct mtk_wed_device *dev)
487 {
488 int i;
489
490 for (i = 0; i < ARRAY_SIZE(dev->tx_ring); i++)
491 mtk_wed_free_ring(dev, &dev->tx_ring[i]);
492 for (i = 0; i < ARRAY_SIZE(dev->rx_wdma); i++)
493 mtk_wed_free_ring(dev, &dev->rx_wdma[i]);
494 }
495
496 static void
mtk_wed_set_ext_int(struct mtk_wed_device * dev,bool en)497 mtk_wed_set_ext_int(struct mtk_wed_device *dev, bool en)
498 {
499 u32 mask = MTK_WED_EXT_INT_STATUS_ERROR_MASK;
500
501 if (dev->hw->version == 1)
502 mask |= MTK_WED_EXT_INT_STATUS_TX_DRV_R_RESP_ERR;
503 else
504 mask |= MTK_WED_EXT_INT_STATUS_RX_FBUF_LO_TH |
505 MTK_WED_EXT_INT_STATUS_RX_FBUF_HI_TH |
506 MTK_WED_EXT_INT_STATUS_RX_DRV_COHERENT |
507 MTK_WED_EXT_INT_STATUS_TX_DMA_W_RESP_ERR;
508
509 if (!dev->hw->num_flows)
510 mask &= ~MTK_WED_EXT_INT_STATUS_TKID_WO_PYLD;
511
512 wed_w32(dev, MTK_WED_EXT_INT_MASK, en ? mask : 0);
513 wed_r32(dev, MTK_WED_EXT_INT_MASK);
514 }
515
516 static void
mtk_wed_set_512_support(struct mtk_wed_device * dev,bool enable)517 mtk_wed_set_512_support(struct mtk_wed_device *dev, bool enable)
518 {
519 if (enable) {
520 wed_w32(dev, MTK_WED_TXDP_CTRL, MTK_WED_TXDP_DW9_OVERWR);
521 wed_w32(dev, MTK_WED_TXP_DW1,
522 FIELD_PREP(MTK_WED_WPDMA_WRITE_TXP, 0x0103));
523 } else {
524 wed_w32(dev, MTK_WED_TXP_DW1,
525 FIELD_PREP(MTK_WED_WPDMA_WRITE_TXP, 0x0100));
526 wed_clr(dev, MTK_WED_TXDP_CTRL, MTK_WED_TXDP_DW9_OVERWR);
527 }
528 }
529
530 #define MTK_WFMDA_RX_DMA_EN BIT(2)
531 static void
mtk_wed_check_wfdma_rx_fill(struct mtk_wed_device * dev,int idx)532 mtk_wed_check_wfdma_rx_fill(struct mtk_wed_device *dev, int idx)
533 {
534 u32 val;
535 int i;
536
537 if (!(dev->rx_ring[idx].flags & MTK_WED_RING_CONFIGURED))
538 return; /* queue is not configured by mt76 */
539
540 for (i = 0; i < 3; i++) {
541 u32 cur_idx;
542
543 cur_idx = wed_r32(dev,
544 MTK_WED_WPDMA_RING_RX_DATA(idx) +
545 MTK_WED_RING_OFS_CPU_IDX);
546 if (cur_idx == MTK_WED_RX_RING_SIZE - 1)
547 break;
548
549 usleep_range(100000, 200000);
550 }
551
552 if (i == 3) {
553 dev_err(dev->hw->dev, "rx dma enable failed\n");
554 return;
555 }
556
557 val = wifi_r32(dev, dev->wlan.wpdma_rx_glo - dev->wlan.phy_base) |
558 MTK_WFMDA_RX_DMA_EN;
559 wifi_w32(dev, dev->wlan.wpdma_rx_glo - dev->wlan.phy_base, val);
560 }
561
562 static void
mtk_wed_dma_disable(struct mtk_wed_device * dev)563 mtk_wed_dma_disable(struct mtk_wed_device *dev)
564 {
565 wed_clr(dev, MTK_WED_WPDMA_GLO_CFG,
566 MTK_WED_WPDMA_GLO_CFG_TX_DRV_EN |
567 MTK_WED_WPDMA_GLO_CFG_RX_DRV_EN);
568
569 wed_clr(dev, MTK_WED_WDMA_GLO_CFG, MTK_WED_WDMA_GLO_CFG_RX_DRV_EN);
570
571 wed_clr(dev, MTK_WED_GLO_CFG,
572 MTK_WED_GLO_CFG_TX_DMA_EN |
573 MTK_WED_GLO_CFG_RX_DMA_EN);
574
575 wdma_clr(dev, MTK_WDMA_GLO_CFG,
576 MTK_WDMA_GLO_CFG_TX_DMA_EN |
577 MTK_WDMA_GLO_CFG_RX_INFO1_PRERES |
578 MTK_WDMA_GLO_CFG_RX_INFO2_PRERES);
579
580 if (dev->hw->version == 1) {
581 regmap_write(dev->hw->mirror, dev->hw->index * 4, 0);
582 wdma_clr(dev, MTK_WDMA_GLO_CFG,
583 MTK_WDMA_GLO_CFG_RX_INFO3_PRERES);
584 } else {
585 wed_clr(dev, MTK_WED_WPDMA_GLO_CFG,
586 MTK_WED_WPDMA_GLO_CFG_RX_DRV_R0_PKT_PROC |
587 MTK_WED_WPDMA_GLO_CFG_RX_DRV_R0_CRX_SYNC);
588
589 wed_clr(dev, MTK_WED_WPDMA_RX_D_GLO_CFG,
590 MTK_WED_WPDMA_RX_D_RX_DRV_EN);
591 wed_clr(dev, MTK_WED_WDMA_GLO_CFG,
592 MTK_WED_WDMA_GLO_CFG_TX_DDONE_CHK);
593 }
594
595 mtk_wed_set_512_support(dev, false);
596 }
597
598 static void
mtk_wed_stop(struct mtk_wed_device * dev)599 mtk_wed_stop(struct mtk_wed_device *dev)
600 {
601 mtk_wed_dma_disable(dev);
602 mtk_wed_set_ext_int(dev, false);
603
604 wed_w32(dev, MTK_WED_WPDMA_INT_TRIGGER, 0);
605 wed_w32(dev, MTK_WED_WDMA_INT_TRIGGER, 0);
606 wdma_w32(dev, MTK_WDMA_INT_MASK, 0);
607 wdma_w32(dev, MTK_WDMA_INT_GRP2, 0);
608
609 if (dev->hw->version == 1)
610 return;
611
612 wed_w32(dev, MTK_WED_EXT_INT_MASK1, 0);
613 wed_w32(dev, MTK_WED_EXT_INT_MASK2, 0);
614 }
615
616 static void
mtk_wed_deinit(struct mtk_wed_device * dev)617 mtk_wed_deinit(struct mtk_wed_device *dev)
618 {
619 mtk_wed_stop(dev);
620
621 wed_clr(dev, MTK_WED_CTRL,
622 MTK_WED_CTRL_WDMA_INT_AGENT_EN |
623 MTK_WED_CTRL_WPDMA_INT_AGENT_EN |
624 MTK_WED_CTRL_WED_TX_BM_EN |
625 MTK_WED_CTRL_WED_TX_FREE_AGENT_EN);
626
627 if (dev->hw->version == 1)
628 return;
629
630 wed_clr(dev, MTK_WED_CTRL,
631 MTK_WED_CTRL_RX_ROUTE_QM_EN |
632 MTK_WED_CTRL_WED_RX_BM_EN |
633 MTK_WED_CTRL_RX_RRO_QM_EN);
634 }
635
636 static void
__mtk_wed_detach(struct mtk_wed_device * dev)637 __mtk_wed_detach(struct mtk_wed_device *dev)
638 {
639 struct mtk_wed_hw *hw = dev->hw;
640
641 mtk_wed_deinit(dev);
642
643 mtk_wdma_rx_reset(dev);
644 mtk_wed_reset(dev, MTK_WED_RESET_WED);
645 mtk_wed_free_tx_buffer(dev);
646 mtk_wed_free_tx_rings(dev);
647
648 if (mtk_wed_get_rx_capa(dev)) {
649 if (hw->wed_wo)
650 mtk_wed_wo_reset(dev);
651 mtk_wed_free_rx_rings(dev);
652 if (hw->wed_wo)
653 mtk_wed_wo_deinit(hw);
654 }
655
656 if (dev->wlan.bus_type == MTK_WED_BUS_PCIE) {
657 struct device_node *wlan_node;
658
659 wlan_node = dev->wlan.pci_dev->dev.of_node;
660 if (of_dma_is_coherent(wlan_node) && hw->hifsys)
661 regmap_update_bits(hw->hifsys, HIFSYS_DMA_AG_MAP,
662 BIT(hw->index), BIT(hw->index));
663 }
664
665 if ((!hw_list[!hw->index] || !hw_list[!hw->index]->wed_dev) &&
666 hw->eth->dma_dev != hw->eth->dev)
667 mtk_eth_set_dma_device(hw->eth, hw->eth->dev);
668
669 memset(dev, 0, sizeof(*dev));
670 module_put(THIS_MODULE);
671
672 hw->wed_dev = NULL;
673 }
674
675 static void
mtk_wed_detach(struct mtk_wed_device * dev)676 mtk_wed_detach(struct mtk_wed_device *dev)
677 {
678 mutex_lock(&hw_lock);
679 __mtk_wed_detach(dev);
680 mutex_unlock(&hw_lock);
681 }
682
683 #define PCIE_BASE_ADDR0 0x11280000
684 static void
mtk_wed_bus_init(struct mtk_wed_device * dev)685 mtk_wed_bus_init(struct mtk_wed_device *dev)
686 {
687 switch (dev->wlan.bus_type) {
688 case MTK_WED_BUS_PCIE: {
689 struct device_node *np = dev->hw->eth->dev->of_node;
690 struct regmap *regs;
691
692 regs = syscon_regmap_lookup_by_phandle(np,
693 "mediatek,wed-pcie");
694 if (IS_ERR(regs))
695 break;
696
697 regmap_update_bits(regs, 0, BIT(0), BIT(0));
698
699 wed_w32(dev, MTK_WED_PCIE_INT_CTRL,
700 FIELD_PREP(MTK_WED_PCIE_INT_CTRL_POLL_EN, 2));
701
702 /* pcie interrupt control: pola/source selection */
703 wed_set(dev, MTK_WED_PCIE_INT_CTRL,
704 MTK_WED_PCIE_INT_CTRL_MSK_EN_POLA |
705 FIELD_PREP(MTK_WED_PCIE_INT_CTRL_SRC_SEL, 1));
706 wed_r32(dev, MTK_WED_PCIE_INT_CTRL);
707
708 wed_w32(dev, MTK_WED_PCIE_CFG_INTM, PCIE_BASE_ADDR0 | 0x180);
709 wed_w32(dev, MTK_WED_PCIE_CFG_BASE, PCIE_BASE_ADDR0 | 0x184);
710
711 /* pcie interrupt status trigger register */
712 wed_w32(dev, MTK_WED_PCIE_INT_TRIGGER, BIT(24));
713 wed_r32(dev, MTK_WED_PCIE_INT_TRIGGER);
714
715 /* pola setting */
716 wed_set(dev, MTK_WED_PCIE_INT_CTRL,
717 MTK_WED_PCIE_INT_CTRL_MSK_EN_POLA);
718 break;
719 }
720 case MTK_WED_BUS_AXI:
721 wed_set(dev, MTK_WED_WPDMA_INT_CTRL,
722 MTK_WED_WPDMA_INT_CTRL_SIG_SRC |
723 FIELD_PREP(MTK_WED_WPDMA_INT_CTRL_SRC_SEL, 0));
724 break;
725 default:
726 break;
727 }
728 }
729
730 static void
mtk_wed_set_wpdma(struct mtk_wed_device * dev)731 mtk_wed_set_wpdma(struct mtk_wed_device *dev)
732 {
733 if (dev->hw->version == 1) {
734 wed_w32(dev, MTK_WED_WPDMA_CFG_BASE, dev->wlan.wpdma_phys);
735 } else {
736 mtk_wed_bus_init(dev);
737
738 wed_w32(dev, MTK_WED_WPDMA_CFG_BASE, dev->wlan.wpdma_int);
739 wed_w32(dev, MTK_WED_WPDMA_CFG_INT_MASK, dev->wlan.wpdma_mask);
740 wed_w32(dev, MTK_WED_WPDMA_CFG_TX, dev->wlan.wpdma_tx);
741 wed_w32(dev, MTK_WED_WPDMA_CFG_TX_FREE, dev->wlan.wpdma_txfree);
742 wed_w32(dev, MTK_WED_WPDMA_RX_GLO_CFG, dev->wlan.wpdma_rx_glo);
743 wed_w32(dev, MTK_WED_WPDMA_RX_RING, dev->wlan.wpdma_rx);
744 }
745 }
746
747 static void
mtk_wed_hw_init_early(struct mtk_wed_device * dev)748 mtk_wed_hw_init_early(struct mtk_wed_device *dev)
749 {
750 u32 mask, set;
751
752 mtk_wed_deinit(dev);
753 mtk_wed_reset(dev, MTK_WED_RESET_WED);
754 mtk_wed_set_wpdma(dev);
755
756 mask = MTK_WED_WDMA_GLO_CFG_BT_SIZE |
757 MTK_WED_WDMA_GLO_CFG_DYNAMIC_DMAD_RECYCLE |
758 MTK_WED_WDMA_GLO_CFG_RX_DIS_FSM_AUTO_IDLE;
759 set = FIELD_PREP(MTK_WED_WDMA_GLO_CFG_BT_SIZE, 2) |
760 MTK_WED_WDMA_GLO_CFG_DYNAMIC_SKIP_DMAD_PREP |
761 MTK_WED_WDMA_GLO_CFG_IDLE_DMAD_SUPPLY;
762 wed_m32(dev, MTK_WED_WDMA_GLO_CFG, mask, set);
763
764 if (dev->hw->version == 1) {
765 u32 offset = dev->hw->index ? 0x04000400 : 0;
766
767 wdma_set(dev, MTK_WDMA_GLO_CFG,
768 MTK_WDMA_GLO_CFG_RX_INFO1_PRERES |
769 MTK_WDMA_GLO_CFG_RX_INFO2_PRERES |
770 MTK_WDMA_GLO_CFG_RX_INFO3_PRERES);
771
772 wed_w32(dev, MTK_WED_WDMA_OFFSET0, 0x2a042a20 + offset);
773 wed_w32(dev, MTK_WED_WDMA_OFFSET1, 0x29002800 + offset);
774 wed_w32(dev, MTK_WED_PCIE_CFG_BASE,
775 MTK_PCIE_BASE(dev->hw->index));
776 } else {
777 wed_w32(dev, MTK_WED_WDMA_CFG_BASE, dev->hw->wdma_phy);
778 wed_set(dev, MTK_WED_CTRL, MTK_WED_CTRL_ETH_DMAD_FMT);
779 wed_w32(dev, MTK_WED_WDMA_OFFSET0,
780 FIELD_PREP(MTK_WED_WDMA_OFST0_GLO_INTS,
781 MTK_WDMA_INT_STATUS) |
782 FIELD_PREP(MTK_WED_WDMA_OFST0_GLO_CFG,
783 MTK_WDMA_GLO_CFG));
784
785 wed_w32(dev, MTK_WED_WDMA_OFFSET1,
786 FIELD_PREP(MTK_WED_WDMA_OFST1_TX_CTRL,
787 MTK_WDMA_RING_TX(0)) |
788 FIELD_PREP(MTK_WED_WDMA_OFST1_RX_CTRL,
789 MTK_WDMA_RING_RX(0)));
790 }
791 }
792
793 static int
mtk_wed_rro_ring_alloc(struct mtk_wed_device * dev,struct mtk_wed_ring * ring,int size)794 mtk_wed_rro_ring_alloc(struct mtk_wed_device *dev, struct mtk_wed_ring *ring,
795 int size)
796 {
797 ring->desc = dma_alloc_coherent(dev->hw->dev,
798 size * sizeof(*ring->desc),
799 &ring->desc_phys, GFP_KERNEL);
800 if (!ring->desc)
801 return -ENOMEM;
802
803 ring->desc_size = sizeof(*ring->desc);
804 ring->size = size;
805
806 return 0;
807 }
808
809 #define MTK_WED_MIOD_COUNT (MTK_WED_MIOD_ENTRY_CNT * MTK_WED_MIOD_CNT)
810 static int
mtk_wed_rro_alloc(struct mtk_wed_device * dev)811 mtk_wed_rro_alloc(struct mtk_wed_device *dev)
812 {
813 struct reserved_mem *rmem;
814 struct device_node *np;
815 int index;
816
817 index = of_property_match_string(dev->hw->node, "memory-region-names",
818 "wo-dlm");
819 if (index < 0)
820 return index;
821
822 np = of_parse_phandle(dev->hw->node, "memory-region", index);
823 if (!np)
824 return -ENODEV;
825
826 rmem = of_reserved_mem_lookup(np);
827 of_node_put(np);
828
829 if (!rmem)
830 return -ENODEV;
831
832 dev->rro.miod_phys = rmem->base;
833 dev->rro.fdbk_phys = MTK_WED_MIOD_COUNT + dev->rro.miod_phys;
834
835 return mtk_wed_rro_ring_alloc(dev, &dev->rro.ring,
836 MTK_WED_RRO_QUE_CNT);
837 }
838
839 static int
mtk_wed_rro_cfg(struct mtk_wed_device * dev)840 mtk_wed_rro_cfg(struct mtk_wed_device *dev)
841 {
842 struct mtk_wed_wo *wo = dev->hw->wed_wo;
843 struct {
844 struct {
845 __le32 base;
846 __le32 cnt;
847 __le32 unit;
848 } ring[2];
849 __le32 wed;
850 u8 version;
851 } req = {
852 .ring[0] = {
853 .base = cpu_to_le32(MTK_WED_WOCPU_VIEW_MIOD_BASE),
854 .cnt = cpu_to_le32(MTK_WED_MIOD_CNT),
855 .unit = cpu_to_le32(MTK_WED_MIOD_ENTRY_CNT),
856 },
857 .ring[1] = {
858 .base = cpu_to_le32(MTK_WED_WOCPU_VIEW_MIOD_BASE +
859 MTK_WED_MIOD_COUNT),
860 .cnt = cpu_to_le32(MTK_WED_FB_CMD_CNT),
861 .unit = cpu_to_le32(4),
862 },
863 };
864
865 return mtk_wed_mcu_send_msg(wo, MTK_WED_MODULE_ID_WO,
866 MTK_WED_WO_CMD_WED_CFG,
867 &req, sizeof(req), true);
868 }
869
870 static void
mtk_wed_rro_hw_init(struct mtk_wed_device * dev)871 mtk_wed_rro_hw_init(struct mtk_wed_device *dev)
872 {
873 wed_w32(dev, MTK_WED_RROQM_MIOD_CFG,
874 FIELD_PREP(MTK_WED_RROQM_MIOD_MID_DW, 0x70 >> 2) |
875 FIELD_PREP(MTK_WED_RROQM_MIOD_MOD_DW, 0x10 >> 2) |
876 FIELD_PREP(MTK_WED_RROQM_MIOD_ENTRY_DW,
877 MTK_WED_MIOD_ENTRY_CNT >> 2));
878
879 wed_w32(dev, MTK_WED_RROQM_MIOD_CTRL0, dev->rro.miod_phys);
880 wed_w32(dev, MTK_WED_RROQM_MIOD_CTRL1,
881 FIELD_PREP(MTK_WED_RROQM_MIOD_CNT, MTK_WED_MIOD_CNT));
882 wed_w32(dev, MTK_WED_RROQM_FDBK_CTRL0, dev->rro.fdbk_phys);
883 wed_w32(dev, MTK_WED_RROQM_FDBK_CTRL1,
884 FIELD_PREP(MTK_WED_RROQM_FDBK_CNT, MTK_WED_FB_CMD_CNT));
885 wed_w32(dev, MTK_WED_RROQM_FDBK_CTRL2, 0);
886 wed_w32(dev, MTK_WED_RROQ_BASE_L, dev->rro.ring.desc_phys);
887
888 wed_set(dev, MTK_WED_RROQM_RST_IDX,
889 MTK_WED_RROQM_RST_IDX_MIOD |
890 MTK_WED_RROQM_RST_IDX_FDBK);
891
892 wed_w32(dev, MTK_WED_RROQM_RST_IDX, 0);
893 wed_w32(dev, MTK_WED_RROQM_MIOD_CTRL2, MTK_WED_MIOD_CNT - 1);
894 wed_set(dev, MTK_WED_CTRL, MTK_WED_CTRL_RX_RRO_QM_EN);
895 }
896
897 static void
mtk_wed_route_qm_hw_init(struct mtk_wed_device * dev)898 mtk_wed_route_qm_hw_init(struct mtk_wed_device *dev)
899 {
900 wed_w32(dev, MTK_WED_RESET, MTK_WED_RESET_RX_ROUTE_QM);
901
902 for (;;) {
903 usleep_range(100, 200);
904 if (!(wed_r32(dev, MTK_WED_RESET) & MTK_WED_RESET_RX_ROUTE_QM))
905 break;
906 }
907
908 /* configure RX_ROUTE_QM */
909 wed_clr(dev, MTK_WED_RTQM_GLO_CFG, MTK_WED_RTQM_Q_RST);
910 wed_clr(dev, MTK_WED_RTQM_GLO_CFG, MTK_WED_RTQM_TXDMAD_FPORT);
911 wed_set(dev, MTK_WED_RTQM_GLO_CFG,
912 FIELD_PREP(MTK_WED_RTQM_TXDMAD_FPORT, 0x3 + dev->hw->index));
913 wed_clr(dev, MTK_WED_RTQM_GLO_CFG, MTK_WED_RTQM_Q_RST);
914 /* enable RX_ROUTE_QM */
915 wed_set(dev, MTK_WED_CTRL, MTK_WED_CTRL_RX_ROUTE_QM_EN);
916 }
917
918 static void
mtk_wed_hw_init(struct mtk_wed_device * dev)919 mtk_wed_hw_init(struct mtk_wed_device *dev)
920 {
921 if (dev->init_done)
922 return;
923
924 dev->init_done = true;
925 mtk_wed_set_ext_int(dev, false);
926 wed_w32(dev, MTK_WED_TX_BM_CTRL,
927 MTK_WED_TX_BM_CTRL_PAUSE |
928 FIELD_PREP(MTK_WED_TX_BM_CTRL_VLD_GRP_NUM,
929 dev->tx_buf_ring.size / 128) |
930 FIELD_PREP(MTK_WED_TX_BM_CTRL_RSV_GRP_NUM,
931 MTK_WED_TX_RING_SIZE / 256));
932
933 wed_w32(dev, MTK_WED_TX_BM_BASE, dev->tx_buf_ring.desc_phys);
934
935 wed_w32(dev, MTK_WED_TX_BM_BUF_LEN, MTK_WED_PKT_SIZE);
936
937 if (dev->hw->version == 1) {
938 wed_w32(dev, MTK_WED_TX_BM_TKID,
939 FIELD_PREP(MTK_WED_TX_BM_TKID_START,
940 dev->wlan.token_start) |
941 FIELD_PREP(MTK_WED_TX_BM_TKID_END,
942 dev->wlan.token_start +
943 dev->wlan.nbuf - 1));
944 wed_w32(dev, MTK_WED_TX_BM_DYN_THR,
945 FIELD_PREP(MTK_WED_TX_BM_DYN_THR_LO, 1) |
946 MTK_WED_TX_BM_DYN_THR_HI);
947 } else {
948 wed_w32(dev, MTK_WED_TX_BM_TKID_V2,
949 FIELD_PREP(MTK_WED_TX_BM_TKID_START,
950 dev->wlan.token_start) |
951 FIELD_PREP(MTK_WED_TX_BM_TKID_END,
952 dev->wlan.token_start +
953 dev->wlan.nbuf - 1));
954 wed_w32(dev, MTK_WED_TX_BM_DYN_THR,
955 FIELD_PREP(MTK_WED_TX_BM_DYN_THR_LO_V2, 0) |
956 MTK_WED_TX_BM_DYN_THR_HI_V2);
957 wed_w32(dev, MTK_WED_TX_TKID_CTRL,
958 MTK_WED_TX_TKID_CTRL_PAUSE |
959 FIELD_PREP(MTK_WED_TX_TKID_CTRL_VLD_GRP_NUM,
960 dev->tx_buf_ring.size / 128) |
961 FIELD_PREP(MTK_WED_TX_TKID_CTRL_RSV_GRP_NUM,
962 dev->tx_buf_ring.size / 128));
963 wed_w32(dev, MTK_WED_TX_TKID_DYN_THR,
964 FIELD_PREP(MTK_WED_TX_TKID_DYN_THR_LO, 0) |
965 MTK_WED_TX_TKID_DYN_THR_HI);
966 }
967
968 mtk_wed_reset(dev, MTK_WED_RESET_TX_BM);
969
970 if (dev->hw->version == 1) {
971 wed_set(dev, MTK_WED_CTRL,
972 MTK_WED_CTRL_WED_TX_BM_EN |
973 MTK_WED_CTRL_WED_TX_FREE_AGENT_EN);
974 } else {
975 wed_clr(dev, MTK_WED_TX_TKID_CTRL, MTK_WED_TX_TKID_CTRL_PAUSE);
976 /* rx hw init */
977 wed_w32(dev, MTK_WED_WPDMA_RX_D_RST_IDX,
978 MTK_WED_WPDMA_RX_D_RST_CRX_IDX |
979 MTK_WED_WPDMA_RX_D_RST_DRV_IDX);
980 wed_w32(dev, MTK_WED_WPDMA_RX_D_RST_IDX, 0);
981
982 mtk_wed_rx_buffer_hw_init(dev);
983 mtk_wed_rro_hw_init(dev);
984 mtk_wed_route_qm_hw_init(dev);
985 }
986
987 wed_clr(dev, MTK_WED_TX_BM_CTRL, MTK_WED_TX_BM_CTRL_PAUSE);
988 }
989
990 static void
mtk_wed_ring_reset(struct mtk_wed_ring * ring,int size,bool tx)991 mtk_wed_ring_reset(struct mtk_wed_ring *ring, int size, bool tx)
992 {
993 void *head = (void *)ring->desc;
994 int i;
995
996 for (i = 0; i < size; i++) {
997 struct mtk_wdma_desc *desc;
998
999 desc = (struct mtk_wdma_desc *)(head + i * ring->desc_size);
1000 desc->buf0 = 0;
1001 if (tx)
1002 desc->ctrl = cpu_to_le32(MTK_WDMA_DESC_CTRL_DMA_DONE);
1003 else
1004 desc->ctrl = cpu_to_le32(MTK_WFDMA_DESC_CTRL_TO_HOST);
1005 desc->buf1 = 0;
1006 desc->info = 0;
1007 }
1008 }
1009
1010 static u32
mtk_wed_check_busy(struct mtk_wed_device * dev,u32 reg,u32 mask)1011 mtk_wed_check_busy(struct mtk_wed_device *dev, u32 reg, u32 mask)
1012 {
1013 return !!(wed_r32(dev, reg) & mask);
1014 }
1015
1016 static int
mtk_wed_poll_busy(struct mtk_wed_device * dev,u32 reg,u32 mask)1017 mtk_wed_poll_busy(struct mtk_wed_device *dev, u32 reg, u32 mask)
1018 {
1019 int sleep = 15000;
1020 int timeout = 100 * sleep;
1021 u32 val;
1022
1023 return read_poll_timeout(mtk_wed_check_busy, val, !val, sleep,
1024 timeout, false, dev, reg, mask);
1025 }
1026
1027 static int
mtk_wed_rx_reset(struct mtk_wed_device * dev)1028 mtk_wed_rx_reset(struct mtk_wed_device *dev)
1029 {
1030 struct mtk_wed_wo *wo = dev->hw->wed_wo;
1031 u8 val = MTK_WED_WO_STATE_SER_RESET;
1032 int i, ret;
1033
1034 ret = mtk_wed_mcu_send_msg(wo, MTK_WED_MODULE_ID_WO,
1035 MTK_WED_WO_CMD_CHANGE_STATE, &val,
1036 sizeof(val), true);
1037 if (ret)
1038 return ret;
1039
1040 wed_clr(dev, MTK_WED_WPDMA_RX_D_GLO_CFG, MTK_WED_WPDMA_RX_D_RX_DRV_EN);
1041 ret = mtk_wed_poll_busy(dev, MTK_WED_WPDMA_RX_D_GLO_CFG,
1042 MTK_WED_WPDMA_RX_D_RX_DRV_BUSY);
1043 if (ret) {
1044 mtk_wed_reset(dev, MTK_WED_RESET_WPDMA_INT_AGENT);
1045 mtk_wed_reset(dev, MTK_WED_RESET_WPDMA_RX_D_DRV);
1046 } else {
1047 wed_w32(dev, MTK_WED_WPDMA_RX_D_RST_IDX,
1048 MTK_WED_WPDMA_RX_D_RST_CRX_IDX |
1049 MTK_WED_WPDMA_RX_D_RST_DRV_IDX);
1050
1051 wed_set(dev, MTK_WED_WPDMA_RX_D_GLO_CFG,
1052 MTK_WED_WPDMA_RX_D_RST_INIT_COMPLETE |
1053 MTK_WED_WPDMA_RX_D_FSM_RETURN_IDLE);
1054 wed_clr(dev, MTK_WED_WPDMA_RX_D_GLO_CFG,
1055 MTK_WED_WPDMA_RX_D_RST_INIT_COMPLETE |
1056 MTK_WED_WPDMA_RX_D_FSM_RETURN_IDLE);
1057
1058 wed_w32(dev, MTK_WED_WPDMA_RX_D_RST_IDX, 0);
1059 }
1060
1061 /* reset rro qm */
1062 wed_clr(dev, MTK_WED_CTRL, MTK_WED_CTRL_RX_RRO_QM_EN);
1063 ret = mtk_wed_poll_busy(dev, MTK_WED_CTRL,
1064 MTK_WED_CTRL_RX_RRO_QM_BUSY);
1065 if (ret) {
1066 mtk_wed_reset(dev, MTK_WED_RESET_RX_RRO_QM);
1067 } else {
1068 wed_set(dev, MTK_WED_RROQM_RST_IDX,
1069 MTK_WED_RROQM_RST_IDX_MIOD |
1070 MTK_WED_RROQM_RST_IDX_FDBK);
1071 wed_w32(dev, MTK_WED_RROQM_RST_IDX, 0);
1072 }
1073
1074 /* reset route qm */
1075 wed_clr(dev, MTK_WED_CTRL, MTK_WED_CTRL_RX_ROUTE_QM_EN);
1076 ret = mtk_wed_poll_busy(dev, MTK_WED_CTRL,
1077 MTK_WED_CTRL_RX_ROUTE_QM_BUSY);
1078 if (ret)
1079 mtk_wed_reset(dev, MTK_WED_RESET_RX_ROUTE_QM);
1080 else
1081 wed_set(dev, MTK_WED_RTQM_GLO_CFG,
1082 MTK_WED_RTQM_Q_RST);
1083
1084 /* reset tx wdma */
1085 mtk_wdma_tx_reset(dev);
1086
1087 /* reset tx wdma drv */
1088 wed_clr(dev, MTK_WED_WDMA_GLO_CFG, MTK_WED_WDMA_GLO_CFG_TX_DRV_EN);
1089 mtk_wed_poll_busy(dev, MTK_WED_CTRL,
1090 MTK_WED_CTRL_WDMA_INT_AGENT_BUSY);
1091 mtk_wed_reset(dev, MTK_WED_RESET_WDMA_TX_DRV);
1092
1093 /* reset wed rx dma */
1094 ret = mtk_wed_poll_busy(dev, MTK_WED_GLO_CFG,
1095 MTK_WED_GLO_CFG_RX_DMA_BUSY);
1096 wed_clr(dev, MTK_WED_GLO_CFG, MTK_WED_GLO_CFG_RX_DMA_EN);
1097 if (ret) {
1098 mtk_wed_reset(dev, MTK_WED_RESET_WED_RX_DMA);
1099 } else {
1100 struct mtk_eth *eth = dev->hw->eth;
1101
1102 if (mtk_is_netsys_v2_or_greater(eth))
1103 wed_set(dev, MTK_WED_RESET_IDX,
1104 MTK_WED_RESET_IDX_RX_V2);
1105 else
1106 wed_set(dev, MTK_WED_RESET_IDX, MTK_WED_RESET_IDX_RX);
1107 wed_w32(dev, MTK_WED_RESET_IDX, 0);
1108 }
1109
1110 /* reset rx bm */
1111 wed_clr(dev, MTK_WED_CTRL, MTK_WED_CTRL_WED_RX_BM_EN);
1112 mtk_wed_poll_busy(dev, MTK_WED_CTRL,
1113 MTK_WED_CTRL_WED_RX_BM_BUSY);
1114 mtk_wed_reset(dev, MTK_WED_RESET_RX_BM);
1115
1116 /* wo change to enable state */
1117 val = MTK_WED_WO_STATE_ENABLE;
1118 ret = mtk_wed_mcu_send_msg(wo, MTK_WED_MODULE_ID_WO,
1119 MTK_WED_WO_CMD_CHANGE_STATE, &val,
1120 sizeof(val), true);
1121 if (ret)
1122 return ret;
1123
1124 /* wed_rx_ring_reset */
1125 for (i = 0; i < ARRAY_SIZE(dev->rx_ring); i++) {
1126 if (!dev->rx_ring[i].desc)
1127 continue;
1128
1129 mtk_wed_ring_reset(&dev->rx_ring[i], MTK_WED_RX_RING_SIZE,
1130 false);
1131 }
1132 mtk_wed_free_rx_buffer(dev);
1133
1134 return 0;
1135 }
1136
1137 static void
mtk_wed_reset_dma(struct mtk_wed_device * dev)1138 mtk_wed_reset_dma(struct mtk_wed_device *dev)
1139 {
1140 bool busy = false;
1141 u32 val;
1142 int i;
1143
1144 for (i = 0; i < ARRAY_SIZE(dev->tx_ring); i++) {
1145 if (!dev->tx_ring[i].desc)
1146 continue;
1147
1148 mtk_wed_ring_reset(&dev->tx_ring[i], MTK_WED_TX_RING_SIZE,
1149 true);
1150 }
1151
1152 /* 1. reset WED tx DMA */
1153 wed_clr(dev, MTK_WED_GLO_CFG, MTK_WED_GLO_CFG_TX_DMA_EN);
1154 busy = mtk_wed_poll_busy(dev, MTK_WED_GLO_CFG,
1155 MTK_WED_GLO_CFG_TX_DMA_BUSY);
1156 if (busy) {
1157 mtk_wed_reset(dev, MTK_WED_RESET_WED_TX_DMA);
1158 } else {
1159 wed_w32(dev, MTK_WED_RESET_IDX, MTK_WED_RESET_IDX_TX);
1160 wed_w32(dev, MTK_WED_RESET_IDX, 0);
1161 }
1162
1163 /* 2. reset WDMA rx DMA */
1164 busy = !!mtk_wdma_rx_reset(dev);
1165 wed_clr(dev, MTK_WED_WDMA_GLO_CFG, MTK_WED_WDMA_GLO_CFG_RX_DRV_EN);
1166 if (!busy)
1167 busy = mtk_wed_poll_busy(dev, MTK_WED_WDMA_GLO_CFG,
1168 MTK_WED_WDMA_GLO_CFG_RX_DRV_BUSY);
1169
1170 if (busy) {
1171 mtk_wed_reset(dev, MTK_WED_RESET_WDMA_INT_AGENT);
1172 mtk_wed_reset(dev, MTK_WED_RESET_WDMA_RX_DRV);
1173 } else {
1174 wed_w32(dev, MTK_WED_WDMA_RESET_IDX,
1175 MTK_WED_WDMA_RESET_IDX_RX | MTK_WED_WDMA_RESET_IDX_DRV);
1176 wed_w32(dev, MTK_WED_WDMA_RESET_IDX, 0);
1177
1178 wed_set(dev, MTK_WED_WDMA_GLO_CFG,
1179 MTK_WED_WDMA_GLO_CFG_RST_INIT_COMPLETE);
1180
1181 wed_clr(dev, MTK_WED_WDMA_GLO_CFG,
1182 MTK_WED_WDMA_GLO_CFG_RST_INIT_COMPLETE);
1183 }
1184
1185 /* 3. reset WED WPDMA tx */
1186 wed_clr(dev, MTK_WED_CTRL, MTK_WED_CTRL_WED_TX_FREE_AGENT_EN);
1187
1188 for (i = 0; i < 100; i++) {
1189 val = wed_r32(dev, MTK_WED_TX_BM_INTF);
1190 if (FIELD_GET(MTK_WED_TX_BM_INTF_TKFIFO_FDEP, val) == 0x40)
1191 break;
1192 }
1193
1194 mtk_wed_reset(dev, MTK_WED_RESET_TX_FREE_AGENT);
1195 wed_clr(dev, MTK_WED_CTRL, MTK_WED_CTRL_WED_TX_BM_EN);
1196 mtk_wed_reset(dev, MTK_WED_RESET_TX_BM);
1197
1198 /* 4. reset WED WPDMA tx */
1199 busy = mtk_wed_poll_busy(dev, MTK_WED_WPDMA_GLO_CFG,
1200 MTK_WED_WPDMA_GLO_CFG_TX_DRV_BUSY);
1201 wed_clr(dev, MTK_WED_WPDMA_GLO_CFG,
1202 MTK_WED_WPDMA_GLO_CFG_TX_DRV_EN |
1203 MTK_WED_WPDMA_GLO_CFG_RX_DRV_EN);
1204 if (!busy)
1205 busy = mtk_wed_poll_busy(dev, MTK_WED_WPDMA_GLO_CFG,
1206 MTK_WED_WPDMA_GLO_CFG_RX_DRV_BUSY);
1207
1208 if (busy) {
1209 mtk_wed_reset(dev, MTK_WED_RESET_WPDMA_INT_AGENT);
1210 mtk_wed_reset(dev, MTK_WED_RESET_WPDMA_TX_DRV);
1211 mtk_wed_reset(dev, MTK_WED_RESET_WPDMA_RX_DRV);
1212 } else {
1213 wed_w32(dev, MTK_WED_WPDMA_RESET_IDX,
1214 MTK_WED_WPDMA_RESET_IDX_TX |
1215 MTK_WED_WPDMA_RESET_IDX_RX);
1216 wed_w32(dev, MTK_WED_WPDMA_RESET_IDX, 0);
1217 }
1218
1219 dev->init_done = false;
1220 if (dev->hw->version == 1)
1221 return;
1222
1223 if (!busy) {
1224 wed_w32(dev, MTK_WED_RESET_IDX, MTK_WED_RESET_WPDMA_IDX_RX);
1225 wed_w32(dev, MTK_WED_RESET_IDX, 0);
1226 }
1227
1228 mtk_wed_rx_reset(dev);
1229 }
1230
1231 static int
mtk_wed_ring_alloc(struct mtk_wed_device * dev,struct mtk_wed_ring * ring,int size,u32 desc_size,bool tx)1232 mtk_wed_ring_alloc(struct mtk_wed_device *dev, struct mtk_wed_ring *ring,
1233 int size, u32 desc_size, bool tx)
1234 {
1235 ring->desc = dma_alloc_coherent(dev->hw->dev, size * desc_size,
1236 &ring->desc_phys, GFP_KERNEL);
1237 if (!ring->desc)
1238 return -ENOMEM;
1239
1240 ring->desc_size = desc_size;
1241 ring->size = size;
1242 mtk_wed_ring_reset(ring, size, tx);
1243
1244 return 0;
1245 }
1246
1247 static int
mtk_wed_wdma_rx_ring_setup(struct mtk_wed_device * dev,int idx,int size,bool reset)1248 mtk_wed_wdma_rx_ring_setup(struct mtk_wed_device *dev, int idx, int size,
1249 bool reset)
1250 {
1251 u32 desc_size = sizeof(struct mtk_wdma_desc) * dev->hw->version;
1252 struct mtk_wed_ring *wdma;
1253
1254 if (idx >= ARRAY_SIZE(dev->rx_wdma))
1255 return -EINVAL;
1256
1257 wdma = &dev->rx_wdma[idx];
1258 if (!reset && mtk_wed_ring_alloc(dev, wdma, MTK_WED_WDMA_RING_SIZE,
1259 desc_size, true))
1260 return -ENOMEM;
1261
1262 wdma_w32(dev, MTK_WDMA_RING_RX(idx) + MTK_WED_RING_OFS_BASE,
1263 wdma->desc_phys);
1264 wdma_w32(dev, MTK_WDMA_RING_RX(idx) + MTK_WED_RING_OFS_COUNT,
1265 size);
1266 wdma_w32(dev, MTK_WDMA_RING_RX(idx) + MTK_WED_RING_OFS_CPU_IDX, 0);
1267
1268 wed_w32(dev, MTK_WED_WDMA_RING_RX(idx) + MTK_WED_RING_OFS_BASE,
1269 wdma->desc_phys);
1270 wed_w32(dev, MTK_WED_WDMA_RING_RX(idx) + MTK_WED_RING_OFS_COUNT,
1271 size);
1272
1273 return 0;
1274 }
1275
1276 static int
mtk_wed_wdma_tx_ring_setup(struct mtk_wed_device * dev,int idx,int size,bool reset)1277 mtk_wed_wdma_tx_ring_setup(struct mtk_wed_device *dev, int idx, int size,
1278 bool reset)
1279 {
1280 u32 desc_size = sizeof(struct mtk_wdma_desc) * dev->hw->version;
1281 struct mtk_wed_ring *wdma;
1282
1283 if (idx >= ARRAY_SIZE(dev->tx_wdma))
1284 return -EINVAL;
1285
1286 wdma = &dev->tx_wdma[idx];
1287 if (!reset && mtk_wed_ring_alloc(dev, wdma, MTK_WED_WDMA_RING_SIZE,
1288 desc_size, true))
1289 return -ENOMEM;
1290
1291 wdma_w32(dev, MTK_WDMA_RING_TX(idx) + MTK_WED_RING_OFS_BASE,
1292 wdma->desc_phys);
1293 wdma_w32(dev, MTK_WDMA_RING_TX(idx) + MTK_WED_RING_OFS_COUNT,
1294 size);
1295 wdma_w32(dev, MTK_WDMA_RING_TX(idx) + MTK_WED_RING_OFS_CPU_IDX, 0);
1296 wdma_w32(dev, MTK_WDMA_RING_TX(idx) + MTK_WED_RING_OFS_DMA_IDX, 0);
1297
1298 if (reset)
1299 mtk_wed_ring_reset(wdma, MTK_WED_WDMA_RING_SIZE, true);
1300
1301 if (!idx) {
1302 wed_w32(dev, MTK_WED_WDMA_RING_TX + MTK_WED_RING_OFS_BASE,
1303 wdma->desc_phys);
1304 wed_w32(dev, MTK_WED_WDMA_RING_TX + MTK_WED_RING_OFS_COUNT,
1305 size);
1306 wed_w32(dev, MTK_WED_WDMA_RING_TX + MTK_WED_RING_OFS_CPU_IDX,
1307 0);
1308 wed_w32(dev, MTK_WED_WDMA_RING_TX + MTK_WED_RING_OFS_DMA_IDX,
1309 0);
1310 }
1311
1312 return 0;
1313 }
1314
1315 static void
mtk_wed_ppe_check(struct mtk_wed_device * dev,struct sk_buff * skb,u32 reason,u32 hash)1316 mtk_wed_ppe_check(struct mtk_wed_device *dev, struct sk_buff *skb,
1317 u32 reason, u32 hash)
1318 {
1319 struct mtk_eth *eth = dev->hw->eth;
1320 struct ethhdr *eh;
1321
1322 if (!skb)
1323 return;
1324
1325 if (reason != MTK_PPE_CPU_REASON_HIT_UNBIND_RATE_REACHED)
1326 return;
1327
1328 skb_set_mac_header(skb, 0);
1329 eh = eth_hdr(skb);
1330 skb->protocol = eh->h_proto;
1331 mtk_ppe_check_skb(eth->ppe[dev->hw->index], skb, hash);
1332 }
1333
1334 static void
mtk_wed_configure_irq(struct mtk_wed_device * dev,u32 irq_mask)1335 mtk_wed_configure_irq(struct mtk_wed_device *dev, u32 irq_mask)
1336 {
1337 u32 wdma_mask = FIELD_PREP(MTK_WDMA_INT_MASK_RX_DONE, GENMASK(1, 0));
1338
1339 /* wed control cr set */
1340 wed_set(dev, MTK_WED_CTRL,
1341 MTK_WED_CTRL_WDMA_INT_AGENT_EN |
1342 MTK_WED_CTRL_WPDMA_INT_AGENT_EN |
1343 MTK_WED_CTRL_WED_TX_BM_EN |
1344 MTK_WED_CTRL_WED_TX_FREE_AGENT_EN);
1345
1346 if (dev->hw->version == 1) {
1347 wed_w32(dev, MTK_WED_PCIE_INT_TRIGGER,
1348 MTK_WED_PCIE_INT_TRIGGER_STATUS);
1349
1350 wed_w32(dev, MTK_WED_WPDMA_INT_TRIGGER,
1351 MTK_WED_WPDMA_INT_TRIGGER_RX_DONE |
1352 MTK_WED_WPDMA_INT_TRIGGER_TX_DONE);
1353
1354 wed_clr(dev, MTK_WED_WDMA_INT_CTRL, wdma_mask);
1355 } else {
1356 wdma_mask |= FIELD_PREP(MTK_WDMA_INT_MASK_TX_DONE,
1357 GENMASK(1, 0));
1358 /* initail tx interrupt trigger */
1359 wed_w32(dev, MTK_WED_WPDMA_INT_CTRL_TX,
1360 MTK_WED_WPDMA_INT_CTRL_TX0_DONE_EN |
1361 MTK_WED_WPDMA_INT_CTRL_TX0_DONE_CLR |
1362 MTK_WED_WPDMA_INT_CTRL_TX1_DONE_EN |
1363 MTK_WED_WPDMA_INT_CTRL_TX1_DONE_CLR |
1364 FIELD_PREP(MTK_WED_WPDMA_INT_CTRL_TX0_DONE_TRIG,
1365 dev->wlan.tx_tbit[0]) |
1366 FIELD_PREP(MTK_WED_WPDMA_INT_CTRL_TX1_DONE_TRIG,
1367 dev->wlan.tx_tbit[1]));
1368
1369 /* initail txfree interrupt trigger */
1370 wed_w32(dev, MTK_WED_WPDMA_INT_CTRL_TX_FREE,
1371 MTK_WED_WPDMA_INT_CTRL_TX_FREE_DONE_EN |
1372 MTK_WED_WPDMA_INT_CTRL_TX_FREE_DONE_CLR |
1373 FIELD_PREP(MTK_WED_WPDMA_INT_CTRL_TX_FREE_DONE_TRIG,
1374 dev->wlan.txfree_tbit));
1375
1376 wed_w32(dev, MTK_WED_WPDMA_INT_CTRL_RX,
1377 MTK_WED_WPDMA_INT_CTRL_RX0_EN |
1378 MTK_WED_WPDMA_INT_CTRL_RX0_CLR |
1379 MTK_WED_WPDMA_INT_CTRL_RX1_EN |
1380 MTK_WED_WPDMA_INT_CTRL_RX1_CLR |
1381 FIELD_PREP(MTK_WED_WPDMA_INT_CTRL_RX0_DONE_TRIG,
1382 dev->wlan.rx_tbit[0]) |
1383 FIELD_PREP(MTK_WED_WPDMA_INT_CTRL_RX1_DONE_TRIG,
1384 dev->wlan.rx_tbit[1]));
1385
1386 wed_w32(dev, MTK_WED_WDMA_INT_CLR, wdma_mask);
1387 wed_set(dev, MTK_WED_WDMA_INT_CTRL,
1388 FIELD_PREP(MTK_WED_WDMA_INT_CTRL_POLL_SRC_SEL,
1389 dev->wdma_idx));
1390 }
1391
1392 wed_w32(dev, MTK_WED_WDMA_INT_TRIGGER, wdma_mask);
1393
1394 wdma_w32(dev, MTK_WDMA_INT_MASK, wdma_mask);
1395 wdma_w32(dev, MTK_WDMA_INT_GRP2, wdma_mask);
1396 wed_w32(dev, MTK_WED_WPDMA_INT_MASK, irq_mask);
1397 wed_w32(dev, MTK_WED_INT_MASK, irq_mask);
1398 }
1399
1400 static void
mtk_wed_dma_enable(struct mtk_wed_device * dev)1401 mtk_wed_dma_enable(struct mtk_wed_device *dev)
1402 {
1403 wed_set(dev, MTK_WED_WPDMA_INT_CTRL, MTK_WED_WPDMA_INT_CTRL_SUBRT_ADV);
1404
1405 wed_set(dev, MTK_WED_GLO_CFG,
1406 MTK_WED_GLO_CFG_TX_DMA_EN |
1407 MTK_WED_GLO_CFG_RX_DMA_EN);
1408 wed_set(dev, MTK_WED_WPDMA_GLO_CFG,
1409 MTK_WED_WPDMA_GLO_CFG_TX_DRV_EN |
1410 MTK_WED_WPDMA_GLO_CFG_RX_DRV_EN);
1411 wed_set(dev, MTK_WED_WDMA_GLO_CFG,
1412 MTK_WED_WDMA_GLO_CFG_RX_DRV_EN);
1413
1414 wdma_set(dev, MTK_WDMA_GLO_CFG,
1415 MTK_WDMA_GLO_CFG_TX_DMA_EN |
1416 MTK_WDMA_GLO_CFG_RX_INFO1_PRERES |
1417 MTK_WDMA_GLO_CFG_RX_INFO2_PRERES);
1418
1419 if (dev->hw->version == 1) {
1420 wdma_set(dev, MTK_WDMA_GLO_CFG,
1421 MTK_WDMA_GLO_CFG_RX_INFO3_PRERES);
1422 } else {
1423 int i;
1424
1425 wed_set(dev, MTK_WED_WPDMA_CTRL,
1426 MTK_WED_WPDMA_CTRL_SDL1_FIXED);
1427
1428 wed_set(dev, MTK_WED_WDMA_GLO_CFG,
1429 MTK_WED_WDMA_GLO_CFG_TX_DRV_EN |
1430 MTK_WED_WDMA_GLO_CFG_TX_DDONE_CHK);
1431
1432 wed_set(dev, MTK_WED_WPDMA_GLO_CFG,
1433 MTK_WED_WPDMA_GLO_CFG_RX_DRV_R0_PKT_PROC |
1434 MTK_WED_WPDMA_GLO_CFG_RX_DRV_R0_CRX_SYNC);
1435
1436 wed_clr(dev, MTK_WED_WPDMA_GLO_CFG,
1437 MTK_WED_WPDMA_GLO_CFG_TX_TKID_KEEP |
1438 MTK_WED_WPDMA_GLO_CFG_TX_DMAD_DW3_PREV);
1439
1440 wed_set(dev, MTK_WED_WPDMA_RX_D_GLO_CFG,
1441 MTK_WED_WPDMA_RX_D_RX_DRV_EN |
1442 FIELD_PREP(MTK_WED_WPDMA_RX_D_RXD_READ_LEN, 0x18) |
1443 FIELD_PREP(MTK_WED_WPDMA_RX_D_INIT_PHASE_RXEN_SEL,
1444 0x2));
1445
1446 for (i = 0; i < MTK_WED_RX_QUEUES; i++)
1447 mtk_wed_check_wfdma_rx_fill(dev, i);
1448 }
1449 }
1450
1451 static void
mtk_wed_start(struct mtk_wed_device * dev,u32 irq_mask)1452 mtk_wed_start(struct mtk_wed_device *dev, u32 irq_mask)
1453 {
1454 int i;
1455
1456 if (mtk_wed_get_rx_capa(dev) && mtk_wed_rx_buffer_alloc(dev))
1457 return;
1458
1459 for (i = 0; i < ARRAY_SIZE(dev->rx_wdma); i++)
1460 if (!dev->rx_wdma[i].desc)
1461 mtk_wed_wdma_rx_ring_setup(dev, i, 16, false);
1462
1463 mtk_wed_hw_init(dev);
1464 mtk_wed_configure_irq(dev, irq_mask);
1465
1466 mtk_wed_set_ext_int(dev, true);
1467
1468 if (dev->hw->version == 1) {
1469 u32 val = dev->wlan.wpdma_phys | MTK_PCIE_MIRROR_MAP_EN |
1470 FIELD_PREP(MTK_PCIE_MIRROR_MAP_WED_ID,
1471 dev->hw->index);
1472
1473 val |= BIT(0) | (BIT(1) * !!dev->hw->index);
1474 regmap_write(dev->hw->mirror, dev->hw->index * 4, val);
1475 } else {
1476 /* driver set mid ready and only once */
1477 wed_w32(dev, MTK_WED_EXT_INT_MASK1,
1478 MTK_WED_EXT_INT_STATUS_WPDMA_MID_RDY);
1479 wed_w32(dev, MTK_WED_EXT_INT_MASK2,
1480 MTK_WED_EXT_INT_STATUS_WPDMA_MID_RDY);
1481
1482 wed_r32(dev, MTK_WED_EXT_INT_MASK1);
1483 wed_r32(dev, MTK_WED_EXT_INT_MASK2);
1484
1485 if (mtk_wed_rro_cfg(dev))
1486 return;
1487
1488 }
1489
1490 mtk_wed_set_512_support(dev, dev->wlan.wcid_512);
1491
1492 mtk_wed_dma_enable(dev);
1493 dev->running = true;
1494 }
1495
1496 static int
mtk_wed_attach(struct mtk_wed_device * dev)1497 mtk_wed_attach(struct mtk_wed_device *dev)
1498 __releases(RCU)
1499 {
1500 struct mtk_wed_hw *hw;
1501 struct device *device;
1502 int ret = 0;
1503
1504 RCU_LOCKDEP_WARN(!rcu_read_lock_held(),
1505 "mtk_wed_attach without holding the RCU read lock");
1506
1507 if ((dev->wlan.bus_type == MTK_WED_BUS_PCIE &&
1508 pci_domain_nr(dev->wlan.pci_dev->bus) > 1) ||
1509 !try_module_get(THIS_MODULE))
1510 ret = -ENODEV;
1511
1512 rcu_read_unlock();
1513
1514 if (ret)
1515 return ret;
1516
1517 mutex_lock(&hw_lock);
1518
1519 hw = mtk_wed_assign(dev);
1520 if (!hw) {
1521 module_put(THIS_MODULE);
1522 ret = -ENODEV;
1523 goto unlock;
1524 }
1525
1526 device = dev->wlan.bus_type == MTK_WED_BUS_PCIE
1527 ? &dev->wlan.pci_dev->dev
1528 : &dev->wlan.platform_dev->dev;
1529 dev_info(device, "attaching wed device %d version %d\n",
1530 hw->index, hw->version);
1531
1532 dev->hw = hw;
1533 dev->dev = hw->dev;
1534 dev->irq = hw->irq;
1535 dev->wdma_idx = hw->index;
1536 dev->version = hw->version;
1537
1538 if (hw->eth->dma_dev == hw->eth->dev &&
1539 of_dma_is_coherent(hw->eth->dev->of_node))
1540 mtk_eth_set_dma_device(hw->eth, hw->dev);
1541
1542 ret = mtk_wed_tx_buffer_alloc(dev);
1543 if (ret)
1544 goto out;
1545
1546 if (mtk_wed_get_rx_capa(dev)) {
1547 ret = mtk_wed_rro_alloc(dev);
1548 if (ret)
1549 goto out;
1550 }
1551
1552 mtk_wed_hw_init_early(dev);
1553 if (hw->version == 1) {
1554 regmap_update_bits(hw->hifsys, HIFSYS_DMA_AG_MAP,
1555 BIT(hw->index), 0);
1556 } else {
1557 dev->rev_id = wed_r32(dev, MTK_WED_REV_ID);
1558 ret = mtk_wed_wo_init(hw);
1559 }
1560 out:
1561 if (ret) {
1562 dev_err(dev->hw->dev, "failed to attach wed device\n");
1563 __mtk_wed_detach(dev);
1564 }
1565 unlock:
1566 mutex_unlock(&hw_lock);
1567
1568 return ret;
1569 }
1570
1571 static int
mtk_wed_tx_ring_setup(struct mtk_wed_device * dev,int idx,void __iomem * regs,bool reset)1572 mtk_wed_tx_ring_setup(struct mtk_wed_device *dev, int idx, void __iomem *regs,
1573 bool reset)
1574 {
1575 struct mtk_wed_ring *ring = &dev->tx_ring[idx];
1576
1577 /*
1578 * Tx ring redirection:
1579 * Instead of configuring the WLAN PDMA TX ring directly, the WLAN
1580 * driver allocated DMA ring gets configured into WED MTK_WED_RING_TX(n)
1581 * registers.
1582 *
1583 * WED driver posts its own DMA ring as WLAN PDMA TX and configures it
1584 * into MTK_WED_WPDMA_RING_TX(n) registers.
1585 * It gets filled with packets picked up from WED TX ring and from
1586 * WDMA RX.
1587 */
1588
1589 if (WARN_ON(idx >= ARRAY_SIZE(dev->tx_ring)))
1590 return -EINVAL;
1591
1592 if (!reset && mtk_wed_ring_alloc(dev, ring, MTK_WED_TX_RING_SIZE,
1593 sizeof(*ring->desc), true))
1594 return -ENOMEM;
1595
1596 if (mtk_wed_wdma_rx_ring_setup(dev, idx, MTK_WED_WDMA_RING_SIZE,
1597 reset))
1598 return -ENOMEM;
1599
1600 ring->reg_base = MTK_WED_RING_TX(idx);
1601 ring->wpdma = regs;
1602
1603 /* WED -> WPDMA */
1604 wpdma_tx_w32(dev, idx, MTK_WED_RING_OFS_BASE, ring->desc_phys);
1605 wpdma_tx_w32(dev, idx, MTK_WED_RING_OFS_COUNT, MTK_WED_TX_RING_SIZE);
1606 wpdma_tx_w32(dev, idx, MTK_WED_RING_OFS_CPU_IDX, 0);
1607
1608 wed_w32(dev, MTK_WED_WPDMA_RING_TX(idx) + MTK_WED_RING_OFS_BASE,
1609 ring->desc_phys);
1610 wed_w32(dev, MTK_WED_WPDMA_RING_TX(idx) + MTK_WED_RING_OFS_COUNT,
1611 MTK_WED_TX_RING_SIZE);
1612 wed_w32(dev, MTK_WED_WPDMA_RING_TX(idx) + MTK_WED_RING_OFS_CPU_IDX, 0);
1613
1614 return 0;
1615 }
1616
1617 static int
mtk_wed_txfree_ring_setup(struct mtk_wed_device * dev,void __iomem * regs)1618 mtk_wed_txfree_ring_setup(struct mtk_wed_device *dev, void __iomem *regs)
1619 {
1620 struct mtk_wed_ring *ring = &dev->txfree_ring;
1621 int i, index = dev->hw->version == 1;
1622
1623 /*
1624 * For txfree event handling, the same DMA ring is shared between WED
1625 * and WLAN. The WLAN driver accesses the ring index registers through
1626 * WED
1627 */
1628 ring->reg_base = MTK_WED_RING_RX(index);
1629 ring->wpdma = regs;
1630
1631 for (i = 0; i < 12; i += 4) {
1632 u32 val = readl(regs + i);
1633
1634 wed_w32(dev, MTK_WED_RING_RX(index) + i, val);
1635 wed_w32(dev, MTK_WED_WPDMA_RING_RX(index) + i, val);
1636 }
1637
1638 return 0;
1639 }
1640
1641 static int
mtk_wed_rx_ring_setup(struct mtk_wed_device * dev,int idx,void __iomem * regs,bool reset)1642 mtk_wed_rx_ring_setup(struct mtk_wed_device *dev, int idx, void __iomem *regs,
1643 bool reset)
1644 {
1645 struct mtk_wed_ring *ring = &dev->rx_ring[idx];
1646
1647 if (WARN_ON(idx >= ARRAY_SIZE(dev->rx_ring)))
1648 return -EINVAL;
1649
1650 if (!reset && mtk_wed_ring_alloc(dev, ring, MTK_WED_RX_RING_SIZE,
1651 sizeof(*ring->desc), false))
1652 return -ENOMEM;
1653
1654 if (mtk_wed_wdma_tx_ring_setup(dev, idx, MTK_WED_WDMA_RING_SIZE,
1655 reset))
1656 return -ENOMEM;
1657
1658 ring->reg_base = MTK_WED_RING_RX_DATA(idx);
1659 ring->wpdma = regs;
1660 ring->flags |= MTK_WED_RING_CONFIGURED;
1661
1662 /* WPDMA -> WED */
1663 wpdma_rx_w32(dev, idx, MTK_WED_RING_OFS_BASE, ring->desc_phys);
1664 wpdma_rx_w32(dev, idx, MTK_WED_RING_OFS_COUNT, MTK_WED_RX_RING_SIZE);
1665
1666 wed_w32(dev, MTK_WED_WPDMA_RING_RX_DATA(idx) + MTK_WED_RING_OFS_BASE,
1667 ring->desc_phys);
1668 wed_w32(dev, MTK_WED_WPDMA_RING_RX_DATA(idx) + MTK_WED_RING_OFS_COUNT,
1669 MTK_WED_RX_RING_SIZE);
1670
1671 return 0;
1672 }
1673
1674 static u32
mtk_wed_irq_get(struct mtk_wed_device * dev,u32 mask)1675 mtk_wed_irq_get(struct mtk_wed_device *dev, u32 mask)
1676 {
1677 u32 val, ext_mask = MTK_WED_EXT_INT_STATUS_ERROR_MASK;
1678
1679 if (dev->hw->version == 1)
1680 ext_mask |= MTK_WED_EXT_INT_STATUS_TX_DRV_R_RESP_ERR;
1681 else
1682 ext_mask |= MTK_WED_EXT_INT_STATUS_RX_FBUF_LO_TH |
1683 MTK_WED_EXT_INT_STATUS_RX_FBUF_HI_TH |
1684 MTK_WED_EXT_INT_STATUS_RX_DRV_COHERENT |
1685 MTK_WED_EXT_INT_STATUS_TX_DMA_W_RESP_ERR;
1686
1687 val = wed_r32(dev, MTK_WED_EXT_INT_STATUS);
1688 wed_w32(dev, MTK_WED_EXT_INT_STATUS, val);
1689 val &= ext_mask;
1690 if (!dev->hw->num_flows)
1691 val &= ~MTK_WED_EXT_INT_STATUS_TKID_WO_PYLD;
1692 if (val && net_ratelimit())
1693 pr_err("mtk_wed%d: error status=%08x\n", dev->hw->index, val);
1694
1695 val = wed_r32(dev, MTK_WED_INT_STATUS);
1696 val &= mask;
1697 wed_w32(dev, MTK_WED_INT_STATUS, val); /* ACK */
1698
1699 return val;
1700 }
1701
1702 static void
mtk_wed_irq_set_mask(struct mtk_wed_device * dev,u32 mask)1703 mtk_wed_irq_set_mask(struct mtk_wed_device *dev, u32 mask)
1704 {
1705 mtk_wed_set_ext_int(dev, !!mask);
1706 wed_w32(dev, MTK_WED_INT_MASK, mask);
1707 }
1708
mtk_wed_flow_add(int index)1709 int mtk_wed_flow_add(int index)
1710 {
1711 struct mtk_wed_hw *hw = hw_list[index];
1712 int ret;
1713
1714 if (!hw || !hw->wed_dev)
1715 return -ENODEV;
1716
1717 if (hw->num_flows) {
1718 hw->num_flows++;
1719 return 0;
1720 }
1721
1722 mutex_lock(&hw_lock);
1723 if (!hw->wed_dev) {
1724 ret = -ENODEV;
1725 goto out;
1726 }
1727
1728 ret = hw->wed_dev->wlan.offload_enable(hw->wed_dev);
1729 if (!ret)
1730 hw->num_flows++;
1731 mtk_wed_set_ext_int(hw->wed_dev, true);
1732
1733 out:
1734 mutex_unlock(&hw_lock);
1735
1736 return ret;
1737 }
1738
mtk_wed_flow_remove(int index)1739 void mtk_wed_flow_remove(int index)
1740 {
1741 struct mtk_wed_hw *hw = hw_list[index];
1742
1743 if (!hw)
1744 return;
1745
1746 if (--hw->num_flows)
1747 return;
1748
1749 mutex_lock(&hw_lock);
1750 if (!hw->wed_dev)
1751 goto out;
1752
1753 hw->wed_dev->wlan.offload_disable(hw->wed_dev);
1754 mtk_wed_set_ext_int(hw->wed_dev, true);
1755
1756 out:
1757 mutex_unlock(&hw_lock);
1758 }
1759
1760 static int
mtk_wed_setup_tc_block_cb(enum tc_setup_type type,void * type_data,void * cb_priv)1761 mtk_wed_setup_tc_block_cb(enum tc_setup_type type, void *type_data, void *cb_priv)
1762 {
1763 struct mtk_wed_flow_block_priv *priv = cb_priv;
1764 struct flow_cls_offload *cls = type_data;
1765 struct mtk_wed_hw *hw = priv->hw;
1766
1767 if (!tc_can_offload(priv->dev))
1768 return -EOPNOTSUPP;
1769
1770 if (type != TC_SETUP_CLSFLOWER)
1771 return -EOPNOTSUPP;
1772
1773 return mtk_flow_offload_cmd(hw->eth, cls, hw->index);
1774 }
1775
1776 static int
mtk_wed_setup_tc_block(struct mtk_wed_hw * hw,struct net_device * dev,struct flow_block_offload * f)1777 mtk_wed_setup_tc_block(struct mtk_wed_hw *hw, struct net_device *dev,
1778 struct flow_block_offload *f)
1779 {
1780 struct mtk_wed_flow_block_priv *priv;
1781 static LIST_HEAD(block_cb_list);
1782 struct flow_block_cb *block_cb;
1783 struct mtk_eth *eth = hw->eth;
1784 flow_setup_cb_t *cb;
1785
1786 if (!eth->soc->offload_version)
1787 return -EOPNOTSUPP;
1788
1789 if (f->binder_type != FLOW_BLOCK_BINDER_TYPE_CLSACT_INGRESS)
1790 return -EOPNOTSUPP;
1791
1792 cb = mtk_wed_setup_tc_block_cb;
1793 f->driver_block_list = &block_cb_list;
1794
1795 switch (f->command) {
1796 case FLOW_BLOCK_BIND:
1797 block_cb = flow_block_cb_lookup(f->block, cb, dev);
1798 if (block_cb) {
1799 flow_block_cb_incref(block_cb);
1800 return 0;
1801 }
1802
1803 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
1804 if (!priv)
1805 return -ENOMEM;
1806
1807 priv->hw = hw;
1808 priv->dev = dev;
1809 block_cb = flow_block_cb_alloc(cb, dev, priv, NULL);
1810 if (IS_ERR(block_cb)) {
1811 kfree(priv);
1812 return PTR_ERR(block_cb);
1813 }
1814
1815 flow_block_cb_incref(block_cb);
1816 flow_block_cb_add(block_cb, f);
1817 list_add_tail(&block_cb->driver_list, &block_cb_list);
1818 return 0;
1819 case FLOW_BLOCK_UNBIND:
1820 block_cb = flow_block_cb_lookup(f->block, cb, dev);
1821 if (!block_cb)
1822 return -ENOENT;
1823
1824 if (!flow_block_cb_decref(block_cb)) {
1825 flow_block_cb_remove(block_cb, f);
1826 list_del(&block_cb->driver_list);
1827 kfree(block_cb->cb_priv);
1828 }
1829 return 0;
1830 default:
1831 return -EOPNOTSUPP;
1832 }
1833 }
1834
1835 static int
mtk_wed_setup_tc(struct mtk_wed_device * wed,struct net_device * dev,enum tc_setup_type type,void * type_data)1836 mtk_wed_setup_tc(struct mtk_wed_device *wed, struct net_device *dev,
1837 enum tc_setup_type type, void *type_data)
1838 {
1839 struct mtk_wed_hw *hw = wed->hw;
1840
1841 if (hw->version < 2)
1842 return -EOPNOTSUPP;
1843
1844 switch (type) {
1845 case TC_SETUP_BLOCK:
1846 case TC_SETUP_FT:
1847 return mtk_wed_setup_tc_block(hw, dev, type_data);
1848 default:
1849 return -EOPNOTSUPP;
1850 }
1851 }
1852
mtk_wed_add_hw(struct device_node * np,struct mtk_eth * eth,void __iomem * wdma,phys_addr_t wdma_phy,int index)1853 void mtk_wed_add_hw(struct device_node *np, struct mtk_eth *eth,
1854 void __iomem *wdma, phys_addr_t wdma_phy,
1855 int index)
1856 {
1857 static const struct mtk_wed_ops wed_ops = {
1858 .attach = mtk_wed_attach,
1859 .tx_ring_setup = mtk_wed_tx_ring_setup,
1860 .rx_ring_setup = mtk_wed_rx_ring_setup,
1861 .txfree_ring_setup = mtk_wed_txfree_ring_setup,
1862 .msg_update = mtk_wed_mcu_msg_update,
1863 .start = mtk_wed_start,
1864 .stop = mtk_wed_stop,
1865 .reset_dma = mtk_wed_reset_dma,
1866 .reg_read = wed_r32,
1867 .reg_write = wed_w32,
1868 .irq_get = mtk_wed_irq_get,
1869 .irq_set_mask = mtk_wed_irq_set_mask,
1870 .detach = mtk_wed_detach,
1871 .ppe_check = mtk_wed_ppe_check,
1872 .setup_tc = mtk_wed_setup_tc,
1873 };
1874 struct device_node *eth_np = eth->dev->of_node;
1875 struct platform_device *pdev;
1876 struct mtk_wed_hw *hw;
1877 struct regmap *regs;
1878 int irq;
1879
1880 if (!np)
1881 return;
1882
1883 pdev = of_find_device_by_node(np);
1884 if (!pdev)
1885 goto err_of_node_put;
1886
1887 get_device(&pdev->dev);
1888 irq = platform_get_irq(pdev, 0);
1889 if (irq < 0)
1890 goto err_put_device;
1891
1892 regs = syscon_regmap_lookup_by_phandle(np, NULL);
1893 if (IS_ERR(regs))
1894 goto err_put_device;
1895
1896 rcu_assign_pointer(mtk_soc_wed_ops, &wed_ops);
1897
1898 mutex_lock(&hw_lock);
1899
1900 if (WARN_ON(hw_list[index]))
1901 goto unlock;
1902
1903 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
1904 if (!hw)
1905 goto unlock;
1906
1907 hw->node = np;
1908 hw->regs = regs;
1909 hw->eth = eth;
1910 hw->dev = &pdev->dev;
1911 hw->wdma_phy = wdma_phy;
1912 hw->wdma = wdma;
1913 hw->index = index;
1914 hw->irq = irq;
1915 hw->version = mtk_is_netsys_v1(eth) ? 1 : 2;
1916
1917 if (hw->version == 1) {
1918 hw->mirror = syscon_regmap_lookup_by_phandle(eth_np,
1919 "mediatek,pcie-mirror");
1920 hw->hifsys = syscon_regmap_lookup_by_phandle(eth_np,
1921 "mediatek,hifsys");
1922 if (IS_ERR(hw->mirror) || IS_ERR(hw->hifsys)) {
1923 kfree(hw);
1924 goto unlock;
1925 }
1926
1927 if (!index) {
1928 regmap_write(hw->mirror, 0, 0);
1929 regmap_write(hw->mirror, 4, 0);
1930 }
1931 }
1932
1933 mtk_wed_hw_add_debugfs(hw);
1934
1935 hw_list[index] = hw;
1936
1937 mutex_unlock(&hw_lock);
1938
1939 return;
1940
1941 unlock:
1942 mutex_unlock(&hw_lock);
1943 err_put_device:
1944 put_device(&pdev->dev);
1945 err_of_node_put:
1946 of_node_put(np);
1947 }
1948
mtk_wed_exit(void)1949 void mtk_wed_exit(void)
1950 {
1951 int i;
1952
1953 rcu_assign_pointer(mtk_soc_wed_ops, NULL);
1954
1955 synchronize_rcu();
1956
1957 for (i = 0; i < ARRAY_SIZE(hw_list); i++) {
1958 struct mtk_wed_hw *hw;
1959
1960 hw = hw_list[i];
1961 if (!hw)
1962 continue;
1963
1964 hw_list[i] = NULL;
1965 debugfs_remove(hw->debugfs_dir);
1966 put_device(hw->dev);
1967 of_node_put(hw->node);
1968 kfree(hw);
1969 }
1970 }
1971