1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2018 MediaTek Inc.
4 * Author: Ryder Lee <ryder.lee@mediatek.com>
5 */
6
7 #include <dm.h>
8
9 #include "pinctrl-mtk-common.h"
10
11 #define PIN_FIELD(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \
12 PIN_FIELD_CALC(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, \
13 _x_bits, 32, false)
14
15 #define MT7629_PIN(_number, _name) MTK_PIN(_number, _name, DRV_GRP1)
16
17 static const struct mtk_pin_field_calc mt7629_pin_mode_range[] = {
18 PIN_FIELD(0, 78, 0x300, 0x10, 0, 4),
19 };
20
21 static const struct mtk_pin_field_calc mt7629_pin_dir_range[] = {
22 PIN_FIELD(0, 78, 0x0, 0x10, 0, 1),
23 };
24
25 static const struct mtk_pin_field_calc mt7629_pin_di_range[] = {
26 PIN_FIELD(0, 78, 0x200, 0x10, 0, 1),
27 };
28
29 static const struct mtk_pin_field_calc mt7629_pin_do_range[] = {
30 PIN_FIELD(0, 78, 0x100, 0x10, 0, 1),
31 };
32
33 static const struct mtk_pin_field_calc mt7629_pin_ies_range[] = {
34 PIN_FIELD(0, 10, 0x1000, 0x10, 0, 1),
35 PIN_FIELD(11, 18, 0x2000, 0x10, 0, 1),
36 PIN_FIELD(19, 32, 0x3000, 0x10, 0, 1),
37 PIN_FIELD(33, 48, 0x4000, 0x10, 0, 1),
38 PIN_FIELD(49, 50, 0x5000, 0x10, 0, 1),
39 PIN_FIELD(51, 69, 0x6000, 0x10, 0, 1),
40 PIN_FIELD(70, 78, 0x7000, 0x10, 0, 1),
41 };
42
43 static const struct mtk_pin_field_calc mt7629_pin_smt_range[] = {
44 PIN_FIELD(0, 10, 0x1100, 0x10, 0, 1),
45 PIN_FIELD(11, 18, 0x2100, 0x10, 0, 1),
46 PIN_FIELD(19, 32, 0x3100, 0x10, 0, 1),
47 PIN_FIELD(33, 48, 0x4100, 0x10, 0, 1),
48 PIN_FIELD(49, 50, 0x5100, 0x10, 0, 1),
49 PIN_FIELD(51, 69, 0x6100, 0x10, 0, 1),
50 PIN_FIELD(70, 78, 0x7100, 0x10, 0, 1),
51 };
52
53 static const struct mtk_pin_field_calc mt7629_pin_pullen_range[] = {
54 PIN_FIELD(0, 10, 0x1400, 0x10, 0, 1),
55 PIN_FIELD(11, 18, 0x2400, 0x10, 0, 1),
56 PIN_FIELD(19, 32, 0x3400, 0x10, 0, 1),
57 PIN_FIELD(33, 48, 0x4400, 0x10, 0, 1),
58 PIN_FIELD(49, 50, 0x5400, 0x10, 0, 1),
59 PIN_FIELD(51, 69, 0x6400, 0x10, 0, 1),
60 PIN_FIELD(70, 78, 0x7400, 0x10, 0, 1),
61 };
62
63 static const struct mtk_pin_field_calc mt7629_pin_pullsel_range[] = {
64 PIN_FIELD(0, 10, 0x1500, 0x10, 0, 1),
65 PIN_FIELD(11, 18, 0x2500, 0x10, 0, 1),
66 PIN_FIELD(19, 32, 0x3500, 0x10, 0, 1),
67 PIN_FIELD(33, 48, 0x4500, 0x10, 0, 1),
68 PIN_FIELD(49, 50, 0x5500, 0x10, 0, 1),
69 PIN_FIELD(51, 69, 0x6500, 0x10, 0, 1),
70 PIN_FIELD(70, 78, 0x7500, 0x10, 0, 1),
71 };
72
73 static const struct mtk_pin_field_calc mt7629_pin_drv_range[] = {
74 PIN_FIELD(0, 10, 0x1600, 0x10, 0, 4),
75 PIN_FIELD(11, 18, 0x2600, 0x10, 0, 4),
76 PIN_FIELD(19, 32, 0x3600, 0x10, 0, 4),
77 PIN_FIELD(33, 48, 0x4600, 0x10, 0, 4),
78 PIN_FIELD(49, 50, 0x5600, 0x10, 0, 4),
79 PIN_FIELD(51, 69, 0x6600, 0x10, 0, 4),
80 PIN_FIELD(70, 78, 0x7600, 0x10, 0, 4),
81 };
82
83 static const struct mtk_pin_reg_calc mt7629_reg_cals[] = {
84 [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7629_pin_mode_range),
85 [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7629_pin_dir_range),
86 [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7629_pin_di_range),
87 [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt7629_pin_do_range),
88 [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt7629_pin_ies_range),
89 [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt7629_pin_smt_range),
90 [PINCTRL_PIN_REG_PULLSEL] = MTK_RANGE(mt7629_pin_pullsel_range),
91 [PINCTRL_PIN_REG_PULLEN] = MTK_RANGE(mt7629_pin_pullen_range),
92 [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt7629_pin_drv_range),
93 };
94
95 static const struct mtk_pin_desc mt7629_pins[] = {
96 MT7629_PIN(0, "TOP_5G_CLK"),
97 MT7629_PIN(1, "TOP_5G_DATA"),
98 MT7629_PIN(2, "WF0_5G_HB0"),
99 MT7629_PIN(3, "WF0_5G_HB1"),
100 MT7629_PIN(4, "WF0_5G_HB2"),
101 MT7629_PIN(5, "WF0_5G_HB3"),
102 MT7629_PIN(6, "WF0_5G_HB4"),
103 MT7629_PIN(7, "WF0_5G_HB5"),
104 MT7629_PIN(8, "WF0_5G_HB6"),
105 MT7629_PIN(9, "XO_REQ"),
106 MT7629_PIN(10, "TOP_RST_N"),
107 MT7629_PIN(11, "SYS_WATCHDOG"),
108 MT7629_PIN(12, "EPHY_LED0_N_JTDO"),
109 MT7629_PIN(13, "EPHY_LED1_N_JTDI"),
110 MT7629_PIN(14, "EPHY_LED2_N_JTMS"),
111 MT7629_PIN(15, "EPHY_LED3_N_JTCLK"),
112 MT7629_PIN(16, "EPHY_LED4_N_JTRST_N"),
113 MT7629_PIN(17, "WF2G_LED_N"),
114 MT7629_PIN(18, "WF5G_LED_N"),
115 MT7629_PIN(19, "I2C_SDA"),
116 MT7629_PIN(20, "I2C_SCL"),
117 MT7629_PIN(21, "GPIO_9"),
118 MT7629_PIN(22, "GPIO_10"),
119 MT7629_PIN(23, "GPIO_11"),
120 MT7629_PIN(24, "GPIO_12"),
121 MT7629_PIN(25, "UART1_TXD"),
122 MT7629_PIN(26, "UART1_RXD"),
123 MT7629_PIN(27, "UART1_CTS"),
124 MT7629_PIN(28, "UART1_RTS"),
125 MT7629_PIN(29, "UART2_TXD"),
126 MT7629_PIN(30, "UART2_RXD"),
127 MT7629_PIN(31, "UART2_CTS"),
128 MT7629_PIN(32, "UART2_RTS"),
129 MT7629_PIN(33, "MDI_TP_P1"),
130 MT7629_PIN(34, "MDI_TN_P1"),
131 MT7629_PIN(35, "MDI_RP_P1"),
132 MT7629_PIN(36, "MDI_RN_P1"),
133 MT7629_PIN(37, "MDI_RP_P2"),
134 MT7629_PIN(38, "MDI_RN_P2"),
135 MT7629_PIN(39, "MDI_TP_P2"),
136 MT7629_PIN(40, "MDI_TN_P2"),
137 MT7629_PIN(41, "MDI_TP_P3"),
138 MT7629_PIN(42, "MDI_TN_P3"),
139 MT7629_PIN(43, "MDI_RP_P3"),
140 MT7629_PIN(44, "MDI_RN_P3"),
141 MT7629_PIN(45, "MDI_RP_P4"),
142 MT7629_PIN(46, "MDI_RN_P4"),
143 MT7629_PIN(47, "MDI_TP_P4"),
144 MT7629_PIN(48, "MDI_TN_P4"),
145 MT7629_PIN(49, "SMI_MDC"),
146 MT7629_PIN(50, "SMI_MDIO"),
147 MT7629_PIN(51, "PCIE_PERESET_N"),
148 MT7629_PIN(52, "PWM_0"),
149 MT7629_PIN(53, "GPIO_0"),
150 MT7629_PIN(54, "GPIO_1"),
151 MT7629_PIN(55, "GPIO_2"),
152 MT7629_PIN(56, "GPIO_3"),
153 MT7629_PIN(57, "GPIO_4"),
154 MT7629_PIN(58, "GPIO_5"),
155 MT7629_PIN(59, "GPIO_6"),
156 MT7629_PIN(60, "GPIO_7"),
157 MT7629_PIN(61, "GPIO_8"),
158 MT7629_PIN(62, "SPI_CLK"),
159 MT7629_PIN(63, "SPI_CS"),
160 MT7629_PIN(64, "SPI_MOSI"),
161 MT7629_PIN(65, "SPI_MISO"),
162 MT7629_PIN(66, "SPI_WP"),
163 MT7629_PIN(67, "SPI_HOLD"),
164 MT7629_PIN(68, "UART0_TXD"),
165 MT7629_PIN(69, "UART0_RXD"),
166 MT7629_PIN(70, "TOP_2G_CLK"),
167 MT7629_PIN(71, "TOP_2G_DATA"),
168 MT7629_PIN(72, "WF0_2G_HB0"),
169 MT7629_PIN(73, "WF0_2G_HB1"),
170 MT7629_PIN(74, "WF0_2G_HB2"),
171 MT7629_PIN(75, "WF0_2G_HB3"),
172 MT7629_PIN(76, "WF0_2G_HB4"),
173 MT7629_PIN(77, "WF0_2G_HB5"),
174 MT7629_PIN(78, "WF0_2G_HB6"),
175 };
176
177 /* List all groups consisting of these pins dedicated to the enablement of
178 * certain hardware block and the corresponding mode for all of the pins.
179 * The hardware probably has multiple combinations of these pinouts.
180 */
181
182 /* WF 5G */
183 static int mt7629_wf0_5g_pins[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, };
184 static int mt7629_wf0_5g_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
185
186 /* LED for EPHY */
187 static int mt7629_ephy_leds_pins[] = { 12, 13, 14, 15, 16, 17, 18, };
188 static int mt7629_ephy_leds_funcs[] = { 1, 1, 1, 1, 1, 1, 1, };
189 static int mt7629_ephy_led0_pins[] = { 12, };
190 static int mt7629_ephy_led0_funcs[] = { 1, };
191 static int mt7629_ephy_led1_pins[] = { 13, };
192 static int mt7629_ephy_led1_funcs[] = { 1, };
193 static int mt7629_ephy_led2_pins[] = { 14, };
194 static int mt7629_ephy_led2_funcs[] = { 1, };
195 static int mt7629_ephy_led3_pins[] = { 15, };
196 static int mt7629_ephy_led3_funcs[] = { 1, };
197 static int mt7629_ephy_led4_pins[] = { 16, };
198 static int mt7629_ephy_led4_funcs[] = { 1, };
199 static int mt7629_wf2g_led_pins[] = { 17, };
200 static int mt7629_wf2g_led_funcs[] = { 1, };
201 static int mt7629_wf5g_led_pins[] = { 18, };
202 static int mt7629_wf5g_led_funcs[] = { 1, };
203
204 /* Watchdog */
205 static int mt7629_watchdog_pins[] = { 11, };
206 static int mt7629_watchdog_funcs[] = { 1, };
207
208 /* LED for GPHY */
209 static int mt7629_gphy_leds_0_pins[] = { 21, 22, 23, };
210 static int mt7629_gphy_leds_0_funcs[] = { 2, 2, 2, };
211 static int mt7629_gphy_led1_0_pins[] = { 21, };
212 static int mt7629_gphy_led1_0_funcs[] = { 2, };
213 static int mt7629_gphy_led2_0_pins[] = { 22, };
214 static int mt7629_gphy_led2_0_funcs[] = { 2, };
215 static int mt7629_gphy_led3_0_pins[] = { 23, };
216 static int mt7629_gphy_led3_0_funcs[] = { 2, };
217 static int mt7629_gphy_leds_1_pins[] = { 57, 58, 59, };
218 static int mt7629_gphy_leds_1_funcs[] = { 1, 1, 1, };
219 static int mt7629_gphy_led1_1_pins[] = { 57, };
220 static int mt7629_gphy_led1_1_funcs[] = { 1, };
221 static int mt7629_gphy_led2_1_pins[] = { 58, };
222 static int mt7629_gphy_led2_1_funcs[] = { 1, };
223 static int mt7629_gphy_led3_1_pins[] = { 59, };
224 static int mt7629_gphy_led3_1_funcs[] = { 1, };
225
226 /* I2C */
227 static int mt7629_i2c_0_pins[] = { 19, 20, };
228 static int mt7629_i2c_0_funcs[] = { 1, 1, };
229 static int mt7629_i2c_1_pins[] = { 53, 54, };
230 static int mt7629_i2c_1_funcs[] = { 1, 1, };
231
232 /* SPI */
233 static int mt7629_spi_0_pins[] = { 21, 22, 23, 24, };
234 static int mt7629_spi_0_funcs[] = { 1, 1, 1, 1, };
235 static int mt7629_spi_1_pins[] = { 62, 63, 64, 65, };
236 static int mt7629_spi_1_funcs[] = { 1, 1, 1, 1, };
237 static int mt7629_spi_wp_pins[] = { 66, };
238 static int mt7629_spi_wp_funcs[] = { 1, };
239 static int mt7629_spi_hold_pins[] = { 67, };
240 static int mt7629_spi_hold_funcs[] = { 1, };
241
242 /* UART */
243 static int mt7629_uart1_0_txd_rxd_pins[] = { 25, 26, };
244 static int mt7629_uart1_0_txd_rxd_funcs[] = { 1, 1, };
245 static int mt7629_uart1_1_txd_rxd_pins[] = { 53, 54, };
246 static int mt7629_uart1_1_txd_rxd_funcs[] = { 2, 2, };
247 static int mt7629_uart2_0_txd_rxd_pins[] = { 29, 30, };
248 static int mt7629_uart2_0_txd_rxd_funcs[] = { 1, 1, };
249 static int mt7629_uart2_1_txd_rxd_pins[] = { 57, 58, };
250 static int mt7629_uart2_1_txd_rxd_funcs[] = { 2, 2, };
251 static int mt7629_uart1_0_cts_rts_pins[] = { 27, 28, };
252 static int mt7629_uart1_0_cts_rts_funcs[] = { 1, 1, };
253 static int mt7629_uart1_1_cts_rts_pins[] = { 55, 56, };
254 static int mt7629_uart1_1_cts_rts_funcs[] = { 2, 2, };
255 static int mt7629_uart2_0_cts_rts_pins[] = { 31, 32, };
256 static int mt7629_uart2_0_cts_rts_funcs[] = { 1, 1, };
257 static int mt7629_uart2_1_cts_rts_pins[] = { 59, 60, };
258 static int mt7629_uart2_1_cts_rts_funcs[] = { 2, 2, };
259 static int mt7629_uart0_txd_rxd_pins[] = { 68, 69, };
260 static int mt7629_uart0_txd_rxd_funcs[] = { 1, 1, };
261
262 /* MDC/MDIO */
263 static int mt7629_mdc_mdio_pins[] = { 49, 50, };
264 static int mt7629_mdc_mdio_funcs[] = { 1, 1, };
265
266 /* PCIE */
267 static int mt7629_pcie_pereset_pins[] = { 51, };
268 static int mt7629_pcie_pereset_funcs[] = { 1, };
269 static int mt7629_pcie_wake_pins[] = { 55, };
270 static int mt7629_pcie_wake_funcs[] = { 1, };
271 static int mt7629_pcie_clkreq_pins[] = { 56, };
272 static int mt7629_pcie_clkreq_funcs[] = { 1, };
273
274 /* PWM */
275 static int mt7629_pwm_0_pins[] = { 52, };
276 static int mt7629_pwm_0_funcs[] = { 1, };
277 static int mt7629_pwm_1_pins[] = { 61, };
278 static int mt7629_pwm_1_funcs[] = { 2, };
279
280 /* WF 2G */
281 static int mt7629_wf0_2g_pins[] = { 70, 71, 72, 73, 74, 75, 76, 77, 78, };
282 static int mt7629_wf0_2g_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, };
283
284 /* SNFI */
285 static int mt7629_snfi_pins[] = { 62, 63, 64, 65, 66, 67 };
286 static int mt7629_snfi_funcs[] = { 2, 2, 2, 2, 2, 2 };
287
288 /* SPI NOR */
289 static int mt7629_snor_pins[] = { 62, 63, 64, 65, 66, 67 };
290 static int mt7629_snor_funcs[] = { 1, 1, 1, 1, 1, 1 };
291
292 static const struct mtk_group_desc mt7629_groups[] = {
293 PINCTRL_PIN_GROUP("wf0_5g", mt7629_wf0_5g),
294 PINCTRL_PIN_GROUP("ephy_leds", mt7629_ephy_leds),
295 PINCTRL_PIN_GROUP("ephy_led0", mt7629_ephy_led0),
296 PINCTRL_PIN_GROUP("ephy_led1", mt7629_ephy_led1),
297 PINCTRL_PIN_GROUP("ephy_led2", mt7629_ephy_led2),
298 PINCTRL_PIN_GROUP("ephy_led3", mt7629_ephy_led3),
299 PINCTRL_PIN_GROUP("ephy_led4", mt7629_ephy_led4),
300 PINCTRL_PIN_GROUP("wf2g_led", mt7629_wf2g_led),
301 PINCTRL_PIN_GROUP("wf5g_led", mt7629_wf5g_led),
302 PINCTRL_PIN_GROUP("watchdog", mt7629_watchdog),
303 PINCTRL_PIN_GROUP("gphy_leds_0", mt7629_gphy_leds_0),
304 PINCTRL_PIN_GROUP("gphy_led1_0", mt7629_gphy_led1_0),
305 PINCTRL_PIN_GROUP("gphy_led2_0", mt7629_gphy_led2_0),
306 PINCTRL_PIN_GROUP("gphy_led3_0", mt7629_gphy_led3_0),
307 PINCTRL_PIN_GROUP("gphy_leds_1", mt7629_gphy_leds_1),
308 PINCTRL_PIN_GROUP("gphy_led1_1", mt7629_gphy_led1_1),
309 PINCTRL_PIN_GROUP("gphy_led2_1", mt7629_gphy_led2_1),
310 PINCTRL_PIN_GROUP("gphy_led3_1", mt7629_gphy_led3_1),
311 PINCTRL_PIN_GROUP("i2c_0", mt7629_i2c_0),
312 PINCTRL_PIN_GROUP("i2c_1", mt7629_i2c_1),
313 PINCTRL_PIN_GROUP("spi_0", mt7629_spi_0),
314 PINCTRL_PIN_GROUP("spi_1", mt7629_spi_1),
315 PINCTRL_PIN_GROUP("spi_wp", mt7629_spi_wp),
316 PINCTRL_PIN_GROUP("spi_hold", mt7629_spi_hold),
317 PINCTRL_PIN_GROUP("uart1_0_txd_rxd", mt7629_uart1_0_txd_rxd),
318 PINCTRL_PIN_GROUP("uart1_1_txd_rxd", mt7629_uart1_1_txd_rxd),
319 PINCTRL_PIN_GROUP("uart2_0_txd_rxd", mt7629_uart2_0_txd_rxd),
320 PINCTRL_PIN_GROUP("uart2_1_txd_rxd", mt7629_uart2_1_txd_rxd),
321 PINCTRL_PIN_GROUP("uart1_0_cts_rts", mt7629_uart1_0_cts_rts),
322 PINCTRL_PIN_GROUP("uart1_1_cts_rts", mt7629_uart1_1_cts_rts),
323 PINCTRL_PIN_GROUP("uart2_0_cts_rts", mt7629_uart2_0_cts_rts),
324 PINCTRL_PIN_GROUP("uart2_1_cts_rts", mt7629_uart2_1_cts_rts),
325 PINCTRL_PIN_GROUP("uart0_txd_rxd", mt7629_uart0_txd_rxd),
326 PINCTRL_PIN_GROUP("mdc_mdio", mt7629_mdc_mdio),
327 PINCTRL_PIN_GROUP("pcie_pereset", mt7629_pcie_pereset),
328 PINCTRL_PIN_GROUP("pcie_wake", mt7629_pcie_wake),
329 PINCTRL_PIN_GROUP("pcie_clkreq", mt7629_pcie_clkreq),
330 PINCTRL_PIN_GROUP("pwm_0", mt7629_pwm_0),
331 PINCTRL_PIN_GROUP("pwm_1", mt7629_pwm_1),
332 PINCTRL_PIN_GROUP("wf0_2g", mt7629_wf0_2g),
333 PINCTRL_PIN_GROUP("snfi", mt7629_snfi),
334 PINCTRL_PIN_GROUP("spi_nor", mt7629_snor),
335 };
336
337 /* Joint those groups owning the same capability in user point of view which
338 * allows that people tend to use through the device tree.
339 */
340 static const char *const mt7629_ethernet_groups[] = { "mdc_mdio", };
341 static const char *const mt7629_i2c_groups[] = { "i2c_0", "i2c_1", };
342 static const char *const mt7629_led_groups[] = { "ephy_leds", "ephy_led0",
343 "ephy_led1", "ephy_led2",
344 "ephy_led3", "ephy_led4",
345 "wf2g_led", "wf5g_led",
346 "gphy_leds_0", "gphy_led1_0",
347 "gphy_led2_0", "gphy_led3_0",
348 "gphy_leds_1", "gphy_led1_1",
349 "gphy_led2_1", "gphy_led3_1",};
350 static const char *const mt7629_pcie_groups[] = { "pcie_pereset", "pcie_wake",
351 "pcie_clkreq", };
352 static const char *const mt7629_pwm_groups[] = { "pwm_0", "pwm_1", };
353 static const char *const mt7629_spi_groups[] = { "spi_0", "spi_1", "spi_wp",
354 "spi_hold", };
355 static const char *const mt7629_uart_groups[] = { "uart1_0_txd_rxd",
356 "uart1_1_txd_rxd",
357 "uart2_0_txd_rxd",
358 "uart2_1_txd_rxd",
359 "uart1_0_cts_rts",
360 "uart1_1_cts_rts",
361 "uart2_0_cts_rts",
362 "uart2_1_cts_rts",
363 "uart0_txd_rxd", };
364 static const char *const mt7629_wdt_groups[] = { "watchdog", };
365 static const char *const mt7629_wifi_groups[] = { "wf0_5g", "wf0_2g", };
366 static const char *const mt7629_flash_groups[] = { "snfi", "spi_nor" };
367
368 static const struct mtk_function_desc mt7629_functions[] = {
369 {"eth", mt7629_ethernet_groups, ARRAY_SIZE(mt7629_ethernet_groups)},
370 {"i2c", mt7629_i2c_groups, ARRAY_SIZE(mt7629_i2c_groups)},
371 {"led", mt7629_led_groups, ARRAY_SIZE(mt7629_led_groups)},
372 {"pcie", mt7629_pcie_groups, ARRAY_SIZE(mt7629_pcie_groups)},
373 {"pwm", mt7629_pwm_groups, ARRAY_SIZE(mt7629_pwm_groups)},
374 {"spi", mt7629_spi_groups, ARRAY_SIZE(mt7629_spi_groups)},
375 {"uart", mt7629_uart_groups, ARRAY_SIZE(mt7629_uart_groups)},
376 {"watchdog", mt7629_wdt_groups, ARRAY_SIZE(mt7629_wdt_groups)},
377 {"wifi", mt7629_wifi_groups, ARRAY_SIZE(mt7629_wifi_groups)},
378 {"flash", mt7629_flash_groups, ARRAY_SIZE(mt7629_flash_groups)},
379 };
380
381 static struct mtk_pinctrl_soc mt7629_data = {
382 .name = "mt7629_pinctrl",
383 .reg_cal = mt7629_reg_cals,
384 .pins = mt7629_pins,
385 .npins = ARRAY_SIZE(mt7629_pins),
386 .grps = mt7629_groups,
387 .ngrps = ARRAY_SIZE(mt7629_groups),
388 .funcs = mt7629_functions,
389 .nfuncs = ARRAY_SIZE(mt7629_functions),
390 };
391
mtk_pinctrl_mt7629_probe(struct udevice * dev)392 static int mtk_pinctrl_mt7629_probe(struct udevice *dev)
393 {
394 return mtk_pinctrl_common_probe(dev, &mt7629_data);
395 }
396
397 static const struct udevice_id mt7629_pctrl_match[] = {
398 { .compatible = "mediatek,mt7629-pinctrl" },
399 { /* sentinel */ }
400 };
401
402 U_BOOT_DRIVER(mt7629_pinctrl) = {
403 .name = "mt7629_pinctrl",
404 .id = UCLASS_PINCTRL,
405 .of_match = mt7629_pctrl_match,
406 .ops = &mtk_pinctrl_ops,
407 .probe = mtk_pinctrl_mt7629_probe,
408 .priv_auto_alloc_size = sizeof(struct mtk_pinctrl_priv),
409 };
410