1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * MediaTek Pinctrl Paris Driver, which implement the vendor per-pin
4  * bindings for MediaTek SoC.
5  *
6  * Copyright (C) 2018 MediaTek Inc.
7  * Author: Sean Wang <sean.wang@mediatek.com>
8  *	   Zhiyong Tao <zhiyong.tao@mediatek.com>
9  *	   Hongzhou.Yang <hongzhou.yang@mediatek.com>
10  */
11 
12 #include <linux/gpio/driver.h>
13 #include <linux/module.h>
14 #include <linux/seq_file.h>
15 
16 #include <linux/pinctrl/consumer.h>
17 
18 #include <dt-bindings/pinctrl/mt65xx.h>
19 
20 #include "pinctrl-paris.h"
21 
22 #define PINCTRL_PINCTRL_DEV	KBUILD_MODNAME
23 
24 /* Custom pinconf parameters */
25 #define MTK_PIN_CONFIG_TDSEL	(PIN_CONFIG_END + 1)
26 #define MTK_PIN_CONFIG_RDSEL	(PIN_CONFIG_END + 2)
27 #define MTK_PIN_CONFIG_PU_ADV	(PIN_CONFIG_END + 3)
28 #define MTK_PIN_CONFIG_PD_ADV	(PIN_CONFIG_END + 4)
29 #define MTK_PIN_CONFIG_DRV_ADV	(PIN_CONFIG_END + 5)
30 
31 static const struct pinconf_generic_params mtk_custom_bindings[] = {
32 	{"mediatek,tdsel",	MTK_PIN_CONFIG_TDSEL,		0},
33 	{"mediatek,rdsel",	MTK_PIN_CONFIG_RDSEL,		0},
34 	{"mediatek,pull-up-adv", MTK_PIN_CONFIG_PU_ADV,		1},
35 	{"mediatek,pull-down-adv", MTK_PIN_CONFIG_PD_ADV,	1},
36 	{"mediatek,drive-strength-adv", MTK_PIN_CONFIG_DRV_ADV,	2},
37 };
38 
39 #ifdef CONFIG_DEBUG_FS
40 static const struct pin_config_item mtk_conf_items[] = {
41 	PCONFDUMP(MTK_PIN_CONFIG_TDSEL, "tdsel", NULL, true),
42 	PCONFDUMP(MTK_PIN_CONFIG_RDSEL, "rdsel", NULL, true),
43 	PCONFDUMP(MTK_PIN_CONFIG_PU_ADV, "pu-adv", NULL, true),
44 	PCONFDUMP(MTK_PIN_CONFIG_PD_ADV, "pd-adv", NULL, true),
45 	PCONFDUMP(MTK_PIN_CONFIG_DRV_ADV, "drive-strength-adv", NULL, true),
46 };
47 #endif
48 
49 static const char * const mtk_gpio_functions[] = {
50 	"func0", "func1", "func2", "func3",
51 	"func4", "func5", "func6", "func7",
52 	"func8", "func9", "func10", "func11",
53 	"func12", "func13", "func14", "func15",
54 };
55 
56 /*
57  * This section supports converting to/from custom MTK_PIN_CONFIG_DRV_ADV
58  * and standard PIN_CONFIG_DRIVE_STRENGTH_UA pin configs.
59  *
60  * The custom value encodes three hardware bits as follows:
61  *
62  *   |           Bits           |
63  *   | 2 (E1) | 1 (E0) | 0 (EN) | drive strength (uA)
64  *   ------------------------------------------------
65  *   |    x   |    x   |    0   | disabled, use standard drive strength
66  *   -------------------------------------
67  *   |    0   |    0   |    1   |  125 uA
68  *   |    0   |    1   |    1   |  250 uA
69  *   |    1   |    0   |    1   |  500 uA
70  *   |    1   |    1   |    1   | 1000 uA
71  */
72 static const int mtk_drv_adv_uA[] = { 125, 250, 500, 1000 };
73 
mtk_drv_adv_to_uA(int val)74 static int mtk_drv_adv_to_uA(int val)
75 {
76 	/* This should never happen. */
77 	if (WARN_ON_ONCE(val < 0 || val > 7))
78 		return -EINVAL;
79 
80 	/* Bit 0 simply enables this hardware part */
81 	if (!(val & BIT(0)))
82 		return -EINVAL;
83 
84 	return mtk_drv_adv_uA[(val >> 1)];
85 }
86 
mtk_drv_uA_to_adv(int val)87 static int mtk_drv_uA_to_adv(int val)
88 {
89 	switch (val) {
90 	case 125:
91 		return 0x1;
92 	case 250:
93 		return 0x3;
94 	case 500:
95 		return 0x5;
96 	case 1000:
97 		return 0x7;
98 	}
99 
100 	return -EINVAL;
101 }
102 
mtk_pinmux_gpio_request_enable(struct pinctrl_dev * pctldev,struct pinctrl_gpio_range * range,unsigned int pin)103 static int mtk_pinmux_gpio_request_enable(struct pinctrl_dev *pctldev,
104 					  struct pinctrl_gpio_range *range,
105 					  unsigned int pin)
106 {
107 	struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
108 	const struct mtk_pin_desc *desc;
109 
110 	desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
111 
112 	return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_MODE,
113 				hw->soc->gpio_m);
114 }
115 
mtk_pinmux_gpio_set_direction(struct pinctrl_dev * pctldev,struct pinctrl_gpio_range * range,unsigned int pin,bool input)116 static int mtk_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev,
117 					 struct pinctrl_gpio_range *range,
118 					 unsigned int pin, bool input)
119 {
120 	struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
121 	const struct mtk_pin_desc *desc;
122 
123 	desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
124 
125 	/* hardware would take 0 as input direction */
126 	return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR, !input);
127 }
128 
mtk_pinconf_get(struct pinctrl_dev * pctldev,unsigned int pin,unsigned long * config)129 static int mtk_pinconf_get(struct pinctrl_dev *pctldev,
130 			   unsigned int pin, unsigned long *config)
131 {
132 	struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
133 	u32 param = pinconf_to_config_param(*config);
134 	int pullup, reg, err = -ENOTSUPP, ret = 1;
135 	const struct mtk_pin_desc *desc;
136 
137 	if (pin >= hw->soc->npins)
138 		return -EINVAL;
139 
140 	desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
141 
142 	switch (param) {
143 	case PIN_CONFIG_BIAS_DISABLE:
144 	case PIN_CONFIG_BIAS_PULL_UP:
145 	case PIN_CONFIG_BIAS_PULL_DOWN:
146 		if (!hw->soc->bias_get_combo)
147 			break;
148 		err = hw->soc->bias_get_combo(hw, desc, &pullup, &ret);
149 		if (err)
150 			break;
151 		if (ret == MTK_PUPD_SET_R1R0_00)
152 			ret = MTK_DISABLE;
153 		if (param == PIN_CONFIG_BIAS_DISABLE) {
154 			if (ret != MTK_DISABLE)
155 				err = -EINVAL;
156 		} else if (param == PIN_CONFIG_BIAS_PULL_UP) {
157 			if (!pullup || ret == MTK_DISABLE)
158 				err = -EINVAL;
159 		} else if (param == PIN_CONFIG_BIAS_PULL_DOWN) {
160 			if (pullup || ret == MTK_DISABLE)
161 				err = -EINVAL;
162 		}
163 		break;
164 	case PIN_CONFIG_SLEW_RATE:
165 		err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_SR, &ret);
166 		break;
167 	case PIN_CONFIG_INPUT_ENABLE:
168 		err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_IES, &ret);
169 		if (!ret)
170 			err = -EINVAL;
171 		break;
172 	case PIN_CONFIG_OUTPUT:
173 		err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DIR, &ret);
174 		if (err)
175 			break;
176 
177 		if (!ret) {
178 			err = -EINVAL;
179 			break;
180 		}
181 
182 		err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DO, &ret);
183 		break;
184 	case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
185 		err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DIR, &ret);
186 		if (err)
187 			break;
188 		/* return error when in output mode
189 		 * because schmitt trigger only work in input mode
190 		 */
191 		if (ret) {
192 			err = -EINVAL;
193 			break;
194 		}
195 
196 		err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_SMT, &ret);
197 		if (!ret)
198 			err = -EINVAL;
199 		break;
200 	case PIN_CONFIG_DRIVE_STRENGTH:
201 		if (!hw->soc->drive_get)
202 			break;
203 
204 		if (hw->soc->adv_drive_get) {
205 			err = hw->soc->adv_drive_get(hw, desc, &ret);
206 			if (!err) {
207 				err = mtk_drv_adv_to_uA(ret);
208 				if (err > 0) {
209 					/* PIN_CONFIG_DRIVE_STRENGTH_UA used */
210 					err = -EINVAL;
211 					break;
212 				}
213 			}
214 		}
215 
216 		err = hw->soc->drive_get(hw, desc, &ret);
217 		break;
218 	case PIN_CONFIG_DRIVE_STRENGTH_UA:
219 		if (!hw->soc->adv_drive_get)
220 			break;
221 
222 		err = hw->soc->adv_drive_get(hw, desc, &ret);
223 		if (err)
224 			break;
225 		err = mtk_drv_adv_to_uA(ret);
226 		if (err < 0)
227 			break;
228 
229 		ret = err;
230 		err = 0;
231 		break;
232 	case MTK_PIN_CONFIG_TDSEL:
233 	case MTK_PIN_CONFIG_RDSEL:
234 		reg = (param == MTK_PIN_CONFIG_TDSEL) ?
235 		       PINCTRL_PIN_REG_TDSEL : PINCTRL_PIN_REG_RDSEL;
236 		err = mtk_hw_get_value(hw, desc, reg, &ret);
237 		break;
238 	case MTK_PIN_CONFIG_PU_ADV:
239 	case MTK_PIN_CONFIG_PD_ADV:
240 		if (!hw->soc->adv_pull_get)
241 			break;
242 		pullup = param == MTK_PIN_CONFIG_PU_ADV;
243 		err = hw->soc->adv_pull_get(hw, desc, pullup, &ret);
244 		break;
245 	case MTK_PIN_CONFIG_DRV_ADV:
246 		if (!hw->soc->adv_drive_get)
247 			break;
248 		err = hw->soc->adv_drive_get(hw, desc, &ret);
249 		break;
250 	}
251 
252 	if (!err)
253 		*config = pinconf_to_config_packed(param, ret);
254 
255 	return err;
256 }
257 
mtk_pinconf_set(struct pinctrl_dev * pctldev,unsigned int pin,enum pin_config_param param,u32 arg)258 static int mtk_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
259 			   enum pin_config_param param, u32 arg)
260 {
261 	struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
262 	const struct mtk_pin_desc *desc;
263 	int err = -ENOTSUPP;
264 	u32 reg;
265 
266 	if (pin >= hw->soc->npins)
267 		return -EINVAL;
268 
269 	desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
270 
271 	switch ((u32)param) {
272 	case PIN_CONFIG_BIAS_DISABLE:
273 		if (!hw->soc->bias_set_combo)
274 			break;
275 		err = hw->soc->bias_set_combo(hw, desc, 0, MTK_DISABLE);
276 		break;
277 	case PIN_CONFIG_BIAS_PULL_UP:
278 		if (!hw->soc->bias_set_combo)
279 			break;
280 		err = hw->soc->bias_set_combo(hw, desc, 1, arg);
281 		break;
282 	case PIN_CONFIG_BIAS_PULL_DOWN:
283 		if (!hw->soc->bias_set_combo)
284 			break;
285 		err = hw->soc->bias_set_combo(hw, desc, 0, arg);
286 		break;
287 	case PIN_CONFIG_INPUT_ENABLE:
288 		/* regard all non-zero value as enable */
289 		err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_IES, !!arg);
290 		break;
291 	case PIN_CONFIG_SLEW_RATE:
292 		/* regard all non-zero value as enable */
293 		err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SR, !!arg);
294 		break;
295 	case PIN_CONFIG_OUTPUT:
296 		err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DO,
297 				       arg);
298 		if (err)
299 			break;
300 
301 		err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR,
302 				       MTK_OUTPUT);
303 		break;
304 	case PIN_CONFIG_INPUT_SCHMITT:
305 	case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
306 		/* arg = 1: Input mode & SMT enable ;
307 		 * arg = 0: Output mode & SMT disable
308 		 */
309 		err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR, !arg);
310 		if (err)
311 			break;
312 
313 		err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SMT, !!arg);
314 		break;
315 	case PIN_CONFIG_DRIVE_STRENGTH:
316 		if (!hw->soc->drive_set)
317 			break;
318 		err = hw->soc->drive_set(hw, desc, arg);
319 		break;
320 	case PIN_CONFIG_DRIVE_STRENGTH_UA:
321 		if (!hw->soc->adv_drive_set)
322 			break;
323 
324 		err = mtk_drv_uA_to_adv(arg);
325 		if (err < 0)
326 			break;
327 		err = hw->soc->adv_drive_set(hw, desc, err);
328 		break;
329 	case MTK_PIN_CONFIG_TDSEL:
330 	case MTK_PIN_CONFIG_RDSEL:
331 		reg = (param == MTK_PIN_CONFIG_TDSEL) ?
332 		       PINCTRL_PIN_REG_TDSEL : PINCTRL_PIN_REG_RDSEL;
333 		err = mtk_hw_set_value(hw, desc, reg, arg);
334 		break;
335 	case MTK_PIN_CONFIG_PU_ADV:
336 	case MTK_PIN_CONFIG_PD_ADV:
337 		if (!hw->soc->adv_pull_set)
338 			break;
339 		err = hw->soc->adv_pull_set(hw, desc,
340 					    (param == MTK_PIN_CONFIG_PU_ADV),
341 					    arg);
342 		break;
343 	case MTK_PIN_CONFIG_DRV_ADV:
344 		if (!hw->soc->adv_drive_set)
345 			break;
346 		err = hw->soc->adv_drive_set(hw, desc, arg);
347 		break;
348 	}
349 
350 	return err;
351 }
352 
353 static struct mtk_pinctrl_group *
mtk_pctrl_find_group_by_pin(struct mtk_pinctrl * hw,u32 pin)354 mtk_pctrl_find_group_by_pin(struct mtk_pinctrl *hw, u32 pin)
355 {
356 	int i;
357 
358 	for (i = 0; i < hw->soc->ngrps; i++) {
359 		struct mtk_pinctrl_group *grp = hw->groups + i;
360 
361 		if (grp->pin == pin)
362 			return grp;
363 	}
364 
365 	return NULL;
366 }
367 
368 static const struct mtk_func_desc *
mtk_pctrl_find_function_by_pin(struct mtk_pinctrl * hw,u32 pin_num,u32 fnum)369 mtk_pctrl_find_function_by_pin(struct mtk_pinctrl *hw, u32 pin_num, u32 fnum)
370 {
371 	const struct mtk_pin_desc *pin = hw->soc->pins + pin_num;
372 	const struct mtk_func_desc *func = pin->funcs;
373 
374 	while (func && func->name) {
375 		if (func->muxval == fnum)
376 			return func;
377 		func++;
378 	}
379 
380 	return NULL;
381 }
382 
mtk_pctrl_is_function_valid(struct mtk_pinctrl * hw,u32 pin_num,u32 fnum)383 static bool mtk_pctrl_is_function_valid(struct mtk_pinctrl *hw, u32 pin_num,
384 					u32 fnum)
385 {
386 	int i;
387 
388 	for (i = 0; i < hw->soc->npins; i++) {
389 		const struct mtk_pin_desc *pin = hw->soc->pins + i;
390 
391 		if (pin->number == pin_num) {
392 			const struct mtk_func_desc *func = pin->funcs;
393 
394 			while (func && func->name) {
395 				if (func->muxval == fnum)
396 					return true;
397 				func++;
398 			}
399 
400 			break;
401 		}
402 	}
403 
404 	return false;
405 }
406 
mtk_pctrl_dt_node_to_map_func(struct mtk_pinctrl * pctl,u32 pin,u32 fnum,struct mtk_pinctrl_group * grp,struct pinctrl_map ** map,unsigned * reserved_maps,unsigned * num_maps)407 static int mtk_pctrl_dt_node_to_map_func(struct mtk_pinctrl *pctl,
408 					 u32 pin, u32 fnum,
409 					 struct mtk_pinctrl_group *grp,
410 					 struct pinctrl_map **map,
411 					 unsigned *reserved_maps,
412 					 unsigned *num_maps)
413 {
414 	bool ret;
415 
416 	if (*num_maps == *reserved_maps)
417 		return -ENOSPC;
418 
419 	(*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
420 	(*map)[*num_maps].data.mux.group = grp->name;
421 
422 	ret = mtk_pctrl_is_function_valid(pctl, pin, fnum);
423 	if (!ret) {
424 		dev_err(pctl->dev, "invalid function %d on pin %d .\n",
425 			fnum, pin);
426 		return -EINVAL;
427 	}
428 
429 	(*map)[*num_maps].data.mux.function = mtk_gpio_functions[fnum];
430 	(*num_maps)++;
431 
432 	return 0;
433 }
434 
mtk_pctrl_dt_subnode_to_map(struct pinctrl_dev * pctldev,struct device_node * node,struct pinctrl_map ** map,unsigned * reserved_maps,unsigned * num_maps)435 static int mtk_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
436 				       struct device_node *node,
437 				       struct pinctrl_map **map,
438 				       unsigned *reserved_maps,
439 				       unsigned *num_maps)
440 {
441 	struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
442 	int num_pins, num_funcs, maps_per_pin, i, err;
443 	struct mtk_pinctrl_group *grp;
444 	unsigned int num_configs;
445 	bool has_config = false;
446 	unsigned long *configs;
447 	u32 pinfunc, pin, func;
448 	struct property *pins;
449 	unsigned reserve = 0;
450 
451 	pins = of_find_property(node, "pinmux", NULL);
452 	if (!pins) {
453 		dev_err(hw->dev, "missing pins property in node %pOFn .\n",
454 			node);
455 		return -EINVAL;
456 	}
457 
458 	err = pinconf_generic_parse_dt_config(node, pctldev, &configs,
459 					      &num_configs);
460 	if (err)
461 		return err;
462 
463 	if (num_configs)
464 		has_config = true;
465 
466 	num_pins = pins->length / sizeof(u32);
467 	num_funcs = num_pins;
468 	maps_per_pin = 0;
469 	if (num_funcs)
470 		maps_per_pin++;
471 	if (has_config && num_pins >= 1)
472 		maps_per_pin++;
473 
474 	if (!num_pins || !maps_per_pin) {
475 		err = -EINVAL;
476 		goto exit;
477 	}
478 
479 	reserve = num_pins * maps_per_pin;
480 
481 	err = pinctrl_utils_reserve_map(pctldev, map, reserved_maps, num_maps,
482 					reserve);
483 	if (err < 0)
484 		goto exit;
485 
486 	for (i = 0; i < num_pins; i++) {
487 		err = of_property_read_u32_index(node, "pinmux", i, &pinfunc);
488 		if (err)
489 			goto exit;
490 
491 		pin = MTK_GET_PIN_NO(pinfunc);
492 		func = MTK_GET_PIN_FUNC(pinfunc);
493 
494 		if (pin >= hw->soc->npins ||
495 		    func >= ARRAY_SIZE(mtk_gpio_functions)) {
496 			dev_err(hw->dev, "invalid pins value.\n");
497 			err = -EINVAL;
498 			goto exit;
499 		}
500 
501 		grp = mtk_pctrl_find_group_by_pin(hw, pin);
502 		if (!grp) {
503 			dev_err(hw->dev, "unable to match pin %d to group\n",
504 				pin);
505 			err = -EINVAL;
506 			goto exit;
507 		}
508 
509 		err = mtk_pctrl_dt_node_to_map_func(hw, pin, func, grp, map,
510 						    reserved_maps, num_maps);
511 		if (err < 0)
512 			goto exit;
513 
514 		if (has_config) {
515 			err = pinctrl_utils_add_map_configs(pctldev, map,
516 							    reserved_maps,
517 							    num_maps,
518 							    grp->name,
519 							    configs,
520 							    num_configs,
521 							    PIN_MAP_TYPE_CONFIGS_GROUP);
522 			if (err < 0)
523 				goto exit;
524 		}
525 	}
526 
527 	err = 0;
528 
529 exit:
530 	kfree(configs);
531 	return err;
532 }
533 
mtk_pctrl_dt_node_to_map(struct pinctrl_dev * pctldev,struct device_node * np_config,struct pinctrl_map ** map,unsigned * num_maps)534 static int mtk_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
535 				    struct device_node *np_config,
536 				    struct pinctrl_map **map,
537 				    unsigned *num_maps)
538 {
539 	struct device_node *np;
540 	unsigned reserved_maps;
541 	int ret;
542 
543 	*map = NULL;
544 	*num_maps = 0;
545 	reserved_maps = 0;
546 
547 	for_each_child_of_node(np_config, np) {
548 		ret = mtk_pctrl_dt_subnode_to_map(pctldev, np, map,
549 						  &reserved_maps,
550 						  num_maps);
551 		if (ret < 0) {
552 			pinctrl_utils_free_map(pctldev, *map, *num_maps);
553 			of_node_put(np);
554 			return ret;
555 		}
556 	}
557 
558 	return 0;
559 }
560 
mtk_pctrl_get_groups_count(struct pinctrl_dev * pctldev)561 static int mtk_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
562 {
563 	struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
564 
565 	return hw->soc->ngrps;
566 }
567 
mtk_pctrl_get_group_name(struct pinctrl_dev * pctldev,unsigned group)568 static const char *mtk_pctrl_get_group_name(struct pinctrl_dev *pctldev,
569 					    unsigned group)
570 {
571 	struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
572 
573 	return hw->groups[group].name;
574 }
575 
mtk_pctrl_get_group_pins(struct pinctrl_dev * pctldev,unsigned group,const unsigned ** pins,unsigned * num_pins)576 static int mtk_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
577 				    unsigned group, const unsigned **pins,
578 				    unsigned *num_pins)
579 {
580 	struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
581 
582 	*pins = (unsigned *)&hw->groups[group].pin;
583 	*num_pins = 1;
584 
585 	return 0;
586 }
587 
mtk_hw_get_value_wrap(struct mtk_pinctrl * hw,unsigned int gpio,int field)588 static int mtk_hw_get_value_wrap(struct mtk_pinctrl *hw, unsigned int gpio, int field)
589 {
590 	const struct mtk_pin_desc *desc;
591 	int value, err;
592 
593 	if (gpio >= hw->soc->npins)
594 		return -EINVAL;
595 
596 	desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio];
597 
598 	err = mtk_hw_get_value(hw, desc, field, &value);
599 	if (err)
600 		return err;
601 
602 	return value;
603 }
604 
605 #define mtk_pctrl_get_pinmux(hw, gpio)			\
606 	mtk_hw_get_value_wrap(hw, gpio, PINCTRL_PIN_REG_MODE)
607 
608 #define mtk_pctrl_get_direction(hw, gpio)		\
609 	mtk_hw_get_value_wrap(hw, gpio, PINCTRL_PIN_REG_DIR)
610 
611 #define mtk_pctrl_get_out(hw, gpio)			\
612 	mtk_hw_get_value_wrap(hw, gpio, PINCTRL_PIN_REG_DO)
613 
614 #define mtk_pctrl_get_in(hw, gpio)			\
615 	mtk_hw_get_value_wrap(hw, gpio, PINCTRL_PIN_REG_DI)
616 
617 #define mtk_pctrl_get_smt(hw, gpio)			\
618 	mtk_hw_get_value_wrap(hw, gpio, PINCTRL_PIN_REG_SMT)
619 
620 #define mtk_pctrl_get_ies(hw, gpio)			\
621 	mtk_hw_get_value_wrap(hw, gpio, PINCTRL_PIN_REG_IES)
622 
623 #define mtk_pctrl_get_driving(hw, gpio)			\
624 	mtk_hw_get_value_wrap(hw, gpio, PINCTRL_PIN_REG_DRV)
625 
mtk_pctrl_show_one_pin(struct mtk_pinctrl * hw,unsigned int gpio,char * buf,unsigned int buf_len)626 ssize_t mtk_pctrl_show_one_pin(struct mtk_pinctrl *hw,
627 	unsigned int gpio, char *buf, unsigned int buf_len)
628 {
629 	int pinmux, pullup = 0, pullen = 0, len = 0, r1 = -1, r0 = -1, rsel = -1;
630 	const struct mtk_pin_desc *desc;
631 	u32 try_all_type = 0;
632 
633 	if (gpio >= hw->soc->npins)
634 		return -EINVAL;
635 
636 	if (mtk_is_virt_gpio(hw, gpio))
637 		return -EINVAL;
638 
639 	desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio];
640 	pinmux = mtk_pctrl_get_pinmux(hw, gpio);
641 	if (pinmux >= hw->soc->nfuncs)
642 		pinmux -= hw->soc->nfuncs;
643 
644 	mtk_pinconf_bias_get_combo(hw, desc, &pullup, &pullen);
645 
646 	if (hw->soc->pull_type)
647 		try_all_type = hw->soc->pull_type[desc->number];
648 
649 	if (hw->rsel_si_unit && (try_all_type & MTK_PULL_RSEL_TYPE)) {
650 		rsel = pullen;
651 		pullen = 1;
652 	} else {
653 		/* Case for: R1R0 */
654 		if (pullen == MTK_PUPD_SET_R1R0_00) {
655 			pullen = 0;
656 			r1 = 0;
657 			r0 = 0;
658 		} else if (pullen == MTK_PUPD_SET_R1R0_01) {
659 			pullen = 1;
660 			r1 = 0;
661 			r0 = 1;
662 		} else if (pullen == MTK_PUPD_SET_R1R0_10) {
663 			pullen = 1;
664 			r1 = 1;
665 			r0 = 0;
666 		} else if (pullen == MTK_PUPD_SET_R1R0_11) {
667 			pullen = 1;
668 			r1 = 1;
669 			r0 = 1;
670 		}
671 
672 		/* Case for: RSEL */
673 		if (pullen >= MTK_PULL_SET_RSEL_000 &&
674 		    pullen <= MTK_PULL_SET_RSEL_111) {
675 			rsel = pullen - MTK_PULL_SET_RSEL_000;
676 			pullen = 1;
677 		}
678 	}
679 	len += scnprintf(buf + len, buf_len - len,
680 			"%03d: %1d%1d%1d%1d%02d%1d%1d%1d%1d",
681 			gpio,
682 			pinmux,
683 			mtk_pctrl_get_direction(hw, gpio),
684 			mtk_pctrl_get_out(hw, gpio),
685 			mtk_pctrl_get_in(hw, gpio),
686 			mtk_pctrl_get_driving(hw, gpio),
687 			mtk_pctrl_get_smt(hw, gpio),
688 			mtk_pctrl_get_ies(hw, gpio),
689 			pullen,
690 			pullup);
691 
692 	if (r1 != -1)
693 		len += scnprintf(buf + len, buf_len - len, " (%1d %1d)", r1, r0);
694 	else if (rsel != -1)
695 		len += scnprintf(buf + len, buf_len - len, " (%1d)", rsel);
696 
697 	return len;
698 }
699 EXPORT_SYMBOL_GPL(mtk_pctrl_show_one_pin);
700 
701 #define PIN_DBG_BUF_SZ 96
mtk_pctrl_dbg_show(struct pinctrl_dev * pctldev,struct seq_file * s,unsigned int gpio)702 static void mtk_pctrl_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
703 			  unsigned int gpio)
704 {
705 	struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
706 	char buf[PIN_DBG_BUF_SZ] = { 0 };
707 
708 	(void)mtk_pctrl_show_one_pin(hw, gpio, buf, PIN_DBG_BUF_SZ);
709 
710 	seq_printf(s, "%s", buf);
711 }
712 
713 static const struct pinctrl_ops mtk_pctlops = {
714 	.dt_node_to_map		= mtk_pctrl_dt_node_to_map,
715 	.dt_free_map		= pinctrl_utils_free_map,
716 	.get_groups_count	= mtk_pctrl_get_groups_count,
717 	.get_group_name		= mtk_pctrl_get_group_name,
718 	.get_group_pins		= mtk_pctrl_get_group_pins,
719 	.pin_dbg_show           = mtk_pctrl_dbg_show,
720 };
721 
mtk_pmx_get_funcs_cnt(struct pinctrl_dev * pctldev)722 static int mtk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
723 {
724 	return ARRAY_SIZE(mtk_gpio_functions);
725 }
726 
mtk_pmx_get_func_name(struct pinctrl_dev * pctldev,unsigned selector)727 static const char *mtk_pmx_get_func_name(struct pinctrl_dev *pctldev,
728 					 unsigned selector)
729 {
730 	return mtk_gpio_functions[selector];
731 }
732 
mtk_pmx_get_func_groups(struct pinctrl_dev * pctldev,unsigned function,const char * const ** groups,unsigned * const num_groups)733 static int mtk_pmx_get_func_groups(struct pinctrl_dev *pctldev,
734 				   unsigned function,
735 				   const char * const **groups,
736 				   unsigned * const num_groups)
737 {
738 	struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
739 
740 	*groups = hw->grp_names;
741 	*num_groups = hw->soc->ngrps;
742 
743 	return 0;
744 }
745 
mtk_pmx_set_mux(struct pinctrl_dev * pctldev,unsigned function,unsigned group)746 static int mtk_pmx_set_mux(struct pinctrl_dev *pctldev,
747 			   unsigned function,
748 			   unsigned group)
749 {
750 	struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
751 	struct mtk_pinctrl_group *grp = hw->groups + group;
752 	const struct mtk_func_desc *desc_func;
753 	const struct mtk_pin_desc *desc;
754 	bool ret;
755 
756 	ret = mtk_pctrl_is_function_valid(hw, grp->pin, function);
757 	if (!ret) {
758 		dev_err(hw->dev, "invalid function %d on group %d .\n",
759 			function, group);
760 		return -EINVAL;
761 	}
762 
763 	desc_func = mtk_pctrl_find_function_by_pin(hw, grp->pin, function);
764 	if (!desc_func)
765 		return -EINVAL;
766 
767 	desc = (const struct mtk_pin_desc *)&hw->soc->pins[grp->pin];
768 	mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_MODE, desc_func->muxval);
769 
770 	return 0;
771 }
772 
773 static const struct pinmux_ops mtk_pmxops = {
774 	.get_functions_count	= mtk_pmx_get_funcs_cnt,
775 	.get_function_name	= mtk_pmx_get_func_name,
776 	.get_function_groups	= mtk_pmx_get_func_groups,
777 	.set_mux		= mtk_pmx_set_mux,
778 	.gpio_set_direction	= mtk_pinmux_gpio_set_direction,
779 	.gpio_request_enable	= mtk_pinmux_gpio_request_enable,
780 };
781 
mtk_pconf_group_get(struct pinctrl_dev * pctldev,unsigned group,unsigned long * config)782 static int mtk_pconf_group_get(struct pinctrl_dev *pctldev, unsigned group,
783 			       unsigned long *config)
784 {
785 	struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
786 	struct mtk_pinctrl_group *grp = &hw->groups[group];
787 
788 	 /* One pin per group only */
789 	return mtk_pinconf_get(pctldev, grp->pin, config);
790 }
791 
mtk_pconf_group_set(struct pinctrl_dev * pctldev,unsigned group,unsigned long * configs,unsigned num_configs)792 static int mtk_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group,
793 			       unsigned long *configs, unsigned num_configs)
794 {
795 	struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
796 	struct mtk_pinctrl_group *grp = &hw->groups[group];
797 	bool drive_strength_uA_found = false;
798 	bool adv_drve_strength_found = false;
799 	int i, ret;
800 
801 	for (i = 0; i < num_configs; i++) {
802 		ret = mtk_pinconf_set(pctldev, grp->pin,
803 				      pinconf_to_config_param(configs[i]),
804 				      pinconf_to_config_argument(configs[i]));
805 		if (ret < 0)
806 			return ret;
807 
808 		if (pinconf_to_config_param(configs[i]) == PIN_CONFIG_DRIVE_STRENGTH_UA)
809 			drive_strength_uA_found = true;
810 		if (pinconf_to_config_param(configs[i]) == MTK_PIN_CONFIG_DRV_ADV)
811 			adv_drve_strength_found = true;
812 	}
813 
814 	/*
815 	 * Disable advanced drive strength mode if drive-strength-microamp
816 	 * is not set. However, mediatek,drive-strength-adv takes precedence
817 	 * as its value can explicitly request the mode be enabled or not.
818 	 */
819 	if (hw->soc->adv_drive_set && !drive_strength_uA_found &&
820 	    !adv_drve_strength_found)
821 		hw->soc->adv_drive_set(hw, &hw->soc->pins[grp->pin], 0);
822 
823 	return 0;
824 }
825 
826 static const struct pinconf_ops mtk_confops = {
827 	.pin_config_get = mtk_pinconf_get,
828 	.pin_config_group_get	= mtk_pconf_group_get,
829 	.pin_config_group_set	= mtk_pconf_group_set,
830 	.is_generic = true,
831 };
832 
833 static struct pinctrl_desc mtk_desc = {
834 	.name = PINCTRL_PINCTRL_DEV,
835 	.pctlops = &mtk_pctlops,
836 	.pmxops = &mtk_pmxops,
837 	.confops = &mtk_confops,
838 	.owner = THIS_MODULE,
839 };
840 
mtk_gpio_get_direction(struct gpio_chip * chip,unsigned int gpio)841 static int mtk_gpio_get_direction(struct gpio_chip *chip, unsigned int gpio)
842 {
843 	struct mtk_pinctrl *hw = gpiochip_get_data(chip);
844 	const struct mtk_pin_desc *desc;
845 	int value, err;
846 
847 	if (gpio >= hw->soc->npins)
848 		return -EINVAL;
849 
850 	/*
851 	 * "Virtual" GPIOs are always and only used for interrupts
852 	 * Since they are only used for interrupts, they are always inputs
853 	 */
854 	if (mtk_is_virt_gpio(hw, gpio))
855 		return 1;
856 
857 	desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio];
858 
859 	err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DIR, &value);
860 	if (err)
861 		return err;
862 
863 	if (value)
864 		return GPIO_LINE_DIRECTION_OUT;
865 
866 	return GPIO_LINE_DIRECTION_IN;
867 }
868 
mtk_gpio_get(struct gpio_chip * chip,unsigned int gpio)869 static int mtk_gpio_get(struct gpio_chip *chip, unsigned int gpio)
870 {
871 	struct mtk_pinctrl *hw = gpiochip_get_data(chip);
872 	const struct mtk_pin_desc *desc;
873 	int value, err;
874 
875 	if (gpio >= hw->soc->npins)
876 		return -EINVAL;
877 
878 	desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio];
879 
880 	err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DI, &value);
881 	if (err)
882 		return err;
883 
884 	return !!value;
885 }
886 
mtk_gpio_set(struct gpio_chip * chip,unsigned int gpio,int value)887 static void mtk_gpio_set(struct gpio_chip *chip, unsigned int gpio, int value)
888 {
889 	struct mtk_pinctrl *hw = gpiochip_get_data(chip);
890 	const struct mtk_pin_desc *desc;
891 
892 	if (gpio >= hw->soc->npins)
893 		return;
894 
895 	desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio];
896 
897 	mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DO, !!value);
898 }
899 
mtk_gpio_direction_input(struct gpio_chip * chip,unsigned int gpio)900 static int mtk_gpio_direction_input(struct gpio_chip *chip, unsigned int gpio)
901 {
902 	struct mtk_pinctrl *hw = gpiochip_get_data(chip);
903 
904 	if (gpio >= hw->soc->npins)
905 		return -EINVAL;
906 
907 	return pinctrl_gpio_direction_input(chip->base + gpio);
908 }
909 
mtk_gpio_direction_output(struct gpio_chip * chip,unsigned int gpio,int value)910 static int mtk_gpio_direction_output(struct gpio_chip *chip, unsigned int gpio,
911 				     int value)
912 {
913 	struct mtk_pinctrl *hw = gpiochip_get_data(chip);
914 
915 	if (gpio >= hw->soc->npins)
916 		return -EINVAL;
917 
918 	mtk_gpio_set(chip, gpio, value);
919 
920 	return pinctrl_gpio_direction_output(chip->base + gpio);
921 }
922 
mtk_gpio_to_irq(struct gpio_chip * chip,unsigned int offset)923 static int mtk_gpio_to_irq(struct gpio_chip *chip, unsigned int offset)
924 {
925 	struct mtk_pinctrl *hw = gpiochip_get_data(chip);
926 	const struct mtk_pin_desc *desc;
927 
928 	if (!hw->eint)
929 		return -ENOTSUPP;
930 
931 	desc = (const struct mtk_pin_desc *)&hw->soc->pins[offset];
932 
933 	if (desc->eint.eint_n == EINT_NA)
934 		return -ENOTSUPP;
935 
936 	return mtk_eint_find_irq(hw->eint, desc->eint.eint_n);
937 }
938 
mtk_gpio_set_config(struct gpio_chip * chip,unsigned int offset,unsigned long config)939 static int mtk_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
940 			       unsigned long config)
941 {
942 	struct mtk_pinctrl *hw = gpiochip_get_data(chip);
943 	const struct mtk_pin_desc *desc;
944 	u32 debounce;
945 
946 	desc = (const struct mtk_pin_desc *)&hw->soc->pins[offset];
947 
948 	if (!hw->eint ||
949 	    pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE ||
950 	    desc->eint.eint_n == EINT_NA)
951 		return -ENOTSUPP;
952 
953 	debounce = pinconf_to_config_argument(config);
954 
955 	return mtk_eint_set_debounce(hw->eint, desc->eint.eint_n, debounce);
956 }
957 
mtk_build_gpiochip(struct mtk_pinctrl * hw)958 static int mtk_build_gpiochip(struct mtk_pinctrl *hw)
959 {
960 	struct gpio_chip *chip = &hw->chip;
961 	int ret;
962 
963 	chip->label		= PINCTRL_PINCTRL_DEV;
964 	chip->parent		= hw->dev;
965 	chip->request		= gpiochip_generic_request;
966 	chip->free		= gpiochip_generic_free;
967 	chip->get_direction	= mtk_gpio_get_direction;
968 	chip->direction_input	= mtk_gpio_direction_input;
969 	chip->direction_output	= mtk_gpio_direction_output;
970 	chip->get		= mtk_gpio_get;
971 	chip->set		= mtk_gpio_set;
972 	chip->to_irq		= mtk_gpio_to_irq;
973 	chip->set_config	= mtk_gpio_set_config;
974 	chip->base		= -1;
975 	chip->ngpio		= hw->soc->npins;
976 
977 	ret = gpiochip_add_data(chip, hw);
978 	if (ret < 0)
979 		return ret;
980 
981 	return 0;
982 }
983 
mtk_pctrl_build_state(struct platform_device * pdev)984 static int mtk_pctrl_build_state(struct platform_device *pdev)
985 {
986 	struct mtk_pinctrl *hw = platform_get_drvdata(pdev);
987 	int i;
988 
989 	/* Allocate groups */
990 	hw->groups = devm_kmalloc_array(&pdev->dev, hw->soc->ngrps,
991 					sizeof(*hw->groups), GFP_KERNEL);
992 	if (!hw->groups)
993 		return -ENOMEM;
994 
995 	/* We assume that one pin is one group, use pin name as group name. */
996 	hw->grp_names = devm_kmalloc_array(&pdev->dev, hw->soc->ngrps,
997 					   sizeof(*hw->grp_names), GFP_KERNEL);
998 	if (!hw->grp_names)
999 		return -ENOMEM;
1000 
1001 	for (i = 0; i < hw->soc->npins; i++) {
1002 		const struct mtk_pin_desc *pin = hw->soc->pins + i;
1003 		struct mtk_pinctrl_group *group = hw->groups + i;
1004 
1005 		group->name = pin->name;
1006 		group->pin = pin->number;
1007 
1008 		hw->grp_names[i] = pin->name;
1009 	}
1010 
1011 	return 0;
1012 }
1013 
mtk_paris_pinctrl_probe(struct platform_device * pdev)1014 int mtk_paris_pinctrl_probe(struct platform_device *pdev)
1015 {
1016 	struct device *dev = &pdev->dev;
1017 	struct pinctrl_pin_desc *pins;
1018 	struct mtk_pinctrl *hw;
1019 	int err, i;
1020 
1021 	hw = devm_kzalloc(&pdev->dev, sizeof(*hw), GFP_KERNEL);
1022 	if (!hw)
1023 		return -ENOMEM;
1024 
1025 	platform_set_drvdata(pdev, hw);
1026 
1027 	hw->soc = device_get_match_data(dev);
1028 	if (!hw->soc)
1029 		return -ENOENT;
1030 
1031 	hw->dev = &pdev->dev;
1032 
1033 	if (!hw->soc->nbase_names)
1034 		return dev_err_probe(dev, -EINVAL,
1035 			"SoC should be assigned at least one register base\n");
1036 
1037 	hw->base = devm_kmalloc_array(&pdev->dev, hw->soc->nbase_names,
1038 				      sizeof(*hw->base), GFP_KERNEL);
1039 	if (!hw->base)
1040 		return -ENOMEM;
1041 
1042 	for (i = 0; i < hw->soc->nbase_names; i++) {
1043 		hw->base[i] = devm_platform_ioremap_resource_byname(pdev,
1044 					hw->soc->base_names[i]);
1045 		if (IS_ERR(hw->base[i]))
1046 			return PTR_ERR(hw->base[i]);
1047 	}
1048 
1049 	hw->nbase = hw->soc->nbase_names;
1050 
1051 	if (of_find_property(hw->dev->of_node,
1052 			     "mediatek,rsel-resistance-in-si-unit", NULL))
1053 		hw->rsel_si_unit = true;
1054 	else
1055 		hw->rsel_si_unit = false;
1056 
1057 	spin_lock_init(&hw->lock);
1058 
1059 	err = mtk_pctrl_build_state(pdev);
1060 	if (err)
1061 		return dev_err_probe(dev, err, "build state failed\n");
1062 
1063 	/* Copy from internal struct mtk_pin_desc to register to the core */
1064 	pins = devm_kmalloc_array(&pdev->dev, hw->soc->npins, sizeof(*pins),
1065 				  GFP_KERNEL);
1066 	if (!pins)
1067 		return -ENOMEM;
1068 
1069 	for (i = 0; i < hw->soc->npins; i++) {
1070 		pins[i].number = hw->soc->pins[i].number;
1071 		pins[i].name = hw->soc->pins[i].name;
1072 	}
1073 
1074 	/* Setup pins descriptions per SoC types */
1075 	mtk_desc.pins = (const struct pinctrl_pin_desc *)pins;
1076 	mtk_desc.npins = hw->soc->npins;
1077 	mtk_desc.num_custom_params = ARRAY_SIZE(mtk_custom_bindings);
1078 	mtk_desc.custom_params = mtk_custom_bindings;
1079 #ifdef CONFIG_DEBUG_FS
1080 	mtk_desc.custom_conf_items = mtk_conf_items;
1081 #endif
1082 
1083 	err = devm_pinctrl_register_and_init(&pdev->dev, &mtk_desc, hw,
1084 					     &hw->pctrl);
1085 	if (err)
1086 		return err;
1087 
1088 	err = pinctrl_enable(hw->pctrl);
1089 	if (err)
1090 		return err;
1091 
1092 	err = mtk_build_eint(hw, pdev);
1093 	if (err)
1094 		dev_warn(&pdev->dev,
1095 			 "Failed to add EINT, but pinctrl still can work\n");
1096 
1097 	/* Build gpiochip should be after pinctrl_enable is done */
1098 	err = mtk_build_gpiochip(hw);
1099 	if (err)
1100 		return dev_err_probe(dev, err, "Failed to add gpio_chip\n");
1101 
1102 	platform_set_drvdata(pdev, hw);
1103 
1104 	return 0;
1105 }
1106 EXPORT_SYMBOL_GPL(mtk_paris_pinctrl_probe);
1107 
mtk_paris_pinctrl_suspend(struct device * device)1108 static int mtk_paris_pinctrl_suspend(struct device *device)
1109 {
1110 	struct mtk_pinctrl *pctl = dev_get_drvdata(device);
1111 
1112 	return mtk_eint_do_suspend(pctl->eint);
1113 }
1114 
mtk_paris_pinctrl_resume(struct device * device)1115 static int mtk_paris_pinctrl_resume(struct device *device)
1116 {
1117 	struct mtk_pinctrl *pctl = dev_get_drvdata(device);
1118 
1119 	return mtk_eint_do_resume(pctl->eint);
1120 }
1121 
1122 const struct dev_pm_ops mtk_paris_pinctrl_pm_ops = {
1123 	.suspend_noirq = mtk_paris_pinctrl_suspend,
1124 	.resume_noirq = mtk_paris_pinctrl_resume,
1125 };
1126 
1127 MODULE_LICENSE("GPL v2");
1128 MODULE_DESCRIPTION("MediaTek Pinctrl Common Driver V2 Paris");
1129