1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * MediaTek ALSA SoC Audio DAI eTDM Control
4  *
5  * Copyright (c) 2021 MediaTek Inc.
6  * Author: Bicycle Tsai <bicycle.tsai@mediatek.com>
7  *         Trevor Wu <trevor.wu@mediatek.com>
8  */
9 
10 #include <linux/delay.h>
11 #include <linux/pm_runtime.h>
12 #include <linux/regmap.h>
13 #include <sound/pcm_params.h>
14 #include "mt8195-afe-clk.h"
15 #include "mt8195-afe-common.h"
16 #include "mt8195-reg.h"
17 
18 #define MT8195_ETDM_MAX_CHANNELS 24
19 #define MT8195_ETDM_NORMAL_MAX_BCK_RATE 24576000
20 #define ETDM_TO_DAI_ID(x) ((x) + MT8195_AFE_IO_ETDM_START)
21 #define ENUM_TO_STR(x)	#x
22 
23 enum {
24 	MTK_DAI_ETDM_FORMAT_I2S = 0,
25 	MTK_DAI_ETDM_FORMAT_LJ,
26 	MTK_DAI_ETDM_FORMAT_RJ,
27 	MTK_DAI_ETDM_FORMAT_EIAJ,
28 	MTK_DAI_ETDM_FORMAT_DSPA,
29 	MTK_DAI_ETDM_FORMAT_DSPB,
30 };
31 
32 enum {
33 	MTK_DAI_ETDM_DATA_ONE_PIN = 0,
34 	MTK_DAI_ETDM_DATA_MULTI_PIN,
35 };
36 
37 enum {
38 	ETDM_IN,
39 	ETDM_OUT,
40 };
41 
42 enum {
43 	ETDM_IN_FROM_PAD,
44 	ETDM_IN_FROM_ETDM_OUT1,
45 	ETDM_IN_FROM_ETDM_OUT2,
46 };
47 
48 enum {
49 	ETDM_IN_SLAVE_FROM_PAD,
50 	ETDM_IN_SLAVE_FROM_ETDM_OUT1,
51 	ETDM_IN_SLAVE_FROM_ETDM_OUT2,
52 };
53 
54 enum {
55 	ETDM_OUT_SLAVE_FROM_PAD,
56 	ETDM_OUT_SLAVE_FROM_ETDM_IN1,
57 	ETDM_OUT_SLAVE_FROM_ETDM_IN2,
58 };
59 
60 enum {
61 	COWORK_ETDM_NONE = 0,
62 	COWORK_ETDM_IN1_M = 2,
63 	COWORK_ETDM_IN1_S = 3,
64 	COWORK_ETDM_IN2_M = 4,
65 	COWORK_ETDM_IN2_S = 5,
66 	COWORK_ETDM_OUT1_M = 10,
67 	COWORK_ETDM_OUT1_S = 11,
68 	COWORK_ETDM_OUT2_M = 12,
69 	COWORK_ETDM_OUT2_S = 13,
70 	COWORK_ETDM_OUT3_M = 14,
71 	COWORK_ETDM_OUT3_S = 15,
72 };
73 
74 enum {
75 	ETDM_RELATCH_TIMING_A1A2SYS,
76 	ETDM_RELATCH_TIMING_A3SYS,
77 	ETDM_RELATCH_TIMING_A4SYS,
78 };
79 
80 enum {
81 	ETDM_SYNC_NONE,
82 	ETDM_SYNC_FROM_IN1,
83 	ETDM_SYNC_FROM_IN2,
84 	ETDM_SYNC_FROM_OUT1,
85 	ETDM_SYNC_FROM_OUT2,
86 	ETDM_SYNC_FROM_OUT3,
87 };
88 
89 struct etdm_con_reg {
90 	unsigned int con0;
91 	unsigned int con1;
92 	unsigned int con2;
93 	unsigned int con3;
94 	unsigned int con4;
95 	unsigned int con5;
96 };
97 
98 struct mtk_dai_etdm_rate {
99 	unsigned int rate;
100 	unsigned int reg_value;
101 };
102 
103 struct mtk_dai_etdm_priv {
104 	unsigned int clock_mode;
105 	unsigned int data_mode;
106 	bool slave_mode;
107 	bool lrck_inv;
108 	bool bck_inv;
109 	unsigned int format;
110 	unsigned int slots;
111 	unsigned int lrck_width;
112 	unsigned int mclk_freq;
113 	unsigned int mclk_apll;
114 	unsigned int mclk_dir;
115 	int cowork_source_id; //dai id
116 	unsigned int cowork_slv_count;
117 	int cowork_slv_id[MT8195_AFE_IO_ETDM_NUM - 1]; //dai_id
118 	bool in_disable_ch[MT8195_ETDM_MAX_CHANNELS];
119 	unsigned int en_ref_cnt;
120 };
121 
122 static const struct mtk_dai_etdm_rate mt8195_etdm_rates[] = {
123 	{ .rate = 8000, .reg_value = 0, },
124 	{ .rate = 12000, .reg_value = 1, },
125 	{ .rate = 16000, .reg_value = 2, },
126 	{ .rate = 24000, .reg_value = 3, },
127 	{ .rate = 32000, .reg_value = 4, },
128 	{ .rate = 48000, .reg_value = 5, },
129 	{ .rate = 96000, .reg_value = 7, },
130 	{ .rate = 192000, .reg_value = 9, },
131 	{ .rate = 384000, .reg_value = 11, },
132 	{ .rate = 11025, .reg_value = 16, },
133 	{ .rate = 22050, .reg_value = 17, },
134 	{ .rate = 44100, .reg_value = 18, },
135 	{ .rate = 88200, .reg_value = 19, },
136 	{ .rate = 176400, .reg_value = 20, },
137 	{ .rate = 352800, .reg_value = 21, },
138 };
139 
mt8195_afe_etdm_is_valid(int id)140 static bool mt8195_afe_etdm_is_valid(int id)
141 {
142 	switch (id) {
143 	case MT8195_AFE_IO_ETDM1_IN:
144 		fallthrough;
145 	case MT8195_AFE_IO_ETDM2_IN:
146 		fallthrough;
147 	case MT8195_AFE_IO_ETDM1_OUT:
148 		fallthrough;
149 	case MT8195_AFE_IO_ETDM2_OUT:
150 		fallthrough;
151 	case MT8195_AFE_IO_DPTX:
152 		fallthrough;
153 	case MT8195_AFE_IO_ETDM3_OUT:
154 		return true;
155 	default:
156 		return false;
157 	}
158 }
159 
mt8195_afe_hdmitx_dptx_is_valid(int id)160 static bool mt8195_afe_hdmitx_dptx_is_valid(int id)
161 {
162 	switch (id) {
163 	case MT8195_AFE_IO_DPTX:
164 		fallthrough;
165 	case MT8195_AFE_IO_ETDM3_OUT:
166 		return true;
167 	default:
168 		return false;
169 	}
170 }
171 
get_etdm_fs_timing(unsigned int rate)172 static int get_etdm_fs_timing(unsigned int rate)
173 {
174 	int i;
175 
176 	for (i = 0; i < ARRAY_SIZE(mt8195_etdm_rates); i++)
177 		if (mt8195_etdm_rates[i].rate == rate)
178 			return mt8195_etdm_rates[i].reg_value;
179 
180 	return -EINVAL;
181 }
182 
get_etdm_ch_fixup(unsigned int channels)183 static unsigned int get_etdm_ch_fixup(unsigned int channels)
184 {
185 	if (channels > 16)
186 		return 24;
187 	else if (channels > 8)
188 		return 16;
189 	else if (channels > 4)
190 		return 8;
191 	else if (channels > 2)
192 		return 4;
193 	else
194 		return 2;
195 }
196 
get_etdm_reg(unsigned int dai_id,struct etdm_con_reg * etdm_reg)197 static int get_etdm_reg(unsigned int dai_id, struct etdm_con_reg *etdm_reg)
198 {
199 	switch (dai_id) {
200 	case MT8195_AFE_IO_ETDM1_IN:
201 		etdm_reg->con0 = ETDM_IN1_CON0;
202 		etdm_reg->con1 = ETDM_IN1_CON1;
203 		etdm_reg->con2 = ETDM_IN1_CON2;
204 		etdm_reg->con3 = ETDM_IN1_CON3;
205 		etdm_reg->con4 = ETDM_IN1_CON4;
206 		etdm_reg->con5 = ETDM_IN1_CON5;
207 		break;
208 	case MT8195_AFE_IO_ETDM2_IN:
209 		etdm_reg->con0 = ETDM_IN2_CON0;
210 		etdm_reg->con1 = ETDM_IN2_CON1;
211 		etdm_reg->con2 = ETDM_IN2_CON2;
212 		etdm_reg->con3 = ETDM_IN2_CON3;
213 		etdm_reg->con4 = ETDM_IN2_CON4;
214 		etdm_reg->con5 = ETDM_IN2_CON5;
215 		break;
216 	case MT8195_AFE_IO_ETDM1_OUT:
217 		etdm_reg->con0 = ETDM_OUT1_CON0;
218 		etdm_reg->con1 = ETDM_OUT1_CON1;
219 		etdm_reg->con2 = ETDM_OUT1_CON2;
220 		etdm_reg->con3 = ETDM_OUT1_CON3;
221 		etdm_reg->con4 = ETDM_OUT1_CON4;
222 		etdm_reg->con5 = ETDM_OUT1_CON5;
223 		break;
224 	case MT8195_AFE_IO_ETDM2_OUT:
225 		etdm_reg->con0 = ETDM_OUT2_CON0;
226 		etdm_reg->con1 = ETDM_OUT2_CON1;
227 		etdm_reg->con2 = ETDM_OUT2_CON2;
228 		etdm_reg->con3 = ETDM_OUT2_CON3;
229 		etdm_reg->con4 = ETDM_OUT2_CON4;
230 		etdm_reg->con5 = ETDM_OUT2_CON5;
231 		break;
232 	case MT8195_AFE_IO_ETDM3_OUT:
233 	case MT8195_AFE_IO_DPTX:
234 		etdm_reg->con0 = ETDM_OUT3_CON0;
235 		etdm_reg->con1 = ETDM_OUT3_CON1;
236 		etdm_reg->con2 = ETDM_OUT3_CON2;
237 		etdm_reg->con3 = ETDM_OUT3_CON3;
238 		etdm_reg->con4 = ETDM_OUT3_CON4;
239 		etdm_reg->con5 = ETDM_OUT3_CON5;
240 		break;
241 	default:
242 		return -EINVAL;
243 	}
244 	return 0;
245 }
246 
get_etdm_dir(unsigned int dai_id)247 static int get_etdm_dir(unsigned int dai_id)
248 {
249 	switch (dai_id) {
250 	case MT8195_AFE_IO_ETDM1_IN:
251 	case MT8195_AFE_IO_ETDM2_IN:
252 		return ETDM_IN;
253 	case MT8195_AFE_IO_ETDM1_OUT:
254 	case MT8195_AFE_IO_ETDM2_OUT:
255 	case MT8195_AFE_IO_ETDM3_OUT:
256 		return ETDM_OUT;
257 	default:
258 		return -EINVAL;
259 	}
260 }
261 
get_etdm_wlen(unsigned int bitwidth)262 static int get_etdm_wlen(unsigned int bitwidth)
263 {
264 	return bitwidth <= 16 ? 16 : 32;
265 }
266 
is_cowork_mode(struct snd_soc_dai * dai)267 static int is_cowork_mode(struct snd_soc_dai *dai)
268 {
269 	struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
270 	struct mt8195_afe_private *afe_priv = afe->platform_priv;
271 	struct mtk_dai_etdm_priv *etdm_data;
272 
273 	if (!mt8195_afe_etdm_is_valid(dai->id))
274 		return -EINVAL;
275 
276 	etdm_data = afe_priv->dai_priv[dai->id];
277 	return (etdm_data->cowork_slv_count > 0 ||
278 		etdm_data->cowork_source_id != COWORK_ETDM_NONE);
279 }
280 
sync_to_dai_id(int source_sel)281 static int sync_to_dai_id(int source_sel)
282 {
283 	switch (source_sel) {
284 	case ETDM_SYNC_FROM_IN1:
285 		return MT8195_AFE_IO_ETDM1_IN;
286 	case ETDM_SYNC_FROM_IN2:
287 		return MT8195_AFE_IO_ETDM2_IN;
288 	case ETDM_SYNC_FROM_OUT1:
289 		return MT8195_AFE_IO_ETDM1_OUT;
290 	case ETDM_SYNC_FROM_OUT2:
291 		return MT8195_AFE_IO_ETDM2_OUT;
292 	case ETDM_SYNC_FROM_OUT3:
293 		return MT8195_AFE_IO_ETDM3_OUT;
294 	default:
295 		return 0;
296 	}
297 }
298 
get_etdm_cowork_master_id(struct snd_soc_dai * dai)299 static int get_etdm_cowork_master_id(struct snd_soc_dai *dai)
300 {
301 	struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
302 	struct mt8195_afe_private *afe_priv = afe->platform_priv;
303 	struct mtk_dai_etdm_priv *etdm_data;
304 	int dai_id;
305 
306 	if (!mt8195_afe_etdm_is_valid(dai->id))
307 		return -EINVAL;
308 
309 	etdm_data = afe_priv->dai_priv[dai->id];
310 	dai_id = etdm_data->cowork_source_id;
311 
312 	if (dai_id == COWORK_ETDM_NONE)
313 		dai_id = dai->id;
314 
315 	return dai_id;
316 }
317 
318 static const struct snd_kcontrol_new mtk_dai_etdm_o048_mix[] = {
319 	SOC_DAPM_SINGLE_AUTODISABLE("I020 Switch", AFE_CONN48, 20, 1, 0),
320 	SOC_DAPM_SINGLE_AUTODISABLE("I022 Switch", AFE_CONN48, 22, 1, 0),
321 	SOC_DAPM_SINGLE_AUTODISABLE("I046 Switch", AFE_CONN48_1, 14, 1, 0),
322 	SOC_DAPM_SINGLE_AUTODISABLE("I070 Switch", AFE_CONN48_2, 6, 1, 0),
323 };
324 
325 static const struct snd_kcontrol_new mtk_dai_etdm_o049_mix[] = {
326 	SOC_DAPM_SINGLE_AUTODISABLE("I021 Switch", AFE_CONN49, 21, 1, 0),
327 	SOC_DAPM_SINGLE_AUTODISABLE("I023 Switch", AFE_CONN49, 23, 1, 0),
328 	SOC_DAPM_SINGLE_AUTODISABLE("I047 Switch", AFE_CONN49_1, 15, 1, 0),
329 	SOC_DAPM_SINGLE_AUTODISABLE("I071 Switch", AFE_CONN49_2, 7, 1, 0),
330 };
331 
332 static const struct snd_kcontrol_new mtk_dai_etdm_o050_mix[] = {
333 	SOC_DAPM_SINGLE_AUTODISABLE("I024 Switch", AFE_CONN50, 24, 1, 0),
334 	SOC_DAPM_SINGLE_AUTODISABLE("I048 Switch", AFE_CONN50_1, 16, 1, 0),
335 };
336 
337 static const struct snd_kcontrol_new mtk_dai_etdm_o051_mix[] = {
338 	SOC_DAPM_SINGLE_AUTODISABLE("I025 Switch", AFE_CONN51, 25, 1, 0),
339 	SOC_DAPM_SINGLE_AUTODISABLE("I049 Switch", AFE_CONN51_1, 17, 1, 0),
340 };
341 
342 static const struct snd_kcontrol_new mtk_dai_etdm_o052_mix[] = {
343 	SOC_DAPM_SINGLE_AUTODISABLE("I026 Switch", AFE_CONN52, 26, 1, 0),
344 	SOC_DAPM_SINGLE_AUTODISABLE("I050 Switch", AFE_CONN52_1, 18, 1, 0),
345 };
346 
347 static const struct snd_kcontrol_new mtk_dai_etdm_o053_mix[] = {
348 	SOC_DAPM_SINGLE_AUTODISABLE("I027 Switch", AFE_CONN53, 27, 1, 0),
349 	SOC_DAPM_SINGLE_AUTODISABLE("I051 Switch", AFE_CONN53_1, 19, 1, 0),
350 };
351 
352 static const struct snd_kcontrol_new mtk_dai_etdm_o054_mix[] = {
353 	SOC_DAPM_SINGLE_AUTODISABLE("I028 Switch", AFE_CONN54, 28, 1, 0),
354 	SOC_DAPM_SINGLE_AUTODISABLE("I052 Switch", AFE_CONN54_1, 20, 1, 0),
355 };
356 
357 static const struct snd_kcontrol_new mtk_dai_etdm_o055_mix[] = {
358 	SOC_DAPM_SINGLE_AUTODISABLE("I029 Switch", AFE_CONN55, 29, 1, 0),
359 	SOC_DAPM_SINGLE_AUTODISABLE("I053 Switch", AFE_CONN55_1, 21, 1, 0),
360 };
361 
362 static const struct snd_kcontrol_new mtk_dai_etdm_o056_mix[] = {
363 	SOC_DAPM_SINGLE_AUTODISABLE("I030 Switch", AFE_CONN56, 30, 1, 0),
364 	SOC_DAPM_SINGLE_AUTODISABLE("I054 Switch", AFE_CONN56_1, 22, 1, 0),
365 };
366 
367 static const struct snd_kcontrol_new mtk_dai_etdm_o057_mix[] = {
368 	SOC_DAPM_SINGLE_AUTODISABLE("I031 Switch", AFE_CONN57, 31, 1, 0),
369 	SOC_DAPM_SINGLE_AUTODISABLE("I055 Switch", AFE_CONN57_1, 23, 1, 0),
370 };
371 
372 static const struct snd_kcontrol_new mtk_dai_etdm_o058_mix[] = {
373 	SOC_DAPM_SINGLE_AUTODISABLE("I032 Switch", AFE_CONN58_1, 0, 1, 0),
374 	SOC_DAPM_SINGLE_AUTODISABLE("I056 Switch", AFE_CONN58_1, 24, 1, 0),
375 };
376 
377 static const struct snd_kcontrol_new mtk_dai_etdm_o059_mix[] = {
378 	SOC_DAPM_SINGLE_AUTODISABLE("I033 Switch", AFE_CONN59_1, 1, 1, 0),
379 	SOC_DAPM_SINGLE_AUTODISABLE("I057 Switch", AFE_CONN59_1, 25, 1, 0),
380 };
381 
382 static const struct snd_kcontrol_new mtk_dai_etdm_o060_mix[] = {
383 	SOC_DAPM_SINGLE_AUTODISABLE("I034 Switch", AFE_CONN60_1, 2, 1, 0),
384 	SOC_DAPM_SINGLE_AUTODISABLE("I058 Switch", AFE_CONN60_1, 26, 1, 0),
385 };
386 
387 static const struct snd_kcontrol_new mtk_dai_etdm_o061_mix[] = {
388 	SOC_DAPM_SINGLE_AUTODISABLE("I035 Switch", AFE_CONN61_1, 3, 1, 0),
389 	SOC_DAPM_SINGLE_AUTODISABLE("I059 Switch", AFE_CONN61_1, 27, 1, 0),
390 };
391 
392 static const struct snd_kcontrol_new mtk_dai_etdm_o062_mix[] = {
393 	SOC_DAPM_SINGLE_AUTODISABLE("I036 Switch", AFE_CONN62_1, 4, 1, 0),
394 	SOC_DAPM_SINGLE_AUTODISABLE("I060 Switch", AFE_CONN62_1, 28, 1, 0),
395 };
396 
397 static const struct snd_kcontrol_new mtk_dai_etdm_o063_mix[] = {
398 	SOC_DAPM_SINGLE_AUTODISABLE("I037 Switch", AFE_CONN63_1, 5, 1, 0),
399 	SOC_DAPM_SINGLE_AUTODISABLE("I061 Switch", AFE_CONN63_1, 29, 1, 0),
400 };
401 
402 static const struct snd_kcontrol_new mtk_dai_etdm_o064_mix[] = {
403 	SOC_DAPM_SINGLE_AUTODISABLE("I038 Switch", AFE_CONN64_1, 6, 1, 0),
404 	SOC_DAPM_SINGLE_AUTODISABLE("I062 Switch", AFE_CONN64_1, 30, 1, 0),
405 };
406 
407 static const struct snd_kcontrol_new mtk_dai_etdm_o065_mix[] = {
408 	SOC_DAPM_SINGLE_AUTODISABLE("I039 Switch", AFE_CONN65_1, 7, 1, 0),
409 	SOC_DAPM_SINGLE_AUTODISABLE("I063 Switch", AFE_CONN65_1, 31, 1, 0),
410 };
411 
412 static const struct snd_kcontrol_new mtk_dai_etdm_o066_mix[] = {
413 	SOC_DAPM_SINGLE_AUTODISABLE("I040 Switch", AFE_CONN66_1, 8, 1, 0),
414 	SOC_DAPM_SINGLE_AUTODISABLE("I064 Switch", AFE_CONN66_2, 0, 1, 0),
415 };
416 
417 static const struct snd_kcontrol_new mtk_dai_etdm_o067_mix[] = {
418 	SOC_DAPM_SINGLE_AUTODISABLE("I041 Switch", AFE_CONN67_1, 9, 1, 0),
419 	SOC_DAPM_SINGLE_AUTODISABLE("I065 Switch", AFE_CONN67_2, 1, 1, 0),
420 };
421 
422 static const struct snd_kcontrol_new mtk_dai_etdm_o068_mix[] = {
423 	SOC_DAPM_SINGLE_AUTODISABLE("I042 Switch", AFE_CONN68_1, 10, 1, 0),
424 	SOC_DAPM_SINGLE_AUTODISABLE("I066 Switch", AFE_CONN68_2, 2, 1, 0),
425 };
426 
427 static const struct snd_kcontrol_new mtk_dai_etdm_o069_mix[] = {
428 	SOC_DAPM_SINGLE_AUTODISABLE("I043 Switch", AFE_CONN69_1, 11, 1, 0),
429 	SOC_DAPM_SINGLE_AUTODISABLE("I067 Switch", AFE_CONN69_2, 3, 1, 0),
430 };
431 
432 static const struct snd_kcontrol_new mtk_dai_etdm_o070_mix[] = {
433 	SOC_DAPM_SINGLE_AUTODISABLE("I044 Switch", AFE_CONN70_1, 12, 1, 0),
434 	SOC_DAPM_SINGLE_AUTODISABLE("I068 Switch", AFE_CONN70_2, 4, 1, 0),
435 };
436 
437 static const struct snd_kcontrol_new mtk_dai_etdm_o071_mix[] = {
438 	SOC_DAPM_SINGLE_AUTODISABLE("I045 Switch", AFE_CONN71_1, 13, 1, 0),
439 	SOC_DAPM_SINGLE_AUTODISABLE("I069 Switch", AFE_CONN71_2, 5, 1, 0),
440 };
441 
442 static const struct snd_kcontrol_new mtk_dai_etdm_o072_mix[] = {
443 	SOC_DAPM_SINGLE_AUTODISABLE("I020 Switch", AFE_CONN72, 20, 1, 0),
444 	SOC_DAPM_SINGLE_AUTODISABLE("I022 Switch", AFE_CONN72, 22, 1, 0),
445 	SOC_DAPM_SINGLE_AUTODISABLE("I046 Switch", AFE_CONN72_1, 14, 1, 0),
446 	SOC_DAPM_SINGLE_AUTODISABLE("I070 Switch", AFE_CONN72_2, 6, 1, 0),
447 };
448 
449 static const struct snd_kcontrol_new mtk_dai_etdm_o073_mix[] = {
450 	SOC_DAPM_SINGLE_AUTODISABLE("I021 Switch", AFE_CONN73, 21, 1, 0),
451 	SOC_DAPM_SINGLE_AUTODISABLE("I023 Switch", AFE_CONN73, 23, 1, 0),
452 	SOC_DAPM_SINGLE_AUTODISABLE("I047 Switch", AFE_CONN73_1, 15, 1, 0),
453 	SOC_DAPM_SINGLE_AUTODISABLE("I071 Switch", AFE_CONN73_2, 7, 1, 0),
454 };
455 
456 static const struct snd_kcontrol_new mtk_dai_etdm_o074_mix[] = {
457 	SOC_DAPM_SINGLE_AUTODISABLE("I024 Switch", AFE_CONN74, 24, 1, 0),
458 	SOC_DAPM_SINGLE_AUTODISABLE("I048 Switch", AFE_CONN74_1, 16, 1, 0),
459 };
460 
461 static const struct snd_kcontrol_new mtk_dai_etdm_o075_mix[] = {
462 	SOC_DAPM_SINGLE_AUTODISABLE("I025 Switch", AFE_CONN75, 25, 1, 0),
463 	SOC_DAPM_SINGLE_AUTODISABLE("I049 Switch", AFE_CONN75_1, 17, 1, 0),
464 };
465 
466 static const struct snd_kcontrol_new mtk_dai_etdm_o076_mix[] = {
467 	SOC_DAPM_SINGLE_AUTODISABLE("I026 Switch", AFE_CONN76, 26, 1, 0),
468 	SOC_DAPM_SINGLE_AUTODISABLE("I050 Switch", AFE_CONN76_1, 18, 1, 0),
469 };
470 
471 static const struct snd_kcontrol_new mtk_dai_etdm_o077_mix[] = {
472 	SOC_DAPM_SINGLE_AUTODISABLE("I027 Switch", AFE_CONN77, 27, 1, 0),
473 	SOC_DAPM_SINGLE_AUTODISABLE("I051 Switch", AFE_CONN77_1, 19, 1, 0),
474 };
475 
476 static const struct snd_kcontrol_new mtk_dai_etdm_o078_mix[] = {
477 	SOC_DAPM_SINGLE_AUTODISABLE("I028 Switch", AFE_CONN78, 28, 1, 0),
478 	SOC_DAPM_SINGLE_AUTODISABLE("I052 Switch", AFE_CONN78_1, 20, 1, 0),
479 };
480 
481 static const struct snd_kcontrol_new mtk_dai_etdm_o079_mix[] = {
482 	SOC_DAPM_SINGLE_AUTODISABLE("I029 Switch", AFE_CONN79, 29, 1, 0),
483 	SOC_DAPM_SINGLE_AUTODISABLE("I053 Switch", AFE_CONN79_1, 21, 1, 0),
484 };
485 
486 static const struct snd_kcontrol_new mtk_dai_etdm_o080_mix[] = {
487 	SOC_DAPM_SINGLE_AUTODISABLE("I030 Switch", AFE_CONN80, 30, 1, 0),
488 	SOC_DAPM_SINGLE_AUTODISABLE("I054 Switch", AFE_CONN80_1, 22, 1, 0),
489 };
490 
491 static const struct snd_kcontrol_new mtk_dai_etdm_o081_mix[] = {
492 	SOC_DAPM_SINGLE_AUTODISABLE("I031 Switch", AFE_CONN81, 31, 1, 0),
493 	SOC_DAPM_SINGLE_AUTODISABLE("I055 Switch", AFE_CONN81_1, 23, 1, 0),
494 };
495 
496 static const struct snd_kcontrol_new mtk_dai_etdm_o082_mix[] = {
497 	SOC_DAPM_SINGLE_AUTODISABLE("I032 Switch", AFE_CONN82_1, 0, 1, 0),
498 	SOC_DAPM_SINGLE_AUTODISABLE("I056 Switch", AFE_CONN82_1, 24, 1, 0),
499 };
500 
501 static const struct snd_kcontrol_new mtk_dai_etdm_o083_mix[] = {
502 	SOC_DAPM_SINGLE_AUTODISABLE("I033 Switch", AFE_CONN83_1, 1, 1, 0),
503 	SOC_DAPM_SINGLE_AUTODISABLE("I057 Switch", AFE_CONN83_1, 25, 1, 0),
504 };
505 
506 static const struct snd_kcontrol_new mtk_dai_etdm_o084_mix[] = {
507 	SOC_DAPM_SINGLE_AUTODISABLE("I034 Switch", AFE_CONN84_1, 2, 1, 0),
508 	SOC_DAPM_SINGLE_AUTODISABLE("I058 Switch", AFE_CONN84_1, 26, 1, 0),
509 };
510 
511 static const struct snd_kcontrol_new mtk_dai_etdm_o085_mix[] = {
512 	SOC_DAPM_SINGLE_AUTODISABLE("I035 Switch", AFE_CONN85_1, 3, 1, 0),
513 	SOC_DAPM_SINGLE_AUTODISABLE("I059 Switch", AFE_CONN85_1, 27, 1, 0),
514 };
515 
516 static const struct snd_kcontrol_new mtk_dai_etdm_o086_mix[] = {
517 	SOC_DAPM_SINGLE_AUTODISABLE("I036 Switch", AFE_CONN86_1, 4, 1, 0),
518 	SOC_DAPM_SINGLE_AUTODISABLE("I060 Switch", AFE_CONN86_1, 28, 1, 0),
519 };
520 
521 static const struct snd_kcontrol_new mtk_dai_etdm_o087_mix[] = {
522 	SOC_DAPM_SINGLE_AUTODISABLE("I037 Switch", AFE_CONN87_1, 5, 1, 0),
523 	SOC_DAPM_SINGLE_AUTODISABLE("I061 Switch", AFE_CONN87_1, 29, 1, 0),
524 };
525 
526 static const struct snd_kcontrol_new mtk_dai_etdm_o088_mix[] = {
527 	SOC_DAPM_SINGLE_AUTODISABLE("I038 Switch", AFE_CONN88_1, 6, 1, 0),
528 	SOC_DAPM_SINGLE_AUTODISABLE("I062 Switch", AFE_CONN88_1, 30, 1, 0),
529 };
530 
531 static const struct snd_kcontrol_new mtk_dai_etdm_o089_mix[] = {
532 	SOC_DAPM_SINGLE_AUTODISABLE("I039 Switch", AFE_CONN89_1, 7, 1, 0),
533 	SOC_DAPM_SINGLE_AUTODISABLE("I063 Switch", AFE_CONN89_1, 31, 1, 0),
534 };
535 
536 static const struct snd_kcontrol_new mtk_dai_etdm_o090_mix[] = {
537 	SOC_DAPM_SINGLE_AUTODISABLE("I040 Switch", AFE_CONN90_1, 8, 1, 0),
538 	SOC_DAPM_SINGLE_AUTODISABLE("I064 Switch", AFE_CONN90_2, 0, 1, 0),
539 };
540 
541 static const struct snd_kcontrol_new mtk_dai_etdm_o091_mix[] = {
542 	SOC_DAPM_SINGLE_AUTODISABLE("I041 Switch", AFE_CONN91_1, 9, 1, 0),
543 	SOC_DAPM_SINGLE_AUTODISABLE("I065 Switch", AFE_CONN91_2, 1, 1, 0),
544 };
545 
546 static const struct snd_kcontrol_new mtk_dai_etdm_o092_mix[] = {
547 	SOC_DAPM_SINGLE_AUTODISABLE("I042 Switch", AFE_CONN92_1, 10, 1, 0),
548 	SOC_DAPM_SINGLE_AUTODISABLE("I066 Switch", AFE_CONN92_2, 2, 1, 0),
549 };
550 
551 static const struct snd_kcontrol_new mtk_dai_etdm_o093_mix[] = {
552 	SOC_DAPM_SINGLE_AUTODISABLE("I043 Switch", AFE_CONN93_1, 11, 1, 0),
553 	SOC_DAPM_SINGLE_AUTODISABLE("I067 Switch", AFE_CONN93_2, 3, 1, 0),
554 };
555 
556 static const struct snd_kcontrol_new mtk_dai_etdm_o094_mix[] = {
557 	SOC_DAPM_SINGLE_AUTODISABLE("I044 Switch", AFE_CONN94_1, 12, 1, 0),
558 	SOC_DAPM_SINGLE_AUTODISABLE("I068 Switch", AFE_CONN94_2, 4, 1, 0),
559 };
560 
561 static const struct snd_kcontrol_new mtk_dai_etdm_o095_mix[] = {
562 	SOC_DAPM_SINGLE_AUTODISABLE("I045 Switch", AFE_CONN95_1, 13, 1, 0),
563 	SOC_DAPM_SINGLE_AUTODISABLE("I069 Switch", AFE_CONN95_2, 5, 1, 0),
564 };
565 
566 static const char * const mt8195_etdm_clk_src_sel_text[] = {
567 	"26m",
568 	"a1sys_a2sys",
569 	"a3sys",
570 	"a4sys",
571 };
572 
573 static SOC_ENUM_SINGLE_EXT_DECL(etdmout_clk_src_enum,
574 	mt8195_etdm_clk_src_sel_text);
575 
576 static const char * const hdmitx_dptx_mux_map[] = {
577 	"Disconnect", "Connect",
578 };
579 
580 static int hdmitx_dptx_mux_map_value[] = {
581 	0, 1,
582 };
583 
584 /* HDMI_OUT_MUX */
585 static SOC_VALUE_ENUM_SINGLE_AUTODISABLE_DECL(hdmi_out_mux_map_enum,
586 				SND_SOC_NOPM,
587 				0,
588 				1,
589 				hdmitx_dptx_mux_map,
590 				hdmitx_dptx_mux_map_value);
591 
592 static const struct snd_kcontrol_new hdmi_out_mux_control =
593 	SOC_DAPM_ENUM("HDMI_OUT_MUX", hdmi_out_mux_map_enum);
594 
595 /* DPTX_OUT_MUX */
596 static SOC_VALUE_ENUM_SINGLE_AUTODISABLE_DECL(dptx_out_mux_map_enum,
597 				SND_SOC_NOPM,
598 				0,
599 				1,
600 				hdmitx_dptx_mux_map,
601 				hdmitx_dptx_mux_map_value);
602 
603 static const struct snd_kcontrol_new dptx_out_mux_control =
604 	SOC_DAPM_ENUM("DPTX_OUT_MUX", dptx_out_mux_map_enum);
605 
606 /* HDMI_CH0_MUX ~ HDMI_CH7_MUX */
607 static const char *const afe_conn_hdmi_mux_map[] = {
608 	"CH0", "CH1", "CH2", "CH3", "CH4", "CH5", "CH6", "CH7",
609 };
610 
611 static int afe_conn_hdmi_mux_map_value[] = {
612 	0, 1, 2, 3, 4, 5, 6, 7,
613 };
614 
615 static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch0_mux_map_enum,
616 				AFE_TDMOUT_CONN0,
617 				0,
618 				0xf,
619 				afe_conn_hdmi_mux_map,
620 				afe_conn_hdmi_mux_map_value);
621 
622 static const struct snd_kcontrol_new hdmi_ch0_mux_control =
623 	SOC_DAPM_ENUM("HDMI_CH0_MUX", hdmi_ch0_mux_map_enum);
624 
625 static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch1_mux_map_enum,
626 				AFE_TDMOUT_CONN0,
627 				4,
628 				0xf,
629 				afe_conn_hdmi_mux_map,
630 				afe_conn_hdmi_mux_map_value);
631 
632 static const struct snd_kcontrol_new hdmi_ch1_mux_control =
633 	SOC_DAPM_ENUM("HDMI_CH1_MUX", hdmi_ch1_mux_map_enum);
634 
635 static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch2_mux_map_enum,
636 				AFE_TDMOUT_CONN0,
637 				8,
638 				0xf,
639 				afe_conn_hdmi_mux_map,
640 				afe_conn_hdmi_mux_map_value);
641 
642 static const struct snd_kcontrol_new hdmi_ch2_mux_control =
643 	SOC_DAPM_ENUM("HDMI_CH2_MUX", hdmi_ch2_mux_map_enum);
644 
645 static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch3_mux_map_enum,
646 				AFE_TDMOUT_CONN0,
647 				12,
648 				0xf,
649 				afe_conn_hdmi_mux_map,
650 				afe_conn_hdmi_mux_map_value);
651 
652 static const struct snd_kcontrol_new hdmi_ch3_mux_control =
653 	SOC_DAPM_ENUM("HDMI_CH3_MUX", hdmi_ch3_mux_map_enum);
654 
655 static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch4_mux_map_enum,
656 				AFE_TDMOUT_CONN0,
657 				16,
658 				0xf,
659 				afe_conn_hdmi_mux_map,
660 				afe_conn_hdmi_mux_map_value);
661 
662 static const struct snd_kcontrol_new hdmi_ch4_mux_control =
663 	SOC_DAPM_ENUM("HDMI_CH4_MUX", hdmi_ch4_mux_map_enum);
664 
665 static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch5_mux_map_enum,
666 				AFE_TDMOUT_CONN0,
667 				20,
668 				0xf,
669 				afe_conn_hdmi_mux_map,
670 				afe_conn_hdmi_mux_map_value);
671 
672 static const struct snd_kcontrol_new hdmi_ch5_mux_control =
673 	SOC_DAPM_ENUM("HDMI_CH5_MUX", hdmi_ch5_mux_map_enum);
674 
675 static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch6_mux_map_enum,
676 				AFE_TDMOUT_CONN0,
677 				24,
678 				0xf,
679 				afe_conn_hdmi_mux_map,
680 				afe_conn_hdmi_mux_map_value);
681 
682 static const struct snd_kcontrol_new hdmi_ch6_mux_control =
683 	SOC_DAPM_ENUM("HDMI_CH6_MUX", hdmi_ch6_mux_map_enum);
684 
685 static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch7_mux_map_enum,
686 				AFE_TDMOUT_CONN0,
687 				28,
688 				0xf,
689 				afe_conn_hdmi_mux_map,
690 				afe_conn_hdmi_mux_map_value);
691 
692 static const struct snd_kcontrol_new hdmi_ch7_mux_control =
693 	SOC_DAPM_ENUM("HDMI_CH7_MUX", hdmi_ch7_mux_map_enum);
694 
mt8195_etdm_clk_src_sel_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)695 static int mt8195_etdm_clk_src_sel_put(struct snd_kcontrol *kcontrol,
696 				       struct snd_ctl_elem_value *ucontrol)
697 {
698 	struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
699 	struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
700 	struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
701 	unsigned int source = ucontrol->value.enumerated.item[0];
702 	unsigned int val;
703 	unsigned int mask;
704 	unsigned int reg;
705 
706 	if (source >= e->items)
707 		return -EINVAL;
708 
709 	reg = 0;
710 	if (!strcmp(kcontrol->id.name, "ETDM_OUT1_Clock_Source")) {
711 		reg = ETDM_OUT1_CON4;
712 		mask = ETDM_OUT_CON4_CLOCK_MASK;
713 		val = ETDM_OUT_CON4_CLOCK(source);
714 	} else if (!strcmp(kcontrol->id.name, "ETDM_OUT2_Clock_Source")) {
715 		reg = ETDM_OUT2_CON4;
716 		mask = ETDM_OUT_CON4_CLOCK_MASK;
717 		val = ETDM_OUT_CON4_CLOCK(source);
718 	} else if (!strcmp(kcontrol->id.name, "ETDM_OUT3_Clock_Source")) {
719 		reg = ETDM_OUT3_CON4;
720 		mask = ETDM_OUT_CON4_CLOCK_MASK;
721 		val = ETDM_OUT_CON4_CLOCK(source);
722 	} else if (!strcmp(kcontrol->id.name, "ETDM_IN1_Clock_Source")) {
723 		reg = ETDM_IN1_CON2;
724 		mask = ETDM_IN_CON2_CLOCK_MASK;
725 		val = ETDM_IN_CON2_CLOCK(source);
726 	} else if (!strcmp(kcontrol->id.name, "ETDM_IN2_Clock_Source")) {
727 		reg = ETDM_IN2_CON2;
728 		mask = ETDM_IN_CON2_CLOCK_MASK;
729 		val = ETDM_IN_CON2_CLOCK(source);
730 	}
731 
732 	if (reg)
733 		regmap_update_bits(afe->regmap, reg, mask, val);
734 
735 	return 0;
736 }
737 
mt8195_etdm_clk_src_sel_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)738 static int mt8195_etdm_clk_src_sel_get(struct snd_kcontrol *kcontrol,
739 				       struct snd_ctl_elem_value *ucontrol)
740 {
741 	struct snd_soc_component *component =
742 		snd_soc_kcontrol_component(kcontrol);
743 	struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
744 	unsigned int value = 0;
745 	unsigned int reg = 0;
746 	unsigned int mask = 0;
747 	unsigned int shift = 0;
748 
749 	if (!strcmp(kcontrol->id.name, "ETDM_OUT1_Clock_Source")) {
750 		reg = ETDM_OUT1_CON4;
751 		mask = ETDM_OUT_CON4_CLOCK_MASK;
752 		shift = ETDM_OUT_CON4_CLOCK_SHIFT;
753 	} else if (!strcmp(kcontrol->id.name, "ETDM_OUT2_Clock_Source")) {
754 		reg = ETDM_OUT2_CON4;
755 		mask = ETDM_OUT_CON4_CLOCK_MASK;
756 		shift = ETDM_OUT_CON4_CLOCK_SHIFT;
757 	} else if (!strcmp(kcontrol->id.name, "ETDM_OUT3_Clock_Source")) {
758 		reg = ETDM_OUT3_CON4;
759 		mask = ETDM_OUT_CON4_CLOCK_MASK;
760 		shift = ETDM_OUT_CON4_CLOCK_SHIFT;
761 	} else if (!strcmp(kcontrol->id.name, "ETDM_IN1_Clock_Source")) {
762 		reg = ETDM_IN1_CON2;
763 		mask = ETDM_IN_CON2_CLOCK_MASK;
764 		shift = ETDM_IN_CON2_CLOCK_SHIFT;
765 	} else if (!strcmp(kcontrol->id.name, "ETDM_IN2_Clock_Source")) {
766 		reg = ETDM_IN2_CON2;
767 		mask = ETDM_IN_CON2_CLOCK_MASK;
768 		shift = ETDM_IN_CON2_CLOCK_SHIFT;
769 	}
770 
771 	if (reg)
772 		regmap_read(afe->regmap, reg, &value);
773 
774 	value &= mask;
775 	value >>= shift;
776 	ucontrol->value.enumerated.item[0] = value;
777 	return 0;
778 }
779 
780 static const struct snd_kcontrol_new mtk_dai_etdm_controls[] = {
781 	SOC_ENUM_EXT("ETDM_OUT1_Clock_Source",
782 		     etdmout_clk_src_enum,
783 		     mt8195_etdm_clk_src_sel_get,
784 		     mt8195_etdm_clk_src_sel_put),
785 	SOC_ENUM_EXT("ETDM_OUT2_Clock_Source",
786 		     etdmout_clk_src_enum,
787 		     mt8195_etdm_clk_src_sel_get,
788 		     mt8195_etdm_clk_src_sel_put),
789 	SOC_ENUM_EXT("ETDM_OUT3_Clock_Source",
790 		     etdmout_clk_src_enum,
791 		     mt8195_etdm_clk_src_sel_get,
792 		     mt8195_etdm_clk_src_sel_put),
793 	SOC_ENUM_EXT("ETDM_IN1_Clock_Source",
794 		     etdmout_clk_src_enum,
795 		     mt8195_etdm_clk_src_sel_get,
796 		     mt8195_etdm_clk_src_sel_put),
797 	SOC_ENUM_EXT("ETDM_IN2_Clock_Source",
798 		     etdmout_clk_src_enum,
799 		     mt8195_etdm_clk_src_sel_get,
800 		     mt8195_etdm_clk_src_sel_put),
801 };
802 
803 static const struct snd_soc_dapm_widget mtk_dai_etdm_widgets[] = {
804 	/* eTDM_IN2 */
805 	SND_SOC_DAPM_MIXER("I012", SND_SOC_NOPM, 0, 0, NULL, 0),
806 	SND_SOC_DAPM_MIXER("I013", SND_SOC_NOPM, 0, 0, NULL, 0),
807 	SND_SOC_DAPM_MIXER("I014", SND_SOC_NOPM, 0, 0, NULL, 0),
808 	SND_SOC_DAPM_MIXER("I015", SND_SOC_NOPM, 0, 0, NULL, 0),
809 	SND_SOC_DAPM_MIXER("I016", SND_SOC_NOPM, 0, 0, NULL, 0),
810 	SND_SOC_DAPM_MIXER("I017", SND_SOC_NOPM, 0, 0, NULL, 0),
811 	SND_SOC_DAPM_MIXER("I018", SND_SOC_NOPM, 0, 0, NULL, 0),
812 	SND_SOC_DAPM_MIXER("I019", SND_SOC_NOPM, 0, 0, NULL, 0),
813 
814 	/* eTDM_IN1 */
815 	SND_SOC_DAPM_MIXER("I072", SND_SOC_NOPM, 0, 0, NULL, 0),
816 	SND_SOC_DAPM_MIXER("I073", SND_SOC_NOPM, 0, 0, NULL, 0),
817 	SND_SOC_DAPM_MIXER("I074", SND_SOC_NOPM, 0, 0, NULL, 0),
818 	SND_SOC_DAPM_MIXER("I075", SND_SOC_NOPM, 0, 0, NULL, 0),
819 	SND_SOC_DAPM_MIXER("I076", SND_SOC_NOPM, 0, 0, NULL, 0),
820 	SND_SOC_DAPM_MIXER("I077", SND_SOC_NOPM, 0, 0, NULL, 0),
821 	SND_SOC_DAPM_MIXER("I078", SND_SOC_NOPM, 0, 0, NULL, 0),
822 	SND_SOC_DAPM_MIXER("I079", SND_SOC_NOPM, 0, 0, NULL, 0),
823 	SND_SOC_DAPM_MIXER("I080", SND_SOC_NOPM, 0, 0, NULL, 0),
824 	SND_SOC_DAPM_MIXER("I081", SND_SOC_NOPM, 0, 0, NULL, 0),
825 	SND_SOC_DAPM_MIXER("I082", SND_SOC_NOPM, 0, 0, NULL, 0),
826 	SND_SOC_DAPM_MIXER("I083", SND_SOC_NOPM, 0, 0, NULL, 0),
827 	SND_SOC_DAPM_MIXER("I084", SND_SOC_NOPM, 0, 0, NULL, 0),
828 	SND_SOC_DAPM_MIXER("I085", SND_SOC_NOPM, 0, 0, NULL, 0),
829 	SND_SOC_DAPM_MIXER("I086", SND_SOC_NOPM, 0, 0, NULL, 0),
830 	SND_SOC_DAPM_MIXER("I087", SND_SOC_NOPM, 0, 0, NULL, 0),
831 	SND_SOC_DAPM_MIXER("I088", SND_SOC_NOPM, 0, 0, NULL, 0),
832 	SND_SOC_DAPM_MIXER("I089", SND_SOC_NOPM, 0, 0, NULL, 0),
833 	SND_SOC_DAPM_MIXER("I090", SND_SOC_NOPM, 0, 0, NULL, 0),
834 	SND_SOC_DAPM_MIXER("I091", SND_SOC_NOPM, 0, 0, NULL, 0),
835 	SND_SOC_DAPM_MIXER("I092", SND_SOC_NOPM, 0, 0, NULL, 0),
836 	SND_SOC_DAPM_MIXER("I093", SND_SOC_NOPM, 0, 0, NULL, 0),
837 	SND_SOC_DAPM_MIXER("I094", SND_SOC_NOPM, 0, 0, NULL, 0),
838 	SND_SOC_DAPM_MIXER("I095", SND_SOC_NOPM, 0, 0, NULL, 0),
839 
840 	/* eTDM_OUT2 */
841 	SND_SOC_DAPM_MIXER("O048", SND_SOC_NOPM, 0, 0,
842 			   mtk_dai_etdm_o048_mix,
843 			   ARRAY_SIZE(mtk_dai_etdm_o048_mix)),
844 	SND_SOC_DAPM_MIXER("O049", SND_SOC_NOPM, 0, 0,
845 			   mtk_dai_etdm_o049_mix,
846 			   ARRAY_SIZE(mtk_dai_etdm_o049_mix)),
847 	SND_SOC_DAPM_MIXER("O050", SND_SOC_NOPM, 0, 0,
848 			   mtk_dai_etdm_o050_mix,
849 			   ARRAY_SIZE(mtk_dai_etdm_o050_mix)),
850 	SND_SOC_DAPM_MIXER("O051", SND_SOC_NOPM, 0, 0,
851 			   mtk_dai_etdm_o051_mix,
852 			   ARRAY_SIZE(mtk_dai_etdm_o051_mix)),
853 	SND_SOC_DAPM_MIXER("O052", SND_SOC_NOPM, 0, 0,
854 			   mtk_dai_etdm_o052_mix,
855 			   ARRAY_SIZE(mtk_dai_etdm_o052_mix)),
856 	SND_SOC_DAPM_MIXER("O053", SND_SOC_NOPM, 0, 0,
857 			   mtk_dai_etdm_o053_mix,
858 			   ARRAY_SIZE(mtk_dai_etdm_o053_mix)),
859 	SND_SOC_DAPM_MIXER("O054", SND_SOC_NOPM, 0, 0,
860 			   mtk_dai_etdm_o054_mix,
861 			   ARRAY_SIZE(mtk_dai_etdm_o054_mix)),
862 	SND_SOC_DAPM_MIXER("O055", SND_SOC_NOPM, 0, 0,
863 			   mtk_dai_etdm_o055_mix,
864 			   ARRAY_SIZE(mtk_dai_etdm_o055_mix)),
865 	SND_SOC_DAPM_MIXER("O056", SND_SOC_NOPM, 0, 0,
866 			   mtk_dai_etdm_o056_mix,
867 			   ARRAY_SIZE(mtk_dai_etdm_o056_mix)),
868 	SND_SOC_DAPM_MIXER("O057", SND_SOC_NOPM, 0, 0,
869 			   mtk_dai_etdm_o057_mix,
870 			   ARRAY_SIZE(mtk_dai_etdm_o057_mix)),
871 	SND_SOC_DAPM_MIXER("O058", SND_SOC_NOPM, 0, 0,
872 			   mtk_dai_etdm_o058_mix,
873 			   ARRAY_SIZE(mtk_dai_etdm_o058_mix)),
874 	SND_SOC_DAPM_MIXER("O059", SND_SOC_NOPM, 0, 0,
875 			   mtk_dai_etdm_o059_mix,
876 			   ARRAY_SIZE(mtk_dai_etdm_o059_mix)),
877 	SND_SOC_DAPM_MIXER("O060", SND_SOC_NOPM, 0, 0,
878 			   mtk_dai_etdm_o060_mix,
879 			   ARRAY_SIZE(mtk_dai_etdm_o060_mix)),
880 	SND_SOC_DAPM_MIXER("O061", SND_SOC_NOPM, 0, 0,
881 			   mtk_dai_etdm_o061_mix,
882 			   ARRAY_SIZE(mtk_dai_etdm_o061_mix)),
883 	SND_SOC_DAPM_MIXER("O062", SND_SOC_NOPM, 0, 0,
884 			   mtk_dai_etdm_o062_mix,
885 			   ARRAY_SIZE(mtk_dai_etdm_o062_mix)),
886 	SND_SOC_DAPM_MIXER("O063", SND_SOC_NOPM, 0, 0,
887 			   mtk_dai_etdm_o063_mix,
888 			   ARRAY_SIZE(mtk_dai_etdm_o063_mix)),
889 	SND_SOC_DAPM_MIXER("O064", SND_SOC_NOPM, 0, 0,
890 			   mtk_dai_etdm_o064_mix,
891 			   ARRAY_SIZE(mtk_dai_etdm_o064_mix)),
892 	SND_SOC_DAPM_MIXER("O065", SND_SOC_NOPM, 0, 0,
893 			   mtk_dai_etdm_o065_mix,
894 			   ARRAY_SIZE(mtk_dai_etdm_o065_mix)),
895 	SND_SOC_DAPM_MIXER("O066", SND_SOC_NOPM, 0, 0,
896 			   mtk_dai_etdm_o066_mix,
897 			   ARRAY_SIZE(mtk_dai_etdm_o066_mix)),
898 	SND_SOC_DAPM_MIXER("O067", SND_SOC_NOPM, 0, 0,
899 			   mtk_dai_etdm_o067_mix,
900 			   ARRAY_SIZE(mtk_dai_etdm_o067_mix)),
901 	SND_SOC_DAPM_MIXER("O068", SND_SOC_NOPM, 0, 0,
902 			   mtk_dai_etdm_o068_mix,
903 			   ARRAY_SIZE(mtk_dai_etdm_o068_mix)),
904 	SND_SOC_DAPM_MIXER("O069", SND_SOC_NOPM, 0, 0,
905 			   mtk_dai_etdm_o069_mix,
906 			   ARRAY_SIZE(mtk_dai_etdm_o069_mix)),
907 	SND_SOC_DAPM_MIXER("O070", SND_SOC_NOPM, 0, 0,
908 			   mtk_dai_etdm_o070_mix,
909 			   ARRAY_SIZE(mtk_dai_etdm_o070_mix)),
910 	SND_SOC_DAPM_MIXER("O071", SND_SOC_NOPM, 0, 0,
911 			   mtk_dai_etdm_o071_mix,
912 			   ARRAY_SIZE(mtk_dai_etdm_o071_mix)),
913 
914 	/* eTDM_OUT1 */
915 	SND_SOC_DAPM_MIXER("O072", SND_SOC_NOPM, 0, 0,
916 			   mtk_dai_etdm_o072_mix,
917 			   ARRAY_SIZE(mtk_dai_etdm_o072_mix)),
918 	SND_SOC_DAPM_MIXER("O073", SND_SOC_NOPM, 0, 0,
919 			   mtk_dai_etdm_o073_mix,
920 			   ARRAY_SIZE(mtk_dai_etdm_o073_mix)),
921 	SND_SOC_DAPM_MIXER("O074", SND_SOC_NOPM, 0, 0,
922 			   mtk_dai_etdm_o074_mix,
923 			   ARRAY_SIZE(mtk_dai_etdm_o074_mix)),
924 	SND_SOC_DAPM_MIXER("O075", SND_SOC_NOPM, 0, 0,
925 			   mtk_dai_etdm_o075_mix,
926 			   ARRAY_SIZE(mtk_dai_etdm_o075_mix)),
927 	SND_SOC_DAPM_MIXER("O076", SND_SOC_NOPM, 0, 0,
928 			   mtk_dai_etdm_o076_mix,
929 			   ARRAY_SIZE(mtk_dai_etdm_o076_mix)),
930 	SND_SOC_DAPM_MIXER("O077", SND_SOC_NOPM, 0, 0,
931 			   mtk_dai_etdm_o077_mix,
932 			   ARRAY_SIZE(mtk_dai_etdm_o077_mix)),
933 	SND_SOC_DAPM_MIXER("O078", SND_SOC_NOPM, 0, 0,
934 			   mtk_dai_etdm_o078_mix,
935 			   ARRAY_SIZE(mtk_dai_etdm_o078_mix)),
936 	SND_SOC_DAPM_MIXER("O079", SND_SOC_NOPM, 0, 0,
937 			   mtk_dai_etdm_o079_mix,
938 			   ARRAY_SIZE(mtk_dai_etdm_o079_mix)),
939 	SND_SOC_DAPM_MIXER("O080", SND_SOC_NOPM, 0, 0,
940 			   mtk_dai_etdm_o080_mix,
941 			   ARRAY_SIZE(mtk_dai_etdm_o080_mix)),
942 	SND_SOC_DAPM_MIXER("O081", SND_SOC_NOPM, 0, 0,
943 			   mtk_dai_etdm_o081_mix,
944 			   ARRAY_SIZE(mtk_dai_etdm_o081_mix)),
945 	SND_SOC_DAPM_MIXER("O082", SND_SOC_NOPM, 0, 0,
946 			   mtk_dai_etdm_o082_mix,
947 			   ARRAY_SIZE(mtk_dai_etdm_o082_mix)),
948 	SND_SOC_DAPM_MIXER("O083", SND_SOC_NOPM, 0, 0,
949 			   mtk_dai_etdm_o083_mix,
950 			   ARRAY_SIZE(mtk_dai_etdm_o083_mix)),
951 	SND_SOC_DAPM_MIXER("O084", SND_SOC_NOPM, 0, 0,
952 			   mtk_dai_etdm_o084_mix,
953 			   ARRAY_SIZE(mtk_dai_etdm_o084_mix)),
954 	SND_SOC_DAPM_MIXER("O085", SND_SOC_NOPM, 0, 0,
955 			   mtk_dai_etdm_o085_mix,
956 			   ARRAY_SIZE(mtk_dai_etdm_o085_mix)),
957 	SND_SOC_DAPM_MIXER("O086", SND_SOC_NOPM, 0, 0,
958 			   mtk_dai_etdm_o086_mix,
959 			   ARRAY_SIZE(mtk_dai_etdm_o086_mix)),
960 	SND_SOC_DAPM_MIXER("O087", SND_SOC_NOPM, 0, 0,
961 			   mtk_dai_etdm_o087_mix,
962 			   ARRAY_SIZE(mtk_dai_etdm_o087_mix)),
963 	SND_SOC_DAPM_MIXER("O088", SND_SOC_NOPM, 0, 0,
964 			   mtk_dai_etdm_o088_mix,
965 			   ARRAY_SIZE(mtk_dai_etdm_o088_mix)),
966 	SND_SOC_DAPM_MIXER("O089", SND_SOC_NOPM, 0, 0,
967 			   mtk_dai_etdm_o089_mix,
968 			   ARRAY_SIZE(mtk_dai_etdm_o089_mix)),
969 	SND_SOC_DAPM_MIXER("O090", SND_SOC_NOPM, 0, 0,
970 			   mtk_dai_etdm_o090_mix,
971 			   ARRAY_SIZE(mtk_dai_etdm_o090_mix)),
972 	SND_SOC_DAPM_MIXER("O091", SND_SOC_NOPM, 0, 0,
973 			   mtk_dai_etdm_o091_mix,
974 			   ARRAY_SIZE(mtk_dai_etdm_o091_mix)),
975 	SND_SOC_DAPM_MIXER("O092", SND_SOC_NOPM, 0, 0,
976 			   mtk_dai_etdm_o092_mix,
977 			   ARRAY_SIZE(mtk_dai_etdm_o092_mix)),
978 	SND_SOC_DAPM_MIXER("O093", SND_SOC_NOPM, 0, 0,
979 			   mtk_dai_etdm_o093_mix,
980 			   ARRAY_SIZE(mtk_dai_etdm_o093_mix)),
981 	SND_SOC_DAPM_MIXER("O094", SND_SOC_NOPM, 0, 0,
982 			   mtk_dai_etdm_o094_mix,
983 			   ARRAY_SIZE(mtk_dai_etdm_o094_mix)),
984 	SND_SOC_DAPM_MIXER("O095", SND_SOC_NOPM, 0, 0,
985 			   mtk_dai_etdm_o095_mix,
986 			   ARRAY_SIZE(mtk_dai_etdm_o095_mix)),
987 
988 	/* eTDM_OUT3 */
989 	SND_SOC_DAPM_MUX("HDMI_OUT_MUX", SND_SOC_NOPM, 0, 0,
990 			 &hdmi_out_mux_control),
991 	SND_SOC_DAPM_MUX("DPTX_OUT_MUX", SND_SOC_NOPM, 0, 0,
992 			 &dptx_out_mux_control),
993 
994 	SND_SOC_DAPM_MUX("HDMI_CH0_MUX", SND_SOC_NOPM, 0, 0,
995 			 &hdmi_ch0_mux_control),
996 	SND_SOC_DAPM_MUX("HDMI_CH1_MUX", SND_SOC_NOPM, 0, 0,
997 			 &hdmi_ch1_mux_control),
998 	SND_SOC_DAPM_MUX("HDMI_CH2_MUX", SND_SOC_NOPM, 0, 0,
999 			 &hdmi_ch2_mux_control),
1000 	SND_SOC_DAPM_MUX("HDMI_CH3_MUX", SND_SOC_NOPM, 0, 0,
1001 			 &hdmi_ch3_mux_control),
1002 	SND_SOC_DAPM_MUX("HDMI_CH4_MUX", SND_SOC_NOPM, 0, 0,
1003 			 &hdmi_ch4_mux_control),
1004 	SND_SOC_DAPM_MUX("HDMI_CH5_MUX", SND_SOC_NOPM, 0, 0,
1005 			 &hdmi_ch5_mux_control),
1006 	SND_SOC_DAPM_MUX("HDMI_CH6_MUX", SND_SOC_NOPM, 0, 0,
1007 			 &hdmi_ch6_mux_control),
1008 	SND_SOC_DAPM_MUX("HDMI_CH7_MUX", SND_SOC_NOPM, 0, 0,
1009 			 &hdmi_ch7_mux_control),
1010 
1011 	SND_SOC_DAPM_INPUT("ETDM_INPUT"),
1012 	SND_SOC_DAPM_OUTPUT("ETDM_OUTPUT"),
1013 };
1014 
1015 static const struct snd_soc_dapm_route mtk_dai_etdm_routes[] = {
1016 	{"I012", NULL, "ETDM2 Capture"},
1017 	{"I013", NULL, "ETDM2 Capture"},
1018 	{"I014", NULL, "ETDM2 Capture"},
1019 	{"I015", NULL, "ETDM2 Capture"},
1020 	{"I016", NULL, "ETDM2 Capture"},
1021 	{"I017", NULL, "ETDM2 Capture"},
1022 	{"I018", NULL, "ETDM2 Capture"},
1023 	{"I019", NULL, "ETDM2 Capture"},
1024 
1025 	{"I072", NULL, "ETDM1 Capture"},
1026 	{"I073", NULL, "ETDM1 Capture"},
1027 	{"I074", NULL, "ETDM1 Capture"},
1028 	{"I075", NULL, "ETDM1 Capture"},
1029 	{"I076", NULL, "ETDM1 Capture"},
1030 	{"I077", NULL, "ETDM1 Capture"},
1031 	{"I078", NULL, "ETDM1 Capture"},
1032 	{"I079", NULL, "ETDM1 Capture"},
1033 	{"I080", NULL, "ETDM1 Capture"},
1034 	{"I081", NULL, "ETDM1 Capture"},
1035 	{"I082", NULL, "ETDM1 Capture"},
1036 	{"I083", NULL, "ETDM1 Capture"},
1037 	{"I084", NULL, "ETDM1 Capture"},
1038 	{"I085", NULL, "ETDM1 Capture"},
1039 	{"I086", NULL, "ETDM1 Capture"},
1040 	{"I087", NULL, "ETDM1 Capture"},
1041 	{"I088", NULL, "ETDM1 Capture"},
1042 	{"I089", NULL, "ETDM1 Capture"},
1043 	{"I090", NULL, "ETDM1 Capture"},
1044 	{"I091", NULL, "ETDM1 Capture"},
1045 	{"I092", NULL, "ETDM1 Capture"},
1046 	{"I093", NULL, "ETDM1 Capture"},
1047 	{"I094", NULL, "ETDM1 Capture"},
1048 	{"I095", NULL, "ETDM1 Capture"},
1049 
1050 	{"UL8", NULL, "ETDM1 Capture"},
1051 	{"UL3", NULL, "ETDM2 Capture"},
1052 
1053 	{"ETDM2 Playback", NULL, "O048"},
1054 	{"ETDM2 Playback", NULL, "O049"},
1055 	{"ETDM2 Playback", NULL, "O050"},
1056 	{"ETDM2 Playback", NULL, "O051"},
1057 	{"ETDM2 Playback", NULL, "O052"},
1058 	{"ETDM2 Playback", NULL, "O053"},
1059 	{"ETDM2 Playback", NULL, "O054"},
1060 	{"ETDM2 Playback", NULL, "O055"},
1061 	{"ETDM2 Playback", NULL, "O056"},
1062 	{"ETDM2 Playback", NULL, "O057"},
1063 	{"ETDM2 Playback", NULL, "O058"},
1064 	{"ETDM2 Playback", NULL, "O059"},
1065 	{"ETDM2 Playback", NULL, "O060"},
1066 	{"ETDM2 Playback", NULL, "O061"},
1067 	{"ETDM2 Playback", NULL, "O062"},
1068 	{"ETDM2 Playback", NULL, "O063"},
1069 	{"ETDM2 Playback", NULL, "O064"},
1070 	{"ETDM2 Playback", NULL, "O065"},
1071 	{"ETDM2 Playback", NULL, "O066"},
1072 	{"ETDM2 Playback", NULL, "O067"},
1073 	{"ETDM2 Playback", NULL, "O068"},
1074 	{"ETDM2 Playback", NULL, "O069"},
1075 	{"ETDM2 Playback", NULL, "O070"},
1076 	{"ETDM2 Playback", NULL, "O071"},
1077 
1078 	{"ETDM1 Playback", NULL, "O072"},
1079 	{"ETDM1 Playback", NULL, "O073"},
1080 	{"ETDM1 Playback", NULL, "O074"},
1081 	{"ETDM1 Playback", NULL, "O075"},
1082 	{"ETDM1 Playback", NULL, "O076"},
1083 	{"ETDM1 Playback", NULL, "O077"},
1084 	{"ETDM1 Playback", NULL, "O078"},
1085 	{"ETDM1 Playback", NULL, "O079"},
1086 	{"ETDM1 Playback", NULL, "O080"},
1087 	{"ETDM1 Playback", NULL, "O081"},
1088 	{"ETDM1 Playback", NULL, "O082"},
1089 	{"ETDM1 Playback", NULL, "O083"},
1090 	{"ETDM1 Playback", NULL, "O084"},
1091 	{"ETDM1 Playback", NULL, "O085"},
1092 	{"ETDM1 Playback", NULL, "O086"},
1093 	{"ETDM1 Playback", NULL, "O087"},
1094 	{"ETDM1 Playback", NULL, "O088"},
1095 	{"ETDM1 Playback", NULL, "O089"},
1096 	{"ETDM1 Playback", NULL, "O090"},
1097 	{"ETDM1 Playback", NULL, "O091"},
1098 	{"ETDM1 Playback", NULL, "O092"},
1099 	{"ETDM1 Playback", NULL, "O093"},
1100 	{"ETDM1 Playback", NULL, "O094"},
1101 	{"ETDM1 Playback", NULL, "O095"},
1102 
1103 	{"O048", "I020 Switch", "I020"},
1104 	{"O049", "I021 Switch", "I021"},
1105 
1106 	{"O048", "I022 Switch", "I022"},
1107 	{"O049", "I023 Switch", "I023"},
1108 	{"O050", "I024 Switch", "I024"},
1109 	{"O051", "I025 Switch", "I025"},
1110 	{"O052", "I026 Switch", "I026"},
1111 	{"O053", "I027 Switch", "I027"},
1112 	{"O054", "I028 Switch", "I028"},
1113 	{"O055", "I029 Switch", "I029"},
1114 	{"O056", "I030 Switch", "I030"},
1115 	{"O057", "I031 Switch", "I031"},
1116 	{"O058", "I032 Switch", "I032"},
1117 	{"O059", "I033 Switch", "I033"},
1118 	{"O060", "I034 Switch", "I034"},
1119 	{"O061", "I035 Switch", "I035"},
1120 	{"O062", "I036 Switch", "I036"},
1121 	{"O063", "I037 Switch", "I037"},
1122 	{"O064", "I038 Switch", "I038"},
1123 	{"O065", "I039 Switch", "I039"},
1124 	{"O066", "I040 Switch", "I040"},
1125 	{"O067", "I041 Switch", "I041"},
1126 	{"O068", "I042 Switch", "I042"},
1127 	{"O069", "I043 Switch", "I043"},
1128 	{"O070", "I044 Switch", "I044"},
1129 	{"O071", "I045 Switch", "I045"},
1130 
1131 	{"O048", "I046 Switch", "I046"},
1132 	{"O049", "I047 Switch", "I047"},
1133 	{"O050", "I048 Switch", "I048"},
1134 	{"O051", "I049 Switch", "I049"},
1135 	{"O052", "I050 Switch", "I050"},
1136 	{"O053", "I051 Switch", "I051"},
1137 	{"O054", "I052 Switch", "I052"},
1138 	{"O055", "I053 Switch", "I053"},
1139 	{"O056", "I054 Switch", "I054"},
1140 	{"O057", "I055 Switch", "I055"},
1141 	{"O058", "I056 Switch", "I056"},
1142 	{"O059", "I057 Switch", "I057"},
1143 	{"O060", "I058 Switch", "I058"},
1144 	{"O061", "I059 Switch", "I059"},
1145 	{"O062", "I060 Switch", "I060"},
1146 	{"O063", "I061 Switch", "I061"},
1147 	{"O064", "I062 Switch", "I062"},
1148 	{"O065", "I063 Switch", "I063"},
1149 	{"O066", "I064 Switch", "I064"},
1150 	{"O067", "I065 Switch", "I065"},
1151 	{"O068", "I066 Switch", "I066"},
1152 	{"O069", "I067 Switch", "I067"},
1153 	{"O070", "I068 Switch", "I068"},
1154 	{"O071", "I069 Switch", "I069"},
1155 
1156 	{"O048", "I070 Switch", "I070"},
1157 	{"O049", "I071 Switch", "I071"},
1158 
1159 	{"O072", "I020 Switch", "I020"},
1160 	{"O073", "I021 Switch", "I021"},
1161 
1162 	{"O072", "I022 Switch", "I022"},
1163 	{"O073", "I023 Switch", "I023"},
1164 	{"O074", "I024 Switch", "I024"},
1165 	{"O075", "I025 Switch", "I025"},
1166 	{"O076", "I026 Switch", "I026"},
1167 	{"O077", "I027 Switch", "I027"},
1168 	{"O078", "I028 Switch", "I028"},
1169 	{"O079", "I029 Switch", "I029"},
1170 	{"O080", "I030 Switch", "I030"},
1171 	{"O081", "I031 Switch", "I031"},
1172 	{"O082", "I032 Switch", "I032"},
1173 	{"O083", "I033 Switch", "I033"},
1174 	{"O084", "I034 Switch", "I034"},
1175 	{"O085", "I035 Switch", "I035"},
1176 	{"O086", "I036 Switch", "I036"},
1177 	{"O087", "I037 Switch", "I037"},
1178 	{"O088", "I038 Switch", "I038"},
1179 	{"O089", "I039 Switch", "I039"},
1180 	{"O090", "I040 Switch", "I040"},
1181 	{"O091", "I041 Switch", "I041"},
1182 	{"O092", "I042 Switch", "I042"},
1183 	{"O093", "I043 Switch", "I043"},
1184 	{"O094", "I044 Switch", "I044"},
1185 	{"O095", "I045 Switch", "I045"},
1186 
1187 	{"O072", "I046 Switch", "I046"},
1188 	{"O073", "I047 Switch", "I047"},
1189 	{"O074", "I048 Switch", "I048"},
1190 	{"O075", "I049 Switch", "I049"},
1191 	{"O076", "I050 Switch", "I050"},
1192 	{"O077", "I051 Switch", "I051"},
1193 	{"O078", "I052 Switch", "I052"},
1194 	{"O079", "I053 Switch", "I053"},
1195 	{"O080", "I054 Switch", "I054"},
1196 	{"O081", "I055 Switch", "I055"},
1197 	{"O082", "I056 Switch", "I056"},
1198 	{"O083", "I057 Switch", "I057"},
1199 	{"O084", "I058 Switch", "I058"},
1200 	{"O085", "I059 Switch", "I059"},
1201 	{"O086", "I060 Switch", "I060"},
1202 	{"O087", "I061 Switch", "I061"},
1203 	{"O088", "I062 Switch", "I062"},
1204 	{"O089", "I063 Switch", "I063"},
1205 	{"O090", "I064 Switch", "I064"},
1206 	{"O091", "I065 Switch", "I065"},
1207 	{"O092", "I066 Switch", "I066"},
1208 	{"O093", "I067 Switch", "I067"},
1209 	{"O094", "I068 Switch", "I068"},
1210 	{"O095", "I069 Switch", "I069"},
1211 
1212 	{"O072", "I070 Switch", "I070"},
1213 	{"O073", "I071 Switch", "I071"},
1214 
1215 	{"HDMI_CH0_MUX", "CH0", "DL10"},
1216 	{"HDMI_CH0_MUX", "CH1", "DL10"},
1217 	{"HDMI_CH0_MUX", "CH2", "DL10"},
1218 	{"HDMI_CH0_MUX", "CH3", "DL10"},
1219 	{"HDMI_CH0_MUX", "CH4", "DL10"},
1220 	{"HDMI_CH0_MUX", "CH5", "DL10"},
1221 	{"HDMI_CH0_MUX", "CH6", "DL10"},
1222 	{"HDMI_CH0_MUX", "CH7", "DL10"},
1223 
1224 	{"HDMI_CH1_MUX", "CH0", "DL10"},
1225 	{"HDMI_CH1_MUX", "CH1", "DL10"},
1226 	{"HDMI_CH1_MUX", "CH2", "DL10"},
1227 	{"HDMI_CH1_MUX", "CH3", "DL10"},
1228 	{"HDMI_CH1_MUX", "CH4", "DL10"},
1229 	{"HDMI_CH1_MUX", "CH5", "DL10"},
1230 	{"HDMI_CH1_MUX", "CH6", "DL10"},
1231 	{"HDMI_CH1_MUX", "CH7", "DL10"},
1232 
1233 	{"HDMI_CH2_MUX", "CH0", "DL10"},
1234 	{"HDMI_CH2_MUX", "CH1", "DL10"},
1235 	{"HDMI_CH2_MUX", "CH2", "DL10"},
1236 	{"HDMI_CH2_MUX", "CH3", "DL10"},
1237 	{"HDMI_CH2_MUX", "CH4", "DL10"},
1238 	{"HDMI_CH2_MUX", "CH5", "DL10"},
1239 	{"HDMI_CH2_MUX", "CH6", "DL10"},
1240 	{"HDMI_CH2_MUX", "CH7", "DL10"},
1241 
1242 	{"HDMI_CH3_MUX", "CH0", "DL10"},
1243 	{"HDMI_CH3_MUX", "CH1", "DL10"},
1244 	{"HDMI_CH3_MUX", "CH2", "DL10"},
1245 	{"HDMI_CH3_MUX", "CH3", "DL10"},
1246 	{"HDMI_CH3_MUX", "CH4", "DL10"},
1247 	{"HDMI_CH3_MUX", "CH5", "DL10"},
1248 	{"HDMI_CH3_MUX", "CH6", "DL10"},
1249 	{"HDMI_CH3_MUX", "CH7", "DL10"},
1250 
1251 	{"HDMI_CH4_MUX", "CH0", "DL10"},
1252 	{"HDMI_CH4_MUX", "CH1", "DL10"},
1253 	{"HDMI_CH4_MUX", "CH2", "DL10"},
1254 	{"HDMI_CH4_MUX", "CH3", "DL10"},
1255 	{"HDMI_CH4_MUX", "CH4", "DL10"},
1256 	{"HDMI_CH4_MUX", "CH5", "DL10"},
1257 	{"HDMI_CH4_MUX", "CH6", "DL10"},
1258 	{"HDMI_CH4_MUX", "CH7", "DL10"},
1259 
1260 	{"HDMI_CH5_MUX", "CH0", "DL10"},
1261 	{"HDMI_CH5_MUX", "CH1", "DL10"},
1262 	{"HDMI_CH5_MUX", "CH2", "DL10"},
1263 	{"HDMI_CH5_MUX", "CH3", "DL10"},
1264 	{"HDMI_CH5_MUX", "CH4", "DL10"},
1265 	{"HDMI_CH5_MUX", "CH5", "DL10"},
1266 	{"HDMI_CH5_MUX", "CH6", "DL10"},
1267 	{"HDMI_CH5_MUX", "CH7", "DL10"},
1268 
1269 	{"HDMI_CH6_MUX", "CH0", "DL10"},
1270 	{"HDMI_CH6_MUX", "CH1", "DL10"},
1271 	{"HDMI_CH6_MUX", "CH2", "DL10"},
1272 	{"HDMI_CH6_MUX", "CH3", "DL10"},
1273 	{"HDMI_CH6_MUX", "CH4", "DL10"},
1274 	{"HDMI_CH6_MUX", "CH5", "DL10"},
1275 	{"HDMI_CH6_MUX", "CH6", "DL10"},
1276 	{"HDMI_CH6_MUX", "CH7", "DL10"},
1277 
1278 	{"HDMI_CH7_MUX", "CH0", "DL10"},
1279 	{"HDMI_CH7_MUX", "CH1", "DL10"},
1280 	{"HDMI_CH7_MUX", "CH2", "DL10"},
1281 	{"HDMI_CH7_MUX", "CH3", "DL10"},
1282 	{"HDMI_CH7_MUX", "CH4", "DL10"},
1283 	{"HDMI_CH7_MUX", "CH5", "DL10"},
1284 	{"HDMI_CH7_MUX", "CH6", "DL10"},
1285 	{"HDMI_CH7_MUX", "CH7", "DL10"},
1286 
1287 	{"HDMI_OUT_MUX", "Connect", "HDMI_CH0_MUX"},
1288 	{"HDMI_OUT_MUX", "Connect", "HDMI_CH1_MUX"},
1289 	{"HDMI_OUT_MUX", "Connect", "HDMI_CH2_MUX"},
1290 	{"HDMI_OUT_MUX", "Connect", "HDMI_CH3_MUX"},
1291 	{"HDMI_OUT_MUX", "Connect", "HDMI_CH4_MUX"},
1292 	{"HDMI_OUT_MUX", "Connect", "HDMI_CH5_MUX"},
1293 	{"HDMI_OUT_MUX", "Connect", "HDMI_CH6_MUX"},
1294 	{"HDMI_OUT_MUX", "Connect", "HDMI_CH7_MUX"},
1295 
1296 	{"DPTX_OUT_MUX", "Connect", "HDMI_CH0_MUX"},
1297 	{"DPTX_OUT_MUX", "Connect", "HDMI_CH1_MUX"},
1298 	{"DPTX_OUT_MUX", "Connect", "HDMI_CH2_MUX"},
1299 	{"DPTX_OUT_MUX", "Connect", "HDMI_CH3_MUX"},
1300 	{"DPTX_OUT_MUX", "Connect", "HDMI_CH4_MUX"},
1301 	{"DPTX_OUT_MUX", "Connect", "HDMI_CH5_MUX"},
1302 	{"DPTX_OUT_MUX", "Connect", "HDMI_CH6_MUX"},
1303 	{"DPTX_OUT_MUX", "Connect", "HDMI_CH7_MUX"},
1304 
1305 	{"ETDM3 Playback", NULL, "HDMI_OUT_MUX"},
1306 	{"DPTX Playback", NULL, "DPTX_OUT_MUX"},
1307 
1308 	{"ETDM_OUTPUT", NULL, "DPTX Playback"},
1309 	{"ETDM_OUTPUT", NULL, "ETDM1 Playback"},
1310 	{"ETDM_OUTPUT", NULL, "ETDM2 Playback"},
1311 	{"ETDM_OUTPUT", NULL, "ETDM3 Playback"},
1312 	{"ETDM1 Capture", NULL, "ETDM_INPUT"},
1313 	{"ETDM2 Capture", NULL, "ETDM_INPUT"},
1314 };
1315 
mt8195_afe_enable_etdm(struct mtk_base_afe * afe,int dai_id)1316 static int mt8195_afe_enable_etdm(struct mtk_base_afe *afe, int dai_id)
1317 {
1318 	int ret = 0;
1319 	struct etdm_con_reg etdm_reg;
1320 	struct mt8195_afe_private *afe_priv = afe->platform_priv;
1321 	struct mtk_dai_etdm_priv *etdm_data;
1322 	unsigned long flags;
1323 
1324 	if (!mt8195_afe_etdm_is_valid(dai_id))
1325 		return -EINVAL;
1326 
1327 	etdm_data = afe_priv->dai_priv[dai_id];
1328 	spin_lock_irqsave(&afe_priv->afe_ctrl_lock, flags);
1329 	etdm_data->en_ref_cnt++;
1330 	if (etdm_data->en_ref_cnt == 1) {
1331 		ret = get_etdm_reg(dai_id, &etdm_reg);
1332 		if (ret < 0)
1333 			goto out;
1334 
1335 		regmap_update_bits(afe->regmap, etdm_reg.con0,
1336 				   ETDM_CON0_EN, ETDM_CON0_EN);
1337 	}
1338 out:
1339 	spin_unlock_irqrestore(&afe_priv->afe_ctrl_lock, flags);
1340 	return ret;
1341 }
1342 
mt8195_afe_disable_etdm(struct mtk_base_afe * afe,int dai_id)1343 static int mt8195_afe_disable_etdm(struct mtk_base_afe *afe, int dai_id)
1344 {
1345 	int ret = 0;
1346 	struct etdm_con_reg etdm_reg;
1347 	struct mt8195_afe_private *afe_priv = afe->platform_priv;
1348 	struct mtk_dai_etdm_priv *etdm_data;
1349 	unsigned long flags;
1350 
1351 	if (!mt8195_afe_etdm_is_valid(dai_id))
1352 		return -EINVAL;
1353 
1354 	etdm_data = afe_priv->dai_priv[dai_id];
1355 	spin_lock_irqsave(&afe_priv->afe_ctrl_lock, flags);
1356 	if (etdm_data->en_ref_cnt > 0) {
1357 		etdm_data->en_ref_cnt--;
1358 		if (etdm_data->en_ref_cnt == 0) {
1359 			ret = get_etdm_reg(dai_id, &etdm_reg);
1360 			if (ret < 0)
1361 				goto out;
1362 
1363 			regmap_update_bits(afe->regmap, etdm_reg.con0,
1364 					   ETDM_CON0_EN, 0);
1365 		}
1366 	}
1367 out:
1368 	spin_unlock_irqrestore(&afe_priv->afe_ctrl_lock, flags);
1369 	return ret;
1370 }
1371 
etdm_cowork_slv_sel(int id,int slave_mode)1372 static int etdm_cowork_slv_sel(int id, int slave_mode)
1373 {
1374 	if (slave_mode) {
1375 		switch (id) {
1376 		case MT8195_AFE_IO_ETDM1_IN:
1377 			return COWORK_ETDM_IN1_S;
1378 		case MT8195_AFE_IO_ETDM2_IN:
1379 			return COWORK_ETDM_IN2_S;
1380 		case MT8195_AFE_IO_ETDM1_OUT:
1381 			return COWORK_ETDM_OUT1_S;
1382 		case MT8195_AFE_IO_ETDM2_OUT:
1383 			return COWORK_ETDM_OUT2_S;
1384 		case MT8195_AFE_IO_ETDM3_OUT:
1385 			return COWORK_ETDM_OUT3_S;
1386 		default:
1387 			return -EINVAL;
1388 		}
1389 	} else {
1390 		switch (id) {
1391 		case MT8195_AFE_IO_ETDM1_IN:
1392 			return COWORK_ETDM_IN1_M;
1393 		case MT8195_AFE_IO_ETDM2_IN:
1394 			return COWORK_ETDM_IN2_M;
1395 		case MT8195_AFE_IO_ETDM1_OUT:
1396 			return COWORK_ETDM_OUT1_M;
1397 		case MT8195_AFE_IO_ETDM2_OUT:
1398 			return COWORK_ETDM_OUT2_M;
1399 		case MT8195_AFE_IO_ETDM3_OUT:
1400 			return COWORK_ETDM_OUT3_M;
1401 		default:
1402 			return -EINVAL;
1403 		}
1404 	}
1405 }
1406 
mt8195_etdm_sync_mode_configure(struct mtk_base_afe * afe,int dai_id)1407 static int mt8195_etdm_sync_mode_configure(struct mtk_base_afe *afe, int dai_id)
1408 {
1409 	struct mt8195_afe_private *afe_priv = afe->platform_priv;
1410 	struct mtk_dai_etdm_priv *etdm_data;
1411 	unsigned int reg = 0;
1412 	unsigned int mask;
1413 	unsigned int val;
1414 	int cowork_source_sel;
1415 
1416 	if (!mt8195_afe_etdm_is_valid(dai_id))
1417 		return -EINVAL;
1418 
1419 	etdm_data = afe_priv->dai_priv[dai_id];
1420 	if (etdm_data->cowork_source_id == COWORK_ETDM_NONE)
1421 		return 0;
1422 
1423 	cowork_source_sel = etdm_cowork_slv_sel(etdm_data->cowork_source_id,
1424 						etdm_data->slave_mode);
1425 	if (cowork_source_sel < 0)
1426 		return cowork_source_sel;
1427 
1428 	switch (dai_id) {
1429 	case MT8195_AFE_IO_ETDM1_IN:
1430 		reg = ETDM_COWORK_CON1;
1431 		mask = ETDM_IN1_SLAVE_SEL_MASK;
1432 		val = ETDM_IN1_SLAVE_SEL(cowork_source_sel);
1433 		break;
1434 	case MT8195_AFE_IO_ETDM2_IN:
1435 		reg = ETDM_COWORK_CON2;
1436 		mask = ETDM_IN2_SLAVE_SEL_MASK;
1437 		val = ETDM_IN2_SLAVE_SEL(cowork_source_sel);
1438 		break;
1439 	case MT8195_AFE_IO_ETDM1_OUT:
1440 		reg = ETDM_COWORK_CON0;
1441 		mask = ETDM_OUT1_SLAVE_SEL_MASK;
1442 		val = ETDM_OUT1_SLAVE_SEL(cowork_source_sel);
1443 		break;
1444 	case MT8195_AFE_IO_ETDM2_OUT:
1445 		reg = ETDM_COWORK_CON2;
1446 		mask = ETDM_OUT2_SLAVE_SEL_MASK;
1447 		val = ETDM_OUT2_SLAVE_SEL(cowork_source_sel);
1448 		break;
1449 	case MT8195_AFE_IO_ETDM3_OUT:
1450 		reg = ETDM_COWORK_CON2;
1451 		mask = ETDM_OUT3_SLAVE_SEL_MASK;
1452 		val = ETDM_OUT3_SLAVE_SEL(cowork_source_sel);
1453 		break;
1454 	default:
1455 		return 0;
1456 	}
1457 
1458 	regmap_update_bits(afe->regmap, reg, mask, val);
1459 
1460 	return 0;
1461 }
1462 
mtk_dai_etdm_get_cg_id_by_dai_id(int dai_id)1463 static int mtk_dai_etdm_get_cg_id_by_dai_id(int dai_id)
1464 {
1465 	int cg_id = -1;
1466 
1467 	switch (dai_id) {
1468 	case MT8195_AFE_IO_DPTX:
1469 		cg_id = MT8195_CLK_AUD_HDMI_OUT;
1470 		break;
1471 	case MT8195_AFE_IO_ETDM1_IN:
1472 		cg_id = MT8195_CLK_AUD_TDM_IN;
1473 		break;
1474 	case MT8195_AFE_IO_ETDM2_IN:
1475 		cg_id = MT8195_CLK_AUD_I2SIN;
1476 		break;
1477 	case MT8195_AFE_IO_ETDM1_OUT:
1478 		cg_id = MT8195_CLK_AUD_TDM_OUT;
1479 		break;
1480 	case MT8195_AFE_IO_ETDM2_OUT:
1481 		cg_id = MT8195_CLK_AUD_I2S_OUT;
1482 		break;
1483 	case MT8195_AFE_IO_ETDM3_OUT:
1484 		cg_id = MT8195_CLK_AUD_HDMI_OUT;
1485 		break;
1486 	default:
1487 		break;
1488 	}
1489 
1490 	return cg_id;
1491 }
1492 
mtk_dai_etdm_get_clk_id_by_dai_id(int dai_id)1493 static int mtk_dai_etdm_get_clk_id_by_dai_id(int dai_id)
1494 {
1495 	int clk_id = -1;
1496 
1497 	switch (dai_id) {
1498 	case MT8195_AFE_IO_DPTX:
1499 		clk_id = MT8195_CLK_TOP_DPTX_M_SEL;
1500 		break;
1501 	case MT8195_AFE_IO_ETDM1_IN:
1502 		clk_id = MT8195_CLK_TOP_I2SI1_M_SEL;
1503 		break;
1504 	case MT8195_AFE_IO_ETDM2_IN:
1505 		clk_id = MT8195_CLK_TOP_I2SI2_M_SEL;
1506 		break;
1507 	case MT8195_AFE_IO_ETDM1_OUT:
1508 		clk_id = MT8195_CLK_TOP_I2SO1_M_SEL;
1509 		break;
1510 	case MT8195_AFE_IO_ETDM2_OUT:
1511 		clk_id = MT8195_CLK_TOP_I2SO2_M_SEL;
1512 		break;
1513 	case MT8195_AFE_IO_ETDM3_OUT:
1514 	default:
1515 		break;
1516 	}
1517 
1518 	return clk_id;
1519 }
1520 
mtk_dai_etdm_get_clkdiv_id_by_dai_id(int dai_id)1521 static int mtk_dai_etdm_get_clkdiv_id_by_dai_id(int dai_id)
1522 {
1523 	int clk_id = -1;
1524 
1525 	switch (dai_id) {
1526 	case MT8195_AFE_IO_DPTX:
1527 		clk_id = MT8195_CLK_TOP_APLL12_DIV9;
1528 		break;
1529 	case MT8195_AFE_IO_ETDM1_IN:
1530 		clk_id = MT8195_CLK_TOP_APLL12_DIV0;
1531 		break;
1532 	case MT8195_AFE_IO_ETDM2_IN:
1533 		clk_id = MT8195_CLK_TOP_APLL12_DIV1;
1534 		break;
1535 	case MT8195_AFE_IO_ETDM1_OUT:
1536 		clk_id = MT8195_CLK_TOP_APLL12_DIV2;
1537 		break;
1538 	case MT8195_AFE_IO_ETDM2_OUT:
1539 		clk_id = MT8195_CLK_TOP_APLL12_DIV3;
1540 		break;
1541 	case MT8195_AFE_IO_ETDM3_OUT:
1542 	default:
1543 		break;
1544 	}
1545 
1546 	return clk_id;
1547 }
1548 
mtk_dai_etdm_enable_mclk(struct mtk_base_afe * afe,int dai_id)1549 static int mtk_dai_etdm_enable_mclk(struct mtk_base_afe *afe, int dai_id)
1550 {
1551 	struct mt8195_afe_private *afe_priv = afe->platform_priv;
1552 	int clkdiv_id = mtk_dai_etdm_get_clkdiv_id_by_dai_id(dai_id);
1553 
1554 	if (clkdiv_id < 0)
1555 		return -EINVAL;
1556 
1557 	mt8195_afe_enable_clk(afe, afe_priv->clk[clkdiv_id]);
1558 
1559 	return 0;
1560 }
1561 
mtk_dai_etdm_disable_mclk(struct mtk_base_afe * afe,int dai_id)1562 static int mtk_dai_etdm_disable_mclk(struct mtk_base_afe *afe, int dai_id)
1563 {
1564 	struct mt8195_afe_private *afe_priv = afe->platform_priv;
1565 	int clkdiv_id = mtk_dai_etdm_get_clkdiv_id_by_dai_id(dai_id);
1566 
1567 	if (clkdiv_id < 0)
1568 		return -EINVAL;
1569 
1570 	mt8195_afe_disable_clk(afe, afe_priv->clk[clkdiv_id]);
1571 
1572 	return 0;
1573 }
1574 
1575 /* dai ops */
mtk_dai_etdm_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)1576 static int mtk_dai_etdm_startup(struct snd_pcm_substream *substream,
1577 				struct snd_soc_dai *dai)
1578 {
1579 	struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
1580 	struct mt8195_afe_private *afe_priv = afe->platform_priv;
1581 	struct mtk_dai_etdm_priv *mst_etdm_data;
1582 	int cg_id;
1583 	int mst_dai_id;
1584 	int slv_dai_id;
1585 	int i;
1586 
1587 	if (is_cowork_mode(dai)) {
1588 		mst_dai_id = get_etdm_cowork_master_id(dai);
1589 		if (!mt8195_afe_etdm_is_valid(mst_dai_id))
1590 			return -EINVAL;
1591 
1592 		mtk_dai_etdm_enable_mclk(afe, mst_dai_id);
1593 		cg_id = mtk_dai_etdm_get_cg_id_by_dai_id(mst_dai_id);
1594 		if (cg_id >= 0)
1595 			mt8195_afe_enable_clk(afe, afe_priv->clk[cg_id]);
1596 
1597 		mst_etdm_data = afe_priv->dai_priv[mst_dai_id];
1598 
1599 		for (i = 0; i < mst_etdm_data->cowork_slv_count; i++) {
1600 			slv_dai_id = mst_etdm_data->cowork_slv_id[i];
1601 			cg_id = mtk_dai_etdm_get_cg_id_by_dai_id(slv_dai_id);
1602 			if (cg_id >= 0)
1603 				mt8195_afe_enable_clk(afe,
1604 						      afe_priv->clk[cg_id]);
1605 		}
1606 	} else {
1607 		mtk_dai_etdm_enable_mclk(afe, dai->id);
1608 
1609 		cg_id = mtk_dai_etdm_get_cg_id_by_dai_id(dai->id);
1610 		if (cg_id >= 0)
1611 			mt8195_afe_enable_clk(afe, afe_priv->clk[cg_id]);
1612 	}
1613 
1614 	return 0;
1615 }
1616 
mtk_dai_etdm_shutdown(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)1617 static void mtk_dai_etdm_shutdown(struct snd_pcm_substream *substream,
1618 				  struct snd_soc_dai *dai)
1619 {
1620 	struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
1621 	struct mt8195_afe_private *afe_priv = afe->platform_priv;
1622 	struct mtk_dai_etdm_priv *mst_etdm_data;
1623 	int cg_id;
1624 	int mst_dai_id;
1625 	int slv_dai_id;
1626 	int i;
1627 
1628 	if (is_cowork_mode(dai)) {
1629 		mst_dai_id = get_etdm_cowork_master_id(dai);
1630 		if (!mt8195_afe_etdm_is_valid(mst_dai_id))
1631 			return;
1632 
1633 		cg_id = mtk_dai_etdm_get_cg_id_by_dai_id(mst_dai_id);
1634 		if (cg_id >= 0)
1635 			mt8195_afe_disable_clk(afe, afe_priv->clk[cg_id]);
1636 
1637 		mst_etdm_data = afe_priv->dai_priv[mst_dai_id];
1638 		for (i = 0; i < mst_etdm_data->cowork_slv_count; i++) {
1639 			slv_dai_id = mst_etdm_data->cowork_slv_id[i];
1640 			cg_id = mtk_dai_etdm_get_cg_id_by_dai_id(slv_dai_id);
1641 			if (cg_id >= 0)
1642 				mt8195_afe_disable_clk(afe,
1643 						       afe_priv->clk[cg_id]);
1644 		}
1645 		mtk_dai_etdm_disable_mclk(afe, mst_dai_id);
1646 	} else {
1647 		cg_id = mtk_dai_etdm_get_cg_id_by_dai_id(dai->id);
1648 		if (cg_id >= 0)
1649 			mt8195_afe_disable_clk(afe, afe_priv->clk[cg_id]);
1650 
1651 		mtk_dai_etdm_disable_mclk(afe, dai->id);
1652 	}
1653 }
1654 
mtk_dai_etdm_fifo_mode(struct mtk_base_afe * afe,int dai_id,unsigned int rate)1655 static int mtk_dai_etdm_fifo_mode(struct mtk_base_afe *afe,
1656 				  int dai_id, unsigned int rate)
1657 {
1658 	unsigned int mode = 0;
1659 	unsigned int reg = 0;
1660 	unsigned int val = 0;
1661 	unsigned int mask = (ETDM_IN_AFIFO_MODE_MASK | ETDM_IN_USE_AFIFO);
1662 
1663 	if (rate != 0)
1664 		mode = mt8195_afe_fs_timing(rate);
1665 
1666 	switch (dai_id) {
1667 	case MT8195_AFE_IO_ETDM1_IN:
1668 		reg = ETDM_IN1_AFIFO_CON;
1669 		if (rate == 0)
1670 			mode = MT8195_ETDM_IN1_1X_EN;
1671 		break;
1672 	case MT8195_AFE_IO_ETDM2_IN:
1673 		reg = ETDM_IN2_AFIFO_CON;
1674 		if (rate == 0)
1675 			mode = MT8195_ETDM_IN2_1X_EN;
1676 		break;
1677 	default:
1678 		return -EINVAL;
1679 	}
1680 
1681 	val = (mode | ETDM_IN_USE_AFIFO);
1682 
1683 	regmap_update_bits(afe->regmap, reg, mask, val);
1684 	return 0;
1685 }
1686 
mtk_dai_etdm_in_configure(struct mtk_base_afe * afe,unsigned int rate,unsigned int channels,int dai_id)1687 static int mtk_dai_etdm_in_configure(struct mtk_base_afe *afe,
1688 				     unsigned int rate,
1689 				     unsigned int channels,
1690 				     int dai_id)
1691 {
1692 	struct mt8195_afe_private *afe_priv = afe->platform_priv;
1693 	struct mtk_dai_etdm_priv *etdm_data;
1694 	struct etdm_con_reg etdm_reg;
1695 	bool slave_mode;
1696 	unsigned int data_mode;
1697 	unsigned int lrck_width;
1698 	unsigned int val = 0;
1699 	unsigned int mask = 0;
1700 	int i;
1701 	int ret;
1702 
1703 	if (!mt8195_afe_etdm_is_valid(dai_id))
1704 		return -EINVAL;
1705 
1706 	etdm_data = afe_priv->dai_priv[dai_id];
1707 	slave_mode = etdm_data->slave_mode;
1708 	data_mode = etdm_data->data_mode;
1709 	lrck_width = etdm_data->lrck_width;
1710 
1711 	dev_dbg(afe->dev, "%s rate %u channels %u, id %d\n",
1712 		__func__, rate, channels, dai_id);
1713 
1714 	ret = get_etdm_reg(dai_id, &etdm_reg);
1715 	if (ret < 0)
1716 		return ret;
1717 
1718 	if (etdm_data->cowork_source_id != COWORK_ETDM_NONE)
1719 		slave_mode = true;
1720 
1721 	/* afifo */
1722 	if (slave_mode)
1723 		mtk_dai_etdm_fifo_mode(afe, dai_id, 0);
1724 	else
1725 		mtk_dai_etdm_fifo_mode(afe, dai_id, rate);
1726 
1727 	/* con1 */
1728 	if (lrck_width > 0) {
1729 		mask |= (ETDM_IN_CON1_LRCK_AUTO_MODE |
1730 			ETDM_IN_CON1_LRCK_WIDTH_MASK);
1731 		val |= ETDM_IN_CON1_LRCK_WIDTH(lrck_width);
1732 	}
1733 	regmap_update_bits(afe->regmap, etdm_reg.con1, mask, val);
1734 
1735 	mask = 0;
1736 	val = 0;
1737 
1738 	/* con2 */
1739 	if (!slave_mode) {
1740 		mask |= ETDM_IN_CON2_UPDATE_GAP_MASK;
1741 		if (rate == 352800 || rate == 384000)
1742 			val |= ETDM_IN_CON2_UPDATE_GAP(4);
1743 		else
1744 			val |= ETDM_IN_CON2_UPDATE_GAP(3);
1745 	}
1746 	mask |= (ETDM_IN_CON2_MULTI_IP_2CH_MODE |
1747 		ETDM_IN_CON2_MULTI_IP_TOTAL_CH_MASK);
1748 	if (data_mode == MTK_DAI_ETDM_DATA_MULTI_PIN) {
1749 		val |= ETDM_IN_CON2_MULTI_IP_2CH_MODE |
1750 		       ETDM_IN_CON2_MULTI_IP_TOTAL_CH(channels);
1751 	}
1752 	regmap_update_bits(afe->regmap, etdm_reg.con2, mask, val);
1753 
1754 	mask = 0;
1755 	val = 0;
1756 
1757 	/* con3 */
1758 	mask |= ETDM_IN_CON3_DISABLE_OUT_MASK;
1759 	for (i = 0; i < channels; i += 2) {
1760 		if (etdm_data->in_disable_ch[i] &&
1761 		    etdm_data->in_disable_ch[i + 1])
1762 			val |= ETDM_IN_CON3_DISABLE_OUT(i >> 1);
1763 	}
1764 	if (!slave_mode) {
1765 		mask |= ETDM_IN_CON3_FS_MASK;
1766 		val |= ETDM_IN_CON3_FS(get_etdm_fs_timing(rate));
1767 	}
1768 	regmap_update_bits(afe->regmap, etdm_reg.con3, mask, val);
1769 
1770 	mask = 0;
1771 	val = 0;
1772 
1773 	/* con4 */
1774 	mask |= (ETDM_IN_CON4_MASTER_LRCK_INV | ETDM_IN_CON4_MASTER_BCK_INV |
1775 		ETDM_IN_CON4_SLAVE_LRCK_INV | ETDM_IN_CON4_SLAVE_BCK_INV);
1776 	if (slave_mode) {
1777 		if (etdm_data->lrck_inv)
1778 			val |= ETDM_IN_CON4_SLAVE_LRCK_INV;
1779 		if (etdm_data->bck_inv)
1780 			val |= ETDM_IN_CON4_SLAVE_BCK_INV;
1781 	} else {
1782 		if (etdm_data->lrck_inv)
1783 			val |= ETDM_IN_CON4_MASTER_LRCK_INV;
1784 		if (etdm_data->bck_inv)
1785 			val |= ETDM_IN_CON4_MASTER_BCK_INV;
1786 	}
1787 	regmap_update_bits(afe->regmap, etdm_reg.con4, mask, val);
1788 
1789 	mask = 0;
1790 	val = 0;
1791 
1792 	/* con5 */
1793 	mask |= ETDM_IN_CON5_LR_SWAP_MASK;
1794 	mask |= ETDM_IN_CON5_ENABLE_ODD_MASK;
1795 	for (i = 0; i < channels; i += 2) {
1796 		if (etdm_data->in_disable_ch[i] &&
1797 		    !etdm_data->in_disable_ch[i + 1]) {
1798 			if (i == (channels - 2))
1799 				val |= ETDM_IN_CON5_LR_SWAP(15);
1800 			else
1801 				val |= ETDM_IN_CON5_LR_SWAP(i >> 1);
1802 			val |= ETDM_IN_CON5_ENABLE_ODD(i >> 1);
1803 		} else if (!etdm_data->in_disable_ch[i] &&
1804 			   etdm_data->in_disable_ch[i + 1]) {
1805 			val |= ETDM_IN_CON5_ENABLE_ODD(i >> 1);
1806 		}
1807 	}
1808 	regmap_update_bits(afe->regmap, etdm_reg.con5, mask, val);
1809 	return 0;
1810 }
1811 
mtk_dai_etdm_out_configure(struct mtk_base_afe * afe,unsigned int rate,unsigned int channels,int dai_id)1812 static int mtk_dai_etdm_out_configure(struct mtk_base_afe *afe,
1813 				      unsigned int rate,
1814 				      unsigned int channels,
1815 				      int dai_id)
1816 {
1817 	struct mt8195_afe_private *afe_priv = afe->platform_priv;
1818 	struct mtk_dai_etdm_priv *etdm_data;
1819 	struct etdm_con_reg etdm_reg;
1820 	bool slave_mode;
1821 	unsigned int lrck_width;
1822 	unsigned int val = 0;
1823 	unsigned int mask = 0;
1824 	int ret;
1825 	int fs = 0;
1826 
1827 	if (!mt8195_afe_etdm_is_valid(dai_id))
1828 		return -EINVAL;
1829 
1830 	etdm_data = afe_priv->dai_priv[dai_id];
1831 	slave_mode = etdm_data->slave_mode;
1832 	lrck_width = etdm_data->lrck_width;
1833 
1834 	dev_dbg(afe->dev, "%s rate %u channels %u, id %d\n",
1835 		__func__, rate, channels, dai_id);
1836 
1837 	ret = get_etdm_reg(dai_id, &etdm_reg);
1838 	if (ret < 0)
1839 		return ret;
1840 
1841 	if (etdm_data->cowork_source_id != COWORK_ETDM_NONE)
1842 		slave_mode = true;
1843 
1844 	/* con0 */
1845 	mask = ETDM_OUT_CON0_RELATCH_DOMAIN_MASK;
1846 	val = ETDM_OUT_CON0_RELATCH_DOMAIN(ETDM_RELATCH_TIMING_A1A2SYS);
1847 	regmap_update_bits(afe->regmap, etdm_reg.con0, mask, val);
1848 
1849 	mask = 0;
1850 	val = 0;
1851 
1852 	/* con1 */
1853 	if (lrck_width > 0) {
1854 		mask |= (ETDM_OUT_CON1_LRCK_AUTO_MODE |
1855 			ETDM_OUT_CON1_LRCK_WIDTH_MASK);
1856 		val |= ETDM_OUT_CON1_LRCK_WIDTH(lrck_width);
1857 	}
1858 	regmap_update_bits(afe->regmap, etdm_reg.con1, mask, val);
1859 
1860 	mask = 0;
1861 	val = 0;
1862 
1863 	if (slave_mode) {
1864 		/* con2 */
1865 		mask = (ETDM_OUT_CON2_LRCK_DELAY_BCK_INV |
1866 			ETDM_OUT_CON2_LRCK_DELAY_0P5T_EN);
1867 		val = (ETDM_OUT_CON2_LRCK_DELAY_BCK_INV |
1868 			ETDM_OUT_CON2_LRCK_DELAY_0P5T_EN);
1869 		regmap_update_bits(afe->regmap, etdm_reg.con2,
1870 				   mask, val);
1871 		mask = 0;
1872 		val = 0;
1873 	} else {
1874 		/* con4 */
1875 		mask |= ETDM_OUT_CON4_FS_MASK;
1876 		val |= ETDM_OUT_CON4_FS(get_etdm_fs_timing(rate));
1877 	}
1878 
1879 	mask |= ETDM_OUT_CON4_RELATCH_EN_MASK;
1880 	if (dai_id == MT8195_AFE_IO_ETDM1_OUT)
1881 		fs = MT8195_ETDM_OUT1_1X_EN;
1882 	else if (dai_id == MT8195_AFE_IO_ETDM2_OUT)
1883 		fs = MT8195_ETDM_OUT2_1X_EN;
1884 
1885 	val |= ETDM_OUT_CON4_RELATCH_EN(fs);
1886 
1887 	regmap_update_bits(afe->regmap, etdm_reg.con4, mask, val);
1888 
1889 	mask = 0;
1890 	val = 0;
1891 
1892 	/* con5 */
1893 	mask |= (ETDM_OUT_CON5_MASTER_LRCK_INV | ETDM_OUT_CON5_MASTER_BCK_INV |
1894 		ETDM_OUT_CON5_SLAVE_LRCK_INV | ETDM_OUT_CON5_SLAVE_BCK_INV);
1895 	if (slave_mode) {
1896 		if (etdm_data->lrck_inv)
1897 			val |= ETDM_OUT_CON5_SLAVE_LRCK_INV;
1898 		if (etdm_data->bck_inv)
1899 			val |= ETDM_OUT_CON5_SLAVE_BCK_INV;
1900 	} else {
1901 		if (etdm_data->lrck_inv)
1902 			val |= ETDM_OUT_CON5_MASTER_LRCK_INV;
1903 		if (etdm_data->bck_inv)
1904 			val |= ETDM_OUT_CON5_MASTER_BCK_INV;
1905 	}
1906 	regmap_update_bits(afe->regmap, etdm_reg.con5, mask, val);
1907 
1908 	return 0;
1909 }
1910 
mtk_dai_etdm_mclk_configure(struct mtk_base_afe * afe,int dai_id)1911 static int mtk_dai_etdm_mclk_configure(struct mtk_base_afe *afe, int dai_id)
1912 {
1913 	struct mt8195_afe_private *afe_priv = afe->platform_priv;
1914 	struct mtk_dai_etdm_priv *etdm_data;
1915 	int clk_id = mtk_dai_etdm_get_clk_id_by_dai_id(dai_id);
1916 	int clkdiv_id = mtk_dai_etdm_get_clkdiv_id_by_dai_id(dai_id);
1917 	int apll;
1918 	int apll_clk_id;
1919 	struct etdm_con_reg etdm_reg;
1920 	unsigned int val = 0;
1921 	unsigned int mask = 0;
1922 	int ret = 0;
1923 
1924 	if (clk_id < 0 || clkdiv_id < 0)
1925 		return 0;
1926 
1927 	if (!mt8195_afe_etdm_is_valid(dai_id))
1928 		return -EINVAL;
1929 
1930 	etdm_data = afe_priv->dai_priv[dai_id];
1931 	ret = get_etdm_reg(dai_id, &etdm_reg);
1932 	if (ret < 0)
1933 		return ret;
1934 
1935 	mask |= ETDM_CON1_MCLK_OUTPUT;
1936 	if (etdm_data->mclk_dir == SND_SOC_CLOCK_OUT)
1937 		val |= ETDM_CON1_MCLK_OUTPUT;
1938 	regmap_update_bits(afe->regmap, etdm_reg.con1, mask, val);
1939 
1940 	if (etdm_data->mclk_freq) {
1941 		apll = etdm_data->mclk_apll;
1942 		apll_clk_id = mt8195_afe_get_mclk_source_clk_id(apll);
1943 		if (apll_clk_id < 0)
1944 			return apll_clk_id;
1945 
1946 		/* select apll */
1947 		ret = mt8195_afe_set_clk_parent(afe, afe_priv->clk[clk_id],
1948 						afe_priv->clk[apll_clk_id]);
1949 		if (ret)
1950 			return ret;
1951 
1952 		/* set rate */
1953 		ret = mt8195_afe_set_clk_rate(afe, afe_priv->clk[clkdiv_id],
1954 					      etdm_data->mclk_freq);
1955 	} else {
1956 		if (etdm_data->mclk_dir == SND_SOC_CLOCK_OUT)
1957 			dev_dbg(afe->dev, "%s mclk freq = 0\n", __func__);
1958 	}
1959 	return ret;
1960 }
1961 
mtk_dai_etdm_configure(struct mtk_base_afe * afe,unsigned int rate,unsigned int channels,unsigned int bit_width,int dai_id)1962 static int mtk_dai_etdm_configure(struct mtk_base_afe *afe,
1963 				  unsigned int rate,
1964 				  unsigned int channels,
1965 				  unsigned int bit_width,
1966 				  int dai_id)
1967 {
1968 	struct mt8195_afe_private *afe_priv = afe->platform_priv;
1969 	struct mtk_dai_etdm_priv *etdm_data;
1970 	struct etdm_con_reg etdm_reg;
1971 	bool slave_mode;
1972 	unsigned int etdm_channels;
1973 	unsigned int val = 0;
1974 	unsigned int mask = 0;
1975 	unsigned int bck;
1976 	unsigned int wlen = get_etdm_wlen(bit_width);
1977 	int ret;
1978 
1979 	if (!mt8195_afe_etdm_is_valid(dai_id))
1980 		return -EINVAL;
1981 
1982 	etdm_data = afe_priv->dai_priv[dai_id];
1983 	slave_mode = etdm_data->slave_mode;
1984 	ret = get_etdm_reg(dai_id, &etdm_reg);
1985 	if (ret < 0)
1986 		return ret;
1987 
1988 	if (etdm_data->cowork_source_id != COWORK_ETDM_NONE)
1989 		slave_mode = true;
1990 
1991 	dev_dbg(afe->dev, "%s fmt %u data %u lrck %d-%u bck %d, clock %u slv %u\n",
1992 		__func__, etdm_data->format, etdm_data->data_mode,
1993 		etdm_data->lrck_inv, etdm_data->lrck_width, etdm_data->bck_inv,
1994 		etdm_data->clock_mode, etdm_data->slave_mode);
1995 	dev_dbg(afe->dev, "%s rate %u channels %u bitwidth %u, id %d\n",
1996 		__func__, rate, channels, bit_width, dai_id);
1997 
1998 	etdm_channels = (etdm_data->data_mode == MTK_DAI_ETDM_DATA_ONE_PIN) ?
1999 			get_etdm_ch_fixup(channels) : 2;
2000 
2001 	bck = rate * etdm_channels * wlen;
2002 	if (bck > MT8195_ETDM_NORMAL_MAX_BCK_RATE) {
2003 		dev_info(afe->dev, "%s bck rate %u not support\n",
2004 			 __func__, bck);
2005 		return -EINVAL;
2006 	}
2007 
2008 	/* con0 */
2009 	mask |= ETDM_CON0_BIT_LEN_MASK;
2010 	val |= ETDM_CON0_BIT_LEN(bit_width);
2011 	mask |= ETDM_CON0_WORD_LEN_MASK;
2012 	val |= ETDM_CON0_WORD_LEN(wlen);
2013 	mask |= ETDM_CON0_FORMAT_MASK;
2014 	val |= ETDM_CON0_FORMAT(etdm_data->format);
2015 	mask |= ETDM_CON0_CH_NUM_MASK;
2016 	val |= ETDM_CON0_CH_NUM(etdm_channels);
2017 
2018 	mask |= ETDM_CON0_SLAVE_MODE;
2019 	if (slave_mode) {
2020 		if (dai_id == MT8195_AFE_IO_ETDM1_OUT &&
2021 		    etdm_data->cowork_source_id == COWORK_ETDM_NONE) {
2022 			dev_info(afe->dev, "%s id %d only support master mode\n",
2023 				 __func__, dai_id);
2024 			return -EINVAL;
2025 		}
2026 		val |= ETDM_CON0_SLAVE_MODE;
2027 	}
2028 	regmap_update_bits(afe->regmap, etdm_reg.con0, mask, val);
2029 
2030 	if (get_etdm_dir(dai_id) == ETDM_IN)
2031 		mtk_dai_etdm_in_configure(afe, rate, channels, dai_id);
2032 	else
2033 		mtk_dai_etdm_out_configure(afe, rate, channels, dai_id);
2034 
2035 	return 0;
2036 }
2037 
mtk_dai_etdm_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)2038 static int mtk_dai_etdm_hw_params(struct snd_pcm_substream *substream,
2039 				  struct snd_pcm_hw_params *params,
2040 				  struct snd_soc_dai *dai)
2041 {
2042 	int ret = 0;
2043 	unsigned int rate = params_rate(params);
2044 	unsigned int bit_width = params_width(params);
2045 	unsigned int channels = params_channels(params);
2046 	struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
2047 	struct mt8195_afe_private *afe_priv = afe->platform_priv;
2048 	struct mtk_dai_etdm_priv *mst_etdm_data;
2049 	int mst_dai_id;
2050 	int slv_dai_id;
2051 	int i;
2052 
2053 	dev_dbg(afe->dev, "%s '%s' period %u-%u\n",
2054 		__func__, snd_pcm_stream_str(substream),
2055 		params_period_size(params), params_periods(params));
2056 
2057 	if (is_cowork_mode(dai)) {
2058 		mst_dai_id = get_etdm_cowork_master_id(dai);
2059 		if (!mt8195_afe_etdm_is_valid(mst_dai_id))
2060 			return -EINVAL;
2061 
2062 		ret = mtk_dai_etdm_mclk_configure(afe, mst_dai_id);
2063 		if (ret)
2064 			return ret;
2065 
2066 		ret = mtk_dai_etdm_configure(afe, rate, channels,
2067 					     bit_width, mst_dai_id);
2068 		if (ret)
2069 			return ret;
2070 
2071 		mst_etdm_data = afe_priv->dai_priv[mst_dai_id];
2072 		for (i = 0; i < mst_etdm_data->cowork_slv_count; i++) {
2073 			slv_dai_id = mst_etdm_data->cowork_slv_id[i];
2074 			ret = mtk_dai_etdm_configure(afe, rate, channels,
2075 						     bit_width, slv_dai_id);
2076 			if (ret)
2077 				return ret;
2078 
2079 			ret = mt8195_etdm_sync_mode_configure(afe, slv_dai_id);
2080 			if (ret)
2081 				return ret;
2082 		}
2083 	} else {
2084 		ret = mtk_dai_etdm_mclk_configure(afe, dai->id);
2085 		if (ret)
2086 			return ret;
2087 
2088 		ret = mtk_dai_etdm_configure(afe, rate, channels,
2089 					     bit_width, dai->id);
2090 	}
2091 
2092 	return ret;
2093 }
2094 
mtk_dai_etdm_trigger(struct snd_pcm_substream * substream,int cmd,struct snd_soc_dai * dai)2095 static int mtk_dai_etdm_trigger(struct snd_pcm_substream *substream, int cmd,
2096 				struct snd_soc_dai *dai)
2097 {
2098 	int ret = 0;
2099 	struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
2100 	struct mt8195_afe_private *afe_priv = afe->platform_priv;
2101 	struct mtk_dai_etdm_priv *mst_etdm_data;
2102 	int mst_dai_id;
2103 	int slv_dai_id;
2104 	int i;
2105 
2106 	dev_dbg(afe->dev, "%s(), cmd %d, dai id %d\n", __func__, cmd, dai->id);
2107 	switch (cmd) {
2108 	case SNDRV_PCM_TRIGGER_START:
2109 	case SNDRV_PCM_TRIGGER_RESUME:
2110 		if (is_cowork_mode(dai)) {
2111 			mst_dai_id = get_etdm_cowork_master_id(dai);
2112 			if (!mt8195_afe_etdm_is_valid(mst_dai_id))
2113 				return -EINVAL;
2114 
2115 			mst_etdm_data = afe_priv->dai_priv[mst_dai_id];
2116 
2117 			//open master first
2118 			ret |= mt8195_afe_enable_etdm(afe, mst_dai_id);
2119 			for (i = 0; i < mst_etdm_data->cowork_slv_count; i++) {
2120 				slv_dai_id = mst_etdm_data->cowork_slv_id[i];
2121 				ret |= mt8195_afe_enable_etdm(afe, slv_dai_id);
2122 			}
2123 		} else {
2124 			ret = mt8195_afe_enable_etdm(afe, dai->id);
2125 		}
2126 		break;
2127 	case SNDRV_PCM_TRIGGER_STOP:
2128 	case SNDRV_PCM_TRIGGER_SUSPEND:
2129 		if (is_cowork_mode(dai)) {
2130 			mst_dai_id = get_etdm_cowork_master_id(dai);
2131 			if (!mt8195_afe_etdm_is_valid(mst_dai_id))
2132 				return -EINVAL;
2133 
2134 			mst_etdm_data = afe_priv->dai_priv[mst_dai_id];
2135 
2136 			for (i = 0; i < mst_etdm_data->cowork_slv_count; i++) {
2137 				slv_dai_id = mst_etdm_data->cowork_slv_id[i];
2138 				ret |= mt8195_afe_disable_etdm(afe, slv_dai_id);
2139 			}
2140 			// close master at last
2141 			ret |= mt8195_afe_disable_etdm(afe, mst_dai_id);
2142 		} else {
2143 			ret = mt8195_afe_disable_etdm(afe, dai->id);
2144 		}
2145 		break;
2146 	default:
2147 		break;
2148 	}
2149 	return ret;
2150 }
2151 
mtk_dai_etdm_cal_mclk(struct mtk_base_afe * afe,int freq,int dai_id)2152 static int mtk_dai_etdm_cal_mclk(struct mtk_base_afe *afe, int freq, int dai_id)
2153 {
2154 	struct mt8195_afe_private *afe_priv = afe->platform_priv;
2155 	struct mtk_dai_etdm_priv *etdm_data;
2156 	int apll;
2157 	int apll_rate;
2158 
2159 	if (!mt8195_afe_etdm_is_valid(dai_id))
2160 		return -EINVAL;
2161 
2162 	etdm_data = afe_priv->dai_priv[dai_id];
2163 	if (freq == 0) {
2164 		etdm_data->mclk_freq = freq;
2165 		return 0;
2166 	}
2167 
2168 	apll = mt8195_afe_get_default_mclk_source_by_rate(freq);
2169 	apll_rate = mt8195_afe_get_mclk_source_rate(afe, apll);
2170 
2171 	if (freq > apll_rate) {
2172 		dev_info(afe->dev, "freq %d > apll rate %d\n", freq, apll_rate);
2173 		return -EINVAL;
2174 	}
2175 
2176 	if (apll_rate % freq != 0) {
2177 		dev_info(afe->dev, "APLL%d cannot generate freq Hz\n", apll);
2178 		return -EINVAL;
2179 	}
2180 
2181 	etdm_data->mclk_apll = apll;
2182 	etdm_data->mclk_freq = freq;
2183 
2184 	return 0;
2185 }
2186 
mtk_dai_etdm_set_sysclk(struct snd_soc_dai * dai,int clk_id,unsigned int freq,int dir)2187 static int mtk_dai_etdm_set_sysclk(struct snd_soc_dai *dai,
2188 				   int clk_id, unsigned int freq, int dir)
2189 {
2190 	struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
2191 	struct mt8195_afe_private *afe_priv = afe->platform_priv;
2192 	struct mtk_dai_etdm_priv *etdm_data;
2193 	int dai_id;
2194 
2195 	dev_dbg(dai->dev, "%s id %d freq %u, dir %d\n",
2196 		__func__, dai->id, freq, dir);
2197 	if (is_cowork_mode(dai))
2198 		dai_id = get_etdm_cowork_master_id(dai);
2199 	else
2200 		dai_id = dai->id;
2201 
2202 	if (!mt8195_afe_etdm_is_valid(dai_id))
2203 		return -EINVAL;
2204 
2205 	etdm_data = afe_priv->dai_priv[dai_id];
2206 	etdm_data->mclk_dir = dir;
2207 	return mtk_dai_etdm_cal_mclk(afe, freq, dai_id);
2208 }
2209 
mtk_dai_etdm_set_tdm_slot(struct snd_soc_dai * dai,unsigned int tx_mask,unsigned int rx_mask,int slots,int slot_width)2210 static int mtk_dai_etdm_set_tdm_slot(struct snd_soc_dai *dai,
2211 				     unsigned int tx_mask, unsigned int rx_mask,
2212 				     int slots, int slot_width)
2213 {
2214 	struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
2215 	struct mt8195_afe_private *afe_priv = afe->platform_priv;
2216 	struct mtk_dai_etdm_priv *etdm_data;
2217 
2218 	if (!mt8195_afe_etdm_is_valid(dai->id))
2219 		return -EINVAL;
2220 
2221 	etdm_data = afe_priv->dai_priv[dai->id];
2222 	dev_dbg(dai->dev, "%s id %d slot_width %d\n",
2223 		__func__, dai->id, slot_width);
2224 
2225 	etdm_data->slots = slots;
2226 	etdm_data->lrck_width = slot_width;
2227 	return 0;
2228 }
2229 
mtk_dai_etdm_set_fmt(struct snd_soc_dai * dai,unsigned int fmt)2230 static int mtk_dai_etdm_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2231 {
2232 	struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
2233 	struct mt8195_afe_private *afe_priv = afe->platform_priv;
2234 	struct mtk_dai_etdm_priv *etdm_data;
2235 
2236 	if (!mt8195_afe_etdm_is_valid(dai->id))
2237 		return -EINVAL;
2238 
2239 	etdm_data = afe_priv->dai_priv[dai->id];
2240 	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2241 	case SND_SOC_DAIFMT_I2S:
2242 		etdm_data->format = MTK_DAI_ETDM_FORMAT_I2S;
2243 		break;
2244 	case SND_SOC_DAIFMT_LEFT_J:
2245 		etdm_data->format = MTK_DAI_ETDM_FORMAT_LJ;
2246 		break;
2247 	case SND_SOC_DAIFMT_RIGHT_J:
2248 		etdm_data->format = MTK_DAI_ETDM_FORMAT_RJ;
2249 		break;
2250 	case SND_SOC_DAIFMT_DSP_A:
2251 		etdm_data->format = MTK_DAI_ETDM_FORMAT_DSPA;
2252 		break;
2253 	case SND_SOC_DAIFMT_DSP_B:
2254 		etdm_data->format = MTK_DAI_ETDM_FORMAT_DSPB;
2255 		break;
2256 	default:
2257 		return -EINVAL;
2258 	}
2259 
2260 	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2261 	case SND_SOC_DAIFMT_NB_NF:
2262 		etdm_data->bck_inv = false;
2263 		etdm_data->lrck_inv = false;
2264 		break;
2265 	case SND_SOC_DAIFMT_NB_IF:
2266 		etdm_data->bck_inv = false;
2267 		etdm_data->lrck_inv = true;
2268 		break;
2269 	case SND_SOC_DAIFMT_IB_NF:
2270 		etdm_data->bck_inv = true;
2271 		etdm_data->lrck_inv = false;
2272 		break;
2273 	case SND_SOC_DAIFMT_IB_IF:
2274 		etdm_data->bck_inv = true;
2275 		etdm_data->lrck_inv = true;
2276 		break;
2277 	default:
2278 		return -EINVAL;
2279 	}
2280 
2281 	switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
2282 	case SND_SOC_DAIFMT_BC_FC:
2283 		etdm_data->slave_mode = true;
2284 		break;
2285 	case SND_SOC_DAIFMT_BP_FP:
2286 		etdm_data->slave_mode = false;
2287 		break;
2288 	default:
2289 		return -EINVAL;
2290 	}
2291 
2292 	return 0;
2293 }
2294 
mtk_dai_hdmitx_dptx_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)2295 static int mtk_dai_hdmitx_dptx_startup(struct snd_pcm_substream *substream,
2296 				       struct snd_soc_dai *dai)
2297 {
2298 	struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
2299 	struct mt8195_afe_private *afe_priv = afe->platform_priv;
2300 	int cg_id = mtk_dai_etdm_get_cg_id_by_dai_id(dai->id);
2301 
2302 	if (cg_id >= 0)
2303 		mt8195_afe_enable_clk(afe, afe_priv->clk[cg_id]);
2304 
2305 	mtk_dai_etdm_enable_mclk(afe, dai->id);
2306 
2307 	return 0;
2308 }
2309 
mtk_dai_hdmitx_dptx_shutdown(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)2310 static void mtk_dai_hdmitx_dptx_shutdown(struct snd_pcm_substream *substream,
2311 					 struct snd_soc_dai *dai)
2312 {
2313 	struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
2314 	struct mt8195_afe_private *afe_priv = afe->platform_priv;
2315 	int cg_id = mtk_dai_etdm_get_cg_id_by_dai_id(dai->id);
2316 
2317 	mtk_dai_etdm_disable_mclk(afe, dai->id);
2318 
2319 	if (cg_id >= 0)
2320 		mt8195_afe_disable_clk(afe, afe_priv->clk[cg_id]);
2321 }
2322 
mtk_dai_get_dptx_ch_en(unsigned int channel)2323 static unsigned int mtk_dai_get_dptx_ch_en(unsigned int channel)
2324 {
2325 	switch (channel) {
2326 	case 1 ... 2:
2327 		return AFE_DPTX_CON_CH_EN_2CH;
2328 	case 3 ... 4:
2329 		return AFE_DPTX_CON_CH_EN_4CH;
2330 	case 5 ... 6:
2331 		return AFE_DPTX_CON_CH_EN_6CH;
2332 	case 7 ... 8:
2333 		return AFE_DPTX_CON_CH_EN_8CH;
2334 	default:
2335 		return AFE_DPTX_CON_CH_EN_2CH;
2336 	}
2337 }
2338 
mtk_dai_get_dptx_ch(unsigned int ch)2339 static unsigned int mtk_dai_get_dptx_ch(unsigned int ch)
2340 {
2341 	return (ch > 2) ?
2342 		AFE_DPTX_CON_CH_NUM_8CH : AFE_DPTX_CON_CH_NUM_2CH;
2343 }
2344 
mtk_dai_get_dptx_wlen(snd_pcm_format_t format)2345 static unsigned int mtk_dai_get_dptx_wlen(snd_pcm_format_t format)
2346 {
2347 	return snd_pcm_format_physical_width(format) <= 16 ?
2348 		AFE_DPTX_CON_16BIT : AFE_DPTX_CON_24BIT;
2349 }
2350 
mtk_dai_hdmitx_dptx_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)2351 static int mtk_dai_hdmitx_dptx_hw_params(struct snd_pcm_substream *substream,
2352 					 struct snd_pcm_hw_params *params,
2353 					 struct snd_soc_dai *dai)
2354 {
2355 	struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
2356 	struct mt8195_afe_private *afe_priv = afe->platform_priv;
2357 	struct mtk_dai_etdm_priv *etdm_data;
2358 	unsigned int rate = params_rate(params);
2359 	unsigned int channels = params_channels(params);
2360 	snd_pcm_format_t format = params_format(params);
2361 	int width = snd_pcm_format_physical_width(format);
2362 	int ret = 0;
2363 
2364 	if (!mt8195_afe_hdmitx_dptx_is_valid(dai->id))
2365 		return -EINVAL;
2366 
2367 	etdm_data = afe_priv->dai_priv[dai->id];
2368 
2369 	/* dptx configure */
2370 	if (dai->id == MT8195_AFE_IO_DPTX) {
2371 		regmap_update_bits(afe->regmap, AFE_DPTX_CON,
2372 				   AFE_DPTX_CON_CH_EN_MASK,
2373 				   mtk_dai_get_dptx_ch_en(channels));
2374 		regmap_update_bits(afe->regmap, AFE_DPTX_CON,
2375 				   AFE_DPTX_CON_CH_NUM_MASK,
2376 				   mtk_dai_get_dptx_ch(channels));
2377 		regmap_update_bits(afe->regmap, AFE_DPTX_CON,
2378 				   AFE_DPTX_CON_16BIT_MASK,
2379 				   mtk_dai_get_dptx_wlen(format));
2380 
2381 		if (mtk_dai_get_dptx_ch(channels) == AFE_DPTX_CON_CH_NUM_8CH) {
2382 			etdm_data->data_mode = MTK_DAI_ETDM_DATA_ONE_PIN;
2383 			channels = 8;
2384 		} else {
2385 			channels = 2;
2386 		}
2387 	} else {
2388 		etdm_data->data_mode = MTK_DAI_ETDM_DATA_MULTI_PIN;
2389 	}
2390 
2391 	ret = mtk_dai_etdm_mclk_configure(afe, dai->id);
2392 	if (ret)
2393 		return ret;
2394 
2395 	ret = mtk_dai_etdm_configure(afe, rate, channels, width, dai->id);
2396 
2397 	return ret;
2398 }
2399 
mtk_dai_hdmitx_dptx_trigger(struct snd_pcm_substream * substream,int cmd,struct snd_soc_dai * dai)2400 static int mtk_dai_hdmitx_dptx_trigger(struct snd_pcm_substream *substream,
2401 				       int cmd,
2402 				       struct snd_soc_dai *dai)
2403 {
2404 	struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
2405 	int ret = 0;
2406 
2407 	dev_dbg(afe->dev, "%s(), cmd %d, dai id %d\n", __func__, cmd, dai->id);
2408 
2409 	switch (cmd) {
2410 	case SNDRV_PCM_TRIGGER_START:
2411 	case SNDRV_PCM_TRIGGER_RESUME:
2412 		/* enable dptx interface */
2413 		if (dai->id == MT8195_AFE_IO_DPTX)
2414 			regmap_update_bits(afe->regmap, AFE_DPTX_CON,
2415 					   AFE_DPTX_CON_ON_MASK,
2416 					   AFE_DPTX_CON_ON);
2417 
2418 		/* enable etdm_out3 */
2419 		ret = mt8195_afe_enable_etdm(afe, dai->id);
2420 		break;
2421 	case SNDRV_PCM_TRIGGER_STOP:
2422 	case SNDRV_PCM_TRIGGER_SUSPEND:
2423 		/* disable etdm_out3 */
2424 		ret = mt8195_afe_disable_etdm(afe, dai->id);
2425 
2426 		/* disable dptx interface */
2427 		if (dai->id == MT8195_AFE_IO_DPTX)
2428 			regmap_update_bits(afe->regmap, AFE_DPTX_CON,
2429 					   AFE_DPTX_CON_ON_MASK, 0);
2430 		break;
2431 	default:
2432 		return -EINVAL;
2433 	}
2434 
2435 	return ret;
2436 }
2437 
mtk_dai_hdmitx_dptx_set_sysclk(struct snd_soc_dai * dai,int clk_id,unsigned int freq,int dir)2438 static int mtk_dai_hdmitx_dptx_set_sysclk(struct snd_soc_dai *dai,
2439 					  int clk_id,
2440 					  unsigned int freq,
2441 					  int dir)
2442 {
2443 	struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
2444 	struct mt8195_afe_private *afe_priv = afe->platform_priv;
2445 	struct mtk_dai_etdm_priv *etdm_data;
2446 
2447 	if (!mt8195_afe_hdmitx_dptx_is_valid(dai->id))
2448 		return -EINVAL;
2449 
2450 	etdm_data = afe_priv->dai_priv[dai->id];
2451 
2452 	dev_dbg(dai->dev, "%s id %d freq %u, dir %d\n",
2453 		__func__, dai->id, freq, dir);
2454 
2455 	etdm_data->mclk_dir = dir;
2456 	return mtk_dai_etdm_cal_mclk(afe, freq, dai->id);
2457 }
2458 
2459 /* dai driver */
2460 #define MTK_ETDM_RATES (SNDRV_PCM_RATE_8000_384000)
2461 
2462 #define MTK_ETDM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
2463 			  SNDRV_PCM_FMTBIT_S24_LE |\
2464 			  SNDRV_PCM_FMTBIT_S32_LE)
2465 
mtk_dai_etdm_probe(struct snd_soc_dai * dai)2466 static int mtk_dai_etdm_probe(struct snd_soc_dai *dai)
2467 {
2468 	struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
2469 	struct mt8195_afe_private *afe_priv = afe->platform_priv;
2470 	struct mtk_dai_etdm_priv *etdm_data;
2471 
2472 	dev_dbg(dai->dev, "%s id %d\n", __func__, dai->id);
2473 
2474 	if (!mt8195_afe_etdm_is_valid(dai->id))
2475 		return -EINVAL;
2476 
2477 	etdm_data = afe_priv->dai_priv[dai->id];
2478 	if (etdm_data->mclk_freq) {
2479 		dev_dbg(afe->dev, "MCLK always on, rate %d\n",
2480 			etdm_data->mclk_freq);
2481 		pm_runtime_get_sync(afe->dev);
2482 		mtk_dai_etdm_mclk_configure(afe, dai->id);
2483 		mtk_dai_etdm_enable_mclk(afe, dai->id);
2484 		pm_runtime_put_sync(afe->dev);
2485 	}
2486 	return 0;
2487 }
2488 
2489 static const struct snd_soc_dai_ops mtk_dai_hdmitx_dptx_ops = {
2490 	.startup	= mtk_dai_hdmitx_dptx_startup,
2491 	.shutdown	= mtk_dai_hdmitx_dptx_shutdown,
2492 	.hw_params	= mtk_dai_hdmitx_dptx_hw_params,
2493 	.trigger	= mtk_dai_hdmitx_dptx_trigger,
2494 	.set_sysclk	= mtk_dai_hdmitx_dptx_set_sysclk,
2495 	.set_fmt	= mtk_dai_etdm_set_fmt,
2496 };
2497 
2498 static const struct snd_soc_dai_ops mtk_dai_hdmitx_dptx_ops2 = {
2499 	.probe		= mtk_dai_etdm_probe,
2500 	.startup	= mtk_dai_hdmitx_dptx_startup,
2501 	.shutdown	= mtk_dai_hdmitx_dptx_shutdown,
2502 	.hw_params	= mtk_dai_hdmitx_dptx_hw_params,
2503 	.trigger	= mtk_dai_hdmitx_dptx_trigger,
2504 	.set_sysclk	= mtk_dai_hdmitx_dptx_set_sysclk,
2505 	.set_fmt	= mtk_dai_etdm_set_fmt,
2506 };
2507 
2508 static const struct snd_soc_dai_ops mtk_dai_etdm_ops = {
2509 	.probe		= mtk_dai_etdm_probe,
2510 	.startup	= mtk_dai_etdm_startup,
2511 	.shutdown	= mtk_dai_etdm_shutdown,
2512 	.hw_params	= mtk_dai_etdm_hw_params,
2513 	.trigger	= mtk_dai_etdm_trigger,
2514 	.set_sysclk	= mtk_dai_etdm_set_sysclk,
2515 	.set_fmt	= mtk_dai_etdm_set_fmt,
2516 	.set_tdm_slot	= mtk_dai_etdm_set_tdm_slot,
2517 };
2518 
2519 static struct snd_soc_dai_driver mtk_dai_etdm_driver[] = {
2520 	{
2521 		.name = "DPTX",
2522 		.id = MT8195_AFE_IO_DPTX,
2523 		.playback = {
2524 			.stream_name = "DPTX Playback",
2525 			.channels_min = 1,
2526 			.channels_max = 8,
2527 			.rates = MTK_ETDM_RATES,
2528 			.formats = MTK_ETDM_FORMATS,
2529 		},
2530 		.ops = &mtk_dai_hdmitx_dptx_ops,
2531 	},
2532 	{
2533 		.name = "ETDM1_IN",
2534 		.id = MT8195_AFE_IO_ETDM1_IN,
2535 		.capture = {
2536 			.stream_name = "ETDM1 Capture",
2537 			.channels_min = 1,
2538 			.channels_max = 24,
2539 			.rates = MTK_ETDM_RATES,
2540 			.formats = MTK_ETDM_FORMATS,
2541 		},
2542 		.ops = &mtk_dai_etdm_ops,
2543 	},
2544 	{
2545 		.name = "ETDM2_IN",
2546 		.id = MT8195_AFE_IO_ETDM2_IN,
2547 		.capture = {
2548 			.stream_name = "ETDM2 Capture",
2549 			.channels_min = 1,
2550 			.channels_max = 16,
2551 			.rates = MTK_ETDM_RATES,
2552 			.formats = MTK_ETDM_FORMATS,
2553 		},
2554 		.ops = &mtk_dai_etdm_ops,
2555 	},
2556 	{
2557 		.name = "ETDM1_OUT",
2558 		.id = MT8195_AFE_IO_ETDM1_OUT,
2559 		.playback = {
2560 			.stream_name = "ETDM1 Playback",
2561 			.channels_min = 1,
2562 			.channels_max = 24,
2563 			.rates = MTK_ETDM_RATES,
2564 			.formats = MTK_ETDM_FORMATS,
2565 		},
2566 		.ops = &mtk_dai_etdm_ops,
2567 	},
2568 	{
2569 		.name = "ETDM2_OUT",
2570 		.id = MT8195_AFE_IO_ETDM2_OUT,
2571 		.playback = {
2572 			.stream_name = "ETDM2 Playback",
2573 			.channels_min = 1,
2574 			.channels_max = 24,
2575 			.rates = MTK_ETDM_RATES,
2576 			.formats = MTK_ETDM_FORMATS,
2577 		},
2578 		.ops = &mtk_dai_etdm_ops,
2579 	},
2580 	{
2581 		.name = "ETDM3_OUT",
2582 		.id = MT8195_AFE_IO_ETDM3_OUT,
2583 		.playback = {
2584 			.stream_name = "ETDM3 Playback",
2585 			.channels_min = 1,
2586 			.channels_max = 8,
2587 			.rates = MTK_ETDM_RATES,
2588 			.formats = MTK_ETDM_FORMATS,
2589 		},
2590 		.ops = &mtk_dai_hdmitx_dptx_ops2,
2591 	},
2592 };
2593 
mt8195_etdm_update_sync_info(struct mtk_base_afe * afe)2594 static void mt8195_etdm_update_sync_info(struct mtk_base_afe *afe)
2595 {
2596 	struct mt8195_afe_private *afe_priv = afe->platform_priv;
2597 	struct mtk_dai_etdm_priv *etdm_data;
2598 	struct mtk_dai_etdm_priv *mst_data;
2599 	int i;
2600 	int mst_dai_id;
2601 
2602 	for (i = MT8195_AFE_IO_ETDM_START; i < MT8195_AFE_IO_ETDM_END; i++) {
2603 		etdm_data = afe_priv->dai_priv[i];
2604 		if (etdm_data->cowork_source_id != COWORK_ETDM_NONE) {
2605 			mst_dai_id = etdm_data->cowork_source_id;
2606 			if (!mt8195_afe_etdm_is_valid(mst_dai_id)) {
2607 				dev_err(afe->dev, "%s invalid dai id %d\n",
2608 					__func__, mst_dai_id);
2609 				return;
2610 			}
2611 			mst_data = afe_priv->dai_priv[mst_dai_id];
2612 			if (mst_data->cowork_source_id != COWORK_ETDM_NONE)
2613 				dev_info(afe->dev, "%s [%d] wrong sync source\n"
2614 					 , __func__, i);
2615 			mst_data->cowork_slv_id[mst_data->cowork_slv_count] = i;
2616 			mst_data->cowork_slv_count++;
2617 		}
2618 	}
2619 }
2620 
mt8195_dai_etdm_parse_of(struct mtk_base_afe * afe)2621 static void mt8195_dai_etdm_parse_of(struct mtk_base_afe *afe)
2622 {
2623 	const struct device_node *of_node = afe->dev->of_node;
2624 	struct mt8195_afe_private *afe_priv = afe->platform_priv;
2625 	struct mtk_dai_etdm_priv *etdm_data;
2626 	int i, j;
2627 	char prop[48];
2628 	u8 disable_chn[MT8195_ETDM_MAX_CHANNELS];
2629 	int max_chn = MT8195_ETDM_MAX_CHANNELS;
2630 	u32 sel;
2631 	int ret;
2632 	int dai_id;
2633 	unsigned int sync_id;
2634 	struct {
2635 		const char *name;
2636 		const unsigned int sync_id;
2637 	} of_afe_etdms[MT8195_AFE_IO_ETDM_NUM] = {
2638 		{"etdm-in1", ETDM_SYNC_FROM_IN1},
2639 		{"etdm-in2", ETDM_SYNC_FROM_IN2},
2640 		{"etdm-out1", ETDM_SYNC_FROM_OUT1},
2641 		{"etdm-out2", ETDM_SYNC_FROM_OUT2},
2642 		{"etdm-out3", ETDM_SYNC_FROM_OUT3},
2643 	};
2644 
2645 	for (i = 0; i < MT8195_AFE_IO_ETDM_NUM; i++) {
2646 		dai_id = ETDM_TO_DAI_ID(i);
2647 		if (!mt8195_afe_etdm_is_valid(dai_id)) {
2648 			dev_err(afe->dev, "%s invalid dai id %d\n",
2649 				__func__, dai_id);
2650 			return;
2651 		}
2652 
2653 		etdm_data = afe_priv->dai_priv[dai_id];
2654 
2655 		ret = snprintf(prop, sizeof(prop),
2656 			       "mediatek,%s-mclk-always-on-rate",
2657 			       of_afe_etdms[i].name);
2658 		if (ret < 0) {
2659 			dev_info(afe->dev, "%s snprintf err=%d\n",
2660 				 __func__, ret);
2661 			return;
2662 		}
2663 		ret = of_property_read_u32(of_node, prop, &sel);
2664 		if (ret == 0) {
2665 			etdm_data->mclk_dir = SND_SOC_CLOCK_OUT;
2666 			if (mtk_dai_etdm_cal_mclk(afe, sel, dai_id))
2667 				dev_info(afe->dev, "%s unsupported mclk %uHz\n",
2668 					 __func__, sel);
2669 		}
2670 
2671 		ret = snprintf(prop, sizeof(prop),
2672 			       "mediatek,%s-multi-pin-mode",
2673 			       of_afe_etdms[i].name);
2674 		if (ret < 0) {
2675 			dev_info(afe->dev, "%s snprintf err=%d\n",
2676 				 __func__, ret);
2677 			return;
2678 		}
2679 		etdm_data->data_mode = of_property_read_bool(of_node, prop);
2680 
2681 		ret = snprintf(prop, sizeof(prop),
2682 			       "mediatek,%s-cowork-source",
2683 			       of_afe_etdms[i].name);
2684 		if (ret < 0) {
2685 			dev_info(afe->dev, "%s snprintf err=%d\n",
2686 				 __func__, ret);
2687 			return;
2688 		}
2689 		ret = of_property_read_u32(of_node, prop, &sel);
2690 		if (ret == 0) {
2691 			if (sel >= MT8195_AFE_IO_ETDM_NUM) {
2692 				dev_info(afe->dev, "%s invalid id=%d\n",
2693 					 __func__, sel);
2694 				etdm_data->cowork_source_id = COWORK_ETDM_NONE;
2695 			} else {
2696 				sync_id = of_afe_etdms[sel].sync_id;
2697 				etdm_data->cowork_source_id =
2698 					sync_to_dai_id(sync_id);
2699 			}
2700 		} else {
2701 			etdm_data->cowork_source_id = COWORK_ETDM_NONE;
2702 		}
2703 	}
2704 
2705 	/* etdm in only */
2706 	for (i = 0; i < 2; i++) {
2707 		dai_id = ETDM_TO_DAI_ID(i);
2708 		etdm_data = afe_priv->dai_priv[dai_id];
2709 
2710 		ret = snprintf(prop, sizeof(prop),
2711 			       "mediatek,%s-chn-disabled",
2712 			       of_afe_etdms[i].name);
2713 		if (ret < 0) {
2714 			dev_info(afe->dev, "%s snprintf err=%d\n",
2715 				 __func__, ret);
2716 			return;
2717 		}
2718 		ret = of_property_read_variable_u8_array(of_node, prop,
2719 							 disable_chn,
2720 							 1, max_chn);
2721 		if (ret < 0)
2722 			continue;
2723 
2724 		for (j = 0; j < ret; j++) {
2725 			if (disable_chn[j] >= MT8195_ETDM_MAX_CHANNELS)
2726 				dev_info(afe->dev, "%s [%d] invalid chn %u\n",
2727 					 __func__, j, disable_chn[j]);
2728 			else
2729 				etdm_data->in_disable_ch[disable_chn[j]] = true;
2730 		}
2731 	}
2732 	mt8195_etdm_update_sync_info(afe);
2733 }
2734 
init_etdm_priv_data(struct mtk_base_afe * afe)2735 static int init_etdm_priv_data(struct mtk_base_afe *afe)
2736 {
2737 	struct mt8195_afe_private *afe_priv = afe->platform_priv;
2738 	struct mtk_dai_etdm_priv *etdm_priv;
2739 	int i;
2740 
2741 	for (i = MT8195_AFE_IO_ETDM_START; i < MT8195_AFE_IO_ETDM_END; i++) {
2742 		etdm_priv = devm_kzalloc(afe->dev,
2743 					 sizeof(struct mtk_dai_etdm_priv),
2744 					 GFP_KERNEL);
2745 		if (!etdm_priv)
2746 			return -ENOMEM;
2747 
2748 		afe_priv->dai_priv[i] = etdm_priv;
2749 	}
2750 
2751 	afe_priv->dai_priv[MT8195_AFE_IO_DPTX] =
2752 		afe_priv->dai_priv[MT8195_AFE_IO_ETDM3_OUT];
2753 
2754 	mt8195_dai_etdm_parse_of(afe);
2755 	return 0;
2756 }
2757 
mt8195_dai_etdm_register(struct mtk_base_afe * afe)2758 int mt8195_dai_etdm_register(struct mtk_base_afe *afe)
2759 {
2760 	struct mtk_base_afe_dai *dai;
2761 
2762 	dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);
2763 	if (!dai)
2764 		return -ENOMEM;
2765 
2766 	list_add(&dai->list, &afe->sub_dais);
2767 
2768 	dai->dai_drivers = mtk_dai_etdm_driver;
2769 	dai->num_dai_drivers = ARRAY_SIZE(mtk_dai_etdm_driver);
2770 
2771 	dai->dapm_widgets = mtk_dai_etdm_widgets;
2772 	dai->num_dapm_widgets = ARRAY_SIZE(mtk_dai_etdm_widgets);
2773 	dai->dapm_routes = mtk_dai_etdm_routes;
2774 	dai->num_dapm_routes = ARRAY_SIZE(mtk_dai_etdm_routes);
2775 	dai->controls = mtk_dai_etdm_controls;
2776 	dai->num_controls = ARRAY_SIZE(mtk_dai_etdm_controls);
2777 
2778 	return init_etdm_priv_data(afe);
2779 }
2780