1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2015 MediaTek Inc.
4 * Author: Hongzhou.Yang <hongzhou.yang@mediatek.com>
5 * Yingjoe Chen <yingjoe.chen@mediatek.com>
6 */
7
8 #include <linux/init.h>
9 #include <linux/platform_device.h>
10 #include <linux/of.h>
11 #include <linux/pinctrl/pinctrl.h>
12 #include <linux/regmap.h>
13 #include <dt-bindings/pinctrl/mt65xx.h>
14
15 #include "pinctrl-mtk-common.h"
16 #include "pinctrl-mtk-mt8127.h"
17
18 static const struct mtk_drv_group_desc mt8127_drv_grp[] = {
19 /* 0E4E8SR 4/8/12/16 */
20 MTK_DRV_GRP(4, 16, 1, 2, 4),
21 /* 0E2E4SR 2/4/6/8 */
22 MTK_DRV_GRP(2, 8, 1, 2, 2),
23 /* E8E4E2 2/4/6/8/10/12/14/16 */
24 MTK_DRV_GRP(2, 16, 0, 2, 2)
25 };
26
27 static const struct mtk_pin_drv_grp mt8127_pin_drv[] = {
28 MTK_PIN_DRV_GRP(0, 0xb00, 0, 1),
29 MTK_PIN_DRV_GRP(1, 0xb00, 0, 1),
30 MTK_PIN_DRV_GRP(2, 0xb00, 0, 1),
31 MTK_PIN_DRV_GRP(3, 0xb00, 0, 1),
32 MTK_PIN_DRV_GRP(4, 0xb00, 0, 1),
33 MTK_PIN_DRV_GRP(5, 0xb00, 0, 1),
34 MTK_PIN_DRV_GRP(6, 0xb00, 0, 1),
35 MTK_PIN_DRV_GRP(7, 0xb00, 12, 1),
36 MTK_PIN_DRV_GRP(8, 0xb00, 12, 1),
37 MTK_PIN_DRV_GRP(9, 0xb00, 12, 1),
38 MTK_PIN_DRV_GRP(10, 0xb00, 8, 1),
39 MTK_PIN_DRV_GRP(11, 0xb00, 8, 1),
40 MTK_PIN_DRV_GRP(12, 0xb00, 8, 1),
41 MTK_PIN_DRV_GRP(13, 0xb00, 8, 1),
42 MTK_PIN_DRV_GRP(14, 0xb10, 4, 0),
43 MTK_PIN_DRV_GRP(15, 0xb10, 4, 0),
44 MTK_PIN_DRV_GRP(16, 0xb10, 4, 0),
45 MTK_PIN_DRV_GRP(17, 0xb10, 4, 0),
46 MTK_PIN_DRV_GRP(18, 0xb10, 8, 0),
47 MTK_PIN_DRV_GRP(19, 0xb10, 8, 0),
48 MTK_PIN_DRV_GRP(20, 0xb10, 8, 0),
49 MTK_PIN_DRV_GRP(21, 0xb10, 8, 0),
50 MTK_PIN_DRV_GRP(22, 0xb20, 0, 0),
51 MTK_PIN_DRV_GRP(23, 0xb20, 0, 0),
52 MTK_PIN_DRV_GRP(24, 0xb20, 0, 0),
53 MTK_PIN_DRV_GRP(25, 0xb20, 0, 0),
54 MTK_PIN_DRV_GRP(26, 0xb20, 0, 0),
55 MTK_PIN_DRV_GRP(27, 0xb20, 4, 0),
56 MTK_PIN_DRV_GRP(28, 0xb20, 4, 0),
57 MTK_PIN_DRV_GRP(29, 0xb20, 4, 0),
58 MTK_PIN_DRV_GRP(30, 0xb20, 4, 0),
59 MTK_PIN_DRV_GRP(31, 0xb20, 4, 0),
60 MTK_PIN_DRV_GRP(32, 0xb20, 4, 0),
61 MTK_PIN_DRV_GRP(33, 0xb30, 4, 1),
62 MTK_PIN_DRV_GRP(34, 0xb30, 8, 1),
63 MTK_PIN_DRV_GRP(35, 0xb30, 8, 1),
64 MTK_PIN_DRV_GRP(36, 0xb30, 8, 1),
65 MTK_PIN_DRV_GRP(37, 0xb30, 8, 1),
66 MTK_PIN_DRV_GRP(38, 0xb30, 8, 1),
67 MTK_PIN_DRV_GRP(39, 0xb30, 12, 1),
68 MTK_PIN_DRV_GRP(40, 0xb30, 12, 1),
69 MTK_PIN_DRV_GRP(41, 0xb30, 12, 1),
70 MTK_PIN_DRV_GRP(42, 0xb30, 12, 1),
71 MTK_PIN_DRV_GRP(43, 0xb40, 12, 0),
72 MTK_PIN_DRV_GRP(44, 0xb40, 12, 0),
73 MTK_PIN_DRV_GRP(45, 0xb40, 12, 0),
74 MTK_PIN_DRV_GRP(46, 0xb50, 0, 2),
75 MTK_PIN_DRV_GRP(47, 0xb50, 0, 2),
76 MTK_PIN_DRV_GRP(48, 0xb50, 0, 2),
77 MTK_PIN_DRV_GRP(49, 0xb50, 0, 2),
78 MTK_PIN_DRV_GRP(50, 0xb70, 0, 1),
79 MTK_PIN_DRV_GRP(51, 0xb70, 0, 1),
80 MTK_PIN_DRV_GRP(52, 0xb70, 0, 1),
81 MTK_PIN_DRV_GRP(53, 0xb50, 12, 1),
82 MTK_PIN_DRV_GRP(54, 0xb50, 12, 1),
83 MTK_PIN_DRV_GRP(55, 0xb50, 12, 1),
84 MTK_PIN_DRV_GRP(56, 0xb50, 12, 1),
85 MTK_PIN_DRV_GRP(59, 0xb40, 4, 1),
86 MTK_PIN_DRV_GRP(60, 0xb40, 0, 1),
87 MTK_PIN_DRV_GRP(61, 0xb40, 0, 1),
88 MTK_PIN_DRV_GRP(62, 0xb40, 0, 1),
89 MTK_PIN_DRV_GRP(63, 0xb40, 4, 1),
90 MTK_PIN_DRV_GRP(64, 0xb40, 4, 1),
91 MTK_PIN_DRV_GRP(65, 0xb40, 4, 1),
92 MTK_PIN_DRV_GRP(66, 0xb40, 8, 1),
93 MTK_PIN_DRV_GRP(67, 0xb40, 8, 1),
94 MTK_PIN_DRV_GRP(68, 0xb40, 8, 1),
95 MTK_PIN_DRV_GRP(69, 0xb40, 8, 1),
96 MTK_PIN_DRV_GRP(70, 0xb40, 8, 1),
97 MTK_PIN_DRV_GRP(71, 0xb40, 8, 1),
98 MTK_PIN_DRV_GRP(72, 0xb50, 4, 1),
99 MTK_PIN_DRV_GRP(73, 0xb50, 4, 1),
100 MTK_PIN_DRV_GRP(74, 0xb50, 4, 1),
101 MTK_PIN_DRV_GRP(79, 0xb50, 8, 1),
102 MTK_PIN_DRV_GRP(80, 0xb50, 8, 1),
103 MTK_PIN_DRV_GRP(81, 0xb50, 8, 1),
104 MTK_PIN_DRV_GRP(82, 0xb50, 8, 1),
105 MTK_PIN_DRV_GRP(83, 0xb50, 8, 1),
106 MTK_PIN_DRV_GRP(84, 0xb50, 8, 1),
107 MTK_PIN_DRV_GRP(85, 0xce0, 0, 2),
108 MTK_PIN_DRV_GRP(86, 0xcd0, 0, 2),
109 MTK_PIN_DRV_GRP(87, 0xcf0, 0, 2),
110 MTK_PIN_DRV_GRP(88, 0xcf0, 0, 2),
111 MTK_PIN_DRV_GRP(89, 0xcf0, 0, 2),
112 MTK_PIN_DRV_GRP(90, 0xcf0, 0, 2),
113 MTK_PIN_DRV_GRP(117, 0xb60, 12, 1),
114 MTK_PIN_DRV_GRP(118, 0xb60, 12, 1),
115 MTK_PIN_DRV_GRP(119, 0xb60, 12, 1),
116 MTK_PIN_DRV_GRP(120, 0xb60, 12, 1),
117 MTK_PIN_DRV_GRP(121, 0xc80, 0, 2),
118 MTK_PIN_DRV_GRP(122, 0xc70, 0, 2),
119 MTK_PIN_DRV_GRP(123, 0xc90, 0, 2),
120 MTK_PIN_DRV_GRP(124, 0xc90, 0, 2),
121 MTK_PIN_DRV_GRP(125, 0xc90, 0, 2),
122 MTK_PIN_DRV_GRP(126, 0xc90, 0, 2),
123 MTK_PIN_DRV_GRP(127, 0xc20, 0, 2),
124 MTK_PIN_DRV_GRP(128, 0xc20, 0, 2),
125 MTK_PIN_DRV_GRP(129, 0xc20, 0, 2),
126 MTK_PIN_DRV_GRP(130, 0xc20, 0, 2),
127 MTK_PIN_DRV_GRP(131, 0xc20, 0, 2),
128 MTK_PIN_DRV_GRP(132, 0xc10, 0, 2),
129 MTK_PIN_DRV_GRP(133, 0xc00, 0, 2),
130 MTK_PIN_DRV_GRP(134, 0xc20, 0, 2),
131 MTK_PIN_DRV_GRP(135, 0xc20, 0, 2),
132 MTK_PIN_DRV_GRP(136, 0xc20, 0, 2),
133 MTK_PIN_DRV_GRP(137, 0xc20, 0, 2),
134 MTK_PIN_DRV_GRP(142, 0xb50, 0, 2),
135 };
136
137 static const struct mtk_pin_spec_pupd_set_samereg mt8127_spec_pupd[] = {
138 MTK_PIN_PUPD_SPEC_SR(33, 0xd90, 2, 0, 1), /* KPROW0 */
139 MTK_PIN_PUPD_SPEC_SR(34, 0xd90, 6, 4, 5), /* KPROW1 */
140 MTK_PIN_PUPD_SPEC_SR(35, 0xd90, 10, 8, 9), /* KPROW2 */
141 MTK_PIN_PUPD_SPEC_SR(36, 0xda0, 2, 0, 1), /* KPCOL0 */
142 MTK_PIN_PUPD_SPEC_SR(37, 0xda0, 6, 4, 5), /* KPCOL1 */
143 MTK_PIN_PUPD_SPEC_SR(38, 0xda0, 10, 8, 9), /* KPCOL2 */
144 MTK_PIN_PUPD_SPEC_SR(46, 0xdb0, 2, 0, 1), /* EINT14 */
145 MTK_PIN_PUPD_SPEC_SR(47, 0xdb0, 6, 4, 5), /* EINT15 */
146 MTK_PIN_PUPD_SPEC_SR(48, 0xdb0, 10, 8, 9), /* EINT16 */
147 MTK_PIN_PUPD_SPEC_SR(49, 0xdb0, 14, 12, 13), /* EINT17 */
148 MTK_PIN_PUPD_SPEC_SR(85, 0xce0, 8, 10, 9), /* MSDC2_CMD */
149 MTK_PIN_PUPD_SPEC_SR(86, 0xcd0, 8, 10, 9), /* MSDC2_CLK */
150 MTK_PIN_PUPD_SPEC_SR(87, 0xd00, 0, 2, 1), /* MSDC2_DAT0 */
151 MTK_PIN_PUPD_SPEC_SR(88, 0xd00, 4, 6, 5), /* MSDC2_DAT1 */
152 MTK_PIN_PUPD_SPEC_SR(89, 0xd00, 8, 10, 9), /* MSDC2_DAT2 */
153 MTK_PIN_PUPD_SPEC_SR(90, 0xd00, 12, 14, 13), /* MSDC2_DAT3 */
154 MTK_PIN_PUPD_SPEC_SR(121, 0xc80, 8, 10, 9), /* MSDC1_CMD */
155 MTK_PIN_PUPD_SPEC_SR(122, 0xc70, 8, 10, 9), /* MSDC1_CLK */
156 MTK_PIN_PUPD_SPEC_SR(123, 0xca0, 0, 2, 1), /* MSDC1_DAT0 */
157 MTK_PIN_PUPD_SPEC_SR(124, 0xca0, 4, 6, 5), /* MSDC1_DAT1 */
158 MTK_PIN_PUPD_SPEC_SR(125, 0xca0, 8, 10, 9), /* MSDC1_DAT2 */
159 MTK_PIN_PUPD_SPEC_SR(126, 0xca0, 12, 14, 13), /* MSDC1_DAT3 */
160 MTK_PIN_PUPD_SPEC_SR(127, 0xc40, 12, 14, 13), /* MSDC0_DAT7 */
161 MTK_PIN_PUPD_SPEC_SR(128, 0xc40, 8, 10, 9), /* MSDC0_DAT6 */
162 MTK_PIN_PUPD_SPEC_SR(129, 0xc40, 4, 6, 5), /* MSDC0_DAT5 */
163 MTK_PIN_PUPD_SPEC_SR(130, 0xc40, 0, 2, 1), /* MSDC0_DAT4 */
164 MTK_PIN_PUPD_SPEC_SR(131, 0xc50, 0, 2, 1), /* MSDC0_RSTB */
165 MTK_PIN_PUPD_SPEC_SR(132, 0xc10, 8, 10, 9), /* MSDC0_CMD */
166 MTK_PIN_PUPD_SPEC_SR(133, 0xc00, 8, 10, 9), /* MSDC0_CLK */
167 MTK_PIN_PUPD_SPEC_SR(134, 0xc30, 12, 14, 13), /* MSDC0_DAT3 */
168 MTK_PIN_PUPD_SPEC_SR(135, 0xc30, 8, 10, 9), /* MSDC0_DAT2 */
169 MTK_PIN_PUPD_SPEC_SR(136, 0xc30, 4, 6, 5), /* MSDC0_DAT1 */
170 MTK_PIN_PUPD_SPEC_SR(137, 0xc30, 0, 2, 1), /* MSDC0_DAT0 */
171 MTK_PIN_PUPD_SPEC_SR(142, 0xdc0, 2, 0, 1), /* EINT21 */
172 };
173
174 static const struct mtk_pin_ies_smt_set mt8127_ies_set[] = {
175 MTK_PIN_IES_SMT_SPEC(0, 9, 0x900, 0),
176 MTK_PIN_IES_SMT_SPEC(10, 13, 0x900, 1),
177 MTK_PIN_IES_SMT_SPEC(14, 28, 0x900, 2),
178 MTK_PIN_IES_SMT_SPEC(29, 32, 0x900, 3),
179 MTK_PIN_IES_SMT_SPEC(33, 33, 0x910, 11),
180 MTK_PIN_IES_SMT_SPEC(34, 38, 0x900, 10),
181 MTK_PIN_IES_SMT_SPEC(39, 42, 0x900, 11),
182 MTK_PIN_IES_SMT_SPEC(43, 45, 0x900, 12),
183 MTK_PIN_IES_SMT_SPEC(46, 49, 0x900, 13),
184 MTK_PIN_IES_SMT_SPEC(50, 52, 0x910, 10),
185 MTK_PIN_IES_SMT_SPEC(53, 56, 0x900, 14),
186 MTK_PIN_IES_SMT_SPEC(57, 58, 0x910, 0),
187 MTK_PIN_IES_SMT_SPEC(59, 65, 0x910, 2),
188 MTK_PIN_IES_SMT_SPEC(66, 71, 0x910, 3),
189 MTK_PIN_IES_SMT_SPEC(72, 74, 0x910, 4),
190 MTK_PIN_IES_SMT_SPEC(75, 76, 0x900, 15),
191 MTK_PIN_IES_SMT_SPEC(77, 78, 0x910, 1),
192 MTK_PIN_IES_SMT_SPEC(79, 82, 0x910, 5),
193 MTK_PIN_IES_SMT_SPEC(83, 84, 0x910, 6),
194 MTK_PIN_IES_SMT_SPEC(117, 120, 0x910, 7),
195 MTK_PIN_IES_SMT_SPEC(121, 121, 0xc80, 4),
196 MTK_PIN_IES_SMT_SPEC(122, 122, 0xc70, 4),
197 MTK_PIN_IES_SMT_SPEC(123, 126, 0xc90, 4),
198 MTK_PIN_IES_SMT_SPEC(127, 131, 0xc20, 4),
199 MTK_PIN_IES_SMT_SPEC(132, 132, 0xc10, 4),
200 MTK_PIN_IES_SMT_SPEC(133, 133, 0xc00, 4),
201 MTK_PIN_IES_SMT_SPEC(134, 137, 0xc20, 4),
202 MTK_PIN_IES_SMT_SPEC(138, 141, 0x910, 9),
203 MTK_PIN_IES_SMT_SPEC(142, 142, 0x900, 13),
204 };
205
206 static const struct mtk_pin_ies_smt_set mt8127_smt_set[] = {
207 MTK_PIN_IES_SMT_SPEC(0, 9, 0x920, 0),
208 MTK_PIN_IES_SMT_SPEC(10, 13, 0x920, 1),
209 MTK_PIN_IES_SMT_SPEC(14, 28, 0x920, 2),
210 MTK_PIN_IES_SMT_SPEC(29, 32, 0x920, 3),
211 MTK_PIN_IES_SMT_SPEC(33, 33, 0x930, 11),
212 MTK_PIN_IES_SMT_SPEC(34, 38, 0x920, 10),
213 MTK_PIN_IES_SMT_SPEC(39, 42, 0x920, 11),
214 MTK_PIN_IES_SMT_SPEC(43, 45, 0x920, 12),
215 MTK_PIN_IES_SMT_SPEC(46, 49, 0x920, 13),
216 MTK_PIN_IES_SMT_SPEC(50, 52, 0x930, 10),
217 MTK_PIN_IES_SMT_SPEC(53, 56, 0x920, 14),
218 MTK_PIN_IES_SMT_SPEC(57, 58, 0x930, 0),
219 MTK_PIN_IES_SMT_SPEC(59, 65, 0x930, 2),
220 MTK_PIN_IES_SMT_SPEC(66, 71, 0x930, 3),
221 MTK_PIN_IES_SMT_SPEC(72, 74, 0x930, 4),
222 MTK_PIN_IES_SMT_SPEC(75, 76, 0x920, 15),
223 MTK_PIN_IES_SMT_SPEC(77, 78, 0x930, 1),
224 MTK_PIN_IES_SMT_SPEC(79, 82, 0x930, 5),
225 MTK_PIN_IES_SMT_SPEC(83, 84, 0x930, 6),
226 MTK_PIN_IES_SMT_SPEC(85, 85, 0xce0, 11),
227 MTK_PIN_IES_SMT_SPEC(86, 86, 0xcd0, 11),
228 MTK_PIN_IES_SMT_SPEC(87, 87, 0xd00, 3),
229 MTK_PIN_IES_SMT_SPEC(88, 88, 0xd00, 7),
230 MTK_PIN_IES_SMT_SPEC(89, 89, 0xd00, 11),
231 MTK_PIN_IES_SMT_SPEC(90, 90, 0xd00, 15),
232 MTK_PIN_IES_SMT_SPEC(117, 120, 0x930, 7),
233 MTK_PIN_IES_SMT_SPEC(121, 121, 0xc80, 11),
234 MTK_PIN_IES_SMT_SPEC(122, 122, 0xc70, 11),
235 MTK_PIN_IES_SMT_SPEC(123, 123, 0xca0, 3),
236 MTK_PIN_IES_SMT_SPEC(124, 124, 0xca0, 7),
237 MTK_PIN_IES_SMT_SPEC(125, 125, 0xca0, 11),
238 MTK_PIN_IES_SMT_SPEC(126, 126, 0xca0, 15),
239 MTK_PIN_IES_SMT_SPEC(127, 127, 0xc40, 15),
240 MTK_PIN_IES_SMT_SPEC(128, 128, 0xc40, 11),
241 MTK_PIN_IES_SMT_SPEC(129, 129, 0xc40, 7),
242 MTK_PIN_IES_SMT_SPEC(130, 130, 0xc40, 3),
243 MTK_PIN_IES_SMT_SPEC(131, 131, 0xc50, 3),
244 MTK_PIN_IES_SMT_SPEC(132, 132, 0xc10, 11),
245 MTK_PIN_IES_SMT_SPEC(133, 133, 0xc00, 11),
246 MTK_PIN_IES_SMT_SPEC(134, 134, 0xc30, 15),
247 MTK_PIN_IES_SMT_SPEC(135, 135, 0xc30, 11),
248 MTK_PIN_IES_SMT_SPEC(136, 136, 0xc30, 7),
249 MTK_PIN_IES_SMT_SPEC(137, 137, 0xc30, 3),
250 MTK_PIN_IES_SMT_SPEC(138, 141, 0x930, 9),
251 MTK_PIN_IES_SMT_SPEC(142, 142, 0x920, 13),
252 };
253
254 static const struct mtk_pinctrl_devdata mt8127_pinctrl_data = {
255 .pins = mtk_pins_mt8127,
256 .npins = ARRAY_SIZE(mtk_pins_mt8127),
257 .grp_desc = mt8127_drv_grp,
258 .n_grp_cls = ARRAY_SIZE(mt8127_drv_grp),
259 .pin_drv_grp = mt8127_pin_drv,
260 .n_pin_drv_grps = ARRAY_SIZE(mt8127_pin_drv),
261 .spec_ies = mt8127_ies_set,
262 .n_spec_ies = ARRAY_SIZE(mt8127_ies_set),
263 .spec_pupd = mt8127_spec_pupd,
264 .n_spec_pupd = ARRAY_SIZE(mt8127_spec_pupd),
265 .spec_smt = mt8127_smt_set,
266 .n_spec_smt = ARRAY_SIZE(mt8127_smt_set),
267 .spec_pull_set = mtk_pctrl_spec_pull_set_samereg,
268 .spec_ies_smt_set = mtk_pconf_spec_set_ies_smt_range,
269 .dir_offset = 0x0000,
270 .pullen_offset = 0x0100,
271 .pullsel_offset = 0x0200,
272 .dout_offset = 0x0400,
273 .din_offset = 0x0500,
274 .pinmux_offset = 0x0600,
275 .type1_start = 143,
276 .type1_end = 143,
277 .port_shf = 4,
278 .port_mask = 0xf,
279 .port_align = 4,
280 .mode_mask = 0xf,
281 .mode_per_reg = 5,
282 .mode_shf = 4,
283 .eint_hw = {
284 .port_mask = 7,
285 .ports = 6,
286 .ap_num = 143,
287 .db_cnt = 16,
288 .db_time = debounce_time_mt2701,
289 },
290 };
291
292 static const struct of_device_id mt8127_pctrl_match[] = {
293 { .compatible = "mediatek,mt8127-pinctrl", .data = &mt8127_pinctrl_data },
294 { }
295 };
296
297 static struct platform_driver mtk_pinctrl_driver = {
298 .probe = mtk_pctrl_common_probe,
299 .driver = {
300 .name = "mediatek-mt8127-pinctrl",
301 .of_match_table = mt8127_pctrl_match,
302 },
303 };
304
mtk_pinctrl_init(void)305 static int __init mtk_pinctrl_init(void)
306 {
307 return platform_driver_register(&mtk_pinctrl_driver);
308 }
309 arch_initcall(mtk_pinctrl_init);
310