1 // SPDX-License-Identifier: ISC
2 /*
3 * Copyright (C) 2022 MediaTek Inc.
4 */
5
6 #include <linux/kernel.h>
7 #include <linux/module.h>
8 #include <linux/pci.h>
9
10 #include "mt7996.h"
11 #include "mac.h"
12 #include "../trace.h"
13
14 static const struct __base mt7996_reg_base[] = {
15 [WF_AGG_BASE] = { { 0x820e2000, 0x820f2000, 0x830e2000 } },
16 [WF_ARB_BASE] = { { 0x820e3000, 0x820f3000, 0x830e3000 } },
17 [WF_TMAC_BASE] = { { 0x820e4000, 0x820f4000, 0x830e4000 } },
18 [WF_RMAC_BASE] = { { 0x820e5000, 0x820f5000, 0x830e5000 } },
19 [WF_DMA_BASE] = { { 0x820e7000, 0x820f7000, 0x830e7000 } },
20 [WF_WTBLOFF_BASE] = { { 0x820e9000, 0x820f9000, 0x830e9000 } },
21 [WF_ETBF_BASE] = { { 0x820ea000, 0x820fa000, 0x830ea000 } },
22 [WF_LPON_BASE] = { { 0x820eb000, 0x820fb000, 0x830eb000 } },
23 [WF_MIB_BASE] = { { 0x820ed000, 0x820fd000, 0x830ed000 } },
24 [WF_RATE_BASE] = { { 0x820ee000, 0x820fe000, 0x830ee000 } },
25 };
26
27 static const struct __map mt7996_reg_map[] = {
28 { 0x54000000, 0x02000, 0x1000 }, /* WFDMA_0 (PCIE0 MCU DMA0) */
29 { 0x55000000, 0x03000, 0x1000 }, /* WFDMA_1 (PCIE0 MCU DMA1) */
30 { 0x56000000, 0x04000, 0x1000 }, /* WFDMA reserved */
31 { 0x57000000, 0x05000, 0x1000 }, /* WFDMA MCU wrap CR */
32 { 0x58000000, 0x06000, 0x1000 }, /* WFDMA PCIE1 MCU DMA0 (MEM_DMA) */
33 { 0x59000000, 0x07000, 0x1000 }, /* WFDMA PCIE1 MCU DMA1 */
34 { 0x820c0000, 0x08000, 0x4000 }, /* WF_UMAC_TOP (PLE) */
35 { 0x820c8000, 0x0c000, 0x2000 }, /* WF_UMAC_TOP (PSE) */
36 { 0x820cc000, 0x0e000, 0x1000 }, /* WF_UMAC_TOP (PP) */
37 { 0x74030000, 0x10000, 0x1000 }, /* PCIe MAC */
38 { 0x820e0000, 0x20000, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_CFG) */
39 { 0x820e1000, 0x20400, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_TRB) */
40 { 0x820e2000, 0x20800, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_AGG) */
41 { 0x820e3000, 0x20c00, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_ARB) */
42 { 0x820e4000, 0x21000, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_TMAC) */
43 { 0x820e5000, 0x21400, 0x0800 }, /* WF_LMAC_TOP BN0 (WF_RMAC) */
44 { 0x820ce000, 0x21c00, 0x0200 }, /* WF_LMAC_TOP (WF_SEC) */
45 { 0x820e7000, 0x21e00, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_DMA) */
46 { 0x820cf000, 0x22000, 0x1000 }, /* WF_LMAC_TOP (WF_PF) */
47 { 0x820e9000, 0x23400, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_WTBLOFF) */
48 { 0x820ea000, 0x24000, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_ETBF) */
49 { 0x820eb000, 0x24200, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_LPON) */
50 { 0x820ec000, 0x24600, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_INT) */
51 { 0x820ed000, 0x24800, 0x0800 }, /* WF_LMAC_TOP BN0 (WF_MIB) */
52 { 0x820ca000, 0x26000, 0x2000 }, /* WF_LMAC_TOP BN0 (WF_MUCOP) */
53 { 0x820d0000, 0x30000, 0x10000 }, /* WF_LMAC_TOP (WF_WTBLON) */
54 { 0x40000000, 0x70000, 0x10000 }, /* WF_UMAC_SYSRAM */
55 { 0x00400000, 0x80000, 0x10000 }, /* WF_MCU_SYSRAM */
56 { 0x00410000, 0x90000, 0x10000 }, /* WF_MCU_SYSRAM (configure register) */
57 { 0x820f0000, 0xa0000, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_CFG) */
58 { 0x820f1000, 0xa0600, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_TRB) */
59 { 0x820f2000, 0xa0800, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_AGG) */
60 { 0x820f3000, 0xa0c00, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_ARB) */
61 { 0x820f4000, 0xa1000, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_TMAC) */
62 { 0x820f5000, 0xa1400, 0x0800 }, /* WF_LMAC_TOP BN1 (WF_RMAC) */
63 { 0x820f7000, 0xa1e00, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_DMA) */
64 { 0x820f9000, 0xa3400, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_WTBLOFF) */
65 { 0x820fa000, 0xa4000, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_ETBF) */
66 { 0x820fb000, 0xa4200, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_LPON) */
67 { 0x820fc000, 0xa4600, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_INT) */
68 { 0x820fd000, 0xa4800, 0x0800 }, /* WF_LMAC_TOP BN1 (WF_MIB) */
69 { 0x820cc000, 0xa5000, 0x2000 }, /* WF_LMAC_TOP BN1 (WF_MUCOP) */
70 { 0x820c4000, 0xa8000, 0x4000 }, /* WF_LMAC_TOP BN1 (WF_MUCOP) */
71 { 0x820b0000, 0xae000, 0x1000 }, /* [APB2] WFSYS_ON */
72 { 0x80020000, 0xb0000, 0x10000 }, /* WF_TOP_MISC_OFF */
73 { 0x81020000, 0xc0000, 0x10000 }, /* WF_TOP_MISC_ON */
74 { 0x7c020000, 0xd0000, 0x10000 }, /* CONN_INFRA, wfdma */
75 { 0x7c060000, 0xe0000, 0x10000 }, /* CONN_INFRA, conn_host_csr_top */
76 { 0x7c000000, 0xf0000, 0x10000 }, /* CONN_INFRA */
77 { 0x0, 0x0, 0x0 }, /* imply end of search */
78 };
79
mt7996_reg_map_l1(struct mt7996_dev * dev,u32 addr)80 static u32 mt7996_reg_map_l1(struct mt7996_dev *dev, u32 addr)
81 {
82 u32 offset = FIELD_GET(MT_HIF_REMAP_L1_OFFSET, addr);
83 u32 base = FIELD_GET(MT_HIF_REMAP_L1_BASE, addr);
84
85 dev->bus_ops->rmw(&dev->mt76, MT_HIF_REMAP_L1,
86 MT_HIF_REMAP_L1_MASK,
87 FIELD_PREP(MT_HIF_REMAP_L1_MASK, base));
88 /* use read to push write */
89 dev->bus_ops->rr(&dev->mt76, MT_HIF_REMAP_L1);
90
91 return MT_HIF_REMAP_BASE_L1 + offset;
92 }
93
mt7996_reg_map_l2(struct mt7996_dev * dev,u32 addr)94 static u32 mt7996_reg_map_l2(struct mt7996_dev *dev, u32 addr)
95 {
96 u32 offset = FIELD_GET(MT_HIF_REMAP_L2_OFFSET, addr);
97 u32 base = FIELD_GET(MT_HIF_REMAP_L2_BASE, addr);
98
99 dev->bus_ops->rmw(&dev->mt76, MT_HIF_REMAP_L2,
100 MT_HIF_REMAP_L2_MASK,
101 FIELD_PREP(MT_HIF_REMAP_L2_MASK, base));
102 /* use read to push write */
103 dev->bus_ops->rr(&dev->mt76, MT_HIF_REMAP_L2);
104
105 return MT_HIF_REMAP_BASE_L2 + offset;
106 }
107
__mt7996_reg_addr(struct mt7996_dev * dev,u32 addr)108 static u32 __mt7996_reg_addr(struct mt7996_dev *dev, u32 addr)
109 {
110 int i;
111
112 if (addr < 0x100000)
113 return addr;
114
115 for (i = 0; i < dev->reg.map_size; i++) {
116 u32 ofs;
117
118 if (addr < dev->reg.map[i].phys)
119 continue;
120
121 ofs = addr - dev->reg.map[i].phys;
122 if (ofs > dev->reg.map[i].size)
123 continue;
124
125 return dev->reg.map[i].mapped + ofs;
126 }
127
128 return 0;
129 }
130
__mt7996_reg_remap_addr(struct mt7996_dev * dev,u32 addr)131 static u32 __mt7996_reg_remap_addr(struct mt7996_dev *dev, u32 addr)
132 {
133 if ((addr >= MT_INFRA_BASE && addr < MT_WFSYS0_PHY_START) ||
134 (addr >= MT_WFSYS0_PHY_START && addr < MT_WFSYS1_PHY_START) ||
135 (addr >= MT_WFSYS1_PHY_START && addr <= MT_WFSYS1_PHY_END))
136 return mt7996_reg_map_l1(dev, addr);
137
138 if (dev_is_pci(dev->mt76.dev) &&
139 ((addr >= MT_CBTOP1_PHY_START && addr <= MT_CBTOP1_PHY_END) ||
140 addr >= MT_CBTOP2_PHY_START))
141 return mt7996_reg_map_l1(dev, addr);
142
143 /* CONN_INFRA: covert to phyiscal addr and use layer 1 remap */
144 if (addr >= MT_INFRA_MCU_START && addr <= MT_INFRA_MCU_END) {
145 addr = addr - MT_INFRA_MCU_START + MT_INFRA_BASE;
146 return mt7996_reg_map_l1(dev, addr);
147 }
148
149 return mt7996_reg_map_l2(dev, addr);
150 }
151
mt7996_memcpy_fromio(struct mt7996_dev * dev,void * buf,u32 offset,size_t len)152 void mt7996_memcpy_fromio(struct mt7996_dev *dev, void *buf, u32 offset,
153 size_t len)
154 {
155 u32 addr = __mt7996_reg_addr(dev, offset);
156
157 if (addr) {
158 memcpy_fromio(buf, dev->mt76.mmio.regs + addr, len);
159 return;
160 }
161
162 spin_lock_bh(&dev->reg_lock);
163 memcpy_fromio(buf, dev->mt76.mmio.regs +
164 __mt7996_reg_remap_addr(dev, offset), len);
165 spin_unlock_bh(&dev->reg_lock);
166 }
167
mt7996_rr(struct mt76_dev * mdev,u32 offset)168 static u32 mt7996_rr(struct mt76_dev *mdev, u32 offset)
169 {
170 struct mt7996_dev *dev = container_of(mdev, struct mt7996_dev, mt76);
171 u32 addr = __mt7996_reg_addr(dev, offset), val;
172
173 if (addr)
174 return dev->bus_ops->rr(mdev, addr);
175
176 spin_lock_bh(&dev->reg_lock);
177 val = dev->bus_ops->rr(mdev, __mt7996_reg_remap_addr(dev, offset));
178 spin_unlock_bh(&dev->reg_lock);
179
180 return val;
181 }
182
mt7996_wr(struct mt76_dev * mdev,u32 offset,u32 val)183 static void mt7996_wr(struct mt76_dev *mdev, u32 offset, u32 val)
184 {
185 struct mt7996_dev *dev = container_of(mdev, struct mt7996_dev, mt76);
186 u32 addr = __mt7996_reg_addr(dev, offset);
187
188 if (addr) {
189 dev->bus_ops->wr(mdev, addr, val);
190 return;
191 }
192
193 spin_lock_bh(&dev->reg_lock);
194 dev->bus_ops->wr(mdev, __mt7996_reg_remap_addr(dev, offset), val);
195 spin_unlock_bh(&dev->reg_lock);
196 }
197
mt7996_rmw(struct mt76_dev * mdev,u32 offset,u32 mask,u32 val)198 static u32 mt7996_rmw(struct mt76_dev *mdev, u32 offset, u32 mask, u32 val)
199 {
200 struct mt7996_dev *dev = container_of(mdev, struct mt7996_dev, mt76);
201 u32 addr = __mt7996_reg_addr(dev, offset);
202
203 if (addr)
204 return dev->bus_ops->rmw(mdev, addr, mask, val);
205
206 spin_lock_bh(&dev->reg_lock);
207 val = dev->bus_ops->rmw(mdev, __mt7996_reg_remap_addr(dev, offset), mask, val);
208 spin_unlock_bh(&dev->reg_lock);
209
210 return val;
211 }
212
mt7996_mmio_init(struct mt76_dev * mdev,void __iomem * mem_base,u32 device_id)213 static int mt7996_mmio_init(struct mt76_dev *mdev,
214 void __iomem *mem_base,
215 u32 device_id)
216 {
217 struct mt76_bus_ops *bus_ops;
218 struct mt7996_dev *dev;
219
220 dev = container_of(mdev, struct mt7996_dev, mt76);
221 mt76_mmio_init(&dev->mt76, mem_base);
222 spin_lock_init(&dev->reg_lock);
223
224 switch (device_id) {
225 case 0x7990:
226 dev->reg.base = mt7996_reg_base;
227 dev->reg.map = mt7996_reg_map;
228 dev->reg.map_size = ARRAY_SIZE(mt7996_reg_map);
229 break;
230 default:
231 return -EINVAL;
232 }
233
234 dev->bus_ops = dev->mt76.bus;
235 bus_ops = devm_kmemdup(dev->mt76.dev, dev->bus_ops, sizeof(*bus_ops),
236 GFP_KERNEL);
237 if (!bus_ops)
238 return -ENOMEM;
239
240 bus_ops->rr = mt7996_rr;
241 bus_ops->wr = mt7996_wr;
242 bus_ops->rmw = mt7996_rmw;
243 dev->mt76.bus = bus_ops;
244
245 mdev->rev = (device_id << 16) | (mt76_rr(dev, MT_HW_REV) & 0xff);
246
247 dev_dbg(mdev->dev, "ASIC revision: %04x\n", mdev->rev);
248
249 return 0;
250 }
251
mt7996_dual_hif_set_irq_mask(struct mt7996_dev * dev,bool write_reg,u32 clear,u32 set)252 void mt7996_dual_hif_set_irq_mask(struct mt7996_dev *dev, bool write_reg,
253 u32 clear, u32 set)
254 {
255 struct mt76_dev *mdev = &dev->mt76;
256 unsigned long flags;
257
258 spin_lock_irqsave(&mdev->mmio.irq_lock, flags);
259
260 mdev->mmio.irqmask &= ~clear;
261 mdev->mmio.irqmask |= set;
262
263 if (write_reg) {
264 mt76_wr(dev, MT_INT_MASK_CSR, mdev->mmio.irqmask);
265 mt76_wr(dev, MT_INT1_MASK_CSR, mdev->mmio.irqmask);
266 }
267
268 spin_unlock_irqrestore(&mdev->mmio.irq_lock, flags);
269 }
270
mt7996_rx_poll_complete(struct mt76_dev * mdev,enum mt76_rxq_id q)271 static void mt7996_rx_poll_complete(struct mt76_dev *mdev,
272 enum mt76_rxq_id q)
273 {
274 struct mt7996_dev *dev = container_of(mdev, struct mt7996_dev, mt76);
275
276 mt7996_irq_enable(dev, MT_INT_RX(q));
277 }
278
279 /* TODO: support 2/4/6/8 MSI-X vectors */
mt7996_irq_tasklet(struct tasklet_struct * t)280 static void mt7996_irq_tasklet(struct tasklet_struct *t)
281 {
282 struct mt7996_dev *dev = from_tasklet(dev, t, mt76.irq_tasklet);
283 u32 i, intr, mask, intr1;
284
285 mt76_wr(dev, MT_INT_MASK_CSR, 0);
286 if (dev->hif2)
287 mt76_wr(dev, MT_INT1_MASK_CSR, 0);
288
289 intr = mt76_rr(dev, MT_INT_SOURCE_CSR);
290 intr &= dev->mt76.mmio.irqmask;
291 mt76_wr(dev, MT_INT_SOURCE_CSR, intr);
292
293 if (dev->hif2) {
294 intr1 = mt76_rr(dev, MT_INT1_SOURCE_CSR);
295 intr1 &= dev->mt76.mmio.irqmask;
296 mt76_wr(dev, MT_INT1_SOURCE_CSR, intr1);
297
298 intr |= intr1;
299 }
300
301 trace_dev_irq(&dev->mt76, intr, dev->mt76.mmio.irqmask);
302
303 mask = intr & MT_INT_RX_DONE_ALL;
304 if (intr & MT_INT_TX_DONE_MCU)
305 mask |= MT_INT_TX_DONE_MCU;
306 mt7996_irq_disable(dev, mask);
307
308 if (intr & MT_INT_TX_DONE_MCU)
309 napi_schedule(&dev->mt76.tx_napi);
310
311 for (i = 0; i < __MT_RXQ_MAX; i++) {
312 if ((intr & MT_INT_RX(i)))
313 napi_schedule(&dev->mt76.napi[i]);
314 }
315
316 if (intr & MT_INT_MCU_CMD) {
317 u32 val = mt76_rr(dev, MT_MCU_CMD);
318
319 mt76_wr(dev, MT_MCU_CMD, val);
320 if (val & (MT_MCU_CMD_ERROR_MASK | MT_MCU_CMD_WDT_MASK)) {
321 dev->recovery.state = val;
322 mt7996_reset(dev);
323 }
324 }
325 }
326
mt7996_irq_handler(int irq,void * dev_instance)327 irqreturn_t mt7996_irq_handler(int irq, void *dev_instance)
328 {
329 struct mt7996_dev *dev = dev_instance;
330
331 mt76_wr(dev, MT_INT_MASK_CSR, 0);
332 if (dev->hif2)
333 mt76_wr(dev, MT_INT1_MASK_CSR, 0);
334
335 if (!test_bit(MT76_STATE_INITIALIZED, &dev->mphy.state))
336 return IRQ_NONE;
337
338 tasklet_schedule(&dev->mt76.irq_tasklet);
339
340 return IRQ_HANDLED;
341 }
342
mt7996_mmio_probe(struct device * pdev,void __iomem * mem_base,u32 device_id)343 struct mt7996_dev *mt7996_mmio_probe(struct device *pdev,
344 void __iomem *mem_base, u32 device_id)
345 {
346 static const struct mt76_driver_ops drv_ops = {
347 /* txwi_size = txd size + txp size */
348 .txwi_size = MT_TXD_SIZE + sizeof(struct mt76_connac_fw_txp),
349 .drv_flags = MT_DRV_TXWI_NO_FREE |
350 MT_DRV_AMSDU_OFFLOAD |
351 MT_DRV_HW_MGMT_TXQ,
352 .survey_flags = SURVEY_INFO_TIME_TX |
353 SURVEY_INFO_TIME_RX |
354 SURVEY_INFO_TIME_BSS_RX,
355 .token_size = MT7996_TOKEN_SIZE,
356 .tx_prepare_skb = mt7996_tx_prepare_skb,
357 .tx_complete_skb = mt76_connac_tx_complete_skb,
358 .rx_skb = mt7996_queue_rx_skb,
359 .rx_check = mt7996_rx_check,
360 .rx_poll_complete = mt7996_rx_poll_complete,
361 .sta_add = mt7996_mac_sta_add,
362 .sta_remove = mt7996_mac_sta_remove,
363 .update_survey = mt7996_update_channel,
364 };
365 struct mt7996_dev *dev;
366 struct mt76_dev *mdev;
367 int ret;
368
369 mdev = mt76_alloc_device(pdev, sizeof(*dev), &mt7996_ops, &drv_ops);
370 if (!mdev)
371 return ERR_PTR(-ENOMEM);
372
373 dev = container_of(mdev, struct mt7996_dev, mt76);
374
375 ret = mt7996_mmio_init(mdev, mem_base, device_id);
376 if (ret)
377 goto error;
378
379 tasklet_setup(&mdev->irq_tasklet, mt7996_irq_tasklet);
380
381 mt76_wr(dev, MT_INT_MASK_CSR, 0);
382
383 return dev;
384
385 error:
386 mt76_free_device(&dev->mt76);
387
388 return ERR_PTR(ret);
389 }
390
mt7996_init(void)391 static int __init mt7996_init(void)
392 {
393 int ret;
394
395 ret = pci_register_driver(&mt7996_hif_driver);
396 if (ret)
397 return ret;
398
399 ret = pci_register_driver(&mt7996_pci_driver);
400 if (ret)
401 pci_unregister_driver(&mt7996_hif_driver);
402
403 return ret;
404 }
405
mt7996_exit(void)406 static void __exit mt7996_exit(void)
407 {
408 pci_unregister_driver(&mt7996_pci_driver);
409 pci_unregister_driver(&mt7996_hif_driver);
410 }
411
412 module_init(mt7996_init);
413 module_exit(mt7996_exit);
414 MODULE_LICENSE("Dual BSD/GPL");
415