1 // SPDX-License-Identifier: ISC
2 /* Copyright (C) 2020 MediaTek Inc. */
3 
4 #include <linux/etherdevice.h>
5 #include <linux/hwmon.h>
6 #include <linux/hwmon-sysfs.h>
7 #include <linux/of.h>
8 #include <linux/thermal.h>
9 #include "mt7915.h"
10 #include "mac.h"
11 #include "mcu.h"
12 #include "coredump.h"
13 #include "eeprom.h"
14 
15 static const struct ieee80211_iface_limit if_limits[] = {
16 	{
17 		.max = 1,
18 		.types = BIT(NL80211_IFTYPE_ADHOC)
19 	}, {
20 		.max = 16,
21 		.types = BIT(NL80211_IFTYPE_AP)
22 #ifdef CONFIG_MAC80211_MESH
23 			 | BIT(NL80211_IFTYPE_MESH_POINT)
24 #endif
25 	}, {
26 		.max = MT7915_MAX_INTERFACES,
27 		.types = BIT(NL80211_IFTYPE_STATION)
28 	}
29 };
30 
31 static const struct ieee80211_iface_combination if_comb[] = {
32 	{
33 		.limits = if_limits,
34 		.n_limits = ARRAY_SIZE(if_limits),
35 		.max_interfaces = MT7915_MAX_INTERFACES,
36 		.num_different_channels = 1,
37 		.beacon_int_infra_match = true,
38 		.radar_detect_widths = BIT(NL80211_CHAN_WIDTH_20_NOHT) |
39 				       BIT(NL80211_CHAN_WIDTH_20) |
40 				       BIT(NL80211_CHAN_WIDTH_40) |
41 				       BIT(NL80211_CHAN_WIDTH_80) |
42 				       BIT(NL80211_CHAN_WIDTH_160),
43 	}
44 };
45 
mt7915_thermal_temp_show(struct device * dev,struct device_attribute * attr,char * buf)46 static ssize_t mt7915_thermal_temp_show(struct device *dev,
47 					struct device_attribute *attr,
48 					char *buf)
49 {
50 	struct mt7915_phy *phy = dev_get_drvdata(dev);
51 	int i = to_sensor_dev_attr(attr)->index;
52 	int temperature;
53 
54 	switch (i) {
55 	case 0:
56 		temperature = mt7915_mcu_get_temperature(phy);
57 		if (temperature < 0)
58 			return temperature;
59 		/* display in millidegree celcius */
60 		return sprintf(buf, "%u\n", temperature * 1000);
61 	case 1:
62 	case 2:
63 		return sprintf(buf, "%u\n",
64 			       phy->throttle_temp[i - 1] * 1000);
65 	case 3:
66 		return sprintf(buf, "%hhu\n", phy->throttle_state);
67 	default:
68 		return -EINVAL;
69 	}
70 }
71 
mt7915_thermal_temp_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)72 static ssize_t mt7915_thermal_temp_store(struct device *dev,
73 					 struct device_attribute *attr,
74 					 const char *buf, size_t count)
75 {
76 	struct mt7915_phy *phy = dev_get_drvdata(dev);
77 	int ret, i = to_sensor_dev_attr(attr)->index;
78 	long val;
79 
80 	ret = kstrtol(buf, 10, &val);
81 	if (ret < 0)
82 		return ret;
83 
84 	mutex_lock(&phy->dev->mt76.mutex);
85 	val = clamp_val(DIV_ROUND_CLOSEST(val, 1000), 60, 130);
86 
87 	if ((i - 1 == MT7915_CRIT_TEMP_IDX &&
88 	     val > phy->throttle_temp[MT7915_MAX_TEMP_IDX]) ||
89 	    (i - 1 == MT7915_MAX_TEMP_IDX &&
90 	     val < phy->throttle_temp[MT7915_CRIT_TEMP_IDX])) {
91 		dev_err(phy->dev->mt76.dev,
92 			"temp1_max shall be greater than temp1_crit.");
93 		mutex_unlock(&phy->dev->mt76.mutex);
94 		return -EINVAL;
95 	}
96 
97 	phy->throttle_temp[i - 1] = val;
98 	mutex_unlock(&phy->dev->mt76.mutex);
99 
100 	ret = mt7915_mcu_set_thermal_protect(phy);
101 	if (ret)
102 		return ret;
103 
104 	return count;
105 }
106 
107 static SENSOR_DEVICE_ATTR_RO(temp1_input, mt7915_thermal_temp, 0);
108 static SENSOR_DEVICE_ATTR_RW(temp1_crit, mt7915_thermal_temp, 1);
109 static SENSOR_DEVICE_ATTR_RW(temp1_max, mt7915_thermal_temp, 2);
110 static SENSOR_DEVICE_ATTR_RO(throttle1, mt7915_thermal_temp, 3);
111 
112 static struct attribute *mt7915_hwmon_attrs[] = {
113 	&sensor_dev_attr_temp1_input.dev_attr.attr,
114 	&sensor_dev_attr_temp1_crit.dev_attr.attr,
115 	&sensor_dev_attr_temp1_max.dev_attr.attr,
116 	&sensor_dev_attr_throttle1.dev_attr.attr,
117 	NULL,
118 };
119 ATTRIBUTE_GROUPS(mt7915_hwmon);
120 
121 static int
mt7915_thermal_get_max_throttle_state(struct thermal_cooling_device * cdev,unsigned long * state)122 mt7915_thermal_get_max_throttle_state(struct thermal_cooling_device *cdev,
123 				      unsigned long *state)
124 {
125 	*state = MT7915_CDEV_THROTTLE_MAX;
126 
127 	return 0;
128 }
129 
130 static int
mt7915_thermal_get_cur_throttle_state(struct thermal_cooling_device * cdev,unsigned long * state)131 mt7915_thermal_get_cur_throttle_state(struct thermal_cooling_device *cdev,
132 				      unsigned long *state)
133 {
134 	struct mt7915_phy *phy = cdev->devdata;
135 
136 	*state = phy->cdev_state;
137 
138 	return 0;
139 }
140 
141 static int
mt7915_thermal_set_cur_throttle_state(struct thermal_cooling_device * cdev,unsigned long state)142 mt7915_thermal_set_cur_throttle_state(struct thermal_cooling_device *cdev,
143 				      unsigned long state)
144 {
145 	struct mt7915_phy *phy = cdev->devdata;
146 	u8 throttling = MT7915_THERMAL_THROTTLE_MAX - state;
147 	int ret;
148 
149 	if (state > MT7915_CDEV_THROTTLE_MAX) {
150 		dev_err(phy->dev->mt76.dev,
151 			"please specify a valid throttling state\n");
152 		return -EINVAL;
153 	}
154 
155 	if (state == phy->cdev_state)
156 		return 0;
157 
158 	/*
159 	 * cooling_device convention: 0 = no cooling, more = more cooling
160 	 * mcu convention: 1 = max cooling, more = less cooling
161 	 */
162 	ret = mt7915_mcu_set_thermal_throttling(phy, throttling);
163 	if (ret)
164 		return ret;
165 
166 	phy->cdev_state = state;
167 
168 	return 0;
169 }
170 
171 static const struct thermal_cooling_device_ops mt7915_thermal_ops = {
172 	.get_max_state = mt7915_thermal_get_max_throttle_state,
173 	.get_cur_state = mt7915_thermal_get_cur_throttle_state,
174 	.set_cur_state = mt7915_thermal_set_cur_throttle_state,
175 };
176 
mt7915_unregister_thermal(struct mt7915_phy * phy)177 static void mt7915_unregister_thermal(struct mt7915_phy *phy)
178 {
179 	struct wiphy *wiphy = phy->mt76->hw->wiphy;
180 
181 	if (!phy->cdev)
182 		return;
183 
184 	sysfs_remove_link(&wiphy->dev.kobj, "cooling_device");
185 	thermal_cooling_device_unregister(phy->cdev);
186 }
187 
mt7915_thermal_init(struct mt7915_phy * phy)188 static int mt7915_thermal_init(struct mt7915_phy *phy)
189 {
190 	struct wiphy *wiphy = phy->mt76->hw->wiphy;
191 	struct thermal_cooling_device *cdev;
192 	struct device *hwmon;
193 	const char *name;
194 
195 	name = devm_kasprintf(&wiphy->dev, GFP_KERNEL, "mt7915_%s",
196 			      wiphy_name(wiphy));
197 
198 	cdev = thermal_cooling_device_register(name, phy, &mt7915_thermal_ops);
199 	if (!IS_ERR(cdev)) {
200 		if (sysfs_create_link(&wiphy->dev.kobj, &cdev->device.kobj,
201 				      "cooling_device") < 0)
202 			thermal_cooling_device_unregister(cdev);
203 		else
204 			phy->cdev = cdev;
205 	}
206 
207 	/* initialize critical/maximum high temperature */
208 	phy->throttle_temp[MT7915_CRIT_TEMP_IDX] = MT7915_CRIT_TEMP;
209 	phy->throttle_temp[MT7915_MAX_TEMP_IDX] = MT7915_MAX_TEMP;
210 
211 	if (!IS_REACHABLE(CONFIG_HWMON))
212 		return 0;
213 
214 	hwmon = devm_hwmon_device_register_with_groups(&wiphy->dev, name, phy,
215 						       mt7915_hwmon_groups);
216 	if (IS_ERR(hwmon))
217 		return PTR_ERR(hwmon);
218 
219 	return 0;
220 }
221 
mt7915_led_set_config(struct led_classdev * led_cdev,u8 delay_on,u8 delay_off)222 static void mt7915_led_set_config(struct led_classdev *led_cdev,
223 				  u8 delay_on, u8 delay_off)
224 {
225 	struct mt7915_dev *dev;
226 	struct mt76_phy *mphy;
227 	u32 val;
228 
229 	mphy = container_of(led_cdev, struct mt76_phy, leds.cdev);
230 	dev = container_of(mphy->dev, struct mt7915_dev, mt76);
231 
232 	/* set PWM mode */
233 	val = FIELD_PREP(MT_LED_STATUS_DURATION, 0xffff) |
234 	      FIELD_PREP(MT_LED_STATUS_OFF, delay_off) |
235 	      FIELD_PREP(MT_LED_STATUS_ON, delay_on);
236 	mt76_wr(dev, MT_LED_STATUS_0(mphy->band_idx), val);
237 	mt76_wr(dev, MT_LED_STATUS_1(mphy->band_idx), val);
238 
239 	/* enable LED */
240 	mt76_wr(dev, MT_LED_EN(mphy->band_idx), 1);
241 
242 	/* control LED */
243 	val = MT_LED_CTRL_KICK;
244 	if (dev->mphy.leds.al)
245 		val |= MT_LED_CTRL_POLARITY;
246 	if (mphy->band_idx)
247 		val |= MT_LED_CTRL_BAND;
248 
249 	mt76_wr(dev, MT_LED_CTRL(mphy->band_idx), val);
250 	mt76_clear(dev, MT_LED_CTRL(mphy->band_idx), MT_LED_CTRL_KICK);
251 }
252 
mt7915_led_set_blink(struct led_classdev * led_cdev,unsigned long * delay_on,unsigned long * delay_off)253 static int mt7915_led_set_blink(struct led_classdev *led_cdev,
254 				unsigned long *delay_on,
255 				unsigned long *delay_off)
256 {
257 	u16 delta_on = 0, delta_off = 0;
258 
259 #define HW_TICK		10
260 #define TO_HW_TICK(_t)	(((_t) > HW_TICK) ? ((_t) / HW_TICK) : HW_TICK)
261 
262 	if (*delay_on)
263 		delta_on = TO_HW_TICK(*delay_on);
264 	if (*delay_off)
265 		delta_off = TO_HW_TICK(*delay_off);
266 
267 	mt7915_led_set_config(led_cdev, delta_on, delta_off);
268 
269 	return 0;
270 }
271 
mt7915_led_set_brightness(struct led_classdev * led_cdev,enum led_brightness brightness)272 static void mt7915_led_set_brightness(struct led_classdev *led_cdev,
273 				      enum led_brightness brightness)
274 {
275 	if (!brightness)
276 		mt7915_led_set_config(led_cdev, 0, 0xff);
277 	else
278 		mt7915_led_set_config(led_cdev, 0xff, 0);
279 }
280 
mt7915_init_txpower(struct mt7915_dev * dev,struct ieee80211_supported_band * sband)281 void mt7915_init_txpower(struct mt7915_dev *dev,
282 			 struct ieee80211_supported_band *sband)
283 {
284 	int i, n_chains = hweight8(dev->mphy.antenna_mask);
285 	int nss_delta = mt76_tx_power_nss_delta(n_chains);
286 	int pwr_delta = mt7915_eeprom_get_power_delta(dev, sband->band);
287 	struct mt76_power_limits limits;
288 
289 	for (i = 0; i < sband->n_channels; i++) {
290 		struct ieee80211_channel *chan = &sband->channels[i];
291 		u32 target_power = 0;
292 		int j;
293 
294 		for (j = 0; j < n_chains; j++) {
295 			u32 val;
296 
297 			val = mt7915_eeprom_get_target_power(dev, chan, j);
298 			target_power = max(target_power, val);
299 		}
300 
301 		target_power += pwr_delta;
302 		target_power = mt76_get_rate_power_limits(&dev->mphy, chan,
303 							  &limits,
304 							  target_power);
305 		target_power += nss_delta;
306 		target_power = DIV_ROUND_UP(target_power, 2);
307 		chan->max_power = min_t(int, chan->max_reg_power,
308 					target_power);
309 		chan->orig_mpwr = target_power;
310 	}
311 }
312 
313 static void
mt7915_regd_notifier(struct wiphy * wiphy,struct regulatory_request * request)314 mt7915_regd_notifier(struct wiphy *wiphy,
315 		     struct regulatory_request *request)
316 {
317 	struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
318 	struct mt7915_dev *dev = mt7915_hw_dev(hw);
319 	struct mt76_phy *mphy = hw->priv;
320 	struct mt7915_phy *phy = mphy->priv;
321 
322 	memcpy(dev->mt76.alpha2, request->alpha2, sizeof(dev->mt76.alpha2));
323 	dev->mt76.region = request->dfs_region;
324 
325 	if (dev->mt76.region == NL80211_DFS_UNSET)
326 		mt7915_mcu_rdd_background_enable(phy, NULL);
327 
328 	mt7915_init_txpower(dev, &mphy->sband_2g.sband);
329 	mt7915_init_txpower(dev, &mphy->sband_5g.sband);
330 	mt7915_init_txpower(dev, &mphy->sband_6g.sband);
331 
332 	mphy->dfs_state = MT_DFS_STATE_UNKNOWN;
333 	mt7915_dfs_init_radar_detector(phy);
334 }
335 
336 static void
mt7915_init_wiphy(struct mt7915_phy * phy)337 mt7915_init_wiphy(struct mt7915_phy *phy)
338 {
339 	struct mt76_phy *mphy = phy->mt76;
340 	struct ieee80211_hw *hw = mphy->hw;
341 	struct mt76_dev *mdev = &phy->dev->mt76;
342 	struct wiphy *wiphy = hw->wiphy;
343 	struct mt7915_dev *dev = phy->dev;
344 
345 	hw->queues = 4;
346 	hw->max_rx_aggregation_subframes = IEEE80211_MAX_AMPDU_BUF_HE;
347 	hw->max_tx_aggregation_subframes = IEEE80211_MAX_AMPDU_BUF_HE;
348 	hw->netdev_features = NETIF_F_RXCSUM;
349 
350 	hw->radiotap_timestamp.units_pos =
351 		IEEE80211_RADIOTAP_TIMESTAMP_UNIT_US;
352 
353 	phy->slottime = 9;
354 
355 	hw->sta_data_size = sizeof(struct mt7915_sta);
356 	hw->vif_data_size = sizeof(struct mt7915_vif);
357 
358 	wiphy->iface_combinations = if_comb;
359 	wiphy->n_iface_combinations = ARRAY_SIZE(if_comb);
360 	wiphy->reg_notifier = mt7915_regd_notifier;
361 	wiphy->flags |= WIPHY_FLAG_HAS_CHANNEL_SWITCH;
362 	wiphy->mbssid_max_interfaces = 16;
363 
364 	wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BSS_COLOR);
365 	wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_VHT_IBSS);
366 	wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_LEGACY);
367 	wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_HT);
368 	wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_VHT);
369 	wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_HE);
370 	wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_UNSOL_BCAST_PROBE_RESP);
371 	wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_FILS_DISCOVERY);
372 	wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_ACK_SIGNAL_SUPPORT);
373 	wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_CAN_REPLACE_PTK0);
374 
375 	if (!is_mt7915(&dev->mt76))
376 		wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_STA_TX_PWR);
377 
378 	if (!mdev->dev->of_node ||
379 	    !of_property_read_bool(mdev->dev->of_node,
380 				   "mediatek,disable-radar-background"))
381 		wiphy_ext_feature_set(wiphy,
382 				      NL80211_EXT_FEATURE_RADAR_BACKGROUND);
383 
384 	ieee80211_hw_set(hw, HAS_RATE_CONTROL);
385 	ieee80211_hw_set(hw, SUPPORTS_TX_ENCAP_OFFLOAD);
386 	ieee80211_hw_set(hw, SUPPORTS_RX_DECAP_OFFLOAD);
387 	ieee80211_hw_set(hw, SUPPORTS_MULTI_BSSID);
388 	ieee80211_hw_set(hw, WANT_MONITOR_VIF);
389 
390 	hw->max_tx_fragments = 4;
391 
392 	if (phy->mt76->cap.has_2ghz) {
393 		phy->mt76->sband_2g.sband.ht_cap.cap |=
394 			IEEE80211_HT_CAP_LDPC_CODING |
395 			IEEE80211_HT_CAP_MAX_AMSDU;
396 		phy->mt76->sband_2g.sband.ht_cap.ampdu_density =
397 			IEEE80211_HT_MPDU_DENSITY_4;
398 	}
399 
400 	if (phy->mt76->cap.has_5ghz) {
401 		struct ieee80211_sta_vht_cap *vht_cap;
402 
403 		vht_cap = &phy->mt76->sband_5g.sband.vht_cap;
404 		phy->mt76->sband_5g.sband.ht_cap.cap |=
405 			IEEE80211_HT_CAP_LDPC_CODING |
406 			IEEE80211_HT_CAP_MAX_AMSDU;
407 		phy->mt76->sband_5g.sband.ht_cap.ampdu_density =
408 			IEEE80211_HT_MPDU_DENSITY_4;
409 
410 		if (is_mt7915(&dev->mt76)) {
411 			vht_cap->cap |=
412 				IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_7991 |
413 				IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK;
414 
415 			if (!dev->dbdc_support)
416 				vht_cap->cap |=
417 					IEEE80211_VHT_CAP_SHORT_GI_160 |
418 					FIELD_PREP(IEEE80211_VHT_CAP_EXT_NSS_BW_MASK, 1);
419 		} else {
420 			vht_cap->cap |=
421 				IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454 |
422 				IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK;
423 
424 			/* mt7916 dbdc with 2g 2x2 bw40 and 5g 2x2 bw160c */
425 			vht_cap->cap |=
426 				IEEE80211_VHT_CAP_SHORT_GI_160 |
427 				IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ;
428 		}
429 
430 		if (!is_mt7915(&dev->mt76) || !dev->dbdc_support)
431 			ieee80211_hw_set(hw, SUPPORTS_VHT_EXT_NSS_BW);
432 	}
433 
434 	mt76_set_stream_caps(phy->mt76, true);
435 	mt7915_set_stream_vht_txbf_caps(phy);
436 	mt7915_set_stream_he_caps(phy);
437 
438 	wiphy->available_antennas_rx = phy->mt76->antenna_mask;
439 	wiphy->available_antennas_tx = phy->mt76->antenna_mask;
440 
441 	/* init led callbacks */
442 	if (IS_ENABLED(CONFIG_MT76_LEDS)) {
443 		mphy->leds.cdev.brightness_set = mt7915_led_set_brightness;
444 		mphy->leds.cdev.blink_set = mt7915_led_set_blink;
445 	}
446 }
447 
448 static void
mt7915_mac_init_band(struct mt7915_dev * dev,u8 band)449 mt7915_mac_init_band(struct mt7915_dev *dev, u8 band)
450 {
451 	u32 mask, set;
452 
453 	mt76_rmw_field(dev, MT_TMAC_CTCR0(band),
454 		       MT_TMAC_CTCR0_INS_DDLMT_REFTIME, 0x3f);
455 	mt76_set(dev, MT_TMAC_CTCR0(band),
456 		 MT_TMAC_CTCR0_INS_DDLMT_VHT_SMPDU_EN |
457 		 MT_TMAC_CTCR0_INS_DDLMT_EN);
458 
459 	mask = MT_MDP_RCFR0_MCU_RX_MGMT |
460 	       MT_MDP_RCFR0_MCU_RX_CTL_NON_BAR |
461 	       MT_MDP_RCFR0_MCU_RX_CTL_BAR;
462 	set = FIELD_PREP(MT_MDP_RCFR0_MCU_RX_MGMT, MT_MDP_TO_HIF) |
463 	      FIELD_PREP(MT_MDP_RCFR0_MCU_RX_CTL_NON_BAR, MT_MDP_TO_HIF) |
464 	      FIELD_PREP(MT_MDP_RCFR0_MCU_RX_CTL_BAR, MT_MDP_TO_HIF);
465 	mt76_rmw(dev, MT_MDP_BNRCFR0(band), mask, set);
466 
467 	mask = MT_MDP_RCFR1_MCU_RX_BYPASS |
468 	       MT_MDP_RCFR1_RX_DROPPED_UCAST |
469 	       MT_MDP_RCFR1_RX_DROPPED_MCAST;
470 	set = FIELD_PREP(MT_MDP_RCFR1_MCU_RX_BYPASS, MT_MDP_TO_HIF) |
471 	      FIELD_PREP(MT_MDP_RCFR1_RX_DROPPED_UCAST, MT_MDP_TO_HIF) |
472 	      FIELD_PREP(MT_MDP_RCFR1_RX_DROPPED_MCAST, MT_MDP_TO_HIF);
473 	mt76_rmw(dev, MT_MDP_BNRCFR1(band), mask, set);
474 
475 	mt76_rmw_field(dev, MT_DMA_DCR0(band), MT_DMA_DCR0_MAX_RX_LEN, 0x680);
476 
477 	/* mt7915: disable rx rate report by default due to hw issues */
478 	mt76_clear(dev, MT_DMA_DCR0(band), MT_DMA_DCR0_RXD_G5_EN);
479 
480 	/* clear estimated value of EIFS for Rx duration & OBSS time */
481 	mt76_wr(dev, MT_WF_RMAC_RSVD0(band), MT_WF_RMAC_RSVD0_EIFS_CLR);
482 
483 	/* clear backoff time for Rx duration  */
484 	mt76_clear(dev, MT_WF_RMAC_MIB_AIRTIME1(band),
485 		   MT_WF_RMAC_MIB_NONQOSD_BACKOFF);
486 	mt76_clear(dev, MT_WF_RMAC_MIB_AIRTIME3(band),
487 		   MT_WF_RMAC_MIB_QOS01_BACKOFF);
488 	mt76_clear(dev, MT_WF_RMAC_MIB_AIRTIME4(band),
489 		   MT_WF_RMAC_MIB_QOS23_BACKOFF);
490 
491 	/* clear backoff time and set software compensation for OBSS time */
492 	mask = MT_WF_RMAC_MIB_OBSS_BACKOFF | MT_WF_RMAC_MIB_ED_OFFSET;
493 	set = FIELD_PREP(MT_WF_RMAC_MIB_OBSS_BACKOFF, 0) |
494 	      FIELD_PREP(MT_WF_RMAC_MIB_ED_OFFSET, 4);
495 	mt76_rmw(dev, MT_WF_RMAC_MIB_AIRTIME0(band), mask, set);
496 
497 	/* filter out non-resp frames and get instanstaeous signal reporting */
498 	mask = MT_WTBLOFF_TOP_RSCR_RCPI_MODE | MT_WTBLOFF_TOP_RSCR_RCPI_PARAM;
499 	set = FIELD_PREP(MT_WTBLOFF_TOP_RSCR_RCPI_MODE, 0) |
500 	      FIELD_PREP(MT_WTBLOFF_TOP_RSCR_RCPI_PARAM, 0x3);
501 	mt76_rmw(dev, MT_WTBLOFF_TOP_RSCR(band), mask, set);
502 
503 	/* MT_TXD5_TX_STATUS_HOST (MPDU format) has higher priority than
504 	 * MT_AGG_ACR_PPDU_TXS2H (PPDU format) even though ACR bit is set.
505 	 */
506 	if (mtk_wed_device_active(&dev->mt76.mmio.wed))
507 		mt76_set(dev, MT_AGG_ACR4(band), MT_AGG_ACR_PPDU_TXS2H);
508 }
509 
510 static void
mt7915_init_led_mux(struct mt7915_dev * dev)511 mt7915_init_led_mux(struct mt7915_dev *dev)
512 {
513 	if (!IS_ENABLED(CONFIG_MT76_LEDS))
514 		return;
515 
516 	if (dev->dbdc_support) {
517 		switch (mt76_chip(&dev->mt76)) {
518 		case 0x7915:
519 			mt76_rmw_field(dev, MT_LED_GPIO_MUX2,
520 				       GENMASK(11, 8), 4);
521 			mt76_rmw_field(dev, MT_LED_GPIO_MUX3,
522 				       GENMASK(11, 8), 4);
523 			break;
524 		case 0x7986:
525 			mt76_rmw_field(dev, MT_LED_GPIO_MUX0,
526 				       GENMASK(7, 4), 1);
527 			mt76_rmw_field(dev, MT_LED_GPIO_MUX0,
528 				       GENMASK(11, 8), 1);
529 			break;
530 		case 0x7916:
531 			mt76_rmw_field(dev, MT_LED_GPIO_MUX1,
532 				       GENMASK(27, 24), 3);
533 			mt76_rmw_field(dev, MT_LED_GPIO_MUX1,
534 				       GENMASK(31, 28), 3);
535 			break;
536 		default:
537 			break;
538 		}
539 	} else if (dev->mphy.leds.pin) {
540 		switch (mt76_chip(&dev->mt76)) {
541 		case 0x7915:
542 			mt76_rmw_field(dev, MT_LED_GPIO_MUX3,
543 				       GENMASK(11, 8), 4);
544 			break;
545 		case 0x7986:
546 			mt76_rmw_field(dev, MT_LED_GPIO_MUX0,
547 				       GENMASK(11, 8), 1);
548 			break;
549 		case 0x7916:
550 			mt76_rmw_field(dev, MT_LED_GPIO_MUX1,
551 				       GENMASK(31, 28), 3);
552 			break;
553 		default:
554 			break;
555 		}
556 	} else {
557 		switch (mt76_chip(&dev->mt76)) {
558 		case 0x7915:
559 			mt76_rmw_field(dev, MT_LED_GPIO_MUX2,
560 				       GENMASK(11, 8), 4);
561 			break;
562 		case 0x7986:
563 			mt76_rmw_field(dev, MT_LED_GPIO_MUX0,
564 				       GENMASK(7, 4), 1);
565 			break;
566 		case 0x7916:
567 			mt76_rmw_field(dev, MT_LED_GPIO_MUX1,
568 				       GENMASK(27, 24), 3);
569 			break;
570 		default:
571 			break;
572 		}
573 	}
574 }
575 
mt7915_mac_init(struct mt7915_dev * dev)576 void mt7915_mac_init(struct mt7915_dev *dev)
577 {
578 	int i;
579 	u32 rx_len = is_mt7915(&dev->mt76) ? 0x400 : 0x680;
580 
581 	/* config pse qid6 wfdma port selection */
582 	if (!is_mt7915(&dev->mt76) && dev->hif2)
583 		mt76_rmw(dev, MT_WF_PP_TOP_RXQ_WFDMA_CF_5, 0,
584 			 MT_WF_PP_TOP_RXQ_QID6_WFDMA_HIF_SEL_MASK);
585 
586 	mt76_rmw_field(dev, MT_MDP_DCR1, MT_MDP_DCR1_MAX_RX_LEN, rx_len);
587 
588 	if (!is_mt7915(&dev->mt76))
589 		mt76_clear(dev, MT_MDP_DCR2, MT_MDP_DCR2_RX_TRANS_SHORT);
590 	else
591 		mt76_clear(dev, MT_PLE_HOST_RPT0, MT_PLE_HOST_RPT0_TX_LATENCY);
592 
593 	/* enable hardware de-agg */
594 	mt76_set(dev, MT_MDP_DCR0, MT_MDP_DCR0_DAMSDU_EN);
595 
596 	for (i = 0; i < mt7915_wtbl_size(dev); i++)
597 		mt7915_mac_wtbl_update(dev, i,
598 				       MT_WTBL_UPDATE_ADM_COUNT_CLEAR);
599 	for (i = 0; i < 2; i++)
600 		mt7915_mac_init_band(dev, i);
601 
602 	mt7915_init_led_mux(dev);
603 }
604 
mt7915_txbf_init(struct mt7915_dev * dev)605 int mt7915_txbf_init(struct mt7915_dev *dev)
606 {
607 	int ret;
608 
609 	if (dev->dbdc_support) {
610 		ret = mt7915_mcu_set_txbf(dev, MT_BF_MODULE_UPDATE);
611 		if (ret)
612 			return ret;
613 	}
614 
615 	/* trigger sounding packets */
616 	ret = mt7915_mcu_set_txbf(dev, MT_BF_SOUNDING_ON);
617 	if (ret)
618 		return ret;
619 
620 	/* enable eBF */
621 	return mt7915_mcu_set_txbf(dev, MT_BF_TYPE_UPDATE);
622 }
623 
624 static struct mt7915_phy *
mt7915_alloc_ext_phy(struct mt7915_dev * dev)625 mt7915_alloc_ext_phy(struct mt7915_dev *dev)
626 {
627 	struct mt7915_phy *phy;
628 	struct mt76_phy *mphy;
629 
630 	if (!dev->dbdc_support)
631 		return NULL;
632 
633 	mphy = mt76_alloc_phy(&dev->mt76, sizeof(*phy), &mt7915_ops, MT_BAND1);
634 	if (!mphy)
635 		return ERR_PTR(-ENOMEM);
636 
637 	phy = mphy->priv;
638 	phy->dev = dev;
639 	phy->mt76 = mphy;
640 
641 	/* Bind main phy to band0 and ext_phy to band1 for dbdc case */
642 	phy->mt76->band_idx = 1;
643 
644 	return phy;
645 }
646 
647 static int
mt7915_register_ext_phy(struct mt7915_dev * dev,struct mt7915_phy * phy)648 mt7915_register_ext_phy(struct mt7915_dev *dev, struct mt7915_phy *phy)
649 {
650 	struct mt76_phy *mphy = phy->mt76;
651 	int ret;
652 
653 	INIT_DELAYED_WORK(&mphy->mac_work, mt7915_mac_work);
654 
655 	mt7915_eeprom_parse_hw_cap(dev, phy);
656 
657 	memcpy(mphy->macaddr, dev->mt76.eeprom.data + MT_EE_MAC_ADDR2,
658 	       ETH_ALEN);
659 	/* Make the secondary PHY MAC address local without overlapping with
660 	 * the usual MAC address allocation scheme on multiple virtual interfaces
661 	 */
662 	if (!is_valid_ether_addr(mphy->macaddr)) {
663 		memcpy(mphy->macaddr, dev->mt76.eeprom.data + MT_EE_MAC_ADDR,
664 		       ETH_ALEN);
665 		mphy->macaddr[0] |= 2;
666 		mphy->macaddr[0] ^= BIT(7);
667 	}
668 	mt76_eeprom_override(mphy);
669 
670 	/* init wiphy according to mphy and phy */
671 	mt7915_init_wiphy(phy);
672 
673 	ret = mt76_register_phy(mphy, true, mt76_rates,
674 				ARRAY_SIZE(mt76_rates));
675 	if (ret)
676 		return ret;
677 
678 	ret = mt7915_thermal_init(phy);
679 	if (ret)
680 		goto unreg;
681 
682 	mt7915_init_debugfs(phy);
683 
684 	return 0;
685 
686 unreg:
687 	mt76_unregister_phy(mphy);
688 	return ret;
689 }
690 
mt7915_init_work(struct work_struct * work)691 static void mt7915_init_work(struct work_struct *work)
692 {
693 	struct mt7915_dev *dev = container_of(work, struct mt7915_dev,
694 				 init_work);
695 
696 	mt7915_mcu_set_eeprom(dev);
697 	mt7915_mac_init(dev);
698 	mt7915_init_txpower(dev, &dev->mphy.sband_2g.sband);
699 	mt7915_init_txpower(dev, &dev->mphy.sband_5g.sband);
700 	mt7915_init_txpower(dev, &dev->mphy.sband_6g.sband);
701 	mt7915_txbf_init(dev);
702 }
703 
mt7915_wfsys_reset(struct mt7915_dev * dev)704 void mt7915_wfsys_reset(struct mt7915_dev *dev)
705 {
706 #define MT_MCU_DUMMY_RANDOM	GENMASK(15, 0)
707 #define MT_MCU_DUMMY_DEFAULT	GENMASK(31, 16)
708 
709 	if (is_mt7915(&dev->mt76)) {
710 		u32 val = MT_TOP_PWR_KEY | MT_TOP_PWR_SW_PWR_ON | MT_TOP_PWR_PWR_ON;
711 
712 		mt76_wr(dev, MT_MCU_WFDMA0_DUMMY_CR, MT_MCU_DUMMY_RANDOM);
713 
714 		/* change to software control */
715 		val |= MT_TOP_PWR_SW_RST;
716 		mt76_wr(dev, MT_TOP_PWR_CTRL, val);
717 
718 		/* reset wfsys */
719 		val &= ~MT_TOP_PWR_SW_RST;
720 		mt76_wr(dev, MT_TOP_PWR_CTRL, val);
721 
722 		/* release wfsys then mcu re-executes romcode */
723 		val |= MT_TOP_PWR_SW_RST;
724 		mt76_wr(dev, MT_TOP_PWR_CTRL, val);
725 
726 		/* switch to hw control */
727 		val &= ~MT_TOP_PWR_SW_RST;
728 		val |= MT_TOP_PWR_HW_CTRL;
729 		mt76_wr(dev, MT_TOP_PWR_CTRL, val);
730 
731 		/* check whether mcu resets to default */
732 		if (!mt76_poll_msec(dev, MT_MCU_WFDMA0_DUMMY_CR,
733 				    MT_MCU_DUMMY_DEFAULT, MT_MCU_DUMMY_DEFAULT,
734 				    1000)) {
735 			dev_err(dev->mt76.dev, "wifi subsystem reset failure\n");
736 			return;
737 		}
738 
739 		/* wfsys reset won't clear host registers */
740 		mt76_clear(dev, MT_TOP_MISC, MT_TOP_MISC_FW_STATE);
741 
742 		msleep(100);
743 	} else if (is_mt798x(&dev->mt76)) {
744 		mt7986_wmac_disable(dev);
745 		msleep(20);
746 
747 		mt7986_wmac_enable(dev);
748 		msleep(20);
749 	} else {
750 		mt76_set(dev, MT_WF_SUBSYS_RST, 0x1);
751 		msleep(20);
752 
753 		mt76_clear(dev, MT_WF_SUBSYS_RST, 0x1);
754 		msleep(20);
755 	}
756 }
757 
mt7915_band_config(struct mt7915_dev * dev)758 static bool mt7915_band_config(struct mt7915_dev *dev)
759 {
760 	bool ret = true;
761 
762 	dev->phy.mt76->band_idx = 0;
763 
764 	if (is_mt798x(&dev->mt76)) {
765 		u32 sku = mt7915_check_adie(dev, true);
766 
767 		/*
768 		 * for mt7986, dbdc support is determined by the number
769 		 * of adie chips and the main phy is bound to band1 when
770 		 * dbdc is disabled.
771 		 */
772 		if (sku == MT7975_ONE_ADIE || sku == MT7976_ONE_ADIE) {
773 			dev->phy.mt76->band_idx = 1;
774 			ret = false;
775 		}
776 	} else {
777 		ret = is_mt7915(&dev->mt76) ?
778 		      !!(mt76_rr(dev, MT_HW_BOUND) & BIT(5)) : true;
779 	}
780 
781 	return ret;
782 }
783 
784 static int
mt7915_init_hardware(struct mt7915_dev * dev,struct mt7915_phy * phy2)785 mt7915_init_hardware(struct mt7915_dev *dev, struct mt7915_phy *phy2)
786 {
787 	int ret, idx;
788 
789 	mt76_wr(dev, MT_INT_MASK_CSR, 0);
790 	mt76_wr(dev, MT_INT_SOURCE_CSR, ~0);
791 
792 	INIT_WORK(&dev->init_work, mt7915_init_work);
793 
794 	ret = mt7915_dma_init(dev, phy2);
795 	if (ret)
796 		return ret;
797 
798 	set_bit(MT76_STATE_INITIALIZED, &dev->mphy.state);
799 
800 	ret = mt7915_mcu_init(dev);
801 	if (ret)
802 		return ret;
803 
804 	ret = mt7915_eeprom_init(dev);
805 	if (ret < 0)
806 		return ret;
807 
808 	if (dev->flash_mode) {
809 		ret = mt7915_mcu_apply_group_cal(dev);
810 		if (ret)
811 			return ret;
812 	}
813 
814 	/* Beacon and mgmt frames should occupy wcid 0 */
815 	idx = mt76_wcid_alloc(dev->mt76.wcid_mask, MT7915_WTBL_STA);
816 	if (idx)
817 		return -ENOSPC;
818 
819 	dev->mt76.global_wcid.idx = idx;
820 	dev->mt76.global_wcid.hw_key_idx = -1;
821 	dev->mt76.global_wcid.tx_info |= MT_WCID_TX_INFO_SET;
822 	rcu_assign_pointer(dev->mt76.wcid[idx], &dev->mt76.global_wcid);
823 
824 	return 0;
825 }
826 
mt7915_set_stream_vht_txbf_caps(struct mt7915_phy * phy)827 void mt7915_set_stream_vht_txbf_caps(struct mt7915_phy *phy)
828 {
829 	int sts;
830 	u32 *cap;
831 
832 	if (!phy->mt76->cap.has_5ghz)
833 		return;
834 
835 	sts = hweight8(phy->mt76->chainmask);
836 	cap = &phy->mt76->sband_5g.sband.vht_cap.cap;
837 
838 	*cap |= IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE |
839 		IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE |
840 		FIELD_PREP(IEEE80211_VHT_CAP_BEAMFORMEE_STS_MASK,
841 			   sts - 1);
842 
843 	*cap &= ~(IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK |
844 		  IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE |
845 		  IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE);
846 
847 	if (sts < 2)
848 		return;
849 
850 	*cap |= IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE |
851 		IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE |
852 		FIELD_PREP(IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK,
853 			   sts - 1);
854 }
855 
856 static void
mt7915_set_stream_he_txbf_caps(struct mt7915_phy * phy,struct ieee80211_sta_he_cap * he_cap,int vif)857 mt7915_set_stream_he_txbf_caps(struct mt7915_phy *phy,
858 			       struct ieee80211_sta_he_cap *he_cap, int vif)
859 {
860 	struct mt7915_dev *dev = phy->dev;
861 	struct ieee80211_he_cap_elem *elem = &he_cap->he_cap_elem;
862 	int sts = hweight8(phy->mt76->chainmask);
863 	u8 c, sts_160 = sts;
864 
865 	/* Can do 1/2 of STS in 160Mhz mode for mt7915 */
866 	if (is_mt7915(&dev->mt76)) {
867 		if (!dev->dbdc_support)
868 			sts_160 /= 2;
869 		else
870 			sts_160 = 0;
871 	}
872 
873 #ifdef CONFIG_MAC80211_MESH
874 	if (vif == NL80211_IFTYPE_MESH_POINT)
875 		return;
876 #endif
877 
878 	elem->phy_cap_info[3] &= ~IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER;
879 	elem->phy_cap_info[4] &= ~IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER;
880 
881 	c = IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK;
882 	if (sts_160)
883 		c |= IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_MASK;
884 	elem->phy_cap_info[5] &= ~c;
885 
886 	c = IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB |
887 	    IEEE80211_HE_PHY_CAP6_TRIG_MU_BEAMFORMING_PARTIAL_BW_FB;
888 	elem->phy_cap_info[6] &= ~c;
889 
890 	elem->phy_cap_info[7] &= ~IEEE80211_HE_PHY_CAP7_MAX_NC_MASK;
891 
892 	c = IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US;
893 	if (!is_mt7915(&dev->mt76))
894 		c |= IEEE80211_HE_PHY_CAP2_UL_MU_FULL_MU_MIMO |
895 		     IEEE80211_HE_PHY_CAP2_UL_MU_PARTIAL_MU_MIMO;
896 	elem->phy_cap_info[2] |= c;
897 
898 	c = IEEE80211_HE_PHY_CAP4_SU_BEAMFORMEE |
899 	    IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_4;
900 	if (sts_160)
901 		c |= IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_4;
902 	elem->phy_cap_info[4] |= c;
903 
904 	/* do not support NG16 due to spec D4.0 changes subcarrier idx */
905 	c = IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_42_SU |
906 	    IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_75_MU;
907 
908 	if (vif == NL80211_IFTYPE_STATION)
909 		c |= IEEE80211_HE_PHY_CAP6_PARTIAL_BANDWIDTH_DL_MUMIMO;
910 
911 	elem->phy_cap_info[6] |= c;
912 
913 	if (sts < 2)
914 		return;
915 
916 	/* the maximum cap is 4 x 3, (Nr, Nc) = (3, 2) */
917 	elem->phy_cap_info[7] |= min_t(int, sts - 1, 2) << 3;
918 
919 	if (vif != NL80211_IFTYPE_AP)
920 		return;
921 
922 	elem->phy_cap_info[3] |= IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER;
923 	elem->phy_cap_info[4] |= IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER;
924 
925 	c = FIELD_PREP(IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK,
926 		       sts - 1);
927 	if (sts_160)
928 		c |= FIELD_PREP(IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_MASK,
929 				sts_160 - 1);
930 	elem->phy_cap_info[5] |= c;
931 
932 	c = IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB |
933 	    IEEE80211_HE_PHY_CAP6_TRIG_MU_BEAMFORMING_PARTIAL_BW_FB;
934 	elem->phy_cap_info[6] |= c;
935 
936 	if (!is_mt7915(&dev->mt76)) {
937 		c = IEEE80211_HE_PHY_CAP7_STBC_TX_ABOVE_80MHZ |
938 		    IEEE80211_HE_PHY_CAP7_STBC_RX_ABOVE_80MHZ;
939 		elem->phy_cap_info[7] |= c;
940 	}
941 }
942 
943 static int
mt7915_init_he_caps(struct mt7915_phy * phy,enum nl80211_band band,struct ieee80211_sband_iftype_data * data)944 mt7915_init_he_caps(struct mt7915_phy *phy, enum nl80211_band band,
945 		    struct ieee80211_sband_iftype_data *data)
946 {
947 	struct mt7915_dev *dev = phy->dev;
948 	int i, idx = 0, nss = hweight8(phy->mt76->antenna_mask);
949 	u16 mcs_map = 0;
950 	u16 mcs_map_160 = 0;
951 	u8 nss_160;
952 
953 	if (!is_mt7915(&dev->mt76))
954 		nss_160 = nss;
955 	else if (!dev->dbdc_support)
956 		/* Can do 1/2 of NSS streams in 160Mhz mode for mt7915 */
957 		nss_160 = nss / 2;
958 	else
959 		/* Can't do 160MHz with mt7915 dbdc */
960 		nss_160 = 0;
961 
962 	for (i = 0; i < 8; i++) {
963 		if (i < nss)
964 			mcs_map |= (IEEE80211_HE_MCS_SUPPORT_0_11 << (i * 2));
965 		else
966 			mcs_map |= (IEEE80211_HE_MCS_NOT_SUPPORTED << (i * 2));
967 
968 		if (i < nss_160)
969 			mcs_map_160 |= (IEEE80211_HE_MCS_SUPPORT_0_11 << (i * 2));
970 		else
971 			mcs_map_160 |= (IEEE80211_HE_MCS_NOT_SUPPORTED << (i * 2));
972 	}
973 
974 	for (i = 0; i < NUM_NL80211_IFTYPES; i++) {
975 		struct ieee80211_sta_he_cap *he_cap = &data[idx].he_cap;
976 		struct ieee80211_he_cap_elem *he_cap_elem =
977 				&he_cap->he_cap_elem;
978 		struct ieee80211_he_mcs_nss_supp *he_mcs =
979 				&he_cap->he_mcs_nss_supp;
980 
981 		switch (i) {
982 		case NL80211_IFTYPE_STATION:
983 		case NL80211_IFTYPE_AP:
984 #ifdef CONFIG_MAC80211_MESH
985 		case NL80211_IFTYPE_MESH_POINT:
986 #endif
987 			break;
988 		default:
989 			continue;
990 		}
991 
992 		data[idx].types_mask = BIT(i);
993 		he_cap->has_he = true;
994 
995 		he_cap_elem->mac_cap_info[0] =
996 			IEEE80211_HE_MAC_CAP0_HTC_HE;
997 		he_cap_elem->mac_cap_info[3] =
998 			IEEE80211_HE_MAC_CAP3_OMI_CONTROL |
999 			IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_EXT_3;
1000 		he_cap_elem->mac_cap_info[4] =
1001 			IEEE80211_HE_MAC_CAP4_AMSDU_IN_AMPDU;
1002 
1003 		if (band == NL80211_BAND_2GHZ)
1004 			he_cap_elem->phy_cap_info[0] =
1005 				IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G;
1006 		else if (nss_160)
1007 			he_cap_elem->phy_cap_info[0] =
1008 				IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G |
1009 				IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G;
1010 		else
1011 			he_cap_elem->phy_cap_info[0] =
1012 				IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G;
1013 
1014 		he_cap_elem->phy_cap_info[1] =
1015 			IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD;
1016 		he_cap_elem->phy_cap_info[2] =
1017 			IEEE80211_HE_PHY_CAP2_STBC_TX_UNDER_80MHZ |
1018 			IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ;
1019 
1020 		switch (i) {
1021 		case NL80211_IFTYPE_AP:
1022 			he_cap_elem->mac_cap_info[0] |=
1023 				IEEE80211_HE_MAC_CAP0_TWT_RES;
1024 			he_cap_elem->mac_cap_info[2] |=
1025 				IEEE80211_HE_MAC_CAP2_BSR;
1026 			he_cap_elem->mac_cap_info[4] |=
1027 				IEEE80211_HE_MAC_CAP4_BQR;
1028 			he_cap_elem->mac_cap_info[5] |=
1029 				IEEE80211_HE_MAC_CAP5_OM_CTRL_UL_MU_DATA_DIS_RX;
1030 			he_cap_elem->phy_cap_info[3] |=
1031 				IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_QPSK |
1032 				IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_QPSK;
1033 			he_cap_elem->phy_cap_info[6] |=
1034 				IEEE80211_HE_PHY_CAP6_PARTIAL_BW_EXT_RANGE |
1035 				IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT;
1036 			he_cap_elem->phy_cap_info[9] |=
1037 				IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU |
1038 				IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU;
1039 			break;
1040 		case NL80211_IFTYPE_STATION:
1041 			he_cap_elem->mac_cap_info[1] |=
1042 				IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US;
1043 
1044 			if (band == NL80211_BAND_2GHZ)
1045 				he_cap_elem->phy_cap_info[0] |=
1046 					IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_RU_MAPPING_IN_2G;
1047 			else
1048 				he_cap_elem->phy_cap_info[0] |=
1049 					IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_RU_MAPPING_IN_5G;
1050 
1051 			he_cap_elem->phy_cap_info[1] |=
1052 				IEEE80211_HE_PHY_CAP1_DEVICE_CLASS_A |
1053 				IEEE80211_HE_PHY_CAP1_HE_LTF_AND_GI_FOR_HE_PPDUS_0_8US;
1054 			he_cap_elem->phy_cap_info[3] |=
1055 				IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_QPSK |
1056 				IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_QPSK;
1057 			he_cap_elem->phy_cap_info[6] |=
1058 				IEEE80211_HE_PHY_CAP6_TRIG_CQI_FB |
1059 				IEEE80211_HE_PHY_CAP6_PARTIAL_BW_EXT_RANGE |
1060 				IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT;
1061 			he_cap_elem->phy_cap_info[7] |=
1062 				IEEE80211_HE_PHY_CAP7_POWER_BOOST_FACTOR_SUPP |
1063 				IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI;
1064 			he_cap_elem->phy_cap_info[8] |=
1065 				IEEE80211_HE_PHY_CAP8_20MHZ_IN_40MHZ_HE_PPDU_IN_2G |
1066 				IEEE80211_HE_PHY_CAP8_DCM_MAX_RU_484;
1067 			if (nss_160)
1068 				he_cap_elem->phy_cap_info[8] |=
1069 					IEEE80211_HE_PHY_CAP8_20MHZ_IN_160MHZ_HE_PPDU |
1070 					IEEE80211_HE_PHY_CAP8_80MHZ_IN_160MHZ_HE_PPDU;
1071 			he_cap_elem->phy_cap_info[9] |=
1072 				IEEE80211_HE_PHY_CAP9_LONGER_THAN_16_SIGB_OFDM_SYM |
1073 				IEEE80211_HE_PHY_CAP9_NON_TRIGGERED_CQI_FEEDBACK |
1074 				IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU |
1075 				IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU |
1076 				IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_COMP_SIGB |
1077 				IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_NON_COMP_SIGB;
1078 			break;
1079 		}
1080 
1081 		memset(he_mcs, 0, sizeof(*he_mcs));
1082 		he_mcs->rx_mcs_80 = cpu_to_le16(mcs_map);
1083 		he_mcs->tx_mcs_80 = cpu_to_le16(mcs_map);
1084 		he_mcs->rx_mcs_160 = cpu_to_le16(mcs_map_160);
1085 		he_mcs->tx_mcs_160 = cpu_to_le16(mcs_map_160);
1086 
1087 		mt7915_set_stream_he_txbf_caps(phy, he_cap, i);
1088 
1089 		memset(he_cap->ppe_thres, 0, sizeof(he_cap->ppe_thres));
1090 		if (he_cap_elem->phy_cap_info[6] &
1091 		    IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT) {
1092 			mt76_connac_gen_ppe_thresh(he_cap->ppe_thres, nss);
1093 		} else {
1094 			he_cap_elem->phy_cap_info[9] |=
1095 				u8_encode_bits(IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_16US,
1096 					       IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_MASK);
1097 		}
1098 
1099 		if (band == NL80211_BAND_6GHZ) {
1100 			u16 cap = IEEE80211_HE_6GHZ_CAP_TX_ANTPAT_CONS |
1101 				  IEEE80211_HE_6GHZ_CAP_RX_ANTPAT_CONS;
1102 
1103 			cap |= u16_encode_bits(IEEE80211_HT_MPDU_DENSITY_2,
1104 					       IEEE80211_HE_6GHZ_CAP_MIN_MPDU_START) |
1105 			       u16_encode_bits(IEEE80211_VHT_MAX_AMPDU_1024K,
1106 					       IEEE80211_HE_6GHZ_CAP_MAX_AMPDU_LEN_EXP) |
1107 			       u16_encode_bits(IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454,
1108 					       IEEE80211_HE_6GHZ_CAP_MAX_MPDU_LEN);
1109 
1110 			data[idx].he_6ghz_capa.capa = cpu_to_le16(cap);
1111 		}
1112 
1113 		idx++;
1114 	}
1115 
1116 	return idx;
1117 }
1118 
mt7915_set_stream_he_caps(struct mt7915_phy * phy)1119 void mt7915_set_stream_he_caps(struct mt7915_phy *phy)
1120 {
1121 	struct ieee80211_sband_iftype_data *data;
1122 	struct ieee80211_supported_band *band;
1123 	int n;
1124 
1125 	if (phy->mt76->cap.has_2ghz) {
1126 		data = phy->iftype[NL80211_BAND_2GHZ];
1127 		n = mt7915_init_he_caps(phy, NL80211_BAND_2GHZ, data);
1128 
1129 		band = &phy->mt76->sband_2g.sband;
1130 		band->iftype_data = data;
1131 		band->n_iftype_data = n;
1132 	}
1133 
1134 	if (phy->mt76->cap.has_5ghz) {
1135 		data = phy->iftype[NL80211_BAND_5GHZ];
1136 		n = mt7915_init_he_caps(phy, NL80211_BAND_5GHZ, data);
1137 
1138 		band = &phy->mt76->sband_5g.sband;
1139 		band->iftype_data = data;
1140 		band->n_iftype_data = n;
1141 	}
1142 
1143 	if (phy->mt76->cap.has_6ghz) {
1144 		data = phy->iftype[NL80211_BAND_6GHZ];
1145 		n = mt7915_init_he_caps(phy, NL80211_BAND_6GHZ, data);
1146 
1147 		band = &phy->mt76->sband_6g.sband;
1148 		band->iftype_data = data;
1149 		band->n_iftype_data = n;
1150 	}
1151 }
1152 
mt7915_unregister_ext_phy(struct mt7915_dev * dev)1153 static void mt7915_unregister_ext_phy(struct mt7915_dev *dev)
1154 {
1155 	struct mt7915_phy *phy = mt7915_ext_phy(dev);
1156 	struct mt76_phy *mphy = dev->mt76.phys[MT_BAND1];
1157 
1158 	if (!phy)
1159 		return;
1160 
1161 	mt7915_unregister_thermal(phy);
1162 	mt76_unregister_phy(mphy);
1163 	ieee80211_free_hw(mphy->hw);
1164 }
1165 
mt7915_stop_hardware(struct mt7915_dev * dev)1166 static void mt7915_stop_hardware(struct mt7915_dev *dev)
1167 {
1168 	mt7915_mcu_exit(dev);
1169 	mt76_connac2_tx_token_put(&dev->mt76);
1170 	mt7915_dma_cleanup(dev);
1171 	tasklet_disable(&dev->mt76.irq_tasklet);
1172 
1173 	if (is_mt798x(&dev->mt76))
1174 		mt7986_wmac_disable(dev);
1175 }
1176 
mt7915_register_device(struct mt7915_dev * dev)1177 int mt7915_register_device(struct mt7915_dev *dev)
1178 {
1179 	struct mt7915_phy *phy2;
1180 	int ret;
1181 
1182 	dev->phy.dev = dev;
1183 	dev->phy.mt76 = &dev->mt76.phy;
1184 	dev->mt76.phy.priv = &dev->phy;
1185 	INIT_WORK(&dev->rc_work, mt7915_mac_sta_rc_work);
1186 	INIT_DELAYED_WORK(&dev->mphy.mac_work, mt7915_mac_work);
1187 	INIT_LIST_HEAD(&dev->sta_rc_list);
1188 	INIT_LIST_HEAD(&dev->twt_list);
1189 
1190 	init_waitqueue_head(&dev->reset_wait);
1191 	INIT_WORK(&dev->reset_work, mt7915_mac_reset_work);
1192 	INIT_WORK(&dev->dump_work, mt7915_mac_dump_work);
1193 	mutex_init(&dev->dump_mutex);
1194 
1195 	dev->dbdc_support = mt7915_band_config(dev);
1196 
1197 	phy2 = mt7915_alloc_ext_phy(dev);
1198 	if (IS_ERR(phy2))
1199 		return PTR_ERR(phy2);
1200 
1201 	ret = mt7915_init_hardware(dev, phy2);
1202 	if (ret)
1203 		goto free_phy2;
1204 
1205 	mt7915_init_wiphy(&dev->phy);
1206 
1207 #ifdef CONFIG_NL80211_TESTMODE
1208 	dev->mt76.test_ops = &mt7915_testmode_ops;
1209 #endif
1210 
1211 	ret = mt76_register_device(&dev->mt76, true, mt76_rates,
1212 				   ARRAY_SIZE(mt76_rates));
1213 	if (ret)
1214 		goto stop_hw;
1215 
1216 	ret = mt7915_thermal_init(&dev->phy);
1217 	if (ret)
1218 		goto unreg_dev;
1219 
1220 	ieee80211_queue_work(mt76_hw(dev), &dev->init_work);
1221 
1222 	if (phy2) {
1223 		ret = mt7915_register_ext_phy(dev, phy2);
1224 		if (ret)
1225 			goto unreg_thermal;
1226 	}
1227 
1228 	dev->recovery.hw_init_done = true;
1229 
1230 	ret = mt7915_init_debugfs(&dev->phy);
1231 	if (ret)
1232 		goto unreg_thermal;
1233 
1234 	ret = mt7915_coredump_register(dev);
1235 	if (ret)
1236 		goto unreg_thermal;
1237 
1238 	return 0;
1239 
1240 unreg_thermal:
1241 	mt7915_unregister_thermal(&dev->phy);
1242 unreg_dev:
1243 	mt76_unregister_device(&dev->mt76);
1244 stop_hw:
1245 	mt7915_stop_hardware(dev);
1246 free_phy2:
1247 	if (phy2)
1248 		ieee80211_free_hw(phy2->mt76->hw);
1249 	return ret;
1250 }
1251 
mt7915_unregister_device(struct mt7915_dev * dev)1252 void mt7915_unregister_device(struct mt7915_dev *dev)
1253 {
1254 	mt7915_unregister_ext_phy(dev);
1255 	mt7915_coredump_unregister(dev);
1256 	mt7915_unregister_thermal(&dev->phy);
1257 	mt76_unregister_device(&dev->mt76);
1258 	mt7915_stop_hardware(dev);
1259 
1260 	mt76_free_device(&dev->mt76);
1261 }
1262