1 /* SPDX-License-Identifier: ISC */
2 /*
3 * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name>
4 */
5
6 #ifndef __MT76_H
7 #define __MT76_H
8
9 #include <linux/kernel.h>
10 #include <linux/io.h>
11 #include <linux/spinlock.h>
12 #include <linux/skbuff.h>
13 #include <linux/leds.h>
14 #include <linux/usb.h>
15 #include <linux/average.h>
16 #include <linux/soc/mediatek/mtk_wed.h>
17 #include <net/mac80211.h>
18 #include <net/page_pool/helpers.h>
19 #include "util.h"
20 #include "testmode.h"
21
22 #define MT_MCU_RING_SIZE 32
23 #define MT_RX_BUF_SIZE 2048
24 #define MT_SKB_HEAD_LEN 256
25
26 #define MT_MAX_NON_AQL_PKT 16
27 #define MT_TXQ_FREE_THR 32
28
29 #define MT76_TOKEN_FREE_THR 64
30
31 #define MT_QFLAG_WED_RING GENMASK(1, 0)
32 #define MT_QFLAG_WED_TYPE GENMASK(3, 2)
33 #define MT_QFLAG_WED BIT(4)
34
35 #define __MT_WED_Q(_type, _n) (MT_QFLAG_WED | \
36 FIELD_PREP(MT_QFLAG_WED_TYPE, _type) | \
37 FIELD_PREP(MT_QFLAG_WED_RING, _n))
38 #define MT_WED_Q_TX(_n) __MT_WED_Q(MT76_WED_Q_TX, _n)
39 #define MT_WED_Q_RX(_n) __MT_WED_Q(MT76_WED_Q_RX, _n)
40 #define MT_WED_Q_TXFREE __MT_WED_Q(MT76_WED_Q_TXFREE, 0)
41
42 struct mt76_dev;
43 struct mt76_phy;
44 struct mt76_wcid;
45 struct mt76s_intr;
46
47 struct mt76_reg_pair {
48 u32 reg;
49 u32 value;
50 };
51
52 enum mt76_bus_type {
53 MT76_BUS_MMIO,
54 MT76_BUS_USB,
55 MT76_BUS_SDIO,
56 };
57
58 enum mt76_wed_type {
59 MT76_WED_Q_TX,
60 MT76_WED_Q_TXFREE,
61 MT76_WED_Q_RX,
62 };
63
64 struct mt76_bus_ops {
65 u32 (*rr)(struct mt76_dev *dev, u32 offset);
66 void (*wr)(struct mt76_dev *dev, u32 offset, u32 val);
67 u32 (*rmw)(struct mt76_dev *dev, u32 offset, u32 mask, u32 val);
68 void (*write_copy)(struct mt76_dev *dev, u32 offset, const void *data,
69 int len);
70 void (*read_copy)(struct mt76_dev *dev, u32 offset, void *data,
71 int len);
72 int (*wr_rp)(struct mt76_dev *dev, u32 base,
73 const struct mt76_reg_pair *rp, int len);
74 int (*rd_rp)(struct mt76_dev *dev, u32 base,
75 struct mt76_reg_pair *rp, int len);
76 enum mt76_bus_type type;
77 };
78
79 #define mt76_is_usb(dev) ((dev)->bus->type == MT76_BUS_USB)
80 #define mt76_is_mmio(dev) ((dev)->bus->type == MT76_BUS_MMIO)
81 #define mt76_is_sdio(dev) ((dev)->bus->type == MT76_BUS_SDIO)
82
83 enum mt76_txq_id {
84 MT_TXQ_VO = IEEE80211_AC_VO,
85 MT_TXQ_VI = IEEE80211_AC_VI,
86 MT_TXQ_BE = IEEE80211_AC_BE,
87 MT_TXQ_BK = IEEE80211_AC_BK,
88 MT_TXQ_PSD,
89 MT_TXQ_BEACON,
90 MT_TXQ_CAB,
91 __MT_TXQ_MAX
92 };
93
94 enum mt76_mcuq_id {
95 MT_MCUQ_WM,
96 MT_MCUQ_WA,
97 MT_MCUQ_FWDL,
98 __MT_MCUQ_MAX
99 };
100
101 enum mt76_rxq_id {
102 MT_RXQ_MAIN,
103 MT_RXQ_MCU,
104 MT_RXQ_MCU_WA,
105 MT_RXQ_BAND1,
106 MT_RXQ_BAND1_WA,
107 MT_RXQ_MAIN_WA,
108 MT_RXQ_BAND2,
109 MT_RXQ_BAND2_WA,
110 __MT_RXQ_MAX
111 };
112
113 enum mt76_band_id {
114 MT_BAND0,
115 MT_BAND1,
116 MT_BAND2,
117 __MT_MAX_BAND
118 };
119
120 enum mt76_cipher_type {
121 MT_CIPHER_NONE,
122 MT_CIPHER_WEP40,
123 MT_CIPHER_TKIP,
124 MT_CIPHER_TKIP_NO_MIC,
125 MT_CIPHER_AES_CCMP,
126 MT_CIPHER_WEP104,
127 MT_CIPHER_BIP_CMAC_128,
128 MT_CIPHER_WEP128,
129 MT_CIPHER_WAPI,
130 MT_CIPHER_CCMP_CCX,
131 MT_CIPHER_CCMP_256,
132 MT_CIPHER_GCMP,
133 MT_CIPHER_GCMP_256,
134 };
135
136 enum mt76_dfs_state {
137 MT_DFS_STATE_UNKNOWN,
138 MT_DFS_STATE_DISABLED,
139 MT_DFS_STATE_CAC,
140 MT_DFS_STATE_ACTIVE,
141 };
142
143 struct mt76_queue_buf {
144 dma_addr_t addr;
145 u16 len;
146 bool skip_unmap;
147 };
148
149 struct mt76_tx_info {
150 struct mt76_queue_buf buf[32];
151 struct sk_buff *skb;
152 int nbuf;
153 u32 info;
154 };
155
156 struct mt76_queue_entry {
157 union {
158 void *buf;
159 struct sk_buff *skb;
160 };
161 union {
162 struct mt76_txwi_cache *txwi;
163 struct urb *urb;
164 int buf_sz;
165 };
166 u32 dma_addr[2];
167 u16 dma_len[2];
168 u16 wcid;
169 bool skip_buf0:1;
170 bool skip_buf1:1;
171 bool done:1;
172 };
173
174 struct mt76_queue_regs {
175 u32 desc_base;
176 u32 ring_size;
177 u32 cpu_idx;
178 u32 dma_idx;
179 } __packed __aligned(4);
180
181 struct mt76_queue {
182 struct mt76_queue_regs __iomem *regs;
183
184 spinlock_t lock;
185 spinlock_t cleanup_lock;
186 struct mt76_queue_entry *entry;
187 struct mt76_desc *desc;
188
189 u16 first;
190 u16 head;
191 u16 tail;
192 int ndesc;
193 int queued;
194 int buf_size;
195 bool stopped;
196 bool blocked;
197
198 u8 buf_offset;
199 u8 hw_idx;
200 u8 flags;
201
202 u32 wed_regs;
203
204 dma_addr_t desc_dma;
205 struct sk_buff *rx_head;
206 struct page_pool *page_pool;
207 };
208
209 struct mt76_mcu_ops {
210 u32 headroom;
211 u32 tailroom;
212
213 int (*mcu_send_msg)(struct mt76_dev *dev, int cmd, const void *data,
214 int len, bool wait_resp);
215 int (*mcu_skb_send_msg)(struct mt76_dev *dev, struct sk_buff *skb,
216 int cmd, int *seq);
217 int (*mcu_parse_response)(struct mt76_dev *dev, int cmd,
218 struct sk_buff *skb, int seq);
219 u32 (*mcu_rr)(struct mt76_dev *dev, u32 offset);
220 void (*mcu_wr)(struct mt76_dev *dev, u32 offset, u32 val);
221 int (*mcu_wr_rp)(struct mt76_dev *dev, u32 base,
222 const struct mt76_reg_pair *rp, int len);
223 int (*mcu_rd_rp)(struct mt76_dev *dev, u32 base,
224 struct mt76_reg_pair *rp, int len);
225 int (*mcu_restart)(struct mt76_dev *dev);
226 };
227
228 struct mt76_queue_ops {
229 int (*init)(struct mt76_dev *dev,
230 int (*poll)(struct napi_struct *napi, int budget));
231
232 int (*alloc)(struct mt76_dev *dev, struct mt76_queue *q,
233 int idx, int n_desc, int bufsize,
234 u32 ring_base);
235
236 int (*tx_queue_skb)(struct mt76_dev *dev, struct mt76_queue *q,
237 enum mt76_txq_id qid, struct sk_buff *skb,
238 struct mt76_wcid *wcid, struct ieee80211_sta *sta);
239
240 int (*tx_queue_skb_raw)(struct mt76_dev *dev, struct mt76_queue *q,
241 struct sk_buff *skb, u32 tx_info);
242
243 void *(*dequeue)(struct mt76_dev *dev, struct mt76_queue *q, bool flush,
244 int *len, u32 *info, bool *more);
245
246 void (*rx_reset)(struct mt76_dev *dev, enum mt76_rxq_id qid);
247
248 void (*tx_cleanup)(struct mt76_dev *dev, struct mt76_queue *q,
249 bool flush);
250
251 void (*rx_cleanup)(struct mt76_dev *dev, struct mt76_queue *q);
252
253 void (*kick)(struct mt76_dev *dev, struct mt76_queue *q);
254
255 void (*reset_q)(struct mt76_dev *dev, struct mt76_queue *q);
256 };
257
258 enum mt76_phy_type {
259 MT_PHY_TYPE_CCK,
260 MT_PHY_TYPE_OFDM,
261 MT_PHY_TYPE_HT,
262 MT_PHY_TYPE_HT_GF,
263 MT_PHY_TYPE_VHT,
264 MT_PHY_TYPE_HE_SU = 8,
265 MT_PHY_TYPE_HE_EXT_SU,
266 MT_PHY_TYPE_HE_TB,
267 MT_PHY_TYPE_HE_MU,
268 MT_PHY_TYPE_EHT_SU = 13,
269 MT_PHY_TYPE_EHT_TRIG,
270 MT_PHY_TYPE_EHT_MU,
271 __MT_PHY_TYPE_MAX,
272 };
273
274 struct mt76_sta_stats {
275 u64 tx_mode[__MT_PHY_TYPE_MAX];
276 u64 tx_bw[5]; /* 20, 40, 80, 160, 320 */
277 u64 tx_nss[4]; /* 1, 2, 3, 4 */
278 u64 tx_mcs[16]; /* mcs idx */
279 u64 tx_bytes;
280 /* WED TX */
281 u32 tx_packets; /* unit: MSDU */
282 u32 tx_retries;
283 u32 tx_failed;
284 /* WED RX */
285 u64 rx_bytes;
286 u32 rx_packets;
287 u32 rx_errors;
288 u32 rx_drops;
289 };
290
291 enum mt76_wcid_flags {
292 MT_WCID_FLAG_CHECK_PS,
293 MT_WCID_FLAG_PS,
294 MT_WCID_FLAG_4ADDR,
295 MT_WCID_FLAG_HDR_TRANS,
296 };
297
298 #define MT76_N_WCIDS 1088
299
300 /* stored in ieee80211_tx_info::hw_queue */
301 #define MT_TX_HW_QUEUE_PHY GENMASK(3, 2)
302
303 DECLARE_EWMA(signal, 10, 8);
304
305 #define MT_WCID_TX_INFO_RATE GENMASK(15, 0)
306 #define MT_WCID_TX_INFO_NSS GENMASK(17, 16)
307 #define MT_WCID_TX_INFO_TXPWR_ADJ GENMASK(25, 18)
308 #define MT_WCID_TX_INFO_SET BIT(31)
309
310 struct mt76_wcid {
311 struct mt76_rx_tid __rcu *aggr[IEEE80211_NUM_TIDS];
312
313 atomic_t non_aql_packets;
314 unsigned long flags;
315
316 struct ewma_signal rssi;
317 int inactive_count;
318
319 struct rate_info rate;
320 unsigned long ampdu_state;
321
322 u16 idx;
323 u8 hw_key_idx;
324 u8 hw_key_idx2;
325
326 u8 sta:1;
327 u8 amsdu:1;
328 u8 phy_idx:2;
329
330 u8 rx_check_pn;
331 u8 rx_key_pn[IEEE80211_NUM_TIDS + 1][6];
332 u16 cipher;
333
334 u32 tx_info;
335 bool sw_iv;
336
337 struct list_head list;
338 struct idr pktid;
339
340 struct mt76_sta_stats stats;
341
342 struct list_head poll_list;
343 };
344
345 struct mt76_txq {
346 u16 wcid;
347
348 u16 agg_ssn;
349 bool send_bar;
350 bool aggr;
351 };
352
353 struct mt76_txwi_cache {
354 struct list_head list;
355 dma_addr_t dma_addr;
356
357 union {
358 struct sk_buff *skb;
359 void *ptr;
360 };
361 };
362
363 struct mt76_rx_tid {
364 struct rcu_head rcu_head;
365
366 struct mt76_dev *dev;
367
368 spinlock_t lock;
369 struct delayed_work reorder_work;
370
371 u16 head;
372 u16 size;
373 u16 nframes;
374
375 u8 num;
376
377 u8 started:1, stopped:1, timer_pending:1;
378
379 struct sk_buff *reorder_buf[];
380 };
381
382 #define MT_TX_CB_DMA_DONE BIT(0)
383 #define MT_TX_CB_TXS_DONE BIT(1)
384 #define MT_TX_CB_TXS_FAILED BIT(2)
385
386 #define MT_PACKET_ID_MASK GENMASK(6, 0)
387 #define MT_PACKET_ID_NO_ACK 0
388 #define MT_PACKET_ID_NO_SKB 1
389 #define MT_PACKET_ID_WED 2
390 #define MT_PACKET_ID_FIRST 3
391 #define MT_PACKET_ID_HAS_RATE BIT(7)
392 /* This is timer for when to give up when waiting for TXS callback,
393 * with starting time being the time at which the DMA_DONE callback
394 * was seen (so, we know packet was processed then, it should not take
395 * long after that for firmware to send the TXS callback if it is going
396 * to do so.)
397 */
398 #define MT_TX_STATUS_SKB_TIMEOUT (HZ / 4)
399
400 struct mt76_tx_cb {
401 unsigned long jiffies;
402 u16 wcid;
403 u8 pktid;
404 u8 flags;
405 };
406
407 enum {
408 MT76_STATE_INITIALIZED,
409 MT76_STATE_REGISTERED,
410 MT76_STATE_RUNNING,
411 MT76_STATE_MCU_RUNNING,
412 MT76_SCANNING,
413 MT76_HW_SCANNING,
414 MT76_HW_SCHED_SCANNING,
415 MT76_RESTART,
416 MT76_RESET,
417 MT76_MCU_RESET,
418 MT76_REMOVED,
419 MT76_READING_STATS,
420 MT76_STATE_POWER_OFF,
421 MT76_STATE_SUSPEND,
422 MT76_STATE_ROC,
423 MT76_STATE_PM,
424 MT76_STATE_WED_RESET,
425 };
426
427 struct mt76_hw_cap {
428 bool has_2ghz;
429 bool has_5ghz;
430 bool has_6ghz;
431 };
432
433 #define MT_DRV_TXWI_NO_FREE BIT(0)
434 #define MT_DRV_TX_ALIGNED4_SKBS BIT(1)
435 #define MT_DRV_SW_RX_AIRTIME BIT(2)
436 #define MT_DRV_RX_DMA_HDR BIT(3)
437 #define MT_DRV_HW_MGMT_TXQ BIT(4)
438 #define MT_DRV_AMSDU_OFFLOAD BIT(5)
439
440 struct mt76_driver_ops {
441 u32 drv_flags;
442 u32 survey_flags;
443 u16 txwi_size;
444 u16 token_size;
445 u8 mcs_rates;
446
447 void (*update_survey)(struct mt76_phy *phy);
448
449 int (*tx_prepare_skb)(struct mt76_dev *dev, void *txwi_ptr,
450 enum mt76_txq_id qid, struct mt76_wcid *wcid,
451 struct ieee80211_sta *sta,
452 struct mt76_tx_info *tx_info);
453
454 void (*tx_complete_skb)(struct mt76_dev *dev,
455 struct mt76_queue_entry *e);
456
457 bool (*tx_status_data)(struct mt76_dev *dev, u8 *update);
458
459 bool (*rx_check)(struct mt76_dev *dev, void *data, int len);
460
461 void (*rx_skb)(struct mt76_dev *dev, enum mt76_rxq_id q,
462 struct sk_buff *skb, u32 *info);
463
464 void (*rx_poll_complete)(struct mt76_dev *dev, enum mt76_rxq_id q);
465
466 void (*sta_ps)(struct mt76_dev *dev, struct ieee80211_sta *sta,
467 bool ps);
468
469 int (*sta_add)(struct mt76_dev *dev, struct ieee80211_vif *vif,
470 struct ieee80211_sta *sta);
471
472 void (*sta_assoc)(struct mt76_dev *dev, struct ieee80211_vif *vif,
473 struct ieee80211_sta *sta);
474
475 void (*sta_remove)(struct mt76_dev *dev, struct ieee80211_vif *vif,
476 struct ieee80211_sta *sta);
477 };
478
479 struct mt76_channel_state {
480 u64 cc_active;
481 u64 cc_busy;
482 u64 cc_rx;
483 u64 cc_bss_rx;
484 u64 cc_tx;
485
486 s8 noise;
487 };
488
489 struct mt76_sband {
490 struct ieee80211_supported_band sband;
491 struct mt76_channel_state *chan;
492 };
493
494 /* addr req mask */
495 #define MT_VEND_TYPE_EEPROM BIT(31)
496 #define MT_VEND_TYPE_CFG BIT(30)
497 #define MT_VEND_TYPE_MASK (MT_VEND_TYPE_EEPROM | MT_VEND_TYPE_CFG)
498
499 #define MT_VEND_ADDR(type, n) (MT_VEND_TYPE_##type | (n))
500 enum mt_vendor_req {
501 MT_VEND_DEV_MODE = 0x1,
502 MT_VEND_WRITE = 0x2,
503 MT_VEND_POWER_ON = 0x4,
504 MT_VEND_MULTI_WRITE = 0x6,
505 MT_VEND_MULTI_READ = 0x7,
506 MT_VEND_READ_EEPROM = 0x9,
507 MT_VEND_WRITE_FCE = 0x42,
508 MT_VEND_WRITE_CFG = 0x46,
509 MT_VEND_READ_CFG = 0x47,
510 MT_VEND_READ_EXT = 0x63,
511 MT_VEND_WRITE_EXT = 0x66,
512 MT_VEND_FEATURE_SET = 0x91,
513 };
514
515 enum mt76u_in_ep {
516 MT_EP_IN_PKT_RX,
517 MT_EP_IN_CMD_RESP,
518 __MT_EP_IN_MAX,
519 };
520
521 enum mt76u_out_ep {
522 MT_EP_OUT_INBAND_CMD,
523 MT_EP_OUT_AC_BE,
524 MT_EP_OUT_AC_BK,
525 MT_EP_OUT_AC_VI,
526 MT_EP_OUT_AC_VO,
527 MT_EP_OUT_HCCA,
528 __MT_EP_OUT_MAX,
529 };
530
531 struct mt76_mcu {
532 struct mutex mutex;
533 u32 msg_seq;
534 int timeout;
535
536 struct sk_buff_head res_q;
537 wait_queue_head_t wait;
538 };
539
540 #define MT_TX_SG_MAX_SIZE 8
541 #define MT_RX_SG_MAX_SIZE 4
542 #define MT_NUM_TX_ENTRIES 256
543 #define MT_NUM_RX_ENTRIES 128
544 #define MCU_RESP_URB_SIZE 1024
545 struct mt76_usb {
546 struct mutex usb_ctrl_mtx;
547 u8 *data;
548 u16 data_len;
549
550 struct mt76_worker status_worker;
551 struct mt76_worker rx_worker;
552
553 struct work_struct stat_work;
554
555 u8 out_ep[__MT_EP_OUT_MAX];
556 u8 in_ep[__MT_EP_IN_MAX];
557 bool sg_en;
558
559 struct mt76u_mcu {
560 u8 *data;
561 /* multiple reads */
562 struct mt76_reg_pair *rp;
563 int rp_len;
564 u32 base;
565 } mcu;
566 };
567
568 #define MT76S_XMIT_BUF_SZ 0x3fe00
569 #define MT76S_NUM_TX_ENTRIES 256
570 #define MT76S_NUM_RX_ENTRIES 512
571 struct mt76_sdio {
572 struct mt76_worker txrx_worker;
573 struct mt76_worker status_worker;
574 struct mt76_worker net_worker;
575 struct mt76_worker stat_worker;
576
577 u8 *xmit_buf;
578 u32 xmit_buf_sz;
579
580 struct sdio_func *func;
581 void *intr_data;
582 u8 hw_ver;
583 wait_queue_head_t wait;
584
585 struct {
586 int pse_data_quota;
587 int ple_data_quota;
588 int pse_mcu_quota;
589 int pse_page_size;
590 int deficit;
591 } sched;
592
593 int (*parse_irq)(struct mt76_dev *dev, struct mt76s_intr *intr);
594 };
595
596 struct mt76_mmio {
597 void __iomem *regs;
598 spinlock_t irq_lock;
599 u32 irqmask;
600
601 struct mtk_wed_device wed;
602 struct completion wed_reset;
603 struct completion wed_reset_complete;
604 };
605
606 struct mt76_rx_status {
607 union {
608 struct mt76_wcid *wcid;
609 u16 wcid_idx;
610 };
611
612 u32 reorder_time;
613
614 u32 ampdu_ref;
615 u32 timestamp;
616
617 u8 iv[6];
618
619 u8 phy_idx:2;
620 u8 aggr:1;
621 u8 qos_ctl;
622 u16 seqno;
623
624 u16 freq;
625 u32 flag;
626 u8 enc_flags;
627 u8 encoding:3, bw:4;
628 union {
629 struct {
630 u8 he_ru:3;
631 u8 he_gi:2;
632 u8 he_dcm:1;
633 };
634 struct {
635 u8 ru:4;
636 u8 gi:2;
637 } eht;
638 };
639
640 u8 amsdu:1, first_amsdu:1, last_amsdu:1;
641 u8 rate_idx;
642 u8 nss:5, band:3;
643 s8 signal;
644 u8 chains;
645 s8 chain_signal[IEEE80211_MAX_CHAINS];
646 };
647
648 struct mt76_freq_range_power {
649 const struct cfg80211_sar_freq_ranges *range;
650 s8 power;
651 };
652
653 struct mt76_testmode_ops {
654 int (*set_state)(struct mt76_phy *phy, enum mt76_testmode_state state);
655 int (*set_params)(struct mt76_phy *phy, struct nlattr **tb,
656 enum mt76_testmode_state new_state);
657 int (*dump_stats)(struct mt76_phy *phy, struct sk_buff *msg);
658 };
659
660 struct mt76_testmode_data {
661 enum mt76_testmode_state state;
662
663 u32 param_set[DIV_ROUND_UP(NUM_MT76_TM_ATTRS, 32)];
664 struct sk_buff *tx_skb;
665
666 u32 tx_count;
667 u16 tx_mpdu_len;
668
669 u8 tx_rate_mode;
670 u8 tx_rate_idx;
671 u8 tx_rate_nss;
672 u8 tx_rate_sgi;
673 u8 tx_rate_ldpc;
674 u8 tx_rate_stbc;
675 u8 tx_ltf;
676
677 u8 tx_antenna_mask;
678 u8 tx_spe_idx;
679
680 u8 tx_duty_cycle;
681 u32 tx_time;
682 u32 tx_ipg;
683
684 u32 freq_offset;
685
686 u8 tx_power[4];
687 u8 tx_power_control;
688
689 u8 addr[3][ETH_ALEN];
690
691 u32 tx_pending;
692 u32 tx_queued;
693 u16 tx_queued_limit;
694 u32 tx_done;
695 struct {
696 u64 packets[__MT_RXQ_MAX];
697 u64 fcs_error[__MT_RXQ_MAX];
698 } rx_stats;
699 };
700
701 struct mt76_vif {
702 u8 idx;
703 u8 omac_idx;
704 u8 band_idx;
705 u8 wmm_idx;
706 u8 scan_seq_num;
707 u8 cipher;
708 u8 basic_rates_idx;
709 u8 mcast_rates_idx;
710 u8 beacon_rates_idx;
711 struct ieee80211_chanctx_conf *ctx;
712 };
713
714 struct mt76_phy {
715 struct ieee80211_hw *hw;
716 struct mt76_dev *dev;
717 void *priv;
718
719 unsigned long state;
720 u8 band_idx;
721
722 struct mt76_queue *q_tx[__MT_TXQ_MAX];
723
724 struct cfg80211_chan_def chandef;
725 struct ieee80211_channel *main_chan;
726
727 struct mt76_channel_state *chan_state;
728 enum mt76_dfs_state dfs_state;
729 ktime_t survey_time;
730
731 u32 aggr_stats[32];
732
733 struct mt76_hw_cap cap;
734 struct mt76_sband sband_2g;
735 struct mt76_sband sband_5g;
736 struct mt76_sband sband_6g;
737
738 u8 macaddr[ETH_ALEN];
739
740 int txpower_cur;
741 u8 antenna_mask;
742 u16 chainmask;
743
744 #ifdef CONFIG_NL80211_TESTMODE
745 struct mt76_testmode_data test;
746 #endif
747
748 struct delayed_work mac_work;
749 u8 mac_work_count;
750
751 struct {
752 struct sk_buff *head;
753 struct sk_buff **tail;
754 u16 seqno;
755 } rx_amsdu[__MT_RXQ_MAX];
756
757 struct mt76_freq_range_power *frp;
758
759 struct {
760 struct led_classdev cdev;
761 char name[32];
762 bool al;
763 u8 pin;
764 } leds;
765 };
766
767 struct mt76_dev {
768 struct mt76_phy phy; /* must be first */
769 struct mt76_phy *phys[__MT_MAX_BAND];
770
771 struct ieee80211_hw *hw;
772
773 spinlock_t wed_lock;
774 spinlock_t lock;
775 spinlock_t cc_lock;
776
777 u32 cur_cc_bss_rx;
778
779 struct mt76_rx_status rx_ampdu_status;
780 u32 rx_ampdu_len;
781 u32 rx_ampdu_ref;
782
783 struct mutex mutex;
784
785 const struct mt76_bus_ops *bus;
786 const struct mt76_driver_ops *drv;
787 const struct mt76_mcu_ops *mcu_ops;
788 struct device *dev;
789 struct device *dma_dev;
790
791 struct mt76_mcu mcu;
792
793 struct net_device napi_dev;
794 struct net_device tx_napi_dev;
795 spinlock_t rx_lock;
796 struct napi_struct napi[__MT_RXQ_MAX];
797 struct sk_buff_head rx_skb[__MT_RXQ_MAX];
798 struct tasklet_struct irq_tasklet;
799
800 struct list_head txwi_cache;
801 struct list_head rxwi_cache;
802 struct mt76_queue *q_mcu[__MT_MCUQ_MAX];
803 struct mt76_queue q_rx[__MT_RXQ_MAX];
804 const struct mt76_queue_ops *queue_ops;
805 int tx_dma_idx[4];
806
807 struct mt76_worker tx_worker;
808 struct napi_struct tx_napi;
809
810 spinlock_t token_lock;
811 struct idr token;
812 u16 wed_token_count;
813 u16 token_count;
814 u16 token_size;
815
816 spinlock_t rx_token_lock;
817 struct idr rx_token;
818 u16 rx_token_size;
819
820 wait_queue_head_t tx_wait;
821 /* spinclock used to protect wcid pktid linked list */
822 spinlock_t status_lock;
823
824 u32 wcid_mask[DIV_ROUND_UP(MT76_N_WCIDS, 32)];
825 u32 wcid_phy_mask[DIV_ROUND_UP(MT76_N_WCIDS, 32)];
826
827 u64 vif_mask;
828
829 struct mt76_wcid global_wcid;
830 struct mt76_wcid __rcu *wcid[MT76_N_WCIDS];
831 struct list_head wcid_list;
832
833 struct list_head sta_poll_list;
834 spinlock_t sta_poll_lock;
835
836 u32 rev;
837
838 struct tasklet_struct pre_tbtt_tasklet;
839 int beacon_int;
840 u8 beacon_mask;
841
842 struct debugfs_blob_wrapper eeprom;
843 struct debugfs_blob_wrapper otp;
844
845 char alpha2[3];
846 enum nl80211_dfs_regions region;
847
848 u32 debugfs_reg;
849
850 u8 csa_complete;
851
852 u32 rxfilter;
853
854 #ifdef CONFIG_NL80211_TESTMODE
855 const struct mt76_testmode_ops *test_ops;
856 struct {
857 const char *name;
858 u32 offset;
859 } test_mtd;
860 #endif
861 struct workqueue_struct *wq;
862
863 union {
864 struct mt76_mmio mmio;
865 struct mt76_usb usb;
866 struct mt76_sdio sdio;
867 };
868 };
869
870 /* per-phy stats. */
871 struct mt76_mib_stats {
872 u32 ack_fail_cnt;
873 u32 fcs_err_cnt;
874 u32 rts_cnt;
875 u32 rts_retries_cnt;
876 u32 ba_miss_cnt;
877 u32 tx_bf_cnt;
878 u32 tx_mu_bf_cnt;
879 u32 tx_mu_mpdu_cnt;
880 u32 tx_mu_acked_mpdu_cnt;
881 u32 tx_su_acked_mpdu_cnt;
882 u32 tx_bf_ibf_ppdu_cnt;
883 u32 tx_bf_ebf_ppdu_cnt;
884
885 u32 tx_bf_rx_fb_all_cnt;
886 u32 tx_bf_rx_fb_eht_cnt;
887 u32 tx_bf_rx_fb_he_cnt;
888 u32 tx_bf_rx_fb_vht_cnt;
889 u32 tx_bf_rx_fb_ht_cnt;
890
891 u32 tx_bf_rx_fb_bw; /* value of last sample, not cumulative */
892 u32 tx_bf_rx_fb_nc_cnt;
893 u32 tx_bf_rx_fb_nr_cnt;
894 u32 tx_bf_fb_cpl_cnt;
895 u32 tx_bf_fb_trig_cnt;
896
897 u32 tx_ampdu_cnt;
898 u32 tx_stop_q_empty_cnt;
899 u32 tx_mpdu_attempts_cnt;
900 u32 tx_mpdu_success_cnt;
901 u32 tx_pkt_ebf_cnt;
902 u32 tx_pkt_ibf_cnt;
903
904 u32 tx_rwp_fail_cnt;
905 u32 tx_rwp_need_cnt;
906
907 /* rx stats */
908 u32 rx_fifo_full_cnt;
909 u32 channel_idle_cnt;
910 u32 primary_cca_busy_time;
911 u32 secondary_cca_busy_time;
912 u32 primary_energy_detect_time;
913 u32 cck_mdrdy_time;
914 u32 ofdm_mdrdy_time;
915 u32 green_mdrdy_time;
916 u32 rx_vector_mismatch_cnt;
917 u32 rx_delimiter_fail_cnt;
918 u32 rx_mrdy_cnt;
919 u32 rx_len_mismatch_cnt;
920 u32 rx_mpdu_cnt;
921 u32 rx_ampdu_cnt;
922 u32 rx_ampdu_bytes_cnt;
923 u32 rx_ampdu_valid_subframe_cnt;
924 u32 rx_ampdu_valid_subframe_bytes_cnt;
925 u32 rx_pfdrop_cnt;
926 u32 rx_vec_queue_overflow_drop_cnt;
927 u32 rx_ba_cnt;
928
929 u32 tx_amsdu[8];
930 u32 tx_amsdu_cnt;
931
932 /* mcu_muru_stats */
933 u32 dl_cck_cnt;
934 u32 dl_ofdm_cnt;
935 u32 dl_htmix_cnt;
936 u32 dl_htgf_cnt;
937 u32 dl_vht_su_cnt;
938 u32 dl_vht_2mu_cnt;
939 u32 dl_vht_3mu_cnt;
940 u32 dl_vht_4mu_cnt;
941 u32 dl_he_su_cnt;
942 u32 dl_he_ext_su_cnt;
943 u32 dl_he_2ru_cnt;
944 u32 dl_he_2mu_cnt;
945 u32 dl_he_3ru_cnt;
946 u32 dl_he_3mu_cnt;
947 u32 dl_he_4ru_cnt;
948 u32 dl_he_4mu_cnt;
949 u32 dl_he_5to8ru_cnt;
950 u32 dl_he_9to16ru_cnt;
951 u32 dl_he_gtr16ru_cnt;
952
953 u32 ul_hetrig_su_cnt;
954 u32 ul_hetrig_2ru_cnt;
955 u32 ul_hetrig_3ru_cnt;
956 u32 ul_hetrig_4ru_cnt;
957 u32 ul_hetrig_5to8ru_cnt;
958 u32 ul_hetrig_9to16ru_cnt;
959 u32 ul_hetrig_gtr16ru_cnt;
960 u32 ul_hetrig_2mu_cnt;
961 u32 ul_hetrig_3mu_cnt;
962 u32 ul_hetrig_4mu_cnt;
963 };
964
965 struct mt76_power_limits {
966 s8 cck[4];
967 s8 ofdm[8];
968 s8 mcs[4][10];
969 s8 ru[7][12];
970 };
971
972 struct mt76_ethtool_worker_info {
973 u64 *data;
974 int idx;
975 int initial_stat_idx;
976 int worker_stat_count;
977 int sta_count;
978 };
979
980 #define CCK_RATE(_idx, _rate) { \
981 .bitrate = _rate, \
982 .flags = IEEE80211_RATE_SHORT_PREAMBLE, \
983 .hw_value = (MT_PHY_TYPE_CCK << 8) | (_idx), \
984 .hw_value_short = (MT_PHY_TYPE_CCK << 8) | (4 + _idx), \
985 }
986
987 #define OFDM_RATE(_idx, _rate) { \
988 .bitrate = _rate, \
989 .hw_value = (MT_PHY_TYPE_OFDM << 8) | (_idx), \
990 .hw_value_short = (MT_PHY_TYPE_OFDM << 8) | (_idx), \
991 }
992
993 extern struct ieee80211_rate mt76_rates[12];
994
995 #define __mt76_rr(dev, ...) (dev)->bus->rr((dev), __VA_ARGS__)
996 #define __mt76_wr(dev, ...) (dev)->bus->wr((dev), __VA_ARGS__)
997 #define __mt76_rmw(dev, ...) (dev)->bus->rmw((dev), __VA_ARGS__)
998 #define __mt76_wr_copy(dev, ...) (dev)->bus->write_copy((dev), __VA_ARGS__)
999 #define __mt76_rr_copy(dev, ...) (dev)->bus->read_copy((dev), __VA_ARGS__)
1000
1001 #define __mt76_set(dev, offset, val) __mt76_rmw(dev, offset, 0, val)
1002 #define __mt76_clear(dev, offset, val) __mt76_rmw(dev, offset, val, 0)
1003
1004 #define mt76_rr(dev, ...) (dev)->mt76.bus->rr(&((dev)->mt76), __VA_ARGS__)
1005 #define mt76_wr(dev, ...) (dev)->mt76.bus->wr(&((dev)->mt76), __VA_ARGS__)
1006 #define mt76_rmw(dev, ...) (dev)->mt76.bus->rmw(&((dev)->mt76), __VA_ARGS__)
1007 #define mt76_wr_copy(dev, ...) (dev)->mt76.bus->write_copy(&((dev)->mt76), __VA_ARGS__)
1008 #define mt76_rr_copy(dev, ...) (dev)->mt76.bus->read_copy(&((dev)->mt76), __VA_ARGS__)
1009 #define mt76_wr_rp(dev, ...) (dev)->mt76.bus->wr_rp(&((dev)->mt76), __VA_ARGS__)
1010 #define mt76_rd_rp(dev, ...) (dev)->mt76.bus->rd_rp(&((dev)->mt76), __VA_ARGS__)
1011
1012
1013 #define mt76_mcu_restart(dev, ...) (dev)->mt76.mcu_ops->mcu_restart(&((dev)->mt76))
1014
1015 #define mt76_set(dev, offset, val) mt76_rmw(dev, offset, 0, val)
1016 #define mt76_clear(dev, offset, val) mt76_rmw(dev, offset, val, 0)
1017
1018 #define mt76_get_field(_dev, _reg, _field) \
1019 FIELD_GET(_field, mt76_rr(dev, _reg))
1020
1021 #define mt76_rmw_field(_dev, _reg, _field, _val) \
1022 mt76_rmw(_dev, _reg, _field, FIELD_PREP(_field, _val))
1023
1024 #define __mt76_rmw_field(_dev, _reg, _field, _val) \
1025 __mt76_rmw(_dev, _reg, _field, FIELD_PREP(_field, _val))
1026
1027 #define mt76_hw(dev) (dev)->mphy.hw
1028
1029 bool __mt76_poll(struct mt76_dev *dev, u32 offset, u32 mask, u32 val,
1030 int timeout);
1031
1032 #define mt76_poll(dev, ...) __mt76_poll(&((dev)->mt76), __VA_ARGS__)
1033
1034 bool ____mt76_poll_msec(struct mt76_dev *dev, u32 offset, u32 mask, u32 val,
1035 int timeout, int kick);
1036 #define __mt76_poll_msec(...) ____mt76_poll_msec(__VA_ARGS__, 10)
1037 #define mt76_poll_msec(dev, ...) ____mt76_poll_msec(&((dev)->mt76), __VA_ARGS__, 10)
1038 #define mt76_poll_msec_tick(dev, ...) ____mt76_poll_msec(&((dev)->mt76), __VA_ARGS__)
1039
1040 void mt76_mmio_init(struct mt76_dev *dev, void __iomem *regs);
1041 void mt76_pci_disable_aspm(struct pci_dev *pdev);
1042
mt76_chip(struct mt76_dev * dev)1043 static inline u16 mt76_chip(struct mt76_dev *dev)
1044 {
1045 return dev->rev >> 16;
1046 }
1047
mt76_rev(struct mt76_dev * dev)1048 static inline u16 mt76_rev(struct mt76_dev *dev)
1049 {
1050 return dev->rev & 0xffff;
1051 }
1052
1053 #define mt76xx_chip(dev) mt76_chip(&((dev)->mt76))
1054 #define mt76xx_rev(dev) mt76_rev(&((dev)->mt76))
1055
1056 #define mt76_init_queues(dev, ...) (dev)->mt76.queue_ops->init(&((dev)->mt76), __VA_ARGS__)
1057 #define mt76_queue_alloc(dev, ...) (dev)->mt76.queue_ops->alloc(&((dev)->mt76), __VA_ARGS__)
1058 #define mt76_tx_queue_skb_raw(dev, ...) (dev)->mt76.queue_ops->tx_queue_skb_raw(&((dev)->mt76), __VA_ARGS__)
1059 #define mt76_tx_queue_skb(dev, ...) (dev)->mt76.queue_ops->tx_queue_skb(&((dev)->mt76), __VA_ARGS__)
1060 #define mt76_queue_rx_reset(dev, ...) (dev)->mt76.queue_ops->rx_reset(&((dev)->mt76), __VA_ARGS__)
1061 #define mt76_queue_tx_cleanup(dev, ...) (dev)->mt76.queue_ops->tx_cleanup(&((dev)->mt76), __VA_ARGS__)
1062 #define mt76_queue_rx_cleanup(dev, ...) (dev)->mt76.queue_ops->rx_cleanup(&((dev)->mt76), __VA_ARGS__)
1063 #define mt76_queue_kick(dev, ...) (dev)->mt76.queue_ops->kick(&((dev)->mt76), __VA_ARGS__)
1064 #define mt76_queue_reset(dev, ...) (dev)->mt76.queue_ops->reset_q(&((dev)->mt76), __VA_ARGS__)
1065
1066 #define mt76_for_each_q_rx(dev, i) \
1067 for (i = 0; i < ARRAY_SIZE((dev)->q_rx); i++) \
1068 if ((dev)->q_rx[i].ndesc)
1069
1070 struct mt76_dev *mt76_alloc_device(struct device *pdev, unsigned int size,
1071 const struct ieee80211_ops *ops,
1072 const struct mt76_driver_ops *drv_ops);
1073 int mt76_register_device(struct mt76_dev *dev, bool vht,
1074 struct ieee80211_rate *rates, int n_rates);
1075 void mt76_unregister_device(struct mt76_dev *dev);
1076 void mt76_free_device(struct mt76_dev *dev);
1077 void mt76_unregister_phy(struct mt76_phy *phy);
1078
1079 struct mt76_phy *mt76_alloc_phy(struct mt76_dev *dev, unsigned int size,
1080 const struct ieee80211_ops *ops,
1081 u8 band_idx);
1082 int mt76_register_phy(struct mt76_phy *phy, bool vht,
1083 struct ieee80211_rate *rates, int n_rates);
1084
1085 struct dentry *mt76_register_debugfs_fops(struct mt76_phy *phy,
1086 const struct file_operations *ops);
mt76_register_debugfs(struct mt76_dev * dev)1087 static inline struct dentry *mt76_register_debugfs(struct mt76_dev *dev)
1088 {
1089 return mt76_register_debugfs_fops(&dev->phy, NULL);
1090 }
1091
1092 int mt76_queues_read(struct seq_file *s, void *data);
1093 void mt76_seq_puts_array(struct seq_file *file, const char *str,
1094 s8 *val, int len);
1095
1096 int mt76_eeprom_init(struct mt76_dev *dev, int len);
1097 void mt76_eeprom_override(struct mt76_phy *phy);
1098 int mt76_get_of_eeprom(struct mt76_dev *dev, void *data, int offset, int len);
1099
1100 struct mt76_queue *
1101 mt76_init_queue(struct mt76_dev *dev, int qid, int idx, int n_desc,
1102 int ring_base, u32 flags);
1103 u16 mt76_calculate_default_rate(struct mt76_phy *phy,
1104 struct ieee80211_vif *vif, int rateidx);
mt76_init_tx_queue(struct mt76_phy * phy,int qid,int idx,int n_desc,int ring_base,u32 flags)1105 static inline int mt76_init_tx_queue(struct mt76_phy *phy, int qid, int idx,
1106 int n_desc, int ring_base, u32 flags)
1107 {
1108 struct mt76_queue *q;
1109
1110 q = mt76_init_queue(phy->dev, qid, idx, n_desc, ring_base, flags);
1111 if (IS_ERR(q))
1112 return PTR_ERR(q);
1113
1114 phy->q_tx[qid] = q;
1115
1116 return 0;
1117 }
1118
mt76_init_mcu_queue(struct mt76_dev * dev,int qid,int idx,int n_desc,int ring_base)1119 static inline int mt76_init_mcu_queue(struct mt76_dev *dev, int qid, int idx,
1120 int n_desc, int ring_base)
1121 {
1122 struct mt76_queue *q;
1123
1124 q = mt76_init_queue(dev, qid, idx, n_desc, ring_base, 0);
1125 if (IS_ERR(q))
1126 return PTR_ERR(q);
1127
1128 dev->q_mcu[qid] = q;
1129
1130 return 0;
1131 }
1132
1133 static inline struct mt76_phy *
mt76_dev_phy(struct mt76_dev * dev,u8 phy_idx)1134 mt76_dev_phy(struct mt76_dev *dev, u8 phy_idx)
1135 {
1136 if ((phy_idx == MT_BAND1 && dev->phys[phy_idx]) ||
1137 (phy_idx == MT_BAND2 && dev->phys[phy_idx]))
1138 return dev->phys[phy_idx];
1139
1140 return &dev->phy;
1141 }
1142
1143 static inline struct ieee80211_hw *
mt76_phy_hw(struct mt76_dev * dev,u8 phy_idx)1144 mt76_phy_hw(struct mt76_dev *dev, u8 phy_idx)
1145 {
1146 return mt76_dev_phy(dev, phy_idx)->hw;
1147 }
1148
1149 static inline u8 *
mt76_get_txwi_ptr(struct mt76_dev * dev,struct mt76_txwi_cache * t)1150 mt76_get_txwi_ptr(struct mt76_dev *dev, struct mt76_txwi_cache *t)
1151 {
1152 return (u8 *)t - dev->drv->txwi_size;
1153 }
1154
1155 /* increment with wrap-around */
mt76_incr(int val,int size)1156 static inline int mt76_incr(int val, int size)
1157 {
1158 return (val + 1) & (size - 1);
1159 }
1160
1161 /* decrement with wrap-around */
mt76_decr(int val,int size)1162 static inline int mt76_decr(int val, int size)
1163 {
1164 return (val - 1) & (size - 1);
1165 }
1166
1167 u8 mt76_ac_to_hwq(u8 ac);
1168
1169 static inline struct ieee80211_txq *
mtxq_to_txq(struct mt76_txq * mtxq)1170 mtxq_to_txq(struct mt76_txq *mtxq)
1171 {
1172 void *ptr = mtxq;
1173
1174 return container_of(ptr, struct ieee80211_txq, drv_priv);
1175 }
1176
1177 static inline struct ieee80211_sta *
wcid_to_sta(struct mt76_wcid * wcid)1178 wcid_to_sta(struct mt76_wcid *wcid)
1179 {
1180 void *ptr = wcid;
1181
1182 if (!wcid || !wcid->sta)
1183 return NULL;
1184
1185 return container_of(ptr, struct ieee80211_sta, drv_priv);
1186 }
1187
mt76_tx_skb_cb(struct sk_buff * skb)1188 static inline struct mt76_tx_cb *mt76_tx_skb_cb(struct sk_buff *skb)
1189 {
1190 BUILD_BUG_ON(sizeof(struct mt76_tx_cb) >
1191 sizeof(IEEE80211_SKB_CB(skb)->status.status_driver_data));
1192 return ((void *)IEEE80211_SKB_CB(skb)->status.status_driver_data);
1193 }
1194
mt76_skb_get_hdr(struct sk_buff * skb)1195 static inline void *mt76_skb_get_hdr(struct sk_buff *skb)
1196 {
1197 struct mt76_rx_status mstat;
1198 u8 *data = skb->data;
1199
1200 /* Alignment concerns */
1201 BUILD_BUG_ON(sizeof(struct ieee80211_radiotap_he) % 4);
1202 BUILD_BUG_ON(sizeof(struct ieee80211_radiotap_he_mu) % 4);
1203
1204 mstat = *((struct mt76_rx_status *)skb->cb);
1205
1206 if (mstat.flag & RX_FLAG_RADIOTAP_HE)
1207 data += sizeof(struct ieee80211_radiotap_he);
1208 if (mstat.flag & RX_FLAG_RADIOTAP_HE_MU)
1209 data += sizeof(struct ieee80211_radiotap_he_mu);
1210
1211 return data;
1212 }
1213
mt76_insert_hdr_pad(struct sk_buff * skb)1214 static inline void mt76_insert_hdr_pad(struct sk_buff *skb)
1215 {
1216 int len = ieee80211_get_hdrlen_from_skb(skb);
1217
1218 if (len % 4 == 0)
1219 return;
1220
1221 skb_push(skb, 2);
1222 memmove(skb->data, skb->data + 2, len);
1223
1224 skb->data[len] = 0;
1225 skb->data[len + 1] = 0;
1226 }
1227
mt76_is_skb_pktid(u8 pktid)1228 static inline bool mt76_is_skb_pktid(u8 pktid)
1229 {
1230 if (pktid & MT_PACKET_ID_HAS_RATE)
1231 return false;
1232
1233 return pktid >= MT_PACKET_ID_FIRST;
1234 }
1235
mt76_tx_power_nss_delta(u8 nss)1236 static inline u8 mt76_tx_power_nss_delta(u8 nss)
1237 {
1238 static const u8 nss_delta[4] = { 0, 6, 9, 12 };
1239 u8 idx = nss - 1;
1240
1241 return (idx < ARRAY_SIZE(nss_delta)) ? nss_delta[idx] : 0;
1242 }
1243
mt76_testmode_enabled(struct mt76_phy * phy)1244 static inline bool mt76_testmode_enabled(struct mt76_phy *phy)
1245 {
1246 #ifdef CONFIG_NL80211_TESTMODE
1247 return phy->test.state != MT76_TM_STATE_OFF;
1248 #else
1249 return false;
1250 #endif
1251 }
1252
mt76_is_testmode_skb(struct mt76_dev * dev,struct sk_buff * skb,struct ieee80211_hw ** hw)1253 static inline bool mt76_is_testmode_skb(struct mt76_dev *dev,
1254 struct sk_buff *skb,
1255 struct ieee80211_hw **hw)
1256 {
1257 #ifdef CONFIG_NL80211_TESTMODE
1258 int i;
1259
1260 for (i = 0; i < ARRAY_SIZE(dev->phys); i++) {
1261 struct mt76_phy *phy = dev->phys[i];
1262
1263 if (phy && skb == phy->test.tx_skb) {
1264 *hw = dev->phys[i]->hw;
1265 return true;
1266 }
1267 }
1268 return false;
1269 #else
1270 return false;
1271 #endif
1272 }
1273
1274 void mt76_rx(struct mt76_dev *dev, enum mt76_rxq_id q, struct sk_buff *skb);
1275 void mt76_tx(struct mt76_phy *dev, struct ieee80211_sta *sta,
1276 struct mt76_wcid *wcid, struct sk_buff *skb);
1277 void mt76_wake_tx_queue(struct ieee80211_hw *hw, struct ieee80211_txq *txq);
1278 void mt76_stop_tx_queues(struct mt76_phy *phy, struct ieee80211_sta *sta,
1279 bool send_bar);
1280 void mt76_tx_check_agg_ssn(struct ieee80211_sta *sta, struct sk_buff *skb);
1281 void mt76_txq_schedule(struct mt76_phy *phy, enum mt76_txq_id qid);
1282 void mt76_txq_schedule_all(struct mt76_phy *phy);
1283 void mt76_tx_worker_run(struct mt76_dev *dev);
1284 void mt76_tx_worker(struct mt76_worker *w);
1285 void mt76_release_buffered_frames(struct ieee80211_hw *hw,
1286 struct ieee80211_sta *sta,
1287 u16 tids, int nframes,
1288 enum ieee80211_frame_release_type reason,
1289 bool more_data);
1290 bool mt76_has_tx_pending(struct mt76_phy *phy);
1291 void mt76_set_channel(struct mt76_phy *phy);
1292 void mt76_update_survey(struct mt76_phy *phy);
1293 void mt76_update_survey_active_time(struct mt76_phy *phy, ktime_t time);
1294 int mt76_get_survey(struct ieee80211_hw *hw, int idx,
1295 struct survey_info *survey);
1296 int mt76_rx_signal(u8 chain_mask, s8 *chain_signal);
1297 void mt76_set_stream_caps(struct mt76_phy *phy, bool vht);
1298
1299 int mt76_rx_aggr_start(struct mt76_dev *dev, struct mt76_wcid *wcid, u8 tid,
1300 u16 ssn, u16 size);
1301 void mt76_rx_aggr_stop(struct mt76_dev *dev, struct mt76_wcid *wcid, u8 tid);
1302
1303 void mt76_wcid_key_setup(struct mt76_dev *dev, struct mt76_wcid *wcid,
1304 struct ieee80211_key_conf *key);
1305
1306 void mt76_tx_status_lock(struct mt76_dev *dev, struct sk_buff_head *list)
1307 __acquires(&dev->status_lock);
1308 void mt76_tx_status_unlock(struct mt76_dev *dev, struct sk_buff_head *list)
1309 __releases(&dev->status_lock);
1310
1311 int mt76_tx_status_skb_add(struct mt76_dev *dev, struct mt76_wcid *wcid,
1312 struct sk_buff *skb);
1313 struct sk_buff *mt76_tx_status_skb_get(struct mt76_dev *dev,
1314 struct mt76_wcid *wcid, int pktid,
1315 struct sk_buff_head *list);
1316 void mt76_tx_status_skb_done(struct mt76_dev *dev, struct sk_buff *skb,
1317 struct sk_buff_head *list);
1318 void __mt76_tx_complete_skb(struct mt76_dev *dev, u16 wcid, struct sk_buff *skb,
1319 struct list_head *free_list);
1320 static inline void
mt76_tx_complete_skb(struct mt76_dev * dev,u16 wcid,struct sk_buff * skb)1321 mt76_tx_complete_skb(struct mt76_dev *dev, u16 wcid, struct sk_buff *skb)
1322 {
1323 __mt76_tx_complete_skb(dev, wcid, skb, NULL);
1324 }
1325
1326 void mt76_tx_status_check(struct mt76_dev *dev, bool flush);
1327 int mt76_sta_state(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1328 struct ieee80211_sta *sta,
1329 enum ieee80211_sta_state old_state,
1330 enum ieee80211_sta_state new_state);
1331 void __mt76_sta_remove(struct mt76_dev *dev, struct ieee80211_vif *vif,
1332 struct ieee80211_sta *sta);
1333 void mt76_sta_pre_rcu_remove(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1334 struct ieee80211_sta *sta);
1335
1336 int mt76_get_min_avg_rssi(struct mt76_dev *dev, bool ext_phy);
1337
1338 int mt76_get_txpower(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1339 int *dbm);
1340 int mt76_init_sar_power(struct ieee80211_hw *hw,
1341 const struct cfg80211_sar_specs *sar);
1342 int mt76_get_sar_power(struct mt76_phy *phy,
1343 struct ieee80211_channel *chan,
1344 int power);
1345
1346 void mt76_csa_check(struct mt76_dev *dev);
1347 void mt76_csa_finish(struct mt76_dev *dev);
1348
1349 int mt76_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant);
1350 int mt76_set_tim(struct ieee80211_hw *hw, struct ieee80211_sta *sta, bool set);
1351 void mt76_insert_ccmp_hdr(struct sk_buff *skb, u8 key_id);
1352 int mt76_get_rate(struct mt76_dev *dev,
1353 struct ieee80211_supported_band *sband,
1354 int idx, bool cck);
1355 void mt76_sw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1356 const u8 *mac);
1357 void mt76_sw_scan_complete(struct ieee80211_hw *hw,
1358 struct ieee80211_vif *vif);
1359 enum mt76_dfs_state mt76_phy_dfs_state(struct mt76_phy *phy);
1360 int mt76_testmode_cmd(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1361 void *data, int len);
1362 int mt76_testmode_dump(struct ieee80211_hw *hw, struct sk_buff *skb,
1363 struct netlink_callback *cb, void *data, int len);
1364 int mt76_testmode_set_state(struct mt76_phy *phy, enum mt76_testmode_state state);
1365 int mt76_testmode_alloc_skb(struct mt76_phy *phy, u32 len);
1366
mt76_testmode_reset(struct mt76_phy * phy,bool disable)1367 static inline void mt76_testmode_reset(struct mt76_phy *phy, bool disable)
1368 {
1369 #ifdef CONFIG_NL80211_TESTMODE
1370 enum mt76_testmode_state state = MT76_TM_STATE_IDLE;
1371
1372 if (disable || phy->test.state == MT76_TM_STATE_OFF)
1373 state = MT76_TM_STATE_OFF;
1374
1375 mt76_testmode_set_state(phy, state);
1376 #endif
1377 }
1378
1379
1380 /* internal */
1381 static inline struct ieee80211_hw *
mt76_tx_status_get_hw(struct mt76_dev * dev,struct sk_buff * skb)1382 mt76_tx_status_get_hw(struct mt76_dev *dev, struct sk_buff *skb)
1383 {
1384 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1385 u8 phy_idx = (info->hw_queue & MT_TX_HW_QUEUE_PHY) >> 2;
1386 struct ieee80211_hw *hw = mt76_phy_hw(dev, phy_idx);
1387
1388 info->hw_queue &= ~MT_TX_HW_QUEUE_PHY;
1389
1390 return hw;
1391 }
1392
1393 void mt76_put_txwi(struct mt76_dev *dev, struct mt76_txwi_cache *t);
1394 void mt76_put_rxwi(struct mt76_dev *dev, struct mt76_txwi_cache *t);
1395 struct mt76_txwi_cache *mt76_get_rxwi(struct mt76_dev *dev);
1396 void mt76_free_pending_rxwi(struct mt76_dev *dev);
1397 void mt76_rx_complete(struct mt76_dev *dev, struct sk_buff_head *frames,
1398 struct napi_struct *napi);
1399 void mt76_rx_poll_complete(struct mt76_dev *dev, enum mt76_rxq_id q,
1400 struct napi_struct *napi);
1401 void mt76_rx_aggr_reorder(struct sk_buff *skb, struct sk_buff_head *frames);
1402 void mt76_testmode_tx_pending(struct mt76_phy *phy);
1403 void mt76_queue_tx_complete(struct mt76_dev *dev, struct mt76_queue *q,
1404 struct mt76_queue_entry *e);
1405
1406 /* usb */
mt76u_urb_error(struct urb * urb)1407 static inline bool mt76u_urb_error(struct urb *urb)
1408 {
1409 return urb->status &&
1410 urb->status != -ECONNRESET &&
1411 urb->status != -ESHUTDOWN &&
1412 urb->status != -ENOENT;
1413 }
1414
1415 /* Map hardware queues to usb endpoints */
q2ep(u8 qid)1416 static inline u8 q2ep(u8 qid)
1417 {
1418 /* TODO: take management packets to queue 5 */
1419 return qid + 1;
1420 }
1421
1422 static inline int
mt76u_bulk_msg(struct mt76_dev * dev,void * data,int len,int * actual_len,int timeout,int ep)1423 mt76u_bulk_msg(struct mt76_dev *dev, void *data, int len, int *actual_len,
1424 int timeout, int ep)
1425 {
1426 struct usb_interface *uintf = to_usb_interface(dev->dev);
1427 struct usb_device *udev = interface_to_usbdev(uintf);
1428 struct mt76_usb *usb = &dev->usb;
1429 unsigned int pipe;
1430
1431 if (actual_len)
1432 pipe = usb_rcvbulkpipe(udev, usb->in_ep[ep]);
1433 else
1434 pipe = usb_sndbulkpipe(udev, usb->out_ep[ep]);
1435
1436 return usb_bulk_msg(udev, pipe, data, len, actual_len, timeout);
1437 }
1438
1439 void mt76_ethtool_page_pool_stats(struct mt76_dev *dev, u64 *data, int *index);
1440 void mt76_ethtool_worker(struct mt76_ethtool_worker_info *wi,
1441 struct mt76_sta_stats *stats, bool eht);
1442 int mt76_skb_adjust_pad(struct sk_buff *skb, int pad);
1443 int __mt76u_vendor_request(struct mt76_dev *dev, u8 req, u8 req_type,
1444 u16 val, u16 offset, void *buf, size_t len);
1445 int mt76u_vendor_request(struct mt76_dev *dev, u8 req,
1446 u8 req_type, u16 val, u16 offset,
1447 void *buf, size_t len);
1448 void mt76u_single_wr(struct mt76_dev *dev, const u8 req,
1449 const u16 offset, const u32 val);
1450 void mt76u_read_copy(struct mt76_dev *dev, u32 offset,
1451 void *data, int len);
1452 u32 ___mt76u_rr(struct mt76_dev *dev, u8 req, u8 req_type, u32 addr);
1453 void ___mt76u_wr(struct mt76_dev *dev, u8 req, u8 req_type,
1454 u32 addr, u32 val);
1455 int __mt76u_init(struct mt76_dev *dev, struct usb_interface *intf,
1456 struct mt76_bus_ops *ops);
1457 int mt76u_init(struct mt76_dev *dev, struct usb_interface *intf);
1458 int mt76u_alloc_mcu_queue(struct mt76_dev *dev);
1459 int mt76u_alloc_queues(struct mt76_dev *dev);
1460 void mt76u_stop_tx(struct mt76_dev *dev);
1461 void mt76u_stop_rx(struct mt76_dev *dev);
1462 int mt76u_resume_rx(struct mt76_dev *dev);
1463 void mt76u_queues_deinit(struct mt76_dev *dev);
1464
1465 int mt76s_init(struct mt76_dev *dev, struct sdio_func *func,
1466 const struct mt76_bus_ops *bus_ops);
1467 int mt76s_alloc_rx_queue(struct mt76_dev *dev, enum mt76_rxq_id qid);
1468 int mt76s_alloc_tx(struct mt76_dev *dev);
1469 void mt76s_deinit(struct mt76_dev *dev);
1470 void mt76s_sdio_irq(struct sdio_func *func);
1471 void mt76s_txrx_worker(struct mt76_sdio *sdio);
1472 bool mt76s_txqs_empty(struct mt76_dev *dev);
1473 int mt76s_hw_init(struct mt76_dev *dev, struct sdio_func *func,
1474 int hw_ver);
1475 u32 mt76s_rr(struct mt76_dev *dev, u32 offset);
1476 void mt76s_wr(struct mt76_dev *dev, u32 offset, u32 val);
1477 u32 mt76s_rmw(struct mt76_dev *dev, u32 offset, u32 mask, u32 val);
1478 u32 mt76s_read_pcr(struct mt76_dev *dev);
1479 void mt76s_write_copy(struct mt76_dev *dev, u32 offset,
1480 const void *data, int len);
1481 void mt76s_read_copy(struct mt76_dev *dev, u32 offset,
1482 void *data, int len);
1483 int mt76s_wr_rp(struct mt76_dev *dev, u32 base,
1484 const struct mt76_reg_pair *data,
1485 int len);
1486 int mt76s_rd_rp(struct mt76_dev *dev, u32 base,
1487 struct mt76_reg_pair *data, int len);
1488
1489 struct sk_buff *
1490 __mt76_mcu_msg_alloc(struct mt76_dev *dev, const void *data,
1491 int len, int data_len, gfp_t gfp);
1492 static inline struct sk_buff *
mt76_mcu_msg_alloc(struct mt76_dev * dev,const void * data,int data_len)1493 mt76_mcu_msg_alloc(struct mt76_dev *dev, const void *data,
1494 int data_len)
1495 {
1496 return __mt76_mcu_msg_alloc(dev, data, data_len, data_len, GFP_KERNEL);
1497 }
1498
1499 void mt76_mcu_rx_event(struct mt76_dev *dev, struct sk_buff *skb);
1500 struct sk_buff *mt76_mcu_get_response(struct mt76_dev *dev,
1501 unsigned long expires);
1502 int mt76_mcu_send_and_get_msg(struct mt76_dev *dev, int cmd, const void *data,
1503 int len, bool wait_resp, struct sk_buff **ret);
1504 int mt76_mcu_skb_send_and_get_msg(struct mt76_dev *dev, struct sk_buff *skb,
1505 int cmd, bool wait_resp, struct sk_buff **ret);
1506 int __mt76_mcu_send_firmware(struct mt76_dev *dev, int cmd, const void *data,
1507 int len, int max_len);
1508 static inline int
mt76_mcu_send_firmware(struct mt76_dev * dev,int cmd,const void * data,int len)1509 mt76_mcu_send_firmware(struct mt76_dev *dev, int cmd, const void *data,
1510 int len)
1511 {
1512 int max_len = 4096 - dev->mcu_ops->headroom;
1513
1514 return __mt76_mcu_send_firmware(dev, cmd, data, len, max_len);
1515 }
1516
1517 static inline int
mt76_mcu_send_msg(struct mt76_dev * dev,int cmd,const void * data,int len,bool wait_resp)1518 mt76_mcu_send_msg(struct mt76_dev *dev, int cmd, const void *data, int len,
1519 bool wait_resp)
1520 {
1521 return mt76_mcu_send_and_get_msg(dev, cmd, data, len, wait_resp, NULL);
1522 }
1523
1524 static inline int
mt76_mcu_skb_send_msg(struct mt76_dev * dev,struct sk_buff * skb,int cmd,bool wait_resp)1525 mt76_mcu_skb_send_msg(struct mt76_dev *dev, struct sk_buff *skb, int cmd,
1526 bool wait_resp)
1527 {
1528 return mt76_mcu_skb_send_and_get_msg(dev, skb, cmd, wait_resp, NULL);
1529 }
1530
1531 void mt76_set_irq_mask(struct mt76_dev *dev, u32 addr, u32 clear, u32 set);
1532
1533 s8 mt76_get_rate_power_limits(struct mt76_phy *phy,
1534 struct ieee80211_channel *chan,
1535 struct mt76_power_limits *dest,
1536 s8 target_power);
1537
mt76_queue_is_wed_rx(struct mt76_queue * q)1538 static inline bool mt76_queue_is_wed_rx(struct mt76_queue *q)
1539 {
1540 return (q->flags & MT_QFLAG_WED) &&
1541 FIELD_GET(MT_QFLAG_WED_TYPE, q->flags) == MT76_WED_Q_RX;
1542 }
1543
1544 struct mt76_txwi_cache *
1545 mt76_token_release(struct mt76_dev *dev, int token, bool *wake);
1546 int mt76_token_consume(struct mt76_dev *dev, struct mt76_txwi_cache **ptxwi);
1547 void __mt76_set_tx_blocked(struct mt76_dev *dev, bool blocked);
1548 struct mt76_txwi_cache *mt76_rx_token_release(struct mt76_dev *dev, int token);
1549 int mt76_rx_token_consume(struct mt76_dev *dev, void *ptr,
1550 struct mt76_txwi_cache *r, dma_addr_t phys);
1551 int mt76_create_page_pool(struct mt76_dev *dev, struct mt76_queue *q);
mt76_put_page_pool_buf(void * buf,bool allow_direct)1552 static inline void mt76_put_page_pool_buf(void *buf, bool allow_direct)
1553 {
1554 struct page *page = virt_to_head_page(buf);
1555
1556 page_pool_put_full_page(page->pp, page, allow_direct);
1557 }
1558
1559 static inline void *
mt76_get_page_pool_buf(struct mt76_queue * q,u32 * offset,u32 size)1560 mt76_get_page_pool_buf(struct mt76_queue *q, u32 *offset, u32 size)
1561 {
1562 struct page *page;
1563
1564 page = page_pool_dev_alloc_frag(q->page_pool, offset, size);
1565 if (!page)
1566 return NULL;
1567
1568 return page_address(page) + *offset;
1569 }
1570
mt76_set_tx_blocked(struct mt76_dev * dev,bool blocked)1571 static inline void mt76_set_tx_blocked(struct mt76_dev *dev, bool blocked)
1572 {
1573 spin_lock_bh(&dev->token_lock);
1574 __mt76_set_tx_blocked(dev, blocked);
1575 spin_unlock_bh(&dev->token_lock);
1576 }
1577
1578 static inline int
mt76_token_get(struct mt76_dev * dev,struct mt76_txwi_cache ** ptxwi)1579 mt76_token_get(struct mt76_dev *dev, struct mt76_txwi_cache **ptxwi)
1580 {
1581 int token;
1582
1583 spin_lock_bh(&dev->token_lock);
1584 token = idr_alloc(&dev->token, *ptxwi, 0, dev->token_size, GFP_ATOMIC);
1585 spin_unlock_bh(&dev->token_lock);
1586
1587 return token;
1588 }
1589
1590 static inline struct mt76_txwi_cache *
mt76_token_put(struct mt76_dev * dev,int token)1591 mt76_token_put(struct mt76_dev *dev, int token)
1592 {
1593 struct mt76_txwi_cache *txwi;
1594
1595 spin_lock_bh(&dev->token_lock);
1596 txwi = idr_remove(&dev->token, token);
1597 spin_unlock_bh(&dev->token_lock);
1598
1599 return txwi;
1600 }
1601
mt76_packet_id_init(struct mt76_wcid * wcid)1602 static inline void mt76_packet_id_init(struct mt76_wcid *wcid)
1603 {
1604 INIT_LIST_HEAD(&wcid->list);
1605 idr_init(&wcid->pktid);
1606 }
1607
1608 static inline void
mt76_packet_id_flush(struct mt76_dev * dev,struct mt76_wcid * wcid)1609 mt76_packet_id_flush(struct mt76_dev *dev, struct mt76_wcid *wcid)
1610 {
1611 struct sk_buff_head list;
1612
1613 mt76_tx_status_lock(dev, &list);
1614 mt76_tx_status_skb_get(dev, wcid, -1, &list);
1615 mt76_tx_status_unlock(dev, &list);
1616
1617 idr_destroy(&wcid->pktid);
1618 }
1619
1620 #endif
1621