1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  *  Driver for Zarlink DVB-T MT352 demodulator
4  *
5  *  Written by Holger Waechtler <holger@qanu.de>
6  *	 and Daniel Mack <daniel@qanu.de>
7  *
8  *  AVerMedia AVerTV DVB-T 771 support by
9  *       Wolfram Joost <dbox2@frokaschwei.de>
10  *
11  *  Support for Samsung TDTC9251DH01C(M) tuner
12  *  Copyright (C) 2004 Antonio Mancuso <antonio.mancuso@digitaltelevision.it>
13  *                     Amauri  Celani  <acelani@essegi.net>
14  *
15  *  DVICO FusionHDTV DVB-T1 and DVICO FusionHDTV DVB-T Lite support by
16  *       Christopher Pascoe <c.pascoe@itee.uq.edu.au>
17  */
18 
19 #include <linux/kernel.h>
20 #include <linux/module.h>
21 #include <linux/init.h>
22 #include <linux/delay.h>
23 #include <linux/string.h>
24 #include <linux/slab.h>
25 
26 #include <media/dvb_frontend.h>
27 #include "mt352_priv.h"
28 #include "mt352.h"
29 
30 struct mt352_state {
31 	struct i2c_adapter* i2c;
32 	struct dvb_frontend frontend;
33 
34 	/* configuration settings */
35 	struct mt352_config config;
36 };
37 
38 static int debug;
39 #define dprintk(args...) \
40 	do { \
41 		if (debug) printk(KERN_DEBUG "mt352: " args); \
42 	} while (0)
43 
mt352_single_write(struct dvb_frontend * fe,u8 reg,u8 val)44 static int mt352_single_write(struct dvb_frontend *fe, u8 reg, u8 val)
45 {
46 	struct mt352_state* state = fe->demodulator_priv;
47 	u8 buf[2] = { reg, val };
48 	struct i2c_msg msg = { .addr = state->config.demod_address, .flags = 0,
49 			       .buf = buf, .len = 2 };
50 	int err = i2c_transfer(state->i2c, &msg, 1);
51 	if (err != 1) {
52 		printk("mt352_write() to reg %x failed (err = %d)!\n", reg, err);
53 		return err;
54 	}
55 	return 0;
56 }
57 
_mt352_write(struct dvb_frontend * fe,const u8 ibuf[],int ilen)58 static int _mt352_write(struct dvb_frontend* fe, const u8 ibuf[], int ilen)
59 {
60 	int err,i;
61 	for (i=0; i < ilen-1; i++)
62 		if ((err = mt352_single_write(fe,ibuf[0]+i,ibuf[i+1])))
63 			return err;
64 
65 	return 0;
66 }
67 
mt352_read_register(struct mt352_state * state,u8 reg)68 static int mt352_read_register(struct mt352_state* state, u8 reg)
69 {
70 	int ret;
71 	u8 b0 [] = { reg };
72 	u8 b1 [] = { 0 };
73 	struct i2c_msg msg [] = { { .addr = state->config.demod_address,
74 				    .flags = 0,
75 				    .buf = b0, .len = 1 },
76 				  { .addr = state->config.demod_address,
77 				    .flags = I2C_M_RD,
78 				    .buf = b1, .len = 1 } };
79 
80 	ret = i2c_transfer(state->i2c, msg, 2);
81 
82 	if (ret != 2) {
83 		printk("%s: readreg error (reg=%d, ret==%i)\n",
84 		       __func__, reg, ret);
85 		return ret;
86 	}
87 
88 	return b1[0];
89 }
90 
mt352_sleep(struct dvb_frontend * fe)91 static int mt352_sleep(struct dvb_frontend* fe)
92 {
93 	static u8 mt352_softdown[] = { CLOCK_CTL, 0x20, 0x08 };
94 
95 	_mt352_write(fe, mt352_softdown, sizeof(mt352_softdown));
96 	return 0;
97 }
98 
mt352_calc_nominal_rate(struct mt352_state * state,u32 bandwidth,unsigned char * buf)99 static void mt352_calc_nominal_rate(struct mt352_state* state,
100 				    u32 bandwidth,
101 				    unsigned char *buf)
102 {
103 	u32 adc_clock = 20480; /* 20.340 MHz */
104 	u32 bw,value;
105 
106 	switch (bandwidth) {
107 	case 6000000:
108 		bw = 6;
109 		break;
110 	case 7000000:
111 		bw = 7;
112 		break;
113 	case 8000000:
114 	default:
115 		bw = 8;
116 		break;
117 	}
118 	if (state->config.adc_clock)
119 		adc_clock = state->config.adc_clock;
120 
121 	value = 64 * bw * (1<<16) / (7 * 8);
122 	value = value * 1000 / adc_clock;
123 	dprintk("%s: bw %d, adc_clock %d => 0x%x\n",
124 		__func__, bw, adc_clock, value);
125 	buf[0] = msb(value);
126 	buf[1] = lsb(value);
127 }
128 
mt352_calc_input_freq(struct mt352_state * state,unsigned char * buf)129 static void mt352_calc_input_freq(struct mt352_state* state,
130 				  unsigned char *buf)
131 {
132 	int adc_clock = 20480; /* 20.480000 MHz */
133 	int if2       = 36167; /* 36.166667 MHz */
134 	int ife,value;
135 
136 	if (state->config.adc_clock)
137 		adc_clock = state->config.adc_clock;
138 	if (state->config.if2)
139 		if2 = state->config.if2;
140 
141 	if (adc_clock >= if2 * 2)
142 		ife = if2;
143 	else {
144 		ife = adc_clock - (if2 % adc_clock);
145 		if (ife > adc_clock / 2)
146 			ife = adc_clock - ife;
147 	}
148 	value = -16374 * ife / adc_clock;
149 	dprintk("%s: if2 %d, ife %d, adc_clock %d => %d / 0x%x\n",
150 		__func__, if2, ife, adc_clock, value, value & 0x3fff);
151 	buf[0] = msb(value);
152 	buf[1] = lsb(value);
153 }
154 
mt352_set_parameters(struct dvb_frontend * fe)155 static int mt352_set_parameters(struct dvb_frontend *fe)
156 {
157 	struct dtv_frontend_properties *op = &fe->dtv_property_cache;
158 	struct mt352_state* state = fe->demodulator_priv;
159 	unsigned char buf[13];
160 	static unsigned char tuner_go[] = { 0x5d, 0x01 };
161 	static unsigned char fsm_go[]   = { 0x5e, 0x01 };
162 	unsigned int tps = 0;
163 
164 	switch (op->code_rate_HP) {
165 		case FEC_2_3:
166 			tps |= (1 << 7);
167 			break;
168 		case FEC_3_4:
169 			tps |= (2 << 7);
170 			break;
171 		case FEC_5_6:
172 			tps |= (3 << 7);
173 			break;
174 		case FEC_7_8:
175 			tps |= (4 << 7);
176 			break;
177 		case FEC_1_2:
178 		case FEC_AUTO:
179 			break;
180 		default:
181 			return -EINVAL;
182 	}
183 
184 	switch (op->code_rate_LP) {
185 		case FEC_2_3:
186 			tps |= (1 << 4);
187 			break;
188 		case FEC_3_4:
189 			tps |= (2 << 4);
190 			break;
191 		case FEC_5_6:
192 			tps |= (3 << 4);
193 			break;
194 		case FEC_7_8:
195 			tps |= (4 << 4);
196 			break;
197 		case FEC_1_2:
198 		case FEC_AUTO:
199 			break;
200 		case FEC_NONE:
201 			if (op->hierarchy == HIERARCHY_AUTO ||
202 			    op->hierarchy == HIERARCHY_NONE)
203 				break;
204 			fallthrough;
205 		default:
206 			return -EINVAL;
207 	}
208 
209 	switch (op->modulation) {
210 		case QPSK:
211 			break;
212 		case QAM_AUTO:
213 		case QAM_16:
214 			tps |= (1 << 13);
215 			break;
216 		case QAM_64:
217 			tps |= (2 << 13);
218 			break;
219 		default:
220 			return -EINVAL;
221 	}
222 
223 	switch (op->transmission_mode) {
224 		case TRANSMISSION_MODE_2K:
225 		case TRANSMISSION_MODE_AUTO:
226 			break;
227 		case TRANSMISSION_MODE_8K:
228 			tps |= (1 << 0);
229 			break;
230 		default:
231 			return -EINVAL;
232 	}
233 
234 	switch (op->guard_interval) {
235 		case GUARD_INTERVAL_1_32:
236 		case GUARD_INTERVAL_AUTO:
237 			break;
238 		case GUARD_INTERVAL_1_16:
239 			tps |= (1 << 2);
240 			break;
241 		case GUARD_INTERVAL_1_8:
242 			tps |= (2 << 2);
243 			break;
244 		case GUARD_INTERVAL_1_4:
245 			tps |= (3 << 2);
246 			break;
247 		default:
248 			return -EINVAL;
249 	}
250 
251 	switch (op->hierarchy) {
252 		case HIERARCHY_AUTO:
253 		case HIERARCHY_NONE:
254 			break;
255 		case HIERARCHY_1:
256 			tps |= (1 << 10);
257 			break;
258 		case HIERARCHY_2:
259 			tps |= (2 << 10);
260 			break;
261 		case HIERARCHY_4:
262 			tps |= (3 << 10);
263 			break;
264 		default:
265 			return -EINVAL;
266 	}
267 
268 
269 	buf[0] = TPS_GIVEN_1; /* TPS_GIVEN_1 and following registers */
270 
271 	buf[1] = msb(tps);      /* TPS_GIVEN_(1|0) */
272 	buf[2] = lsb(tps);
273 
274 	buf[3] = 0x50;  // old
275 //	buf[3] = 0xf4;  // pinnacle
276 
277 	mt352_calc_nominal_rate(state, op->bandwidth_hz, buf+4);
278 	mt352_calc_input_freq(state, buf+6);
279 
280 	if (state->config.no_tuner) {
281 		if (fe->ops.tuner_ops.set_params) {
282 			fe->ops.tuner_ops.set_params(fe);
283 			if (fe->ops.i2c_gate_ctrl)
284 				fe->ops.i2c_gate_ctrl(fe, 0);
285 		}
286 
287 		_mt352_write(fe, buf, 8);
288 		_mt352_write(fe, fsm_go, 2);
289 	} else {
290 		if (fe->ops.tuner_ops.calc_regs) {
291 			fe->ops.tuner_ops.calc_regs(fe, buf+8, 5);
292 			buf[8] <<= 1;
293 			_mt352_write(fe, buf, sizeof(buf));
294 			_mt352_write(fe, tuner_go, 2);
295 		}
296 	}
297 
298 	return 0;
299 }
300 
mt352_get_parameters(struct dvb_frontend * fe,struct dtv_frontend_properties * op)301 static int mt352_get_parameters(struct dvb_frontend* fe,
302 				struct dtv_frontend_properties *op)
303 {
304 	struct mt352_state* state = fe->demodulator_priv;
305 	u16 tps;
306 	u16 div;
307 	u8 trl;
308 	static const u8 tps_fec_to_api[8] =
309 	{
310 		FEC_1_2,
311 		FEC_2_3,
312 		FEC_3_4,
313 		FEC_5_6,
314 		FEC_7_8,
315 		FEC_AUTO,
316 		FEC_AUTO,
317 		FEC_AUTO
318 	};
319 
320 	if ( (mt352_read_register(state,0x00) & 0xC0) != 0xC0 )
321 		return -EINVAL;
322 
323 	/* Use TPS_RECEIVED-registers, not the TPS_CURRENT-registers because
324 	 * the mt352 sometimes works with the wrong parameters
325 	 */
326 	tps = (mt352_read_register(state, TPS_RECEIVED_1) << 8) | mt352_read_register(state, TPS_RECEIVED_0);
327 	div = (mt352_read_register(state, CHAN_START_1) << 8) | mt352_read_register(state, CHAN_START_0);
328 	trl = mt352_read_register(state, TRL_NOMINAL_RATE_1);
329 
330 	op->code_rate_HP = tps_fec_to_api[(tps >> 7) & 7];
331 	op->code_rate_LP = tps_fec_to_api[(tps >> 4) & 7];
332 
333 	switch ( (tps >> 13) & 3)
334 	{
335 		case 0:
336 			op->modulation = QPSK;
337 			break;
338 		case 1:
339 			op->modulation = QAM_16;
340 			break;
341 		case 2:
342 			op->modulation = QAM_64;
343 			break;
344 		default:
345 			op->modulation = QAM_AUTO;
346 			break;
347 	}
348 
349 	op->transmission_mode = (tps & 0x01) ? TRANSMISSION_MODE_8K : TRANSMISSION_MODE_2K;
350 
351 	switch ( (tps >> 2) & 3)
352 	{
353 		case 0:
354 			op->guard_interval = GUARD_INTERVAL_1_32;
355 			break;
356 		case 1:
357 			op->guard_interval = GUARD_INTERVAL_1_16;
358 			break;
359 		case 2:
360 			op->guard_interval = GUARD_INTERVAL_1_8;
361 			break;
362 		case 3:
363 			op->guard_interval = GUARD_INTERVAL_1_4;
364 			break;
365 		default:
366 			op->guard_interval = GUARD_INTERVAL_AUTO;
367 			break;
368 	}
369 
370 	switch ( (tps >> 10) & 7)
371 	{
372 		case 0:
373 			op->hierarchy = HIERARCHY_NONE;
374 			break;
375 		case 1:
376 			op->hierarchy = HIERARCHY_1;
377 			break;
378 		case 2:
379 			op->hierarchy = HIERARCHY_2;
380 			break;
381 		case 3:
382 			op->hierarchy = HIERARCHY_4;
383 			break;
384 		default:
385 			op->hierarchy = HIERARCHY_AUTO;
386 			break;
387 	}
388 
389 	op->frequency = (500 * (div - IF_FREQUENCYx6)) / 3 * 1000;
390 
391 	if (trl == 0x72)
392 		op->bandwidth_hz = 8000000;
393 	else if (trl == 0x64)
394 		op->bandwidth_hz = 7000000;
395 	else
396 		op->bandwidth_hz = 6000000;
397 
398 
399 	if (mt352_read_register(state, STATUS_2) & 0x02)
400 		op->inversion = INVERSION_OFF;
401 	else
402 		op->inversion = INVERSION_ON;
403 
404 	return 0;
405 }
406 
mt352_read_status(struct dvb_frontend * fe,enum fe_status * status)407 static int mt352_read_status(struct dvb_frontend *fe, enum fe_status *status)
408 {
409 	struct mt352_state* state = fe->demodulator_priv;
410 	int s0, s1, s3;
411 
412 	/* FIXME:
413 	 *
414 	 * The MT352 design manual from Zarlink states (page 46-47):
415 	 *
416 	 * Notes about the TUNER_GO register:
417 	 *
418 	 * If the Read_Tuner_Byte (bit-1) is activated, then the tuner status
419 	 * byte is copied from the tuner to the STATUS_3 register and
420 	 * completion of the read operation is indicated by bit-5 of the
421 	 * INTERRUPT_3 register.
422 	 */
423 
424 	if ((s0 = mt352_read_register(state, STATUS_0)) < 0)
425 		return -EREMOTEIO;
426 	if ((s1 = mt352_read_register(state, STATUS_1)) < 0)
427 		return -EREMOTEIO;
428 	if ((s3 = mt352_read_register(state, STATUS_3)) < 0)
429 		return -EREMOTEIO;
430 
431 	*status = 0;
432 	if (s0 & (1 << 4))
433 		*status |= FE_HAS_CARRIER;
434 	if (s0 & (1 << 1))
435 		*status |= FE_HAS_VITERBI;
436 	if (s0 & (1 << 5))
437 		*status |= FE_HAS_LOCK;
438 	if (s1 & (1 << 1))
439 		*status |= FE_HAS_SYNC;
440 	if (s3 & (1 << 6))
441 		*status |= FE_HAS_SIGNAL;
442 
443 	if ((*status & (FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC)) !=
444 		      (FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC))
445 		*status &= ~FE_HAS_LOCK;
446 
447 	return 0;
448 }
449 
mt352_read_ber(struct dvb_frontend * fe,u32 * ber)450 static int mt352_read_ber(struct dvb_frontend* fe, u32* ber)
451 {
452 	struct mt352_state* state = fe->demodulator_priv;
453 
454 	*ber = (mt352_read_register (state, RS_ERR_CNT_2) << 16) |
455 	       (mt352_read_register (state, RS_ERR_CNT_1) << 8) |
456 	       (mt352_read_register (state, RS_ERR_CNT_0));
457 
458 	return 0;
459 }
460 
mt352_read_signal_strength(struct dvb_frontend * fe,u16 * strength)461 static int mt352_read_signal_strength(struct dvb_frontend* fe, u16* strength)
462 {
463 	struct mt352_state* state = fe->demodulator_priv;
464 
465 	/* align the 12 bit AGC gain with the most significant bits */
466 	u16 signal = ((mt352_read_register(state, AGC_GAIN_1) & 0x0f) << 12) |
467 		(mt352_read_register(state, AGC_GAIN_0) << 4);
468 
469 	/* inverse of gain is signal strength */
470 	*strength = ~signal;
471 	return 0;
472 }
473 
mt352_read_snr(struct dvb_frontend * fe,u16 * snr)474 static int mt352_read_snr(struct dvb_frontend* fe, u16* snr)
475 {
476 	struct mt352_state* state = fe->demodulator_priv;
477 
478 	u8 _snr = mt352_read_register (state, SNR);
479 	*snr = (_snr << 8) | _snr;
480 
481 	return 0;
482 }
483 
mt352_read_ucblocks(struct dvb_frontend * fe,u32 * ucblocks)484 static int mt352_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
485 {
486 	struct mt352_state* state = fe->demodulator_priv;
487 
488 	*ucblocks = (mt352_read_register (state,  RS_UBC_1) << 8) |
489 		    (mt352_read_register (state,  RS_UBC_0));
490 
491 	return 0;
492 }
493 
mt352_get_tune_settings(struct dvb_frontend * fe,struct dvb_frontend_tune_settings * fe_tune_settings)494 static int mt352_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings* fe_tune_settings)
495 {
496 	fe_tune_settings->min_delay_ms = 800;
497 	fe_tune_settings->step_size = 0;
498 	fe_tune_settings->max_drift = 0;
499 
500 	return 0;
501 }
502 
mt352_init(struct dvb_frontend * fe)503 static int mt352_init(struct dvb_frontend* fe)
504 {
505 	struct mt352_state* state = fe->demodulator_priv;
506 
507 	static u8 mt352_reset_attach [] = { RESET, 0xC0 };
508 
509 	dprintk("%s: hello\n",__func__);
510 
511 	if ((mt352_read_register(state, CLOCK_CTL) & 0x10) == 0 ||
512 	    (mt352_read_register(state, CONFIG) & 0x20) == 0) {
513 
514 		/* Do a "hard" reset */
515 		_mt352_write(fe, mt352_reset_attach, sizeof(mt352_reset_attach));
516 		return state->config.demod_init(fe);
517 	}
518 
519 	return 0;
520 }
521 
mt352_release(struct dvb_frontend * fe)522 static void mt352_release(struct dvb_frontend* fe)
523 {
524 	struct mt352_state* state = fe->demodulator_priv;
525 	kfree(state);
526 }
527 
528 static const struct dvb_frontend_ops mt352_ops;
529 
mt352_attach(const struct mt352_config * config,struct i2c_adapter * i2c)530 struct dvb_frontend* mt352_attach(const struct mt352_config* config,
531 				  struct i2c_adapter* i2c)
532 {
533 	struct mt352_state* state = NULL;
534 
535 	/* allocate memory for the internal state */
536 	state = kzalloc(sizeof(struct mt352_state), GFP_KERNEL);
537 	if (state == NULL) goto error;
538 
539 	/* setup the state */
540 	state->i2c = i2c;
541 	memcpy(&state->config,config,sizeof(struct mt352_config));
542 
543 	/* check if the demod is there */
544 	if (mt352_read_register(state, CHIP_ID) != ID_MT352) goto error;
545 
546 	/* create dvb_frontend */
547 	memcpy(&state->frontend.ops, &mt352_ops, sizeof(struct dvb_frontend_ops));
548 	state->frontend.demodulator_priv = state;
549 	return &state->frontend;
550 
551 error:
552 	kfree(state);
553 	return NULL;
554 }
555 
556 static const struct dvb_frontend_ops mt352_ops = {
557 	.delsys = { SYS_DVBT },
558 	.info = {
559 		.name			= "Zarlink MT352 DVB-T",
560 		.frequency_min_hz	= 174 * MHz,
561 		.frequency_max_hz	= 862 * MHz,
562 		.frequency_stepsize_hz	= 166667,
563 		.caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
564 			FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 |
565 			FE_CAN_FEC_AUTO |
566 			FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
567 			FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO |
568 			FE_CAN_HIERARCHY_AUTO | FE_CAN_RECOVER |
569 			FE_CAN_MUTE_TS
570 	},
571 
572 	.release = mt352_release,
573 
574 	.init = mt352_init,
575 	.sleep = mt352_sleep,
576 	.write = _mt352_write,
577 
578 	.set_frontend = mt352_set_parameters,
579 	.get_frontend = mt352_get_parameters,
580 	.get_tune_settings = mt352_get_tune_settings,
581 
582 	.read_status = mt352_read_status,
583 	.read_ber = mt352_read_ber,
584 	.read_signal_strength = mt352_read_signal_strength,
585 	.read_snr = mt352_read_snr,
586 	.read_ucblocks = mt352_read_ucblocks,
587 };
588 
589 module_param(debug, int, 0644);
590 MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
591 
592 MODULE_DESCRIPTION("Zarlink MT352 DVB-T Demodulator driver");
593 MODULE_AUTHOR("Holger Waechtler, Daniel Mack, Antonio Mancuso");
594 MODULE_LICENSE("GPL");
595 
596 EXPORT_SYMBOL_GPL(mt352_attach);
597