1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2006,2009-2010 Freescale Semiconductor, Inc.
4 * Jeff Brown
5 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
6 */
7
8 #include <common.h>
9 #include <watchdog.h>
10 #include <command.h>
11 #include <asm/cache.h>
12 #include <asm/mmu.h>
13 #include <mpc86xx.h>
14 #include <asm/fsl_law.h>
15 #include <asm/ppc.h>
16
17 DECLARE_GLOBAL_DATA_PTR;
18
19 /*
20 * Default board reset function
21 */
22 static void
__board_reset(void)23 __board_reset(void)
24 {
25 /* Do nothing */
26 }
27 void board_reset(void) __attribute__((weak, alias("__board_reset")));
28
29
30 int
checkcpu(void)31 checkcpu(void)
32 {
33 sys_info_t sysinfo;
34 uint pvr, svr;
35 uint major, minor;
36 char buf1[32], buf2[32];
37 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
38 volatile ccsr_gur_t *gur = &immap->im_gur;
39 struct cpu_type *cpu;
40 uint msscr0 = mfspr(MSSCR0);
41
42 svr = get_svr();
43 major = SVR_MAJ(svr);
44 minor = SVR_MIN(svr);
45
46 if (cpu_numcores() > 1) {
47 #ifndef CONFIG_MP
48 puts("Unicore software on multiprocessor system!!\n"
49 "To enable mutlticore build define CONFIG_MP\n");
50 #endif
51 }
52 puts("CPU: ");
53
54 cpu = gd->arch.cpu;
55
56 puts(cpu->name);
57
58 printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
59 puts("Core: ");
60
61 pvr = get_pvr();
62 major = PVR_E600_MAJ(pvr);
63 minor = PVR_E600_MIN(pvr);
64
65 printf("e600 Core %d", (msscr0 & 0x20) ? 1 : 0);
66 if (gur->pordevsr & MPC86xx_PORDEVSR_CORE1TE)
67 puts("\n Core1Translation Enabled");
68 debug(" (MSSCR0=%x, PORDEVSR=%x)", msscr0, gur->pordevsr);
69
70 printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
71
72 get_sys_info(&sysinfo);
73
74 puts("Clock Configuration:\n");
75 printf(" CPU:%-4s MHz, ", strmhz(buf1, sysinfo.freq_processor));
76 printf("MPX:%-4s MHz\n", strmhz(buf1, sysinfo.freq_systembus));
77 printf(" DDR:%-4s MHz (%s MT/s data rate), ",
78 strmhz(buf1, sysinfo.freq_systembus / 2),
79 strmhz(buf2, sysinfo.freq_systembus));
80
81 if (sysinfo.freq_localbus > LCRR_CLKDIV) {
82 printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freq_localbus));
83 } else {
84 printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n",
85 sysinfo.freq_localbus);
86 }
87
88 puts("L1: D-cache 32 KiB enabled\n");
89 puts(" I-cache 32 KiB enabled\n");
90
91 puts("L2: ");
92 if (get_l2cr() & 0x80000000) {
93 #if defined(CONFIG_ARCH_MPC8610)
94 puts("256");
95 #elif defined(CONFIG_ARCH_MPC8641)
96 puts("512");
97 #endif
98 puts(" KiB enabled\n");
99 } else {
100 puts("Disabled\n");
101 }
102
103 return 0;
104 }
105
106
do_reset(cmd_tbl_t * cmdtp,int flag,int argc,char * const argv[])107 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
108 {
109 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
110 volatile ccsr_gur_t *gur = &immap->im_gur;
111
112 /* Attempt board-specific reset */
113 board_reset();
114
115 /* Next try asserting HRESET_REQ */
116 out_be32(&gur->rstcr, MPC86xx_RSTCR_HRST_REQ);
117
118 while (1)
119 ;
120
121 return 1;
122 }
123
124
125 /*
126 * Get timebase clock frequency
127 */
128 unsigned long
get_tbclk(void)129 get_tbclk(void)
130 {
131 sys_info_t sys_info;
132
133 get_sys_info(&sys_info);
134 return (sys_info.freq_systembus + 3L) / 4L;
135 }
136
137
138 #if defined(CONFIG_WATCHDOG)
139 void
watchdog_reset(void)140 watchdog_reset(void)
141 {
142 #if defined(CONFIG_ARCH_MPC8610)
143 /*
144 * This actually feed the hard enabled watchdog.
145 */
146 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
147 volatile ccsr_wdt_t *wdt = &immap->im_wdt;
148 volatile ccsr_gur_t *gur = &immap->im_gur;
149 u32 tmp = gur->pordevsr;
150
151 if (tmp & 0x4000) {
152 wdt->swsrr = 0x556c;
153 wdt->swsrr = 0xaa39;
154 }
155 #endif
156 }
157 #endif /* CONFIG_WATCHDOG */
158
159 /*
160 * Print out the state of various machine registers.
161 * Currently prints out LAWs, BR0/OR0, and BATs
162 */
print_reginfo(void)163 void print_reginfo(void)
164 {
165 print_bats();
166 print_laws();
167 print_lbc_regs();
168 }
169
170 /*
171 * Set the DDR BATs to reflect the actual size of DDR.
172 *
173 * dram_size is the actual size of DDR, in bytes
174 *
175 * Note: we assume that CONFIG_MAX_MEM_MAPPED is 2G or smaller as we only
176 * are using a single BAT to cover DDR.
177 *
178 * If this is not true, (e.g. CONFIG_MAX_MEM_MAPPED is 2GB but HID0_XBSEN
179 * is not defined) then we might have a situation where U-Boot will attempt
180 * to relocated itself outside of the region mapped by DBAT0.
181 * This will cause a machine check.
182 *
183 * Currently we are limited to power of two sized DDR since we only use a
184 * single bat. If a non-power of two size is used that is less than
185 * CONFIG_MAX_MEM_MAPPED u-boot will crash.
186 *
187 */
setup_ddr_bat(phys_addr_t dram_size)188 void setup_ddr_bat(phys_addr_t dram_size)
189 {
190 unsigned long batu, bl;
191
192 bl = TO_BATU_BL(min(dram_size, CONFIG_MAX_MEM_MAPPED));
193
194 if (BATU_SIZE(bl) != dram_size) {
195 u64 sz = (u64)dram_size - BATU_SIZE(bl);
196 print_size(sz, " left unmapped\n");
197 }
198
199 batu = bl | BATU_VS | BATU_VP;
200 write_bat(DBAT0, batu, CONFIG_SYS_DBAT0L);
201 write_bat(IBAT0, batu, CONFIG_SYS_IBAT0L);
202 }
203