1 /*
2 * QEMU KVM support
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
6 *
7 * Authors:
8 * Anthony Liguori <aliguori@us.ibm.com>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
12 *
13 */
14
15 #include "qemu/osdep.h"
16 #include "qapi/qapi-events-run-state.h"
17 #include "qapi/error.h"
18 #include "qapi/visitor.h"
19 #include <math.h>
20 #include <sys/ioctl.h>
21 #include <sys/utsname.h>
22 #include <sys/syscall.h>
23 #include <sys/resource.h>
24 #include <sys/time.h>
25
26 #include <linux/kvm.h>
27 #include <linux/kvm_para.h>
28 #include "standard-headers/asm-x86/kvm_para.h"
29 #include "hw/xen/interface/arch-x86/cpuid.h"
30
31 #include "cpu.h"
32 #include "host-cpu.h"
33 #include "vmsr_energy.h"
34 #include "system/system.h"
35 #include "system/hw_accel.h"
36 #include "system/kvm_int.h"
37 #include "system/runstate.h"
38 #include "kvm_i386.h"
39 #include "../confidential-guest.h"
40 #include "sev.h"
41 #include "tdx.h"
42 #include "xen-emu.h"
43 #include "hyperv.h"
44 #include "hyperv-proto.h"
45
46 #include "gdbstub/enums.h"
47 #include "qemu/host-utils.h"
48 #include "qemu/main-loop.h"
49 #include "qemu/ratelimit.h"
50 #include "qemu/config-file.h"
51 #include "qemu/error-report.h"
52 #include "qemu/memalign.h"
53 #include "hw/i386/x86.h"
54 #include "hw/i386/kvm/xen_evtchn.h"
55 #include "hw/i386/pc.h"
56 #include "hw/i386/apic.h"
57 #include "hw/i386/apic_internal.h"
58 #include "hw/i386/apic-msidef.h"
59 #include "hw/i386/intel_iommu.h"
60 #include "hw/i386/topology.h"
61 #include "hw/i386/x86-iommu.h"
62 #include "hw/i386/e820_memory_layout.h"
63
64 #include "hw/xen/xen.h"
65
66 #include "hw/pci/pci.h"
67 #include "hw/pci/msi.h"
68 #include "hw/pci/msix.h"
69 #include "migration/blocker.h"
70 #include "exec/memattrs.h"
71 #include "exec/target_page.h"
72 #include "trace.h"
73
74 #include CONFIG_DEVICES
75
76 //#define DEBUG_KVM
77
78 #ifdef DEBUG_KVM
79 #define DPRINTF(fmt, ...) \
80 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
81 #else
82 #define DPRINTF(fmt, ...) \
83 do { } while (0)
84 #endif
85
86 /*
87 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
88 * In order to use vm86 mode, an EPT identity map and a TSS are needed.
89 * Since these must be part of guest physical memory, we need to allocate
90 * them, both by setting their start addresses in the kernel and by
91 * creating a corresponding e820 entry. We need 4 pages before the BIOS,
92 * so this value allows up to 16M BIOSes.
93 */
94 #define KVM_IDENTITY_BASE 0xfeffc000
95
96 /* From arch/x86/kvm/lapic.h */
97 #define KVM_APIC_BUS_CYCLE_NS 1
98 #define KVM_APIC_BUS_FREQUENCY (1000000000ULL / KVM_APIC_BUS_CYCLE_NS)
99
100 /* A 4096-byte buffer can hold the 8-byte kvm_msrs header, plus
101 * 255 kvm_msr_entry structs */
102 #define MSR_BUF_SIZE 4096
103
104 typedef bool QEMURDMSRHandler(X86CPU *cpu, uint32_t msr, uint64_t *val);
105 typedef bool QEMUWRMSRHandler(X86CPU *cpu, uint32_t msr, uint64_t val);
106 typedef struct {
107 uint32_t msr;
108 QEMURDMSRHandler *rdmsr;
109 QEMUWRMSRHandler *wrmsr;
110 } KVMMSRHandlers;
111
112 static void kvm_init_msrs(X86CPU *cpu);
113 static int kvm_filter_msr(KVMState *s, uint32_t msr, QEMURDMSRHandler *rdmsr,
114 QEMUWRMSRHandler *wrmsr);
115
116 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
117 KVM_CAP_INFO(SET_TSS_ADDR),
118 KVM_CAP_INFO(EXT_CPUID),
119 KVM_CAP_INFO(MP_STATE),
120 KVM_CAP_INFO(SIGNAL_MSI),
121 KVM_CAP_INFO(IRQ_ROUTING),
122 KVM_CAP_INFO(DEBUGREGS),
123 KVM_CAP_INFO(XSAVE),
124 KVM_CAP_INFO(VCPU_EVENTS),
125 KVM_CAP_INFO(X86_ROBUST_SINGLESTEP),
126 KVM_CAP_INFO(MCE),
127 KVM_CAP_INFO(ADJUST_CLOCK),
128 KVM_CAP_INFO(SET_IDENTITY_MAP_ADDR),
129 KVM_CAP_LAST_INFO
130 };
131
132 static bool has_msr_star;
133 static bool has_msr_hsave_pa;
134 static bool has_msr_tsc_aux;
135 static bool has_msr_tsc_adjust;
136 static bool has_msr_tsc_deadline;
137 static bool has_msr_feature_control;
138 static bool has_msr_misc_enable;
139 static bool has_msr_smbase;
140 static bool has_msr_bndcfgs;
141 static int lm_capable_kernel;
142 static bool has_msr_hv_hypercall;
143 static bool has_msr_hv_crash;
144 static bool has_msr_hv_reset;
145 static bool has_msr_hv_vpindex;
146 static bool hv_vpindex_settable;
147 static bool has_msr_hv_runtime;
148 static bool has_msr_hv_synic;
149 static bool has_msr_hv_stimer;
150 static bool has_msr_hv_frequencies;
151 static bool has_msr_hv_reenlightenment;
152 static bool has_msr_hv_syndbg_options;
153 static bool has_msr_xss;
154 static bool has_msr_umwait;
155 static bool has_msr_spec_ctrl;
156 static bool has_tsc_scale_msr;
157 static bool has_msr_tsx_ctrl;
158 static bool has_msr_virt_ssbd;
159 static bool has_msr_smi_count;
160 static bool has_msr_arch_capabs;
161 static bool has_msr_core_capabs;
162 static bool has_msr_vmx_vmfunc;
163 static bool has_msr_ucode_rev;
164 static bool has_msr_vmx_procbased_ctls2;
165 static bool has_msr_perf_capabs;
166 static bool has_msr_pkrs;
167 static bool has_msr_hwcr;
168
169 static uint32_t has_architectural_pmu_version;
170 static uint32_t num_architectural_pmu_gp_counters;
171 static uint32_t num_architectural_pmu_fixed_counters;
172
173 static int has_xsave2;
174 static int has_xcrs;
175 static int has_sregs2;
176 static int has_exception_payload;
177 static int has_triple_fault_event;
178
179 static bool has_msr_mcg_ext_ctl;
180
181 static struct kvm_cpuid2 *cpuid_cache;
182 static struct kvm_cpuid2 *hv_cpuid_cache;
183 static struct kvm_msr_list *kvm_feature_msrs;
184
185 static KVMMSRHandlers msr_handlers[KVM_MSR_FILTER_MAX_RANGES];
186
187 #define BUS_LOCK_SLICE_TIME 1000000000ULL /* ns */
188 static RateLimit bus_lock_ratelimit_ctrl;
189 static int kvm_get_one_msr(X86CPU *cpu, int index, uint64_t *value);
190
191 static const char *vm_type_name[] = {
192 [KVM_X86_DEFAULT_VM] = "default",
193 [KVM_X86_SEV_VM] = "SEV",
194 [KVM_X86_SEV_ES_VM] = "SEV-ES",
195 [KVM_X86_SNP_VM] = "SEV-SNP",
196 [KVM_X86_TDX_VM] = "TDX",
197 };
198
kvm_is_vm_type_supported(int type)199 bool kvm_is_vm_type_supported(int type)
200 {
201 uint32_t machine_types;
202
203 /*
204 * old KVM doesn't support KVM_CAP_VM_TYPES but KVM_X86_DEFAULT_VM
205 * is always supported
206 */
207 if (type == KVM_X86_DEFAULT_VM) {
208 return true;
209 }
210
211 machine_types = kvm_check_extension(KVM_STATE(current_machine->accelerator),
212 KVM_CAP_VM_TYPES);
213 return !!(machine_types & BIT(type));
214 }
215
kvm_get_vm_type(MachineState * ms)216 int kvm_get_vm_type(MachineState *ms)
217 {
218 int kvm_type = KVM_X86_DEFAULT_VM;
219
220 if (ms->cgs) {
221 if (!object_dynamic_cast(OBJECT(ms->cgs), TYPE_X86_CONFIDENTIAL_GUEST)) {
222 error_report("configuration type %s not supported for x86 guests",
223 object_get_typename(OBJECT(ms->cgs)));
224 exit(1);
225 }
226 kvm_type = x86_confidential_guest_kvm_type(
227 X86_CONFIDENTIAL_GUEST(ms->cgs));
228 }
229
230 if (!kvm_is_vm_type_supported(kvm_type)) {
231 error_report("vm-type %s not supported by KVM", vm_type_name[kvm_type]);
232 exit(1);
233 }
234
235 return kvm_type;
236 }
237
kvm_enable_hypercall(uint64_t enable_mask)238 bool kvm_enable_hypercall(uint64_t enable_mask)
239 {
240 KVMState *s = KVM_STATE(current_accel());
241
242 return !kvm_vm_enable_cap(s, KVM_CAP_EXIT_HYPERCALL, 0, enable_mask);
243 }
244
kvm_has_smm(void)245 bool kvm_has_smm(void)
246 {
247 return kvm_vm_check_extension(kvm_state, KVM_CAP_X86_SMM);
248 }
249
kvm_has_adjust_clock_stable(void)250 bool kvm_has_adjust_clock_stable(void)
251 {
252 int ret = kvm_check_extension(kvm_state, KVM_CAP_ADJUST_CLOCK);
253
254 return (ret & KVM_CLOCK_TSC_STABLE);
255 }
256
kvm_has_exception_payload(void)257 bool kvm_has_exception_payload(void)
258 {
259 return has_exception_payload;
260 }
261
kvm_x2apic_api_set_flags(uint64_t flags)262 static bool kvm_x2apic_api_set_flags(uint64_t flags)
263 {
264 KVMState *s = KVM_STATE(current_accel());
265
266 return !kvm_vm_enable_cap(s, KVM_CAP_X2APIC_API, 0, flags);
267 }
268
269 #define MEMORIZE(fn, _result) \
270 ({ \
271 static bool _memorized; \
272 \
273 if (_memorized) { \
274 return _result; \
275 } \
276 _memorized = true; \
277 _result = fn; \
278 })
279
280 static bool has_x2apic_api;
281
kvm_has_x2apic_api(void)282 bool kvm_has_x2apic_api(void)
283 {
284 return has_x2apic_api;
285 }
286
kvm_enable_x2apic(void)287 bool kvm_enable_x2apic(void)
288 {
289 return MEMORIZE(
290 kvm_x2apic_api_set_flags(KVM_X2APIC_API_USE_32BIT_IDS |
291 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK),
292 has_x2apic_api);
293 }
294
kvm_hv_vpindex_settable(void)295 bool kvm_hv_vpindex_settable(void)
296 {
297 return hv_vpindex_settable;
298 }
299
kvm_get_tsc(CPUState * cs)300 static int kvm_get_tsc(CPUState *cs)
301 {
302 X86CPU *cpu = X86_CPU(cs);
303 CPUX86State *env = &cpu->env;
304 uint64_t value;
305 int ret;
306
307 if (env->tsc_valid) {
308 return 0;
309 }
310
311 env->tsc_valid = !runstate_is_running();
312
313 ret = kvm_get_one_msr(cpu, MSR_IA32_TSC, &value);
314 if (ret < 0) {
315 return ret;
316 }
317
318 env->tsc = value;
319 return 0;
320 }
321
do_kvm_synchronize_tsc(CPUState * cpu,run_on_cpu_data arg)322 static inline void do_kvm_synchronize_tsc(CPUState *cpu, run_on_cpu_data arg)
323 {
324 kvm_get_tsc(cpu);
325 }
326
kvm_synchronize_all_tsc(void)327 void kvm_synchronize_all_tsc(void)
328 {
329 CPUState *cpu;
330
331 if (kvm_enabled() && !is_tdx_vm()) {
332 CPU_FOREACH(cpu) {
333 run_on_cpu(cpu, do_kvm_synchronize_tsc, RUN_ON_CPU_NULL);
334 }
335 }
336 }
337
try_get_cpuid(KVMState * s,int max)338 static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
339 {
340 struct kvm_cpuid2 *cpuid;
341 int r, size;
342
343 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
344 cpuid = g_malloc0(size);
345 cpuid->nent = max;
346 r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
347 if (r == 0 && cpuid->nent >= max) {
348 r = -E2BIG;
349 }
350 if (r < 0) {
351 if (r == -E2BIG) {
352 g_free(cpuid);
353 return NULL;
354 } else {
355 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
356 strerror(-r));
357 exit(1);
358 }
359 }
360 return cpuid;
361 }
362
363 /* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
364 * for all entries.
365 */
get_supported_cpuid(KVMState * s)366 static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s)
367 {
368 struct kvm_cpuid2 *cpuid;
369 int max = 1;
370
371 if (cpuid_cache != NULL) {
372 return cpuid_cache;
373 }
374 while ((cpuid = try_get_cpuid(s, max)) == NULL) {
375 max *= 2;
376 }
377 cpuid_cache = cpuid;
378 return cpuid;
379 }
380
host_tsx_broken(void)381 static bool host_tsx_broken(void)
382 {
383 int family, model, stepping;\
384 char vendor[CPUID_VENDOR_SZ + 1];
385
386 host_cpu_vendor_fms(vendor, &family, &model, &stepping);
387
388 /* Check if we are running on a Haswell host known to have broken TSX */
389 return !strcmp(vendor, CPUID_VENDOR_INTEL) &&
390 (family == 6) &&
391 ((model == 63 && stepping < 4) ||
392 model == 60 || model == 69 || model == 70);
393 }
394
395 /* Returns the value for a specific register on the cpuid entry
396 */
cpuid_entry_get_reg(struct kvm_cpuid_entry2 * entry,int reg)397 uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg)
398 {
399 uint32_t ret = 0;
400 switch (reg) {
401 case R_EAX:
402 ret = entry->eax;
403 break;
404 case R_EBX:
405 ret = entry->ebx;
406 break;
407 case R_ECX:
408 ret = entry->ecx;
409 break;
410 case R_EDX:
411 ret = entry->edx;
412 break;
413 }
414 return ret;
415 }
416
417 /* Find matching entry for function/index on kvm_cpuid2 struct
418 */
cpuid_find_entry(struct kvm_cpuid2 * cpuid,uint32_t function,uint32_t index)419 struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid,
420 uint32_t function,
421 uint32_t index)
422 {
423 int i;
424 for (i = 0; i < cpuid->nent; ++i) {
425 if (cpuid->entries[i].function == function &&
426 cpuid->entries[i].index == index) {
427 return &cpuid->entries[i];
428 }
429 }
430 /* not found: */
431 return NULL;
432 }
433
kvm_arch_get_supported_cpuid(KVMState * s,uint32_t function,uint32_t index,int reg)434 uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
435 uint32_t index, int reg)
436 {
437 struct kvm_cpuid2 *cpuid;
438 uint32_t ret = 0;
439 uint32_t cpuid_1_edx, unused;
440 uint64_t bitmask;
441
442 cpuid = get_supported_cpuid(s);
443
444 struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index);
445 if (entry) {
446 ret = cpuid_entry_get_reg(entry, reg);
447 }
448
449 /* Fixups for the data returned by KVM, below */
450
451 if (function == 1 && reg == R_EDX) {
452 /* KVM before 2.6.30 misreports the following features */
453 ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
454 /* KVM never reports CPUID_HT but QEMU can support when vcpus > 1 */
455 ret |= CPUID_HT;
456 } else if (function == 1 && reg == R_ECX) {
457 /* We can set the hypervisor flag, even if KVM does not return it on
458 * GET_SUPPORTED_CPUID
459 */
460 ret |= CPUID_EXT_HYPERVISOR;
461 /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
462 * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
463 * and the irqchip is in the kernel.
464 */
465 if (kvm_irqchip_in_kernel() &&
466 kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
467 ret |= CPUID_EXT_TSC_DEADLINE_TIMER;
468 }
469
470 /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
471 * without the in-kernel irqchip
472 */
473 if (!kvm_irqchip_in_kernel()) {
474 ret &= ~CPUID_EXT_X2APIC;
475 }
476
477 if (enable_cpu_pm) {
478 int disable_exits = kvm_check_extension(s,
479 KVM_CAP_X86_DISABLE_EXITS);
480
481 if (disable_exits & KVM_X86_DISABLE_EXITS_MWAIT) {
482 ret |= CPUID_EXT_MONITOR;
483 }
484 }
485 } else if (function == 6 && reg == R_EAX) {
486 ret |= CPUID_6_EAX_ARAT; /* safe to allow because of emulated APIC */
487 } else if (function == 7 && index == 0 && reg == R_EBX) {
488 /* Not new instructions, just an optimization. */
489 uint32_t ebx;
490 host_cpuid(7, 0, &unused, &ebx, &unused, &unused);
491 ret |= ebx & CPUID_7_0_EBX_ERMS;
492
493 if (host_tsx_broken()) {
494 ret &= ~(CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_HLE);
495 }
496 } else if (function == 7 && index == 0 && reg == R_EDX) {
497 /* Not new instructions, just an optimization. */
498 uint32_t edx;
499 host_cpuid(7, 0, &unused, &unused, &unused, &edx);
500 ret |= edx & CPUID_7_0_EDX_FSRM;
501
502 /*
503 * Linux v4.17-v4.20 incorrectly return ARCH_CAPABILITIES on SVM hosts.
504 * We can detect the bug by checking if MSR_IA32_ARCH_CAPABILITIES is
505 * returned by KVM_GET_MSR_INDEX_LIST.
506 *
507 * But also, because Windows does not like ARCH_CAPABILITIES on AMD
508 * mcahines at all, do not show the fake ARCH_CAPABILITIES MSR that
509 * KVM sets up.
510 */
511 if (!has_msr_arch_capabs || !(edx & CPUID_7_0_EDX_ARCH_CAPABILITIES)) {
512 ret &= ~CPUID_7_0_EDX_ARCH_CAPABILITIES;
513 }
514 } else if (function == 7 && index == 1 && reg == R_EAX) {
515 /* Not new instructions, just an optimization. */
516 uint32_t eax;
517 host_cpuid(7, 1, &eax, &unused, &unused, &unused);
518 ret |= eax & (CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_FSRC);
519 } else if (function == 7 && index == 2 && reg == R_EDX) {
520 uint32_t edx;
521 host_cpuid(7, 2, &unused, &unused, &unused, &edx);
522 ret |= edx & CPUID_7_2_EDX_MCDT_NO;
523 } else if (function == 0xd && index == 0 &&
524 (reg == R_EAX || reg == R_EDX)) {
525 /*
526 * The value returned by KVM_GET_SUPPORTED_CPUID does not include
527 * features that still have to be enabled with the arch_prctl
528 * system call. QEMU needs the full value, which is retrieved
529 * with KVM_GET_DEVICE_ATTR.
530 */
531 struct kvm_device_attr attr = {
532 .group = 0,
533 .attr = KVM_X86_XCOMP_GUEST_SUPP,
534 .addr = (unsigned long) &bitmask
535 };
536
537 bool sys_attr = kvm_check_extension(s, KVM_CAP_SYS_ATTRIBUTES);
538 if (!sys_attr) {
539 return ret;
540 }
541
542 int rc = kvm_ioctl(s, KVM_GET_DEVICE_ATTR, &attr);
543 if (rc < 0) {
544 if (rc != -ENXIO) {
545 warn_report("KVM_GET_DEVICE_ATTR(0, KVM_X86_XCOMP_GUEST_SUPP) "
546 "error: %d", rc);
547 }
548 return ret;
549 }
550 ret = (reg == R_EAX) ? bitmask : bitmask >> 32;
551 } else if (function == 0x80000001 && reg == R_ECX) {
552 /*
553 * It's safe to enable TOPOEXT even if it's not returned by
554 * GET_SUPPORTED_CPUID. Unconditionally enabling TOPOEXT here allows
555 * us to keep CPU models including TOPOEXT runnable on older kernels.
556 */
557 ret |= CPUID_EXT3_TOPOEXT;
558 } else if (function == 0x80000001 && reg == R_EDX) {
559 /* On Intel, kvm returns cpuid according to the Intel spec,
560 * so add missing bits according to the AMD spec:
561 */
562 cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
563 ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES;
564 } else if (function == 0x80000007 && reg == R_EBX) {
565 ret |= CPUID_8000_0007_EBX_OVERFLOW_RECOV | CPUID_8000_0007_EBX_SUCCOR;
566 } else if (function == KVM_CPUID_FEATURES && reg == R_EAX) {
567 /* kvm_pv_unhalt is reported by GET_SUPPORTED_CPUID, but it can't
568 * be enabled without the in-kernel irqchip
569 */
570 if (!kvm_irqchip_in_kernel()) {
571 ret &= ~CPUID_KVM_PV_UNHALT;
572 }
573 if (kvm_irqchip_is_split()) {
574 ret |= CPUID_KVM_MSI_EXT_DEST_ID;
575 }
576 } else if (function == KVM_CPUID_FEATURES && reg == R_EDX) {
577 ret |= CPUID_KVM_HINTS_REALTIME;
578 }
579
580 if (current_machine->cgs) {
581 ret = x86_confidential_guest_adjust_cpuid_features(
582 X86_CONFIDENTIAL_GUEST(current_machine->cgs),
583 function, index, reg, ret);
584 }
585 return ret;
586 }
587
kvm_arch_get_supported_msr_feature(KVMState * s,uint32_t index)588 uint64_t kvm_arch_get_supported_msr_feature(KVMState *s, uint32_t index)
589 {
590 struct {
591 struct kvm_msrs info;
592 struct kvm_msr_entry entries[1];
593 } msr_data = {};
594 uint64_t value;
595 uint32_t ret, can_be_one, must_be_one;
596
597 if (kvm_feature_msrs == NULL) { /* Host doesn't support feature MSRs */
598 return 0;
599 }
600
601 /* Check if requested MSR is supported feature MSR */
602 int i;
603 for (i = 0; i < kvm_feature_msrs->nmsrs; i++)
604 if (kvm_feature_msrs->indices[i] == index) {
605 break;
606 }
607 if (i == kvm_feature_msrs->nmsrs) {
608 return 0; /* if the feature MSR is not supported, simply return 0 */
609 }
610
611 msr_data.info.nmsrs = 1;
612 msr_data.entries[0].index = index;
613
614 ret = kvm_ioctl(s, KVM_GET_MSRS, &msr_data);
615 if (ret != 1) {
616 error_report("KVM get MSR (index=0x%x) feature failed, %s",
617 index, strerror(-ret));
618 exit(1);
619 }
620
621 value = msr_data.entries[0].data;
622 switch (index) {
623 case MSR_IA32_VMX_PROCBASED_CTLS2:
624 if (!has_msr_vmx_procbased_ctls2) {
625 /* KVM forgot to add these bits for some time, do this ourselves. */
626 if (kvm_arch_get_supported_cpuid(s, 0xD, 1, R_ECX) &
627 CPUID_XSAVE_XSAVES) {
628 value |= (uint64_t)VMX_SECONDARY_EXEC_XSAVES << 32;
629 }
630 if (kvm_arch_get_supported_cpuid(s, 1, 0, R_ECX) &
631 CPUID_EXT_RDRAND) {
632 value |= (uint64_t)VMX_SECONDARY_EXEC_RDRAND_EXITING << 32;
633 }
634 if (kvm_arch_get_supported_cpuid(s, 7, 0, R_EBX) &
635 CPUID_7_0_EBX_INVPCID) {
636 value |= (uint64_t)VMX_SECONDARY_EXEC_ENABLE_INVPCID << 32;
637 }
638 if (kvm_arch_get_supported_cpuid(s, 7, 0, R_EBX) &
639 CPUID_7_0_EBX_RDSEED) {
640 value |= (uint64_t)VMX_SECONDARY_EXEC_RDSEED_EXITING << 32;
641 }
642 if (kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_EDX) &
643 CPUID_EXT2_RDTSCP) {
644 value |= (uint64_t)VMX_SECONDARY_EXEC_RDTSCP << 32;
645 }
646 }
647 /* fall through */
648 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
649 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
650 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
651 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
652 /*
653 * Return true for bits that can be one, but do not have to be one.
654 * The SDM tells us which bits could have a "must be one" setting,
655 * so we can do the opposite transformation in make_vmx_msr_value.
656 */
657 must_be_one = (uint32_t)value;
658 can_be_one = (uint32_t)(value >> 32);
659 return can_be_one & ~must_be_one;
660
661 default:
662 return value;
663 }
664 }
665
kvm_get_mce_cap_supported(KVMState * s,uint64_t * mce_cap,int * max_banks)666 static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
667 int *max_banks)
668 {
669 *max_banks = kvm_check_extension(s, KVM_CAP_MCE);
670 return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
671 }
672
kvm_mce_inject(X86CPU * cpu,hwaddr paddr,int code)673 static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code)
674 {
675 CPUState *cs = CPU(cpu);
676 CPUX86State *env = &cpu->env;
677 uint64_t status = MCI_STATUS_VAL | MCI_STATUS_EN | MCI_STATUS_MISCV |
678 MCI_STATUS_ADDRV;
679 uint64_t mcg_status = MCG_STATUS_MCIP | MCG_STATUS_RIPV;
680 int flags = 0;
681
682 if (!IS_AMD_CPU(env)) {
683 status |= MCI_STATUS_S | MCI_STATUS_UC;
684 if (code == BUS_MCEERR_AR) {
685 status |= MCI_STATUS_AR | 0x134;
686 mcg_status |= MCG_STATUS_EIPV;
687 } else {
688 status |= 0xc0;
689 }
690 } else {
691 if (code == BUS_MCEERR_AR) {
692 status |= MCI_STATUS_UC | MCI_STATUS_POISON;
693 mcg_status |= MCG_STATUS_EIPV;
694 } else {
695 /* Setting the POISON bit for deferred errors indicates to the
696 * guest kernel that the address provided by the MCE is valid
697 * and usable which will ensure that the guest kernel will send
698 * a SIGBUS_AO signal to the guest process. This allows for
699 * more desirable behavior in the case that the guest process
700 * with poisoned memory has set the MCE_KILL_EARLY prctl flag
701 * which indicates that the process would prefer to handle or
702 * shutdown due to the poisoned memory condition before the
703 * memory has been accessed.
704 *
705 * While the POISON bit would not be set in a deferred error
706 * sent from hardware, the bit is not meaningful for deferred
707 * errors and can be reused in this scenario.
708 */
709 status |= MCI_STATUS_DEFERRED | MCI_STATUS_POISON;
710 }
711 }
712
713 flags = cpu_x86_support_mca_broadcast(env) ? MCE_INJECT_BROADCAST : 0;
714 /* We need to read back the value of MSR_EXT_MCG_CTL that was set by the
715 * guest kernel back into env->mcg_ext_ctl.
716 */
717 cpu_synchronize_state(cs);
718 if (env->mcg_ext_ctl & MCG_EXT_CTL_LMCE_EN) {
719 mcg_status |= MCG_STATUS_LMCE;
720 flags = 0;
721 }
722
723 cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr,
724 (MCM_ADDR_PHYS << 6) | 0xc, flags);
725 }
726
emit_hypervisor_memory_failure(MemoryFailureAction action,bool ar)727 static void emit_hypervisor_memory_failure(MemoryFailureAction action, bool ar)
728 {
729 MemoryFailureFlags mff = {.action_required = ar, .recursive = false};
730
731 qapi_event_send_memory_failure(MEMORY_FAILURE_RECIPIENT_HYPERVISOR, action,
732 &mff);
733 }
734
hardware_memory_error(void * host_addr)735 static void hardware_memory_error(void *host_addr)
736 {
737 emit_hypervisor_memory_failure(MEMORY_FAILURE_ACTION_FATAL, true);
738 error_report("QEMU got Hardware memory error at addr %p", host_addr);
739 exit(1);
740 }
741
kvm_arch_on_sigbus_vcpu(CPUState * c,int code,void * addr)742 void kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
743 {
744 X86CPU *cpu = X86_CPU(c);
745 CPUX86State *env = &cpu->env;
746 ram_addr_t ram_addr;
747 hwaddr paddr;
748
749 /* If we get an action required MCE, it has been injected by KVM
750 * while the VM was running. An action optional MCE instead should
751 * be coming from the main thread, which qemu_init_sigbus identifies
752 * as the "early kill" thread.
753 */
754 assert(code == BUS_MCEERR_AR || code == BUS_MCEERR_AO);
755
756 if ((env->mcg_cap & MCG_SER_P) && addr) {
757 ram_addr = qemu_ram_addr_from_host(addr);
758 if (ram_addr != RAM_ADDR_INVALID &&
759 kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
760 kvm_hwpoison_page_add(ram_addr);
761 kvm_mce_inject(cpu, paddr, code);
762
763 /*
764 * Use different logging severity based on error type.
765 * If there is additional MCE reporting on the hypervisor, QEMU VA
766 * could be another source to identify the PA and MCE details.
767 */
768 if (code == BUS_MCEERR_AR) {
769 error_report("Guest MCE Memory Error at QEMU addr %p and "
770 "GUEST addr 0x%" HWADDR_PRIx " of type %s injected",
771 addr, paddr, "BUS_MCEERR_AR");
772 } else {
773 warn_report("Guest MCE Memory Error at QEMU addr %p and "
774 "GUEST addr 0x%" HWADDR_PRIx " of type %s injected",
775 addr, paddr, "BUS_MCEERR_AO");
776 }
777
778 return;
779 }
780
781 if (code == BUS_MCEERR_AO) {
782 warn_report("Hardware memory error at addr %p of type %s "
783 "for memory used by QEMU itself instead of guest system!",
784 addr, "BUS_MCEERR_AO");
785 }
786 }
787
788 if (code == BUS_MCEERR_AR) {
789 hardware_memory_error(addr);
790 }
791
792 /* Hope we are lucky for AO MCE, just notify a event */
793 emit_hypervisor_memory_failure(MEMORY_FAILURE_ACTION_IGNORE, false);
794 }
795
kvm_queue_exception(CPUX86State * env,int32_t exception_nr,uint8_t exception_has_payload,uint64_t exception_payload)796 static void kvm_queue_exception(CPUX86State *env,
797 int32_t exception_nr,
798 uint8_t exception_has_payload,
799 uint64_t exception_payload)
800 {
801 assert(env->exception_nr == -1);
802 assert(!env->exception_pending);
803 assert(!env->exception_injected);
804 assert(!env->exception_has_payload);
805
806 env->exception_nr = exception_nr;
807
808 if (has_exception_payload) {
809 env->exception_pending = 1;
810
811 env->exception_has_payload = exception_has_payload;
812 env->exception_payload = exception_payload;
813 } else {
814 env->exception_injected = 1;
815
816 if (exception_nr == EXCP01_DB) {
817 assert(exception_has_payload);
818 env->dr[6] = exception_payload;
819 } else if (exception_nr == EXCP0E_PAGE) {
820 assert(exception_has_payload);
821 env->cr[2] = exception_payload;
822 } else {
823 assert(!exception_has_payload);
824 }
825 }
826 }
827
cpu_update_state(void * opaque,bool running,RunState state)828 static void cpu_update_state(void *opaque, bool running, RunState state)
829 {
830 CPUX86State *env = opaque;
831
832 if (running) {
833 env->tsc_valid = false;
834 }
835 }
836
kvm_arch_vcpu_id(CPUState * cs)837 unsigned long kvm_arch_vcpu_id(CPUState *cs)
838 {
839 X86CPU *cpu = X86_CPU(cs);
840 return cpu->apic_id;
841 }
842
843 #ifndef KVM_CPUID_SIGNATURE_NEXT
844 #define KVM_CPUID_SIGNATURE_NEXT 0x40000100
845 #endif
846
hyperv_enabled(X86CPU * cpu)847 static bool hyperv_enabled(X86CPU *cpu)
848 {
849 return kvm_check_extension(kvm_state, KVM_CAP_HYPERV) > 0 &&
850 ((cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_NOTIFY) ||
851 cpu->hyperv_features || cpu->hyperv_passthrough);
852 }
853
854 /*
855 * Check whether target_freq is within conservative
856 * ntp correctable bounds (250ppm) of freq
857 */
freq_within_bounds(int freq,int target_freq)858 static inline bool freq_within_bounds(int freq, int target_freq)
859 {
860 int max_freq = freq + (freq * 250 / 1000000);
861 int min_freq = freq - (freq * 250 / 1000000);
862
863 if (target_freq >= min_freq && target_freq <= max_freq) {
864 return true;
865 }
866
867 return false;
868 }
869
kvm_arch_set_tsc_khz(CPUState * cs)870 static int kvm_arch_set_tsc_khz(CPUState *cs)
871 {
872 X86CPU *cpu = X86_CPU(cs);
873 CPUX86State *env = &cpu->env;
874 int r, cur_freq;
875 bool set_ioctl = false;
876
877 /*
878 * TSC of TD vcpu is immutable, it cannot be set/changed via vcpu scope
879 * VM_SET_TSC_KHZ, but only be initialized via VM scope VM_SET_TSC_KHZ
880 * before ioctl KVM_TDX_INIT_VM in tdx_pre_create_vcpu()
881 */
882 if (is_tdx_vm()) {
883 return 0;
884 }
885
886 if (!env->tsc_khz) {
887 return 0;
888 }
889
890 cur_freq = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
891 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) : -ENOTSUP;
892
893 /*
894 * If TSC scaling is supported, attempt to set TSC frequency.
895 */
896 if (kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL)) {
897 set_ioctl = true;
898 }
899
900 /*
901 * If desired TSC frequency is within bounds of NTP correction,
902 * attempt to set TSC frequency.
903 */
904 if (cur_freq != -ENOTSUP && freq_within_bounds(cur_freq, env->tsc_khz)) {
905 set_ioctl = true;
906 }
907
908 r = set_ioctl ?
909 kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz) :
910 -ENOTSUP;
911
912 if (r < 0) {
913 /* When KVM_SET_TSC_KHZ fails, it's an error only if the current
914 * TSC frequency doesn't match the one we want.
915 */
916 cur_freq = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
917 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
918 -ENOTSUP;
919 if (cur_freq <= 0 || cur_freq != env->tsc_khz) {
920 warn_report("TSC frequency mismatch between "
921 "VM (%" PRId64 " kHz) and host (%d kHz), "
922 "and TSC scaling unavailable",
923 env->tsc_khz, cur_freq);
924 return r;
925 }
926 }
927
928 return 0;
929 }
930
tsc_is_stable_and_known(CPUX86State * env)931 static bool tsc_is_stable_and_known(CPUX86State *env)
932 {
933 if (!env->tsc_khz) {
934 return false;
935 }
936 return (env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC)
937 || env->user_tsc_khz;
938 }
939
940 #define DEFAULT_EVMCS_VERSION ((1 << 8) | 1)
941
942 static struct {
943 const char *desc;
944 struct {
945 uint32_t func;
946 int reg;
947 uint32_t bits;
948 } flags[2];
949 uint64_t dependencies;
950 bool skip_passthrough;
951 } kvm_hyperv_properties[] = {
952 [HYPERV_FEAT_RELAXED] = {
953 .desc = "relaxed timing (hv-relaxed)",
954 .flags = {
955 {.func = HV_CPUID_ENLIGHTMENT_INFO, .reg = R_EAX,
956 .bits = HV_RELAXED_TIMING_RECOMMENDED}
957 }
958 },
959 [HYPERV_FEAT_VAPIC] = {
960 .desc = "virtual APIC (hv-vapic)",
961 .flags = {
962 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
963 .bits = HV_APIC_ACCESS_AVAILABLE}
964 }
965 },
966 [HYPERV_FEAT_TIME] = {
967 .desc = "clocksources (hv-time)",
968 .flags = {
969 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
970 .bits = HV_TIME_REF_COUNT_AVAILABLE | HV_REFERENCE_TSC_AVAILABLE}
971 }
972 },
973 [HYPERV_FEAT_CRASH] = {
974 .desc = "crash MSRs (hv-crash)",
975 .flags = {
976 {.func = HV_CPUID_FEATURES, .reg = R_EDX,
977 .bits = HV_GUEST_CRASH_MSR_AVAILABLE}
978 }
979 },
980 [HYPERV_FEAT_RESET] = {
981 .desc = "reset MSR (hv-reset)",
982 .flags = {
983 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
984 .bits = HV_RESET_AVAILABLE}
985 }
986 },
987 [HYPERV_FEAT_VPINDEX] = {
988 .desc = "VP_INDEX MSR (hv-vpindex)",
989 .flags = {
990 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
991 .bits = HV_VP_INDEX_AVAILABLE}
992 }
993 },
994 [HYPERV_FEAT_RUNTIME] = {
995 .desc = "VP_RUNTIME MSR (hv-runtime)",
996 .flags = {
997 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
998 .bits = HV_VP_RUNTIME_AVAILABLE}
999 }
1000 },
1001 [HYPERV_FEAT_SYNIC] = {
1002 .desc = "synthetic interrupt controller (hv-synic)",
1003 .flags = {
1004 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
1005 .bits = HV_SYNIC_AVAILABLE}
1006 }
1007 },
1008 [HYPERV_FEAT_STIMER] = {
1009 .desc = "synthetic timers (hv-stimer)",
1010 .flags = {
1011 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
1012 .bits = HV_SYNTIMERS_AVAILABLE}
1013 },
1014 .dependencies = BIT(HYPERV_FEAT_SYNIC) | BIT(HYPERV_FEAT_TIME)
1015 },
1016 [HYPERV_FEAT_FREQUENCIES] = {
1017 .desc = "frequency MSRs (hv-frequencies)",
1018 .flags = {
1019 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
1020 .bits = HV_ACCESS_FREQUENCY_MSRS},
1021 {.func = HV_CPUID_FEATURES, .reg = R_EDX,
1022 .bits = HV_FREQUENCY_MSRS_AVAILABLE}
1023 }
1024 },
1025 [HYPERV_FEAT_REENLIGHTENMENT] = {
1026 .desc = "reenlightenment MSRs (hv-reenlightenment)",
1027 .flags = {
1028 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
1029 .bits = HV_ACCESS_REENLIGHTENMENTS_CONTROL}
1030 }
1031 },
1032 [HYPERV_FEAT_TLBFLUSH] = {
1033 .desc = "paravirtualized TLB flush (hv-tlbflush)",
1034 .flags = {
1035 {.func = HV_CPUID_ENLIGHTMENT_INFO, .reg = R_EAX,
1036 .bits = HV_REMOTE_TLB_FLUSH_RECOMMENDED |
1037 HV_EX_PROCESSOR_MASKS_RECOMMENDED}
1038 },
1039 .dependencies = BIT(HYPERV_FEAT_VPINDEX)
1040 },
1041 [HYPERV_FEAT_EVMCS] = {
1042 .desc = "enlightened VMCS (hv-evmcs)",
1043 .flags = {
1044 {.func = HV_CPUID_ENLIGHTMENT_INFO, .reg = R_EAX,
1045 .bits = HV_ENLIGHTENED_VMCS_RECOMMENDED}
1046 },
1047 .dependencies = BIT(HYPERV_FEAT_VAPIC)
1048 },
1049 [HYPERV_FEAT_IPI] = {
1050 .desc = "paravirtualized IPI (hv-ipi)",
1051 .flags = {
1052 {.func = HV_CPUID_ENLIGHTMENT_INFO, .reg = R_EAX,
1053 .bits = HV_CLUSTER_IPI_RECOMMENDED |
1054 HV_EX_PROCESSOR_MASKS_RECOMMENDED}
1055 },
1056 .dependencies = BIT(HYPERV_FEAT_VPINDEX)
1057 },
1058 [HYPERV_FEAT_STIMER_DIRECT] = {
1059 .desc = "direct mode synthetic timers (hv-stimer-direct)",
1060 .flags = {
1061 {.func = HV_CPUID_FEATURES, .reg = R_EDX,
1062 .bits = HV_STIMER_DIRECT_MODE_AVAILABLE}
1063 },
1064 .dependencies = BIT(HYPERV_FEAT_STIMER)
1065 },
1066 [HYPERV_FEAT_AVIC] = {
1067 .desc = "AVIC/APICv support (hv-avic/hv-apicv)",
1068 .flags = {
1069 {.func = HV_CPUID_ENLIGHTMENT_INFO, .reg = R_EAX,
1070 .bits = HV_DEPRECATING_AEOI_RECOMMENDED}
1071 }
1072 },
1073 [HYPERV_FEAT_SYNDBG] = {
1074 .desc = "Enable synthetic kernel debugger channel (hv-syndbg)",
1075 .flags = {
1076 {.func = HV_CPUID_FEATURES, .reg = R_EDX,
1077 .bits = HV_FEATURE_DEBUG_MSRS_AVAILABLE}
1078 },
1079 .dependencies = BIT(HYPERV_FEAT_SYNIC) | BIT(HYPERV_FEAT_RELAXED),
1080 .skip_passthrough = true,
1081 },
1082 [HYPERV_FEAT_MSR_BITMAP] = {
1083 .desc = "enlightened MSR-Bitmap (hv-emsr-bitmap)",
1084 .flags = {
1085 {.func = HV_CPUID_NESTED_FEATURES, .reg = R_EAX,
1086 .bits = HV_NESTED_MSR_BITMAP}
1087 }
1088 },
1089 [HYPERV_FEAT_XMM_INPUT] = {
1090 .desc = "XMM fast hypercall input (hv-xmm-input)",
1091 .flags = {
1092 {.func = HV_CPUID_FEATURES, .reg = R_EDX,
1093 .bits = HV_HYPERCALL_XMM_INPUT_AVAILABLE}
1094 }
1095 },
1096 [HYPERV_FEAT_TLBFLUSH_EXT] = {
1097 .desc = "Extended gva ranges for TLB flush hypercalls (hv-tlbflush-ext)",
1098 .flags = {
1099 {.func = HV_CPUID_FEATURES, .reg = R_EDX,
1100 .bits = HV_EXT_GVA_RANGES_FLUSH_AVAILABLE}
1101 },
1102 .dependencies = BIT(HYPERV_FEAT_TLBFLUSH)
1103 },
1104 [HYPERV_FEAT_TLBFLUSH_DIRECT] = {
1105 .desc = "direct TLB flush (hv-tlbflush-direct)",
1106 .flags = {
1107 {.func = HV_CPUID_NESTED_FEATURES, .reg = R_EAX,
1108 .bits = HV_NESTED_DIRECT_FLUSH}
1109 },
1110 .dependencies = BIT(HYPERV_FEAT_VAPIC)
1111 },
1112 };
1113
try_get_hv_cpuid(CPUState * cs,int max,bool do_sys_ioctl)1114 static struct kvm_cpuid2 *try_get_hv_cpuid(CPUState *cs, int max,
1115 bool do_sys_ioctl)
1116 {
1117 struct kvm_cpuid2 *cpuid;
1118 int r, size;
1119
1120 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
1121 cpuid = g_malloc0(size);
1122 cpuid->nent = max;
1123
1124 if (do_sys_ioctl) {
1125 r = kvm_ioctl(kvm_state, KVM_GET_SUPPORTED_HV_CPUID, cpuid);
1126 } else {
1127 r = kvm_vcpu_ioctl(cs, KVM_GET_SUPPORTED_HV_CPUID, cpuid);
1128 }
1129 if (r == 0 && cpuid->nent >= max) {
1130 r = -E2BIG;
1131 }
1132 if (r < 0) {
1133 if (r == -E2BIG) {
1134 g_free(cpuid);
1135 return NULL;
1136 } else {
1137 fprintf(stderr, "KVM_GET_SUPPORTED_HV_CPUID failed: %s\n",
1138 strerror(-r));
1139 exit(1);
1140 }
1141 }
1142 return cpuid;
1143 }
1144
1145 /*
1146 * Run KVM_GET_SUPPORTED_HV_CPUID ioctl(), allocating a buffer large enough
1147 * for all entries.
1148 */
get_supported_hv_cpuid(CPUState * cs)1149 static struct kvm_cpuid2 *get_supported_hv_cpuid(CPUState *cs)
1150 {
1151 struct kvm_cpuid2 *cpuid;
1152 /* 0x40000000..0x40000005, 0x4000000A, 0x40000080..0x40000082 leaves */
1153 int max = 11;
1154 int i;
1155 bool do_sys_ioctl;
1156
1157 do_sys_ioctl =
1158 kvm_check_extension(kvm_state, KVM_CAP_SYS_HYPERV_CPUID) > 0;
1159
1160 /*
1161 * Non-empty KVM context is needed when KVM_CAP_SYS_HYPERV_CPUID is
1162 * unsupported, kvm_hyperv_expand_features() checks for that.
1163 */
1164 assert(do_sys_ioctl || cs->kvm_state);
1165
1166 /*
1167 * When the buffer is too small, KVM_GET_SUPPORTED_HV_CPUID fails with
1168 * -E2BIG, however, it doesn't report back the right size. Keep increasing
1169 * it and re-trying until we succeed.
1170 */
1171 while ((cpuid = try_get_hv_cpuid(cs, max, do_sys_ioctl)) == NULL) {
1172 max++;
1173 }
1174
1175 /*
1176 * KVM_GET_SUPPORTED_HV_CPUID does not set EVMCS CPUID bit before
1177 * KVM_CAP_HYPERV_ENLIGHTENED_VMCS is enabled but we want to get the
1178 * information early, just check for the capability and set the bit
1179 * manually.
1180 */
1181 if (!do_sys_ioctl && kvm_check_extension(cs->kvm_state,
1182 KVM_CAP_HYPERV_ENLIGHTENED_VMCS) > 0) {
1183 for (i = 0; i < cpuid->nent; i++) {
1184 if (cpuid->entries[i].function == HV_CPUID_ENLIGHTMENT_INFO) {
1185 cpuid->entries[i].eax |= HV_ENLIGHTENED_VMCS_RECOMMENDED;
1186 }
1187 }
1188 }
1189
1190 return cpuid;
1191 }
1192
1193 /*
1194 * When KVM_GET_SUPPORTED_HV_CPUID is not supported we fill CPUID feature
1195 * leaves from KVM_CAP_HYPERV* and present MSRs data.
1196 */
get_supported_hv_cpuid_legacy(CPUState * cs)1197 static struct kvm_cpuid2 *get_supported_hv_cpuid_legacy(CPUState *cs)
1198 {
1199 X86CPU *cpu = X86_CPU(cs);
1200 struct kvm_cpuid2 *cpuid;
1201 struct kvm_cpuid_entry2 *entry_feat, *entry_recomm;
1202
1203 /* HV_CPUID_FEATURES, HV_CPUID_ENLIGHTMENT_INFO */
1204 cpuid = g_malloc0(sizeof(*cpuid) + 2 * sizeof(*cpuid->entries));
1205 cpuid->nent = 2;
1206
1207 /* HV_CPUID_VENDOR_AND_MAX_FUNCTIONS */
1208 entry_feat = &cpuid->entries[0];
1209 entry_feat->function = HV_CPUID_FEATURES;
1210
1211 entry_recomm = &cpuid->entries[1];
1212 entry_recomm->function = HV_CPUID_ENLIGHTMENT_INFO;
1213 entry_recomm->ebx = cpu->hyperv_spinlock_attempts;
1214
1215 if (kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0) {
1216 entry_feat->eax |= HV_HYPERCALL_AVAILABLE;
1217 entry_feat->eax |= HV_APIC_ACCESS_AVAILABLE;
1218 entry_feat->edx |= HV_CPU_DYNAMIC_PARTITIONING_AVAILABLE;
1219 entry_recomm->eax |= HV_RELAXED_TIMING_RECOMMENDED;
1220 entry_recomm->eax |= HV_APIC_ACCESS_RECOMMENDED;
1221 }
1222
1223 if (kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_TIME) > 0) {
1224 entry_feat->eax |= HV_TIME_REF_COUNT_AVAILABLE;
1225 entry_feat->eax |= HV_REFERENCE_TSC_AVAILABLE;
1226 }
1227
1228 if (has_msr_hv_frequencies) {
1229 entry_feat->eax |= HV_ACCESS_FREQUENCY_MSRS;
1230 entry_feat->edx |= HV_FREQUENCY_MSRS_AVAILABLE;
1231 }
1232
1233 if (has_msr_hv_crash) {
1234 entry_feat->edx |= HV_GUEST_CRASH_MSR_AVAILABLE;
1235 }
1236
1237 if (has_msr_hv_reenlightenment) {
1238 entry_feat->eax |= HV_ACCESS_REENLIGHTENMENTS_CONTROL;
1239 }
1240
1241 if (has_msr_hv_reset) {
1242 entry_feat->eax |= HV_RESET_AVAILABLE;
1243 }
1244
1245 if (has_msr_hv_vpindex) {
1246 entry_feat->eax |= HV_VP_INDEX_AVAILABLE;
1247 }
1248
1249 if (has_msr_hv_runtime) {
1250 entry_feat->eax |= HV_VP_RUNTIME_AVAILABLE;
1251 }
1252
1253 if (has_msr_hv_synic) {
1254 unsigned int cap = cpu->hyperv_synic_kvm_only ?
1255 KVM_CAP_HYPERV_SYNIC : KVM_CAP_HYPERV_SYNIC2;
1256
1257 if (kvm_check_extension(cs->kvm_state, cap) > 0) {
1258 entry_feat->eax |= HV_SYNIC_AVAILABLE;
1259 }
1260 }
1261
1262 if (has_msr_hv_stimer) {
1263 entry_feat->eax |= HV_SYNTIMERS_AVAILABLE;
1264 }
1265
1266 if (has_msr_hv_syndbg_options) {
1267 entry_feat->edx |= HV_GUEST_DEBUGGING_AVAILABLE;
1268 entry_feat->edx |= HV_FEATURE_DEBUG_MSRS_AVAILABLE;
1269 entry_feat->ebx |= HV_PARTITION_DEBUGGING_ALLOWED;
1270 }
1271
1272 if (kvm_check_extension(cs->kvm_state,
1273 KVM_CAP_HYPERV_TLBFLUSH) > 0) {
1274 entry_recomm->eax |= HV_REMOTE_TLB_FLUSH_RECOMMENDED;
1275 entry_recomm->eax |= HV_EX_PROCESSOR_MASKS_RECOMMENDED;
1276 }
1277
1278 if (kvm_check_extension(cs->kvm_state,
1279 KVM_CAP_HYPERV_ENLIGHTENED_VMCS) > 0) {
1280 entry_recomm->eax |= HV_ENLIGHTENED_VMCS_RECOMMENDED;
1281 }
1282
1283 if (kvm_check_extension(cs->kvm_state,
1284 KVM_CAP_HYPERV_SEND_IPI) > 0) {
1285 entry_recomm->eax |= HV_CLUSTER_IPI_RECOMMENDED;
1286 entry_recomm->eax |= HV_EX_PROCESSOR_MASKS_RECOMMENDED;
1287 }
1288
1289 return cpuid;
1290 }
1291
hv_cpuid_get_host(CPUState * cs,uint32_t func,int reg)1292 static uint32_t hv_cpuid_get_host(CPUState *cs, uint32_t func, int reg)
1293 {
1294 struct kvm_cpuid_entry2 *entry;
1295 struct kvm_cpuid2 *cpuid;
1296
1297 if (hv_cpuid_cache) {
1298 cpuid = hv_cpuid_cache;
1299 } else {
1300 if (kvm_check_extension(kvm_state, KVM_CAP_HYPERV_CPUID) > 0) {
1301 cpuid = get_supported_hv_cpuid(cs);
1302 } else {
1303 /*
1304 * 'cs->kvm_state' may be NULL when Hyper-V features are expanded
1305 * before KVM context is created but this is only done when
1306 * KVM_CAP_SYS_HYPERV_CPUID is supported and it implies
1307 * KVM_CAP_HYPERV_CPUID.
1308 */
1309 assert(cs->kvm_state);
1310
1311 cpuid = get_supported_hv_cpuid_legacy(cs);
1312 }
1313 hv_cpuid_cache = cpuid;
1314 }
1315
1316 if (!cpuid) {
1317 return 0;
1318 }
1319
1320 entry = cpuid_find_entry(cpuid, func, 0);
1321 if (!entry) {
1322 return 0;
1323 }
1324
1325 return cpuid_entry_get_reg(entry, reg);
1326 }
1327
hyperv_feature_supported(CPUState * cs,int feature)1328 static bool hyperv_feature_supported(CPUState *cs, int feature)
1329 {
1330 uint32_t func, bits;
1331 int i, reg;
1332
1333 /*
1334 * kvm_hyperv_properties needs to define at least one CPUID flag which
1335 * must be used to detect the feature, it's hard to say whether it is
1336 * supported or not otherwise.
1337 */
1338 assert(kvm_hyperv_properties[feature].flags[0].func);
1339
1340 for (i = 0; i < ARRAY_SIZE(kvm_hyperv_properties[feature].flags); i++) {
1341
1342 func = kvm_hyperv_properties[feature].flags[i].func;
1343 reg = kvm_hyperv_properties[feature].flags[i].reg;
1344 bits = kvm_hyperv_properties[feature].flags[i].bits;
1345
1346 if (!func) {
1347 continue;
1348 }
1349
1350 if ((hv_cpuid_get_host(cs, func, reg) & bits) != bits) {
1351 return false;
1352 }
1353 }
1354
1355 return true;
1356 }
1357
1358 /* Checks that all feature dependencies are enabled */
hv_feature_check_deps(X86CPU * cpu,int feature,Error ** errp)1359 static bool hv_feature_check_deps(X86CPU *cpu, int feature, Error **errp)
1360 {
1361 uint64_t deps;
1362 int dep_feat;
1363
1364 deps = kvm_hyperv_properties[feature].dependencies;
1365 while (deps) {
1366 dep_feat = ctz64(deps);
1367 if (!(hyperv_feat_enabled(cpu, dep_feat))) {
1368 error_setg(errp, "Hyper-V %s requires Hyper-V %s",
1369 kvm_hyperv_properties[feature].desc,
1370 kvm_hyperv_properties[dep_feat].desc);
1371 return false;
1372 }
1373 deps &= ~(1ull << dep_feat);
1374 }
1375
1376 return true;
1377 }
1378
hv_build_cpuid_leaf(CPUState * cs,uint32_t func,int reg)1379 static uint32_t hv_build_cpuid_leaf(CPUState *cs, uint32_t func, int reg)
1380 {
1381 X86CPU *cpu = X86_CPU(cs);
1382 uint32_t r = 0;
1383 int i, j;
1384
1385 for (i = 0; i < ARRAY_SIZE(kvm_hyperv_properties); i++) {
1386 if (!hyperv_feat_enabled(cpu, i)) {
1387 continue;
1388 }
1389
1390 for (j = 0; j < ARRAY_SIZE(kvm_hyperv_properties[i].flags); j++) {
1391 if (kvm_hyperv_properties[i].flags[j].func != func) {
1392 continue;
1393 }
1394 if (kvm_hyperv_properties[i].flags[j].reg != reg) {
1395 continue;
1396 }
1397
1398 r |= kvm_hyperv_properties[i].flags[j].bits;
1399 }
1400 }
1401
1402 /* HV_CPUID_NESTED_FEATURES.EAX also encodes the supported eVMCS range */
1403 if (func == HV_CPUID_NESTED_FEATURES && reg == R_EAX) {
1404 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS)) {
1405 r |= DEFAULT_EVMCS_VERSION;
1406 }
1407 }
1408
1409 return r;
1410 }
1411
1412 /*
1413 * Expand Hyper-V CPU features. In partucular, check that all the requested
1414 * features are supported by the host and the sanity of the configuration
1415 * (that all the required dependencies are included). Also, this takes care
1416 * of 'hv_passthrough' mode and fills the environment with all supported
1417 * Hyper-V features.
1418 */
kvm_hyperv_expand_features(X86CPU * cpu,Error ** errp)1419 bool kvm_hyperv_expand_features(X86CPU *cpu, Error **errp)
1420 {
1421 CPUState *cs = CPU(cpu);
1422 Error *local_err = NULL;
1423 int feat;
1424
1425 if (!hyperv_enabled(cpu))
1426 return true;
1427
1428 /*
1429 * When kvm_hyperv_expand_features is called at CPU feature expansion
1430 * time per-CPU kvm_state is not available yet so we can only proceed
1431 * when KVM_CAP_SYS_HYPERV_CPUID is supported.
1432 */
1433 if (!cs->kvm_state &&
1434 !kvm_check_extension(kvm_state, KVM_CAP_SYS_HYPERV_CPUID))
1435 return true;
1436
1437 if (cpu->hyperv_passthrough) {
1438 cpu->hyperv_vendor_id[0] =
1439 hv_cpuid_get_host(cs, HV_CPUID_VENDOR_AND_MAX_FUNCTIONS, R_EBX);
1440 cpu->hyperv_vendor_id[1] =
1441 hv_cpuid_get_host(cs, HV_CPUID_VENDOR_AND_MAX_FUNCTIONS, R_ECX);
1442 cpu->hyperv_vendor_id[2] =
1443 hv_cpuid_get_host(cs, HV_CPUID_VENDOR_AND_MAX_FUNCTIONS, R_EDX);
1444 cpu->hyperv_vendor = g_realloc(cpu->hyperv_vendor,
1445 sizeof(cpu->hyperv_vendor_id) + 1);
1446 memcpy(cpu->hyperv_vendor, cpu->hyperv_vendor_id,
1447 sizeof(cpu->hyperv_vendor_id));
1448 cpu->hyperv_vendor[sizeof(cpu->hyperv_vendor_id)] = 0;
1449
1450 cpu->hyperv_interface_id[0] =
1451 hv_cpuid_get_host(cs, HV_CPUID_INTERFACE, R_EAX);
1452 cpu->hyperv_interface_id[1] =
1453 hv_cpuid_get_host(cs, HV_CPUID_INTERFACE, R_EBX);
1454 cpu->hyperv_interface_id[2] =
1455 hv_cpuid_get_host(cs, HV_CPUID_INTERFACE, R_ECX);
1456 cpu->hyperv_interface_id[3] =
1457 hv_cpuid_get_host(cs, HV_CPUID_INTERFACE, R_EDX);
1458
1459 cpu->hyperv_ver_id_build =
1460 hv_cpuid_get_host(cs, HV_CPUID_VERSION, R_EAX);
1461 cpu->hyperv_ver_id_major =
1462 hv_cpuid_get_host(cs, HV_CPUID_VERSION, R_EBX) >> 16;
1463 cpu->hyperv_ver_id_minor =
1464 hv_cpuid_get_host(cs, HV_CPUID_VERSION, R_EBX) & 0xffff;
1465 cpu->hyperv_ver_id_sp =
1466 hv_cpuid_get_host(cs, HV_CPUID_VERSION, R_ECX);
1467 cpu->hyperv_ver_id_sb =
1468 hv_cpuid_get_host(cs, HV_CPUID_VERSION, R_EDX) >> 24;
1469 cpu->hyperv_ver_id_sn =
1470 hv_cpuid_get_host(cs, HV_CPUID_VERSION, R_EDX) & 0xffffff;
1471
1472 cpu->hv_max_vps = hv_cpuid_get_host(cs, HV_CPUID_IMPLEMENT_LIMITS,
1473 R_EAX);
1474 cpu->hyperv_limits[0] =
1475 hv_cpuid_get_host(cs, HV_CPUID_IMPLEMENT_LIMITS, R_EBX);
1476 cpu->hyperv_limits[1] =
1477 hv_cpuid_get_host(cs, HV_CPUID_IMPLEMENT_LIMITS, R_ECX);
1478 cpu->hyperv_limits[2] =
1479 hv_cpuid_get_host(cs, HV_CPUID_IMPLEMENT_LIMITS, R_EDX);
1480
1481 cpu->hyperv_spinlock_attempts =
1482 hv_cpuid_get_host(cs, HV_CPUID_ENLIGHTMENT_INFO, R_EBX);
1483
1484 /*
1485 * Mark feature as enabled in 'cpu->hyperv_features' as
1486 * hv_build_cpuid_leaf() uses this info to build guest CPUIDs.
1487 */
1488 for (feat = 0; feat < ARRAY_SIZE(kvm_hyperv_properties); feat++) {
1489 if (hyperv_feature_supported(cs, feat) &&
1490 !kvm_hyperv_properties[feat].skip_passthrough) {
1491 cpu->hyperv_features |= BIT(feat);
1492 }
1493 }
1494 } else {
1495 /* Check features availability and dependencies */
1496 for (feat = 0; feat < ARRAY_SIZE(kvm_hyperv_properties); feat++) {
1497 /* If the feature was not requested skip it. */
1498 if (!hyperv_feat_enabled(cpu, feat)) {
1499 continue;
1500 }
1501
1502 /* Check if the feature is supported by KVM */
1503 if (!hyperv_feature_supported(cs, feat)) {
1504 error_setg(errp, "Hyper-V %s is not supported by kernel",
1505 kvm_hyperv_properties[feat].desc);
1506 return false;
1507 }
1508
1509 /* Check dependencies */
1510 if (!hv_feature_check_deps(cpu, feat, &local_err)) {
1511 error_propagate(errp, local_err);
1512 return false;
1513 }
1514 }
1515 }
1516
1517 /* Additional dependencies not covered by kvm_hyperv_properties[] */
1518 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC) &&
1519 !cpu->hyperv_synic_kvm_only &&
1520 !hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX)) {
1521 error_setg(errp, "Hyper-V %s requires Hyper-V %s",
1522 kvm_hyperv_properties[HYPERV_FEAT_SYNIC].desc,
1523 kvm_hyperv_properties[HYPERV_FEAT_VPINDEX].desc);
1524 return false;
1525 }
1526
1527 return true;
1528 }
1529
1530 /*
1531 * Fill in Hyper-V CPUIDs. Returns the number of entries filled in cpuid_ent.
1532 */
hyperv_fill_cpuids(CPUState * cs,struct kvm_cpuid_entry2 * cpuid_ent)1533 static int hyperv_fill_cpuids(CPUState *cs,
1534 struct kvm_cpuid_entry2 *cpuid_ent)
1535 {
1536 X86CPU *cpu = X86_CPU(cs);
1537 struct kvm_cpuid_entry2 *c;
1538 uint32_t signature[3];
1539 uint32_t cpuid_i = 0, max_cpuid_leaf = 0;
1540 uint32_t nested_eax =
1541 hv_build_cpuid_leaf(cs, HV_CPUID_NESTED_FEATURES, R_EAX);
1542
1543 max_cpuid_leaf = nested_eax ? HV_CPUID_NESTED_FEATURES :
1544 HV_CPUID_IMPLEMENT_LIMITS;
1545
1546 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNDBG)) {
1547 max_cpuid_leaf =
1548 MAX(max_cpuid_leaf, HV_CPUID_SYNDBG_PLATFORM_CAPABILITIES);
1549 }
1550
1551 c = &cpuid_ent[cpuid_i++];
1552 c->function = HV_CPUID_VENDOR_AND_MAX_FUNCTIONS;
1553 c->eax = max_cpuid_leaf;
1554 c->ebx = cpu->hyperv_vendor_id[0];
1555 c->ecx = cpu->hyperv_vendor_id[1];
1556 c->edx = cpu->hyperv_vendor_id[2];
1557
1558 c = &cpuid_ent[cpuid_i++];
1559 c->function = HV_CPUID_INTERFACE;
1560 c->eax = cpu->hyperv_interface_id[0];
1561 c->ebx = cpu->hyperv_interface_id[1];
1562 c->ecx = cpu->hyperv_interface_id[2];
1563 c->edx = cpu->hyperv_interface_id[3];
1564
1565 c = &cpuid_ent[cpuid_i++];
1566 c->function = HV_CPUID_VERSION;
1567 c->eax = cpu->hyperv_ver_id_build;
1568 c->ebx = (uint32_t)cpu->hyperv_ver_id_major << 16 |
1569 cpu->hyperv_ver_id_minor;
1570 c->ecx = cpu->hyperv_ver_id_sp;
1571 c->edx = (uint32_t)cpu->hyperv_ver_id_sb << 24 |
1572 (cpu->hyperv_ver_id_sn & 0xffffff);
1573
1574 c = &cpuid_ent[cpuid_i++];
1575 c->function = HV_CPUID_FEATURES;
1576 c->eax = hv_build_cpuid_leaf(cs, HV_CPUID_FEATURES, R_EAX);
1577 c->ebx = hv_build_cpuid_leaf(cs, HV_CPUID_FEATURES, R_EBX);
1578 c->edx = hv_build_cpuid_leaf(cs, HV_CPUID_FEATURES, R_EDX);
1579
1580 /* Unconditionally required with any Hyper-V enlightenment */
1581 c->eax |= HV_HYPERCALL_AVAILABLE;
1582
1583 /* SynIC and Vmbus devices require messages/signals hypercalls */
1584 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC) &&
1585 !cpu->hyperv_synic_kvm_only) {
1586 c->ebx |= HV_POST_MESSAGES | HV_SIGNAL_EVENTS;
1587 }
1588
1589
1590 /* Not exposed by KVM but needed to make CPU hotplug in Windows work */
1591 c->edx |= HV_CPU_DYNAMIC_PARTITIONING_AVAILABLE;
1592
1593 c = &cpuid_ent[cpuid_i++];
1594 c->function = HV_CPUID_ENLIGHTMENT_INFO;
1595 c->eax = hv_build_cpuid_leaf(cs, HV_CPUID_ENLIGHTMENT_INFO, R_EAX);
1596 c->ebx = cpu->hyperv_spinlock_attempts;
1597
1598 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VAPIC) &&
1599 !hyperv_feat_enabled(cpu, HYPERV_FEAT_AVIC)) {
1600 c->eax |= HV_APIC_ACCESS_RECOMMENDED;
1601 }
1602
1603 if (cpu->hyperv_no_nonarch_cs == ON_OFF_AUTO_ON) {
1604 c->eax |= HV_NO_NONARCH_CORESHARING;
1605 } else if (cpu->hyperv_no_nonarch_cs == ON_OFF_AUTO_AUTO) {
1606 c->eax |= hv_cpuid_get_host(cs, HV_CPUID_ENLIGHTMENT_INFO, R_EAX) &
1607 HV_NO_NONARCH_CORESHARING;
1608 }
1609
1610 c = &cpuid_ent[cpuid_i++];
1611 c->function = HV_CPUID_IMPLEMENT_LIMITS;
1612 c->eax = cpu->hv_max_vps;
1613 c->ebx = cpu->hyperv_limits[0];
1614 c->ecx = cpu->hyperv_limits[1];
1615 c->edx = cpu->hyperv_limits[2];
1616
1617 if (nested_eax) {
1618 uint32_t function;
1619
1620 /* Create zeroed 0x40000006..0x40000009 leaves */
1621 for (function = HV_CPUID_IMPLEMENT_LIMITS + 1;
1622 function < HV_CPUID_NESTED_FEATURES; function++) {
1623 c = &cpuid_ent[cpuid_i++];
1624 c->function = function;
1625 }
1626
1627 c = &cpuid_ent[cpuid_i++];
1628 c->function = HV_CPUID_NESTED_FEATURES;
1629 c->eax = nested_eax;
1630 }
1631
1632 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNDBG)) {
1633 c = &cpuid_ent[cpuid_i++];
1634 c->function = HV_CPUID_SYNDBG_VENDOR_AND_MAX_FUNCTIONS;
1635 c->eax = hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS) ?
1636 HV_CPUID_NESTED_FEATURES : HV_CPUID_IMPLEMENT_LIMITS;
1637 memcpy(signature, "Microsoft VS", 12);
1638 c->eax = 0;
1639 c->ebx = signature[0];
1640 c->ecx = signature[1];
1641 c->edx = signature[2];
1642
1643 c = &cpuid_ent[cpuid_i++];
1644 c->function = HV_CPUID_SYNDBG_INTERFACE;
1645 memcpy(signature, "VS#1\0\0\0\0\0\0\0\0", 12);
1646 c->eax = signature[0];
1647 c->ebx = 0;
1648 c->ecx = 0;
1649 c->edx = 0;
1650
1651 c = &cpuid_ent[cpuid_i++];
1652 c->function = HV_CPUID_SYNDBG_PLATFORM_CAPABILITIES;
1653 c->eax = HV_SYNDBG_CAP_ALLOW_KERNEL_DEBUGGING;
1654 c->ebx = 0;
1655 c->ecx = 0;
1656 c->edx = 0;
1657 }
1658
1659 return cpuid_i;
1660 }
1661
1662 static Error *hv_passthrough_mig_blocker;
1663 static Error *hv_no_nonarch_cs_mig_blocker;
1664
1665 /* Checks that the exposed eVMCS version range is supported by KVM */
evmcs_version_supported(uint16_t evmcs_version,uint16_t supported_evmcs_version)1666 static bool evmcs_version_supported(uint16_t evmcs_version,
1667 uint16_t supported_evmcs_version)
1668 {
1669 uint8_t min_version = evmcs_version & 0xff;
1670 uint8_t max_version = evmcs_version >> 8;
1671 uint8_t min_supported_version = supported_evmcs_version & 0xff;
1672 uint8_t max_supported_version = supported_evmcs_version >> 8;
1673
1674 return (min_version >= min_supported_version) &&
1675 (max_version <= max_supported_version);
1676 }
1677
hyperv_init_vcpu(X86CPU * cpu)1678 static int hyperv_init_vcpu(X86CPU *cpu)
1679 {
1680 CPUState *cs = CPU(cpu);
1681 Error *local_err = NULL;
1682 int ret;
1683
1684 if (cpu->hyperv_passthrough && hv_passthrough_mig_blocker == NULL) {
1685 error_setg(&hv_passthrough_mig_blocker,
1686 "'hv-passthrough' CPU flag prevents migration, use explicit"
1687 " set of hv-* flags instead");
1688 ret = migrate_add_blocker(&hv_passthrough_mig_blocker, &local_err);
1689 if (ret < 0) {
1690 error_report_err(local_err);
1691 return ret;
1692 }
1693 }
1694
1695 if (cpu->hyperv_no_nonarch_cs == ON_OFF_AUTO_AUTO &&
1696 hv_no_nonarch_cs_mig_blocker == NULL) {
1697 error_setg(&hv_no_nonarch_cs_mig_blocker,
1698 "'hv-no-nonarch-coresharing=auto' CPU flag prevents migration"
1699 " use explicit 'hv-no-nonarch-coresharing=on' instead (but"
1700 " make sure SMT is disabled and/or that vCPUs are properly"
1701 " pinned)");
1702 ret = migrate_add_blocker(&hv_no_nonarch_cs_mig_blocker, &local_err);
1703 if (ret < 0) {
1704 error_report_err(local_err);
1705 return ret;
1706 }
1707 }
1708
1709 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX) && !hv_vpindex_settable) {
1710 /*
1711 * the kernel doesn't support setting vp_index; assert that its value
1712 * is in sync
1713 */
1714 uint64_t value;
1715
1716 ret = kvm_get_one_msr(cpu, HV_X64_MSR_VP_INDEX, &value);
1717 if (ret < 0) {
1718 return ret;
1719 }
1720
1721 if (value != hyperv_vp_index(CPU(cpu))) {
1722 error_report("kernel's vp_index != QEMU's vp_index");
1723 return -ENXIO;
1724 }
1725 }
1726
1727 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
1728 uint32_t synic_cap = cpu->hyperv_synic_kvm_only ?
1729 KVM_CAP_HYPERV_SYNIC : KVM_CAP_HYPERV_SYNIC2;
1730 ret = kvm_vcpu_enable_cap(cs, synic_cap, 0);
1731 if (ret < 0) {
1732 error_report("failed to turn on HyperV SynIC in KVM: %s",
1733 strerror(-ret));
1734 return ret;
1735 }
1736
1737 if (!cpu->hyperv_synic_kvm_only) {
1738 ret = hyperv_x86_synic_add(cpu);
1739 if (ret < 0) {
1740 error_report("failed to create HyperV SynIC: %s",
1741 strerror(-ret));
1742 return ret;
1743 }
1744 }
1745 }
1746
1747 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS)) {
1748 uint16_t evmcs_version = DEFAULT_EVMCS_VERSION;
1749 uint16_t supported_evmcs_version;
1750
1751 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_HYPERV_ENLIGHTENED_VMCS, 0,
1752 (uintptr_t)&supported_evmcs_version);
1753
1754 /*
1755 * KVM is required to support EVMCS ver.1. as that's what 'hv-evmcs'
1756 * option sets. Note: we hardcode the maximum supported eVMCS version
1757 * to '1' as well so 'hv-evmcs' feature is migratable even when (and if)
1758 * ver.2 is implemented. A new option (e.g. 'hv-evmcs=2') will then have
1759 * to be added.
1760 */
1761 if (ret < 0) {
1762 error_report("Hyper-V %s is not supported by kernel",
1763 kvm_hyperv_properties[HYPERV_FEAT_EVMCS].desc);
1764 return ret;
1765 }
1766
1767 if (!evmcs_version_supported(evmcs_version, supported_evmcs_version)) {
1768 error_report("eVMCS version range [%d..%d] is not supported by "
1769 "kernel (supported: [%d..%d])", evmcs_version & 0xff,
1770 evmcs_version >> 8, supported_evmcs_version & 0xff,
1771 supported_evmcs_version >> 8);
1772 return -ENOTSUP;
1773 }
1774 }
1775
1776 if (cpu->hyperv_enforce_cpuid) {
1777 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_HYPERV_ENFORCE_CPUID, 0, 1);
1778 if (ret < 0) {
1779 error_report("failed to enable KVM_CAP_HYPERV_ENFORCE_CPUID: %s",
1780 strerror(-ret));
1781 return ret;
1782 }
1783 }
1784
1785 /* Skip SynIC and VP_INDEX since they are hard deps already */
1786 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_STIMER) &&
1787 hyperv_feat_enabled(cpu, HYPERV_FEAT_VAPIC) &&
1788 hyperv_feat_enabled(cpu, HYPERV_FEAT_RUNTIME)) {
1789 hyperv_x86_set_vmbus_recommended_features_enabled();
1790 }
1791
1792 return 0;
1793 }
1794
1795 static Error *invtsc_mig_blocker;
1796
kvm_init_xsave(CPUX86State * env)1797 static void kvm_init_xsave(CPUX86State *env)
1798 {
1799 if (has_xsave2) {
1800 env->xsave_buf_len = QEMU_ALIGN_UP(has_xsave2, 4096);
1801 } else {
1802 env->xsave_buf_len = sizeof(struct kvm_xsave);
1803 }
1804
1805 env->xsave_buf = qemu_memalign(4096, env->xsave_buf_len);
1806 memset(env->xsave_buf, 0, env->xsave_buf_len);
1807 /*
1808 * The allocated storage must be large enough for all of the
1809 * possible XSAVE state components.
1810 */
1811 assert(kvm_arch_get_supported_cpuid(kvm_state, 0xd, 0, R_ECX) <=
1812 env->xsave_buf_len);
1813 }
1814
kvm_init_nested_state(CPUX86State * env)1815 static void kvm_init_nested_state(CPUX86State *env)
1816 {
1817 struct kvm_vmx_nested_state_hdr *vmx_hdr;
1818 uint32_t size;
1819
1820 if (!env->nested_state) {
1821 return;
1822 }
1823
1824 size = env->nested_state->size;
1825
1826 memset(env->nested_state, 0, size);
1827 env->nested_state->size = size;
1828
1829 if (cpu_has_vmx(env)) {
1830 env->nested_state->format = KVM_STATE_NESTED_FORMAT_VMX;
1831 vmx_hdr = &env->nested_state->hdr.vmx;
1832 vmx_hdr->vmxon_pa = -1ull;
1833 vmx_hdr->vmcs12_pa = -1ull;
1834 } else if (cpu_has_svm(env)) {
1835 env->nested_state->format = KVM_STATE_NESTED_FORMAT_SVM;
1836 }
1837 }
1838
kvm_x86_build_cpuid(CPUX86State * env,struct kvm_cpuid_entry2 * entries,uint32_t cpuid_i)1839 uint32_t kvm_x86_build_cpuid(CPUX86State *env, struct kvm_cpuid_entry2 *entries,
1840 uint32_t cpuid_i)
1841 {
1842 uint32_t limit, i, j;
1843 uint32_t unused;
1844 struct kvm_cpuid_entry2 *c;
1845
1846 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
1847
1848 for (i = 0; i <= limit; i++) {
1849 j = 0;
1850 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1851 goto full;
1852 }
1853 c = &entries[cpuid_i++];
1854 switch (i) {
1855 case 2: {
1856 /* Keep reading function 2 till all the input is received */
1857 int times;
1858
1859 c->function = i;
1860 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1861 times = c->eax & 0xff;
1862 if (times > 1) {
1863 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
1864 KVM_CPUID_FLAG_STATE_READ_NEXT;
1865 }
1866
1867 for (j = 1; j < times; ++j) {
1868 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1869 goto full;
1870 }
1871 c = &entries[cpuid_i++];
1872 c->function = i;
1873 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
1874 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1875 }
1876 break;
1877 }
1878 case 0x1f:
1879 if (!x86_has_cpuid_0x1f(env_archcpu(env))) {
1880 cpuid_i--;
1881 break;
1882 }
1883 /* fallthrough */
1884 case 4:
1885 case 0xb:
1886 case 0xd:
1887 for (j = 0; ; j++) {
1888 c->function = i;
1889 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1890 c->index = j;
1891 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
1892
1893 if (i == 4 && c->eax == 0) {
1894 break;
1895 }
1896 if (i == 0xb && !(c->ecx & 0xff00)) {
1897 break;
1898 }
1899 if (i == 0x1f && !(c->ecx & 0xff00)) {
1900 break;
1901 }
1902 if (i == 0xd && c->eax == 0) {
1903 if (j < 63) {
1904 continue;
1905 } else {
1906 cpuid_i--;
1907 break;
1908 }
1909 }
1910 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1911 goto full;
1912 }
1913 c = &entries[cpuid_i++];
1914 }
1915 break;
1916 case 0x12:
1917 for (j = 0; ; j++) {
1918 c->function = i;
1919 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1920 c->index = j;
1921 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
1922
1923 if (j > 1 && (c->eax & 0xf) != 1) {
1924 break;
1925 }
1926
1927 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1928 goto full;
1929 }
1930 c = &entries[cpuid_i++];
1931 }
1932 break;
1933 case 0x7:
1934 case 0x14:
1935 case 0x1d:
1936 case 0x1e:
1937 case 0x24: {
1938 uint32_t times;
1939
1940 c->function = i;
1941 c->index = 0;
1942 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1943 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1944 times = c->eax;
1945
1946 for (j = 1; j <= times; ++j) {
1947 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1948 goto full;
1949 }
1950 c = &entries[cpuid_i++];
1951 c->function = i;
1952 c->index = j;
1953 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1954 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
1955 }
1956 break;
1957 }
1958 default:
1959 c->function = i;
1960 c->flags = 0;
1961 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1962 if (!c->eax && !c->ebx && !c->ecx && !c->edx) {
1963 /*
1964 * KVM already returns all zeroes if a CPUID entry is missing,
1965 * so we can omit it and avoid hitting KVM's 80-entry limit.
1966 */
1967 cpuid_i--;
1968 }
1969 break;
1970 }
1971 }
1972
1973 if (limit >= 0x0a) {
1974 uint32_t eax, edx;
1975
1976 cpu_x86_cpuid(env, 0x0a, 0, &eax, &unused, &unused, &edx);
1977
1978 has_architectural_pmu_version = eax & 0xff;
1979 if (has_architectural_pmu_version > 0) {
1980 num_architectural_pmu_gp_counters = (eax & 0xff00) >> 8;
1981
1982 /* Shouldn't be more than 32, since that's the number of bits
1983 * available in EBX to tell us _which_ counters are available.
1984 * Play it safe.
1985 */
1986 if (num_architectural_pmu_gp_counters > MAX_GP_COUNTERS) {
1987 num_architectural_pmu_gp_counters = MAX_GP_COUNTERS;
1988 }
1989
1990 if (has_architectural_pmu_version > 1) {
1991 num_architectural_pmu_fixed_counters = edx & 0x1f;
1992
1993 if (num_architectural_pmu_fixed_counters > MAX_FIXED_COUNTERS) {
1994 num_architectural_pmu_fixed_counters = MAX_FIXED_COUNTERS;
1995 }
1996 }
1997 }
1998 }
1999
2000 cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
2001
2002 for (i = 0x80000000; i <= limit; i++) {
2003 j = 0;
2004 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
2005 goto full;
2006 }
2007 c = &entries[cpuid_i++];
2008
2009 switch (i) {
2010 case 0x8000001d:
2011 /* Query for all AMD cache information leaves */
2012 for (j = 0; ; j++) {
2013 c->function = i;
2014 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2015 c->index = j;
2016 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
2017
2018 if (c->eax == 0) {
2019 break;
2020 }
2021 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
2022 goto full;
2023 }
2024 c = &entries[cpuid_i++];
2025 }
2026 break;
2027 default:
2028 c->function = i;
2029 c->flags = 0;
2030 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
2031 if (!c->eax && !c->ebx && !c->ecx && !c->edx) {
2032 /*
2033 * KVM already returns all zeroes if a CPUID entry is missing,
2034 * so we can omit it and avoid hitting KVM's 80-entry limit.
2035 */
2036 cpuid_i--;
2037 }
2038 break;
2039 }
2040 }
2041
2042 /* Call Centaur's CPUID instructions they are supported. */
2043 if (env->cpuid_xlevel2 > 0) {
2044 cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
2045
2046 for (i = 0xC0000000; i <= limit; i++) {
2047 j = 0;
2048 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
2049 goto full;
2050 }
2051 c = &entries[cpuid_i++];
2052
2053 c->function = i;
2054 c->flags = 0;
2055 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
2056 }
2057 }
2058
2059 return cpuid_i;
2060
2061 full:
2062 fprintf(stderr, "cpuid_data is full, no space for "
2063 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
2064 abort();
2065 }
2066
kvm_arch_pre_create_vcpu(CPUState * cpu,Error ** errp)2067 int kvm_arch_pre_create_vcpu(CPUState *cpu, Error **errp)
2068 {
2069 if (is_tdx_vm()) {
2070 return tdx_pre_create_vcpu(cpu, errp);
2071 }
2072
2073 return 0;
2074 }
2075
kvm_arch_init_vcpu(CPUState * cs)2076 int kvm_arch_init_vcpu(CPUState *cs)
2077 {
2078 struct {
2079 struct kvm_cpuid2 cpuid;
2080 struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES];
2081 } cpuid_data;
2082 /*
2083 * The kernel defines these structs with padding fields so there
2084 * should be no extra padding in our cpuid_data struct.
2085 */
2086 QEMU_BUILD_BUG_ON(sizeof(cpuid_data) !=
2087 sizeof(struct kvm_cpuid2) +
2088 sizeof(struct kvm_cpuid_entry2) * KVM_MAX_CPUID_ENTRIES);
2089
2090 X86CPU *cpu = X86_CPU(cs);
2091 CPUX86State *env = &cpu->env;
2092 uint32_t cpuid_i;
2093 struct kvm_cpuid_entry2 *c;
2094 uint32_t signature[3];
2095 int kvm_base = KVM_CPUID_SIGNATURE;
2096 int max_nested_state_len;
2097 int r;
2098 Error *local_err = NULL;
2099
2100 if (current_machine->cgs) {
2101 r = x86_confidential_guest_check_features(
2102 X86_CONFIDENTIAL_GUEST(current_machine->cgs), cs);
2103 if (r < 0) {
2104 return r;
2105 }
2106 }
2107
2108 memset(&cpuid_data, 0, sizeof(cpuid_data));
2109
2110 cpuid_i = 0;
2111
2112 has_xsave2 = kvm_check_extension(cs->kvm_state, KVM_CAP_XSAVE2);
2113
2114 r = kvm_arch_set_tsc_khz(cs);
2115 if (r < 0) {
2116 return r;
2117 }
2118
2119 /* vcpu's TSC frequency is either specified by user, or following
2120 * the value used by KVM if the former is not present. In the
2121 * latter case, we query it from KVM and record in env->tsc_khz,
2122 * so that vcpu's TSC frequency can be migrated later via this field.
2123 */
2124 if (!env->tsc_khz) {
2125 r = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
2126 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
2127 -ENOTSUP;
2128 if (r > 0) {
2129 env->tsc_khz = r;
2130 }
2131 }
2132
2133 env->apic_bus_freq = KVM_APIC_BUS_FREQUENCY;
2134
2135 /*
2136 * kvm_hyperv_expand_features() is called here for the second time in case
2137 * KVM_CAP_SYS_HYPERV_CPUID is not supported. While we can't possibly handle
2138 * 'query-cpu-model-expansion' in this case as we don't have a KVM vCPU to
2139 * check which Hyper-V enlightenments are supported and which are not, we
2140 * can still proceed and check/expand Hyper-V enlightenments here so legacy
2141 * behavior is preserved.
2142 */
2143 if (!kvm_hyperv_expand_features(cpu, &local_err)) {
2144 error_report_err(local_err);
2145 return -ENOSYS;
2146 }
2147
2148 if (hyperv_enabled(cpu)) {
2149 r = hyperv_init_vcpu(cpu);
2150 if (r) {
2151 return r;
2152 }
2153
2154 cpuid_i = hyperv_fill_cpuids(cs, cpuid_data.entries);
2155 kvm_base = KVM_CPUID_SIGNATURE_NEXT;
2156 has_msr_hv_hypercall = true;
2157 }
2158
2159 if (cs->kvm_state->xen_version) {
2160 #ifdef CONFIG_XEN_EMU
2161 struct kvm_cpuid_entry2 *xen_max_leaf;
2162
2163 memcpy(signature, "XenVMMXenVMM", 12);
2164
2165 xen_max_leaf = c = &cpuid_data.entries[cpuid_i++];
2166 c->function = kvm_base + XEN_CPUID_SIGNATURE;
2167 c->eax = kvm_base + XEN_CPUID_TIME;
2168 c->ebx = signature[0];
2169 c->ecx = signature[1];
2170 c->edx = signature[2];
2171
2172 c = &cpuid_data.entries[cpuid_i++];
2173 c->function = kvm_base + XEN_CPUID_VENDOR;
2174 c->eax = cs->kvm_state->xen_version;
2175 c->ebx = 0;
2176 c->ecx = 0;
2177 c->edx = 0;
2178
2179 c = &cpuid_data.entries[cpuid_i++];
2180 c->function = kvm_base + XEN_CPUID_HVM_MSR;
2181 /* Number of hypercall-transfer pages */
2182 c->eax = 1;
2183 /* Hypercall MSR base address */
2184 if (hyperv_enabled(cpu)) {
2185 c->ebx = XEN_HYPERCALL_MSR_HYPERV;
2186 kvm_xen_init(cs->kvm_state, c->ebx);
2187 } else {
2188 c->ebx = XEN_HYPERCALL_MSR;
2189 }
2190 c->ecx = 0;
2191 c->edx = 0;
2192
2193 c = &cpuid_data.entries[cpuid_i++];
2194 c->function = kvm_base + XEN_CPUID_TIME;
2195 c->eax = ((!!tsc_is_stable_and_known(env) << 1) |
2196 (!!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_RDTSCP) << 2));
2197 /* default=0 (emulate if necessary) */
2198 c->ebx = 0;
2199 /* guest tsc frequency */
2200 c->ecx = env->user_tsc_khz;
2201 /* guest tsc incarnation (migration count) */
2202 c->edx = 0;
2203
2204 c = &cpuid_data.entries[cpuid_i++];
2205 c->function = kvm_base + XEN_CPUID_HVM;
2206 xen_max_leaf->eax = kvm_base + XEN_CPUID_HVM;
2207 if (cs->kvm_state->xen_version >= XEN_VERSION(4, 5)) {
2208 c->function = kvm_base + XEN_CPUID_HVM;
2209
2210 if (cpu->xen_vapic) {
2211 c->eax |= XEN_HVM_CPUID_APIC_ACCESS_VIRT;
2212 c->eax |= XEN_HVM_CPUID_X2APIC_VIRT;
2213 }
2214
2215 c->eax |= XEN_HVM_CPUID_IOMMU_MAPPINGS;
2216
2217 if (cs->kvm_state->xen_version >= XEN_VERSION(4, 6)) {
2218 c->eax |= XEN_HVM_CPUID_VCPU_ID_PRESENT;
2219 c->ebx = cs->cpu_index;
2220 }
2221
2222 if (cs->kvm_state->xen_version >= XEN_VERSION(4, 17)) {
2223 c->eax |= XEN_HVM_CPUID_UPCALL_VECTOR;
2224 }
2225 }
2226
2227 r = kvm_xen_init_vcpu(cs);
2228 if (r) {
2229 return r;
2230 }
2231
2232 kvm_base += 0x100;
2233 #else /* CONFIG_XEN_EMU */
2234 /* This should never happen as kvm_arch_init() would have died first. */
2235 fprintf(stderr, "Cannot enable Xen CPUID without Xen support\n");
2236 abort();
2237 #endif
2238 } else if (cpu->expose_kvm) {
2239 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
2240 c = &cpuid_data.entries[cpuid_i++];
2241 c->function = KVM_CPUID_SIGNATURE | kvm_base;
2242 c->eax = KVM_CPUID_FEATURES | kvm_base;
2243 c->ebx = signature[0];
2244 c->ecx = signature[1];
2245 c->edx = signature[2];
2246
2247 c = &cpuid_data.entries[cpuid_i++];
2248 c->function = KVM_CPUID_FEATURES | kvm_base;
2249 c->eax = env->features[FEAT_KVM];
2250 c->edx = env->features[FEAT_KVM_HINTS];
2251 }
2252
2253 if (cpu->kvm_pv_enforce_cpuid) {
2254 r = kvm_vcpu_enable_cap(cs, KVM_CAP_ENFORCE_PV_FEATURE_CPUID, 0, 1);
2255 if (r < 0) {
2256 fprintf(stderr,
2257 "failed to enable KVM_CAP_ENFORCE_PV_FEATURE_CPUID: %s",
2258 strerror(-r));
2259 abort();
2260 }
2261 }
2262
2263 cpuid_i = kvm_x86_build_cpuid(env, cpuid_data.entries, cpuid_i);
2264 cpuid_data.cpuid.nent = cpuid_i;
2265
2266 if (x86_cpu_family(env->cpuid_version) >= 6
2267 && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
2268 (CPUID_MCE | CPUID_MCA)) {
2269 uint64_t mcg_cap, unsupported_caps;
2270 int banks;
2271 int ret;
2272
2273 ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks);
2274 if (ret < 0) {
2275 fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
2276 return ret;
2277 }
2278
2279 if (banks < (env->mcg_cap & MCG_CAP_BANKS_MASK)) {
2280 error_report("kvm: Unsupported MCE bank count (QEMU = %d, KVM = %d)",
2281 (int)(env->mcg_cap & MCG_CAP_BANKS_MASK), banks);
2282 return -ENOTSUP;
2283 }
2284
2285 unsupported_caps = env->mcg_cap & ~(mcg_cap | MCG_CAP_BANKS_MASK);
2286 if (unsupported_caps) {
2287 if (unsupported_caps & MCG_LMCE_P) {
2288 error_report("kvm: LMCE not supported");
2289 return -ENOTSUP;
2290 }
2291 warn_report("Unsupported MCG_CAP bits: 0x%" PRIx64,
2292 unsupported_caps);
2293 }
2294
2295 env->mcg_cap &= mcg_cap | MCG_CAP_BANKS_MASK;
2296 ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &env->mcg_cap);
2297 if (ret < 0) {
2298 fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
2299 return ret;
2300 }
2301 }
2302
2303 cpu->vmsentry = qemu_add_vm_change_state_handler(cpu_update_state, env);
2304
2305 c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0);
2306 if (c) {
2307 has_msr_feature_control = !!(c->ecx & CPUID_EXT_VMX) ||
2308 !!(c->ecx & CPUID_EXT_SMX);
2309 }
2310
2311 c = cpuid_find_entry(&cpuid_data.cpuid, 7, 0);
2312 if (c && (c->ebx & CPUID_7_0_EBX_SGX)) {
2313 has_msr_feature_control = true;
2314 }
2315
2316 if (env->mcg_cap & MCG_LMCE_P) {
2317 has_msr_mcg_ext_ctl = has_msr_feature_control = true;
2318 }
2319
2320 if (!env->user_tsc_khz) {
2321 if ((env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC) &&
2322 invtsc_mig_blocker == NULL) {
2323 error_setg(&invtsc_mig_blocker,
2324 "State blocked by non-migratable CPU device"
2325 " (invtsc flag)");
2326 r = migrate_add_blocker(&invtsc_mig_blocker, &local_err);
2327 if (r < 0) {
2328 error_report_err(local_err);
2329 return r;
2330 }
2331 }
2332 }
2333
2334 if (cpu->vmware_cpuid_freq
2335 /* Guests depend on 0x40000000 to detect this feature, so only expose
2336 * it if KVM exposes leaf 0x40000000. (Conflicts with Hyper-V) */
2337 && cpu->expose_kvm
2338 && kvm_base == KVM_CPUID_SIGNATURE
2339 /* TSC clock must be stable and known for this feature. */
2340 && tsc_is_stable_and_known(env)) {
2341
2342 c = &cpuid_data.entries[cpuid_i++];
2343 c->function = KVM_CPUID_SIGNATURE | 0x10;
2344 c->eax = env->tsc_khz;
2345 c->ebx = env->apic_bus_freq / 1000; /* Hz to KHz */
2346 c->ecx = c->edx = 0;
2347
2348 c = cpuid_find_entry(&cpuid_data.cpuid, kvm_base, 0);
2349 c->eax = MAX(c->eax, KVM_CPUID_SIGNATURE | 0x10);
2350 }
2351
2352 cpuid_data.cpuid.nent = cpuid_i;
2353
2354 cpuid_data.cpuid.padding = 0;
2355 r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data);
2356 if (r) {
2357 goto fail;
2358 }
2359 kvm_init_xsave(env);
2360
2361 max_nested_state_len = kvm_max_nested_state_length();
2362 if (max_nested_state_len > 0) {
2363 assert(max_nested_state_len >= offsetof(struct kvm_nested_state, data));
2364
2365 if (cpu_has_vmx(env) || cpu_has_svm(env)) {
2366 env->nested_state = g_malloc0(max_nested_state_len);
2367 env->nested_state->size = max_nested_state_len;
2368
2369 kvm_init_nested_state(env);
2370 }
2371 }
2372
2373 cpu->kvm_msr_buf = g_malloc0(MSR_BUF_SIZE);
2374
2375 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_RDTSCP)) {
2376 has_msr_tsc_aux = false;
2377 }
2378
2379 kvm_init_msrs(cpu);
2380
2381 return 0;
2382
2383 fail:
2384 migrate_del_blocker(&invtsc_mig_blocker);
2385
2386 return r;
2387 }
2388
kvm_arch_destroy_vcpu(CPUState * cs)2389 int kvm_arch_destroy_vcpu(CPUState *cs)
2390 {
2391 X86CPU *cpu = X86_CPU(cs);
2392 CPUX86State *env = &cpu->env;
2393
2394 g_free(env->xsave_buf);
2395
2396 g_free(cpu->kvm_msr_buf);
2397 cpu->kvm_msr_buf = NULL;
2398
2399 g_free(env->nested_state);
2400 env->nested_state = NULL;
2401
2402 qemu_del_vm_change_state_handler(cpu->vmsentry);
2403
2404 return 0;
2405 }
2406
kvm_arch_reset_vcpu(X86CPU * cpu)2407 void kvm_arch_reset_vcpu(X86CPU *cpu)
2408 {
2409 CPUX86State *env = &cpu->env;
2410
2411 env->xcr0 = 1;
2412 if (kvm_irqchip_in_kernel()) {
2413 env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
2414 KVM_MP_STATE_UNINITIALIZED;
2415 } else {
2416 env->mp_state = KVM_MP_STATE_RUNNABLE;
2417 }
2418
2419 /* enabled by default */
2420 env->poll_control_msr = 1;
2421
2422 kvm_init_nested_state(env);
2423
2424 sev_es_set_reset_vector(CPU(cpu));
2425 }
2426
kvm_arch_after_reset_vcpu(X86CPU * cpu)2427 void kvm_arch_after_reset_vcpu(X86CPU *cpu)
2428 {
2429 CPUX86State *env = &cpu->env;
2430 int i;
2431
2432 /*
2433 * Reset SynIC after all other devices have been reset to let them remove
2434 * their SINT routes first.
2435 */
2436 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
2437 for (i = 0; i < ARRAY_SIZE(env->msr_hv_synic_sint); i++) {
2438 env->msr_hv_synic_sint[i] = HV_SINT_MASKED;
2439 }
2440
2441 hyperv_x86_synic_reset(cpu);
2442 }
2443 }
2444
kvm_arch_reset_parked_vcpu(unsigned long vcpu_id,int kvm_fd)2445 void kvm_arch_reset_parked_vcpu(unsigned long vcpu_id, int kvm_fd)
2446 {
2447 g_autofree struct kvm_msrs *msrs = NULL;
2448
2449 msrs = g_malloc0(sizeof(*msrs) + sizeof(msrs->entries[0]));
2450 msrs->entries[0].index = MSR_IA32_TSC;
2451 msrs->entries[0].data = 1; /* match the value in x86_cpu_reset() */
2452 msrs->nmsrs++;
2453
2454 if (ioctl(kvm_fd, KVM_SET_MSRS, msrs) != 1) {
2455 warn_report("parked vCPU %lu TSC reset failed: %d",
2456 vcpu_id, errno);
2457 }
2458 }
2459
kvm_arch_do_init_vcpu(X86CPU * cpu)2460 void kvm_arch_do_init_vcpu(X86CPU *cpu)
2461 {
2462 CPUX86State *env = &cpu->env;
2463
2464 /* APs get directly into wait-for-SIPI state. */
2465 if (env->mp_state == KVM_MP_STATE_UNINITIALIZED) {
2466 env->mp_state = KVM_MP_STATE_INIT_RECEIVED;
2467 }
2468 }
2469
kvm_get_supported_feature_msrs(KVMState * s)2470 static int kvm_get_supported_feature_msrs(KVMState *s)
2471 {
2472 int ret = 0;
2473
2474 if (kvm_feature_msrs != NULL) {
2475 return 0;
2476 }
2477
2478 if (!kvm_check_extension(s, KVM_CAP_GET_MSR_FEATURES)) {
2479 return 0;
2480 }
2481
2482 struct kvm_msr_list msr_list;
2483
2484 msr_list.nmsrs = 0;
2485 ret = kvm_ioctl(s, KVM_GET_MSR_FEATURE_INDEX_LIST, &msr_list);
2486 if (ret < 0 && ret != -E2BIG) {
2487 error_report("Fetch KVM feature MSR list failed: %s",
2488 strerror(-ret));
2489 return ret;
2490 }
2491
2492 assert(msr_list.nmsrs > 0);
2493 kvm_feature_msrs = g_malloc0(sizeof(msr_list) +
2494 msr_list.nmsrs * sizeof(msr_list.indices[0]));
2495
2496 kvm_feature_msrs->nmsrs = msr_list.nmsrs;
2497 ret = kvm_ioctl(s, KVM_GET_MSR_FEATURE_INDEX_LIST, kvm_feature_msrs);
2498
2499 if (ret < 0) {
2500 error_report("Fetch KVM feature MSR list failed: %s",
2501 strerror(-ret));
2502 g_free(kvm_feature_msrs);
2503 kvm_feature_msrs = NULL;
2504 return ret;
2505 }
2506
2507 return 0;
2508 }
2509
kvm_get_supported_msrs(KVMState * s)2510 static int kvm_get_supported_msrs(KVMState *s)
2511 {
2512 int ret = 0;
2513 struct kvm_msr_list msr_list, *kvm_msr_list;
2514
2515 /*
2516 * Obtain MSR list from KVM. These are the MSRs that we must
2517 * save/restore.
2518 */
2519 msr_list.nmsrs = 0;
2520 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
2521 if (ret < 0 && ret != -E2BIG) {
2522 return ret;
2523 }
2524 /*
2525 * Old kernel modules had a bug and could write beyond the provided
2526 * memory. Allocate at least a safe amount of 1K.
2527 */
2528 kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
2529 msr_list.nmsrs *
2530 sizeof(msr_list.indices[0])));
2531
2532 kvm_msr_list->nmsrs = msr_list.nmsrs;
2533 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
2534 if (ret >= 0) {
2535 int i;
2536
2537 for (i = 0; i < kvm_msr_list->nmsrs; i++) {
2538 switch (kvm_msr_list->indices[i]) {
2539 case MSR_STAR:
2540 has_msr_star = true;
2541 break;
2542 case MSR_VM_HSAVE_PA:
2543 has_msr_hsave_pa = true;
2544 break;
2545 case MSR_TSC_AUX:
2546 has_msr_tsc_aux = true;
2547 break;
2548 case MSR_TSC_ADJUST:
2549 has_msr_tsc_adjust = true;
2550 break;
2551 case MSR_IA32_TSCDEADLINE:
2552 has_msr_tsc_deadline = true;
2553 break;
2554 case MSR_IA32_SMBASE:
2555 has_msr_smbase = true;
2556 break;
2557 case MSR_SMI_COUNT:
2558 has_msr_smi_count = true;
2559 break;
2560 case MSR_IA32_MISC_ENABLE:
2561 has_msr_misc_enable = true;
2562 break;
2563 case MSR_IA32_BNDCFGS:
2564 has_msr_bndcfgs = true;
2565 break;
2566 case MSR_IA32_XSS:
2567 has_msr_xss = true;
2568 break;
2569 case MSR_IA32_UMWAIT_CONTROL:
2570 has_msr_umwait = true;
2571 break;
2572 case HV_X64_MSR_CRASH_CTL:
2573 has_msr_hv_crash = true;
2574 break;
2575 case HV_X64_MSR_RESET:
2576 has_msr_hv_reset = true;
2577 break;
2578 case HV_X64_MSR_VP_INDEX:
2579 has_msr_hv_vpindex = true;
2580 break;
2581 case HV_X64_MSR_VP_RUNTIME:
2582 has_msr_hv_runtime = true;
2583 break;
2584 case HV_X64_MSR_SCONTROL:
2585 has_msr_hv_synic = true;
2586 break;
2587 case HV_X64_MSR_STIMER0_CONFIG:
2588 has_msr_hv_stimer = true;
2589 break;
2590 case HV_X64_MSR_TSC_FREQUENCY:
2591 has_msr_hv_frequencies = true;
2592 break;
2593 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2594 has_msr_hv_reenlightenment = true;
2595 break;
2596 case HV_X64_MSR_SYNDBG_OPTIONS:
2597 has_msr_hv_syndbg_options = true;
2598 break;
2599 case MSR_IA32_SPEC_CTRL:
2600 has_msr_spec_ctrl = true;
2601 break;
2602 case MSR_AMD64_TSC_RATIO:
2603 has_tsc_scale_msr = true;
2604 break;
2605 case MSR_IA32_TSX_CTRL:
2606 has_msr_tsx_ctrl = true;
2607 break;
2608 case MSR_VIRT_SSBD:
2609 has_msr_virt_ssbd = true;
2610 break;
2611 case MSR_IA32_ARCH_CAPABILITIES:
2612 has_msr_arch_capabs = true;
2613 break;
2614 case MSR_IA32_CORE_CAPABILITY:
2615 has_msr_core_capabs = true;
2616 break;
2617 case MSR_IA32_PERF_CAPABILITIES:
2618 has_msr_perf_capabs = true;
2619 break;
2620 case MSR_IA32_VMX_VMFUNC:
2621 has_msr_vmx_vmfunc = true;
2622 break;
2623 case MSR_IA32_UCODE_REV:
2624 has_msr_ucode_rev = true;
2625 break;
2626 case MSR_IA32_VMX_PROCBASED_CTLS2:
2627 has_msr_vmx_procbased_ctls2 = true;
2628 break;
2629 case MSR_IA32_PKRS:
2630 has_msr_pkrs = true;
2631 break;
2632 case MSR_K7_HWCR:
2633 has_msr_hwcr = true;
2634 }
2635 }
2636 }
2637
2638 g_free(kvm_msr_list);
2639
2640 return ret;
2641 }
2642
kvm_rdmsr_core_thread_count(X86CPU * cpu,uint32_t msr,uint64_t * val)2643 static bool kvm_rdmsr_core_thread_count(X86CPU *cpu,
2644 uint32_t msr,
2645 uint64_t *val)
2646 {
2647 *val = cpu_x86_get_msr_core_thread_count(cpu);
2648
2649 return true;
2650 }
2651
kvm_rdmsr_rapl_power_unit(X86CPU * cpu,uint32_t msr,uint64_t * val)2652 static bool kvm_rdmsr_rapl_power_unit(X86CPU *cpu,
2653 uint32_t msr,
2654 uint64_t *val)
2655 {
2656
2657 CPUState *cs = CPU(cpu);
2658
2659 *val = cs->kvm_state->msr_energy.msr_unit;
2660
2661 return true;
2662 }
2663
kvm_rdmsr_pkg_power_limit(X86CPU * cpu,uint32_t msr,uint64_t * val)2664 static bool kvm_rdmsr_pkg_power_limit(X86CPU *cpu,
2665 uint32_t msr,
2666 uint64_t *val)
2667 {
2668
2669 CPUState *cs = CPU(cpu);
2670
2671 *val = cs->kvm_state->msr_energy.msr_limit;
2672
2673 return true;
2674 }
2675
kvm_rdmsr_pkg_power_info(X86CPU * cpu,uint32_t msr,uint64_t * val)2676 static bool kvm_rdmsr_pkg_power_info(X86CPU *cpu,
2677 uint32_t msr,
2678 uint64_t *val)
2679 {
2680
2681 CPUState *cs = CPU(cpu);
2682
2683 *val = cs->kvm_state->msr_energy.msr_info;
2684
2685 return true;
2686 }
2687
kvm_rdmsr_pkg_energy_status(X86CPU * cpu,uint32_t msr,uint64_t * val)2688 static bool kvm_rdmsr_pkg_energy_status(X86CPU *cpu,
2689 uint32_t msr,
2690 uint64_t *val)
2691 {
2692
2693 CPUState *cs = CPU(cpu);
2694 *val = cs->kvm_state->msr_energy.msr_value[cs->cpu_index];
2695
2696 return true;
2697 }
2698
2699 static Notifier smram_machine_done;
2700 static KVMMemoryListener smram_listener;
2701 static AddressSpace smram_address_space;
2702 static MemoryRegion smram_as_root;
2703 static MemoryRegion smram_as_mem;
2704
register_smram_listener(Notifier * n,void * unused)2705 static void register_smram_listener(Notifier *n, void *unused)
2706 {
2707 CPUState *cpu;
2708 MemoryRegion *smram =
2709 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
2710
2711 /* Outer container... */
2712 memory_region_init(&smram_as_root, OBJECT(kvm_state), "mem-container-smram", ~0ull);
2713 memory_region_set_enabled(&smram_as_root, true);
2714
2715 /* ... with two regions inside: normal system memory with low
2716 * priority, and...
2717 */
2718 memory_region_init_alias(&smram_as_mem, OBJECT(kvm_state), "mem-smram",
2719 get_system_memory(), 0, ~0ull);
2720 memory_region_add_subregion_overlap(&smram_as_root, 0, &smram_as_mem, 0);
2721 memory_region_set_enabled(&smram_as_mem, true);
2722
2723 if (smram) {
2724 /* ... SMRAM with higher priority */
2725 memory_region_add_subregion_overlap(&smram_as_root, 0, smram, 10);
2726 memory_region_set_enabled(smram, true);
2727 }
2728
2729 address_space_init(&smram_address_space, &smram_as_root, "KVM-SMRAM");
2730 kvm_memory_listener_register(kvm_state, &smram_listener,
2731 &smram_address_space, X86ASIdx_SMM, "kvm-smram");
2732
2733 CPU_FOREACH(cpu) {
2734 cpu_address_space_init(cpu, X86ASIdx_SMM, "cpu-smm", &smram_as_root);
2735 }
2736 }
2737
kvm_msr_energy_thread(void * data)2738 static void *kvm_msr_energy_thread(void *data)
2739 {
2740 KVMState *s = data;
2741 struct KVMMsrEnergy *vmsr = &s->msr_energy;
2742
2743 g_autofree vmsr_package_energy_stat *pkg_stat = NULL;
2744 g_autofree vmsr_thread_stat *thd_stat = NULL;
2745 g_autofree CPUState *cpu = NULL;
2746 g_autofree unsigned int *vpkgs_energy_stat = NULL;
2747 unsigned int num_threads = 0;
2748
2749 X86CPUTopoIDs topo_ids;
2750
2751 rcu_register_thread();
2752
2753 /* Allocate memory for each package energy status */
2754 pkg_stat = g_new0(vmsr_package_energy_stat, vmsr->host_topo.maxpkgs);
2755
2756 /* Allocate memory for thread stats */
2757 thd_stat = g_new0(vmsr_thread_stat, 1);
2758
2759 /* Allocate memory for holding virtual package energy counter */
2760 vpkgs_energy_stat = g_new0(unsigned int, vmsr->guest_vsockets);
2761
2762 /* Populate the max tick of each packages */
2763 for (int i = 0; i < vmsr->host_topo.maxpkgs; i++) {
2764 /*
2765 * Max numbers of ticks per package
2766 * Time in second * Number of ticks/second * Number of cores/package
2767 * ex: 100 ticks/second/CPU, 12 CPUs per Package gives 1200 ticks max
2768 */
2769 vmsr->host_topo.maxticks[i] = (MSR_ENERGY_THREAD_SLEEP_US / 1000000)
2770 * sysconf(_SC_CLK_TCK)
2771 * vmsr->host_topo.pkg_cpu_count[i];
2772 }
2773
2774 while (true) {
2775 /* Get all qemu threads id */
2776 g_autofree pid_t *thread_ids
2777 = vmsr_get_thread_ids(vmsr->pid, &num_threads);
2778
2779 if (thread_ids == NULL) {
2780 goto clean;
2781 }
2782
2783 thd_stat = g_renew(vmsr_thread_stat, thd_stat, num_threads);
2784 /* Unlike g_new0, g_renew0 function doesn't exist yet... */
2785 memset(thd_stat, 0, num_threads * sizeof(vmsr_thread_stat));
2786
2787 /* Populate all the thread stats */
2788 for (int i = 0; i < num_threads; i++) {
2789 thd_stat[i].utime = g_new0(unsigned long long, 2);
2790 thd_stat[i].stime = g_new0(unsigned long long, 2);
2791 thd_stat[i].thread_id = thread_ids[i];
2792 vmsr_read_thread_stat(vmsr->pid,
2793 thd_stat[i].thread_id,
2794 &thd_stat[i].utime[0],
2795 &thd_stat[i].stime[0],
2796 &thd_stat[i].cpu_id);
2797 thd_stat[i].pkg_id =
2798 vmsr_get_physical_package_id(thd_stat[i].cpu_id);
2799 }
2800
2801 /* Retrieve all packages power plane energy counter */
2802 for (int i = 0; i < vmsr->host_topo.maxpkgs; i++) {
2803 for (int j = 0; j < num_threads; j++) {
2804 /*
2805 * Use the first thread we found that ran on the CPU
2806 * of the package to read the packages energy counter
2807 */
2808 if (thd_stat[j].pkg_id == i) {
2809 pkg_stat[i].e_start =
2810 vmsr_read_msr(MSR_PKG_ENERGY_STATUS,
2811 thd_stat[j].cpu_id,
2812 thd_stat[j].thread_id,
2813 s->msr_energy.sioc);
2814 break;
2815 }
2816 }
2817 }
2818
2819 /* Sleep a short period while the other threads are working */
2820 usleep(MSR_ENERGY_THREAD_SLEEP_US);
2821
2822 /*
2823 * Retrieve all packages power plane energy counter
2824 * Calculate the delta of all packages
2825 */
2826 for (int i = 0; i < vmsr->host_topo.maxpkgs; i++) {
2827 for (int j = 0; j < num_threads; j++) {
2828 /*
2829 * Use the first thread we found that ran on the CPU
2830 * of the package to read the packages energy counter
2831 */
2832 if (thd_stat[j].pkg_id == i) {
2833 pkg_stat[i].e_end =
2834 vmsr_read_msr(MSR_PKG_ENERGY_STATUS,
2835 thd_stat[j].cpu_id,
2836 thd_stat[j].thread_id,
2837 s->msr_energy.sioc);
2838 /*
2839 * Prevent the case we have migrate the VM
2840 * during the sleep period or any other cases
2841 * were energy counter might be lower after
2842 * the sleep period.
2843 */
2844 if (pkg_stat[i].e_end > pkg_stat[i].e_start) {
2845 pkg_stat[i].e_delta =
2846 pkg_stat[i].e_end - pkg_stat[i].e_start;
2847 } else {
2848 pkg_stat[i].e_delta = 0;
2849 }
2850 break;
2851 }
2852 }
2853 }
2854
2855 /* Delta of ticks spend by each thread between the sample */
2856 for (int i = 0; i < num_threads; i++) {
2857 vmsr_read_thread_stat(vmsr->pid,
2858 thd_stat[i].thread_id,
2859 &thd_stat[i].utime[1],
2860 &thd_stat[i].stime[1],
2861 &thd_stat[i].cpu_id);
2862
2863 if (vmsr->pid < 0) {
2864 /*
2865 * We don't count the dead thread
2866 * i.e threads that existed before the sleep
2867 * and not anymore
2868 */
2869 thd_stat[i].delta_ticks = 0;
2870 } else {
2871 vmsr_delta_ticks(thd_stat, i);
2872 }
2873 }
2874
2875 /*
2876 * Identify the vcpu threads
2877 * Calculate the number of vcpu per package
2878 */
2879 CPU_FOREACH(cpu) {
2880 for (int i = 0; i < num_threads; i++) {
2881 if (cpu->thread_id == thd_stat[i].thread_id) {
2882 thd_stat[i].is_vcpu = true;
2883 thd_stat[i].vcpu_id = cpu->cpu_index;
2884 pkg_stat[thd_stat[i].pkg_id].nb_vcpu++;
2885 thd_stat[i].acpi_id = kvm_arch_vcpu_id(cpu);
2886 break;
2887 }
2888 }
2889 }
2890
2891 /* Retrieve the virtual package number of each vCPU */
2892 for (int i = 0; i < vmsr->guest_cpu_list->len; i++) {
2893 for (int j = 0; j < num_threads; j++) {
2894 if ((thd_stat[j].acpi_id ==
2895 vmsr->guest_cpu_list->cpus[i].arch_id)
2896 && (thd_stat[j].is_vcpu == true)) {
2897 x86_topo_ids_from_apicid(thd_stat[j].acpi_id,
2898 &vmsr->guest_topo_info, &topo_ids);
2899 thd_stat[j].vpkg_id = topo_ids.pkg_id;
2900 }
2901 }
2902 }
2903
2904 /* Calculate the total energy of all non-vCPU thread */
2905 for (int i = 0; i < num_threads; i++) {
2906 if ((thd_stat[i].is_vcpu != true) &&
2907 (thd_stat[i].delta_ticks > 0)) {
2908 double temp;
2909 temp = vmsr_get_ratio(pkg_stat[thd_stat[i].pkg_id].e_delta,
2910 thd_stat[i].delta_ticks,
2911 vmsr->host_topo.maxticks[thd_stat[i].pkg_id]);
2912 pkg_stat[thd_stat[i].pkg_id].e_ratio
2913 += (uint64_t)lround(temp);
2914 }
2915 }
2916
2917 /* Calculate the ratio per non-vCPU thread of each package */
2918 for (int i = 0; i < vmsr->host_topo.maxpkgs; i++) {
2919 if (pkg_stat[i].nb_vcpu > 0) {
2920 pkg_stat[i].e_ratio = pkg_stat[i].e_ratio / pkg_stat[i].nb_vcpu;
2921 }
2922 }
2923
2924 /*
2925 * Calculate the energy for each Package:
2926 * Energy Package = sum of each vCPU energy that belongs to the package
2927 */
2928 for (int i = 0; i < num_threads; i++) {
2929 if ((thd_stat[i].is_vcpu == true) && \
2930 (thd_stat[i].delta_ticks > 0)) {
2931 double temp;
2932 temp = vmsr_get_ratio(pkg_stat[thd_stat[i].pkg_id].e_delta,
2933 thd_stat[i].delta_ticks,
2934 vmsr->host_topo.maxticks[thd_stat[i].pkg_id]);
2935 vpkgs_energy_stat[thd_stat[i].vpkg_id] +=
2936 (uint64_t)lround(temp);
2937 vpkgs_energy_stat[thd_stat[i].vpkg_id] +=
2938 pkg_stat[thd_stat[i].pkg_id].e_ratio;
2939 }
2940 }
2941
2942 /*
2943 * Finally populate the vmsr register of each vCPU with the total
2944 * package value to emulate the real hardware where each CPU return the
2945 * value of the package it belongs.
2946 */
2947 for (int i = 0; i < num_threads; i++) {
2948 if ((thd_stat[i].is_vcpu == true) && \
2949 (thd_stat[i].delta_ticks > 0)) {
2950 vmsr->msr_value[thd_stat[i].vcpu_id] = \
2951 vpkgs_energy_stat[thd_stat[i].vpkg_id];
2952 }
2953 }
2954
2955 /* Freeing memory before zeroing the pointer */
2956 for (int i = 0; i < num_threads; i++) {
2957 g_free(thd_stat[i].utime);
2958 g_free(thd_stat[i].stime);
2959 }
2960 }
2961
2962 clean:
2963 rcu_unregister_thread();
2964 return NULL;
2965 }
2966
kvm_msr_energy_thread_init(KVMState * s,MachineState * ms)2967 static int kvm_msr_energy_thread_init(KVMState *s, MachineState *ms)
2968 {
2969 MachineClass *mc = MACHINE_GET_CLASS(ms);
2970 struct KVMMsrEnergy *r = &s->msr_energy;
2971
2972 /*
2973 * Sanity check
2974 * 1. Host cpu must be Intel cpu
2975 * 2. RAPL must be enabled on the Host
2976 */
2977 if (!is_host_cpu_intel()) {
2978 error_report("The RAPL feature can only be enabled on hosts "
2979 "with Intel CPU models");
2980 return -1;
2981 }
2982
2983 if (!is_rapl_enabled()) {
2984 return -1;
2985 }
2986
2987 /* Retrieve the virtual topology */
2988 vmsr_init_topo_info(&r->guest_topo_info, ms);
2989
2990 /* Retrieve the number of vcpu */
2991 r->guest_vcpus = ms->smp.cpus;
2992
2993 /* Retrieve the number of virtual sockets */
2994 r->guest_vsockets = ms->smp.sockets;
2995
2996 /* Allocate register memory (MSR_PKG_STATUS) for each vcpu */
2997 r->msr_value = g_new0(uint64_t, r->guest_vcpus);
2998
2999 /* Retrieve the CPUArchIDlist */
3000 r->guest_cpu_list = mc->possible_cpu_arch_ids(ms);
3001
3002 /* Max number of cpus on the Host */
3003 r->host_topo.maxcpus = vmsr_get_maxcpus();
3004 if (r->host_topo.maxcpus == 0) {
3005 error_report("host max cpus = 0");
3006 return -1;
3007 }
3008
3009 /* Max number of packages on the host */
3010 r->host_topo.maxpkgs = vmsr_get_max_physical_package(r->host_topo.maxcpus);
3011 if (r->host_topo.maxpkgs == 0) {
3012 error_report("host max pkgs = 0");
3013 return -1;
3014 }
3015
3016 /* Allocate memory for each package on the host */
3017 r->host_topo.pkg_cpu_count = g_new0(unsigned int, r->host_topo.maxpkgs);
3018 r->host_topo.maxticks = g_new0(unsigned int, r->host_topo.maxpkgs);
3019
3020 vmsr_count_cpus_per_package(r->host_topo.pkg_cpu_count,
3021 r->host_topo.maxpkgs);
3022 for (int i = 0; i < r->host_topo.maxpkgs; i++) {
3023 if (r->host_topo.pkg_cpu_count[i] == 0) {
3024 error_report("cpu per packages = 0 on package_%d", i);
3025 return -1;
3026 }
3027 }
3028
3029 /* Get QEMU PID*/
3030 r->pid = getpid();
3031
3032 /* Compute the socket path if necessary */
3033 if (s->msr_energy.socket_path == NULL) {
3034 s->msr_energy.socket_path = vmsr_compute_default_paths();
3035 }
3036
3037 /* Open socket with vmsr helper */
3038 s->msr_energy.sioc = vmsr_open_socket(s->msr_energy.socket_path);
3039
3040 if (s->msr_energy.sioc == NULL) {
3041 error_report("vmsr socket opening failed");
3042 return -1;
3043 }
3044
3045 /* Those MSR values should not change */
3046 r->msr_unit = vmsr_read_msr(MSR_RAPL_POWER_UNIT, 0, r->pid,
3047 s->msr_energy.sioc);
3048 r->msr_limit = vmsr_read_msr(MSR_PKG_POWER_LIMIT, 0, r->pid,
3049 s->msr_energy.sioc);
3050 r->msr_info = vmsr_read_msr(MSR_PKG_POWER_INFO, 0, r->pid,
3051 s->msr_energy.sioc);
3052 if (r->msr_unit == 0 || r->msr_limit == 0 || r->msr_info == 0) {
3053 error_report("can't read any virtual msr");
3054 return -1;
3055 }
3056
3057 qemu_thread_create(&r->msr_thr, "kvm-msr",
3058 kvm_msr_energy_thread,
3059 s, QEMU_THREAD_JOINABLE);
3060 return 0;
3061 }
3062
kvm_arch_get_default_type(MachineState * ms)3063 int kvm_arch_get_default_type(MachineState *ms)
3064 {
3065 return 0;
3066 }
3067
kvm_vm_enable_exception_payload(KVMState * s)3068 static int kvm_vm_enable_exception_payload(KVMState *s)
3069 {
3070 int ret = 0;
3071 has_exception_payload = kvm_check_extension(s, KVM_CAP_EXCEPTION_PAYLOAD);
3072 if (has_exception_payload) {
3073 ret = kvm_vm_enable_cap(s, KVM_CAP_EXCEPTION_PAYLOAD, 0, true);
3074 if (ret < 0) {
3075 error_report("kvm: Failed to enable exception payload cap: %s",
3076 strerror(-ret));
3077 }
3078 }
3079
3080 return ret;
3081 }
3082
kvm_vm_enable_triple_fault_event(KVMState * s)3083 static int kvm_vm_enable_triple_fault_event(KVMState *s)
3084 {
3085 int ret = 0;
3086 has_triple_fault_event = \
3087 kvm_check_extension(s,
3088 KVM_CAP_X86_TRIPLE_FAULT_EVENT);
3089 if (has_triple_fault_event) {
3090 ret = kvm_vm_enable_cap(s, KVM_CAP_X86_TRIPLE_FAULT_EVENT, 0, true);
3091 if (ret < 0) {
3092 error_report("kvm: Failed to enable triple fault event cap: %s",
3093 strerror(-ret));
3094 }
3095 }
3096 return ret;
3097 }
3098
kvm_vm_set_identity_map_addr(KVMState * s,uint64_t identity_base)3099 static int kvm_vm_set_identity_map_addr(KVMState *s, uint64_t identity_base)
3100 {
3101 return kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
3102 }
3103
kvm_vm_set_nr_mmu_pages(KVMState * s)3104 static int kvm_vm_set_nr_mmu_pages(KVMState *s)
3105 {
3106 uint64_t shadow_mem;
3107 int ret = 0;
3108 shadow_mem = object_property_get_int(OBJECT(s),
3109 "kvm-shadow-mem",
3110 &error_abort);
3111 if (shadow_mem != -1) {
3112 shadow_mem /= 4096;
3113 ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
3114 }
3115 return ret;
3116 }
3117
kvm_vm_set_tss_addr(KVMState * s,uint64_t tss_base)3118 static int kvm_vm_set_tss_addr(KVMState *s, uint64_t tss_base)
3119 {
3120 return kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, tss_base);
3121 }
3122
kvm_vm_enable_disable_exits(KVMState * s)3123 static int kvm_vm_enable_disable_exits(KVMState *s)
3124 {
3125 int disable_exits = kvm_check_extension(s, KVM_CAP_X86_DISABLE_EXITS);
3126
3127 if (disable_exits) {
3128 disable_exits &= (KVM_X86_DISABLE_EXITS_MWAIT |
3129 KVM_X86_DISABLE_EXITS_HLT |
3130 KVM_X86_DISABLE_EXITS_PAUSE |
3131 KVM_X86_DISABLE_EXITS_CSTATE);
3132 }
3133
3134 return kvm_vm_enable_cap(s, KVM_CAP_X86_DISABLE_EXITS, 0,
3135 disable_exits);
3136 }
3137
kvm_vm_enable_bus_lock_exit(KVMState * s)3138 static int kvm_vm_enable_bus_lock_exit(KVMState *s)
3139 {
3140 int ret = 0;
3141 ret = kvm_check_extension(s, KVM_CAP_X86_BUS_LOCK_EXIT);
3142 if (!(ret & KVM_BUS_LOCK_DETECTION_EXIT)) {
3143 error_report("kvm: bus lock detection unsupported");
3144 return -ENOTSUP;
3145 }
3146 ret = kvm_vm_enable_cap(s, KVM_CAP_X86_BUS_LOCK_EXIT, 0,
3147 KVM_BUS_LOCK_DETECTION_EXIT);
3148 if (ret < 0) {
3149 error_report("kvm: Failed to enable bus lock detection cap: %s",
3150 strerror(-ret));
3151 }
3152
3153 return ret;
3154 }
3155
kvm_vm_enable_notify_vmexit(KVMState * s)3156 static int kvm_vm_enable_notify_vmexit(KVMState *s)
3157 {
3158 int ret = 0;
3159 if (s->notify_vmexit != NOTIFY_VMEXIT_OPTION_DISABLE) {
3160 uint64_t notify_window_flags =
3161 ((uint64_t)s->notify_window << 32) |
3162 KVM_X86_NOTIFY_VMEXIT_ENABLED |
3163 KVM_X86_NOTIFY_VMEXIT_USER;
3164 ret = kvm_vm_enable_cap(s, KVM_CAP_X86_NOTIFY_VMEXIT, 0,
3165 notify_window_flags);
3166 if (ret < 0) {
3167 error_report("kvm: Failed to enable notify vmexit cap: %s",
3168 strerror(-ret));
3169 }
3170 }
3171 return ret;
3172 }
3173
kvm_vm_enable_userspace_msr(KVMState * s)3174 static int kvm_vm_enable_userspace_msr(KVMState *s)
3175 {
3176 int ret;
3177
3178 ret = kvm_vm_enable_cap(s, KVM_CAP_X86_USER_SPACE_MSR, 0,
3179 KVM_MSR_EXIT_REASON_FILTER);
3180 if (ret < 0) {
3181 error_report("Could not enable user space MSRs: %s",
3182 strerror(-ret));
3183 exit(1);
3184 }
3185
3186 ret = kvm_filter_msr(s, MSR_CORE_THREAD_COUNT,
3187 kvm_rdmsr_core_thread_count, NULL);
3188 if (ret < 0) {
3189 error_report("Could not install MSR_CORE_THREAD_COUNT handler: %s",
3190 strerror(-ret));
3191 exit(1);
3192 }
3193
3194 return 0;
3195 }
3196
kvm_vm_enable_energy_msrs(KVMState * s)3197 static int kvm_vm_enable_energy_msrs(KVMState *s)
3198 {
3199 int ret;
3200
3201 if (s->msr_energy.enable == true) {
3202 ret = kvm_filter_msr(s, MSR_RAPL_POWER_UNIT,
3203 kvm_rdmsr_rapl_power_unit, NULL);
3204 if (ret < 0) {
3205 error_report("Could not install MSR_RAPL_POWER_UNIT handler: %s",
3206 strerror(-ret));
3207 return ret;
3208 }
3209
3210 ret = kvm_filter_msr(s, MSR_PKG_POWER_LIMIT,
3211 kvm_rdmsr_pkg_power_limit, NULL);
3212 if (ret < 0) {
3213 error_report("Could not install MSR_PKG_POWER_LIMIT handler: %s",
3214 strerror(-ret));
3215 return ret;
3216 }
3217
3218 ret = kvm_filter_msr(s, MSR_PKG_POWER_INFO,
3219 kvm_rdmsr_pkg_power_info, NULL);
3220 if (ret < 0) {
3221 error_report("Could not install MSR_PKG_POWER_INFO handler: %s",
3222 strerror(-ret));
3223 return ret;
3224 }
3225 ret = kvm_filter_msr(s, MSR_PKG_ENERGY_STATUS,
3226 kvm_rdmsr_pkg_energy_status, NULL);
3227 if (ret < 0) {
3228 error_report("Could not install MSR_PKG_ENERGY_STATUS handler: %s",
3229 strerror(-ret));
3230 return ret;
3231 }
3232 }
3233 return 0;
3234 }
3235
kvm_arch_init(MachineState * ms,KVMState * s)3236 int kvm_arch_init(MachineState *ms, KVMState *s)
3237 {
3238 int ret;
3239 struct utsname utsname;
3240 Error *local_err = NULL;
3241
3242 /*
3243 * Initialize confidential guest (SEV/TDX) context, if required
3244 */
3245 if (ms->cgs) {
3246 ret = confidential_guest_kvm_init(ms->cgs, &local_err);
3247 if (ret < 0) {
3248 error_report_err(local_err);
3249 return ret;
3250 }
3251 }
3252
3253 has_xcrs = kvm_check_extension(s, KVM_CAP_XCRS);
3254 has_sregs2 = kvm_check_extension(s, KVM_CAP_SREGS2) > 0;
3255
3256 hv_vpindex_settable = kvm_check_extension(s, KVM_CAP_HYPERV_VP_INDEX);
3257
3258 ret = kvm_vm_enable_exception_payload(s);
3259 if (ret < 0) {
3260 return ret;
3261 }
3262
3263 ret = kvm_vm_enable_triple_fault_event(s);
3264 if (ret < 0) {
3265 return ret;
3266 }
3267
3268 if (s->xen_version) {
3269 #ifdef CONFIG_XEN_EMU
3270 if (!object_dynamic_cast(OBJECT(ms), TYPE_PC_MACHINE)) {
3271 error_report("kvm: Xen support only available in PC machine");
3272 return -ENOTSUP;
3273 }
3274 /* hyperv_enabled() doesn't work yet. */
3275 uint32_t msr = XEN_HYPERCALL_MSR;
3276 ret = kvm_xen_init(s, msr);
3277 if (ret < 0) {
3278 return ret;
3279 }
3280 #else
3281 error_report("kvm: Xen support not enabled in qemu");
3282 return -ENOTSUP;
3283 #endif
3284 }
3285
3286 ret = kvm_get_supported_msrs(s);
3287 if (ret < 0) {
3288 return ret;
3289 }
3290
3291 ret = kvm_get_supported_feature_msrs(s);
3292 if (ret < 0) {
3293 return ret;
3294 }
3295
3296 uname(&utsname);
3297 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
3298
3299 ret = kvm_vm_set_identity_map_addr(s, KVM_IDENTITY_BASE);
3300 if (ret < 0) {
3301 return ret;
3302 }
3303
3304 /* Set TSS base one page after EPT identity map. */
3305 ret = kvm_vm_set_tss_addr(s, KVM_IDENTITY_BASE + 0x1000);
3306 if (ret < 0) {
3307 return ret;
3308 }
3309
3310 /* Tell fw_cfg to notify the BIOS to reserve the range. */
3311 e820_add_entry(KVM_IDENTITY_BASE, 0x4000, E820_RESERVED);
3312
3313 ret = kvm_vm_set_nr_mmu_pages(s);
3314 if (ret < 0) {
3315 return ret;
3316 }
3317
3318 if (kvm_check_extension(s, KVM_CAP_X86_SMM) &&
3319 object_dynamic_cast(OBJECT(ms), TYPE_X86_MACHINE) &&
3320 x86_machine_is_smm_enabled(X86_MACHINE(ms))) {
3321 smram_machine_done.notify = register_smram_listener;
3322 qemu_add_machine_init_done_notifier(&smram_machine_done);
3323 }
3324
3325 if (enable_cpu_pm) {
3326 ret = kvm_vm_enable_disable_exits(s);
3327 if (ret < 0) {
3328 error_report("kvm: guest stopping CPU not supported: %s",
3329 strerror(-ret));
3330 return ret;
3331 }
3332 }
3333
3334 if (object_dynamic_cast(OBJECT(ms), TYPE_X86_MACHINE)) {
3335 X86MachineState *x86ms = X86_MACHINE(ms);
3336
3337 if (x86ms->bus_lock_ratelimit > 0) {
3338 ret = kvm_vm_enable_bus_lock_exit(s);
3339 if (ret < 0) {
3340 return ret;
3341 }
3342 ratelimit_init(&bus_lock_ratelimit_ctrl);
3343 ratelimit_set_speed(&bus_lock_ratelimit_ctrl,
3344 x86ms->bus_lock_ratelimit, BUS_LOCK_SLICE_TIME);
3345 }
3346 }
3347
3348 if (kvm_check_extension(s, KVM_CAP_X86_NOTIFY_VMEXIT)) {
3349 ret = kvm_vm_enable_notify_vmexit(s);
3350 if (ret < 0) {
3351 return ret;
3352 }
3353 }
3354
3355 if (kvm_vm_check_extension(s, KVM_CAP_X86_USER_SPACE_MSR)) {
3356 ret = kvm_vm_enable_userspace_msr(s);
3357 if (ret < 0) {
3358 return ret;
3359 }
3360
3361 if (s->msr_energy.enable == true) {
3362 ret = kvm_vm_enable_energy_msrs(s);
3363 if (ret < 0) {
3364 return ret;
3365 }
3366
3367 ret = kvm_msr_energy_thread_init(s, ms);
3368 if (ret < 0) {
3369 error_report("kvm : error RAPL feature requirement not met");
3370 return ret;
3371 }
3372 }
3373 }
3374
3375 return 0;
3376 }
3377
set_v8086_seg(struct kvm_segment * lhs,const SegmentCache * rhs)3378 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
3379 {
3380 lhs->selector = rhs->selector;
3381 lhs->base = rhs->base;
3382 lhs->limit = rhs->limit;
3383 lhs->type = 3;
3384 lhs->present = 1;
3385 lhs->dpl = 3;
3386 lhs->db = 0;
3387 lhs->s = 1;
3388 lhs->l = 0;
3389 lhs->g = 0;
3390 lhs->avl = 0;
3391 lhs->unusable = 0;
3392 }
3393
set_seg(struct kvm_segment * lhs,const SegmentCache * rhs)3394 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
3395 {
3396 unsigned flags = rhs->flags;
3397 lhs->selector = rhs->selector;
3398 lhs->base = rhs->base;
3399 lhs->limit = rhs->limit;
3400 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
3401 lhs->present = (flags & DESC_P_MASK) != 0;
3402 lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
3403 lhs->db = (flags >> DESC_B_SHIFT) & 1;
3404 lhs->s = (flags & DESC_S_MASK) != 0;
3405 lhs->l = (flags >> DESC_L_SHIFT) & 1;
3406 lhs->g = (flags & DESC_G_MASK) != 0;
3407 lhs->avl = (flags & DESC_AVL_MASK) != 0;
3408 lhs->unusable = !lhs->present;
3409 lhs->padding = 0;
3410 }
3411
get_seg(SegmentCache * lhs,const struct kvm_segment * rhs)3412 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
3413 {
3414 lhs->selector = rhs->selector;
3415 lhs->base = rhs->base;
3416 lhs->limit = rhs->limit;
3417 lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
3418 ((rhs->present && !rhs->unusable) * DESC_P_MASK) |
3419 (rhs->dpl << DESC_DPL_SHIFT) |
3420 (rhs->db << DESC_B_SHIFT) |
3421 (rhs->s * DESC_S_MASK) |
3422 (rhs->l << DESC_L_SHIFT) |
3423 (rhs->g * DESC_G_MASK) |
3424 (rhs->avl * DESC_AVL_MASK);
3425 }
3426
kvm_getput_reg(__u64 * kvm_reg,target_ulong * qemu_reg,int set)3427 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
3428 {
3429 if (set) {
3430 *kvm_reg = *qemu_reg;
3431 } else {
3432 *qemu_reg = *kvm_reg;
3433 }
3434 }
3435
kvm_getput_regs(X86CPU * cpu,int set)3436 static int kvm_getput_regs(X86CPU *cpu, int set)
3437 {
3438 CPUX86State *env = &cpu->env;
3439 struct kvm_regs regs;
3440 int ret = 0;
3441
3442 if (!set) {
3443 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, ®s);
3444 if (ret < 0) {
3445 return ret;
3446 }
3447 }
3448
3449 kvm_getput_reg(®s.rax, &env->regs[R_EAX], set);
3450 kvm_getput_reg(®s.rbx, &env->regs[R_EBX], set);
3451 kvm_getput_reg(®s.rcx, &env->regs[R_ECX], set);
3452 kvm_getput_reg(®s.rdx, &env->regs[R_EDX], set);
3453 kvm_getput_reg(®s.rsi, &env->regs[R_ESI], set);
3454 kvm_getput_reg(®s.rdi, &env->regs[R_EDI], set);
3455 kvm_getput_reg(®s.rsp, &env->regs[R_ESP], set);
3456 kvm_getput_reg(®s.rbp, &env->regs[R_EBP], set);
3457 #ifdef TARGET_X86_64
3458 kvm_getput_reg(®s.r8, &env->regs[8], set);
3459 kvm_getput_reg(®s.r9, &env->regs[9], set);
3460 kvm_getput_reg(®s.r10, &env->regs[10], set);
3461 kvm_getput_reg(®s.r11, &env->regs[11], set);
3462 kvm_getput_reg(®s.r12, &env->regs[12], set);
3463 kvm_getput_reg(®s.r13, &env->regs[13], set);
3464 kvm_getput_reg(®s.r14, &env->regs[14], set);
3465 kvm_getput_reg(®s.r15, &env->regs[15], set);
3466 #endif
3467
3468 kvm_getput_reg(®s.rflags, &env->eflags, set);
3469 kvm_getput_reg(®s.rip, &env->eip, set);
3470
3471 if (set) {
3472 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, ®s);
3473 }
3474
3475 return ret;
3476 }
3477
kvm_put_xsave(X86CPU * cpu)3478 static int kvm_put_xsave(X86CPU *cpu)
3479 {
3480 CPUX86State *env = &cpu->env;
3481 void *xsave = env->xsave_buf;
3482
3483 x86_cpu_xsave_all_areas(cpu, xsave, env->xsave_buf_len);
3484
3485 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);
3486 }
3487
kvm_put_xcrs(X86CPU * cpu)3488 static int kvm_put_xcrs(X86CPU *cpu)
3489 {
3490 CPUX86State *env = &cpu->env;
3491 struct kvm_xcrs xcrs = {};
3492
3493 if (!has_xcrs) {
3494 return 0;
3495 }
3496
3497 xcrs.nr_xcrs = 1;
3498 xcrs.flags = 0;
3499 xcrs.xcrs[0].xcr = 0;
3500 xcrs.xcrs[0].value = env->xcr0;
3501 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs);
3502 }
3503
kvm_put_sregs(X86CPU * cpu)3504 static int kvm_put_sregs(X86CPU *cpu)
3505 {
3506 CPUX86State *env = &cpu->env;
3507 struct kvm_sregs sregs;
3508
3509 /*
3510 * The interrupt_bitmap is ignored because KVM_SET_SREGS is
3511 * always followed by KVM_SET_VCPU_EVENTS.
3512 */
3513 memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
3514
3515 if ((env->eflags & VM_MASK)) {
3516 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
3517 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
3518 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
3519 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
3520 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
3521 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
3522 } else {
3523 set_seg(&sregs.cs, &env->segs[R_CS]);
3524 set_seg(&sregs.ds, &env->segs[R_DS]);
3525 set_seg(&sregs.es, &env->segs[R_ES]);
3526 set_seg(&sregs.fs, &env->segs[R_FS]);
3527 set_seg(&sregs.gs, &env->segs[R_GS]);
3528 set_seg(&sregs.ss, &env->segs[R_SS]);
3529 }
3530
3531 set_seg(&sregs.tr, &env->tr);
3532 set_seg(&sregs.ldt, &env->ldt);
3533
3534 sregs.idt.limit = env->idt.limit;
3535 sregs.idt.base = env->idt.base;
3536 memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
3537 sregs.gdt.limit = env->gdt.limit;
3538 sregs.gdt.base = env->gdt.base;
3539 memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
3540
3541 sregs.cr0 = env->cr[0];
3542 sregs.cr2 = env->cr[2];
3543 sregs.cr3 = env->cr[3];
3544 sregs.cr4 = env->cr[4];
3545
3546 sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state);
3547 sregs.apic_base = cpu_get_apic_base(cpu->apic_state);
3548
3549 sregs.efer = env->efer;
3550
3551 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
3552 }
3553
kvm_put_sregs2(X86CPU * cpu)3554 static int kvm_put_sregs2(X86CPU *cpu)
3555 {
3556 CPUX86State *env = &cpu->env;
3557 struct kvm_sregs2 sregs;
3558 int i;
3559
3560 sregs.flags = 0;
3561
3562 if ((env->eflags & VM_MASK)) {
3563 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
3564 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
3565 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
3566 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
3567 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
3568 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
3569 } else {
3570 set_seg(&sregs.cs, &env->segs[R_CS]);
3571 set_seg(&sregs.ds, &env->segs[R_DS]);
3572 set_seg(&sregs.es, &env->segs[R_ES]);
3573 set_seg(&sregs.fs, &env->segs[R_FS]);
3574 set_seg(&sregs.gs, &env->segs[R_GS]);
3575 set_seg(&sregs.ss, &env->segs[R_SS]);
3576 }
3577
3578 set_seg(&sregs.tr, &env->tr);
3579 set_seg(&sregs.ldt, &env->ldt);
3580
3581 sregs.idt.limit = env->idt.limit;
3582 sregs.idt.base = env->idt.base;
3583 memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
3584 sregs.gdt.limit = env->gdt.limit;
3585 sregs.gdt.base = env->gdt.base;
3586 memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
3587
3588 sregs.cr0 = env->cr[0];
3589 sregs.cr2 = env->cr[2];
3590 sregs.cr3 = env->cr[3];
3591 sregs.cr4 = env->cr[4];
3592
3593 sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state);
3594 sregs.apic_base = cpu_get_apic_base(cpu->apic_state);
3595
3596 sregs.efer = env->efer;
3597
3598 if (env->pdptrs_valid) {
3599 for (i = 0; i < 4; i++) {
3600 sregs.pdptrs[i] = env->pdptrs[i];
3601 }
3602 sregs.flags |= KVM_SREGS2_FLAGS_PDPTRS_VALID;
3603 }
3604
3605 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS2, &sregs);
3606 }
3607
3608
kvm_msr_buf_reset(X86CPU * cpu)3609 static void kvm_msr_buf_reset(X86CPU *cpu)
3610 {
3611 memset(cpu->kvm_msr_buf, 0, MSR_BUF_SIZE);
3612 }
3613
kvm_msr_entry_add(X86CPU * cpu,uint32_t index,uint64_t value)3614 static void kvm_msr_entry_add(X86CPU *cpu, uint32_t index, uint64_t value)
3615 {
3616 struct kvm_msrs *msrs = cpu->kvm_msr_buf;
3617 void *limit = ((void *)msrs) + MSR_BUF_SIZE;
3618 struct kvm_msr_entry *entry = &msrs->entries[msrs->nmsrs];
3619
3620 assert((void *)(entry + 1) <= limit);
3621
3622 entry->index = index;
3623 entry->reserved = 0;
3624 entry->data = value;
3625 msrs->nmsrs++;
3626 }
3627
kvm_put_one_msr(X86CPU * cpu,int index,uint64_t value)3628 static int kvm_put_one_msr(X86CPU *cpu, int index, uint64_t value)
3629 {
3630 kvm_msr_buf_reset(cpu);
3631 kvm_msr_entry_add(cpu, index, value);
3632
3633 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
3634 }
3635
kvm_get_one_msr(X86CPU * cpu,int index,uint64_t * value)3636 static int kvm_get_one_msr(X86CPU *cpu, int index, uint64_t *value)
3637 {
3638 int ret;
3639 struct {
3640 struct kvm_msrs info;
3641 struct kvm_msr_entry entries[1];
3642 } msr_data = {
3643 .info.nmsrs = 1,
3644 .entries[0].index = index,
3645 };
3646
3647 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
3648 if (ret < 0) {
3649 return ret;
3650 }
3651 assert(ret == 1);
3652 *value = msr_data.entries[0].data;
3653 return ret;
3654 }
kvm_put_apicbase(X86CPU * cpu,uint64_t value)3655 void kvm_put_apicbase(X86CPU *cpu, uint64_t value)
3656 {
3657 int ret;
3658
3659 ret = kvm_put_one_msr(cpu, MSR_IA32_APICBASE, value);
3660 assert(ret == 1);
3661 }
3662
kvm_put_tscdeadline_msr(X86CPU * cpu)3663 static int kvm_put_tscdeadline_msr(X86CPU *cpu)
3664 {
3665 CPUX86State *env = &cpu->env;
3666 int ret;
3667
3668 if (!has_msr_tsc_deadline) {
3669 return 0;
3670 }
3671
3672 ret = kvm_put_one_msr(cpu, MSR_IA32_TSCDEADLINE, env->tsc_deadline);
3673 if (ret < 0) {
3674 return ret;
3675 }
3676
3677 assert(ret == 1);
3678 return 0;
3679 }
3680
3681 /*
3682 * Provide a separate write service for the feature control MSR in order to
3683 * kick the VCPU out of VMXON or even guest mode on reset. This has to be done
3684 * before writing any other state because forcibly leaving nested mode
3685 * invalidates the VCPU state.
3686 */
kvm_put_msr_feature_control(X86CPU * cpu)3687 static int kvm_put_msr_feature_control(X86CPU *cpu)
3688 {
3689 int ret;
3690
3691 if (!has_msr_feature_control) {
3692 return 0;
3693 }
3694
3695 ret = kvm_put_one_msr(cpu, MSR_IA32_FEATURE_CONTROL,
3696 cpu->env.msr_ia32_feature_control);
3697 if (ret < 0) {
3698 return ret;
3699 }
3700
3701 assert(ret == 1);
3702 return 0;
3703 }
3704
make_vmx_msr_value(uint32_t index,uint32_t features)3705 static uint64_t make_vmx_msr_value(uint32_t index, uint32_t features)
3706 {
3707 uint32_t default1, can_be_one, can_be_zero;
3708 uint32_t must_be_one;
3709
3710 switch (index) {
3711 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3712 default1 = 0x00000016;
3713 break;
3714 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3715 default1 = 0x0401e172;
3716 break;
3717 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3718 default1 = 0x000011ff;
3719 break;
3720 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3721 default1 = 0x00036dff;
3722 break;
3723 case MSR_IA32_VMX_PROCBASED_CTLS2:
3724 default1 = 0;
3725 break;
3726 default:
3727 abort();
3728 }
3729
3730 /* If a feature bit is set, the control can be either set or clear.
3731 * Otherwise the value is limited to either 0 or 1 by default1.
3732 */
3733 can_be_one = features | default1;
3734 can_be_zero = features | ~default1;
3735 must_be_one = ~can_be_zero;
3736
3737 /*
3738 * Bit 0:31 -> 0 if the control bit can be zero (i.e. 1 if it must be one).
3739 * Bit 32:63 -> 1 if the control bit can be one.
3740 */
3741 return must_be_one | (((uint64_t)can_be_one) << 32);
3742 }
3743
kvm_msr_entry_add_vmx(X86CPU * cpu,FeatureWordArray f)3744 static void kvm_msr_entry_add_vmx(X86CPU *cpu, FeatureWordArray f)
3745 {
3746 uint64_t kvm_vmx_basic =
3747 kvm_arch_get_supported_msr_feature(kvm_state,
3748 MSR_IA32_VMX_BASIC);
3749
3750 if (!kvm_vmx_basic) {
3751 /* If the kernel doesn't support VMX feature (kvm_intel.nested=0),
3752 * then kvm_vmx_basic will be 0 and KVM_SET_MSR will fail.
3753 */
3754 return;
3755 }
3756
3757 uint64_t kvm_vmx_misc =
3758 kvm_arch_get_supported_msr_feature(kvm_state,
3759 MSR_IA32_VMX_MISC);
3760 uint64_t kvm_vmx_ept_vpid =
3761 kvm_arch_get_supported_msr_feature(kvm_state,
3762 MSR_IA32_VMX_EPT_VPID_CAP);
3763
3764 /*
3765 * If the guest is 64-bit, a value of 1 is allowed for the host address
3766 * space size vmexit control.
3767 */
3768 uint64_t fixed_vmx_exit = f[FEAT_8000_0001_EDX] & CPUID_EXT2_LM
3769 ? (uint64_t)VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE << 32 : 0;
3770
3771 /*
3772 * Bits 0-30, 32-44 and 50-53 come from the host. KVM should
3773 * not change them for backwards compatibility.
3774 */
3775 uint64_t fixed_vmx_basic = kvm_vmx_basic &
3776 (MSR_VMX_BASIC_VMCS_REVISION_MASK |
3777 MSR_VMX_BASIC_VMXON_REGION_SIZE_MASK |
3778 MSR_VMX_BASIC_VMCS_MEM_TYPE_MASK);
3779
3780 /*
3781 * Same for bits 0-4 and 25-27. Bits 16-24 (CR3 target count) can
3782 * change in the future but are always zero for now, clear them to be
3783 * future proof. Bits 32-63 in theory could change, though KVM does
3784 * not support dual-monitor treatment and probably never will; mask
3785 * them out as well.
3786 */
3787 uint64_t fixed_vmx_misc = kvm_vmx_misc &
3788 (MSR_VMX_MISC_PREEMPTION_TIMER_SHIFT_MASK |
3789 MSR_VMX_MISC_MAX_MSR_LIST_SIZE_MASK);
3790
3791 /*
3792 * EPT memory types should not change either, so we do not bother
3793 * adding features for them.
3794 */
3795 uint64_t fixed_vmx_ept_mask =
3796 (f[FEAT_VMX_SECONDARY_CTLS] & VMX_SECONDARY_EXEC_ENABLE_EPT ?
3797 MSR_VMX_EPT_UC | MSR_VMX_EPT_WB : 0);
3798 uint64_t fixed_vmx_ept_vpid = kvm_vmx_ept_vpid & fixed_vmx_ept_mask;
3799
3800 kvm_msr_entry_add(cpu, MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
3801 make_vmx_msr_value(MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
3802 f[FEAT_VMX_PROCBASED_CTLS]));
3803 kvm_msr_entry_add(cpu, MSR_IA32_VMX_TRUE_PINBASED_CTLS,
3804 make_vmx_msr_value(MSR_IA32_VMX_TRUE_PINBASED_CTLS,
3805 f[FEAT_VMX_PINBASED_CTLS]));
3806 kvm_msr_entry_add(cpu, MSR_IA32_VMX_TRUE_EXIT_CTLS,
3807 make_vmx_msr_value(MSR_IA32_VMX_TRUE_EXIT_CTLS,
3808 f[FEAT_VMX_EXIT_CTLS]) | fixed_vmx_exit);
3809 kvm_msr_entry_add(cpu, MSR_IA32_VMX_TRUE_ENTRY_CTLS,
3810 make_vmx_msr_value(MSR_IA32_VMX_TRUE_ENTRY_CTLS,
3811 f[FEAT_VMX_ENTRY_CTLS]));
3812 kvm_msr_entry_add(cpu, MSR_IA32_VMX_PROCBASED_CTLS2,
3813 make_vmx_msr_value(MSR_IA32_VMX_PROCBASED_CTLS2,
3814 f[FEAT_VMX_SECONDARY_CTLS]));
3815 kvm_msr_entry_add(cpu, MSR_IA32_VMX_EPT_VPID_CAP,
3816 f[FEAT_VMX_EPT_VPID_CAPS] | fixed_vmx_ept_vpid);
3817 kvm_msr_entry_add(cpu, MSR_IA32_VMX_BASIC,
3818 f[FEAT_VMX_BASIC] | fixed_vmx_basic);
3819 kvm_msr_entry_add(cpu, MSR_IA32_VMX_MISC,
3820 f[FEAT_VMX_MISC] | fixed_vmx_misc);
3821 if (has_msr_vmx_vmfunc) {
3822 kvm_msr_entry_add(cpu, MSR_IA32_VMX_VMFUNC, f[FEAT_VMX_VMFUNC]);
3823 }
3824
3825 /*
3826 * Just to be safe, write these with constant values. The CRn_FIXED1
3827 * MSRs are generated by KVM based on the vCPU's CPUID.
3828 */
3829 kvm_msr_entry_add(cpu, MSR_IA32_VMX_CR0_FIXED0,
3830 CR0_PE_MASK | CR0_PG_MASK | CR0_NE_MASK);
3831 kvm_msr_entry_add(cpu, MSR_IA32_VMX_CR4_FIXED0,
3832 CR4_VMXE_MASK);
3833
3834 if (f[FEAT_7_1_EAX] & CPUID_7_1_EAX_FRED) {
3835 /* FRED injected-event data (0x2052). */
3836 kvm_msr_entry_add(cpu, MSR_IA32_VMX_VMCS_ENUM, 0x52);
3837 } else if (f[FEAT_VMX_EXIT_CTLS] &
3838 VMX_VM_EXIT_ACTIVATE_SECONDARY_CONTROLS) {
3839 /* Secondary VM-exit controls (0x2044). */
3840 kvm_msr_entry_add(cpu, MSR_IA32_VMX_VMCS_ENUM, 0x44);
3841 } else if (f[FEAT_VMX_SECONDARY_CTLS] & VMX_SECONDARY_EXEC_TSC_SCALING) {
3842 /* TSC multiplier (0x2032). */
3843 kvm_msr_entry_add(cpu, MSR_IA32_VMX_VMCS_ENUM, 0x32);
3844 } else {
3845 /* Preemption timer (0x482E). */
3846 kvm_msr_entry_add(cpu, MSR_IA32_VMX_VMCS_ENUM, 0x2E);
3847 }
3848 }
3849
kvm_msr_entry_add_perf(X86CPU * cpu,FeatureWordArray f)3850 static void kvm_msr_entry_add_perf(X86CPU *cpu, FeatureWordArray f)
3851 {
3852 uint64_t kvm_perf_cap =
3853 kvm_arch_get_supported_msr_feature(kvm_state,
3854 MSR_IA32_PERF_CAPABILITIES);
3855
3856 if (kvm_perf_cap) {
3857 kvm_msr_entry_add(cpu, MSR_IA32_PERF_CAPABILITIES,
3858 kvm_perf_cap & f[FEAT_PERF_CAPABILITIES]);
3859 }
3860 }
3861
kvm_buf_set_msrs(X86CPU * cpu)3862 static int kvm_buf_set_msrs(X86CPU *cpu)
3863 {
3864 int ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
3865 if (ret < 0) {
3866 return ret;
3867 }
3868
3869 if (ret < cpu->kvm_msr_buf->nmsrs) {
3870 struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
3871 error_report("error: failed to set MSR 0x%" PRIx32 " to 0x%" PRIx64,
3872 (uint32_t)e->index, (uint64_t)e->data);
3873 }
3874
3875 assert(ret == cpu->kvm_msr_buf->nmsrs);
3876 return 0;
3877 }
3878
kvm_init_msrs(X86CPU * cpu)3879 static void kvm_init_msrs(X86CPU *cpu)
3880 {
3881 CPUX86State *env = &cpu->env;
3882
3883 kvm_msr_buf_reset(cpu);
3884
3885 if (!is_tdx_vm()) {
3886 if (has_msr_arch_capabs) {
3887 kvm_msr_entry_add(cpu, MSR_IA32_ARCH_CAPABILITIES,
3888 env->features[FEAT_ARCH_CAPABILITIES]);
3889 }
3890
3891 if (has_msr_core_capabs) {
3892 kvm_msr_entry_add(cpu, MSR_IA32_CORE_CAPABILITY,
3893 env->features[FEAT_CORE_CAPABILITY]);
3894 }
3895
3896 if (has_msr_perf_capabs && cpu->enable_pmu) {
3897 kvm_msr_entry_add_perf(cpu, env->features);
3898 }
3899
3900 /*
3901 * Older kernels do not include VMX MSRs in KVM_GET_MSR_INDEX_LIST, but
3902 * all kernels with MSR features should have them.
3903 */
3904 if (kvm_feature_msrs && cpu_has_vmx(env)) {
3905 kvm_msr_entry_add_vmx(cpu, env->features);
3906 }
3907 }
3908
3909 if (has_msr_ucode_rev) {
3910 kvm_msr_entry_add(cpu, MSR_IA32_UCODE_REV, cpu->ucode_rev);
3911 }
3912 assert(kvm_buf_set_msrs(cpu) == 0);
3913 }
3914
kvm_put_msrs(X86CPU * cpu,int level)3915 static int kvm_put_msrs(X86CPU *cpu, int level)
3916 {
3917 CPUX86State *env = &cpu->env;
3918 int i;
3919
3920 kvm_msr_buf_reset(cpu);
3921
3922 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, env->sysenter_cs);
3923 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
3924 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
3925 kvm_msr_entry_add(cpu, MSR_PAT, env->pat);
3926 if (has_msr_star) {
3927 kvm_msr_entry_add(cpu, MSR_STAR, env->star);
3928 }
3929 if (has_msr_hsave_pa) {
3930 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, env->vm_hsave);
3931 }
3932 if (has_msr_tsc_aux) {
3933 kvm_msr_entry_add(cpu, MSR_TSC_AUX, env->tsc_aux);
3934 }
3935 if (has_msr_tsc_adjust) {
3936 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, env->tsc_adjust);
3937 }
3938 if (has_msr_misc_enable) {
3939 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE,
3940 env->msr_ia32_misc_enable);
3941 }
3942 if (has_msr_smbase) {
3943 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, env->smbase);
3944 }
3945 if (has_msr_smi_count) {
3946 kvm_msr_entry_add(cpu, MSR_SMI_COUNT, env->msr_smi_count);
3947 }
3948 if (has_msr_pkrs) {
3949 kvm_msr_entry_add(cpu, MSR_IA32_PKRS, env->pkrs);
3950 }
3951 if (has_msr_bndcfgs) {
3952 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, env->msr_bndcfgs);
3953 }
3954 if (has_msr_xss) {
3955 kvm_msr_entry_add(cpu, MSR_IA32_XSS, env->xss);
3956 }
3957 if (has_msr_umwait) {
3958 kvm_msr_entry_add(cpu, MSR_IA32_UMWAIT_CONTROL, env->umwait);
3959 }
3960 if (has_msr_spec_ctrl) {
3961 kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, env->spec_ctrl);
3962 }
3963 if (has_tsc_scale_msr) {
3964 kvm_msr_entry_add(cpu, MSR_AMD64_TSC_RATIO, env->amd_tsc_scale_msr);
3965 }
3966
3967 if (has_msr_tsx_ctrl) {
3968 kvm_msr_entry_add(cpu, MSR_IA32_TSX_CTRL, env->tsx_ctrl);
3969 }
3970 if (has_msr_virt_ssbd) {
3971 kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, env->virt_ssbd);
3972 }
3973 if (has_msr_hwcr) {
3974 kvm_msr_entry_add(cpu, MSR_K7_HWCR, env->msr_hwcr);
3975 }
3976
3977 #ifdef TARGET_X86_64
3978 if (lm_capable_kernel) {
3979 kvm_msr_entry_add(cpu, MSR_CSTAR, env->cstar);
3980 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, env->kernelgsbase);
3981 kvm_msr_entry_add(cpu, MSR_FMASK, env->fmask);
3982 kvm_msr_entry_add(cpu, MSR_LSTAR, env->lstar);
3983 if (env->features[FEAT_7_1_EAX] & CPUID_7_1_EAX_FRED) {
3984 kvm_msr_entry_add(cpu, MSR_IA32_FRED_RSP0, env->fred_rsp0);
3985 kvm_msr_entry_add(cpu, MSR_IA32_FRED_RSP1, env->fred_rsp1);
3986 kvm_msr_entry_add(cpu, MSR_IA32_FRED_RSP2, env->fred_rsp2);
3987 kvm_msr_entry_add(cpu, MSR_IA32_FRED_RSP3, env->fred_rsp3);
3988 kvm_msr_entry_add(cpu, MSR_IA32_FRED_STKLVLS, env->fred_stklvls);
3989 kvm_msr_entry_add(cpu, MSR_IA32_FRED_SSP1, env->fred_ssp1);
3990 kvm_msr_entry_add(cpu, MSR_IA32_FRED_SSP2, env->fred_ssp2);
3991 kvm_msr_entry_add(cpu, MSR_IA32_FRED_SSP3, env->fred_ssp3);
3992 kvm_msr_entry_add(cpu, MSR_IA32_FRED_CONFIG, env->fred_config);
3993 }
3994 }
3995 #endif
3996
3997 /*
3998 * The following MSRs have side effects on the guest or are too heavy
3999 * for normal writeback. Limit them to reset or full state updates.
4000 */
4001 if (level >= KVM_PUT_RESET_STATE) {
4002 kvm_msr_entry_add(cpu, MSR_IA32_TSC, env->tsc);
4003 if (env->features[FEAT_KVM] & (CPUID_KVM_CLOCK | CPUID_KVM_CLOCK2)) {
4004 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, env->system_time_msr);
4005 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
4006 }
4007 if (env->features[FEAT_KVM] & CPUID_KVM_ASYNCPF_INT) {
4008 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_INT, env->async_pf_int_msr);
4009 }
4010 if (env->features[FEAT_KVM] & CPUID_KVM_ASYNCPF) {
4011 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, env->async_pf_en_msr);
4012 }
4013 if (env->features[FEAT_KVM] & CPUID_KVM_PV_EOI) {
4014 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, env->pv_eoi_en_msr);
4015 }
4016 if (env->features[FEAT_KVM] & CPUID_KVM_STEAL_TIME) {
4017 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, env->steal_time_msr);
4018 }
4019
4020 if (env->features[FEAT_KVM] & CPUID_KVM_POLL_CONTROL) {
4021 kvm_msr_entry_add(cpu, MSR_KVM_POLL_CONTROL, env->poll_control_msr);
4022 }
4023
4024 if (has_architectural_pmu_version > 0) {
4025 if (has_architectural_pmu_version > 1) {
4026 /* Stop the counter. */
4027 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
4028 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
4029 }
4030
4031 /* Set the counter values. */
4032 for (i = 0; i < num_architectural_pmu_fixed_counters; i++) {
4033 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i,
4034 env->msr_fixed_counters[i]);
4035 }
4036 for (i = 0; i < num_architectural_pmu_gp_counters; i++) {
4037 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i,
4038 env->msr_gp_counters[i]);
4039 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i,
4040 env->msr_gp_evtsel[i]);
4041 }
4042 if (has_architectural_pmu_version > 1) {
4043 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS,
4044 env->msr_global_status);
4045 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
4046 env->msr_global_ovf_ctrl);
4047
4048 /* Now start the PMU. */
4049 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL,
4050 env->msr_fixed_ctr_ctrl);
4051 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL,
4052 env->msr_global_ctrl);
4053 }
4054 }
4055 /*
4056 * Hyper-V partition-wide MSRs: to avoid clearing them on cpu hot-add,
4057 * only sync them to KVM on the first cpu
4058 */
4059 if (current_cpu == first_cpu) {
4060 if (has_msr_hv_hypercall) {
4061 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID,
4062 env->msr_hv_guest_os_id);
4063 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL,
4064 env->msr_hv_hypercall);
4065 }
4066 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_TIME)) {
4067 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC,
4068 env->msr_hv_tsc);
4069 }
4070 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_REENLIGHTENMENT)) {
4071 kvm_msr_entry_add(cpu, HV_X64_MSR_REENLIGHTENMENT_CONTROL,
4072 env->msr_hv_reenlightenment_control);
4073 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_CONTROL,
4074 env->msr_hv_tsc_emulation_control);
4075 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_STATUS,
4076 env->msr_hv_tsc_emulation_status);
4077 }
4078 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNDBG) &&
4079 has_msr_hv_syndbg_options) {
4080 kvm_msr_entry_add(cpu, HV_X64_MSR_SYNDBG_OPTIONS,
4081 hyperv_syndbg_query_options());
4082 }
4083 }
4084 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VAPIC)) {
4085 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE,
4086 env->msr_hv_vapic);
4087 }
4088 if (has_msr_hv_crash) {
4089 int j;
4090
4091 for (j = 0; j < HV_CRASH_PARAMS; j++)
4092 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j,
4093 env->msr_hv_crash_params[j]);
4094
4095 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_CTL, HV_CRASH_CTL_NOTIFY);
4096 }
4097 if (has_msr_hv_runtime) {
4098 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, env->msr_hv_runtime);
4099 }
4100 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX)
4101 && hv_vpindex_settable) {
4102 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_INDEX,
4103 hyperv_vp_index(CPU(cpu)));
4104 }
4105 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
4106 int j;
4107
4108 kvm_msr_entry_add(cpu, HV_X64_MSR_SVERSION, HV_SYNIC_VERSION);
4109
4110 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL,
4111 env->msr_hv_synic_control);
4112 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP,
4113 env->msr_hv_synic_evt_page);
4114 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP,
4115 env->msr_hv_synic_msg_page);
4116
4117 for (j = 0; j < ARRAY_SIZE(env->msr_hv_synic_sint); j++) {
4118 kvm_msr_entry_add(cpu, HV_X64_MSR_SINT0 + j,
4119 env->msr_hv_synic_sint[j]);
4120 }
4121 }
4122 if (has_msr_hv_stimer) {
4123 int j;
4124
4125 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_config); j++) {
4126 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_CONFIG + j * 2,
4127 env->msr_hv_stimer_config[j]);
4128 }
4129
4130 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_count); j++) {
4131 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_COUNT + j * 2,
4132 env->msr_hv_stimer_count[j]);
4133 }
4134 }
4135 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
4136 uint64_t phys_mask = MAKE_64BIT_MASK(0, cpu->phys_bits);
4137
4138 kvm_msr_entry_add(cpu, MSR_MTRRdefType, env->mtrr_deftype);
4139 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, env->mtrr_fixed[0]);
4140 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, env->mtrr_fixed[1]);
4141 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, env->mtrr_fixed[2]);
4142 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, env->mtrr_fixed[3]);
4143 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, env->mtrr_fixed[4]);
4144 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, env->mtrr_fixed[5]);
4145 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, env->mtrr_fixed[6]);
4146 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, env->mtrr_fixed[7]);
4147 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, env->mtrr_fixed[8]);
4148 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, env->mtrr_fixed[9]);
4149 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, env->mtrr_fixed[10]);
4150 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
4151 /* The CPU GPs if we write to a bit above the physical limit of
4152 * the host CPU (and KVM emulates that)
4153 */
4154 uint64_t mask = env->mtrr_var[i].mask;
4155 mask &= phys_mask;
4156
4157 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i),
4158 env->mtrr_var[i].base);
4159 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), mask);
4160 }
4161 }
4162 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) {
4163 int addr_num = kvm_arch_get_supported_cpuid(kvm_state,
4164 0x14, 1, R_EAX) & 0x7;
4165
4166 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL,
4167 env->msr_rtit_ctrl);
4168 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_STATUS,
4169 env->msr_rtit_status);
4170 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_BASE,
4171 env->msr_rtit_output_base);
4172 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_MASK,
4173 env->msr_rtit_output_mask);
4174 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CR3_MATCH,
4175 env->msr_rtit_cr3_match);
4176 for (i = 0; i < addr_num; i++) {
4177 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i,
4178 env->msr_rtit_addrs[i]);
4179 }
4180 }
4181
4182 if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_SGX_LC) {
4183 kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH0,
4184 env->msr_ia32_sgxlepubkeyhash[0]);
4185 kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH1,
4186 env->msr_ia32_sgxlepubkeyhash[1]);
4187 kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH2,
4188 env->msr_ia32_sgxlepubkeyhash[2]);
4189 kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH3,
4190 env->msr_ia32_sgxlepubkeyhash[3]);
4191 }
4192
4193 if (env->features[FEAT_XSAVE] & CPUID_D_1_EAX_XFD) {
4194 kvm_msr_entry_add(cpu, MSR_IA32_XFD,
4195 env->msr_xfd);
4196 kvm_msr_entry_add(cpu, MSR_IA32_XFD_ERR,
4197 env->msr_xfd_err);
4198 }
4199
4200 if (kvm_enabled() && cpu->enable_pmu &&
4201 (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR)) {
4202 uint64_t depth;
4203 int ret;
4204
4205 /*
4206 * Only migrate Arch LBR states when the host Arch LBR depth
4207 * equals that of source guest's, this is to avoid mismatch
4208 * of guest/host config for the msr hence avoid unexpected
4209 * misbehavior.
4210 */
4211 ret = kvm_get_one_msr(cpu, MSR_ARCH_LBR_DEPTH, &depth);
4212
4213 if (ret == 1 && !!depth && depth == env->msr_lbr_depth) {
4214 kvm_msr_entry_add(cpu, MSR_ARCH_LBR_CTL, env->msr_lbr_ctl);
4215 kvm_msr_entry_add(cpu, MSR_ARCH_LBR_DEPTH, env->msr_lbr_depth);
4216
4217 for (i = 0; i < ARCH_LBR_NR_ENTRIES; i++) {
4218 if (!env->lbr_records[i].from) {
4219 continue;
4220 }
4221 kvm_msr_entry_add(cpu, MSR_ARCH_LBR_FROM_0 + i,
4222 env->lbr_records[i].from);
4223 kvm_msr_entry_add(cpu, MSR_ARCH_LBR_TO_0 + i,
4224 env->lbr_records[i].to);
4225 kvm_msr_entry_add(cpu, MSR_ARCH_LBR_INFO_0 + i,
4226 env->lbr_records[i].info);
4227 }
4228 }
4229 }
4230
4231 /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
4232 * kvm_put_msr_feature_control. */
4233 }
4234
4235 if (env->mcg_cap) {
4236 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, env->mcg_status);
4237 kvm_msr_entry_add(cpu, MSR_MCG_CTL, env->mcg_ctl);
4238 if (has_msr_mcg_ext_ctl) {
4239 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, env->mcg_ext_ctl);
4240 }
4241 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
4242 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, env->mce_banks[i]);
4243 }
4244 }
4245
4246 return kvm_buf_set_msrs(cpu);
4247 }
4248
4249
kvm_get_xsave(X86CPU * cpu)4250 static int kvm_get_xsave(X86CPU *cpu)
4251 {
4252 CPUX86State *env = &cpu->env;
4253 void *xsave = env->xsave_buf;
4254 unsigned long type;
4255 int ret;
4256
4257 type = has_xsave2 ? KVM_GET_XSAVE2 : KVM_GET_XSAVE;
4258 ret = kvm_vcpu_ioctl(CPU(cpu), type, xsave);
4259 if (ret < 0) {
4260 return ret;
4261 }
4262 x86_cpu_xrstor_all_areas(cpu, xsave, env->xsave_buf_len);
4263
4264 return 0;
4265 }
4266
kvm_get_xcrs(X86CPU * cpu)4267 static int kvm_get_xcrs(X86CPU *cpu)
4268 {
4269 CPUX86State *env = &cpu->env;
4270 int i, ret;
4271 struct kvm_xcrs xcrs;
4272
4273 if (!has_xcrs) {
4274 return 0;
4275 }
4276
4277 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs);
4278 if (ret < 0) {
4279 return ret;
4280 }
4281
4282 for (i = 0; i < xcrs.nr_xcrs; i++) {
4283 /* Only support xcr0 now */
4284 if (xcrs.xcrs[i].xcr == 0) {
4285 env->xcr0 = xcrs.xcrs[i].value;
4286 break;
4287 }
4288 }
4289 return 0;
4290 }
4291
kvm_get_sregs(X86CPU * cpu)4292 static int kvm_get_sregs(X86CPU *cpu)
4293 {
4294 CPUX86State *env = &cpu->env;
4295 struct kvm_sregs sregs;
4296 int ret;
4297
4298 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
4299 if (ret < 0) {
4300 return ret;
4301 }
4302
4303 /*
4304 * The interrupt_bitmap is ignored because KVM_GET_SREGS is
4305 * always preceded by KVM_GET_VCPU_EVENTS.
4306 */
4307
4308 get_seg(&env->segs[R_CS], &sregs.cs);
4309 get_seg(&env->segs[R_DS], &sregs.ds);
4310 get_seg(&env->segs[R_ES], &sregs.es);
4311 get_seg(&env->segs[R_FS], &sregs.fs);
4312 get_seg(&env->segs[R_GS], &sregs.gs);
4313 get_seg(&env->segs[R_SS], &sregs.ss);
4314
4315 get_seg(&env->tr, &sregs.tr);
4316 get_seg(&env->ldt, &sregs.ldt);
4317
4318 env->idt.limit = sregs.idt.limit;
4319 env->idt.base = sregs.idt.base;
4320 env->gdt.limit = sregs.gdt.limit;
4321 env->gdt.base = sregs.gdt.base;
4322
4323 env->cr[0] = sregs.cr0;
4324 env->cr[2] = sregs.cr2;
4325 env->cr[3] = sregs.cr3;
4326 env->cr[4] = sregs.cr4;
4327
4328 env->efer = sregs.efer;
4329 if (sev_es_enabled() && env->efer & MSR_EFER_LME &&
4330 env->cr[0] & CR0_PG_MASK) {
4331 env->efer |= MSR_EFER_LMA;
4332 }
4333
4334 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
4335 x86_update_hflags(env);
4336
4337 return 0;
4338 }
4339
kvm_get_sregs2(X86CPU * cpu)4340 static int kvm_get_sregs2(X86CPU *cpu)
4341 {
4342 CPUX86State *env = &cpu->env;
4343 struct kvm_sregs2 sregs;
4344 int i, ret;
4345
4346 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS2, &sregs);
4347 if (ret < 0) {
4348 return ret;
4349 }
4350
4351 get_seg(&env->segs[R_CS], &sregs.cs);
4352 get_seg(&env->segs[R_DS], &sregs.ds);
4353 get_seg(&env->segs[R_ES], &sregs.es);
4354 get_seg(&env->segs[R_FS], &sregs.fs);
4355 get_seg(&env->segs[R_GS], &sregs.gs);
4356 get_seg(&env->segs[R_SS], &sregs.ss);
4357
4358 get_seg(&env->tr, &sregs.tr);
4359 get_seg(&env->ldt, &sregs.ldt);
4360
4361 env->idt.limit = sregs.idt.limit;
4362 env->idt.base = sregs.idt.base;
4363 env->gdt.limit = sregs.gdt.limit;
4364 env->gdt.base = sregs.gdt.base;
4365
4366 env->cr[0] = sregs.cr0;
4367 env->cr[2] = sregs.cr2;
4368 env->cr[3] = sregs.cr3;
4369 env->cr[4] = sregs.cr4;
4370
4371 env->efer = sregs.efer;
4372 if (sev_es_enabled() && env->efer & MSR_EFER_LME &&
4373 env->cr[0] & CR0_PG_MASK) {
4374 env->efer |= MSR_EFER_LMA;
4375 }
4376
4377 env->pdptrs_valid = sregs.flags & KVM_SREGS2_FLAGS_PDPTRS_VALID;
4378
4379 if (env->pdptrs_valid) {
4380 for (i = 0; i < 4; i++) {
4381 env->pdptrs[i] = sregs.pdptrs[i];
4382 }
4383 }
4384
4385 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
4386 x86_update_hflags(env);
4387
4388 return 0;
4389 }
4390
kvm_get_msrs(X86CPU * cpu)4391 static int kvm_get_msrs(X86CPU *cpu)
4392 {
4393 CPUX86State *env = &cpu->env;
4394 struct kvm_msr_entry *msrs = cpu->kvm_msr_buf->entries;
4395 int ret, i;
4396 uint64_t mtrr_top_bits;
4397
4398 kvm_msr_buf_reset(cpu);
4399
4400 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, 0);
4401 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, 0);
4402 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, 0);
4403 kvm_msr_entry_add(cpu, MSR_PAT, 0);
4404 if (has_msr_star) {
4405 kvm_msr_entry_add(cpu, MSR_STAR, 0);
4406 }
4407 if (has_msr_hsave_pa) {
4408 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, 0);
4409 }
4410 if (has_msr_tsc_aux) {
4411 kvm_msr_entry_add(cpu, MSR_TSC_AUX, 0);
4412 }
4413 if (has_msr_tsc_adjust) {
4414 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, 0);
4415 }
4416 if (has_msr_tsc_deadline) {
4417 kvm_msr_entry_add(cpu, MSR_IA32_TSCDEADLINE, 0);
4418 }
4419 if (has_msr_misc_enable) {
4420 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE, 0);
4421 }
4422 if (has_msr_smbase) {
4423 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, 0);
4424 }
4425 if (has_msr_smi_count) {
4426 kvm_msr_entry_add(cpu, MSR_SMI_COUNT, 0);
4427 }
4428 if (has_msr_feature_control) {
4429 kvm_msr_entry_add(cpu, MSR_IA32_FEATURE_CONTROL, 0);
4430 }
4431 if (has_msr_pkrs) {
4432 kvm_msr_entry_add(cpu, MSR_IA32_PKRS, 0);
4433 }
4434 if (has_msr_bndcfgs) {
4435 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, 0);
4436 }
4437 if (has_msr_xss) {
4438 kvm_msr_entry_add(cpu, MSR_IA32_XSS, 0);
4439 }
4440 if (has_msr_umwait) {
4441 kvm_msr_entry_add(cpu, MSR_IA32_UMWAIT_CONTROL, 0);
4442 }
4443 if (has_msr_spec_ctrl) {
4444 kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, 0);
4445 }
4446 if (has_tsc_scale_msr) {
4447 kvm_msr_entry_add(cpu, MSR_AMD64_TSC_RATIO, 0);
4448 }
4449
4450 if (has_msr_tsx_ctrl) {
4451 kvm_msr_entry_add(cpu, MSR_IA32_TSX_CTRL, 0);
4452 }
4453 if (has_msr_virt_ssbd) {
4454 kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, 0);
4455 }
4456 if (!env->tsc_valid) {
4457 kvm_msr_entry_add(cpu, MSR_IA32_TSC, 0);
4458 env->tsc_valid = !runstate_is_running();
4459 }
4460 if (has_msr_hwcr) {
4461 kvm_msr_entry_add(cpu, MSR_K7_HWCR, 0);
4462 }
4463
4464 #ifdef TARGET_X86_64
4465 if (lm_capable_kernel) {
4466 kvm_msr_entry_add(cpu, MSR_CSTAR, 0);
4467 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, 0);
4468 kvm_msr_entry_add(cpu, MSR_FMASK, 0);
4469 kvm_msr_entry_add(cpu, MSR_LSTAR, 0);
4470 if (env->features[FEAT_7_1_EAX] & CPUID_7_1_EAX_FRED) {
4471 kvm_msr_entry_add(cpu, MSR_IA32_FRED_RSP0, 0);
4472 kvm_msr_entry_add(cpu, MSR_IA32_FRED_RSP1, 0);
4473 kvm_msr_entry_add(cpu, MSR_IA32_FRED_RSP2, 0);
4474 kvm_msr_entry_add(cpu, MSR_IA32_FRED_RSP3, 0);
4475 kvm_msr_entry_add(cpu, MSR_IA32_FRED_STKLVLS, 0);
4476 kvm_msr_entry_add(cpu, MSR_IA32_FRED_SSP1, 0);
4477 kvm_msr_entry_add(cpu, MSR_IA32_FRED_SSP2, 0);
4478 kvm_msr_entry_add(cpu, MSR_IA32_FRED_SSP3, 0);
4479 kvm_msr_entry_add(cpu, MSR_IA32_FRED_CONFIG, 0);
4480 }
4481 }
4482 #endif
4483 if (env->features[FEAT_KVM] & (CPUID_KVM_CLOCK | CPUID_KVM_CLOCK2)) {
4484 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, 0);
4485 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, 0);
4486 }
4487 if (env->features[FEAT_KVM] & CPUID_KVM_ASYNCPF_INT) {
4488 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_INT, 0);
4489 }
4490 if (env->features[FEAT_KVM] & CPUID_KVM_ASYNCPF) {
4491 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, 0);
4492 }
4493 if (env->features[FEAT_KVM] & CPUID_KVM_PV_EOI) {
4494 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, 0);
4495 }
4496 if (env->features[FEAT_KVM] & CPUID_KVM_STEAL_TIME) {
4497 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, 0);
4498 }
4499 if (env->features[FEAT_KVM] & CPUID_KVM_POLL_CONTROL) {
4500 kvm_msr_entry_add(cpu, MSR_KVM_POLL_CONTROL, 1);
4501 }
4502 if (has_architectural_pmu_version > 0) {
4503 if (has_architectural_pmu_version > 1) {
4504 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
4505 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
4506 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS, 0);
4507 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL, 0);
4508 }
4509 for (i = 0; i < num_architectural_pmu_fixed_counters; i++) {
4510 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i, 0);
4511 }
4512 for (i = 0; i < num_architectural_pmu_gp_counters; i++) {
4513 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i, 0);
4514 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i, 0);
4515 }
4516 }
4517
4518 if (env->mcg_cap) {
4519 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, 0);
4520 kvm_msr_entry_add(cpu, MSR_MCG_CTL, 0);
4521 if (has_msr_mcg_ext_ctl) {
4522 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, 0);
4523 }
4524 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
4525 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, 0);
4526 }
4527 }
4528
4529 if (has_msr_hv_hypercall) {
4530 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL, 0);
4531 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID, 0);
4532 }
4533 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VAPIC)) {
4534 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE, 0);
4535 }
4536 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_TIME)) {
4537 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC, 0);
4538 }
4539 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_REENLIGHTENMENT)) {
4540 kvm_msr_entry_add(cpu, HV_X64_MSR_REENLIGHTENMENT_CONTROL, 0);
4541 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_CONTROL, 0);
4542 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_STATUS, 0);
4543 }
4544 if (has_msr_hv_syndbg_options) {
4545 kvm_msr_entry_add(cpu, HV_X64_MSR_SYNDBG_OPTIONS, 0);
4546 }
4547 if (has_msr_hv_crash) {
4548 int j;
4549
4550 for (j = 0; j < HV_CRASH_PARAMS; j++) {
4551 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j, 0);
4552 }
4553 }
4554 if (has_msr_hv_runtime) {
4555 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, 0);
4556 }
4557 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
4558 uint32_t msr;
4559
4560 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL, 0);
4561 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP, 0);
4562 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP, 0);
4563 for (msr = HV_X64_MSR_SINT0; msr <= HV_X64_MSR_SINT15; msr++) {
4564 kvm_msr_entry_add(cpu, msr, 0);
4565 }
4566 }
4567 if (has_msr_hv_stimer) {
4568 uint32_t msr;
4569
4570 for (msr = HV_X64_MSR_STIMER0_CONFIG; msr <= HV_X64_MSR_STIMER3_COUNT;
4571 msr++) {
4572 kvm_msr_entry_add(cpu, msr, 0);
4573 }
4574 }
4575 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
4576 kvm_msr_entry_add(cpu, MSR_MTRRdefType, 0);
4577 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, 0);
4578 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, 0);
4579 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, 0);
4580 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, 0);
4581 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, 0);
4582 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, 0);
4583 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, 0);
4584 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, 0);
4585 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, 0);
4586 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, 0);
4587 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, 0);
4588 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
4589 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i), 0);
4590 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), 0);
4591 }
4592 }
4593
4594 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) {
4595 int addr_num =
4596 kvm_arch_get_supported_cpuid(kvm_state, 0x14, 1, R_EAX) & 0x7;
4597
4598 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL, 0);
4599 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_STATUS, 0);
4600 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_BASE, 0);
4601 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_MASK, 0);
4602 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CR3_MATCH, 0);
4603 for (i = 0; i < addr_num; i++) {
4604 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i, 0);
4605 }
4606 }
4607
4608 if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_SGX_LC) {
4609 kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH0, 0);
4610 kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH1, 0);
4611 kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH2, 0);
4612 kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH3, 0);
4613 }
4614
4615 if (env->features[FEAT_XSAVE] & CPUID_D_1_EAX_XFD) {
4616 kvm_msr_entry_add(cpu, MSR_IA32_XFD, 0);
4617 kvm_msr_entry_add(cpu, MSR_IA32_XFD_ERR, 0);
4618 }
4619
4620 if (kvm_enabled() && cpu->enable_pmu &&
4621 (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR)) {
4622 uint64_t depth;
4623
4624 ret = kvm_get_one_msr(cpu, MSR_ARCH_LBR_DEPTH, &depth);
4625 if (ret == 1 && depth == ARCH_LBR_NR_ENTRIES) {
4626 kvm_msr_entry_add(cpu, MSR_ARCH_LBR_CTL, 0);
4627 kvm_msr_entry_add(cpu, MSR_ARCH_LBR_DEPTH, 0);
4628
4629 for (i = 0; i < ARCH_LBR_NR_ENTRIES; i++) {
4630 kvm_msr_entry_add(cpu, MSR_ARCH_LBR_FROM_0 + i, 0);
4631 kvm_msr_entry_add(cpu, MSR_ARCH_LBR_TO_0 + i, 0);
4632 kvm_msr_entry_add(cpu, MSR_ARCH_LBR_INFO_0 + i, 0);
4633 }
4634 }
4635 }
4636
4637 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, cpu->kvm_msr_buf);
4638 if (ret < 0) {
4639 return ret;
4640 }
4641
4642 if (ret < cpu->kvm_msr_buf->nmsrs) {
4643 struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
4644 error_report("error: failed to get MSR 0x%" PRIx32,
4645 (uint32_t)e->index);
4646 }
4647
4648 assert(ret == cpu->kvm_msr_buf->nmsrs);
4649 /*
4650 * MTRR masks: Each mask consists of 5 parts
4651 * a 10..0: must be zero
4652 * b 11 : valid bit
4653 * c n-1.12: actual mask bits
4654 * d 51..n: reserved must be zero
4655 * e 63.52: reserved must be zero
4656 *
4657 * 'n' is the number of physical bits supported by the CPU and is
4658 * apparently always <= 52. We know our 'n' but don't know what
4659 * the destinations 'n' is; it might be smaller, in which case
4660 * it masks (c) on loading. It might be larger, in which case
4661 * we fill 'd' so that d..c is consistent irrespetive of the 'n'
4662 * we're migrating to.
4663 */
4664
4665 if (cpu->fill_mtrr_mask) {
4666 QEMU_BUILD_BUG_ON(TARGET_PHYS_ADDR_SPACE_BITS > 52);
4667 assert(cpu->phys_bits <= TARGET_PHYS_ADDR_SPACE_BITS);
4668 mtrr_top_bits = MAKE_64BIT_MASK(cpu->phys_bits, 52 - cpu->phys_bits);
4669 } else {
4670 mtrr_top_bits = 0;
4671 }
4672
4673 for (i = 0; i < ret; i++) {
4674 uint32_t index = msrs[i].index;
4675 switch (index) {
4676 case MSR_IA32_SYSENTER_CS:
4677 env->sysenter_cs = msrs[i].data;
4678 break;
4679 case MSR_IA32_SYSENTER_ESP:
4680 env->sysenter_esp = msrs[i].data;
4681 break;
4682 case MSR_IA32_SYSENTER_EIP:
4683 env->sysenter_eip = msrs[i].data;
4684 break;
4685 case MSR_PAT:
4686 env->pat = msrs[i].data;
4687 break;
4688 case MSR_STAR:
4689 env->star = msrs[i].data;
4690 break;
4691 #ifdef TARGET_X86_64
4692 case MSR_CSTAR:
4693 env->cstar = msrs[i].data;
4694 break;
4695 case MSR_KERNELGSBASE:
4696 env->kernelgsbase = msrs[i].data;
4697 break;
4698 case MSR_FMASK:
4699 env->fmask = msrs[i].data;
4700 break;
4701 case MSR_LSTAR:
4702 env->lstar = msrs[i].data;
4703 break;
4704 case MSR_IA32_FRED_RSP0:
4705 env->fred_rsp0 = msrs[i].data;
4706 break;
4707 case MSR_IA32_FRED_RSP1:
4708 env->fred_rsp1 = msrs[i].data;
4709 break;
4710 case MSR_IA32_FRED_RSP2:
4711 env->fred_rsp2 = msrs[i].data;
4712 break;
4713 case MSR_IA32_FRED_RSP3:
4714 env->fred_rsp3 = msrs[i].data;
4715 break;
4716 case MSR_IA32_FRED_STKLVLS:
4717 env->fred_stklvls = msrs[i].data;
4718 break;
4719 case MSR_IA32_FRED_SSP1:
4720 env->fred_ssp1 = msrs[i].data;
4721 break;
4722 case MSR_IA32_FRED_SSP2:
4723 env->fred_ssp2 = msrs[i].data;
4724 break;
4725 case MSR_IA32_FRED_SSP3:
4726 env->fred_ssp3 = msrs[i].data;
4727 break;
4728 case MSR_IA32_FRED_CONFIG:
4729 env->fred_config = msrs[i].data;
4730 break;
4731 #endif
4732 case MSR_IA32_TSC:
4733 env->tsc = msrs[i].data;
4734 break;
4735 case MSR_TSC_AUX:
4736 env->tsc_aux = msrs[i].data;
4737 break;
4738 case MSR_TSC_ADJUST:
4739 env->tsc_adjust = msrs[i].data;
4740 break;
4741 case MSR_IA32_TSCDEADLINE:
4742 env->tsc_deadline = msrs[i].data;
4743 break;
4744 case MSR_VM_HSAVE_PA:
4745 env->vm_hsave = msrs[i].data;
4746 break;
4747 case MSR_KVM_SYSTEM_TIME:
4748 env->system_time_msr = msrs[i].data;
4749 break;
4750 case MSR_KVM_WALL_CLOCK:
4751 env->wall_clock_msr = msrs[i].data;
4752 break;
4753 case MSR_MCG_STATUS:
4754 env->mcg_status = msrs[i].data;
4755 break;
4756 case MSR_MCG_CTL:
4757 env->mcg_ctl = msrs[i].data;
4758 break;
4759 case MSR_MCG_EXT_CTL:
4760 env->mcg_ext_ctl = msrs[i].data;
4761 break;
4762 case MSR_IA32_MISC_ENABLE:
4763 env->msr_ia32_misc_enable = msrs[i].data;
4764 break;
4765 case MSR_IA32_SMBASE:
4766 env->smbase = msrs[i].data;
4767 break;
4768 case MSR_SMI_COUNT:
4769 env->msr_smi_count = msrs[i].data;
4770 break;
4771 case MSR_IA32_FEATURE_CONTROL:
4772 env->msr_ia32_feature_control = msrs[i].data;
4773 break;
4774 case MSR_IA32_BNDCFGS:
4775 env->msr_bndcfgs = msrs[i].data;
4776 break;
4777 case MSR_IA32_XSS:
4778 env->xss = msrs[i].data;
4779 break;
4780 case MSR_IA32_UMWAIT_CONTROL:
4781 env->umwait = msrs[i].data;
4782 break;
4783 case MSR_IA32_PKRS:
4784 env->pkrs = msrs[i].data;
4785 break;
4786 default:
4787 if (msrs[i].index >= MSR_MC0_CTL &&
4788 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
4789 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
4790 }
4791 break;
4792 case MSR_KVM_ASYNC_PF_EN:
4793 env->async_pf_en_msr = msrs[i].data;
4794 break;
4795 case MSR_KVM_ASYNC_PF_INT:
4796 env->async_pf_int_msr = msrs[i].data;
4797 break;
4798 case MSR_KVM_PV_EOI_EN:
4799 env->pv_eoi_en_msr = msrs[i].data;
4800 break;
4801 case MSR_KVM_STEAL_TIME:
4802 env->steal_time_msr = msrs[i].data;
4803 break;
4804 case MSR_KVM_POLL_CONTROL: {
4805 env->poll_control_msr = msrs[i].data;
4806 break;
4807 }
4808 case MSR_CORE_PERF_FIXED_CTR_CTRL:
4809 env->msr_fixed_ctr_ctrl = msrs[i].data;
4810 break;
4811 case MSR_CORE_PERF_GLOBAL_CTRL:
4812 env->msr_global_ctrl = msrs[i].data;
4813 break;
4814 case MSR_CORE_PERF_GLOBAL_STATUS:
4815 env->msr_global_status = msrs[i].data;
4816 break;
4817 case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
4818 env->msr_global_ovf_ctrl = msrs[i].data;
4819 break;
4820 case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1:
4821 env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] = msrs[i].data;
4822 break;
4823 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR0 + MAX_GP_COUNTERS - 1:
4824 env->msr_gp_counters[index - MSR_P6_PERFCTR0] = msrs[i].data;
4825 break;
4826 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1:
4827 env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data;
4828 break;
4829 case HV_X64_MSR_HYPERCALL:
4830 env->msr_hv_hypercall = msrs[i].data;
4831 break;
4832 case HV_X64_MSR_GUEST_OS_ID:
4833 env->msr_hv_guest_os_id = msrs[i].data;
4834 break;
4835 case HV_X64_MSR_APIC_ASSIST_PAGE:
4836 env->msr_hv_vapic = msrs[i].data;
4837 break;
4838 case HV_X64_MSR_REFERENCE_TSC:
4839 env->msr_hv_tsc = msrs[i].data;
4840 break;
4841 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
4842 env->msr_hv_crash_params[index - HV_X64_MSR_CRASH_P0] = msrs[i].data;
4843 break;
4844 case HV_X64_MSR_VP_RUNTIME:
4845 env->msr_hv_runtime = msrs[i].data;
4846 break;
4847 case HV_X64_MSR_SCONTROL:
4848 env->msr_hv_synic_control = msrs[i].data;
4849 break;
4850 case HV_X64_MSR_SIEFP:
4851 env->msr_hv_synic_evt_page = msrs[i].data;
4852 break;
4853 case HV_X64_MSR_SIMP:
4854 env->msr_hv_synic_msg_page = msrs[i].data;
4855 break;
4856 case HV_X64_MSR_SINT0 ... HV_X64_MSR_SINT15:
4857 env->msr_hv_synic_sint[index - HV_X64_MSR_SINT0] = msrs[i].data;
4858 break;
4859 case HV_X64_MSR_STIMER0_CONFIG:
4860 case HV_X64_MSR_STIMER1_CONFIG:
4861 case HV_X64_MSR_STIMER2_CONFIG:
4862 case HV_X64_MSR_STIMER3_CONFIG:
4863 env->msr_hv_stimer_config[(index - HV_X64_MSR_STIMER0_CONFIG)/2] =
4864 msrs[i].data;
4865 break;
4866 case HV_X64_MSR_STIMER0_COUNT:
4867 case HV_X64_MSR_STIMER1_COUNT:
4868 case HV_X64_MSR_STIMER2_COUNT:
4869 case HV_X64_MSR_STIMER3_COUNT:
4870 env->msr_hv_stimer_count[(index - HV_X64_MSR_STIMER0_COUNT)/2] =
4871 msrs[i].data;
4872 break;
4873 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
4874 env->msr_hv_reenlightenment_control = msrs[i].data;
4875 break;
4876 case HV_X64_MSR_TSC_EMULATION_CONTROL:
4877 env->msr_hv_tsc_emulation_control = msrs[i].data;
4878 break;
4879 case HV_X64_MSR_TSC_EMULATION_STATUS:
4880 env->msr_hv_tsc_emulation_status = msrs[i].data;
4881 break;
4882 case HV_X64_MSR_SYNDBG_OPTIONS:
4883 env->msr_hv_syndbg_options = msrs[i].data;
4884 break;
4885 case MSR_MTRRdefType:
4886 env->mtrr_deftype = msrs[i].data;
4887 break;
4888 case MSR_MTRRfix64K_00000:
4889 env->mtrr_fixed[0] = msrs[i].data;
4890 break;
4891 case MSR_MTRRfix16K_80000:
4892 env->mtrr_fixed[1] = msrs[i].data;
4893 break;
4894 case MSR_MTRRfix16K_A0000:
4895 env->mtrr_fixed[2] = msrs[i].data;
4896 break;
4897 case MSR_MTRRfix4K_C0000:
4898 env->mtrr_fixed[3] = msrs[i].data;
4899 break;
4900 case MSR_MTRRfix4K_C8000:
4901 env->mtrr_fixed[4] = msrs[i].data;
4902 break;
4903 case MSR_MTRRfix4K_D0000:
4904 env->mtrr_fixed[5] = msrs[i].data;
4905 break;
4906 case MSR_MTRRfix4K_D8000:
4907 env->mtrr_fixed[6] = msrs[i].data;
4908 break;
4909 case MSR_MTRRfix4K_E0000:
4910 env->mtrr_fixed[7] = msrs[i].data;
4911 break;
4912 case MSR_MTRRfix4K_E8000:
4913 env->mtrr_fixed[8] = msrs[i].data;
4914 break;
4915 case MSR_MTRRfix4K_F0000:
4916 env->mtrr_fixed[9] = msrs[i].data;
4917 break;
4918 case MSR_MTRRfix4K_F8000:
4919 env->mtrr_fixed[10] = msrs[i].data;
4920 break;
4921 case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT - 1):
4922 if (index & 1) {
4923 env->mtrr_var[MSR_MTRRphysIndex(index)].mask = msrs[i].data |
4924 mtrr_top_bits;
4925 } else {
4926 env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data;
4927 }
4928 break;
4929 case MSR_IA32_SPEC_CTRL:
4930 env->spec_ctrl = msrs[i].data;
4931 break;
4932 case MSR_AMD64_TSC_RATIO:
4933 env->amd_tsc_scale_msr = msrs[i].data;
4934 break;
4935 case MSR_IA32_TSX_CTRL:
4936 env->tsx_ctrl = msrs[i].data;
4937 break;
4938 case MSR_VIRT_SSBD:
4939 env->virt_ssbd = msrs[i].data;
4940 break;
4941 case MSR_IA32_RTIT_CTL:
4942 env->msr_rtit_ctrl = msrs[i].data;
4943 break;
4944 case MSR_IA32_RTIT_STATUS:
4945 env->msr_rtit_status = msrs[i].data;
4946 break;
4947 case MSR_IA32_RTIT_OUTPUT_BASE:
4948 env->msr_rtit_output_base = msrs[i].data;
4949 break;
4950 case MSR_IA32_RTIT_OUTPUT_MASK:
4951 env->msr_rtit_output_mask = msrs[i].data;
4952 break;
4953 case MSR_IA32_RTIT_CR3_MATCH:
4954 env->msr_rtit_cr3_match = msrs[i].data;
4955 break;
4956 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
4957 env->msr_rtit_addrs[index - MSR_IA32_RTIT_ADDR0_A] = msrs[i].data;
4958 break;
4959 case MSR_IA32_SGXLEPUBKEYHASH0 ... MSR_IA32_SGXLEPUBKEYHASH3:
4960 env->msr_ia32_sgxlepubkeyhash[index - MSR_IA32_SGXLEPUBKEYHASH0] =
4961 msrs[i].data;
4962 break;
4963 case MSR_IA32_XFD:
4964 env->msr_xfd = msrs[i].data;
4965 break;
4966 case MSR_IA32_XFD_ERR:
4967 env->msr_xfd_err = msrs[i].data;
4968 break;
4969 case MSR_ARCH_LBR_CTL:
4970 env->msr_lbr_ctl = msrs[i].data;
4971 break;
4972 case MSR_ARCH_LBR_DEPTH:
4973 env->msr_lbr_depth = msrs[i].data;
4974 break;
4975 case MSR_ARCH_LBR_FROM_0 ... MSR_ARCH_LBR_FROM_0 + 31:
4976 env->lbr_records[index - MSR_ARCH_LBR_FROM_0].from = msrs[i].data;
4977 break;
4978 case MSR_ARCH_LBR_TO_0 ... MSR_ARCH_LBR_TO_0 + 31:
4979 env->lbr_records[index - MSR_ARCH_LBR_TO_0].to = msrs[i].data;
4980 break;
4981 case MSR_ARCH_LBR_INFO_0 ... MSR_ARCH_LBR_INFO_0 + 31:
4982 env->lbr_records[index - MSR_ARCH_LBR_INFO_0].info = msrs[i].data;
4983 break;
4984 case MSR_K7_HWCR:
4985 env->msr_hwcr = msrs[i].data;
4986 break;
4987 }
4988 }
4989
4990 return 0;
4991 }
4992
kvm_put_mp_state(X86CPU * cpu)4993 static int kvm_put_mp_state(X86CPU *cpu)
4994 {
4995 struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state };
4996
4997 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state);
4998 }
4999
kvm_get_mp_state(X86CPU * cpu)5000 static int kvm_get_mp_state(X86CPU *cpu)
5001 {
5002 CPUState *cs = CPU(cpu);
5003 CPUX86State *env = &cpu->env;
5004 struct kvm_mp_state mp_state;
5005 int ret;
5006
5007 ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state);
5008 if (ret < 0) {
5009 return ret;
5010 }
5011 env->mp_state = mp_state.mp_state;
5012 if (kvm_irqchip_in_kernel()) {
5013 cs->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
5014 }
5015 return 0;
5016 }
5017
kvm_get_apic(X86CPU * cpu)5018 static int kvm_get_apic(X86CPU *cpu)
5019 {
5020 DeviceState *apic = cpu->apic_state;
5021 struct kvm_lapic_state kapic;
5022 int ret;
5023
5024 if (apic && kvm_irqchip_in_kernel()) {
5025 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic);
5026 if (ret < 0) {
5027 return ret;
5028 }
5029
5030 kvm_get_apic_state(apic, &kapic);
5031 }
5032 return 0;
5033 }
5034
kvm_put_vcpu_events(X86CPU * cpu,int level)5035 static int kvm_put_vcpu_events(X86CPU *cpu, int level)
5036 {
5037 CPUState *cs = CPU(cpu);
5038 CPUX86State *env = &cpu->env;
5039 struct kvm_vcpu_events events = {};
5040
5041 events.flags = 0;
5042
5043 if (has_exception_payload) {
5044 events.flags |= KVM_VCPUEVENT_VALID_PAYLOAD;
5045 events.exception.pending = env->exception_pending;
5046 events.exception_has_payload = env->exception_has_payload;
5047 events.exception_payload = env->exception_payload;
5048 }
5049 events.exception.nr = env->exception_nr;
5050 events.exception.injected = env->exception_injected;
5051 events.exception.has_error_code = env->has_error_code;
5052 events.exception.error_code = env->error_code;
5053
5054 events.interrupt.injected = (env->interrupt_injected >= 0);
5055 events.interrupt.nr = env->interrupt_injected;
5056 events.interrupt.soft = env->soft_interrupt;
5057
5058 events.nmi.injected = env->nmi_injected;
5059 events.nmi.pending = env->nmi_pending;
5060 events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
5061
5062 events.sipi_vector = env->sipi_vector;
5063
5064 if (has_msr_smbase) {
5065 events.flags |= KVM_VCPUEVENT_VALID_SMM;
5066 events.smi.smm = !!(env->hflags & HF_SMM_MASK);
5067 events.smi.smm_inside_nmi = !!(env->hflags2 & HF2_SMM_INSIDE_NMI_MASK);
5068 if (kvm_irqchip_in_kernel()) {
5069 /* As soon as these are moved to the kernel, remove them
5070 * from cs->interrupt_request.
5071 */
5072 events.smi.pending = cs->interrupt_request & CPU_INTERRUPT_SMI;
5073 events.smi.latched_init = cs->interrupt_request & CPU_INTERRUPT_INIT;
5074 cs->interrupt_request &= ~(CPU_INTERRUPT_INIT | CPU_INTERRUPT_SMI);
5075 } else {
5076 /* Keep these in cs->interrupt_request. */
5077 events.smi.pending = 0;
5078 events.smi.latched_init = 0;
5079 }
5080 }
5081
5082 if (level >= KVM_PUT_RESET_STATE) {
5083 events.flags |= KVM_VCPUEVENT_VALID_NMI_PENDING;
5084 if (env->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
5085 events.flags |= KVM_VCPUEVENT_VALID_SIPI_VECTOR;
5086 }
5087 }
5088
5089 if (has_triple_fault_event) {
5090 events.flags |= KVM_VCPUEVENT_VALID_TRIPLE_FAULT;
5091 events.triple_fault.pending = env->triple_fault_pending;
5092 }
5093
5094 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events);
5095 }
5096
kvm_get_vcpu_events(X86CPU * cpu)5097 static int kvm_get_vcpu_events(X86CPU *cpu)
5098 {
5099 CPUX86State *env = &cpu->env;
5100 struct kvm_vcpu_events events;
5101 int ret;
5102
5103 memset(&events, 0, sizeof(events));
5104 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events);
5105 if (ret < 0) {
5106 return ret;
5107 }
5108
5109 if (events.flags & KVM_VCPUEVENT_VALID_PAYLOAD) {
5110 env->exception_pending = events.exception.pending;
5111 env->exception_has_payload = events.exception_has_payload;
5112 env->exception_payload = events.exception_payload;
5113 } else {
5114 env->exception_pending = 0;
5115 env->exception_has_payload = false;
5116 }
5117 env->exception_injected = events.exception.injected;
5118 env->exception_nr =
5119 (env->exception_pending || env->exception_injected) ?
5120 events.exception.nr : -1;
5121 env->has_error_code = events.exception.has_error_code;
5122 env->error_code = events.exception.error_code;
5123
5124 env->interrupt_injected =
5125 events.interrupt.injected ? events.interrupt.nr : -1;
5126 env->soft_interrupt = events.interrupt.soft;
5127
5128 env->nmi_injected = events.nmi.injected;
5129 env->nmi_pending = events.nmi.pending;
5130 if (events.nmi.masked) {
5131 env->hflags2 |= HF2_NMI_MASK;
5132 } else {
5133 env->hflags2 &= ~HF2_NMI_MASK;
5134 }
5135
5136 if (events.flags & KVM_VCPUEVENT_VALID_SMM) {
5137 if (events.smi.smm) {
5138 env->hflags |= HF_SMM_MASK;
5139 } else {
5140 env->hflags &= ~HF_SMM_MASK;
5141 }
5142 if (events.smi.pending) {
5143 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
5144 } else {
5145 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
5146 }
5147 if (events.smi.smm_inside_nmi) {
5148 env->hflags2 |= HF2_SMM_INSIDE_NMI_MASK;
5149 } else {
5150 env->hflags2 &= ~HF2_SMM_INSIDE_NMI_MASK;
5151 }
5152 if (events.smi.latched_init) {
5153 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
5154 } else {
5155 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
5156 }
5157 }
5158
5159 if (events.flags & KVM_VCPUEVENT_VALID_TRIPLE_FAULT) {
5160 env->triple_fault_pending = events.triple_fault.pending;
5161 }
5162
5163 env->sipi_vector = events.sipi_vector;
5164
5165 return 0;
5166 }
5167
kvm_put_debugregs(X86CPU * cpu)5168 static int kvm_put_debugregs(X86CPU *cpu)
5169 {
5170 CPUX86State *env = &cpu->env;
5171 struct kvm_debugregs dbgregs;
5172 int i;
5173
5174 memset(&dbgregs, 0, sizeof(dbgregs));
5175 for (i = 0; i < 4; i++) {
5176 dbgregs.db[i] = env->dr[i];
5177 }
5178 dbgregs.dr6 = env->dr[6];
5179 dbgregs.dr7 = env->dr[7];
5180 dbgregs.flags = 0;
5181
5182 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs);
5183 }
5184
kvm_get_debugregs(X86CPU * cpu)5185 static int kvm_get_debugregs(X86CPU *cpu)
5186 {
5187 CPUX86State *env = &cpu->env;
5188 struct kvm_debugregs dbgregs;
5189 int i, ret;
5190
5191 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs);
5192 if (ret < 0) {
5193 return ret;
5194 }
5195 for (i = 0; i < 4; i++) {
5196 env->dr[i] = dbgregs.db[i];
5197 }
5198 env->dr[4] = env->dr[6] = dbgregs.dr6;
5199 env->dr[5] = env->dr[7] = dbgregs.dr7;
5200
5201 return 0;
5202 }
5203
kvm_put_nested_state(X86CPU * cpu)5204 static int kvm_put_nested_state(X86CPU *cpu)
5205 {
5206 CPUX86State *env = &cpu->env;
5207 int max_nested_state_len = kvm_max_nested_state_length();
5208
5209 if (!env->nested_state) {
5210 return 0;
5211 }
5212
5213 /*
5214 * Copy flags that are affected by reset from env->hflags and env->hflags2.
5215 */
5216 if (env->hflags & HF_GUEST_MASK) {
5217 env->nested_state->flags |= KVM_STATE_NESTED_GUEST_MODE;
5218 } else {
5219 env->nested_state->flags &= ~KVM_STATE_NESTED_GUEST_MODE;
5220 }
5221
5222 /* Don't set KVM_STATE_NESTED_GIF_SET on VMX as it is illegal */
5223 if (cpu_has_svm(env) && (env->hflags2 & HF2_GIF_MASK)) {
5224 env->nested_state->flags |= KVM_STATE_NESTED_GIF_SET;
5225 } else {
5226 env->nested_state->flags &= ~KVM_STATE_NESTED_GIF_SET;
5227 }
5228
5229 assert(env->nested_state->size <= max_nested_state_len);
5230 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_NESTED_STATE, env->nested_state);
5231 }
5232
kvm_get_nested_state(X86CPU * cpu)5233 static int kvm_get_nested_state(X86CPU *cpu)
5234 {
5235 CPUX86State *env = &cpu->env;
5236 int max_nested_state_len = kvm_max_nested_state_length();
5237 int ret;
5238
5239 if (!env->nested_state) {
5240 return 0;
5241 }
5242
5243 /*
5244 * It is possible that migration restored a smaller size into
5245 * nested_state->hdr.size than what our kernel support.
5246 * We preserve migration origin nested_state->hdr.size for
5247 * call to KVM_SET_NESTED_STATE but wish that our next call
5248 * to KVM_GET_NESTED_STATE will use max size our kernel support.
5249 */
5250 env->nested_state->size = max_nested_state_len;
5251
5252 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_NESTED_STATE, env->nested_state);
5253 if (ret < 0) {
5254 return ret;
5255 }
5256
5257 /*
5258 * Copy flags that are affected by reset to env->hflags and env->hflags2.
5259 */
5260 if (env->nested_state->flags & KVM_STATE_NESTED_GUEST_MODE) {
5261 env->hflags |= HF_GUEST_MASK;
5262 } else {
5263 env->hflags &= ~HF_GUEST_MASK;
5264 }
5265
5266 /* Keep HF2_GIF_MASK set on !SVM as x86_cpu_pending_interrupt() needs it */
5267 if (cpu_has_svm(env)) {
5268 if (env->nested_state->flags & KVM_STATE_NESTED_GIF_SET) {
5269 env->hflags2 |= HF2_GIF_MASK;
5270 } else {
5271 env->hflags2 &= ~HF2_GIF_MASK;
5272 }
5273 }
5274
5275 return ret;
5276 }
5277
kvm_arch_put_registers(CPUState * cpu,int level,Error ** errp)5278 int kvm_arch_put_registers(CPUState *cpu, int level, Error **errp)
5279 {
5280 X86CPU *x86_cpu = X86_CPU(cpu);
5281 int ret;
5282
5283 assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));
5284
5285 /*
5286 * Put MSR_IA32_FEATURE_CONTROL first, this ensures the VM gets out of VMX
5287 * root operation upon vCPU reset. kvm_put_msr_feature_control() should also
5288 * precede kvm_put_nested_state() when 'real' nested state is set.
5289 */
5290 if (level >= KVM_PUT_RESET_STATE) {
5291 ret = kvm_put_msr_feature_control(x86_cpu);
5292 if (ret < 0) {
5293 error_setg_errno(errp, -ret, "Failed to set feature control MSR");
5294 return ret;
5295 }
5296 }
5297
5298 /* must be before kvm_put_nested_state so that EFER.SVME is set */
5299 ret = has_sregs2 ? kvm_put_sregs2(x86_cpu) : kvm_put_sregs(x86_cpu);
5300 if (ret < 0) {
5301 error_setg_errno(errp, -ret, "Failed to set special registers");
5302 return ret;
5303 }
5304
5305 if (level >= KVM_PUT_RESET_STATE) {
5306 ret = kvm_put_nested_state(x86_cpu);
5307 if (ret < 0) {
5308 error_setg_errno(errp, -ret, "Failed to set nested state");
5309 return ret;
5310 }
5311 }
5312
5313 if (level == KVM_PUT_FULL_STATE) {
5314 /* We don't check for kvm_arch_set_tsc_khz() errors here,
5315 * because TSC frequency mismatch shouldn't abort migration,
5316 * unless the user explicitly asked for a more strict TSC
5317 * setting (e.g. using an explicit "tsc-freq" option).
5318 */
5319 kvm_arch_set_tsc_khz(cpu);
5320 }
5321
5322 #ifdef CONFIG_XEN_EMU
5323 if (xen_mode == XEN_EMULATE && level == KVM_PUT_FULL_STATE) {
5324 ret = kvm_put_xen_state(cpu);
5325 if (ret < 0) {
5326 error_setg_errno(errp, -ret, "Failed to set Xen state");
5327 return ret;
5328 }
5329 }
5330 #endif
5331
5332 ret = kvm_getput_regs(x86_cpu, 1);
5333 if (ret < 0) {
5334 error_setg_errno(errp, -ret, "Failed to set general purpose registers");
5335 return ret;
5336 }
5337 ret = kvm_put_xsave(x86_cpu);
5338 if (ret < 0) {
5339 error_setg_errno(errp, -ret, "Failed to set XSAVE");
5340 return ret;
5341 }
5342 ret = kvm_put_xcrs(x86_cpu);
5343 if (ret < 0) {
5344 error_setg_errno(errp, -ret, "Failed to set XCRs");
5345 return ret;
5346 }
5347 ret = kvm_put_msrs(x86_cpu, level);
5348 if (ret < 0) {
5349 error_setg_errno(errp, -ret, "Failed to set MSRs");
5350 return ret;
5351 }
5352 ret = kvm_put_vcpu_events(x86_cpu, level);
5353 if (ret < 0) {
5354 error_setg_errno(errp, -ret, "Failed to set vCPU events");
5355 return ret;
5356 }
5357 if (level >= KVM_PUT_RESET_STATE) {
5358 ret = kvm_put_mp_state(x86_cpu);
5359 if (ret < 0) {
5360 error_setg_errno(errp, -ret, "Failed to set MP state");
5361 return ret;
5362 }
5363 }
5364
5365 ret = kvm_put_tscdeadline_msr(x86_cpu);
5366 if (ret < 0) {
5367 error_setg_errno(errp, -ret, "Failed to set TSC deadline MSR");
5368 return ret;
5369 }
5370 ret = kvm_put_debugregs(x86_cpu);
5371 if (ret < 0) {
5372 error_setg_errno(errp, -ret, "Failed to set debug registers");
5373 return ret;
5374 }
5375 return 0;
5376 }
5377
kvm_arch_get_registers(CPUState * cs,Error ** errp)5378 int kvm_arch_get_registers(CPUState *cs, Error **errp)
5379 {
5380 X86CPU *cpu = X86_CPU(cs);
5381 int ret;
5382
5383 assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs));
5384
5385 ret = kvm_get_vcpu_events(cpu);
5386 if (ret < 0) {
5387 error_setg_errno(errp, -ret, "Failed to get vCPU events");
5388 goto out;
5389 }
5390 /*
5391 * KVM_GET_MPSTATE can modify CS and RIP, call it before
5392 * KVM_GET_REGS and KVM_GET_SREGS.
5393 */
5394 ret = kvm_get_mp_state(cpu);
5395 if (ret < 0) {
5396 error_setg_errno(errp, -ret, "Failed to get MP state");
5397 goto out;
5398 }
5399 ret = kvm_getput_regs(cpu, 0);
5400 if (ret < 0) {
5401 error_setg_errno(errp, -ret, "Failed to get general purpose registers");
5402 goto out;
5403 }
5404 ret = kvm_get_xsave(cpu);
5405 if (ret < 0) {
5406 error_setg_errno(errp, -ret, "Failed to get XSAVE");
5407 goto out;
5408 }
5409 ret = kvm_get_xcrs(cpu);
5410 if (ret < 0) {
5411 error_setg_errno(errp, -ret, "Failed to get XCRs");
5412 goto out;
5413 }
5414 ret = has_sregs2 ? kvm_get_sregs2(cpu) : kvm_get_sregs(cpu);
5415 if (ret < 0) {
5416 error_setg_errno(errp, -ret, "Failed to get special registers");
5417 goto out;
5418 }
5419 ret = kvm_get_msrs(cpu);
5420 if (ret < 0) {
5421 error_setg_errno(errp, -ret, "Failed to get MSRs");
5422 goto out;
5423 }
5424 ret = kvm_get_apic(cpu);
5425 if (ret < 0) {
5426 error_setg_errno(errp, -ret, "Failed to get APIC");
5427 goto out;
5428 }
5429 ret = kvm_get_debugregs(cpu);
5430 if (ret < 0) {
5431 error_setg_errno(errp, -ret, "Failed to get debug registers");
5432 goto out;
5433 }
5434 ret = kvm_get_nested_state(cpu);
5435 if (ret < 0) {
5436 error_setg_errno(errp, -ret, "Failed to get nested state");
5437 goto out;
5438 }
5439 #ifdef CONFIG_XEN_EMU
5440 if (xen_mode == XEN_EMULATE) {
5441 ret = kvm_get_xen_state(cs);
5442 if (ret < 0) {
5443 error_setg_errno(errp, -ret, "Failed to get Xen state");
5444 goto out;
5445 }
5446 }
5447 #endif
5448 ret = 0;
5449 out:
5450 cpu_sync_bndcs_hflags(&cpu->env);
5451 return ret;
5452 }
5453
kvm_arch_pre_run(CPUState * cpu,struct kvm_run * run)5454 void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run)
5455 {
5456 X86CPU *x86_cpu = X86_CPU(cpu);
5457 CPUX86State *env = &x86_cpu->env;
5458 int ret;
5459
5460 /* Inject NMI */
5461 if (cpu->interrupt_request & (CPU_INTERRUPT_NMI | CPU_INTERRUPT_SMI)) {
5462 if (cpu->interrupt_request & CPU_INTERRUPT_NMI) {
5463 bql_lock();
5464 cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
5465 bql_unlock();
5466 DPRINTF("injected NMI\n");
5467 ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
5468 if (ret < 0) {
5469 fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
5470 strerror(-ret));
5471 }
5472 }
5473 if (cpu->interrupt_request & CPU_INTERRUPT_SMI) {
5474 bql_lock();
5475 cpu->interrupt_request &= ~CPU_INTERRUPT_SMI;
5476 bql_unlock();
5477 DPRINTF("injected SMI\n");
5478 ret = kvm_vcpu_ioctl(cpu, KVM_SMI);
5479 if (ret < 0) {
5480 fprintf(stderr, "KVM: injection failed, SMI lost (%s)\n",
5481 strerror(-ret));
5482 }
5483 }
5484 }
5485
5486 if (!kvm_pic_in_kernel()) {
5487 bql_lock();
5488 }
5489
5490 /* Force the VCPU out of its inner loop to process any INIT requests
5491 * or (for userspace APIC, but it is cheap to combine the checks here)
5492 * pending TPR access reports.
5493 */
5494 if (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
5495 if ((cpu->interrupt_request & CPU_INTERRUPT_INIT) &&
5496 !(env->hflags & HF_SMM_MASK)) {
5497 cpu->exit_request = 1;
5498 }
5499 if (cpu->interrupt_request & CPU_INTERRUPT_TPR) {
5500 cpu->exit_request = 1;
5501 }
5502 }
5503
5504 if (!kvm_pic_in_kernel()) {
5505 /* Try to inject an interrupt if the guest can accept it */
5506 if (run->ready_for_interrupt_injection &&
5507 (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
5508 (env->eflags & IF_MASK)) {
5509 int irq;
5510
5511 cpu->interrupt_request &= ~CPU_INTERRUPT_HARD;
5512 irq = cpu_get_pic_interrupt(env);
5513 if (irq >= 0) {
5514 struct kvm_interrupt intr;
5515
5516 intr.irq = irq;
5517 DPRINTF("injected interrupt %d\n", irq);
5518 ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr);
5519 if (ret < 0) {
5520 fprintf(stderr,
5521 "KVM: injection failed, interrupt lost (%s)\n",
5522 strerror(-ret));
5523 }
5524 }
5525 }
5526
5527 /* If we have an interrupt but the guest is not ready to receive an
5528 * interrupt, request an interrupt window exit. This will
5529 * cause a return to userspace as soon as the guest is ready to
5530 * receive interrupts. */
5531 if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) {
5532 run->request_interrupt_window = 1;
5533 } else {
5534 run->request_interrupt_window = 0;
5535 }
5536
5537 DPRINTF("setting tpr\n");
5538 run->cr8 = cpu_get_apic_tpr(x86_cpu->apic_state);
5539
5540 bql_unlock();
5541 }
5542 }
5543
kvm_rate_limit_on_bus_lock(void)5544 static void kvm_rate_limit_on_bus_lock(void)
5545 {
5546 uint64_t delay_ns = ratelimit_calculate_delay(&bus_lock_ratelimit_ctrl, 1);
5547
5548 if (delay_ns) {
5549 g_usleep(delay_ns / SCALE_US);
5550 }
5551 }
5552
kvm_arch_post_run(CPUState * cpu,struct kvm_run * run)5553 MemTxAttrs kvm_arch_post_run(CPUState *cpu, struct kvm_run *run)
5554 {
5555 X86CPU *x86_cpu = X86_CPU(cpu);
5556 CPUX86State *env = &x86_cpu->env;
5557
5558 if (run->flags & KVM_RUN_X86_SMM) {
5559 env->hflags |= HF_SMM_MASK;
5560 } else {
5561 env->hflags &= ~HF_SMM_MASK;
5562 }
5563 if (run->if_flag) {
5564 env->eflags |= IF_MASK;
5565 } else {
5566 env->eflags &= ~IF_MASK;
5567 }
5568 if (run->flags & KVM_RUN_X86_BUS_LOCK) {
5569 kvm_rate_limit_on_bus_lock();
5570 }
5571
5572 #ifdef CONFIG_XEN_EMU
5573 /*
5574 * If the callback is asserted as a GSI (or PCI INTx) then check if
5575 * vcpu_info->evtchn_upcall_pending has been cleared, and deassert
5576 * the callback IRQ if so. Ideally we could hook into the PIC/IOAPIC
5577 * EOI and only resample then, exactly how the VFIO eventfd pairs
5578 * are designed to work for level triggered interrupts.
5579 */
5580 if (x86_cpu->env.xen_callback_asserted) {
5581 kvm_xen_maybe_deassert_callback(cpu);
5582 }
5583 #endif
5584
5585 /* We need to protect the apic state against concurrent accesses from
5586 * different threads in case the userspace irqchip is used. */
5587 if (!kvm_irqchip_in_kernel()) {
5588 bql_lock();
5589 }
5590 cpu_set_apic_tpr(x86_cpu->apic_state, run->cr8);
5591 cpu_set_apic_base(x86_cpu->apic_state, run->apic_base);
5592 if (!kvm_irqchip_in_kernel()) {
5593 bql_unlock();
5594 }
5595 return cpu_get_mem_attrs(env);
5596 }
5597
kvm_arch_process_async_events(CPUState * cs)5598 int kvm_arch_process_async_events(CPUState *cs)
5599 {
5600 X86CPU *cpu = X86_CPU(cs);
5601 CPUX86State *env = &cpu->env;
5602
5603 if (cs->interrupt_request & CPU_INTERRUPT_MCE) {
5604 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
5605 assert(env->mcg_cap);
5606
5607 cs->interrupt_request &= ~CPU_INTERRUPT_MCE;
5608
5609 kvm_cpu_synchronize_state(cs);
5610
5611 if (env->exception_nr == EXCP08_DBLE) {
5612 /* this means triple fault */
5613 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
5614 cs->exit_request = 1;
5615 return 0;
5616 }
5617 kvm_queue_exception(env, EXCP12_MCHK, 0, 0);
5618 env->has_error_code = 0;
5619
5620 cs->halted = 0;
5621 if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
5622 env->mp_state = KVM_MP_STATE_RUNNABLE;
5623 }
5624 }
5625
5626 if ((cs->interrupt_request & CPU_INTERRUPT_INIT) &&
5627 !(env->hflags & HF_SMM_MASK)) {
5628 kvm_cpu_synchronize_state(cs);
5629 do_cpu_init(cpu);
5630 }
5631
5632 if (kvm_irqchip_in_kernel()) {
5633 return 0;
5634 }
5635
5636 if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
5637 cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
5638 apic_poll_irq(cpu->apic_state);
5639 }
5640 if (((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
5641 (env->eflags & IF_MASK)) ||
5642 (cs->interrupt_request & CPU_INTERRUPT_NMI)) {
5643 cs->halted = 0;
5644 }
5645 if (cs->interrupt_request & CPU_INTERRUPT_SIPI) {
5646 kvm_cpu_synchronize_state(cs);
5647 do_cpu_sipi(cpu);
5648 }
5649 if (cs->interrupt_request & CPU_INTERRUPT_TPR) {
5650 cs->interrupt_request &= ~CPU_INTERRUPT_TPR;
5651 kvm_cpu_synchronize_state(cs);
5652 apic_handle_tpr_access_report(cpu->apic_state, env->eip,
5653 env->tpr_access_type);
5654 }
5655
5656 return cs->halted;
5657 }
5658
kvm_handle_halt(X86CPU * cpu)5659 static int kvm_handle_halt(X86CPU *cpu)
5660 {
5661 CPUState *cs = CPU(cpu);
5662 CPUX86State *env = &cpu->env;
5663
5664 if (!((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
5665 (env->eflags & IF_MASK)) &&
5666 !(cs->interrupt_request & CPU_INTERRUPT_NMI)) {
5667 cs->halted = 1;
5668 return EXCP_HLT;
5669 }
5670
5671 return 0;
5672 }
5673
kvm_handle_tpr_access(X86CPU * cpu)5674 static int kvm_handle_tpr_access(X86CPU *cpu)
5675 {
5676 CPUState *cs = CPU(cpu);
5677 struct kvm_run *run = cs->kvm_run;
5678
5679 apic_handle_tpr_access_report(cpu->apic_state, run->tpr_access.rip,
5680 run->tpr_access.is_write ? TPR_ACCESS_WRITE
5681 : TPR_ACCESS_READ);
5682 return 1;
5683 }
5684
kvm_arch_insert_sw_breakpoint(CPUState * cs,struct kvm_sw_breakpoint * bp)5685 int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
5686 {
5687 static const uint8_t int3 = 0xcc;
5688
5689 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
5690 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&int3, 1, 1)) {
5691 return -EINVAL;
5692 }
5693 return 0;
5694 }
5695
kvm_arch_remove_sw_breakpoint(CPUState * cs,struct kvm_sw_breakpoint * bp)5696 int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
5697 {
5698 uint8_t int3;
5699
5700 if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0)) {
5701 return -EINVAL;
5702 }
5703 if (int3 != 0xcc) {
5704 return 0;
5705 }
5706 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
5707 return -EINVAL;
5708 }
5709 return 0;
5710 }
5711
5712 static struct {
5713 target_ulong addr;
5714 int len;
5715 int type;
5716 } hw_breakpoint[4];
5717
5718 static int nb_hw_breakpoint;
5719
find_hw_breakpoint(target_ulong addr,int len,int type)5720 static int find_hw_breakpoint(target_ulong addr, int len, int type)
5721 {
5722 int n;
5723
5724 for (n = 0; n < nb_hw_breakpoint; n++) {
5725 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
5726 (hw_breakpoint[n].len == len || len == -1)) {
5727 return n;
5728 }
5729 }
5730 return -1;
5731 }
5732
kvm_arch_insert_hw_breakpoint(vaddr addr,vaddr len,int type)5733 int kvm_arch_insert_hw_breakpoint(vaddr addr, vaddr len, int type)
5734 {
5735 switch (type) {
5736 case GDB_BREAKPOINT_HW:
5737 len = 1;
5738 break;
5739 case GDB_WATCHPOINT_WRITE:
5740 case GDB_WATCHPOINT_ACCESS:
5741 switch (len) {
5742 case 1:
5743 break;
5744 case 2:
5745 case 4:
5746 case 8:
5747 if (addr & (len - 1)) {
5748 return -EINVAL;
5749 }
5750 break;
5751 default:
5752 return -EINVAL;
5753 }
5754 break;
5755 default:
5756 return -ENOSYS;
5757 }
5758
5759 if (nb_hw_breakpoint == 4) {
5760 return -ENOBUFS;
5761 }
5762 if (find_hw_breakpoint(addr, len, type) >= 0) {
5763 return -EEXIST;
5764 }
5765 hw_breakpoint[nb_hw_breakpoint].addr = addr;
5766 hw_breakpoint[nb_hw_breakpoint].len = len;
5767 hw_breakpoint[nb_hw_breakpoint].type = type;
5768 nb_hw_breakpoint++;
5769
5770 return 0;
5771 }
5772
kvm_arch_remove_hw_breakpoint(vaddr addr,vaddr len,int type)5773 int kvm_arch_remove_hw_breakpoint(vaddr addr, vaddr len, int type)
5774 {
5775 int n;
5776
5777 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
5778 if (n < 0) {
5779 return -ENOENT;
5780 }
5781 nb_hw_breakpoint--;
5782 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
5783
5784 return 0;
5785 }
5786
kvm_arch_remove_all_hw_breakpoints(void)5787 void kvm_arch_remove_all_hw_breakpoints(void)
5788 {
5789 nb_hw_breakpoint = 0;
5790 }
5791
5792 static CPUWatchpoint hw_watchpoint;
5793
kvm_handle_debug(X86CPU * cpu,struct kvm_debug_exit_arch * arch_info)5794 static int kvm_handle_debug(X86CPU *cpu,
5795 struct kvm_debug_exit_arch *arch_info)
5796 {
5797 CPUState *cs = CPU(cpu);
5798 CPUX86State *env = &cpu->env;
5799 int ret = 0;
5800 int n;
5801
5802 if (arch_info->exception == EXCP01_DB) {
5803 if (arch_info->dr6 & DR6_BS) {
5804 if (cs->singlestep_enabled) {
5805 ret = EXCP_DEBUG;
5806 }
5807 } else {
5808 for (n = 0; n < 4; n++) {
5809 if (arch_info->dr6 & (1 << n)) {
5810 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
5811 case 0x0:
5812 ret = EXCP_DEBUG;
5813 break;
5814 case 0x1:
5815 ret = EXCP_DEBUG;
5816 cs->watchpoint_hit = &hw_watchpoint;
5817 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
5818 hw_watchpoint.flags = BP_MEM_WRITE;
5819 break;
5820 case 0x3:
5821 ret = EXCP_DEBUG;
5822 cs->watchpoint_hit = &hw_watchpoint;
5823 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
5824 hw_watchpoint.flags = BP_MEM_ACCESS;
5825 break;
5826 }
5827 }
5828 }
5829 }
5830 } else if (kvm_find_sw_breakpoint(cs, arch_info->pc)) {
5831 ret = EXCP_DEBUG;
5832 }
5833 if (ret == 0) {
5834 cpu_synchronize_state(cs);
5835 assert(env->exception_nr == -1);
5836
5837 /* pass to guest */
5838 kvm_queue_exception(env, arch_info->exception,
5839 arch_info->exception == EXCP01_DB,
5840 arch_info->dr6);
5841 env->has_error_code = 0;
5842 }
5843
5844 return ret;
5845 }
5846
kvm_arch_update_guest_debug(CPUState * cpu,struct kvm_guest_debug * dbg)5847 void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg)
5848 {
5849 const uint8_t type_code[] = {
5850 [GDB_BREAKPOINT_HW] = 0x0,
5851 [GDB_WATCHPOINT_WRITE] = 0x1,
5852 [GDB_WATCHPOINT_ACCESS] = 0x3
5853 };
5854 const uint8_t len_code[] = {
5855 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
5856 };
5857 int n;
5858
5859 if (kvm_sw_breakpoints_active(cpu)) {
5860 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
5861 }
5862 if (nb_hw_breakpoint > 0) {
5863 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
5864 dbg->arch.debugreg[7] = 0x0600;
5865 for (n = 0; n < nb_hw_breakpoint; n++) {
5866 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
5867 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
5868 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
5869 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
5870 }
5871 }
5872 }
5873
kvm_install_msr_filters(KVMState * s)5874 static int kvm_install_msr_filters(KVMState *s)
5875 {
5876 uint64_t zero = 0;
5877 struct kvm_msr_filter filter = {
5878 .flags = KVM_MSR_FILTER_DEFAULT_ALLOW,
5879 };
5880 int i, j = 0;
5881
5882 QEMU_BUILD_BUG_ON(ARRAY_SIZE(msr_handlers) != ARRAY_SIZE(filter.ranges));
5883 for (i = 0; i < ARRAY_SIZE(msr_handlers); i++) {
5884 KVMMSRHandlers *handler = &msr_handlers[i];
5885 if (handler->msr) {
5886 struct kvm_msr_filter_range *range = &filter.ranges[j++];
5887
5888 *range = (struct kvm_msr_filter_range) {
5889 .flags = 0,
5890 .nmsrs = 1,
5891 .base = handler->msr,
5892 .bitmap = (__u8 *)&zero,
5893 };
5894
5895 if (handler->rdmsr) {
5896 range->flags |= KVM_MSR_FILTER_READ;
5897 }
5898
5899 if (handler->wrmsr) {
5900 range->flags |= KVM_MSR_FILTER_WRITE;
5901 }
5902 }
5903 }
5904
5905 return kvm_vm_ioctl(s, KVM_X86_SET_MSR_FILTER, &filter);
5906 }
5907
kvm_filter_msr(KVMState * s,uint32_t msr,QEMURDMSRHandler * rdmsr,QEMUWRMSRHandler * wrmsr)5908 static int kvm_filter_msr(KVMState *s, uint32_t msr, QEMURDMSRHandler *rdmsr,
5909 QEMUWRMSRHandler *wrmsr)
5910 {
5911 int i, ret;
5912
5913 for (i = 0; i < ARRAY_SIZE(msr_handlers); i++) {
5914 if (!msr_handlers[i].msr) {
5915 msr_handlers[i] = (KVMMSRHandlers) {
5916 .msr = msr,
5917 .rdmsr = rdmsr,
5918 .wrmsr = wrmsr,
5919 };
5920
5921 ret = kvm_install_msr_filters(s);
5922 if (ret) {
5923 msr_handlers[i] = (KVMMSRHandlers) { };
5924 return ret;
5925 }
5926
5927 return 0;
5928 }
5929 }
5930
5931 return -EINVAL;
5932 }
5933
kvm_handle_rdmsr(X86CPU * cpu,struct kvm_run * run)5934 static int kvm_handle_rdmsr(X86CPU *cpu, struct kvm_run *run)
5935 {
5936 int i;
5937 bool r;
5938
5939 for (i = 0; i < ARRAY_SIZE(msr_handlers); i++) {
5940 KVMMSRHandlers *handler = &msr_handlers[i];
5941 if (run->msr.index == handler->msr) {
5942 if (handler->rdmsr) {
5943 r = handler->rdmsr(cpu, handler->msr,
5944 (uint64_t *)&run->msr.data);
5945 run->msr.error = r ? 0 : 1;
5946 return 0;
5947 }
5948 }
5949 }
5950
5951 g_assert_not_reached();
5952 }
5953
kvm_handle_wrmsr(X86CPU * cpu,struct kvm_run * run)5954 static int kvm_handle_wrmsr(X86CPU *cpu, struct kvm_run *run)
5955 {
5956 int i;
5957 bool r;
5958
5959 for (i = 0; i < ARRAY_SIZE(msr_handlers); i++) {
5960 KVMMSRHandlers *handler = &msr_handlers[i];
5961 if (run->msr.index == handler->msr) {
5962 if (handler->wrmsr) {
5963 r = handler->wrmsr(cpu, handler->msr, run->msr.data);
5964 run->msr.error = r ? 0 : 1;
5965 return 0;
5966 }
5967 }
5968 }
5969
5970 g_assert_not_reached();
5971 }
5972
5973 static bool has_sgx_provisioning;
5974
__kvm_enable_sgx_provisioning(KVMState * s)5975 static bool __kvm_enable_sgx_provisioning(KVMState *s)
5976 {
5977 int fd, ret;
5978
5979 if (!kvm_vm_check_extension(s, KVM_CAP_SGX_ATTRIBUTE)) {
5980 return false;
5981 }
5982
5983 fd = qemu_open_old("/dev/sgx_provision", O_RDONLY);
5984 if (fd < 0) {
5985 return false;
5986 }
5987
5988 ret = kvm_vm_enable_cap(s, KVM_CAP_SGX_ATTRIBUTE, 0, fd);
5989 if (ret) {
5990 error_report("Could not enable SGX PROVISIONKEY: %s", strerror(-ret));
5991 exit(1);
5992 }
5993 close(fd);
5994 return true;
5995 }
5996
kvm_enable_sgx_provisioning(KVMState * s)5997 bool kvm_enable_sgx_provisioning(KVMState *s)
5998 {
5999 return MEMORIZE(__kvm_enable_sgx_provisioning(s), has_sgx_provisioning);
6000 }
6001
host_supports_vmx(void)6002 static bool host_supports_vmx(void)
6003 {
6004 uint32_t ecx, unused;
6005
6006 host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
6007 return ecx & CPUID_EXT_VMX;
6008 }
6009
6010 /*
6011 * Currently the handling here only supports use of KVM_HC_MAP_GPA_RANGE
6012 * to service guest-initiated memory attribute update requests so that
6013 * KVM_SET_MEMORY_ATTRIBUTES can update whether or not a page should be
6014 * backed by the private memory pool provided by guest_memfd, and as such
6015 * is only applicable to guest_memfd-backed guests (e.g. SNP/TDX).
6016 *
6017 * Other other use-cases for KVM_HC_MAP_GPA_RANGE, such as for SEV live
6018 * migration, are not implemented here currently.
6019 *
6020 * For the guest_memfd use-case, these exits will generally be synthesized
6021 * by KVM based on platform-specific hypercalls, like GHCB requests in the
6022 * case of SEV-SNP, and not issued directly within the guest though the
6023 * KVM_HC_MAP_GPA_RANGE hypercall. So in this case, KVM_HC_MAP_GPA_RANGE is
6024 * not actually advertised to guests via the KVM CPUID feature bit, as
6025 * opposed to SEV live migration where it would be. Since it is unlikely the
6026 * SEV live migration use-case would be useful for guest-memfd backed guests,
6027 * because private/shared page tracking is already provided through other
6028 * means, these 2 use-cases should be treated as being mutually-exclusive.
6029 */
kvm_handle_hc_map_gpa_range(X86CPU * cpu,struct kvm_run * run)6030 static int kvm_handle_hc_map_gpa_range(X86CPU *cpu, struct kvm_run *run)
6031 {
6032 struct kvm_pre_fault_memory mem;
6033 uint64_t gpa, size, attributes;
6034 int ret;
6035
6036 if (!machine_require_guest_memfd(current_machine))
6037 return -EINVAL;
6038
6039 gpa = run->hypercall.args[0];
6040 size = run->hypercall.args[1] * TARGET_PAGE_SIZE;
6041 attributes = run->hypercall.args[2];
6042
6043 trace_kvm_hc_map_gpa_range(gpa, size, attributes, run->hypercall.flags);
6044
6045 ret = kvm_convert_memory(gpa, size, attributes & KVM_MAP_GPA_RANGE_ENCRYPTED);
6046 if (ret || !kvm_pre_fault_memory_supported) {
6047 return ret;
6048 }
6049
6050 /*
6051 * Opportunistically pre-fault memory in. Failures are ignored so that any
6052 * errors in faulting in the memory will get captured in KVM page fault
6053 * path when the guest first accesses the page.
6054 */
6055 memset(&mem, 0, sizeof(mem));
6056 mem.gpa = gpa;
6057 mem.size = size;
6058 while (mem.size) {
6059 if (kvm_vcpu_ioctl(CPU(cpu), KVM_PRE_FAULT_MEMORY, &mem)) {
6060 break;
6061 }
6062 }
6063
6064 return 0;
6065 }
6066
kvm_handle_hypercall(X86CPU * cpu,struct kvm_run * run)6067 static int kvm_handle_hypercall(X86CPU *cpu, struct kvm_run *run)
6068 {
6069 if (run->hypercall.nr == KVM_HC_MAP_GPA_RANGE)
6070 return kvm_handle_hc_map_gpa_range(cpu, run);
6071
6072 return -EINVAL;
6073 }
6074
6075 #define VMX_INVALID_GUEST_STATE 0x80000021
6076
kvm_arch_handle_exit(CPUState * cs,struct kvm_run * run)6077 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
6078 {
6079 X86CPU *cpu = X86_CPU(cs);
6080 uint64_t code;
6081 int ret;
6082 bool ctx_invalid;
6083 KVMState *state;
6084
6085 switch (run->exit_reason) {
6086 case KVM_EXIT_HLT:
6087 DPRINTF("handle_hlt\n");
6088 bql_lock();
6089 ret = kvm_handle_halt(cpu);
6090 bql_unlock();
6091 break;
6092 case KVM_EXIT_SET_TPR:
6093 ret = 0;
6094 break;
6095 case KVM_EXIT_TPR_ACCESS:
6096 bql_lock();
6097 ret = kvm_handle_tpr_access(cpu);
6098 bql_unlock();
6099 break;
6100 case KVM_EXIT_FAIL_ENTRY:
6101 code = run->fail_entry.hardware_entry_failure_reason;
6102 fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
6103 code);
6104 if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
6105 fprintf(stderr,
6106 "\nIf you're running a guest on an Intel machine without "
6107 "unrestricted mode\n"
6108 "support, the failure can be most likely due to the guest "
6109 "entering an invalid\n"
6110 "state for Intel VT. For example, the guest maybe running "
6111 "in big real mode\n"
6112 "which is not supported on less recent Intel processors."
6113 "\n\n");
6114 }
6115 ret = -1;
6116 break;
6117 case KVM_EXIT_EXCEPTION:
6118 fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
6119 run->ex.exception, run->ex.error_code);
6120 ret = -1;
6121 break;
6122 case KVM_EXIT_DEBUG:
6123 DPRINTF("kvm_exit_debug\n");
6124 bql_lock();
6125 ret = kvm_handle_debug(cpu, &run->debug.arch);
6126 bql_unlock();
6127 break;
6128 case KVM_EXIT_HYPERV:
6129 ret = kvm_hv_handle_exit(cpu, &run->hyperv);
6130 break;
6131 case KVM_EXIT_IOAPIC_EOI:
6132 ioapic_eoi_broadcast(run->eoi.vector);
6133 ret = 0;
6134 break;
6135 case KVM_EXIT_X86_BUS_LOCK:
6136 /* already handled in kvm_arch_post_run */
6137 ret = 0;
6138 break;
6139 case KVM_EXIT_NOTIFY:
6140 ctx_invalid = !!(run->notify.flags & KVM_NOTIFY_CONTEXT_INVALID);
6141 state = KVM_STATE(current_accel());
6142 if (ctx_invalid ||
6143 state->notify_vmexit == NOTIFY_VMEXIT_OPTION_INTERNAL_ERROR) {
6144 warn_report("KVM internal error: Encountered a notify exit "
6145 "with invalid context in guest.");
6146 ret = -1;
6147 } else {
6148 warn_report_once("KVM: Encountered a notify exit with valid "
6149 "context in guest. "
6150 "The guest could be misbehaving.");
6151 ret = 0;
6152 }
6153 break;
6154 case KVM_EXIT_X86_RDMSR:
6155 /* We only enable MSR filtering, any other exit is bogus */
6156 assert(run->msr.reason == KVM_MSR_EXIT_REASON_FILTER);
6157 ret = kvm_handle_rdmsr(cpu, run);
6158 break;
6159 case KVM_EXIT_X86_WRMSR:
6160 /* We only enable MSR filtering, any other exit is bogus */
6161 assert(run->msr.reason == KVM_MSR_EXIT_REASON_FILTER);
6162 ret = kvm_handle_wrmsr(cpu, run);
6163 break;
6164 #ifdef CONFIG_XEN_EMU
6165 case KVM_EXIT_XEN:
6166 ret = kvm_xen_handle_exit(cpu, &run->xen);
6167 break;
6168 #endif
6169 case KVM_EXIT_HYPERCALL:
6170 ret = kvm_handle_hypercall(cpu, run);
6171 break;
6172 case KVM_EXIT_SYSTEM_EVENT:
6173 switch (run->system_event.type) {
6174 case KVM_SYSTEM_EVENT_TDX_FATAL:
6175 ret = tdx_handle_report_fatal_error(cpu, run);
6176 break;
6177 default:
6178 ret = -1;
6179 break;
6180 }
6181 break;
6182 case KVM_EXIT_TDX:
6183 /*
6184 * run->tdx is already set up for the case where userspace
6185 * does not handle the TDVMCALL.
6186 */
6187 switch (run->tdx.nr) {
6188 case TDVMCALL_GET_QUOTE:
6189 tdx_handle_get_quote(cpu, run);
6190 break;
6191 case TDVMCALL_GET_TD_VM_CALL_INFO:
6192 tdx_handle_get_tdvmcall_info(cpu, run);
6193 break;
6194 case TDVMCALL_SETUP_EVENT_NOTIFY_INTERRUPT:
6195 tdx_handle_setup_event_notify_interrupt(cpu, run);
6196 break;
6197 }
6198 ret = 0;
6199 break;
6200 default:
6201 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
6202 ret = -1;
6203 break;
6204 }
6205
6206 return ret;
6207 }
6208
kvm_arch_stop_on_emulation_error(CPUState * cs)6209 bool kvm_arch_stop_on_emulation_error(CPUState *cs)
6210 {
6211 X86CPU *cpu = X86_CPU(cs);
6212 CPUX86State *env = &cpu->env;
6213
6214 kvm_cpu_synchronize_state(cs);
6215 return !(env->cr[0] & CR0_PE_MASK) ||
6216 ((env->segs[R_CS].selector & 3) != 3);
6217 }
6218
kvm_arch_init_irq_routing(KVMState * s)6219 void kvm_arch_init_irq_routing(KVMState *s)
6220 {
6221 /* We know at this point that we're using the in-kernel
6222 * irqchip, so we can use irqfds, and on x86 we know
6223 * we can use msi via irqfd and GSI routing.
6224 */
6225 kvm_msi_via_irqfd_allowed = true;
6226 kvm_gsi_routing_allowed = true;
6227
6228 if (kvm_irqchip_is_split()) {
6229 KVMRouteChange c = kvm_irqchip_begin_route_changes(s);
6230 int i;
6231
6232 /* If the ioapic is in QEMU and the lapics are in KVM, reserve
6233 MSI routes for signaling interrupts to the local apics. */
6234 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
6235 if (kvm_irqchip_add_msi_route(&c, 0, NULL) < 0) {
6236 error_report("Could not enable split IRQ mode.");
6237 exit(1);
6238 }
6239 }
6240 kvm_irqchip_commit_route_changes(&c);
6241 }
6242 }
6243
kvm_arch_irqchip_create(KVMState * s)6244 int kvm_arch_irqchip_create(KVMState *s)
6245 {
6246 int ret;
6247 if (kvm_kernel_irqchip_split()) {
6248 ret = kvm_vm_enable_cap(s, KVM_CAP_SPLIT_IRQCHIP, 0, 24);
6249 if (ret) {
6250 error_report("Could not enable split irqchip mode: %s",
6251 strerror(-ret));
6252 exit(1);
6253 } else {
6254 DPRINTF("Enabled KVM_CAP_SPLIT_IRQCHIP\n");
6255 kvm_split_irqchip = true;
6256 return 1;
6257 }
6258 } else {
6259 return 0;
6260 }
6261 }
6262
kvm_swizzle_msi_ext_dest_id(uint64_t address)6263 uint64_t kvm_swizzle_msi_ext_dest_id(uint64_t address)
6264 {
6265 CPUX86State *env;
6266 uint64_t ext_id;
6267
6268 if (!first_cpu) {
6269 return address;
6270 }
6271 env = &X86_CPU(first_cpu)->env;
6272 if (!(env->features[FEAT_KVM] & CPUID_KVM_MSI_EXT_DEST_ID)) {
6273 return address;
6274 }
6275
6276 /*
6277 * If the remappable format bit is set, or the upper bits are
6278 * already set in address_hi, or the low extended bits aren't
6279 * there anyway, do nothing.
6280 */
6281 ext_id = address & (0xff << MSI_ADDR_DEST_IDX_SHIFT);
6282 if (!ext_id || (ext_id & (1 << MSI_ADDR_DEST_IDX_SHIFT)) || (address >> 32)) {
6283 return address;
6284 }
6285
6286 address &= ~ext_id;
6287 address |= ext_id << 35;
6288 return address;
6289 }
6290
kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry * route,uint64_t address,uint32_t data,PCIDevice * dev)6291 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
6292 uint64_t address, uint32_t data, PCIDevice *dev)
6293 {
6294 X86IOMMUState *iommu = x86_iommu_get_default();
6295
6296 if (iommu) {
6297 X86IOMMUClass *class = X86_IOMMU_DEVICE_GET_CLASS(iommu);
6298
6299 if (class->int_remap) {
6300 int ret;
6301 MSIMessage src, dst;
6302
6303 src.address = route->u.msi.address_hi;
6304 src.address <<= VTD_MSI_ADDR_HI_SHIFT;
6305 src.address |= route->u.msi.address_lo;
6306 src.data = route->u.msi.data;
6307
6308 ret = class->int_remap(iommu, &src, &dst, dev ? \
6309 pci_requester_id(dev) : \
6310 X86_IOMMU_SID_INVALID);
6311 if (ret) {
6312 trace_kvm_x86_fixup_msi_error(route->gsi);
6313 return 1;
6314 }
6315
6316 /*
6317 * Handled untranslated compatibility format interrupt with
6318 * extended destination ID in the low bits 11-5. */
6319 dst.address = kvm_swizzle_msi_ext_dest_id(dst.address);
6320
6321 route->u.msi.address_hi = dst.address >> VTD_MSI_ADDR_HI_SHIFT;
6322 route->u.msi.address_lo = dst.address & VTD_MSI_ADDR_LO_MASK;
6323 route->u.msi.data = dst.data;
6324 return 0;
6325 }
6326 }
6327
6328 #ifdef CONFIG_XEN_EMU
6329 if (xen_mode == XEN_EMULATE) {
6330 int handled = xen_evtchn_translate_pirq_msi(route, address, data);
6331
6332 /*
6333 * If it was a PIRQ and successfully routed (handled == 0) or it was
6334 * an error (handled < 0), return. If it wasn't a PIRQ, keep going.
6335 */
6336 if (handled <= 0) {
6337 return handled;
6338 }
6339 }
6340 #endif
6341
6342 address = kvm_swizzle_msi_ext_dest_id(address);
6343 route->u.msi.address_hi = address >> VTD_MSI_ADDR_HI_SHIFT;
6344 route->u.msi.address_lo = address & VTD_MSI_ADDR_LO_MASK;
6345 return 0;
6346 }
6347
6348 typedef struct MSIRouteEntry MSIRouteEntry;
6349
6350 struct MSIRouteEntry {
6351 PCIDevice *dev; /* Device pointer */
6352 int vector; /* MSI/MSIX vector index */
6353 int virq; /* Virtual IRQ index */
6354 QLIST_ENTRY(MSIRouteEntry) list;
6355 };
6356
6357 /* List of used GSI routes */
6358 static QLIST_HEAD(, MSIRouteEntry) msi_route_list = \
6359 QLIST_HEAD_INITIALIZER(msi_route_list);
6360
kvm_update_msi_routes_all(void * private,bool global,uint32_t index,uint32_t mask)6361 void kvm_update_msi_routes_all(void *private, bool global,
6362 uint32_t index, uint32_t mask)
6363 {
6364 int cnt = 0, vector;
6365 MSIRouteEntry *entry;
6366 MSIMessage msg;
6367 PCIDevice *dev;
6368
6369 /* TODO: explicit route update */
6370 QLIST_FOREACH(entry, &msi_route_list, list) {
6371 cnt++;
6372 vector = entry->vector;
6373 dev = entry->dev;
6374 if (msix_enabled(dev) && !msix_is_masked(dev, vector)) {
6375 msg = msix_get_message(dev, vector);
6376 } else if (msi_enabled(dev) && !msi_is_masked(dev, vector)) {
6377 msg = msi_get_message(dev, vector);
6378 } else {
6379 /*
6380 * Either MSI/MSIX is disabled for the device, or the
6381 * specific message was masked out. Skip this one.
6382 */
6383 continue;
6384 }
6385 kvm_irqchip_update_msi_route(kvm_state, entry->virq, msg, dev);
6386 }
6387 kvm_irqchip_commit_routes(kvm_state);
6388 trace_kvm_x86_update_msi_routes(cnt);
6389 }
6390
kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry * route,int vector,PCIDevice * dev)6391 int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route,
6392 int vector, PCIDevice *dev)
6393 {
6394 static bool notify_list_inited = false;
6395 MSIRouteEntry *entry;
6396
6397 if (!dev) {
6398 /* These are (possibly) IOAPIC routes only used for split
6399 * kernel irqchip mode, while what we are housekeeping are
6400 * PCI devices only. */
6401 return 0;
6402 }
6403
6404 entry = g_new0(MSIRouteEntry, 1);
6405 entry->dev = dev;
6406 entry->vector = vector;
6407 entry->virq = route->gsi;
6408 QLIST_INSERT_HEAD(&msi_route_list, entry, list);
6409
6410 trace_kvm_x86_add_msi_route(route->gsi);
6411
6412 if (!notify_list_inited) {
6413 /* For the first time we do add route, add ourselves into
6414 * IOMMU's IEC notify list if needed. */
6415 X86IOMMUState *iommu = x86_iommu_get_default();
6416 if (iommu) {
6417 x86_iommu_iec_register_notifier(iommu,
6418 kvm_update_msi_routes_all,
6419 NULL);
6420 }
6421 notify_list_inited = true;
6422 }
6423 return 0;
6424 }
6425
kvm_arch_release_virq_post(int virq)6426 int kvm_arch_release_virq_post(int virq)
6427 {
6428 MSIRouteEntry *entry, *next;
6429 QLIST_FOREACH_SAFE(entry, &msi_route_list, list, next) {
6430 if (entry->virq == virq) {
6431 trace_kvm_x86_remove_msi_route(virq);
6432 QLIST_REMOVE(entry, list);
6433 g_free(entry);
6434 break;
6435 }
6436 }
6437 return 0;
6438 }
6439
kvm_arch_msi_data_to_gsi(uint32_t data)6440 int kvm_arch_msi_data_to_gsi(uint32_t data)
6441 {
6442 abort();
6443 }
6444
kvm_has_waitpkg(void)6445 bool kvm_has_waitpkg(void)
6446 {
6447 return has_msr_umwait;
6448 }
6449
6450 #define ARCH_REQ_XCOMP_GUEST_PERM 0x1025
6451
kvm_request_xsave_components(X86CPU * cpu,uint64_t mask)6452 void kvm_request_xsave_components(X86CPU *cpu, uint64_t mask)
6453 {
6454 KVMState *s = kvm_state;
6455 uint64_t supported;
6456
6457 mask &= XSTATE_DYNAMIC_MASK;
6458 if (!mask) {
6459 return;
6460 }
6461 /*
6462 * Just ignore bits that are not in CPUID[EAX=0xD,ECX=0].
6463 * ARCH_REQ_XCOMP_GUEST_PERM would fail, and QEMU has warned
6464 * about them already because they are not supported features.
6465 */
6466 supported = kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EAX);
6467 supported |= (uint64_t)kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EDX) << 32;
6468 mask &= supported;
6469
6470 while (mask) {
6471 int bit = ctz64(mask);
6472 int rc = syscall(SYS_arch_prctl, ARCH_REQ_XCOMP_GUEST_PERM, bit);
6473 if (rc) {
6474 /*
6475 * Older kernel version (<5.17) do not support
6476 * ARCH_REQ_XCOMP_GUEST_PERM, but also do not return
6477 * any dynamic feature from kvm_arch_get_supported_cpuid.
6478 */
6479 warn_report("prctl(ARCH_REQ_XCOMP_GUEST_PERM) failure "
6480 "for feature bit %d", bit);
6481 }
6482 mask &= ~BIT_ULL(bit);
6483 }
6484 }
6485
kvm_arch_get_notify_vmexit(Object * obj,Error ** errp)6486 static int kvm_arch_get_notify_vmexit(Object *obj, Error **errp)
6487 {
6488 KVMState *s = KVM_STATE(obj);
6489 return s->notify_vmexit;
6490 }
6491
kvm_arch_set_notify_vmexit(Object * obj,int value,Error ** errp)6492 static void kvm_arch_set_notify_vmexit(Object *obj, int value, Error **errp)
6493 {
6494 KVMState *s = KVM_STATE(obj);
6495
6496 if (s->fd != -1) {
6497 error_setg(errp, "Cannot set properties after the accelerator has been initialized");
6498 return;
6499 }
6500
6501 s->notify_vmexit = value;
6502 }
6503
kvm_arch_get_notify_window(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)6504 static void kvm_arch_get_notify_window(Object *obj, Visitor *v,
6505 const char *name, void *opaque,
6506 Error **errp)
6507 {
6508 KVMState *s = KVM_STATE(obj);
6509 uint32_t value = s->notify_window;
6510
6511 visit_type_uint32(v, name, &value, errp);
6512 }
6513
kvm_arch_set_notify_window(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)6514 static void kvm_arch_set_notify_window(Object *obj, Visitor *v,
6515 const char *name, void *opaque,
6516 Error **errp)
6517 {
6518 KVMState *s = KVM_STATE(obj);
6519 uint32_t value;
6520
6521 if (s->fd != -1) {
6522 error_setg(errp, "Cannot set properties after the accelerator has been initialized");
6523 return;
6524 }
6525
6526 if (!visit_type_uint32(v, name, &value, errp)) {
6527 return;
6528 }
6529
6530 s->notify_window = value;
6531 }
6532
kvm_arch_get_xen_version(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)6533 static void kvm_arch_get_xen_version(Object *obj, Visitor *v,
6534 const char *name, void *opaque,
6535 Error **errp)
6536 {
6537 KVMState *s = KVM_STATE(obj);
6538 uint32_t value = s->xen_version;
6539
6540 visit_type_uint32(v, name, &value, errp);
6541 }
6542
kvm_arch_set_xen_version(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)6543 static void kvm_arch_set_xen_version(Object *obj, Visitor *v,
6544 const char *name, void *opaque,
6545 Error **errp)
6546 {
6547 KVMState *s = KVM_STATE(obj);
6548 Error *error = NULL;
6549 uint32_t value;
6550
6551 visit_type_uint32(v, name, &value, &error);
6552 if (error) {
6553 error_propagate(errp, error);
6554 return;
6555 }
6556
6557 s->xen_version = value;
6558 if (value && xen_mode == XEN_DISABLED) {
6559 xen_mode = XEN_EMULATE;
6560 }
6561 }
6562
kvm_arch_get_xen_gnttab_max_frames(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)6563 static void kvm_arch_get_xen_gnttab_max_frames(Object *obj, Visitor *v,
6564 const char *name, void *opaque,
6565 Error **errp)
6566 {
6567 KVMState *s = KVM_STATE(obj);
6568 uint16_t value = s->xen_gnttab_max_frames;
6569
6570 visit_type_uint16(v, name, &value, errp);
6571 }
6572
kvm_arch_set_xen_gnttab_max_frames(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)6573 static void kvm_arch_set_xen_gnttab_max_frames(Object *obj, Visitor *v,
6574 const char *name, void *opaque,
6575 Error **errp)
6576 {
6577 KVMState *s = KVM_STATE(obj);
6578 Error *error = NULL;
6579 uint16_t value;
6580
6581 visit_type_uint16(v, name, &value, &error);
6582 if (error) {
6583 error_propagate(errp, error);
6584 return;
6585 }
6586
6587 s->xen_gnttab_max_frames = value;
6588 }
6589
kvm_arch_get_xen_evtchn_max_pirq(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)6590 static void kvm_arch_get_xen_evtchn_max_pirq(Object *obj, Visitor *v,
6591 const char *name, void *opaque,
6592 Error **errp)
6593 {
6594 KVMState *s = KVM_STATE(obj);
6595 uint16_t value = s->xen_evtchn_max_pirq;
6596
6597 visit_type_uint16(v, name, &value, errp);
6598 }
6599
kvm_arch_set_xen_evtchn_max_pirq(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)6600 static void kvm_arch_set_xen_evtchn_max_pirq(Object *obj, Visitor *v,
6601 const char *name, void *opaque,
6602 Error **errp)
6603 {
6604 KVMState *s = KVM_STATE(obj);
6605 Error *error = NULL;
6606 uint16_t value;
6607
6608 visit_type_uint16(v, name, &value, &error);
6609 if (error) {
6610 error_propagate(errp, error);
6611 return;
6612 }
6613
6614 s->xen_evtchn_max_pirq = value;
6615 }
6616
kvm_arch_accel_class_init(ObjectClass * oc)6617 void kvm_arch_accel_class_init(ObjectClass *oc)
6618 {
6619 object_class_property_add_enum(oc, "notify-vmexit", "NotifyVMexitOption",
6620 &NotifyVmexitOption_lookup,
6621 kvm_arch_get_notify_vmexit,
6622 kvm_arch_set_notify_vmexit);
6623 object_class_property_set_description(oc, "notify-vmexit",
6624 "Enable notify VM exit");
6625
6626 object_class_property_add(oc, "notify-window", "uint32",
6627 kvm_arch_get_notify_window,
6628 kvm_arch_set_notify_window,
6629 NULL, NULL);
6630 object_class_property_set_description(oc, "notify-window",
6631 "Clock cycles without an event window "
6632 "after which a notification VM exit occurs");
6633
6634 object_class_property_add(oc, "xen-version", "uint32",
6635 kvm_arch_get_xen_version,
6636 kvm_arch_set_xen_version,
6637 NULL, NULL);
6638 object_class_property_set_description(oc, "xen-version",
6639 "Xen version to be emulated "
6640 "(in XENVER_version form "
6641 "e.g. 0x4000a for 4.10)");
6642
6643 object_class_property_add(oc, "xen-gnttab-max-frames", "uint16",
6644 kvm_arch_get_xen_gnttab_max_frames,
6645 kvm_arch_set_xen_gnttab_max_frames,
6646 NULL, NULL);
6647 object_class_property_set_description(oc, "xen-gnttab-max-frames",
6648 "Maximum number of grant table frames");
6649
6650 object_class_property_add(oc, "xen-evtchn-max-pirq", "uint16",
6651 kvm_arch_get_xen_evtchn_max_pirq,
6652 kvm_arch_set_xen_evtchn_max_pirq,
6653 NULL, NULL);
6654 object_class_property_set_description(oc, "xen-evtchn-max-pirq",
6655 "Maximum number of Xen PIRQs");
6656 }
6657
kvm_set_max_apic_id(uint32_t max_apic_id)6658 void kvm_set_max_apic_id(uint32_t max_apic_id)
6659 {
6660 kvm_vm_enable_cap(kvm_state, KVM_CAP_MAX_VCPU_ID, 0, max_apic_id);
6661 }
6662