1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * VMX control MSR test
4  *
5  * Copyright (C) 2022 Google LLC.
6  *
7  * Tests for KVM ownership of bits in the VMX entry/exit control MSRs. Checks
8  * that KVM will set owned bits where appropriate, and will not if
9  * KVM_X86_QUIRK_TWEAK_VMX_CTRL_MSRS is disabled.
10  */
11 #include <linux/bitmap.h>
12 #include "kvm_util.h"
13 #include "vmx.h"
14 
vmx_fixed1_msr_test(struct kvm_vcpu * vcpu,uint32_t msr_index,uint64_t mask)15 static void vmx_fixed1_msr_test(struct kvm_vcpu *vcpu, uint32_t msr_index,
16 				  uint64_t mask)
17 {
18 	uint64_t val = vcpu_get_msr(vcpu, msr_index);
19 	uint64_t bit;
20 
21 	mask &= val;
22 
23 	for_each_set_bit(bit, &mask, 64) {
24 		vcpu_set_msr(vcpu, msr_index, val & ~BIT_ULL(bit));
25 		vcpu_set_msr(vcpu, msr_index, val);
26 	}
27 }
28 
vmx_fixed0_msr_test(struct kvm_vcpu * vcpu,uint32_t msr_index,uint64_t mask)29 static void vmx_fixed0_msr_test(struct kvm_vcpu *vcpu, uint32_t msr_index,
30 				uint64_t mask)
31 {
32 	uint64_t val = vcpu_get_msr(vcpu, msr_index);
33 	uint64_t bit;
34 
35 	mask = ~mask | val;
36 
37 	for_each_clear_bit(bit, &mask, 64) {
38 		vcpu_set_msr(vcpu, msr_index, val | BIT_ULL(bit));
39 		vcpu_set_msr(vcpu, msr_index, val);
40 	}
41 }
42 
vmx_fixed0and1_msr_test(struct kvm_vcpu * vcpu,uint32_t msr_index)43 static void vmx_fixed0and1_msr_test(struct kvm_vcpu *vcpu, uint32_t msr_index)
44 {
45 	vmx_fixed0_msr_test(vcpu, msr_index, GENMASK_ULL(31, 0));
46 	vmx_fixed1_msr_test(vcpu, msr_index, GENMASK_ULL(63, 32));
47 }
48 
vmx_save_restore_msrs_test(struct kvm_vcpu * vcpu)49 static void vmx_save_restore_msrs_test(struct kvm_vcpu *vcpu)
50 {
51 	vcpu_set_msr(vcpu, MSR_IA32_VMX_VMCS_ENUM, 0);
52 	vcpu_set_msr(vcpu, MSR_IA32_VMX_VMCS_ENUM, -1ull);
53 
54 	vmx_fixed1_msr_test(vcpu, MSR_IA32_VMX_BASIC,
55 			    BIT_ULL(49) | BIT_ULL(54) | BIT_ULL(55));
56 
57 	vmx_fixed1_msr_test(vcpu, MSR_IA32_VMX_MISC,
58 			    BIT_ULL(5) | GENMASK_ULL(8, 6) | BIT_ULL(14) |
59 			    BIT_ULL(15) | BIT_ULL(28) | BIT_ULL(29) | BIT_ULL(30));
60 
61 	vmx_fixed0and1_msr_test(vcpu, MSR_IA32_VMX_PROCBASED_CTLS2);
62 	vmx_fixed1_msr_test(vcpu, MSR_IA32_VMX_EPT_VPID_CAP, -1ull);
63 	vmx_fixed0and1_msr_test(vcpu, MSR_IA32_VMX_TRUE_PINBASED_CTLS);
64 	vmx_fixed0and1_msr_test(vcpu, MSR_IA32_VMX_TRUE_PROCBASED_CTLS);
65 	vmx_fixed0and1_msr_test(vcpu, MSR_IA32_VMX_TRUE_EXIT_CTLS);
66 	vmx_fixed0and1_msr_test(vcpu, MSR_IA32_VMX_TRUE_ENTRY_CTLS);
67 	vmx_fixed1_msr_test(vcpu, MSR_IA32_VMX_VMFUNC, -1ull);
68 }
69 
__ia32_feature_control_msr_test(struct kvm_vcpu * vcpu,uint64_t msr_bit,struct kvm_x86_cpu_feature feature)70 static void __ia32_feature_control_msr_test(struct kvm_vcpu *vcpu,
71 					    uint64_t msr_bit,
72 					    struct kvm_x86_cpu_feature feature)
73 {
74 	uint64_t val;
75 
76 	vcpu_clear_cpuid_feature(vcpu, feature);
77 
78 	val = vcpu_get_msr(vcpu, MSR_IA32_FEAT_CTL);
79 	vcpu_set_msr(vcpu, MSR_IA32_FEAT_CTL, val | msr_bit | FEAT_CTL_LOCKED);
80 	vcpu_set_msr(vcpu, MSR_IA32_FEAT_CTL, (val & ~msr_bit) | FEAT_CTL_LOCKED);
81 	vcpu_set_msr(vcpu, MSR_IA32_FEAT_CTL, val | msr_bit | FEAT_CTL_LOCKED);
82 	vcpu_set_msr(vcpu, MSR_IA32_FEAT_CTL, (val & ~msr_bit) | FEAT_CTL_LOCKED);
83 	vcpu_set_msr(vcpu, MSR_IA32_FEAT_CTL, val);
84 
85 	if (!kvm_cpu_has(feature))
86 		return;
87 
88 	vcpu_set_cpuid_feature(vcpu, feature);
89 }
90 
ia32_feature_control_msr_test(struct kvm_vcpu * vcpu)91 static void ia32_feature_control_msr_test(struct kvm_vcpu *vcpu)
92 {
93 	uint64_t supported_bits = FEAT_CTL_LOCKED |
94 				  FEAT_CTL_VMX_ENABLED_INSIDE_SMX |
95 				  FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX |
96 				  FEAT_CTL_SGX_LC_ENABLED |
97 				  FEAT_CTL_SGX_ENABLED |
98 				  FEAT_CTL_LMCE_ENABLED;
99 	int bit, r;
100 
101 	__ia32_feature_control_msr_test(vcpu, FEAT_CTL_VMX_ENABLED_INSIDE_SMX, X86_FEATURE_SMX);
102 	__ia32_feature_control_msr_test(vcpu, FEAT_CTL_VMX_ENABLED_INSIDE_SMX, X86_FEATURE_VMX);
103 	__ia32_feature_control_msr_test(vcpu, FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX, X86_FEATURE_VMX);
104 	__ia32_feature_control_msr_test(vcpu, FEAT_CTL_SGX_LC_ENABLED, X86_FEATURE_SGX_LC);
105 	__ia32_feature_control_msr_test(vcpu, FEAT_CTL_SGX_LC_ENABLED, X86_FEATURE_SGX);
106 	__ia32_feature_control_msr_test(vcpu, FEAT_CTL_SGX_ENABLED, X86_FEATURE_SGX);
107 	__ia32_feature_control_msr_test(vcpu, FEAT_CTL_LMCE_ENABLED, X86_FEATURE_MCE);
108 
109 	for_each_clear_bit(bit, &supported_bits, 64) {
110 		r = _vcpu_set_msr(vcpu, MSR_IA32_FEAT_CTL, BIT(bit));
111 		TEST_ASSERT(r == 0,
112 			    "Setting reserved bit %d in IA32_FEATURE_CONTROL should fail", bit);
113 	}
114 }
115 
main(void)116 int main(void)
117 {
118 	struct kvm_vcpu *vcpu;
119 	struct kvm_vm *vm;
120 
121 	TEST_REQUIRE(kvm_has_cap(KVM_CAP_DISABLE_QUIRKS2));
122 	TEST_REQUIRE(kvm_cpu_has(X86_FEATURE_VMX));
123 
124 	/* No need to actually do KVM_RUN, thus no guest code. */
125 	vm = vm_create_with_one_vcpu(&vcpu, NULL);
126 
127 	vmx_save_restore_msrs_test(vcpu);
128 	ia32_feature_control_msr_test(vcpu);
129 
130 	kvm_vm_free(vm);
131 }
132