xref: /openbmc/linux/drivers/gpu/drm/msm/msm_drv.c (revision 274f1614)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (c) 2016-2018, 2020-2021 The Linux Foundation. All rights reserved.
4  * Copyright (C) 2013 Red Hat
5  * Author: Rob Clark <robdclark@gmail.com>
6  */
7 
8 #include <linux/dma-mapping.h>
9 #include <linux/fault-inject.h>
10 #include <linux/kthread.h>
11 #include <linux/of_address.h>
12 #include <linux/sched/mm.h>
13 #include <linux/uaccess.h>
14 #include <uapi/linux/sched/types.h>
15 
16 #include <drm/drm_aperture.h>
17 #include <drm/drm_bridge.h>
18 #include <drm/drm_drv.h>
19 #include <drm/drm_file.h>
20 #include <drm/drm_ioctl.h>
21 #include <drm/drm_prime.h>
22 #include <drm/drm_of.h>
23 #include <drm/drm_vblank.h>
24 
25 #include "disp/msm_disp_snapshot.h"
26 #include "msm_drv.h"
27 #include "msm_debugfs.h"
28 #include "msm_fence.h"
29 #include "msm_gem.h"
30 #include "msm_gpu.h"
31 #include "msm_kms.h"
32 #include "msm_mmu.h"
33 #include "adreno/adreno_gpu.h"
34 
35 /*
36  * MSM driver version:
37  * - 1.0.0 - initial interface
38  * - 1.1.0 - adds madvise, and support for submits with > 4 cmd buffers
39  * - 1.2.0 - adds explicit fence support for submit ioctl
40  * - 1.3.0 - adds GMEM_BASE + NR_RINGS params, SUBMITQUEUE_NEW +
41  *           SUBMITQUEUE_CLOSE ioctls, and MSM_INFO_IOVA flag for
42  *           MSM_GEM_INFO ioctl.
43  * - 1.4.0 - softpin, MSM_RELOC_BO_DUMP, and GEM_INFO support to set/get
44  *           GEM object's debug name
45  * - 1.5.0 - Add SUBMITQUERY_QUERY ioctl
46  * - 1.6.0 - Syncobj support
47  * - 1.7.0 - Add MSM_PARAM_SUSPENDS to access suspend count
48  * - 1.8.0 - Add MSM_BO_CACHED_COHERENT for supported GPUs (a6xx)
49  * - 1.9.0 - Add MSM_SUBMIT_FENCE_SN_IN
50  * - 1.10.0 - Add MSM_SUBMIT_BO_NO_IMPLICIT
51  * - 1.11.0 - Add wait boost (MSM_WAIT_FENCE_BOOST, MSM_PREP_BOOST)
52  */
53 #define MSM_VERSION_MAJOR	1
54 #define MSM_VERSION_MINOR	10
55 #define MSM_VERSION_PATCHLEVEL	0
56 
57 static void msm_deinit_vram(struct drm_device *ddev);
58 
59 static const struct drm_mode_config_funcs mode_config_funcs = {
60 	.fb_create = msm_framebuffer_create,
61 	.atomic_check = msm_atomic_check,
62 	.atomic_commit = drm_atomic_helper_commit,
63 };
64 
65 static const struct drm_mode_config_helper_funcs mode_config_helper_funcs = {
66 	.atomic_commit_tail = msm_atomic_commit_tail,
67 };
68 
69 static char *vram = "16m";
70 MODULE_PARM_DESC(vram, "Configure VRAM size (for devices without IOMMU/GPUMMU)");
71 module_param(vram, charp, 0);
72 
73 bool dumpstate;
74 MODULE_PARM_DESC(dumpstate, "Dump KMS state on errors");
75 module_param(dumpstate, bool, 0600);
76 
77 static bool modeset = true;
78 MODULE_PARM_DESC(modeset, "Use kernel modesetting [KMS] (1=on (default), 0=disable)");
79 module_param(modeset, bool, 0600);
80 
81 #ifdef CONFIG_FAULT_INJECTION
82 DECLARE_FAULT_ATTR(fail_gem_alloc);
83 DECLARE_FAULT_ATTR(fail_gem_iova);
84 #endif
85 
msm_irq(int irq,void * arg)86 static irqreturn_t msm_irq(int irq, void *arg)
87 {
88 	struct drm_device *dev = arg;
89 	struct msm_drm_private *priv = dev->dev_private;
90 	struct msm_kms *kms = priv->kms;
91 
92 	BUG_ON(!kms);
93 
94 	return kms->funcs->irq(kms);
95 }
96 
msm_irq_preinstall(struct drm_device * dev)97 static void msm_irq_preinstall(struct drm_device *dev)
98 {
99 	struct msm_drm_private *priv = dev->dev_private;
100 	struct msm_kms *kms = priv->kms;
101 
102 	BUG_ON(!kms);
103 
104 	kms->funcs->irq_preinstall(kms);
105 }
106 
msm_irq_postinstall(struct drm_device * dev)107 static int msm_irq_postinstall(struct drm_device *dev)
108 {
109 	struct msm_drm_private *priv = dev->dev_private;
110 	struct msm_kms *kms = priv->kms;
111 
112 	BUG_ON(!kms);
113 
114 	if (kms->funcs->irq_postinstall)
115 		return kms->funcs->irq_postinstall(kms);
116 
117 	return 0;
118 }
119 
msm_irq_install(struct drm_device * dev,unsigned int irq)120 static int msm_irq_install(struct drm_device *dev, unsigned int irq)
121 {
122 	struct msm_drm_private *priv = dev->dev_private;
123 	struct msm_kms *kms = priv->kms;
124 	int ret;
125 
126 	if (irq == IRQ_NOTCONNECTED)
127 		return -ENOTCONN;
128 
129 	msm_irq_preinstall(dev);
130 
131 	ret = request_irq(irq, msm_irq, 0, dev->driver->name, dev);
132 	if (ret)
133 		return ret;
134 
135 	kms->irq_requested = true;
136 
137 	ret = msm_irq_postinstall(dev);
138 	if (ret) {
139 		free_irq(irq, dev);
140 		return ret;
141 	}
142 
143 	return 0;
144 }
145 
msm_irq_uninstall(struct drm_device * dev)146 static void msm_irq_uninstall(struct drm_device *dev)
147 {
148 	struct msm_drm_private *priv = dev->dev_private;
149 	struct msm_kms *kms = priv->kms;
150 
151 	kms->funcs->irq_uninstall(kms);
152 	if (kms->irq_requested)
153 		free_irq(kms->irq, dev);
154 }
155 
156 struct msm_vblank_work {
157 	struct work_struct work;
158 	struct drm_crtc *crtc;
159 	bool enable;
160 	struct msm_drm_private *priv;
161 };
162 
vblank_ctrl_worker(struct work_struct * work)163 static void vblank_ctrl_worker(struct work_struct *work)
164 {
165 	struct msm_vblank_work *vbl_work = container_of(work,
166 						struct msm_vblank_work, work);
167 	struct msm_drm_private *priv = vbl_work->priv;
168 	struct msm_kms *kms = priv->kms;
169 
170 	if (vbl_work->enable)
171 		kms->funcs->enable_vblank(kms, vbl_work->crtc);
172 	else
173 		kms->funcs->disable_vblank(kms,	vbl_work->crtc);
174 
175 	kfree(vbl_work);
176 }
177 
vblank_ctrl_queue_work(struct msm_drm_private * priv,struct drm_crtc * crtc,bool enable)178 static int vblank_ctrl_queue_work(struct msm_drm_private *priv,
179 					struct drm_crtc *crtc, bool enable)
180 {
181 	struct msm_vblank_work *vbl_work;
182 
183 	vbl_work = kzalloc(sizeof(*vbl_work), GFP_ATOMIC);
184 	if (!vbl_work)
185 		return -ENOMEM;
186 
187 	INIT_WORK(&vbl_work->work, vblank_ctrl_worker);
188 
189 	vbl_work->crtc = crtc;
190 	vbl_work->enable = enable;
191 	vbl_work->priv = priv;
192 
193 	queue_work(priv->wq, &vbl_work->work);
194 
195 	return 0;
196 }
197 
msm_drm_uninit(struct device * dev)198 static int msm_drm_uninit(struct device *dev)
199 {
200 	struct platform_device *pdev = to_platform_device(dev);
201 	struct msm_drm_private *priv = platform_get_drvdata(pdev);
202 	struct drm_device *ddev = priv->dev;
203 	struct msm_kms *kms = priv->kms;
204 	int i;
205 
206 	/*
207 	 * Shutdown the hw if we're far enough along where things might be on.
208 	 * If we run this too early, we'll end up panicking in any variety of
209 	 * places. Since we don't register the drm device until late in
210 	 * msm_drm_init, drm_dev->registered is used as an indicator that the
211 	 * shutdown will be successful.
212 	 */
213 	if (ddev->registered) {
214 		drm_dev_unregister(ddev);
215 		drm_atomic_helper_shutdown(ddev);
216 	}
217 
218 	/* We must cancel and cleanup any pending vblank enable/disable
219 	 * work before msm_irq_uninstall() to avoid work re-enabling an
220 	 * irq after uninstall has disabled it.
221 	 */
222 
223 	flush_workqueue(priv->wq);
224 
225 	/* clean up event worker threads */
226 	for (i = 0; i < priv->num_crtcs; i++) {
227 		if (priv->event_thread[i].worker)
228 			kthread_destroy_worker(priv->event_thread[i].worker);
229 	}
230 
231 	msm_gem_shrinker_cleanup(ddev);
232 
233 	drm_kms_helper_poll_fini(ddev);
234 
235 	msm_perf_debugfs_cleanup(priv);
236 	msm_rd_debugfs_cleanup(priv);
237 
238 	if (kms)
239 		msm_disp_snapshot_destroy(ddev);
240 
241 	drm_mode_config_cleanup(ddev);
242 
243 	for (i = 0; i < priv->num_bridges; i++)
244 		drm_bridge_remove(priv->bridges[i]);
245 	priv->num_bridges = 0;
246 
247 	if (kms) {
248 		pm_runtime_get_sync(dev);
249 		msm_irq_uninstall(ddev);
250 		pm_runtime_put_sync(dev);
251 	}
252 
253 	if (kms && kms->funcs)
254 		kms->funcs->destroy(kms);
255 
256 	msm_deinit_vram(ddev);
257 
258 	component_unbind_all(dev, ddev);
259 
260 	ddev->dev_private = NULL;
261 	drm_dev_put(ddev);
262 
263 	destroy_workqueue(priv->wq);
264 
265 	return 0;
266 }
267 
msm_kms_init_aspace(struct drm_device * dev)268 struct msm_gem_address_space *msm_kms_init_aspace(struct drm_device *dev)
269 {
270 	struct msm_gem_address_space *aspace;
271 	struct msm_mmu *mmu;
272 	struct device *mdp_dev = dev->dev;
273 	struct device *mdss_dev = mdp_dev->parent;
274 	struct device *iommu_dev;
275 
276 	/*
277 	 * IOMMUs can be a part of MDSS device tree binding, or the
278 	 * MDP/DPU device.
279 	 */
280 	if (device_iommu_mapped(mdp_dev))
281 		iommu_dev = mdp_dev;
282 	else
283 		iommu_dev = mdss_dev;
284 
285 	mmu = msm_iommu_new(iommu_dev, 0);
286 	if (IS_ERR(mmu))
287 		return ERR_CAST(mmu);
288 
289 	if (!mmu) {
290 		drm_info(dev, "no IOMMU, fallback to phys contig buffers for scanout\n");
291 		return NULL;
292 	}
293 
294 	aspace = msm_gem_address_space_create(mmu, "mdp_kms",
295 		0x1000, 0x100000000 - 0x1000);
296 	if (IS_ERR(aspace)) {
297 		dev_err(mdp_dev, "aspace create, error %pe\n", aspace);
298 		mmu->funcs->destroy(mmu);
299 	}
300 
301 	return aspace;
302 }
303 
msm_use_mmu(struct drm_device * dev)304 bool msm_use_mmu(struct drm_device *dev)
305 {
306 	struct msm_drm_private *priv = dev->dev_private;
307 
308 	/*
309 	 * a2xx comes with its own MMU
310 	 * On other platforms IOMMU can be declared specified either for the
311 	 * MDP/DPU device or for its parent, MDSS device.
312 	 */
313 	return priv->is_a2xx ||
314 		device_iommu_mapped(dev->dev) ||
315 		device_iommu_mapped(dev->dev->parent);
316 }
317 
msm_init_vram(struct drm_device * dev)318 static int msm_init_vram(struct drm_device *dev)
319 {
320 	struct msm_drm_private *priv = dev->dev_private;
321 	struct device_node *node;
322 	unsigned long size = 0;
323 	int ret = 0;
324 
325 	/* In the device-tree world, we could have a 'memory-region'
326 	 * phandle, which gives us a link to our "vram".  Allocating
327 	 * is all nicely abstracted behind the dma api, but we need
328 	 * to know the entire size to allocate it all in one go. There
329 	 * are two cases:
330 	 *  1) device with no IOMMU, in which case we need exclusive
331 	 *     access to a VRAM carveout big enough for all gpu
332 	 *     buffers
333 	 *  2) device with IOMMU, but where the bootloader puts up
334 	 *     a splash screen.  In this case, the VRAM carveout
335 	 *     need only be large enough for fbdev fb.  But we need
336 	 *     exclusive access to the buffer to avoid the kernel
337 	 *     using those pages for other purposes (which appears
338 	 *     as corruption on screen before we have a chance to
339 	 *     load and do initial modeset)
340 	 */
341 
342 	node = of_parse_phandle(dev->dev->of_node, "memory-region", 0);
343 	if (node) {
344 		struct resource r;
345 		ret = of_address_to_resource(node, 0, &r);
346 		of_node_put(node);
347 		if (ret)
348 			return ret;
349 		size = r.end - r.start + 1;
350 		DRM_INFO("using VRAM carveout: %lx@%pa\n", size, &r.start);
351 
352 		/* if we have no IOMMU, then we need to use carveout allocator.
353 		 * Grab the entire DMA chunk carved out in early startup in
354 		 * mach-msm:
355 		 */
356 	} else if (!msm_use_mmu(dev)) {
357 		DRM_INFO("using %s VRAM carveout\n", vram);
358 		size = memparse(vram, NULL);
359 	}
360 
361 	if (size) {
362 		unsigned long attrs = 0;
363 		void *p;
364 
365 		priv->vram.size = size;
366 
367 		drm_mm_init(&priv->vram.mm, 0, (size >> PAGE_SHIFT) - 1);
368 		spin_lock_init(&priv->vram.lock);
369 
370 		attrs |= DMA_ATTR_NO_KERNEL_MAPPING;
371 		attrs |= DMA_ATTR_WRITE_COMBINE;
372 
373 		/* note that for no-kernel-mapping, the vaddr returned
374 		 * is bogus, but non-null if allocation succeeded:
375 		 */
376 		p = dma_alloc_attrs(dev->dev, size,
377 				&priv->vram.paddr, GFP_KERNEL, attrs);
378 		if (!p) {
379 			DRM_DEV_ERROR(dev->dev, "failed to allocate VRAM\n");
380 			priv->vram.paddr = 0;
381 			return -ENOMEM;
382 		}
383 
384 		DRM_DEV_INFO(dev->dev, "VRAM: %08x->%08x\n",
385 				(uint32_t)priv->vram.paddr,
386 				(uint32_t)(priv->vram.paddr + size));
387 	}
388 
389 	return ret;
390 }
391 
msm_deinit_vram(struct drm_device * ddev)392 static void msm_deinit_vram(struct drm_device *ddev)
393 {
394 	struct msm_drm_private *priv = ddev->dev_private;
395 	unsigned long attrs = DMA_ATTR_NO_KERNEL_MAPPING;
396 
397 	if (!priv->vram.paddr)
398 		return;
399 
400 	drm_mm_takedown(&priv->vram.mm);
401 	dma_free_attrs(ddev->dev, priv->vram.size, NULL, priv->vram.paddr,
402 			attrs);
403 }
404 
msm_drm_init(struct device * dev,const struct drm_driver * drv)405 static int msm_drm_init(struct device *dev, const struct drm_driver *drv)
406 {
407 	struct msm_drm_private *priv = dev_get_drvdata(dev);
408 	struct drm_device *ddev;
409 	struct msm_kms *kms;
410 	struct drm_crtc *crtc;
411 	int ret;
412 
413 	if (drm_firmware_drivers_only())
414 		return -ENODEV;
415 
416 	ddev = drm_dev_alloc(drv, dev);
417 	if (IS_ERR(ddev)) {
418 		DRM_DEV_ERROR(dev, "failed to allocate drm_device\n");
419 		return PTR_ERR(ddev);
420 	}
421 	ddev->dev_private = priv;
422 	priv->dev = ddev;
423 
424 	priv->wq = alloc_ordered_workqueue("msm", 0);
425 	if (!priv->wq) {
426 		ret = -ENOMEM;
427 		goto err_put_dev;
428 	}
429 
430 	INIT_LIST_HEAD(&priv->objects);
431 	mutex_init(&priv->obj_lock);
432 
433 	/*
434 	 * Initialize the LRUs:
435 	 */
436 	mutex_init(&priv->lru.lock);
437 	drm_gem_lru_init(&priv->lru.unbacked, &priv->lru.lock);
438 	drm_gem_lru_init(&priv->lru.pinned,   &priv->lru.lock);
439 	drm_gem_lru_init(&priv->lru.willneed, &priv->lru.lock);
440 	drm_gem_lru_init(&priv->lru.dontneed, &priv->lru.lock);
441 
442 	/* Teach lockdep about lock ordering wrt. shrinker: */
443 	fs_reclaim_acquire(GFP_KERNEL);
444 	might_lock(&priv->lru.lock);
445 	fs_reclaim_release(GFP_KERNEL);
446 
447 	drm_mode_config_init(ddev);
448 
449 	ret = msm_init_vram(ddev);
450 	if (ret)
451 		goto err_cleanup_mode_config;
452 
453 	dma_set_max_seg_size(dev, UINT_MAX);
454 
455 	/* Bind all our sub-components: */
456 	ret = component_bind_all(dev, ddev);
457 	if (ret)
458 		goto err_deinit_vram;
459 
460 	/* the fw fb could be anywhere in memory */
461 	ret = drm_aperture_remove_framebuffers(drv);
462 	if (ret)
463 		goto err_msm_uninit;
464 
465 	msm_gem_shrinker_init(ddev);
466 
467 	if (priv->kms_init) {
468 		ret = priv->kms_init(ddev);
469 		if (ret) {
470 			DRM_DEV_ERROR(dev, "failed to load kms\n");
471 			priv->kms = NULL;
472 			goto err_msm_uninit;
473 		}
474 		kms = priv->kms;
475 	} else {
476 		/* valid only for the dummy headless case, where of_node=NULL */
477 		WARN_ON(dev->of_node);
478 		kms = NULL;
479 	}
480 
481 	/* Enable normalization of plane zpos */
482 	ddev->mode_config.normalize_zpos = true;
483 
484 	if (kms) {
485 		kms->dev = ddev;
486 		ret = kms->funcs->hw_init(kms);
487 		if (ret) {
488 			DRM_DEV_ERROR(dev, "kms hw init failed: %d\n", ret);
489 			goto err_msm_uninit;
490 		}
491 	}
492 
493 	drm_helper_move_panel_connectors_to_head(ddev);
494 
495 	ddev->mode_config.funcs = &mode_config_funcs;
496 	ddev->mode_config.helper_private = &mode_config_helper_funcs;
497 
498 	drm_for_each_crtc(crtc, ddev) {
499 		struct msm_drm_thread *ev_thread;
500 
501 		/* initialize event thread */
502 		ev_thread = &priv->event_thread[drm_crtc_index(crtc)];
503 		ev_thread->dev = ddev;
504 		ev_thread->worker = kthread_create_worker(0, "crtc_event:%d", crtc->base.id);
505 		if (IS_ERR(ev_thread->worker)) {
506 			ret = PTR_ERR(ev_thread->worker);
507 			DRM_DEV_ERROR(dev, "failed to create crtc_event kthread\n");
508 			ev_thread->worker = NULL;
509 			goto err_msm_uninit;
510 		}
511 
512 		sched_set_fifo(ev_thread->worker->task);
513 	}
514 
515 	ret = drm_vblank_init(ddev, priv->num_crtcs);
516 	if (ret < 0) {
517 		DRM_DEV_ERROR(dev, "failed to initialize vblank\n");
518 		goto err_msm_uninit;
519 	}
520 
521 	if (kms) {
522 		pm_runtime_get_sync(dev);
523 		ret = msm_irq_install(ddev, kms->irq);
524 		pm_runtime_put_sync(dev);
525 		if (ret < 0) {
526 			DRM_DEV_ERROR(dev, "failed to install IRQ handler\n");
527 			goto err_msm_uninit;
528 		}
529 	}
530 
531 	ret = drm_dev_register(ddev, 0);
532 	if (ret)
533 		goto err_msm_uninit;
534 
535 	if (kms) {
536 		ret = msm_disp_snapshot_init(ddev);
537 		if (ret)
538 			DRM_DEV_ERROR(dev, "msm_disp_snapshot_init failed ret = %d\n", ret);
539 	}
540 	drm_mode_config_reset(ddev);
541 
542 	ret = msm_debugfs_late_init(ddev);
543 	if (ret)
544 		goto err_msm_uninit;
545 
546 	drm_kms_helper_poll_init(ddev);
547 
548 	if (kms)
549 		msm_fbdev_setup(ddev);
550 
551 	return 0;
552 
553 err_msm_uninit:
554 	msm_drm_uninit(dev);
555 
556 	return ret;
557 
558 err_deinit_vram:
559 	msm_deinit_vram(ddev);
560 err_cleanup_mode_config:
561 	drm_mode_config_cleanup(ddev);
562 	destroy_workqueue(priv->wq);
563 err_put_dev:
564 	drm_dev_put(ddev);
565 
566 	return ret;
567 }
568 
569 /*
570  * DRM operations:
571  */
572 
load_gpu(struct drm_device * dev)573 static void load_gpu(struct drm_device *dev)
574 {
575 	static DEFINE_MUTEX(init_lock);
576 	struct msm_drm_private *priv = dev->dev_private;
577 
578 	mutex_lock(&init_lock);
579 
580 	if (!priv->gpu)
581 		priv->gpu = adreno_load_gpu(dev);
582 
583 	mutex_unlock(&init_lock);
584 }
585 
context_init(struct drm_device * dev,struct drm_file * file)586 static int context_init(struct drm_device *dev, struct drm_file *file)
587 {
588 	static atomic_t ident = ATOMIC_INIT(0);
589 	struct msm_drm_private *priv = dev->dev_private;
590 	struct msm_file_private *ctx;
591 
592 	ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
593 	if (!ctx)
594 		return -ENOMEM;
595 
596 	INIT_LIST_HEAD(&ctx->submitqueues);
597 	rwlock_init(&ctx->queuelock);
598 
599 	kref_init(&ctx->ref);
600 	msm_submitqueue_init(dev, ctx);
601 
602 	ctx->aspace = msm_gpu_create_private_address_space(priv->gpu, current);
603 	file->driver_priv = ctx;
604 
605 	ctx->seqno = atomic_inc_return(&ident);
606 
607 	return 0;
608 }
609 
msm_open(struct drm_device * dev,struct drm_file * file)610 static int msm_open(struct drm_device *dev, struct drm_file *file)
611 {
612 	/* For now, load gpu on open.. to avoid the requirement of having
613 	 * firmware in the initrd.
614 	 */
615 	load_gpu(dev);
616 
617 	return context_init(dev, file);
618 }
619 
context_close(struct msm_file_private * ctx)620 static void context_close(struct msm_file_private *ctx)
621 {
622 	msm_submitqueue_close(ctx);
623 	msm_file_private_put(ctx);
624 }
625 
msm_postclose(struct drm_device * dev,struct drm_file * file)626 static void msm_postclose(struct drm_device *dev, struct drm_file *file)
627 {
628 	struct msm_drm_private *priv = dev->dev_private;
629 	struct msm_file_private *ctx = file->driver_priv;
630 
631 	/*
632 	 * It is not possible to set sysprof param to non-zero if gpu
633 	 * is not initialized:
634 	 */
635 	if (priv->gpu)
636 		msm_file_private_set_sysprof(ctx, priv->gpu, 0);
637 
638 	context_close(ctx);
639 }
640 
msm_crtc_enable_vblank(struct drm_crtc * crtc)641 int msm_crtc_enable_vblank(struct drm_crtc *crtc)
642 {
643 	struct drm_device *dev = crtc->dev;
644 	struct msm_drm_private *priv = dev->dev_private;
645 	struct msm_kms *kms = priv->kms;
646 	if (!kms)
647 		return -ENXIO;
648 	drm_dbg_vbl(dev, "crtc=%u", crtc->base.id);
649 	return vblank_ctrl_queue_work(priv, crtc, true);
650 }
651 
msm_crtc_disable_vblank(struct drm_crtc * crtc)652 void msm_crtc_disable_vblank(struct drm_crtc *crtc)
653 {
654 	struct drm_device *dev = crtc->dev;
655 	struct msm_drm_private *priv = dev->dev_private;
656 	struct msm_kms *kms = priv->kms;
657 	if (!kms)
658 		return;
659 	drm_dbg_vbl(dev, "crtc=%u", crtc->base.id);
660 	vblank_ctrl_queue_work(priv, crtc, false);
661 }
662 
663 /*
664  * DRM ioctls:
665  */
666 
msm_ioctl_get_param(struct drm_device * dev,void * data,struct drm_file * file)667 static int msm_ioctl_get_param(struct drm_device *dev, void *data,
668 		struct drm_file *file)
669 {
670 	struct msm_drm_private *priv = dev->dev_private;
671 	struct drm_msm_param *args = data;
672 	struct msm_gpu *gpu;
673 
674 	/* for now, we just have 3d pipe.. eventually this would need to
675 	 * be more clever to dispatch to appropriate gpu module:
676 	 */
677 	if ((args->pipe != MSM_PIPE_3D0) || (args->pad != 0))
678 		return -EINVAL;
679 
680 	gpu = priv->gpu;
681 
682 	if (!gpu)
683 		return -ENXIO;
684 
685 	return gpu->funcs->get_param(gpu, file->driver_priv,
686 				     args->param, &args->value, &args->len);
687 }
688 
msm_ioctl_set_param(struct drm_device * dev,void * data,struct drm_file * file)689 static int msm_ioctl_set_param(struct drm_device *dev, void *data,
690 		struct drm_file *file)
691 {
692 	struct msm_drm_private *priv = dev->dev_private;
693 	struct drm_msm_param *args = data;
694 	struct msm_gpu *gpu;
695 
696 	if ((args->pipe != MSM_PIPE_3D0) || (args->pad != 0))
697 		return -EINVAL;
698 
699 	gpu = priv->gpu;
700 
701 	if (!gpu)
702 		return -ENXIO;
703 
704 	return gpu->funcs->set_param(gpu, file->driver_priv,
705 				     args->param, args->value, args->len);
706 }
707 
msm_ioctl_gem_new(struct drm_device * dev,void * data,struct drm_file * file)708 static int msm_ioctl_gem_new(struct drm_device *dev, void *data,
709 		struct drm_file *file)
710 {
711 	struct drm_msm_gem_new *args = data;
712 	uint32_t flags = args->flags;
713 
714 	if (args->flags & ~MSM_BO_FLAGS) {
715 		DRM_ERROR("invalid flags: %08x\n", args->flags);
716 		return -EINVAL;
717 	}
718 
719 	/*
720 	 * Uncached CPU mappings are deprecated, as of:
721 	 *
722 	 * 9ef364432db4 ("drm/msm: deprecate MSM_BO_UNCACHED (map as writecombine instead)")
723 	 *
724 	 * So promote them to WC.
725 	 */
726 	if (flags & MSM_BO_UNCACHED) {
727 		flags &= ~MSM_BO_CACHED;
728 		flags |= MSM_BO_WC;
729 	}
730 
731 	if (should_fail(&fail_gem_alloc, args->size))
732 		return -ENOMEM;
733 
734 	return msm_gem_new_handle(dev, file, args->size,
735 			args->flags, &args->handle, NULL);
736 }
737 
to_ktime(struct drm_msm_timespec timeout)738 static inline ktime_t to_ktime(struct drm_msm_timespec timeout)
739 {
740 	return ktime_set(timeout.tv_sec, timeout.tv_nsec);
741 }
742 
msm_ioctl_gem_cpu_prep(struct drm_device * dev,void * data,struct drm_file * file)743 static int msm_ioctl_gem_cpu_prep(struct drm_device *dev, void *data,
744 		struct drm_file *file)
745 {
746 	struct drm_msm_gem_cpu_prep *args = data;
747 	struct drm_gem_object *obj;
748 	ktime_t timeout = to_ktime(args->timeout);
749 	int ret;
750 
751 	if (args->op & ~MSM_PREP_FLAGS) {
752 		DRM_ERROR("invalid op: %08x\n", args->op);
753 		return -EINVAL;
754 	}
755 
756 	obj = drm_gem_object_lookup(file, args->handle);
757 	if (!obj)
758 		return -ENOENT;
759 
760 	ret = msm_gem_cpu_prep(obj, args->op, &timeout);
761 
762 	drm_gem_object_put(obj);
763 
764 	return ret;
765 }
766 
msm_ioctl_gem_cpu_fini(struct drm_device * dev,void * data,struct drm_file * file)767 static int msm_ioctl_gem_cpu_fini(struct drm_device *dev, void *data,
768 		struct drm_file *file)
769 {
770 	struct drm_msm_gem_cpu_fini *args = data;
771 	struct drm_gem_object *obj;
772 	int ret;
773 
774 	obj = drm_gem_object_lookup(file, args->handle);
775 	if (!obj)
776 		return -ENOENT;
777 
778 	ret = msm_gem_cpu_fini(obj);
779 
780 	drm_gem_object_put(obj);
781 
782 	return ret;
783 }
784 
msm_ioctl_gem_info_iova(struct drm_device * dev,struct drm_file * file,struct drm_gem_object * obj,uint64_t * iova)785 static int msm_ioctl_gem_info_iova(struct drm_device *dev,
786 		struct drm_file *file, struct drm_gem_object *obj,
787 		uint64_t *iova)
788 {
789 	struct msm_drm_private *priv = dev->dev_private;
790 	struct msm_file_private *ctx = file->driver_priv;
791 
792 	if (!priv->gpu)
793 		return -EINVAL;
794 
795 	if (should_fail(&fail_gem_iova, obj->size))
796 		return -ENOMEM;
797 
798 	/*
799 	 * Don't pin the memory here - just get an address so that userspace can
800 	 * be productive
801 	 */
802 	return msm_gem_get_iova(obj, ctx->aspace, iova);
803 }
804 
msm_ioctl_gem_info_set_iova(struct drm_device * dev,struct drm_file * file,struct drm_gem_object * obj,uint64_t iova)805 static int msm_ioctl_gem_info_set_iova(struct drm_device *dev,
806 		struct drm_file *file, struct drm_gem_object *obj,
807 		uint64_t iova)
808 {
809 	struct msm_drm_private *priv = dev->dev_private;
810 	struct msm_file_private *ctx = file->driver_priv;
811 
812 	if (!priv->gpu)
813 		return -EINVAL;
814 
815 	/* Only supported if per-process address space is supported: */
816 	if (priv->gpu->aspace == ctx->aspace)
817 		return -EOPNOTSUPP;
818 
819 	if (should_fail(&fail_gem_iova, obj->size))
820 		return -ENOMEM;
821 
822 	return msm_gem_set_iova(obj, ctx->aspace, iova);
823 }
824 
msm_ioctl_gem_info(struct drm_device * dev,void * data,struct drm_file * file)825 static int msm_ioctl_gem_info(struct drm_device *dev, void *data,
826 		struct drm_file *file)
827 {
828 	struct drm_msm_gem_info *args = data;
829 	struct drm_gem_object *obj;
830 	struct msm_gem_object *msm_obj;
831 	int i, ret = 0;
832 
833 	if (args->pad)
834 		return -EINVAL;
835 
836 	switch (args->info) {
837 	case MSM_INFO_GET_OFFSET:
838 	case MSM_INFO_GET_IOVA:
839 	case MSM_INFO_SET_IOVA:
840 	case MSM_INFO_GET_FLAGS:
841 		/* value returned as immediate, not pointer, so len==0: */
842 		if (args->len)
843 			return -EINVAL;
844 		break;
845 	case MSM_INFO_SET_NAME:
846 	case MSM_INFO_GET_NAME:
847 		break;
848 	default:
849 		return -EINVAL;
850 	}
851 
852 	obj = drm_gem_object_lookup(file, args->handle);
853 	if (!obj)
854 		return -ENOENT;
855 
856 	msm_obj = to_msm_bo(obj);
857 
858 	switch (args->info) {
859 	case MSM_INFO_GET_OFFSET:
860 		args->value = msm_gem_mmap_offset(obj);
861 		break;
862 	case MSM_INFO_GET_IOVA:
863 		ret = msm_ioctl_gem_info_iova(dev, file, obj, &args->value);
864 		break;
865 	case MSM_INFO_SET_IOVA:
866 		ret = msm_ioctl_gem_info_set_iova(dev, file, obj, args->value);
867 		break;
868 	case MSM_INFO_GET_FLAGS:
869 		if (obj->import_attach) {
870 			ret = -EINVAL;
871 			break;
872 		}
873 		/* Hide internal kernel-only flags: */
874 		args->value = to_msm_bo(obj)->flags & MSM_BO_FLAGS;
875 		ret = 0;
876 		break;
877 	case MSM_INFO_SET_NAME:
878 		/* length check should leave room for terminating null: */
879 		if (args->len >= sizeof(msm_obj->name)) {
880 			ret = -EINVAL;
881 			break;
882 		}
883 		if (copy_from_user(msm_obj->name, u64_to_user_ptr(args->value),
884 				   args->len)) {
885 			msm_obj->name[0] = '\0';
886 			ret = -EFAULT;
887 			break;
888 		}
889 		msm_obj->name[args->len] = '\0';
890 		for (i = 0; i < args->len; i++) {
891 			if (!isprint(msm_obj->name[i])) {
892 				msm_obj->name[i] = '\0';
893 				break;
894 			}
895 		}
896 		break;
897 	case MSM_INFO_GET_NAME:
898 		if (args->value && (args->len < strlen(msm_obj->name))) {
899 			ret = -EINVAL;
900 			break;
901 		}
902 		args->len = strlen(msm_obj->name);
903 		if (args->value) {
904 			if (copy_to_user(u64_to_user_ptr(args->value),
905 					 msm_obj->name, args->len))
906 				ret = -EFAULT;
907 		}
908 		break;
909 	}
910 
911 	drm_gem_object_put(obj);
912 
913 	return ret;
914 }
915 
wait_fence(struct msm_gpu_submitqueue * queue,uint32_t fence_id,ktime_t timeout,uint32_t flags)916 static int wait_fence(struct msm_gpu_submitqueue *queue, uint32_t fence_id,
917 		      ktime_t timeout, uint32_t flags)
918 {
919 	struct dma_fence *fence;
920 	int ret;
921 
922 	if (fence_after(fence_id, queue->last_fence)) {
923 		DRM_ERROR_RATELIMITED("waiting on invalid fence: %u (of %u)\n",
924 				      fence_id, queue->last_fence);
925 		return -EINVAL;
926 	}
927 
928 	/*
929 	 * Map submitqueue scoped "seqno" (which is actually an idr key)
930 	 * back to underlying dma-fence
931 	 *
932 	 * The fence is removed from the fence_idr when the submit is
933 	 * retired, so if the fence is not found it means there is nothing
934 	 * to wait for
935 	 */
936 	spin_lock(&queue->idr_lock);
937 	fence = idr_find(&queue->fence_idr, fence_id);
938 	if (fence)
939 		fence = dma_fence_get_rcu(fence);
940 	spin_unlock(&queue->idr_lock);
941 
942 	if (!fence)
943 		return 0;
944 
945 	if (flags & MSM_WAIT_FENCE_BOOST)
946 		dma_fence_set_deadline(fence, ktime_get());
947 
948 	ret = dma_fence_wait_timeout(fence, true, timeout_to_jiffies(&timeout));
949 	if (ret == 0) {
950 		ret = -ETIMEDOUT;
951 	} else if (ret != -ERESTARTSYS) {
952 		ret = 0;
953 	}
954 
955 	dma_fence_put(fence);
956 
957 	return ret;
958 }
959 
msm_ioctl_wait_fence(struct drm_device * dev,void * data,struct drm_file * file)960 static int msm_ioctl_wait_fence(struct drm_device *dev, void *data,
961 		struct drm_file *file)
962 {
963 	struct msm_drm_private *priv = dev->dev_private;
964 	struct drm_msm_wait_fence *args = data;
965 	struct msm_gpu_submitqueue *queue;
966 	int ret;
967 
968 	if (args->flags & ~MSM_WAIT_FENCE_FLAGS) {
969 		DRM_ERROR("invalid flags: %08x\n", args->flags);
970 		return -EINVAL;
971 	}
972 
973 	if (!priv->gpu)
974 		return 0;
975 
976 	queue = msm_submitqueue_get(file->driver_priv, args->queueid);
977 	if (!queue)
978 		return -ENOENT;
979 
980 	ret = wait_fence(queue, args->fence, to_ktime(args->timeout), args->flags);
981 
982 	msm_submitqueue_put(queue);
983 
984 	return ret;
985 }
986 
msm_ioctl_gem_madvise(struct drm_device * dev,void * data,struct drm_file * file)987 static int msm_ioctl_gem_madvise(struct drm_device *dev, void *data,
988 		struct drm_file *file)
989 {
990 	struct drm_msm_gem_madvise *args = data;
991 	struct drm_gem_object *obj;
992 	int ret;
993 
994 	switch (args->madv) {
995 	case MSM_MADV_DONTNEED:
996 	case MSM_MADV_WILLNEED:
997 		break;
998 	default:
999 		return -EINVAL;
1000 	}
1001 
1002 	obj = drm_gem_object_lookup(file, args->handle);
1003 	if (!obj) {
1004 		return -ENOENT;
1005 	}
1006 
1007 	ret = msm_gem_madvise(obj, args->madv);
1008 	if (ret >= 0) {
1009 		args->retained = ret;
1010 		ret = 0;
1011 	}
1012 
1013 	drm_gem_object_put(obj);
1014 
1015 	return ret;
1016 }
1017 
1018 
msm_ioctl_submitqueue_new(struct drm_device * dev,void * data,struct drm_file * file)1019 static int msm_ioctl_submitqueue_new(struct drm_device *dev, void *data,
1020 		struct drm_file *file)
1021 {
1022 	struct drm_msm_submitqueue *args = data;
1023 
1024 	if (args->flags & ~MSM_SUBMITQUEUE_FLAGS)
1025 		return -EINVAL;
1026 
1027 	return msm_submitqueue_create(dev, file->driver_priv, args->prio,
1028 		args->flags, &args->id);
1029 }
1030 
msm_ioctl_submitqueue_query(struct drm_device * dev,void * data,struct drm_file * file)1031 static int msm_ioctl_submitqueue_query(struct drm_device *dev, void *data,
1032 		struct drm_file *file)
1033 {
1034 	return msm_submitqueue_query(dev, file->driver_priv, data);
1035 }
1036 
msm_ioctl_submitqueue_close(struct drm_device * dev,void * data,struct drm_file * file)1037 static int msm_ioctl_submitqueue_close(struct drm_device *dev, void *data,
1038 		struct drm_file *file)
1039 {
1040 	u32 id = *(u32 *) data;
1041 
1042 	return msm_submitqueue_remove(file->driver_priv, id);
1043 }
1044 
1045 static const struct drm_ioctl_desc msm_ioctls[] = {
1046 	DRM_IOCTL_DEF_DRV(MSM_GET_PARAM,    msm_ioctl_get_param,    DRM_RENDER_ALLOW),
1047 	DRM_IOCTL_DEF_DRV(MSM_SET_PARAM,    msm_ioctl_set_param,    DRM_RENDER_ALLOW),
1048 	DRM_IOCTL_DEF_DRV(MSM_GEM_NEW,      msm_ioctl_gem_new,      DRM_RENDER_ALLOW),
1049 	DRM_IOCTL_DEF_DRV(MSM_GEM_INFO,     msm_ioctl_gem_info,     DRM_RENDER_ALLOW),
1050 	DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_PREP, msm_ioctl_gem_cpu_prep, DRM_RENDER_ALLOW),
1051 	DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_FINI, msm_ioctl_gem_cpu_fini, DRM_RENDER_ALLOW),
1052 	DRM_IOCTL_DEF_DRV(MSM_GEM_SUBMIT,   msm_ioctl_gem_submit,   DRM_RENDER_ALLOW),
1053 	DRM_IOCTL_DEF_DRV(MSM_WAIT_FENCE,   msm_ioctl_wait_fence,   DRM_RENDER_ALLOW),
1054 	DRM_IOCTL_DEF_DRV(MSM_GEM_MADVISE,  msm_ioctl_gem_madvise,  DRM_RENDER_ALLOW),
1055 	DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_NEW,   msm_ioctl_submitqueue_new,   DRM_RENDER_ALLOW),
1056 	DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_CLOSE, msm_ioctl_submitqueue_close, DRM_RENDER_ALLOW),
1057 	DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_QUERY, msm_ioctl_submitqueue_query, DRM_RENDER_ALLOW),
1058 };
1059 
msm_show_fdinfo(struct drm_printer * p,struct drm_file * file)1060 static void msm_show_fdinfo(struct drm_printer *p, struct drm_file *file)
1061 {
1062 	struct drm_device *dev = file->minor->dev;
1063 	struct msm_drm_private *priv = dev->dev_private;
1064 
1065 	if (!priv->gpu)
1066 		return;
1067 
1068 	msm_gpu_show_fdinfo(priv->gpu, file->driver_priv, p);
1069 
1070 	drm_show_memory_stats(p, file);
1071 }
1072 
1073 static const struct file_operations fops = {
1074 	.owner = THIS_MODULE,
1075 	DRM_GEM_FOPS,
1076 	.show_fdinfo = drm_show_fdinfo,
1077 };
1078 
1079 static const struct drm_driver msm_driver = {
1080 	.driver_features    = DRIVER_GEM |
1081 				DRIVER_RENDER |
1082 				DRIVER_ATOMIC |
1083 				DRIVER_MODESET |
1084 				DRIVER_SYNCOBJ,
1085 	.open               = msm_open,
1086 	.postclose          = msm_postclose,
1087 	.dumb_create        = msm_gem_dumb_create,
1088 	.dumb_map_offset    = msm_gem_dumb_map_offset,
1089 	.gem_prime_import_sg_table = msm_gem_prime_import_sg_table,
1090 #ifdef CONFIG_DEBUG_FS
1091 	.debugfs_init       = msm_debugfs_init,
1092 #endif
1093 	.show_fdinfo        = msm_show_fdinfo,
1094 	.ioctls             = msm_ioctls,
1095 	.num_ioctls         = ARRAY_SIZE(msm_ioctls),
1096 	.fops               = &fops,
1097 	.name               = "msm",
1098 	.desc               = "MSM Snapdragon DRM",
1099 	.date               = "20130625",
1100 	.major              = MSM_VERSION_MAJOR,
1101 	.minor              = MSM_VERSION_MINOR,
1102 	.patchlevel         = MSM_VERSION_PATCHLEVEL,
1103 };
1104 
msm_pm_prepare(struct device * dev)1105 int msm_pm_prepare(struct device *dev)
1106 {
1107 	struct msm_drm_private *priv = dev_get_drvdata(dev);
1108 	struct drm_device *ddev = priv ? priv->dev : NULL;
1109 
1110 	if (!priv || !priv->kms)
1111 		return 0;
1112 
1113 	return drm_mode_config_helper_suspend(ddev);
1114 }
1115 
msm_pm_complete(struct device * dev)1116 void msm_pm_complete(struct device *dev)
1117 {
1118 	struct msm_drm_private *priv = dev_get_drvdata(dev);
1119 	struct drm_device *ddev = priv ? priv->dev : NULL;
1120 
1121 	if (!priv || !priv->kms)
1122 		return;
1123 
1124 	drm_mode_config_helper_resume(ddev);
1125 }
1126 
1127 static const struct dev_pm_ops msm_pm_ops = {
1128 	.prepare = msm_pm_prepare,
1129 	.complete = msm_pm_complete,
1130 };
1131 
1132 /*
1133  * Componentized driver support:
1134  */
1135 
1136 /*
1137  * Identify what components need to be added by parsing what remote-endpoints
1138  * our MDP output ports are connected to. In the case of LVDS on MDP4, there
1139  * is no external component that we need to add since LVDS is within MDP4
1140  * itself.
1141  */
add_components_mdp(struct device * master_dev,struct component_match ** matchptr)1142 static int add_components_mdp(struct device *master_dev,
1143 			      struct component_match **matchptr)
1144 {
1145 	struct device_node *np = master_dev->of_node;
1146 	struct device_node *ep_node;
1147 
1148 	for_each_endpoint_of_node(np, ep_node) {
1149 		struct device_node *intf;
1150 		struct of_endpoint ep;
1151 		int ret;
1152 
1153 		ret = of_graph_parse_endpoint(ep_node, &ep);
1154 		if (ret) {
1155 			DRM_DEV_ERROR(master_dev, "unable to parse port endpoint\n");
1156 			of_node_put(ep_node);
1157 			return ret;
1158 		}
1159 
1160 		/*
1161 		 * The LCDC/LVDS port on MDP4 is a speacial case where the
1162 		 * remote-endpoint isn't a component that we need to add
1163 		 */
1164 		if (of_device_is_compatible(np, "qcom,mdp4") &&
1165 		    ep.port == 0)
1166 			continue;
1167 
1168 		/*
1169 		 * It's okay if some of the ports don't have a remote endpoint
1170 		 * specified. It just means that the port isn't connected to
1171 		 * any external interface.
1172 		 */
1173 		intf = of_graph_get_remote_port_parent(ep_node);
1174 		if (!intf)
1175 			continue;
1176 
1177 		if (of_device_is_available(intf))
1178 			drm_of_component_match_add(master_dev, matchptr,
1179 						   component_compare_of, intf);
1180 
1181 		of_node_put(intf);
1182 	}
1183 
1184 	return 0;
1185 }
1186 
1187 /*
1188  * We don't know what's the best binding to link the gpu with the drm device.
1189  * Fow now, we just hunt for all the possible gpus that we support, and add them
1190  * as components.
1191  */
1192 static const struct of_device_id msm_gpu_match[] = {
1193 	{ .compatible = "qcom,adreno" },
1194 	{ .compatible = "qcom,adreno-3xx" },
1195 	{ .compatible = "amd,imageon" },
1196 	{ .compatible = "qcom,kgsl-3d0" },
1197 	{ },
1198 };
1199 
add_gpu_components(struct device * dev,struct component_match ** matchptr)1200 static int add_gpu_components(struct device *dev,
1201 			      struct component_match **matchptr)
1202 {
1203 	struct device_node *np;
1204 
1205 	np = of_find_matching_node(NULL, msm_gpu_match);
1206 	if (!np)
1207 		return 0;
1208 
1209 	if (of_device_is_available(np))
1210 		drm_of_component_match_add(dev, matchptr, component_compare_of, np);
1211 
1212 	of_node_put(np);
1213 
1214 	return 0;
1215 }
1216 
msm_drm_bind(struct device * dev)1217 static int msm_drm_bind(struct device *dev)
1218 {
1219 	return msm_drm_init(dev, &msm_driver);
1220 }
1221 
msm_drm_unbind(struct device * dev)1222 static void msm_drm_unbind(struct device *dev)
1223 {
1224 	msm_drm_uninit(dev);
1225 }
1226 
1227 const struct component_master_ops msm_drm_ops = {
1228 	.bind = msm_drm_bind,
1229 	.unbind = msm_drm_unbind,
1230 };
1231 
msm_drv_probe(struct device * master_dev,int (* kms_init)(struct drm_device * dev))1232 int msm_drv_probe(struct device *master_dev,
1233 	int (*kms_init)(struct drm_device *dev))
1234 {
1235 	struct msm_drm_private *priv;
1236 	struct component_match *match = NULL;
1237 	int ret;
1238 
1239 	priv = devm_kzalloc(master_dev, sizeof(*priv), GFP_KERNEL);
1240 	if (!priv)
1241 		return -ENOMEM;
1242 
1243 	priv->kms_init = kms_init;
1244 	dev_set_drvdata(master_dev, priv);
1245 
1246 	/* Add mdp components if we have KMS. */
1247 	if (kms_init) {
1248 		ret = add_components_mdp(master_dev, &match);
1249 		if (ret)
1250 			return ret;
1251 	}
1252 
1253 	ret = add_gpu_components(master_dev, &match);
1254 	if (ret)
1255 		return ret;
1256 
1257 	/* on all devices that I am aware of, iommu's which can map
1258 	 * any address the cpu can see are used:
1259 	 */
1260 	ret = dma_set_mask_and_coherent(master_dev, ~0);
1261 	if (ret)
1262 		return ret;
1263 
1264 	ret = component_master_add_with_match(master_dev, &msm_drm_ops, match);
1265 	if (ret)
1266 		return ret;
1267 
1268 	return 0;
1269 }
1270 
1271 /*
1272  * Platform driver:
1273  * Used only for headlesss GPU instances
1274  */
1275 
msm_pdev_probe(struct platform_device * pdev)1276 static int msm_pdev_probe(struct platform_device *pdev)
1277 {
1278 	return msm_drv_probe(&pdev->dev, NULL);
1279 }
1280 
msm_pdev_remove(struct platform_device * pdev)1281 static int msm_pdev_remove(struct platform_device *pdev)
1282 {
1283 	component_master_del(&pdev->dev, &msm_drm_ops);
1284 
1285 	return 0;
1286 }
1287 
msm_drv_shutdown(struct platform_device * pdev)1288 void msm_drv_shutdown(struct platform_device *pdev)
1289 {
1290 	struct msm_drm_private *priv = platform_get_drvdata(pdev);
1291 	struct drm_device *drm = priv ? priv->dev : NULL;
1292 
1293 	/*
1294 	 * Shutdown the hw if we're far enough along where things might be on.
1295 	 * If we run this too early, we'll end up panicking in any variety of
1296 	 * places. Since we don't register the drm device until late in
1297 	 * msm_drm_init, drm_dev->registered is used as an indicator that the
1298 	 * shutdown will be successful.
1299 	 */
1300 	if (drm && drm->registered && priv->kms)
1301 		drm_atomic_helper_shutdown(drm);
1302 }
1303 
1304 static struct platform_driver msm_platform_driver = {
1305 	.probe      = msm_pdev_probe,
1306 	.remove     = msm_pdev_remove,
1307 	.shutdown   = msm_drv_shutdown,
1308 	.driver     = {
1309 		.name   = "msm",
1310 		.pm     = &msm_pm_ops,
1311 	},
1312 };
1313 
msm_drm_register(void)1314 static int __init msm_drm_register(void)
1315 {
1316 	if (!modeset)
1317 		return -EINVAL;
1318 
1319 	DBG("init");
1320 	msm_mdp_register();
1321 	msm_dpu_register();
1322 	msm_dsi_register();
1323 	msm_hdmi_register();
1324 	msm_dp_register();
1325 	adreno_register();
1326 	msm_mdp4_register();
1327 	msm_mdss_register();
1328 	return platform_driver_register(&msm_platform_driver);
1329 }
1330 
msm_drm_unregister(void)1331 static void __exit msm_drm_unregister(void)
1332 {
1333 	DBG("fini");
1334 	platform_driver_unregister(&msm_platform_driver);
1335 	msm_mdss_unregister();
1336 	msm_mdp4_unregister();
1337 	msm_dp_unregister();
1338 	msm_hdmi_unregister();
1339 	adreno_unregister();
1340 	msm_dsi_unregister();
1341 	msm_mdp_unregister();
1342 	msm_dpu_unregister();
1343 }
1344 
1345 module_init(msm_drm_register);
1346 module_exit(msm_drm_unregister);
1347 
1348 MODULE_AUTHOR("Rob Clark <robdclark@gmail.com");
1349 MODULE_DESCRIPTION("MSM DRM Driver");
1350 MODULE_LICENSE("GPL");
1351