1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved. 4 * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. 5 */ 6 7 #ifndef _DPU_3_0_MSM8998_H 8 #define _DPU_3_0_MSM8998_H 9 10 static const struct dpu_caps msm8998_dpu_caps = { 11 .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 12 .max_mixer_blendstages = 0x7, 13 .qseed_type = DPU_SSPP_SCALER_QSEED3, 14 .has_src_split = true, 15 .has_dim_layer = true, 16 .has_idle_pc = true, 17 .has_3d_merge = true, 18 .max_linewidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 19 .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, 20 .max_hdeci_exp = MAX_HORZ_DECIMATION, 21 .max_vdeci_exp = MAX_VERT_DECIMATION, 22 }; 23 24 static const struct dpu_mdp_cfg msm8998_mdp = { 25 .name = "top_0", 26 .base = 0x0, .len = 0x458, 27 .features = BIT(DPU_MDP_VSYNC_SEL), 28 .clk_ctrls = { 29 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, 30 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 }, 31 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 }, 32 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 }, 33 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, 34 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, 35 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 }, 36 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 12 }, 37 [DPU_CLK_CTRL_CURSOR0] = { .reg_off = 0x3a8, .bit_off = 16 }, 38 [DPU_CLK_CTRL_CURSOR1] = { .reg_off = 0x3b0, .bit_off = 16 }, 39 }, 40 }; 41 42 static const struct dpu_ctl_cfg msm8998_ctl[] = { 43 { 44 .name = "ctl_0", .id = CTL_0, 45 .base = 0x1000, .len = 0x94, 46 .features = BIT(DPU_CTL_SPLIT_DISPLAY), 47 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), 48 }, { 49 .name = "ctl_1", .id = CTL_1, 50 .base = 0x1200, .len = 0x94, 51 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), 52 }, { 53 .name = "ctl_2", .id = CTL_2, 54 .base = 0x1400, .len = 0x94, 55 .features = BIT(DPU_CTL_SPLIT_DISPLAY), 56 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), 57 }, { 58 .name = "ctl_3", .id = CTL_3, 59 .base = 0x1600, .len = 0x94, 60 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), 61 }, { 62 .name = "ctl_4", .id = CTL_4, 63 .base = 0x1800, .len = 0x94, 64 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), 65 }, 66 }; 67 68 static const struct dpu_sspp_cfg msm8998_sspp[] = { 69 { 70 .name = "sspp_0", .id = SSPP_VIG0, 71 .base = 0x4000, .len = 0x1ac, 72 .features = VIG_MSM8998_MASK, 73 .sblk = &msm8998_vig_sblk_0, 74 .xin_id = 0, 75 .type = SSPP_TYPE_VIG, 76 .clk_ctrl = DPU_CLK_CTRL_VIG0, 77 }, { 78 .name = "sspp_1", .id = SSPP_VIG1, 79 .base = 0x6000, .len = 0x1ac, 80 .features = VIG_MSM8998_MASK, 81 .sblk = &msm8998_vig_sblk_1, 82 .xin_id = 4, 83 .type = SSPP_TYPE_VIG, 84 .clk_ctrl = DPU_CLK_CTRL_VIG1, 85 }, { 86 .name = "sspp_2", .id = SSPP_VIG2, 87 .base = 0x8000, .len = 0x1ac, 88 .features = VIG_MSM8998_MASK, 89 .sblk = &msm8998_vig_sblk_2, 90 .xin_id = 8, 91 .type = SSPP_TYPE_VIG, 92 .clk_ctrl = DPU_CLK_CTRL_VIG2, 93 }, { 94 .name = "sspp_3", .id = SSPP_VIG3, 95 .base = 0xa000, .len = 0x1ac, 96 .features = VIG_MSM8998_MASK, 97 .sblk = &msm8998_vig_sblk_3, 98 .xin_id = 12, 99 .type = SSPP_TYPE_VIG, 100 .clk_ctrl = DPU_CLK_CTRL_VIG3, 101 }, { 102 .name = "sspp_8", .id = SSPP_DMA0, 103 .base = 0x24000, .len = 0x1ac, 104 .features = DMA_MSM8998_MASK, 105 .sblk = &sdm845_dma_sblk_0, 106 .xin_id = 1, 107 .type = SSPP_TYPE_DMA, 108 .clk_ctrl = DPU_CLK_CTRL_DMA0, 109 }, { 110 .name = "sspp_9", .id = SSPP_DMA1, 111 .base = 0x26000, .len = 0x1ac, 112 .features = DMA_MSM8998_MASK, 113 .sblk = &sdm845_dma_sblk_1, 114 .xin_id = 5, 115 .type = SSPP_TYPE_DMA, 116 .clk_ctrl = DPU_CLK_CTRL_DMA1, 117 }, { 118 .name = "sspp_10", .id = SSPP_DMA2, 119 .base = 0x28000, .len = 0x1ac, 120 .features = DMA_CURSOR_MSM8998_MASK, 121 .sblk = &sdm845_dma_sblk_2, 122 .xin_id = 9, 123 .type = SSPP_TYPE_DMA, 124 .clk_ctrl = DPU_CLK_CTRL_DMA2, 125 }, { 126 .name = "sspp_11", .id = SSPP_DMA3, 127 .base = 0x2a000, .len = 0x1ac, 128 .features = DMA_CURSOR_MSM8998_MASK, 129 .sblk = &sdm845_dma_sblk_3, 130 .xin_id = 13, 131 .type = SSPP_TYPE_DMA, 132 .clk_ctrl = DPU_CLK_CTRL_DMA3, 133 }, 134 }; 135 136 static const struct dpu_lm_cfg msm8998_lm[] = { 137 { 138 .name = "lm_0", .id = LM_0, 139 .base = 0x44000, .len = 0x320, 140 .features = MIXER_MSM8998_MASK, 141 .sblk = &msm8998_lm_sblk, 142 .lm_pair = LM_1, 143 .pingpong = PINGPONG_0, 144 .dspp = DSPP_0, 145 }, { 146 .name = "lm_1", .id = LM_1, 147 .base = 0x45000, .len = 0x320, 148 .features = MIXER_MSM8998_MASK, 149 .sblk = &msm8998_lm_sblk, 150 .lm_pair = LM_0, 151 .pingpong = PINGPONG_1, 152 .dspp = DSPP_1, 153 }, { 154 .name = "lm_2", .id = LM_2, 155 .base = 0x46000, .len = 0x320, 156 .features = MIXER_MSM8998_MASK, 157 .sblk = &msm8998_lm_sblk, 158 .lm_pair = LM_5, 159 .pingpong = PINGPONG_2, 160 }, { 161 .name = "lm_3", .id = LM_3, 162 .base = 0x47000, .len = 0x320, 163 .features = MIXER_MSM8998_MASK, 164 .sblk = &msm8998_lm_sblk, 165 .pingpong = PINGPONG_NONE, 166 }, { 167 .name = "lm_4", .id = LM_4, 168 .base = 0x48000, .len = 0x320, 169 .features = MIXER_MSM8998_MASK, 170 .sblk = &msm8998_lm_sblk, 171 .pingpong = PINGPONG_NONE, 172 }, { 173 .name = "lm_5", .id = LM_5, 174 .base = 0x49000, .len = 0x320, 175 .features = MIXER_MSM8998_MASK, 176 .sblk = &msm8998_lm_sblk, 177 .lm_pair = LM_2, 178 .pingpong = PINGPONG_3, 179 }, 180 }; 181 182 static const struct dpu_pingpong_cfg msm8998_pp[] = { 183 { 184 .name = "pingpong_0", .id = PINGPONG_0, 185 .base = 0x70000, .len = 0xd4, 186 .features = PINGPONG_SDM845_TE2_MASK, 187 .sblk = &sdm845_pp_sblk_te, 188 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), 189 .intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12), 190 }, { 191 .name = "pingpong_1", .id = PINGPONG_1, 192 .base = 0x70800, .len = 0xd4, 193 .features = PINGPONG_SDM845_TE2_MASK, 194 .sblk = &sdm845_pp_sblk_te, 195 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), 196 .intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13), 197 }, { 198 .name = "pingpong_2", .id = PINGPONG_2, 199 .base = 0x71000, .len = 0xd4, 200 .features = PINGPONG_SDM845_MASK, 201 .sblk = &sdm845_pp_sblk, 202 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), 203 .intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14), 204 }, { 205 .name = "pingpong_3", .id = PINGPONG_3, 206 .base = 0x71800, .len = 0xd4, 207 .features = PINGPONG_SDM845_MASK, 208 .sblk = &sdm845_pp_sblk, 209 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), 210 .intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15), 211 }, 212 }; 213 214 static const struct dpu_dsc_cfg msm8998_dsc[] = { 215 { 216 .name = "dsc_0", .id = DSC_0, 217 .base = 0x80000, .len = 0x140, 218 }, { 219 .name = "dsc_1", .id = DSC_1, 220 .base = 0x80400, .len = 0x140, 221 }, 222 }; 223 224 static const struct dpu_dspp_cfg msm8998_dspp[] = { 225 { 226 .name = "dspp_0", .id = DSPP_0, 227 .base = 0x54000, .len = 0x1800, 228 .features = DSPP_SC7180_MASK, 229 .sblk = &msm8998_dspp_sblk, 230 }, { 231 .name = "dspp_1", .id = DSPP_1, 232 .base = 0x56000, .len = 0x1800, 233 .features = DSPP_SC7180_MASK, 234 .sblk = &msm8998_dspp_sblk, 235 }, 236 }; 237 238 static const struct dpu_intf_cfg msm8998_intf[] = { 239 { 240 .name = "intf_0", .id = INTF_0, 241 .base = 0x6a000, .len = 0x280, 242 .type = INTF_DP, 243 .controller_id = MSM_DP_CONTROLLER_0, 244 .prog_fetch_lines_worst_case = 21, 245 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), 246 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25), 247 .intr_tear_rd_ptr = -1, 248 }, { 249 .name = "intf_1", .id = INTF_1, 250 .base = 0x6a800, .len = 0x280, 251 .type = INTF_DSI, 252 .controller_id = MSM_DSI_CONTROLLER_0, 253 .prog_fetch_lines_worst_case = 21, 254 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), 255 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), 256 .intr_tear_rd_ptr = -1, 257 }, { 258 .name = "intf_2", .id = INTF_2, 259 .base = 0x6b000, .len = 0x280, 260 .type = INTF_DSI, 261 .controller_id = MSM_DSI_CONTROLLER_1, 262 .prog_fetch_lines_worst_case = 21, 263 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28), 264 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29), 265 .intr_tear_rd_ptr = -1, 266 }, { 267 .name = "intf_3", .id = INTF_3, 268 .base = 0x6b800, .len = 0x280, 269 .type = INTF_HDMI, 270 .prog_fetch_lines_worst_case = 21, 271 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30), 272 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31), 273 .intr_tear_rd_ptr = -1, 274 }, 275 }; 276 277 static const struct dpu_perf_cfg msm8998_perf_data = { 278 .max_bw_low = 6700000, 279 .max_bw_high = 6700000, 280 .min_core_ib = 2400000, 281 .min_llcc_ib = 800000, 282 .min_dram_ib = 800000, 283 .undersized_prefill_lines = 2, 284 .xtra_prefill_lines = 2, 285 .dest_scale_prefill_lines = 3, 286 .macrotile_prefill_lines = 4, 287 .yuv_nv12_prefill_lines = 8, 288 .linear_prefill_lines = 1, 289 .downscaling_prefill_lines = 1, 290 .amortizable_threshold = 25, 291 .min_prefill_lines = 25, 292 .danger_lut_tbl = {0xf, 0xffff, 0x0}, 293 .safe_lut_tbl = {0xfffc, 0xff00, 0xffff}, 294 .qos_lut_tbl = { 295 {.nentry = ARRAY_SIZE(msm8998_qos_linear), 296 .entries = msm8998_qos_linear 297 }, 298 {.nentry = ARRAY_SIZE(msm8998_qos_macrotile), 299 .entries = msm8998_qos_macrotile 300 }, 301 {.nentry = ARRAY_SIZE(msm8998_qos_nrt), 302 .entries = msm8998_qos_nrt 303 }, 304 }, 305 .cdp_cfg = { 306 {.rd_enable = 1, .wr_enable = 1}, 307 {.rd_enable = 1, .wr_enable = 0} 308 }, 309 .clk_inefficiency_factor = 200, 310 .bw_inefficiency_factor = 120, 311 }; 312 313 static const struct dpu_mdss_version msm8998_mdss_ver = { 314 .core_major_ver = 3, 315 .core_minor_ver = 0, 316 }; 317 318 const struct dpu_mdss_cfg dpu_msm8998_cfg = { 319 .mdss_ver = &msm8998_mdss_ver, 320 .caps = &msm8998_dpu_caps, 321 .mdp = &msm8998_mdp, 322 .ctl_count = ARRAY_SIZE(msm8998_ctl), 323 .ctl = msm8998_ctl, 324 .sspp_count = ARRAY_SIZE(msm8998_sspp), 325 .sspp = msm8998_sspp, 326 .mixer_count = ARRAY_SIZE(msm8998_lm), 327 .mixer = msm8998_lm, 328 .dspp_count = ARRAY_SIZE(msm8998_dspp), 329 .dspp = msm8998_dspp, 330 .pingpong_count = ARRAY_SIZE(msm8998_pp), 331 .pingpong = msm8998_pp, 332 .dsc_count = ARRAY_SIZE(msm8998_dsc), 333 .dsc = msm8998_dsc, 334 .intf_count = ARRAY_SIZE(msm8998_intf), 335 .intf = msm8998_intf, 336 .vbif_count = ARRAY_SIZE(msm8998_vbif), 337 .vbif = msm8998_vbif, 338 .perf = &msm8998_perf_data, 339 }; 340 341 #endif 342