1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Qualcomm Ramp Controller driver
4  * Copyright (c) 2022, AngeloGioacchino Del Regno
5  *                     <angelogioacchino.delregno@collabora.com>
6  */
7 
8 #include <linux/bitfield.h>
9 #include <linux/kernel.h>
10 #include <linux/module.h>
11 #include <linux/of.h>
12 #include <linux/of_platform.h>
13 #include <linux/platform_device.h>
14 #include <linux/regmap.h>
15 #include <linux/types.h>
16 
17 #define RC_UPDATE_EN		BIT(0)
18 #define RC_ROOT_EN		BIT(1)
19 
20 #define RC_REG_CFG_UPDATE	0x60
21 #define RC_CFG_UPDATE_EN	BIT(8)
22 #define RC_CFG_ACK		GENMASK(31, 16)
23 
24 #define RC_DCVS_CFG_SID		2
25 #define RC_LINK_SID		3
26 #define RC_LMH_SID		6
27 #define RC_DFS_SID		14
28 
29 #define RC_UPDATE_TIMEOUT_US	500
30 
31 /**
32  * struct qcom_ramp_controller_desc - SoC specific parameters
33  * @cfg_dfs_sid:      Dynamic Frequency Scaling SID configuration
34  * @cfg_link_sid:     Link SID configuration
35  * @cfg_lmh_sid:      Limits Management hardware SID configuration
36  * @cfg_ramp_en:      Ramp Controller enable sequence
37  * @cfg_ramp_dis:     Ramp Controller disable sequence
38  * @cmd_reg:          Command register offset
39  * @num_dfs_sids:     Number of DFS SIDs (max 8)
40  * @num_link_sids:    Number of Link SIDs (max 3)
41  * @num_lmh_sids:     Number of LMh SIDs (max 8)
42  * @num_ramp_en:      Number of entries in enable sequence
43  * @num_ramp_dis:     Number of entries in disable sequence
44  */
45 struct qcom_ramp_controller_desc {
46 	const struct reg_sequence *cfg_dfs_sid;
47 	const struct reg_sequence *cfg_link_sid;
48 	const struct reg_sequence *cfg_lmh_sid;
49 	const struct reg_sequence *cfg_ramp_en;
50 	const struct reg_sequence *cfg_ramp_dis;
51 	u8 cmd_reg;
52 	u8 num_dfs_sids;
53 	u8 num_link_sids;
54 	u8 num_lmh_sids;
55 	u8 num_ramp_en;
56 	u8 num_ramp_dis;
57 };
58 
59 /**
60  * struct qcom_ramp_controller - Main driver structure
61  * @regmap: Regmap handle
62  * @desc:   SoC specific parameters
63  */
64 struct qcom_ramp_controller {
65 	struct regmap *regmap;
66 	const struct qcom_ramp_controller_desc *desc;
67 };
68 
69 /**
70  * rc_wait_for_update() - Wait for Ramp Controller root update
71  * @qrc: Main driver structure
72  *
73  * Return: Zero for success or negative number for failure
74  */
rc_wait_for_update(struct qcom_ramp_controller * qrc)75 static int rc_wait_for_update(struct qcom_ramp_controller *qrc)
76 {
77 	const struct qcom_ramp_controller_desc *d = qrc->desc;
78 	struct regmap *r = qrc->regmap;
79 	u32 val;
80 	int ret;
81 
82 	ret = regmap_set_bits(r, d->cmd_reg, RC_ROOT_EN);
83 	if (ret)
84 		return ret;
85 
86 	return regmap_read_poll_timeout(r, d->cmd_reg, val, !(val & RC_UPDATE_EN),
87 					1, RC_UPDATE_TIMEOUT_US);
88 }
89 
90 /**
91  * rc_set_cfg_update() - Ramp Controller configuration update
92  * @qrc: Main driver structure
93  * @ce: Configuration entry to update
94  *
95  * Return: Zero for success or negative number for failure
96  */
rc_set_cfg_update(struct qcom_ramp_controller * qrc,u8 ce)97 static int rc_set_cfg_update(struct qcom_ramp_controller *qrc, u8 ce)
98 {
99 	const struct qcom_ramp_controller_desc *d = qrc->desc;
100 	struct regmap *r = qrc->regmap;
101 	u32 ack, val;
102 	int ret;
103 
104 	/* The ack bit is between bits 16-31 of RC_REG_CFG_UPDATE */
105 	ack = FIELD_PREP(RC_CFG_ACK, BIT(ce));
106 
107 	/* Write the configuration type first... */
108 	ret = regmap_set_bits(r, d->cmd_reg + RC_REG_CFG_UPDATE, ce);
109 	if (ret)
110 		return ret;
111 
112 	/* ...and after that, enable the update bit to sync the changes */
113 	ret = regmap_set_bits(r, d->cmd_reg + RC_REG_CFG_UPDATE, RC_CFG_UPDATE_EN);
114 	if (ret)
115 		return ret;
116 
117 	/* Wait for the changes to go through */
118 	ret = regmap_read_poll_timeout(r, d->cmd_reg + RC_REG_CFG_UPDATE, val,
119 				       val & ack, 1, RC_UPDATE_TIMEOUT_US);
120 	if (ret)
121 		return ret;
122 
123 	/*
124 	 * Configuration update success! The CFG_UPDATE register will not be
125 	 * cleared automatically upon applying the configuration, so we have
126 	 * to do that manually in order to leave the ramp controller in a
127 	 * predictable and clean state.
128 	 */
129 	ret = regmap_write(r, d->cmd_reg + RC_REG_CFG_UPDATE, 0);
130 	if (ret)
131 		return ret;
132 
133 	/* Wait for the update bit cleared ack */
134 	return regmap_read_poll_timeout(r, d->cmd_reg + RC_REG_CFG_UPDATE,
135 					val, !(val & RC_CFG_ACK), 1,
136 					RC_UPDATE_TIMEOUT_US);
137 }
138 
139 /**
140  * rc_write_cfg - Send configuration sequence
141  * @qrc: Main driver structure
142  * @seq: Register sequence to send before asking for update
143  * @ce: Configuration SID
144  * @nsids: Total number of SIDs
145  *
146  * Returns: Zero for success or negative number for error
147  */
rc_write_cfg(struct qcom_ramp_controller * qrc,const struct reg_sequence * seq,u16 ce,u8 nsids)148 static int rc_write_cfg(struct qcom_ramp_controller *qrc,
149 			const struct reg_sequence *seq,
150 			u16 ce, u8 nsids)
151 {
152 	int ret;
153 	u8 i;
154 
155 	/* Check if, and wait until the ramp controller is ready */
156 	ret = rc_wait_for_update(qrc);
157 	if (ret)
158 		return ret;
159 
160 	/* Write the sequence */
161 	ret = regmap_multi_reg_write(qrc->regmap, seq, nsids);
162 	if (ret)
163 		return ret;
164 
165 	/* Pull the trigger: do config update starting from the last sid */
166 	for (i = 0; i < nsids; i++) {
167 		ret = rc_set_cfg_update(qrc, (u8)ce - i);
168 		if (ret)
169 			return ret;
170 	}
171 
172 	return 0;
173 }
174 
175 /**
176  * rc_ramp_ctrl_enable() - Enable Ramp up/down Control
177  * @qrc: Main driver structure
178  *
179  * Return: Zero for success or negative number for error
180  */
rc_ramp_ctrl_enable(struct qcom_ramp_controller * qrc)181 static int rc_ramp_ctrl_enable(struct qcom_ramp_controller *qrc)
182 {
183 	const struct qcom_ramp_controller_desc *d = qrc->desc;
184 	int i, ret;
185 
186 	for (i = 0; i < d->num_ramp_en; i++) {
187 		ret = rc_write_cfg(qrc, &d->cfg_ramp_en[i], RC_DCVS_CFG_SID, 1);
188 		if (ret)
189 			return ret;
190 	}
191 
192 	return 0;
193 }
194 
195 /**
196  * qcom_ramp_controller_start() - Initialize and start the ramp controller
197  * @qrc: Main driver structure
198  *
199  * The Ramp Controller needs to be initialized by programming the relevant
200  * registers with SoC-specific configuration: once programming is done,
201  * the hardware will take care of the rest (no further handling required).
202  *
203  * Return: Zero for success or negative number for error
204  */
qcom_ramp_controller_start(struct qcom_ramp_controller * qrc)205 static int qcom_ramp_controller_start(struct qcom_ramp_controller *qrc)
206 {
207 	const struct qcom_ramp_controller_desc *d = qrc->desc;
208 	int ret;
209 
210 	/* Program LMH, DFS, Link SIDs */
211 	ret = rc_write_cfg(qrc, d->cfg_lmh_sid, RC_LMH_SID, d->num_lmh_sids);
212 	if (ret)
213 		return ret;
214 
215 	ret = rc_write_cfg(qrc, d->cfg_dfs_sid, RC_DFS_SID, d->num_dfs_sids);
216 	if (ret)
217 		return ret;
218 
219 	ret = rc_write_cfg(qrc, d->cfg_link_sid, RC_LINK_SID, d->num_link_sids);
220 	if (ret)
221 		return ret;
222 
223 	/* Everything is ready! Enable the ramp up/down control */
224 	return rc_ramp_ctrl_enable(qrc);
225 }
226 
227 static const struct regmap_config qrc_regmap_config = {
228 	.reg_bits = 32,
229 	.reg_stride = 4,
230 	.val_bits = 32,
231 	.max_register =	0x68,
232 	.fast_io = true,
233 };
234 
235 static const struct reg_sequence msm8976_cfg_dfs_sid[] = {
236 	{ 0x10, 0xfefebff7 },
237 	{ 0x14, 0xfdff7fef },
238 	{ 0x18, 0xfbffdefb },
239 	{ 0x1c, 0xb69b5555 },
240 	{ 0x20, 0x24929249 },
241 	{ 0x24, 0x49241112 },
242 	{ 0x28, 0x11112111 },
243 	{ 0x2c, 0x8102 }
244 };
245 
246 static const struct reg_sequence msm8976_cfg_link_sid[] = {
247 	{ 0x40, 0xfc987 }
248 };
249 
250 static const struct reg_sequence msm8976_cfg_lmh_sid[] = {
251 	{ 0x30, 0x77706db },
252 	{ 0x34, 0x5550249 },
253 	{ 0x38, 0x111 }
254 };
255 
256 static const struct reg_sequence msm8976_cfg_ramp_en[] = {
257 	{ 0x50, 0x800 }, /* pre_en */
258 	{ 0x50, 0xc00 }, /* en */
259 	{ 0x50, 0x400 }  /* post_en */
260 };
261 
262 static const struct reg_sequence msm8976_cfg_ramp_dis[] = {
263 	{ 0x50, 0x0 }
264 };
265 
266 static const struct qcom_ramp_controller_desc msm8976_rc_cfg = {
267 	.cfg_dfs_sid = msm8976_cfg_dfs_sid,
268 	.num_dfs_sids = ARRAY_SIZE(msm8976_cfg_dfs_sid),
269 
270 	.cfg_link_sid = msm8976_cfg_link_sid,
271 	.num_link_sids = ARRAY_SIZE(msm8976_cfg_link_sid),
272 
273 	.cfg_lmh_sid = msm8976_cfg_lmh_sid,
274 	.num_lmh_sids = ARRAY_SIZE(msm8976_cfg_lmh_sid),
275 
276 	.cfg_ramp_en = msm8976_cfg_ramp_en,
277 	.num_ramp_en = ARRAY_SIZE(msm8976_cfg_ramp_en),
278 
279 	.cfg_ramp_dis = msm8976_cfg_ramp_dis,
280 	.num_ramp_dis = ARRAY_SIZE(msm8976_cfg_ramp_dis),
281 
282 	.cmd_reg = 0x0,
283 };
284 
qcom_ramp_controller_probe(struct platform_device * pdev)285 static int qcom_ramp_controller_probe(struct platform_device *pdev)
286 {
287 	struct qcom_ramp_controller *qrc;
288 	void __iomem *base;
289 
290 	base = devm_platform_ioremap_resource(pdev, 0);
291 	if (IS_ERR(base))
292 		return PTR_ERR(base);
293 
294 	qrc = devm_kmalloc(&pdev->dev, sizeof(*qrc), GFP_KERNEL);
295 	if (!qrc)
296 		return -ENOMEM;
297 
298 	qrc->desc = device_get_match_data(&pdev->dev);
299 	if (!qrc->desc)
300 		return -EINVAL;
301 
302 	qrc->regmap = devm_regmap_init_mmio(&pdev->dev, base, &qrc_regmap_config);
303 	if (IS_ERR(qrc->regmap))
304 		return PTR_ERR(qrc->regmap);
305 
306 	platform_set_drvdata(pdev, qrc);
307 
308 	return qcom_ramp_controller_start(qrc);
309 }
310 
qcom_ramp_controller_remove(struct platform_device * pdev)311 static void qcom_ramp_controller_remove(struct platform_device *pdev)
312 {
313 	struct qcom_ramp_controller *qrc = platform_get_drvdata(pdev);
314 	int ret;
315 
316 	ret = rc_write_cfg(qrc, qrc->desc->cfg_ramp_dis,
317 			   RC_DCVS_CFG_SID, qrc->desc->num_ramp_dis);
318 	if (ret)
319 		dev_err(&pdev->dev, "Failed to send disable sequence\n");
320 }
321 
322 static const struct of_device_id qcom_ramp_controller_match_table[] = {
323 	{ .compatible = "qcom,msm8976-ramp-controller", .data = &msm8976_rc_cfg },
324 	{ /* sentinel */ }
325 };
326 MODULE_DEVICE_TABLE(of, qcom_ramp_controller_match_table);
327 
328 static struct platform_driver qcom_ramp_controller_driver = {
329 	.driver = {
330 		.name = "qcom-ramp-controller",
331 		.of_match_table = qcom_ramp_controller_match_table,
332 		.suppress_bind_attrs = true,
333 	},
334 	.probe  = qcom_ramp_controller_probe,
335 	.remove_new = qcom_ramp_controller_remove,
336 };
337 
qcom_ramp_controller_init(void)338 static int __init qcom_ramp_controller_init(void)
339 {
340 	return platform_driver_register(&qcom_ramp_controller_driver);
341 }
342 arch_initcall(qcom_ramp_controller_init);
343 
344 MODULE_AUTHOR("AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>");
345 MODULE_DESCRIPTION("Qualcomm Ramp Controller driver");
346 MODULE_LICENSE("GPL");
347