1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * HyperV Detection code.
4 *
5 * Copyright (C) 2010, Novell, Inc.
6 * Author : K. Y. Srinivasan <ksrinivasan@novell.com>
7 */
8
9 #include <linux/types.h>
10 #include <linux/time.h>
11 #include <linux/clocksource.h>
12 #include <linux/init.h>
13 #include <linux/export.h>
14 #include <linux/hardirq.h>
15 #include <linux/efi.h>
16 #include <linux/interrupt.h>
17 #include <linux/irq.h>
18 #include <linux/kexec.h>
19 #include <linux/i8253.h>
20 #include <linux/random.h>
21 #include <asm/processor.h>
22 #include <asm/hypervisor.h>
23 #include <asm/hyperv-tlfs.h>
24 #include <asm/mshyperv.h>
25 #include <asm/desc.h>
26 #include <asm/idtentry.h>
27 #include <asm/irq_regs.h>
28 #include <asm/i8259.h>
29 #include <asm/apic.h>
30 #include <asm/timer.h>
31 #include <asm/reboot.h>
32 #include <asm/nmi.h>
33 #include <clocksource/hyperv_timer.h>
34 #include <asm/numa.h>
35 #include <asm/svm.h>
36
37 /* Is Linux running as the root partition? */
38 bool hv_root_partition;
39 /* Is Linux running on nested Microsoft Hypervisor */
40 bool hv_nested;
41 struct ms_hyperv_info ms_hyperv;
42
43 /* Used in modules via hv_do_hypercall(): see arch/x86/include/asm/mshyperv.h */
44 bool hyperv_paravisor_present __ro_after_init;
45 EXPORT_SYMBOL_GPL(hyperv_paravisor_present);
46
47 #if IS_ENABLED(CONFIG_HYPERV)
hv_get_nested_reg(unsigned int reg)48 static inline unsigned int hv_get_nested_reg(unsigned int reg)
49 {
50 if (hv_is_sint_reg(reg))
51 return reg - HV_REGISTER_SINT0 + HV_REGISTER_NESTED_SINT0;
52
53 switch (reg) {
54 case HV_REGISTER_SIMP:
55 return HV_REGISTER_NESTED_SIMP;
56 case HV_REGISTER_SIEFP:
57 return HV_REGISTER_NESTED_SIEFP;
58 case HV_REGISTER_SVERSION:
59 return HV_REGISTER_NESTED_SVERSION;
60 case HV_REGISTER_SCONTROL:
61 return HV_REGISTER_NESTED_SCONTROL;
62 case HV_REGISTER_EOM:
63 return HV_REGISTER_NESTED_EOM;
64 default:
65 return reg;
66 }
67 }
68
hv_get_non_nested_register(unsigned int reg)69 u64 hv_get_non_nested_register(unsigned int reg)
70 {
71 u64 value;
72
73 if (hv_is_synic_reg(reg) && ms_hyperv.paravisor_present)
74 hv_ivm_msr_read(reg, &value);
75 else
76 rdmsrl(reg, value);
77 return value;
78 }
79 EXPORT_SYMBOL_GPL(hv_get_non_nested_register);
80
hv_set_non_nested_register(unsigned int reg,u64 value)81 void hv_set_non_nested_register(unsigned int reg, u64 value)
82 {
83 if (hv_is_synic_reg(reg) && ms_hyperv.paravisor_present) {
84 hv_ivm_msr_write(reg, value);
85
86 /* Write proxy bit via wrmsl instruction */
87 if (hv_is_sint_reg(reg))
88 wrmsrl(reg, value | 1 << 20);
89 } else {
90 wrmsrl(reg, value);
91 }
92 }
93 EXPORT_SYMBOL_GPL(hv_set_non_nested_register);
94
hv_get_register(unsigned int reg)95 u64 hv_get_register(unsigned int reg)
96 {
97 if (hv_nested)
98 reg = hv_get_nested_reg(reg);
99
100 return hv_get_non_nested_register(reg);
101 }
102 EXPORT_SYMBOL_GPL(hv_get_register);
103
hv_set_register(unsigned int reg,u64 value)104 void hv_set_register(unsigned int reg, u64 value)
105 {
106 if (hv_nested)
107 reg = hv_get_nested_reg(reg);
108
109 hv_set_non_nested_register(reg, value);
110 }
111 EXPORT_SYMBOL_GPL(hv_set_register);
112
113 static void (*vmbus_handler)(void);
114 static void (*hv_stimer0_handler)(void);
115 static void (*hv_kexec_handler)(void);
116 static void (*hv_crash_handler)(struct pt_regs *regs);
117
DEFINE_IDTENTRY_SYSVEC(sysvec_hyperv_callback)118 DEFINE_IDTENTRY_SYSVEC(sysvec_hyperv_callback)
119 {
120 struct pt_regs *old_regs = set_irq_regs(regs);
121
122 inc_irq_stat(irq_hv_callback_count);
123 if (vmbus_handler)
124 vmbus_handler();
125
126 if (ms_hyperv.hints & HV_DEPRECATING_AEOI_RECOMMENDED)
127 apic_eoi();
128
129 set_irq_regs(old_regs);
130 }
131
hv_setup_vmbus_handler(void (* handler)(void))132 void hv_setup_vmbus_handler(void (*handler)(void))
133 {
134 vmbus_handler = handler;
135 }
136
hv_remove_vmbus_handler(void)137 void hv_remove_vmbus_handler(void)
138 {
139 /* We have no way to deallocate the interrupt gate */
140 vmbus_handler = NULL;
141 }
142
143 /*
144 * Routines to do per-architecture handling of stimer0
145 * interrupts when in Direct Mode
146 */
DEFINE_IDTENTRY_SYSVEC(sysvec_hyperv_stimer0)147 DEFINE_IDTENTRY_SYSVEC(sysvec_hyperv_stimer0)
148 {
149 struct pt_regs *old_regs = set_irq_regs(regs);
150
151 inc_irq_stat(hyperv_stimer0_count);
152 if (hv_stimer0_handler)
153 hv_stimer0_handler();
154 add_interrupt_randomness(HYPERV_STIMER0_VECTOR);
155 apic_eoi();
156
157 set_irq_regs(old_regs);
158 }
159
160 /* For x86/x64, override weak placeholders in hyperv_timer.c */
hv_setup_stimer0_handler(void (* handler)(void))161 void hv_setup_stimer0_handler(void (*handler)(void))
162 {
163 hv_stimer0_handler = handler;
164 }
165
hv_remove_stimer0_handler(void)166 void hv_remove_stimer0_handler(void)
167 {
168 /* We have no way to deallocate the interrupt gate */
169 hv_stimer0_handler = NULL;
170 }
171
hv_setup_kexec_handler(void (* handler)(void))172 void hv_setup_kexec_handler(void (*handler)(void))
173 {
174 hv_kexec_handler = handler;
175 }
176
hv_remove_kexec_handler(void)177 void hv_remove_kexec_handler(void)
178 {
179 hv_kexec_handler = NULL;
180 }
181
hv_setup_crash_handler(void (* handler)(struct pt_regs * regs))182 void hv_setup_crash_handler(void (*handler)(struct pt_regs *regs))
183 {
184 hv_crash_handler = handler;
185 }
186
hv_remove_crash_handler(void)187 void hv_remove_crash_handler(void)
188 {
189 hv_crash_handler = NULL;
190 }
191
192 #ifdef CONFIG_KEXEC_CORE
hv_machine_shutdown(void)193 static void hv_machine_shutdown(void)
194 {
195 if (kexec_in_progress && hv_kexec_handler)
196 hv_kexec_handler();
197
198 /*
199 * Call hv_cpu_die() on all the CPUs, otherwise later the hypervisor
200 * corrupts the old VP Assist Pages and can crash the kexec kernel.
201 */
202 if (kexec_in_progress)
203 cpuhp_remove_state(CPUHP_AP_HYPERV_ONLINE);
204
205 /* The function calls stop_other_cpus(). */
206 native_machine_shutdown();
207
208 /* Disable the hypercall page when there is only 1 active CPU. */
209 if (kexec_in_progress)
210 hyperv_cleanup();
211 }
212
hv_machine_crash_shutdown(struct pt_regs * regs)213 static void hv_machine_crash_shutdown(struct pt_regs *regs)
214 {
215 if (hv_crash_handler)
216 hv_crash_handler(regs);
217
218 /* The function calls crash_smp_send_stop(). */
219 native_machine_crash_shutdown(regs);
220
221 /* Disable the hypercall page when there is only 1 active CPU. */
222 hyperv_cleanup();
223 }
224 #endif /* CONFIG_KEXEC_CORE */
225
226 static u64 hv_ref_counter_at_suspend;
227 static void (*old_save_sched_clock_state)(void);
228 static void (*old_restore_sched_clock_state)(void);
229
230 /*
231 * Hyper-V clock counter resets during hibernation. Save and restore clock
232 * offset during suspend/resume, while also considering the time passed
233 * before suspend. This is to make sure that sched_clock using hv tsc page
234 * based clocksource, proceeds from where it left off during suspend and
235 * it shows correct time for the timestamps of kernel messages after resume.
236 */
save_hv_clock_tsc_state(void)237 static void save_hv_clock_tsc_state(void)
238 {
239 hv_ref_counter_at_suspend = hv_read_reference_counter();
240 }
241
restore_hv_clock_tsc_state(void)242 static void restore_hv_clock_tsc_state(void)
243 {
244 /*
245 * Adjust the offsets used by hv tsc clocksource to
246 * account for the time spent before hibernation.
247 * adjusted value = reference counter (time) at suspend
248 * - reference counter (time) now.
249 */
250 hv_adj_sched_clock_offset(hv_ref_counter_at_suspend - hv_read_reference_counter());
251 }
252
253 /*
254 * Functions to override save_sched_clock_state and restore_sched_clock_state
255 * functions of x86_platform. The Hyper-V clock counter is reset during
256 * suspend-resume and the offset used to measure time needs to be
257 * corrected, post resume.
258 */
hv_save_sched_clock_state(void)259 static void hv_save_sched_clock_state(void)
260 {
261 old_save_sched_clock_state();
262 save_hv_clock_tsc_state();
263 }
264
hv_restore_sched_clock_state(void)265 static void hv_restore_sched_clock_state(void)
266 {
267 restore_hv_clock_tsc_state();
268 old_restore_sched_clock_state();
269 }
270
x86_setup_ops_for_tsc_pg_clock(void)271 static void __init x86_setup_ops_for_tsc_pg_clock(void)
272 {
273 if (!(ms_hyperv.features & HV_MSR_REFERENCE_TSC_AVAILABLE))
274 return;
275
276 old_save_sched_clock_state = x86_platform.save_sched_clock_state;
277 x86_platform.save_sched_clock_state = hv_save_sched_clock_state;
278
279 old_restore_sched_clock_state = x86_platform.restore_sched_clock_state;
280 x86_platform.restore_sched_clock_state = hv_restore_sched_clock_state;
281 }
282 #endif /* CONFIG_HYPERV */
283
ms_hyperv_platform(void)284 static uint32_t __init ms_hyperv_platform(void)
285 {
286 u32 eax;
287 u32 hyp_signature[3];
288
289 if (!boot_cpu_has(X86_FEATURE_HYPERVISOR))
290 return 0;
291
292 cpuid(HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS,
293 &eax, &hyp_signature[0], &hyp_signature[1], &hyp_signature[2]);
294
295 if (eax < HYPERV_CPUID_MIN || eax > HYPERV_CPUID_MAX ||
296 memcmp("Microsoft Hv", hyp_signature, 12))
297 return 0;
298
299 /* HYPERCALL and VP_INDEX MSRs are mandatory for all features. */
300 eax = cpuid_eax(HYPERV_CPUID_FEATURES);
301 if (!(eax & HV_MSR_HYPERCALL_AVAILABLE)) {
302 pr_warn("x86/hyperv: HYPERCALL MSR not available.\n");
303 return 0;
304 }
305 if (!(eax & HV_MSR_VP_INDEX_AVAILABLE)) {
306 pr_warn("x86/hyperv: VP_INDEX MSR not available.\n");
307 return 0;
308 }
309
310 return HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS;
311 }
312
313 #ifdef CONFIG_X86_LOCAL_APIC
314 /*
315 * Prior to WS2016 Debug-VM sends NMIs to all CPUs which makes
316 * it difficult to process CHANNELMSG_UNLOAD in case of crash. Handle
317 * unknown NMI on the first CPU which gets it.
318 */
hv_nmi_unknown(unsigned int val,struct pt_regs * regs)319 static int hv_nmi_unknown(unsigned int val, struct pt_regs *regs)
320 {
321 static atomic_t nmi_cpu = ATOMIC_INIT(-1);
322
323 if (!unknown_nmi_panic)
324 return NMI_DONE;
325
326 if (atomic_cmpxchg(&nmi_cpu, -1, raw_smp_processor_id()) != -1)
327 return NMI_HANDLED;
328
329 return NMI_DONE;
330 }
331 #endif
332
hv_get_tsc_khz(void)333 static unsigned long hv_get_tsc_khz(void)
334 {
335 unsigned long freq;
336
337 rdmsrl(HV_X64_MSR_TSC_FREQUENCY, freq);
338
339 return freq / 1000;
340 }
341
342 #if defined(CONFIG_SMP) && IS_ENABLED(CONFIG_HYPERV)
hv_smp_prepare_boot_cpu(void)343 static void __init hv_smp_prepare_boot_cpu(void)
344 {
345 native_smp_prepare_boot_cpu();
346 #if defined(CONFIG_X86_64) && defined(CONFIG_PARAVIRT_SPINLOCKS)
347 hv_init_spinlocks();
348 #endif
349 }
350
hv_smp_prepare_cpus(unsigned int max_cpus)351 static void __init hv_smp_prepare_cpus(unsigned int max_cpus)
352 {
353 #ifdef CONFIG_X86_64
354 int i;
355 int ret;
356 #endif
357
358 native_smp_prepare_cpus(max_cpus);
359
360 /*
361 * Override wakeup_secondary_cpu_64 callback for SEV-SNP
362 * enlightened guest.
363 */
364 if (!ms_hyperv.paravisor_present && hv_isolation_type_snp()) {
365 apic->wakeup_secondary_cpu_64 = hv_snp_boot_ap;
366 return;
367 }
368
369 #ifdef CONFIG_X86_64
370 for_each_present_cpu(i) {
371 if (i == 0)
372 continue;
373 ret = hv_call_add_logical_proc(numa_cpu_node(i), i, cpu_physical_id(i));
374 BUG_ON(ret);
375 }
376
377 for_each_present_cpu(i) {
378 if (i == 0)
379 continue;
380 ret = hv_call_create_vp(numa_cpu_node(i), hv_current_partition_id, i, i);
381 BUG_ON(ret);
382 }
383 #endif
384 }
385 #endif
386
387 /*
388 * When a fully enlightened TDX VM runs on Hyper-V, the firmware sets the
389 * HW_REDUCED flag: refer to acpi_tb_create_local_fadt(). Consequently ttyS0
390 * interrupts can't work because request_irq() -> ... -> irq_to_desc() returns
391 * NULL for ttyS0. This happens because mp_config_acpi_legacy_irqs() sees a
392 * nr_legacy_irqs() of 0, so it doesn't initialize the array 'mp_irqs[]', and
393 * later setup_IO_APIC_irqs() -> find_irq_entry() fails to find the legacy irqs
394 * from the array and hence doesn't create the necessary irq description info.
395 *
396 * Clone arch/x86/kernel/acpi/boot.c: acpi_generic_reduced_hw_init() here,
397 * except don't change 'legacy_pic', which keeps its default value
398 * 'default_legacy_pic'. This way, mp_config_acpi_legacy_irqs() sees a non-zero
399 * nr_legacy_irqs() and eventually serial console interrupts works properly.
400 */
reduced_hw_init(void)401 static void __init reduced_hw_init(void)
402 {
403 x86_init.timers.timer_init = x86_init_noop;
404 x86_init.irqs.pre_vector_init = x86_init_noop;
405 }
406
ms_hyperv_init_platform(void)407 static void __init ms_hyperv_init_platform(void)
408 {
409 int hv_max_functions_eax;
410 int hv_host_info_eax;
411 int hv_host_info_ebx;
412 int hv_host_info_ecx;
413 int hv_host_info_edx;
414
415 #ifdef CONFIG_PARAVIRT
416 pv_info.name = "Hyper-V";
417 #endif
418
419 /*
420 * Extract the features and hints
421 */
422 ms_hyperv.features = cpuid_eax(HYPERV_CPUID_FEATURES);
423 ms_hyperv.priv_high = cpuid_ebx(HYPERV_CPUID_FEATURES);
424 ms_hyperv.misc_features = cpuid_edx(HYPERV_CPUID_FEATURES);
425 ms_hyperv.hints = cpuid_eax(HYPERV_CPUID_ENLIGHTMENT_INFO);
426
427 hv_max_functions_eax = cpuid_eax(HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS);
428
429 pr_info("Hyper-V: privilege flags low 0x%x, high 0x%x, hints 0x%x, misc 0x%x\n",
430 ms_hyperv.features, ms_hyperv.priv_high, ms_hyperv.hints,
431 ms_hyperv.misc_features);
432
433 ms_hyperv.max_vp_index = cpuid_eax(HYPERV_CPUID_IMPLEMENT_LIMITS);
434 ms_hyperv.max_lp_index = cpuid_ebx(HYPERV_CPUID_IMPLEMENT_LIMITS);
435
436 pr_debug("Hyper-V: max %u virtual processors, %u logical processors\n",
437 ms_hyperv.max_vp_index, ms_hyperv.max_lp_index);
438
439 /*
440 * Check CPU management privilege.
441 *
442 * To mirror what Windows does we should extract CPU management
443 * features and use the ReservedIdentityBit to detect if Linux is the
444 * root partition. But that requires negotiating CPU management
445 * interface (a process to be finalized). For now, use the privilege
446 * flag as the indicator for running as root.
447 *
448 * Hyper-V should never specify running as root and as a Confidential
449 * VM. But to protect against a compromised/malicious Hyper-V trying
450 * to exploit root behavior to expose Confidential VM memory, ignore
451 * the root partition setting if also a Confidential VM.
452 */
453 if ((ms_hyperv.priv_high & HV_CPU_MANAGEMENT) &&
454 !(ms_hyperv.priv_high & HV_ISOLATION)) {
455 hv_root_partition = true;
456 pr_info("Hyper-V: running as root partition\n");
457 }
458
459 if (ms_hyperv.hints & HV_X64_HYPERV_NESTED) {
460 hv_nested = true;
461 pr_info("Hyper-V: running on a nested hypervisor\n");
462 }
463
464 /*
465 * Extract host information.
466 */
467 if (hv_max_functions_eax >= HYPERV_CPUID_VERSION) {
468 hv_host_info_eax = cpuid_eax(HYPERV_CPUID_VERSION);
469 hv_host_info_ebx = cpuid_ebx(HYPERV_CPUID_VERSION);
470 hv_host_info_ecx = cpuid_ecx(HYPERV_CPUID_VERSION);
471 hv_host_info_edx = cpuid_edx(HYPERV_CPUID_VERSION);
472
473 pr_info("Hyper-V: Host Build %d.%d.%d.%d-%d-%d\n",
474 hv_host_info_ebx >> 16, hv_host_info_ebx & 0xFFFF,
475 hv_host_info_eax, hv_host_info_edx & 0xFFFFFF,
476 hv_host_info_ecx, hv_host_info_edx >> 24);
477 }
478
479 if (ms_hyperv.features & HV_ACCESS_FREQUENCY_MSRS &&
480 ms_hyperv.misc_features & HV_FEATURE_FREQUENCY_MSRS_AVAILABLE) {
481 x86_platform.calibrate_tsc = hv_get_tsc_khz;
482 x86_platform.calibrate_cpu = hv_get_tsc_khz;
483 setup_force_cpu_cap(X86_FEATURE_TSC_KNOWN_FREQ);
484 }
485
486 if (ms_hyperv.priv_high & HV_ISOLATION) {
487 ms_hyperv.isolation_config_a = cpuid_eax(HYPERV_CPUID_ISOLATION_CONFIG);
488 ms_hyperv.isolation_config_b = cpuid_ebx(HYPERV_CPUID_ISOLATION_CONFIG);
489
490 if (ms_hyperv.shared_gpa_boundary_active)
491 ms_hyperv.shared_gpa_boundary =
492 BIT_ULL(ms_hyperv.shared_gpa_boundary_bits);
493
494 hyperv_paravisor_present = !!ms_hyperv.paravisor_present;
495
496 pr_info("Hyper-V: Isolation Config: Group A 0x%x, Group B 0x%x\n",
497 ms_hyperv.isolation_config_a, ms_hyperv.isolation_config_b);
498
499
500 if (hv_get_isolation_type() == HV_ISOLATION_TYPE_SNP) {
501 static_branch_enable(&isolation_type_snp);
502 } else if (hv_get_isolation_type() == HV_ISOLATION_TYPE_TDX) {
503 static_branch_enable(&isolation_type_tdx);
504
505 /* A TDX VM must use x2APIC and doesn't use lazy EOI. */
506 ms_hyperv.hints &= ~HV_X64_APIC_ACCESS_RECOMMENDED;
507
508 if (!ms_hyperv.paravisor_present) {
509 /* To be supported: more work is required. */
510 ms_hyperv.features &= ~HV_MSR_REFERENCE_TSC_AVAILABLE;
511
512 /* HV_REGISTER_CRASH_CTL is unsupported. */
513 ms_hyperv.misc_features &= ~HV_FEATURE_GUEST_CRASH_MSR_AVAILABLE;
514
515 /* Don't trust Hyper-V's TLB-flushing hypercalls. */
516 ms_hyperv.hints &= ~HV_X64_REMOTE_TLB_FLUSH_RECOMMENDED;
517
518 x86_init.acpi.reduced_hw_early_init = reduced_hw_init;
519 }
520 }
521 }
522
523 if (hv_max_functions_eax >= HYPERV_CPUID_NESTED_FEATURES) {
524 ms_hyperv.nested_features =
525 cpuid_eax(HYPERV_CPUID_NESTED_FEATURES);
526 pr_info("Hyper-V: Nested features: 0x%x\n",
527 ms_hyperv.nested_features);
528 }
529
530 #ifdef CONFIG_X86_LOCAL_APIC
531 if (ms_hyperv.features & HV_ACCESS_FREQUENCY_MSRS &&
532 ms_hyperv.misc_features & HV_FEATURE_FREQUENCY_MSRS_AVAILABLE) {
533 /*
534 * Get the APIC frequency.
535 */
536 u64 hv_lapic_frequency;
537
538 rdmsrl(HV_X64_MSR_APIC_FREQUENCY, hv_lapic_frequency);
539 hv_lapic_frequency = div_u64(hv_lapic_frequency, HZ);
540 lapic_timer_period = hv_lapic_frequency;
541 pr_info("Hyper-V: LAPIC Timer Frequency: %#x\n",
542 lapic_timer_period);
543 }
544
545 register_nmi_handler(NMI_UNKNOWN, hv_nmi_unknown, NMI_FLAG_FIRST,
546 "hv_nmi_unknown");
547 #endif
548
549 #ifdef CONFIG_X86_IO_APIC
550 no_timer_check = 1;
551 #endif
552
553 #if IS_ENABLED(CONFIG_HYPERV) && defined(CONFIG_KEXEC_CORE)
554 machine_ops.shutdown = hv_machine_shutdown;
555 machine_ops.crash_shutdown = hv_machine_crash_shutdown;
556 #endif
557 if (ms_hyperv.features & HV_ACCESS_TSC_INVARIANT) {
558 /*
559 * Writing to synthetic MSR 0x40000118 updates/changes the
560 * guest visible CPUIDs. Setting bit 0 of this MSR enables
561 * guests to report invariant TSC feature through CPUID
562 * instruction, CPUID 0x800000007/EDX, bit 8. See code in
563 * early_init_intel() where this bit is examined. The
564 * setting of this MSR bit should happen before init_intel()
565 * is called.
566 */
567 wrmsrl(HV_X64_MSR_TSC_INVARIANT_CONTROL, HV_EXPOSE_INVARIANT_TSC);
568 setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE);
569 }
570
571 /*
572 * Generation 2 instances don't support reading the NMI status from
573 * 0x61 port.
574 */
575 if (efi_enabled(EFI_BOOT))
576 x86_platform.get_nmi_reason = hv_get_nmi_reason;
577
578 /*
579 * Hyper-V VMs have a PIT emulation quirk such that zeroing the
580 * counter register during PIT shutdown restarts the PIT. So it
581 * continues to interrupt @18.2 HZ. Setting i8253_clear_counter
582 * to false tells pit_shutdown() not to zero the counter so that
583 * the PIT really is shutdown. Generation 2 VMs don't have a PIT,
584 * and setting this value has no effect.
585 */
586 i8253_clear_counter_on_shutdown = false;
587
588 #if IS_ENABLED(CONFIG_HYPERV)
589 if ((hv_get_isolation_type() == HV_ISOLATION_TYPE_VBS) ||
590 ms_hyperv.paravisor_present)
591 hv_vtom_init();
592 /*
593 * Setup the hook to get control post apic initialization.
594 */
595 x86_platform.apic_post_init = hyperv_init;
596 hyperv_setup_mmu_ops();
597 /* Setup the IDT for hypervisor callback */
598 alloc_intr_gate(HYPERVISOR_CALLBACK_VECTOR, asm_sysvec_hyperv_callback);
599
600 /* Setup the IDT for reenlightenment notifications */
601 if (ms_hyperv.features & HV_ACCESS_REENLIGHTENMENT) {
602 alloc_intr_gate(HYPERV_REENLIGHTENMENT_VECTOR,
603 asm_sysvec_hyperv_reenlightenment);
604 }
605
606 /* Setup the IDT for stimer0 */
607 if (ms_hyperv.misc_features & HV_STIMER_DIRECT_MODE_AVAILABLE) {
608 alloc_intr_gate(HYPERV_STIMER0_VECTOR,
609 asm_sysvec_hyperv_stimer0);
610 }
611
612 # ifdef CONFIG_SMP
613 smp_ops.smp_prepare_boot_cpu = hv_smp_prepare_boot_cpu;
614 if (hv_root_partition ||
615 (!ms_hyperv.paravisor_present && hv_isolation_type_snp()))
616 smp_ops.smp_prepare_cpus = hv_smp_prepare_cpus;
617 # endif
618
619 /*
620 * Hyper-V doesn't provide irq remapping for IO-APIC. To enable x2apic,
621 * set x2apic destination mode to physical mode when x2apic is available
622 * and Hyper-V IOMMU driver makes sure cpus assigned with IO-APIC irqs
623 * have 8-bit APIC id.
624 */
625 # ifdef CONFIG_X86_X2APIC
626 if (x2apic_supported())
627 x2apic_phys = 1;
628 # endif
629
630 /* Register Hyper-V specific clocksource */
631 hv_init_clocksource();
632 x86_setup_ops_for_tsc_pg_clock();
633 hv_vtl_init_platform();
634 #endif
635 /*
636 * TSC should be marked as unstable only after Hyper-V
637 * clocksource has been initialized. This ensures that the
638 * stability of the sched_clock is not altered.
639 */
640 if (!(ms_hyperv.features & HV_ACCESS_TSC_INVARIANT))
641 mark_tsc_unstable("running on Hyper-V");
642
643 hardlockup_detector_disable();
644 }
645
ms_hyperv_x2apic_available(void)646 static bool __init ms_hyperv_x2apic_available(void)
647 {
648 return x2apic_supported();
649 }
650
651 /*
652 * If ms_hyperv_msi_ext_dest_id() returns true, hyperv_prepare_irq_remapping()
653 * returns -ENODEV and the Hyper-V IOMMU driver is not used; instead, the
654 * generic support of the 15-bit APIC ID is used: see __irq_msi_compose_msg().
655 *
656 * Note: for a VM on Hyper-V, the I/O-APIC is the only device which
657 * (logically) generates MSIs directly to the system APIC irq domain.
658 * There is no HPET, and PCI MSI/MSI-X interrupts are remapped by the
659 * pci-hyperv host bridge.
660 *
661 * Note: for a Hyper-V root partition, this will always return false.
662 * The hypervisor doesn't expose these HYPERV_CPUID_VIRT_STACK_* cpuids by
663 * default, they are implemented as intercepts by the Windows Hyper-V stack.
664 * Even a nested root partition (L2 root) will not get them because the
665 * nested (L1) hypervisor filters them out.
666 */
ms_hyperv_msi_ext_dest_id(void)667 static bool __init ms_hyperv_msi_ext_dest_id(void)
668 {
669 u32 eax;
670
671 eax = cpuid_eax(HYPERV_CPUID_VIRT_STACK_INTERFACE);
672 if (eax != HYPERV_VS_INTERFACE_EAX_SIGNATURE)
673 return false;
674
675 eax = cpuid_eax(HYPERV_CPUID_VIRT_STACK_PROPERTIES);
676 return eax & HYPERV_VS_PROPERTIES_EAX_EXTENDED_IOAPIC_RTE;
677 }
678
679 #ifdef CONFIG_AMD_MEM_ENCRYPT
hv_sev_es_hcall_prepare(struct ghcb * ghcb,struct pt_regs * regs)680 static void hv_sev_es_hcall_prepare(struct ghcb *ghcb, struct pt_regs *regs)
681 {
682 /* RAX and CPL are already in the GHCB */
683 ghcb_set_rcx(ghcb, regs->cx);
684 ghcb_set_rdx(ghcb, regs->dx);
685 ghcb_set_r8(ghcb, regs->r8);
686 }
687
hv_sev_es_hcall_finish(struct ghcb * ghcb,struct pt_regs * regs)688 static bool hv_sev_es_hcall_finish(struct ghcb *ghcb, struct pt_regs *regs)
689 {
690 /* No checking of the return state needed */
691 return true;
692 }
693 #endif
694
695 const __initconst struct hypervisor_x86 x86_hyper_ms_hyperv = {
696 .name = "Microsoft Hyper-V",
697 .detect = ms_hyperv_platform,
698 .type = X86_HYPER_MS_HYPERV,
699 .init.x2apic_available = ms_hyperv_x2apic_available,
700 .init.msi_ext_dest_id = ms_hyperv_msi_ext_dest_id,
701 .init.init_platform = ms_hyperv_init_platform,
702 #ifdef CONFIG_AMD_MEM_ENCRYPT
703 .runtime.sev_es_hcall_prepare = hv_sev_es_hcall_prepare,
704 .runtime.sev_es_hcall_finish = hv_sev_es_hcall_finish,
705 #endif
706 };
707