xref: /openbmc/linux/arch/powerpc/sysdev/mpic_u3msi.c (revision 4545c6a3)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright 2006, Segher Boessenkool, IBM Corporation.
4  * Copyright 2006-2007, Michael Ellerman, IBM Corporation.
5  */
6 
7 #include <linux/irq.h>
8 #include <linux/irqdomain.h>
9 #include <linux/msi.h>
10 #include <asm/mpic.h>
11 #include <asm/hw_irq.h>
12 #include <asm/ppc-pci.h>
13 #include <asm/msi_bitmap.h>
14 
15 #include "mpic.h"
16 
17 /* A bit ugly, can we get this from the pci_dev somehow? */
18 static struct mpic *msi_mpic;
19 
mpic_u3msi_mask_irq(struct irq_data * data)20 static void mpic_u3msi_mask_irq(struct irq_data *data)
21 {
22 	pci_msi_mask_irq(data);
23 	mpic_mask_irq(data);
24 }
25 
mpic_u3msi_unmask_irq(struct irq_data * data)26 static void mpic_u3msi_unmask_irq(struct irq_data *data)
27 {
28 	mpic_unmask_irq(data);
29 	pci_msi_unmask_irq(data);
30 }
31 
32 static struct irq_chip mpic_u3msi_chip = {
33 	.irq_shutdown		= mpic_u3msi_mask_irq,
34 	.irq_mask		= mpic_u3msi_mask_irq,
35 	.irq_unmask		= mpic_u3msi_unmask_irq,
36 	.irq_eoi		= mpic_end_irq,
37 	.irq_set_type		= mpic_set_irq_type,
38 	.irq_set_affinity	= mpic_set_affinity,
39 	.name			= "MPIC-U3MSI",
40 };
41 
read_ht_magic_addr(struct pci_dev * pdev,unsigned int pos)42 static u64 read_ht_magic_addr(struct pci_dev *pdev, unsigned int pos)
43 {
44 	u8 flags;
45 	u32 tmp;
46 	u64 addr;
47 
48 	pci_read_config_byte(pdev, pos + HT_MSI_FLAGS, &flags);
49 
50 	if (flags & HT_MSI_FLAGS_FIXED)
51 		return HT_MSI_FIXED_ADDR;
52 
53 	pci_read_config_dword(pdev, pos + HT_MSI_ADDR_LO, &tmp);
54 	addr = tmp & HT_MSI_ADDR_LO_MASK;
55 	pci_read_config_dword(pdev, pos + HT_MSI_ADDR_HI, &tmp);
56 	addr = addr | ((u64)tmp << 32);
57 
58 	return addr;
59 }
60 
find_ht_magic_addr(struct pci_dev * pdev,unsigned int hwirq)61 static u64 find_ht_magic_addr(struct pci_dev *pdev, unsigned int hwirq)
62 {
63 	struct pci_bus *bus;
64 	unsigned int pos;
65 
66 	for (bus = pdev->bus; bus && bus->self; bus = bus->parent) {
67 		pos = pci_find_ht_capability(bus->self, HT_CAPTYPE_MSI_MAPPING);
68 		if (pos)
69 			return read_ht_magic_addr(bus->self, pos);
70 	}
71 
72 	return 0;
73 }
74 
find_u4_magic_addr(struct pci_dev * pdev,unsigned int hwirq)75 static u64 find_u4_magic_addr(struct pci_dev *pdev, unsigned int hwirq)
76 {
77 	struct pci_controller *hose = pci_bus_to_host(pdev->bus);
78 
79 	/* U4 PCIe MSIs need to write to the special register in
80 	 * the bridge that generates interrupts. There should be
81 	 * theoretically a register at 0xf8005000 where you just write
82 	 * the MSI number and that triggers the right interrupt, but
83 	 * unfortunately, this is busted in HW, the bridge endian swaps
84 	 * the value and hits the wrong nibble in the register.
85 	 *
86 	 * So instead we use another register set which is used normally
87 	 * for converting HT interrupts to MPIC interrupts, which decodes
88 	 * the interrupt number as part of the low address bits
89 	 *
90 	 * This will not work if we ever use more than one legacy MSI in
91 	 * a block but we never do. For one MSI or multiple MSI-X where
92 	 * each interrupt address can be specified separately, it works
93 	 * just fine.
94 	 */
95 	if (of_device_is_compatible(hose->dn, "u4-pcie") ||
96 	    of_device_is_compatible(hose->dn, "U4-pcie"))
97 		return 0xf8004000 | (hwirq << 4);
98 
99 	return 0;
100 }
101 
u3msi_teardown_msi_irqs(struct pci_dev * pdev)102 static void u3msi_teardown_msi_irqs(struct pci_dev *pdev)
103 {
104 	struct msi_desc *entry;
105 	irq_hw_number_t hwirq;
106 
107 	msi_for_each_desc(entry, &pdev->dev, MSI_DESC_ASSOCIATED) {
108 		hwirq = virq_to_hw(entry->irq);
109 		irq_set_msi_desc(entry->irq, NULL);
110 		irq_dispose_mapping(entry->irq);
111 		entry->irq = 0;
112 		msi_bitmap_free_hwirqs(&msi_mpic->msi_bitmap, hwirq, 1);
113 	}
114 }
115 
u3msi_setup_msi_irqs(struct pci_dev * pdev,int nvec,int type)116 static int u3msi_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
117 {
118 	unsigned int virq;
119 	struct msi_desc *entry;
120 	struct msi_msg msg;
121 	u64 addr;
122 	int hwirq;
123 
124 	if (type == PCI_CAP_ID_MSIX)
125 		pr_debug("u3msi: MSI-X untested, trying anyway.\n");
126 
127 	/* If we can't find a magic address then MSI ain't gonna work */
128 	if (find_ht_magic_addr(pdev, 0) == 0 &&
129 	    find_u4_magic_addr(pdev, 0) == 0) {
130 		pr_debug("u3msi: no magic address found for %s\n",
131 			 pci_name(pdev));
132 		return -ENXIO;
133 	}
134 
135 	msi_for_each_desc(entry, &pdev->dev, MSI_DESC_NOTASSOCIATED) {
136 		hwirq = msi_bitmap_alloc_hwirqs(&msi_mpic->msi_bitmap, 1);
137 		if (hwirq < 0) {
138 			pr_debug("u3msi: failed allocating hwirq\n");
139 			return hwirq;
140 		}
141 
142 		addr = find_ht_magic_addr(pdev, hwirq);
143 		if (addr == 0)
144 			addr = find_u4_magic_addr(pdev, hwirq);
145 		msg.address_lo = addr & 0xFFFFFFFF;
146 		msg.address_hi = addr >> 32;
147 
148 		virq = irq_create_mapping(msi_mpic->irqhost, hwirq);
149 		if (!virq) {
150 			pr_debug("u3msi: failed mapping hwirq 0x%x\n", hwirq);
151 			msi_bitmap_free_hwirqs(&msi_mpic->msi_bitmap, hwirq, 1);
152 			return -ENOSPC;
153 		}
154 
155 		irq_set_msi_desc(virq, entry);
156 		irq_set_chip(virq, &mpic_u3msi_chip);
157 		irq_set_irq_type(virq, IRQ_TYPE_EDGE_RISING);
158 
159 		pr_debug("u3msi: allocated virq 0x%x (hw 0x%x) addr 0x%lx\n",
160 			  virq, hwirq, (unsigned long)addr);
161 
162 		printk("u3msi: allocated virq 0x%x (hw 0x%x) addr 0x%lx\n",
163 			  virq, hwirq, (unsigned long)addr);
164 		msg.data = hwirq;
165 		pci_write_msi_msg(virq, &msg);
166 
167 		hwirq++;
168 	}
169 
170 	return 0;
171 }
172 
mpic_u3msi_init(struct mpic * mpic)173 int __init mpic_u3msi_init(struct mpic *mpic)
174 {
175 	int rc;
176 	struct pci_controller *phb;
177 
178 	rc = mpic_msi_init_allocator(mpic);
179 	if (rc) {
180 		pr_debug("u3msi: Error allocating bitmap!\n");
181 		return rc;
182 	}
183 
184 	pr_debug("u3msi: Registering MPIC U3 MSI callbacks.\n");
185 
186 	BUG_ON(msi_mpic);
187 	msi_mpic = mpic;
188 
189 	list_for_each_entry(phb, &hose_list, list_node) {
190 		WARN_ON(phb->controller_ops.setup_msi_irqs);
191 		phb->controller_ops.setup_msi_irqs = u3msi_setup_msi_irqs;
192 		phb->controller_ops.teardown_msi_irqs = u3msi_teardown_msi_irqs;
193 	}
194 
195 	return 0;
196 }
197