1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Driver for Broadcom MPI3 Storage Controllers
4 *
5 * Copyright (C) 2017-2023 Broadcom Inc.
6 * (mailto: mpi3mr-linuxdrv.pdl@broadcom.com)
7 *
8 */
9
10 #include "mpi3mr.h"
11 #include <linux/io-64-nonatomic-lo-hi.h>
12
13 static int
14 mpi3mr_issue_reset(struct mpi3mr_ioc *mrioc, u16 reset_type, u32 reset_reason);
15 static int mpi3mr_setup_admin_qpair(struct mpi3mr_ioc *mrioc);
16 static void mpi3mr_process_factsdata(struct mpi3mr_ioc *mrioc,
17 struct mpi3_ioc_facts_data *facts_data);
18 static void mpi3mr_pel_wait_complete(struct mpi3mr_ioc *mrioc,
19 struct mpi3mr_drv_cmd *drv_cmd);
20
21 static int poll_queues;
22 module_param(poll_queues, int, 0444);
23 MODULE_PARM_DESC(poll_queues, "Number of queues for io_uring poll mode. (Range 1 - 126)");
24
25 #if defined(writeq) && defined(CONFIG_64BIT)
mpi3mr_writeq(__u64 b,volatile void __iomem * addr)26 static inline void mpi3mr_writeq(__u64 b, volatile void __iomem *addr)
27 {
28 writeq(b, addr);
29 }
30 #else
mpi3mr_writeq(__u64 b,volatile void __iomem * addr)31 static inline void mpi3mr_writeq(__u64 b, volatile void __iomem *addr)
32 {
33 __u64 data_out = b;
34
35 writel((u32)(data_out), addr);
36 writel((u32)(data_out >> 32), (addr + 4));
37 }
38 #endif
39
40 static inline bool
mpi3mr_check_req_qfull(struct op_req_qinfo * op_req_q)41 mpi3mr_check_req_qfull(struct op_req_qinfo *op_req_q)
42 {
43 u16 pi, ci, max_entries;
44 bool is_qfull = false;
45
46 pi = op_req_q->pi;
47 ci = READ_ONCE(op_req_q->ci);
48 max_entries = op_req_q->num_requests;
49
50 if ((ci == (pi + 1)) || ((!ci) && (pi == (max_entries - 1))))
51 is_qfull = true;
52
53 return is_qfull;
54 }
55
mpi3mr_sync_irqs(struct mpi3mr_ioc * mrioc)56 static void mpi3mr_sync_irqs(struct mpi3mr_ioc *mrioc)
57 {
58 u16 i, max_vectors;
59
60 max_vectors = mrioc->intr_info_count;
61
62 for (i = 0; i < max_vectors; i++)
63 synchronize_irq(pci_irq_vector(mrioc->pdev, i));
64 }
65
mpi3mr_ioc_disable_intr(struct mpi3mr_ioc * mrioc)66 void mpi3mr_ioc_disable_intr(struct mpi3mr_ioc *mrioc)
67 {
68 mrioc->intr_enabled = 0;
69 mpi3mr_sync_irqs(mrioc);
70 }
71
mpi3mr_ioc_enable_intr(struct mpi3mr_ioc * mrioc)72 void mpi3mr_ioc_enable_intr(struct mpi3mr_ioc *mrioc)
73 {
74 mrioc->intr_enabled = 1;
75 }
76
mpi3mr_cleanup_isr(struct mpi3mr_ioc * mrioc)77 static void mpi3mr_cleanup_isr(struct mpi3mr_ioc *mrioc)
78 {
79 u16 i;
80
81 mpi3mr_ioc_disable_intr(mrioc);
82
83 if (!mrioc->intr_info)
84 return;
85
86 for (i = 0; i < mrioc->intr_info_count; i++)
87 free_irq(pci_irq_vector(mrioc->pdev, i),
88 (mrioc->intr_info + i));
89
90 kfree(mrioc->intr_info);
91 mrioc->intr_info = NULL;
92 mrioc->intr_info_count = 0;
93 mrioc->is_intr_info_set = false;
94 pci_free_irq_vectors(mrioc->pdev);
95 }
96
mpi3mr_add_sg_single(void * paddr,u8 flags,u32 length,dma_addr_t dma_addr)97 void mpi3mr_add_sg_single(void *paddr, u8 flags, u32 length,
98 dma_addr_t dma_addr)
99 {
100 struct mpi3_sge_common *sgel = paddr;
101
102 sgel->flags = flags;
103 sgel->length = cpu_to_le32(length);
104 sgel->address = cpu_to_le64(dma_addr);
105 }
106
mpi3mr_build_zero_len_sge(void * paddr)107 void mpi3mr_build_zero_len_sge(void *paddr)
108 {
109 u8 sgl_flags = MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST;
110
111 mpi3mr_add_sg_single(paddr, sgl_flags, 0, -1);
112 }
113
mpi3mr_get_reply_virt_addr(struct mpi3mr_ioc * mrioc,dma_addr_t phys_addr)114 void *mpi3mr_get_reply_virt_addr(struct mpi3mr_ioc *mrioc,
115 dma_addr_t phys_addr)
116 {
117 if (!phys_addr)
118 return NULL;
119
120 if ((phys_addr < mrioc->reply_buf_dma) ||
121 (phys_addr > mrioc->reply_buf_dma_max_address))
122 return NULL;
123
124 return mrioc->reply_buf + (phys_addr - mrioc->reply_buf_dma);
125 }
126
mpi3mr_get_sensebuf_virt_addr(struct mpi3mr_ioc * mrioc,dma_addr_t phys_addr)127 void *mpi3mr_get_sensebuf_virt_addr(struct mpi3mr_ioc *mrioc,
128 dma_addr_t phys_addr)
129 {
130 if (!phys_addr)
131 return NULL;
132
133 return mrioc->sense_buf + (phys_addr - mrioc->sense_buf_dma);
134 }
135
mpi3mr_repost_reply_buf(struct mpi3mr_ioc * mrioc,u64 reply_dma)136 static void mpi3mr_repost_reply_buf(struct mpi3mr_ioc *mrioc,
137 u64 reply_dma)
138 {
139 u32 old_idx = 0;
140 unsigned long flags;
141
142 spin_lock_irqsave(&mrioc->reply_free_queue_lock, flags);
143 old_idx = mrioc->reply_free_queue_host_index;
144 mrioc->reply_free_queue_host_index = (
145 (mrioc->reply_free_queue_host_index ==
146 (mrioc->reply_free_qsz - 1)) ? 0 :
147 (mrioc->reply_free_queue_host_index + 1));
148 mrioc->reply_free_q[old_idx] = cpu_to_le64(reply_dma);
149 writel(mrioc->reply_free_queue_host_index,
150 &mrioc->sysif_regs->reply_free_host_index);
151 spin_unlock_irqrestore(&mrioc->reply_free_queue_lock, flags);
152 }
153
mpi3mr_repost_sense_buf(struct mpi3mr_ioc * mrioc,u64 sense_buf_dma)154 void mpi3mr_repost_sense_buf(struct mpi3mr_ioc *mrioc,
155 u64 sense_buf_dma)
156 {
157 u32 old_idx = 0;
158 unsigned long flags;
159
160 spin_lock_irqsave(&mrioc->sbq_lock, flags);
161 old_idx = mrioc->sbq_host_index;
162 mrioc->sbq_host_index = ((mrioc->sbq_host_index ==
163 (mrioc->sense_buf_q_sz - 1)) ? 0 :
164 (mrioc->sbq_host_index + 1));
165 mrioc->sense_buf_q[old_idx] = cpu_to_le64(sense_buf_dma);
166 writel(mrioc->sbq_host_index,
167 &mrioc->sysif_regs->sense_buffer_free_host_index);
168 spin_unlock_irqrestore(&mrioc->sbq_lock, flags);
169 }
170
mpi3mr_print_event_data(struct mpi3mr_ioc * mrioc,struct mpi3_event_notification_reply * event_reply)171 static void mpi3mr_print_event_data(struct mpi3mr_ioc *mrioc,
172 struct mpi3_event_notification_reply *event_reply)
173 {
174 char *desc = NULL;
175 u16 event;
176
177 if (!(mrioc->logging_level & MPI3_DEBUG_EVENT))
178 return;
179
180 event = event_reply->event;
181
182 switch (event) {
183 case MPI3_EVENT_LOG_DATA:
184 desc = "Log Data";
185 break;
186 case MPI3_EVENT_CHANGE:
187 desc = "Event Change";
188 break;
189 case MPI3_EVENT_GPIO_INTERRUPT:
190 desc = "GPIO Interrupt";
191 break;
192 case MPI3_EVENT_CABLE_MGMT:
193 desc = "Cable Management";
194 break;
195 case MPI3_EVENT_ENERGY_PACK_CHANGE:
196 desc = "Energy Pack Change";
197 break;
198 case MPI3_EVENT_DEVICE_ADDED:
199 {
200 struct mpi3_device_page0 *event_data =
201 (struct mpi3_device_page0 *)event_reply->event_data;
202 ioc_info(mrioc, "Device Added: dev=0x%04x Form=0x%x\n",
203 event_data->dev_handle, event_data->device_form);
204 return;
205 }
206 case MPI3_EVENT_DEVICE_INFO_CHANGED:
207 {
208 struct mpi3_device_page0 *event_data =
209 (struct mpi3_device_page0 *)event_reply->event_data;
210 ioc_info(mrioc, "Device Info Changed: dev=0x%04x Form=0x%x\n",
211 event_data->dev_handle, event_data->device_form);
212 return;
213 }
214 case MPI3_EVENT_DEVICE_STATUS_CHANGE:
215 {
216 struct mpi3_event_data_device_status_change *event_data =
217 (struct mpi3_event_data_device_status_change *)event_reply->event_data;
218 ioc_info(mrioc, "Device status Change: dev=0x%04x RC=0x%x\n",
219 event_data->dev_handle, event_data->reason_code);
220 return;
221 }
222 case MPI3_EVENT_SAS_DISCOVERY:
223 {
224 struct mpi3_event_data_sas_discovery *event_data =
225 (struct mpi3_event_data_sas_discovery *)event_reply->event_data;
226 ioc_info(mrioc, "SAS Discovery: (%s) status (0x%08x)\n",
227 (event_data->reason_code == MPI3_EVENT_SAS_DISC_RC_STARTED) ?
228 "start" : "stop",
229 le32_to_cpu(event_data->discovery_status));
230 return;
231 }
232 case MPI3_EVENT_SAS_BROADCAST_PRIMITIVE:
233 desc = "SAS Broadcast Primitive";
234 break;
235 case MPI3_EVENT_SAS_NOTIFY_PRIMITIVE:
236 desc = "SAS Notify Primitive";
237 break;
238 case MPI3_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE:
239 desc = "SAS Init Device Status Change";
240 break;
241 case MPI3_EVENT_SAS_INIT_TABLE_OVERFLOW:
242 desc = "SAS Init Table Overflow";
243 break;
244 case MPI3_EVENT_SAS_TOPOLOGY_CHANGE_LIST:
245 desc = "SAS Topology Change List";
246 break;
247 case MPI3_EVENT_ENCL_DEVICE_STATUS_CHANGE:
248 desc = "Enclosure Device Status Change";
249 break;
250 case MPI3_EVENT_ENCL_DEVICE_ADDED:
251 desc = "Enclosure Added";
252 break;
253 case MPI3_EVENT_HARD_RESET_RECEIVED:
254 desc = "Hard Reset Received";
255 break;
256 case MPI3_EVENT_SAS_PHY_COUNTER:
257 desc = "SAS PHY Counter";
258 break;
259 case MPI3_EVENT_SAS_DEVICE_DISCOVERY_ERROR:
260 desc = "SAS Device Discovery Error";
261 break;
262 case MPI3_EVENT_PCIE_TOPOLOGY_CHANGE_LIST:
263 desc = "PCIE Topology Change List";
264 break;
265 case MPI3_EVENT_PCIE_ENUMERATION:
266 {
267 struct mpi3_event_data_pcie_enumeration *event_data =
268 (struct mpi3_event_data_pcie_enumeration *)event_reply->event_data;
269 ioc_info(mrioc, "PCIE Enumeration: (%s)",
270 (event_data->reason_code ==
271 MPI3_EVENT_PCIE_ENUM_RC_STARTED) ? "start" : "stop");
272 if (event_data->enumeration_status)
273 ioc_info(mrioc, "enumeration_status(0x%08x)\n",
274 le32_to_cpu(event_data->enumeration_status));
275 return;
276 }
277 case MPI3_EVENT_PREPARE_FOR_RESET:
278 desc = "Prepare For Reset";
279 break;
280 }
281
282 if (!desc)
283 return;
284
285 ioc_info(mrioc, "%s\n", desc);
286 }
287
mpi3mr_handle_events(struct mpi3mr_ioc * mrioc,struct mpi3_default_reply * def_reply)288 static void mpi3mr_handle_events(struct mpi3mr_ioc *mrioc,
289 struct mpi3_default_reply *def_reply)
290 {
291 struct mpi3_event_notification_reply *event_reply =
292 (struct mpi3_event_notification_reply *)def_reply;
293
294 mrioc->change_count = le16_to_cpu(event_reply->ioc_change_count);
295 mpi3mr_print_event_data(mrioc, event_reply);
296 mpi3mr_os_handle_events(mrioc, event_reply);
297 }
298
299 static struct mpi3mr_drv_cmd *
mpi3mr_get_drv_cmd(struct mpi3mr_ioc * mrioc,u16 host_tag,struct mpi3_default_reply * def_reply)300 mpi3mr_get_drv_cmd(struct mpi3mr_ioc *mrioc, u16 host_tag,
301 struct mpi3_default_reply *def_reply)
302 {
303 u16 idx;
304
305 switch (host_tag) {
306 case MPI3MR_HOSTTAG_INITCMDS:
307 return &mrioc->init_cmds;
308 case MPI3MR_HOSTTAG_CFG_CMDS:
309 return &mrioc->cfg_cmds;
310 case MPI3MR_HOSTTAG_BSG_CMDS:
311 return &mrioc->bsg_cmds;
312 case MPI3MR_HOSTTAG_BLK_TMS:
313 return &mrioc->host_tm_cmds;
314 case MPI3MR_HOSTTAG_PEL_ABORT:
315 return &mrioc->pel_abort_cmd;
316 case MPI3MR_HOSTTAG_PEL_WAIT:
317 return &mrioc->pel_cmds;
318 case MPI3MR_HOSTTAG_TRANSPORT_CMDS:
319 return &mrioc->transport_cmds;
320 case MPI3MR_HOSTTAG_INVALID:
321 if (def_reply && def_reply->function ==
322 MPI3_FUNCTION_EVENT_NOTIFICATION)
323 mpi3mr_handle_events(mrioc, def_reply);
324 return NULL;
325 default:
326 break;
327 }
328 if (host_tag >= MPI3MR_HOSTTAG_DEVRMCMD_MIN &&
329 host_tag <= MPI3MR_HOSTTAG_DEVRMCMD_MAX) {
330 idx = host_tag - MPI3MR_HOSTTAG_DEVRMCMD_MIN;
331 return &mrioc->dev_rmhs_cmds[idx];
332 }
333
334 if (host_tag >= MPI3MR_HOSTTAG_EVTACKCMD_MIN &&
335 host_tag <= MPI3MR_HOSTTAG_EVTACKCMD_MAX) {
336 idx = host_tag - MPI3MR_HOSTTAG_EVTACKCMD_MIN;
337 return &mrioc->evtack_cmds[idx];
338 }
339
340 return NULL;
341 }
342
mpi3mr_process_admin_reply_desc(struct mpi3mr_ioc * mrioc,struct mpi3_default_reply_descriptor * reply_desc,u64 * reply_dma)343 static void mpi3mr_process_admin_reply_desc(struct mpi3mr_ioc *mrioc,
344 struct mpi3_default_reply_descriptor *reply_desc, u64 *reply_dma)
345 {
346 u16 reply_desc_type, host_tag = 0;
347 u16 ioc_status = MPI3_IOCSTATUS_SUCCESS;
348 u32 ioc_loginfo = 0;
349 struct mpi3_status_reply_descriptor *status_desc;
350 struct mpi3_address_reply_descriptor *addr_desc;
351 struct mpi3_success_reply_descriptor *success_desc;
352 struct mpi3_default_reply *def_reply = NULL;
353 struct mpi3mr_drv_cmd *cmdptr = NULL;
354 struct mpi3_scsi_io_reply *scsi_reply;
355 u8 *sense_buf = NULL;
356
357 *reply_dma = 0;
358 reply_desc_type = le16_to_cpu(reply_desc->reply_flags) &
359 MPI3_REPLY_DESCRIPT_FLAGS_TYPE_MASK;
360 switch (reply_desc_type) {
361 case MPI3_REPLY_DESCRIPT_FLAGS_TYPE_STATUS:
362 status_desc = (struct mpi3_status_reply_descriptor *)reply_desc;
363 host_tag = le16_to_cpu(status_desc->host_tag);
364 ioc_status = le16_to_cpu(status_desc->ioc_status);
365 if (ioc_status &
366 MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_LOGINFOAVAIL)
367 ioc_loginfo = le32_to_cpu(status_desc->ioc_log_info);
368 ioc_status &= MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_STATUS_MASK;
369 break;
370 case MPI3_REPLY_DESCRIPT_FLAGS_TYPE_ADDRESS_REPLY:
371 addr_desc = (struct mpi3_address_reply_descriptor *)reply_desc;
372 *reply_dma = le64_to_cpu(addr_desc->reply_frame_address);
373 def_reply = mpi3mr_get_reply_virt_addr(mrioc, *reply_dma);
374 if (!def_reply)
375 goto out;
376 host_tag = le16_to_cpu(def_reply->host_tag);
377 ioc_status = le16_to_cpu(def_reply->ioc_status);
378 if (ioc_status &
379 MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_LOGINFOAVAIL)
380 ioc_loginfo = le32_to_cpu(def_reply->ioc_log_info);
381 ioc_status &= MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_STATUS_MASK;
382 if (def_reply->function == MPI3_FUNCTION_SCSI_IO) {
383 scsi_reply = (struct mpi3_scsi_io_reply *)def_reply;
384 sense_buf = mpi3mr_get_sensebuf_virt_addr(mrioc,
385 le64_to_cpu(scsi_reply->sense_data_buffer_address));
386 }
387 break;
388 case MPI3_REPLY_DESCRIPT_FLAGS_TYPE_SUCCESS:
389 success_desc = (struct mpi3_success_reply_descriptor *)reply_desc;
390 host_tag = le16_to_cpu(success_desc->host_tag);
391 break;
392 default:
393 break;
394 }
395
396 cmdptr = mpi3mr_get_drv_cmd(mrioc, host_tag, def_reply);
397 if (cmdptr) {
398 if (cmdptr->state & MPI3MR_CMD_PENDING) {
399 cmdptr->state |= MPI3MR_CMD_COMPLETE;
400 cmdptr->ioc_loginfo = ioc_loginfo;
401 cmdptr->ioc_status = ioc_status;
402 cmdptr->state &= ~MPI3MR_CMD_PENDING;
403 if (def_reply) {
404 cmdptr->state |= MPI3MR_CMD_REPLY_VALID;
405 memcpy((u8 *)cmdptr->reply, (u8 *)def_reply,
406 mrioc->reply_sz);
407 }
408 if (sense_buf && cmdptr->sensebuf) {
409 cmdptr->is_sense = 1;
410 memcpy(cmdptr->sensebuf, sense_buf,
411 MPI3MR_SENSE_BUF_SZ);
412 }
413 if (cmdptr->is_waiting) {
414 complete(&cmdptr->done);
415 cmdptr->is_waiting = 0;
416 } else if (cmdptr->callback)
417 cmdptr->callback(mrioc, cmdptr);
418 }
419 }
420 out:
421 if (sense_buf)
422 mpi3mr_repost_sense_buf(mrioc,
423 le64_to_cpu(scsi_reply->sense_data_buffer_address));
424 }
425
mpi3mr_process_admin_reply_q(struct mpi3mr_ioc * mrioc)426 int mpi3mr_process_admin_reply_q(struct mpi3mr_ioc *mrioc)
427 {
428 u32 exp_phase = mrioc->admin_reply_ephase;
429 u32 admin_reply_ci = mrioc->admin_reply_ci;
430 u32 num_admin_replies = 0;
431 u64 reply_dma = 0;
432 struct mpi3_default_reply_descriptor *reply_desc;
433
434 if (!atomic_add_unless(&mrioc->admin_reply_q_in_use, 1, 1))
435 return 0;
436
437 reply_desc = (struct mpi3_default_reply_descriptor *)mrioc->admin_reply_base +
438 admin_reply_ci;
439
440 if ((le16_to_cpu(reply_desc->reply_flags) &
441 MPI3_REPLY_DESCRIPT_FLAGS_PHASE_MASK) != exp_phase) {
442 atomic_dec(&mrioc->admin_reply_q_in_use);
443 return 0;
444 }
445
446 do {
447 if (mrioc->unrecoverable)
448 break;
449
450 mrioc->admin_req_ci = le16_to_cpu(reply_desc->request_queue_ci);
451 mpi3mr_process_admin_reply_desc(mrioc, reply_desc, &reply_dma);
452 if (reply_dma)
453 mpi3mr_repost_reply_buf(mrioc, reply_dma);
454 num_admin_replies++;
455 if (++admin_reply_ci == mrioc->num_admin_replies) {
456 admin_reply_ci = 0;
457 exp_phase ^= 1;
458 }
459 reply_desc =
460 (struct mpi3_default_reply_descriptor *)mrioc->admin_reply_base +
461 admin_reply_ci;
462 if ((le16_to_cpu(reply_desc->reply_flags) &
463 MPI3_REPLY_DESCRIPT_FLAGS_PHASE_MASK) != exp_phase)
464 break;
465 } while (1);
466
467 writel(admin_reply_ci, &mrioc->sysif_regs->admin_reply_queue_ci);
468 mrioc->admin_reply_ci = admin_reply_ci;
469 mrioc->admin_reply_ephase = exp_phase;
470 atomic_dec(&mrioc->admin_reply_q_in_use);
471
472 return num_admin_replies;
473 }
474
475 /**
476 * mpi3mr_get_reply_desc - get reply descriptor frame corresponding to
477 * queue's consumer index from operational reply descriptor queue.
478 * @op_reply_q: op_reply_qinfo object
479 * @reply_ci: operational reply descriptor's queue consumer index
480 *
481 * Returns reply descriptor frame address
482 */
483 static inline struct mpi3_default_reply_descriptor *
mpi3mr_get_reply_desc(struct op_reply_qinfo * op_reply_q,u32 reply_ci)484 mpi3mr_get_reply_desc(struct op_reply_qinfo *op_reply_q, u32 reply_ci)
485 {
486 void *segment_base_addr;
487 struct segments *segments = op_reply_q->q_segments;
488 struct mpi3_default_reply_descriptor *reply_desc = NULL;
489
490 segment_base_addr =
491 segments[reply_ci / op_reply_q->segment_qd].segment;
492 reply_desc = (struct mpi3_default_reply_descriptor *)segment_base_addr +
493 (reply_ci % op_reply_q->segment_qd);
494 return reply_desc;
495 }
496
497 /**
498 * mpi3mr_process_op_reply_q - Operational reply queue handler
499 * @mrioc: Adapter instance reference
500 * @op_reply_q: Operational reply queue info
501 *
502 * Checks the specific operational reply queue and drains the
503 * reply queue entries until the queue is empty and process the
504 * individual reply descriptors.
505 *
506 * Return: 0 if queue is already processed,or number of reply
507 * descriptors processed.
508 */
mpi3mr_process_op_reply_q(struct mpi3mr_ioc * mrioc,struct op_reply_qinfo * op_reply_q)509 int mpi3mr_process_op_reply_q(struct mpi3mr_ioc *mrioc,
510 struct op_reply_qinfo *op_reply_q)
511 {
512 struct op_req_qinfo *op_req_q;
513 u32 exp_phase;
514 u32 reply_ci;
515 u32 num_op_reply = 0;
516 u64 reply_dma = 0;
517 struct mpi3_default_reply_descriptor *reply_desc;
518 u16 req_q_idx = 0, reply_qidx;
519
520 reply_qidx = op_reply_q->qid - 1;
521
522 if (!atomic_add_unless(&op_reply_q->in_use, 1, 1))
523 return 0;
524
525 exp_phase = op_reply_q->ephase;
526 reply_ci = op_reply_q->ci;
527
528 reply_desc = mpi3mr_get_reply_desc(op_reply_q, reply_ci);
529 if ((le16_to_cpu(reply_desc->reply_flags) &
530 MPI3_REPLY_DESCRIPT_FLAGS_PHASE_MASK) != exp_phase) {
531 atomic_dec(&op_reply_q->in_use);
532 return 0;
533 }
534
535 do {
536 if (mrioc->unrecoverable)
537 break;
538
539 req_q_idx = le16_to_cpu(reply_desc->request_queue_id) - 1;
540 op_req_q = &mrioc->req_qinfo[req_q_idx];
541
542 WRITE_ONCE(op_req_q->ci, le16_to_cpu(reply_desc->request_queue_ci));
543 mpi3mr_process_op_reply_desc(mrioc, reply_desc, &reply_dma,
544 reply_qidx);
545 atomic_dec(&op_reply_q->pend_ios);
546 if (reply_dma)
547 mpi3mr_repost_reply_buf(mrioc, reply_dma);
548 num_op_reply++;
549
550 if (++reply_ci == op_reply_q->num_replies) {
551 reply_ci = 0;
552 exp_phase ^= 1;
553 }
554
555 reply_desc = mpi3mr_get_reply_desc(op_reply_q, reply_ci);
556
557 if ((le16_to_cpu(reply_desc->reply_flags) &
558 MPI3_REPLY_DESCRIPT_FLAGS_PHASE_MASK) != exp_phase)
559 break;
560 #ifndef CONFIG_PREEMPT_RT
561 /*
562 * Exit completion loop to avoid CPU lockup
563 * Ensure remaining completion happens from threaded ISR.
564 */
565 if (num_op_reply > mrioc->max_host_ios) {
566 op_reply_q->enable_irq_poll = true;
567 break;
568 }
569 #endif
570 } while (1);
571
572 writel(reply_ci,
573 &mrioc->sysif_regs->oper_queue_indexes[reply_qidx].consumer_index);
574 op_reply_q->ci = reply_ci;
575 op_reply_q->ephase = exp_phase;
576
577 atomic_dec(&op_reply_q->in_use);
578 return num_op_reply;
579 }
580
581 /**
582 * mpi3mr_blk_mq_poll - Operational reply queue handler
583 * @shost: SCSI Host reference
584 * @queue_num: Request queue number (w.r.t OS it is hardware context number)
585 *
586 * Checks the specific operational reply queue and drains the
587 * reply queue entries until the queue is empty and process the
588 * individual reply descriptors.
589 *
590 * Return: 0 if queue is already processed,or number of reply
591 * descriptors processed.
592 */
mpi3mr_blk_mq_poll(struct Scsi_Host * shost,unsigned int queue_num)593 int mpi3mr_blk_mq_poll(struct Scsi_Host *shost, unsigned int queue_num)
594 {
595 int num_entries = 0;
596 struct mpi3mr_ioc *mrioc;
597
598 mrioc = (struct mpi3mr_ioc *)shost->hostdata;
599
600 if ((mrioc->reset_in_progress || mrioc->prepare_for_reset ||
601 mrioc->unrecoverable))
602 return 0;
603
604 num_entries = mpi3mr_process_op_reply_q(mrioc,
605 &mrioc->op_reply_qinfo[queue_num]);
606
607 return num_entries;
608 }
609
mpi3mr_isr_primary(int irq,void * privdata)610 static irqreturn_t mpi3mr_isr_primary(int irq, void *privdata)
611 {
612 struct mpi3mr_intr_info *intr_info = privdata;
613 struct mpi3mr_ioc *mrioc;
614 u16 midx;
615 u32 num_admin_replies = 0, num_op_reply = 0;
616
617 if (!intr_info)
618 return IRQ_NONE;
619
620 mrioc = intr_info->mrioc;
621
622 if (!mrioc->intr_enabled)
623 return IRQ_NONE;
624
625 midx = intr_info->msix_index;
626
627 if (!midx)
628 num_admin_replies = mpi3mr_process_admin_reply_q(mrioc);
629 if (intr_info->op_reply_q)
630 num_op_reply = mpi3mr_process_op_reply_q(mrioc,
631 intr_info->op_reply_q);
632
633 if (num_admin_replies || num_op_reply)
634 return IRQ_HANDLED;
635 else
636 return IRQ_NONE;
637 }
638
639 #ifndef CONFIG_PREEMPT_RT
640
mpi3mr_isr(int irq,void * privdata)641 static irqreturn_t mpi3mr_isr(int irq, void *privdata)
642 {
643 struct mpi3mr_intr_info *intr_info = privdata;
644 int ret;
645
646 if (!intr_info)
647 return IRQ_NONE;
648
649 /* Call primary ISR routine */
650 ret = mpi3mr_isr_primary(irq, privdata);
651
652 /*
653 * If more IOs are expected, schedule IRQ polling thread.
654 * Otherwise exit from ISR.
655 */
656 if (!intr_info->op_reply_q)
657 return ret;
658
659 if (!intr_info->op_reply_q->enable_irq_poll ||
660 !atomic_read(&intr_info->op_reply_q->pend_ios))
661 return ret;
662
663 disable_irq_nosync(intr_info->os_irq);
664
665 return IRQ_WAKE_THREAD;
666 }
667
668 /**
669 * mpi3mr_isr_poll - Reply queue polling routine
670 * @irq: IRQ
671 * @privdata: Interrupt info
672 *
673 * poll for pending I/O completions in a loop until pending I/Os
674 * present or controller queue depth I/Os are processed.
675 *
676 * Return: IRQ_NONE or IRQ_HANDLED
677 */
mpi3mr_isr_poll(int irq,void * privdata)678 static irqreturn_t mpi3mr_isr_poll(int irq, void *privdata)
679 {
680 struct mpi3mr_intr_info *intr_info = privdata;
681 struct mpi3mr_ioc *mrioc;
682 u16 midx;
683 u32 num_op_reply = 0;
684
685 if (!intr_info || !intr_info->op_reply_q)
686 return IRQ_NONE;
687
688 mrioc = intr_info->mrioc;
689 midx = intr_info->msix_index;
690
691 /* Poll for pending IOs completions */
692 do {
693 if (!mrioc->intr_enabled || mrioc->unrecoverable)
694 break;
695
696 if (!midx)
697 mpi3mr_process_admin_reply_q(mrioc);
698 if (intr_info->op_reply_q)
699 num_op_reply +=
700 mpi3mr_process_op_reply_q(mrioc,
701 intr_info->op_reply_q);
702
703 usleep_range(MPI3MR_IRQ_POLL_SLEEP, 10 * MPI3MR_IRQ_POLL_SLEEP);
704
705 } while (atomic_read(&intr_info->op_reply_q->pend_ios) &&
706 (num_op_reply < mrioc->max_host_ios));
707
708 intr_info->op_reply_q->enable_irq_poll = false;
709 enable_irq(intr_info->os_irq);
710
711 return IRQ_HANDLED;
712 }
713
714 #endif
715
716 /**
717 * mpi3mr_request_irq - Request IRQ and register ISR
718 * @mrioc: Adapter instance reference
719 * @index: IRQ vector index
720 *
721 * Request threaded ISR with primary ISR and secondary
722 *
723 * Return: 0 on success and non zero on failures.
724 */
mpi3mr_request_irq(struct mpi3mr_ioc * mrioc,u16 index)725 static inline int mpi3mr_request_irq(struct mpi3mr_ioc *mrioc, u16 index)
726 {
727 struct pci_dev *pdev = mrioc->pdev;
728 struct mpi3mr_intr_info *intr_info = mrioc->intr_info + index;
729 int retval = 0;
730
731 intr_info->mrioc = mrioc;
732 intr_info->msix_index = index;
733 intr_info->op_reply_q = NULL;
734
735 snprintf(intr_info->name, MPI3MR_NAME_LENGTH, "%s%d-msix%d",
736 mrioc->driver_name, mrioc->id, index);
737
738 #ifndef CONFIG_PREEMPT_RT
739 retval = request_threaded_irq(pci_irq_vector(pdev, index), mpi3mr_isr,
740 mpi3mr_isr_poll, IRQF_SHARED, intr_info->name, intr_info);
741 #else
742 retval = request_threaded_irq(pci_irq_vector(pdev, index), mpi3mr_isr_primary,
743 NULL, IRQF_SHARED, intr_info->name, intr_info);
744 #endif
745 if (retval) {
746 ioc_err(mrioc, "%s: Unable to allocate interrupt %d!\n",
747 intr_info->name, pci_irq_vector(pdev, index));
748 return retval;
749 }
750
751 intr_info->os_irq = pci_irq_vector(pdev, index);
752 return retval;
753 }
754
mpi3mr_calc_poll_queues(struct mpi3mr_ioc * mrioc,u16 max_vectors)755 static void mpi3mr_calc_poll_queues(struct mpi3mr_ioc *mrioc, u16 max_vectors)
756 {
757 if (!mrioc->requested_poll_qcount)
758 return;
759
760 /* Reserved for Admin and Default Queue */
761 if (max_vectors > 2 &&
762 (mrioc->requested_poll_qcount < max_vectors - 2)) {
763 ioc_info(mrioc,
764 "enabled polled queues (%d) msix (%d)\n",
765 mrioc->requested_poll_qcount, max_vectors);
766 } else {
767 ioc_info(mrioc,
768 "disabled polled queues (%d) msix (%d) because of no resources for default queue\n",
769 mrioc->requested_poll_qcount, max_vectors);
770 mrioc->requested_poll_qcount = 0;
771 }
772 }
773
774 /**
775 * mpi3mr_setup_isr - Setup ISR for the controller
776 * @mrioc: Adapter instance reference
777 * @setup_one: Request one IRQ or more
778 *
779 * Allocate IRQ vectors and call mpi3mr_request_irq to setup ISR
780 *
781 * Return: 0 on success and non zero on failures.
782 */
mpi3mr_setup_isr(struct mpi3mr_ioc * mrioc,u8 setup_one)783 static int mpi3mr_setup_isr(struct mpi3mr_ioc *mrioc, u8 setup_one)
784 {
785 unsigned int irq_flags = PCI_IRQ_MSIX;
786 int max_vectors, min_vec;
787 int retval;
788 int i;
789 struct irq_affinity desc = { .pre_vectors = 1, .post_vectors = 1 };
790
791 if (mrioc->is_intr_info_set)
792 return 0;
793
794 mpi3mr_cleanup_isr(mrioc);
795
796 if (setup_one || reset_devices) {
797 max_vectors = 1;
798 retval = pci_alloc_irq_vectors(mrioc->pdev,
799 1, max_vectors, irq_flags);
800 if (retval < 0) {
801 ioc_err(mrioc, "cannot allocate irq vectors, ret %d\n",
802 retval);
803 goto out_failed;
804 }
805 } else {
806 max_vectors =
807 min_t(int, mrioc->cpu_count + 1 +
808 mrioc->requested_poll_qcount, mrioc->msix_count);
809
810 mpi3mr_calc_poll_queues(mrioc, max_vectors);
811
812 ioc_info(mrioc,
813 "MSI-X vectors supported: %d, no of cores: %d,",
814 mrioc->msix_count, mrioc->cpu_count);
815 ioc_info(mrioc,
816 "MSI-x vectors requested: %d poll_queues %d\n",
817 max_vectors, mrioc->requested_poll_qcount);
818
819 desc.post_vectors = mrioc->requested_poll_qcount;
820 min_vec = desc.pre_vectors + desc.post_vectors;
821 irq_flags |= PCI_IRQ_AFFINITY | PCI_IRQ_ALL_TYPES;
822
823 retval = pci_alloc_irq_vectors_affinity(mrioc->pdev,
824 min_vec, max_vectors, irq_flags, &desc);
825
826 if (retval < 0) {
827 ioc_err(mrioc, "cannot allocate irq vectors, ret %d\n",
828 retval);
829 goto out_failed;
830 }
831
832
833 /*
834 * If only one MSI-x is allocated, then MSI-x 0 will be shared
835 * between Admin queue and operational queue
836 */
837 if (retval == min_vec)
838 mrioc->op_reply_q_offset = 0;
839 else if (retval != (max_vectors)) {
840 ioc_info(mrioc,
841 "allocated vectors (%d) are less than configured (%d)\n",
842 retval, max_vectors);
843 }
844
845 max_vectors = retval;
846 mrioc->op_reply_q_offset = (max_vectors > 1) ? 1 : 0;
847
848 mpi3mr_calc_poll_queues(mrioc, max_vectors);
849
850 }
851
852 mrioc->intr_info = kzalloc(sizeof(struct mpi3mr_intr_info) * max_vectors,
853 GFP_KERNEL);
854 if (!mrioc->intr_info) {
855 retval = -ENOMEM;
856 pci_free_irq_vectors(mrioc->pdev);
857 goto out_failed;
858 }
859 for (i = 0; i < max_vectors; i++) {
860 retval = mpi3mr_request_irq(mrioc, i);
861 if (retval) {
862 mrioc->intr_info_count = i;
863 goto out_failed;
864 }
865 }
866 if (reset_devices || !setup_one)
867 mrioc->is_intr_info_set = true;
868 mrioc->intr_info_count = max_vectors;
869 mpi3mr_ioc_enable_intr(mrioc);
870 return 0;
871
872 out_failed:
873 mpi3mr_cleanup_isr(mrioc);
874
875 return retval;
876 }
877
878 static const struct {
879 enum mpi3mr_iocstate value;
880 char *name;
881 } mrioc_states[] = {
882 { MRIOC_STATE_READY, "ready" },
883 { MRIOC_STATE_FAULT, "fault" },
884 { MRIOC_STATE_RESET, "reset" },
885 { MRIOC_STATE_BECOMING_READY, "becoming ready" },
886 { MRIOC_STATE_RESET_REQUESTED, "reset requested" },
887 { MRIOC_STATE_UNRECOVERABLE, "unrecoverable error" },
888 };
889
mpi3mr_iocstate_name(enum mpi3mr_iocstate mrioc_state)890 static const char *mpi3mr_iocstate_name(enum mpi3mr_iocstate mrioc_state)
891 {
892 int i;
893 char *name = NULL;
894
895 for (i = 0; i < ARRAY_SIZE(mrioc_states); i++) {
896 if (mrioc_states[i].value == mrioc_state) {
897 name = mrioc_states[i].name;
898 break;
899 }
900 }
901 return name;
902 }
903
904 /* Reset reason to name mapper structure*/
905 static const struct {
906 enum mpi3mr_reset_reason value;
907 char *name;
908 } mpi3mr_reset_reason_codes[] = {
909 { MPI3MR_RESET_FROM_BRINGUP, "timeout in bringup" },
910 { MPI3MR_RESET_FROM_FAULT_WATCH, "fault" },
911 { MPI3MR_RESET_FROM_APP, "application invocation" },
912 { MPI3MR_RESET_FROM_EH_HOS, "error handling" },
913 { MPI3MR_RESET_FROM_TM_TIMEOUT, "TM timeout" },
914 { MPI3MR_RESET_FROM_APP_TIMEOUT, "application command timeout" },
915 { MPI3MR_RESET_FROM_MUR_FAILURE, "MUR failure" },
916 { MPI3MR_RESET_FROM_CTLR_CLEANUP, "timeout in controller cleanup" },
917 { MPI3MR_RESET_FROM_CIACTIV_FAULT, "component image activation fault" },
918 { MPI3MR_RESET_FROM_PE_TIMEOUT, "port enable timeout" },
919 { MPI3MR_RESET_FROM_TSU_TIMEOUT, "time stamp update timeout" },
920 { MPI3MR_RESET_FROM_DELREQQ_TIMEOUT, "delete request queue timeout" },
921 { MPI3MR_RESET_FROM_DELREPQ_TIMEOUT, "delete reply queue timeout" },
922 {
923 MPI3MR_RESET_FROM_CREATEREPQ_TIMEOUT,
924 "create request queue timeout"
925 },
926 {
927 MPI3MR_RESET_FROM_CREATEREQQ_TIMEOUT,
928 "create reply queue timeout"
929 },
930 { MPI3MR_RESET_FROM_IOCFACTS_TIMEOUT, "IOC facts timeout" },
931 { MPI3MR_RESET_FROM_IOCINIT_TIMEOUT, "IOC init timeout" },
932 { MPI3MR_RESET_FROM_EVTNOTIFY_TIMEOUT, "event notify timeout" },
933 { MPI3MR_RESET_FROM_EVTACK_TIMEOUT, "event acknowledgment timeout" },
934 {
935 MPI3MR_RESET_FROM_CIACTVRST_TIMER,
936 "component image activation timeout"
937 },
938 {
939 MPI3MR_RESET_FROM_GETPKGVER_TIMEOUT,
940 "get package version timeout"
941 },
942 { MPI3MR_RESET_FROM_SYSFS, "sysfs invocation" },
943 { MPI3MR_RESET_FROM_SYSFS_TIMEOUT, "sysfs TM timeout" },
944 { MPI3MR_RESET_FROM_FIRMWARE, "firmware asynchronous reset" },
945 { MPI3MR_RESET_FROM_CFG_REQ_TIMEOUT, "configuration request timeout"},
946 { MPI3MR_RESET_FROM_SAS_TRANSPORT_TIMEOUT, "timeout of a SAS transport layer request" },
947 };
948
949 /**
950 * mpi3mr_reset_rc_name - get reset reason code name
951 * @reason_code: reset reason code value
952 *
953 * Map reset reason to an NULL terminated ASCII string
954 *
955 * Return: name corresponding to reset reason value or NULL.
956 */
mpi3mr_reset_rc_name(enum mpi3mr_reset_reason reason_code)957 static const char *mpi3mr_reset_rc_name(enum mpi3mr_reset_reason reason_code)
958 {
959 int i;
960 char *name = NULL;
961
962 for (i = 0; i < ARRAY_SIZE(mpi3mr_reset_reason_codes); i++) {
963 if (mpi3mr_reset_reason_codes[i].value == reason_code) {
964 name = mpi3mr_reset_reason_codes[i].name;
965 break;
966 }
967 }
968 return name;
969 }
970
971 /* Reset type to name mapper structure*/
972 static const struct {
973 u16 reset_type;
974 char *name;
975 } mpi3mr_reset_types[] = {
976 { MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET, "soft" },
977 { MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT, "diag fault" },
978 };
979
980 /**
981 * mpi3mr_reset_type_name - get reset type name
982 * @reset_type: reset type value
983 *
984 * Map reset type to an NULL terminated ASCII string
985 *
986 * Return: name corresponding to reset type value or NULL.
987 */
mpi3mr_reset_type_name(u16 reset_type)988 static const char *mpi3mr_reset_type_name(u16 reset_type)
989 {
990 int i;
991 char *name = NULL;
992
993 for (i = 0; i < ARRAY_SIZE(mpi3mr_reset_types); i++) {
994 if (mpi3mr_reset_types[i].reset_type == reset_type) {
995 name = mpi3mr_reset_types[i].name;
996 break;
997 }
998 }
999 return name;
1000 }
1001
1002 /**
1003 * mpi3mr_print_fault_info - Display fault information
1004 * @mrioc: Adapter instance reference
1005 *
1006 * Display the controller fault information if there is a
1007 * controller fault.
1008 *
1009 * Return: Nothing.
1010 */
mpi3mr_print_fault_info(struct mpi3mr_ioc * mrioc)1011 void mpi3mr_print_fault_info(struct mpi3mr_ioc *mrioc)
1012 {
1013 u32 ioc_status, code, code1, code2, code3;
1014
1015 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1016
1017 if (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT) {
1018 code = readl(&mrioc->sysif_regs->fault);
1019 code1 = readl(&mrioc->sysif_regs->fault_info[0]);
1020 code2 = readl(&mrioc->sysif_regs->fault_info[1]);
1021 code3 = readl(&mrioc->sysif_regs->fault_info[2]);
1022
1023 ioc_info(mrioc,
1024 "fault code(0x%08X): Additional code: (0x%08X:0x%08X:0x%08X)\n",
1025 code, code1, code2, code3);
1026 }
1027 }
1028
1029 /**
1030 * mpi3mr_get_iocstate - Get IOC State
1031 * @mrioc: Adapter instance reference
1032 *
1033 * Return a proper IOC state enum based on the IOC status and
1034 * IOC configuration and unrcoverable state of the controller.
1035 *
1036 * Return: Current IOC state.
1037 */
mpi3mr_get_iocstate(struct mpi3mr_ioc * mrioc)1038 enum mpi3mr_iocstate mpi3mr_get_iocstate(struct mpi3mr_ioc *mrioc)
1039 {
1040 u32 ioc_status, ioc_config;
1041 u8 ready, enabled;
1042
1043 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1044 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
1045
1046 if (mrioc->unrecoverable)
1047 return MRIOC_STATE_UNRECOVERABLE;
1048 if (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT)
1049 return MRIOC_STATE_FAULT;
1050
1051 ready = (ioc_status & MPI3_SYSIF_IOC_STATUS_READY);
1052 enabled = (ioc_config & MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC);
1053
1054 if (ready && enabled)
1055 return MRIOC_STATE_READY;
1056 if ((!ready) && (!enabled))
1057 return MRIOC_STATE_RESET;
1058 if ((!ready) && (enabled))
1059 return MRIOC_STATE_BECOMING_READY;
1060
1061 return MRIOC_STATE_RESET_REQUESTED;
1062 }
1063
1064 /**
1065 * mpi3mr_clear_reset_history - clear reset history
1066 * @mrioc: Adapter instance reference
1067 *
1068 * Write the reset history bit in IOC status to clear the bit,
1069 * if it is already set.
1070 *
1071 * Return: Nothing.
1072 */
mpi3mr_clear_reset_history(struct mpi3mr_ioc * mrioc)1073 static inline void mpi3mr_clear_reset_history(struct mpi3mr_ioc *mrioc)
1074 {
1075 u32 ioc_status;
1076
1077 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1078 if (ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY)
1079 writel(ioc_status, &mrioc->sysif_regs->ioc_status);
1080 }
1081
1082 /**
1083 * mpi3mr_issue_and_process_mur - Message unit Reset handler
1084 * @mrioc: Adapter instance reference
1085 * @reset_reason: Reset reason code
1086 *
1087 * Issue Message unit Reset to the controller and wait for it to
1088 * be complete.
1089 *
1090 * Return: 0 on success, -1 on failure.
1091 */
mpi3mr_issue_and_process_mur(struct mpi3mr_ioc * mrioc,u32 reset_reason)1092 static int mpi3mr_issue_and_process_mur(struct mpi3mr_ioc *mrioc,
1093 u32 reset_reason)
1094 {
1095 u32 ioc_config, timeout, ioc_status;
1096 int retval = -1;
1097
1098 ioc_info(mrioc, "Issuing Message unit Reset(MUR)\n");
1099 if (mrioc->unrecoverable) {
1100 ioc_info(mrioc, "IOC is unrecoverable MUR not issued\n");
1101 return retval;
1102 }
1103 mpi3mr_clear_reset_history(mrioc);
1104 writel(reset_reason, &mrioc->sysif_regs->scratchpad[0]);
1105 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
1106 ioc_config &= ~MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC;
1107 writel(ioc_config, &mrioc->sysif_regs->ioc_configuration);
1108
1109 timeout = MPI3MR_MUR_TIMEOUT * 10;
1110 do {
1111 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1112 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY)) {
1113 mpi3mr_clear_reset_history(mrioc);
1114 break;
1115 }
1116 if (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT) {
1117 mpi3mr_print_fault_info(mrioc);
1118 break;
1119 }
1120 msleep(100);
1121 } while (--timeout);
1122
1123 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
1124 if (timeout && !((ioc_status & MPI3_SYSIF_IOC_STATUS_READY) ||
1125 (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT) ||
1126 (ioc_config & MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC)))
1127 retval = 0;
1128
1129 ioc_info(mrioc, "Base IOC Sts/Config after %s MUR is (0x%x)/(0x%x)\n",
1130 (!retval) ? "successful" : "failed", ioc_status, ioc_config);
1131 return retval;
1132 }
1133
1134 /**
1135 * mpi3mr_revalidate_factsdata - validate IOCFacts parameters
1136 * during reset/resume
1137 * @mrioc: Adapter instance reference
1138 *
1139 * Return zero if the new IOCFacts parameters value is compatible with
1140 * older values else return -EPERM
1141 */
1142 static int
mpi3mr_revalidate_factsdata(struct mpi3mr_ioc * mrioc)1143 mpi3mr_revalidate_factsdata(struct mpi3mr_ioc *mrioc)
1144 {
1145 unsigned long *removepend_bitmap;
1146
1147 if (mrioc->facts.reply_sz > mrioc->reply_sz) {
1148 ioc_err(mrioc,
1149 "cannot increase reply size from %d to %d\n",
1150 mrioc->reply_sz, mrioc->facts.reply_sz);
1151 return -EPERM;
1152 }
1153
1154 if (mrioc->facts.max_op_reply_q < mrioc->num_op_reply_q) {
1155 ioc_err(mrioc,
1156 "cannot reduce number of operational reply queues from %d to %d\n",
1157 mrioc->num_op_reply_q,
1158 mrioc->facts.max_op_reply_q);
1159 return -EPERM;
1160 }
1161
1162 if (mrioc->facts.max_op_req_q < mrioc->num_op_req_q) {
1163 ioc_err(mrioc,
1164 "cannot reduce number of operational request queues from %d to %d\n",
1165 mrioc->num_op_req_q, mrioc->facts.max_op_req_q);
1166 return -EPERM;
1167 }
1168
1169 if (mrioc->shost->max_sectors != (mrioc->facts.max_data_length / 512))
1170 ioc_err(mrioc, "Warning: The maximum data transfer length\n"
1171 "\tchanged after reset: previous(%d), new(%d),\n"
1172 "the driver cannot change this at run time\n",
1173 mrioc->shost->max_sectors * 512, mrioc->facts.max_data_length);
1174
1175 if ((mrioc->sas_transport_enabled) && (mrioc->facts.ioc_capabilities &
1176 MPI3_IOCFACTS_CAPABILITY_MULTIPATH_ENABLED))
1177 ioc_err(mrioc,
1178 "critical error: multipath capability is enabled at the\n"
1179 "\tcontroller while sas transport support is enabled at the\n"
1180 "\tdriver, please reboot the system or reload the driver\n");
1181
1182 if (mrioc->facts.max_devhandle > mrioc->dev_handle_bitmap_bits) {
1183 removepend_bitmap = bitmap_zalloc(mrioc->facts.max_devhandle,
1184 GFP_KERNEL);
1185 if (!removepend_bitmap) {
1186 ioc_err(mrioc,
1187 "failed to increase removepend_bitmap bits from %d to %d\n",
1188 mrioc->dev_handle_bitmap_bits,
1189 mrioc->facts.max_devhandle);
1190 return -EPERM;
1191 }
1192 bitmap_free(mrioc->removepend_bitmap);
1193 mrioc->removepend_bitmap = removepend_bitmap;
1194 ioc_info(mrioc,
1195 "increased bits of dev_handle_bitmap from %d to %d\n",
1196 mrioc->dev_handle_bitmap_bits,
1197 mrioc->facts.max_devhandle);
1198 mrioc->dev_handle_bitmap_bits = mrioc->facts.max_devhandle;
1199 }
1200
1201 return 0;
1202 }
1203
1204 /**
1205 * mpi3mr_bring_ioc_ready - Bring controller to ready state
1206 * @mrioc: Adapter instance reference
1207 *
1208 * Set Enable IOC bit in IOC configuration register and wait for
1209 * the controller to become ready.
1210 *
1211 * Return: 0 on success, appropriate error on failure.
1212 */
mpi3mr_bring_ioc_ready(struct mpi3mr_ioc * mrioc)1213 static int mpi3mr_bring_ioc_ready(struct mpi3mr_ioc *mrioc)
1214 {
1215 u32 ioc_config, ioc_status, timeout, host_diagnostic;
1216 int retval = 0;
1217 enum mpi3mr_iocstate ioc_state;
1218 u64 base_info;
1219
1220 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1221 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
1222 base_info = lo_hi_readq(&mrioc->sysif_regs->ioc_information);
1223 ioc_info(mrioc, "ioc_status(0x%08x), ioc_config(0x%08x), ioc_info(0x%016llx) at the bringup\n",
1224 ioc_status, ioc_config, base_info);
1225
1226 /*The timeout value is in 2sec unit, changing it to seconds*/
1227 mrioc->ready_timeout =
1228 ((base_info & MPI3_SYSIF_IOC_INFO_LOW_TIMEOUT_MASK) >>
1229 MPI3_SYSIF_IOC_INFO_LOW_TIMEOUT_SHIFT) * 2;
1230
1231 ioc_info(mrioc, "ready timeout: %d seconds\n", mrioc->ready_timeout);
1232
1233 ioc_state = mpi3mr_get_iocstate(mrioc);
1234 ioc_info(mrioc, "controller is in %s state during detection\n",
1235 mpi3mr_iocstate_name(ioc_state));
1236
1237 if (ioc_state == MRIOC_STATE_BECOMING_READY ||
1238 ioc_state == MRIOC_STATE_RESET_REQUESTED) {
1239 timeout = mrioc->ready_timeout * 10;
1240 do {
1241 msleep(100);
1242 } while (--timeout);
1243
1244 if (!pci_device_is_present(mrioc->pdev)) {
1245 mrioc->unrecoverable = 1;
1246 ioc_err(mrioc,
1247 "controller is not present while waiting to reset\n");
1248 retval = -1;
1249 goto out_device_not_present;
1250 }
1251
1252 ioc_state = mpi3mr_get_iocstate(mrioc);
1253 ioc_info(mrioc,
1254 "controller is in %s state after waiting to reset\n",
1255 mpi3mr_iocstate_name(ioc_state));
1256 }
1257
1258 if (ioc_state == MRIOC_STATE_READY) {
1259 ioc_info(mrioc, "issuing message unit reset (MUR) to bring to reset state\n");
1260 retval = mpi3mr_issue_and_process_mur(mrioc,
1261 MPI3MR_RESET_FROM_BRINGUP);
1262 ioc_state = mpi3mr_get_iocstate(mrioc);
1263 if (retval)
1264 ioc_err(mrioc,
1265 "message unit reset failed with error %d current state %s\n",
1266 retval, mpi3mr_iocstate_name(ioc_state));
1267 }
1268 if (ioc_state != MRIOC_STATE_RESET) {
1269 if (ioc_state == MRIOC_STATE_FAULT) {
1270 timeout = MPI3_SYSIF_DIAG_SAVE_TIMEOUT * 10;
1271 mpi3mr_print_fault_info(mrioc);
1272 do {
1273 host_diagnostic =
1274 readl(&mrioc->sysif_regs->host_diagnostic);
1275 if (!(host_diagnostic &
1276 MPI3_SYSIF_HOST_DIAG_SAVE_IN_PROGRESS))
1277 break;
1278 if (!pci_device_is_present(mrioc->pdev)) {
1279 mrioc->unrecoverable = 1;
1280 ioc_err(mrioc, "controller is not present at the bringup\n");
1281 goto out_device_not_present;
1282 }
1283 msleep(100);
1284 } while (--timeout);
1285 }
1286 mpi3mr_print_fault_info(mrioc);
1287 ioc_info(mrioc, "issuing soft reset to bring to reset state\n");
1288 retval = mpi3mr_issue_reset(mrioc,
1289 MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET,
1290 MPI3MR_RESET_FROM_BRINGUP);
1291 if (retval) {
1292 ioc_err(mrioc,
1293 "soft reset failed with error %d\n", retval);
1294 goto out_failed;
1295 }
1296 }
1297 ioc_state = mpi3mr_get_iocstate(mrioc);
1298 if (ioc_state != MRIOC_STATE_RESET) {
1299 ioc_err(mrioc,
1300 "cannot bring controller to reset state, current state: %s\n",
1301 mpi3mr_iocstate_name(ioc_state));
1302 goto out_failed;
1303 }
1304 mpi3mr_clear_reset_history(mrioc);
1305 retval = mpi3mr_setup_admin_qpair(mrioc);
1306 if (retval) {
1307 ioc_err(mrioc, "failed to setup admin queues: error %d\n",
1308 retval);
1309 goto out_failed;
1310 }
1311
1312 ioc_info(mrioc, "bringing controller to ready state\n");
1313 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
1314 ioc_config |= MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC;
1315 writel(ioc_config, &mrioc->sysif_regs->ioc_configuration);
1316
1317 timeout = mrioc->ready_timeout * 10;
1318 do {
1319 ioc_state = mpi3mr_get_iocstate(mrioc);
1320 if (ioc_state == MRIOC_STATE_READY) {
1321 ioc_info(mrioc,
1322 "successfully transitioned to %s state\n",
1323 mpi3mr_iocstate_name(ioc_state));
1324 return 0;
1325 }
1326 if (!pci_device_is_present(mrioc->pdev)) {
1327 mrioc->unrecoverable = 1;
1328 ioc_err(mrioc,
1329 "controller is not present at the bringup\n");
1330 retval = -1;
1331 goto out_device_not_present;
1332 }
1333 msleep(100);
1334 } while (--timeout);
1335
1336 out_failed:
1337 ioc_state = mpi3mr_get_iocstate(mrioc);
1338 ioc_err(mrioc,
1339 "failed to bring to ready state, current state: %s\n",
1340 mpi3mr_iocstate_name(ioc_state));
1341 out_device_not_present:
1342 return retval;
1343 }
1344
1345 /**
1346 * mpi3mr_soft_reset_success - Check softreset is success or not
1347 * @ioc_status: IOC status register value
1348 * @ioc_config: IOC config register value
1349 *
1350 * Check whether the soft reset is successful or not based on
1351 * IOC status and IOC config register values.
1352 *
1353 * Return: True when the soft reset is success, false otherwise.
1354 */
1355 static inline bool
mpi3mr_soft_reset_success(u32 ioc_status,u32 ioc_config)1356 mpi3mr_soft_reset_success(u32 ioc_status, u32 ioc_config)
1357 {
1358 if (!((ioc_status & MPI3_SYSIF_IOC_STATUS_READY) ||
1359 (ioc_config & MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC)))
1360 return true;
1361 return false;
1362 }
1363
1364 /**
1365 * mpi3mr_diagfault_success - Check diag fault is success or not
1366 * @mrioc: Adapter reference
1367 * @ioc_status: IOC status register value
1368 *
1369 * Check whether the controller hit diag reset fault code.
1370 *
1371 * Return: True when there is diag fault, false otherwise.
1372 */
mpi3mr_diagfault_success(struct mpi3mr_ioc * mrioc,u32 ioc_status)1373 static inline bool mpi3mr_diagfault_success(struct mpi3mr_ioc *mrioc,
1374 u32 ioc_status)
1375 {
1376 u32 fault;
1377
1378 if (!(ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT))
1379 return false;
1380 fault = readl(&mrioc->sysif_regs->fault) & MPI3_SYSIF_FAULT_CODE_MASK;
1381 if (fault == MPI3_SYSIF_FAULT_CODE_DIAG_FAULT_RESET) {
1382 mpi3mr_print_fault_info(mrioc);
1383 return true;
1384 }
1385 return false;
1386 }
1387
1388 /**
1389 * mpi3mr_set_diagsave - Set diag save bit for snapdump
1390 * @mrioc: Adapter reference
1391 *
1392 * Set diag save bit in IOC configuration register to enable
1393 * snapdump.
1394 *
1395 * Return: Nothing.
1396 */
mpi3mr_set_diagsave(struct mpi3mr_ioc * mrioc)1397 static inline void mpi3mr_set_diagsave(struct mpi3mr_ioc *mrioc)
1398 {
1399 u32 ioc_config;
1400
1401 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
1402 ioc_config |= MPI3_SYSIF_IOC_CONFIG_DIAG_SAVE;
1403 writel(ioc_config, &mrioc->sysif_regs->ioc_configuration);
1404 }
1405
1406 /**
1407 * mpi3mr_issue_reset - Issue reset to the controller
1408 * @mrioc: Adapter reference
1409 * @reset_type: Reset type
1410 * @reset_reason: Reset reason code
1411 *
1412 * Unlock the host diagnostic registers and write the specific
1413 * reset type to that, wait for reset acknowledgment from the
1414 * controller, if the reset is not successful retry for the
1415 * predefined number of times.
1416 *
1417 * Return: 0 on success, non-zero on failure.
1418 */
mpi3mr_issue_reset(struct mpi3mr_ioc * mrioc,u16 reset_type,u32 reset_reason)1419 static int mpi3mr_issue_reset(struct mpi3mr_ioc *mrioc, u16 reset_type,
1420 u32 reset_reason)
1421 {
1422 int retval = -1;
1423 u8 unlock_retry_count = 0;
1424 u32 host_diagnostic, ioc_status, ioc_config;
1425 u32 timeout = MPI3MR_RESET_ACK_TIMEOUT * 10;
1426
1427 if ((reset_type != MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET) &&
1428 (reset_type != MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT))
1429 return retval;
1430 if (mrioc->unrecoverable)
1431 return retval;
1432 if (reset_reason == MPI3MR_RESET_FROM_FIRMWARE) {
1433 retval = 0;
1434 return retval;
1435 }
1436
1437 ioc_info(mrioc, "%s reset due to %s(0x%x)\n",
1438 mpi3mr_reset_type_name(reset_type),
1439 mpi3mr_reset_rc_name(reset_reason), reset_reason);
1440
1441 mpi3mr_clear_reset_history(mrioc);
1442 do {
1443 ioc_info(mrioc,
1444 "Write magic sequence to unlock host diag register (retry=%d)\n",
1445 ++unlock_retry_count);
1446 if (unlock_retry_count >= MPI3MR_HOSTDIAG_UNLOCK_RETRY_COUNT) {
1447 ioc_err(mrioc,
1448 "%s reset failed due to unlock failure, host_diagnostic(0x%08x)\n",
1449 mpi3mr_reset_type_name(reset_type),
1450 host_diagnostic);
1451 mrioc->unrecoverable = 1;
1452 return retval;
1453 }
1454
1455 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_FLUSH,
1456 &mrioc->sysif_regs->write_sequence);
1457 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_1ST,
1458 &mrioc->sysif_regs->write_sequence);
1459 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_2ND,
1460 &mrioc->sysif_regs->write_sequence);
1461 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_3RD,
1462 &mrioc->sysif_regs->write_sequence);
1463 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_4TH,
1464 &mrioc->sysif_regs->write_sequence);
1465 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_5TH,
1466 &mrioc->sysif_regs->write_sequence);
1467 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_6TH,
1468 &mrioc->sysif_regs->write_sequence);
1469 usleep_range(1000, 1100);
1470 host_diagnostic = readl(&mrioc->sysif_regs->host_diagnostic);
1471 ioc_info(mrioc,
1472 "wrote magic sequence: retry_count(%d), host_diagnostic(0x%08x)\n",
1473 unlock_retry_count, host_diagnostic);
1474 } while (!(host_diagnostic & MPI3_SYSIF_HOST_DIAG_DIAG_WRITE_ENABLE));
1475
1476 writel(reset_reason, &mrioc->sysif_regs->scratchpad[0]);
1477 writel(host_diagnostic | reset_type,
1478 &mrioc->sysif_regs->host_diagnostic);
1479 switch (reset_type) {
1480 case MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET:
1481 do {
1482 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1483 ioc_config =
1484 readl(&mrioc->sysif_regs->ioc_configuration);
1485 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY)
1486 && mpi3mr_soft_reset_success(ioc_status, ioc_config)
1487 ) {
1488 mpi3mr_clear_reset_history(mrioc);
1489 retval = 0;
1490 break;
1491 }
1492 msleep(100);
1493 } while (--timeout);
1494 mpi3mr_print_fault_info(mrioc);
1495 break;
1496 case MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT:
1497 do {
1498 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1499 if (mpi3mr_diagfault_success(mrioc, ioc_status)) {
1500 retval = 0;
1501 break;
1502 }
1503 msleep(100);
1504 } while (--timeout);
1505 break;
1506 default:
1507 break;
1508 }
1509
1510 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_2ND,
1511 &mrioc->sysif_regs->write_sequence);
1512
1513 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
1514 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1515 ioc_info(mrioc,
1516 "ioc_status/ioc_onfig after %s reset is (0x%x)/(0x%x)\n",
1517 (!retval)?"successful":"failed", ioc_status,
1518 ioc_config);
1519 if (retval)
1520 mrioc->unrecoverable = 1;
1521 return retval;
1522 }
1523
1524 /**
1525 * mpi3mr_admin_request_post - Post request to admin queue
1526 * @mrioc: Adapter reference
1527 * @admin_req: MPI3 request
1528 * @admin_req_sz: Request size
1529 * @ignore_reset: Ignore reset in process
1530 *
1531 * Post the MPI3 request into admin request queue and
1532 * inform the controller, if the queue is full return
1533 * appropriate error.
1534 *
1535 * Return: 0 on success, non-zero on failure.
1536 */
mpi3mr_admin_request_post(struct mpi3mr_ioc * mrioc,void * admin_req,u16 admin_req_sz,u8 ignore_reset)1537 int mpi3mr_admin_request_post(struct mpi3mr_ioc *mrioc, void *admin_req,
1538 u16 admin_req_sz, u8 ignore_reset)
1539 {
1540 u16 areq_pi = 0, areq_ci = 0, max_entries = 0;
1541 int retval = 0;
1542 unsigned long flags;
1543 u8 *areq_entry;
1544
1545 if (mrioc->unrecoverable) {
1546 ioc_err(mrioc, "%s : Unrecoverable controller\n", __func__);
1547 return -EFAULT;
1548 }
1549
1550 spin_lock_irqsave(&mrioc->admin_req_lock, flags);
1551 areq_pi = mrioc->admin_req_pi;
1552 areq_ci = mrioc->admin_req_ci;
1553 max_entries = mrioc->num_admin_req;
1554 if ((areq_ci == (areq_pi + 1)) || ((!areq_ci) &&
1555 (areq_pi == (max_entries - 1)))) {
1556 ioc_err(mrioc, "AdminReqQ full condition detected\n");
1557 retval = -EAGAIN;
1558 goto out;
1559 }
1560 if (!ignore_reset && mrioc->reset_in_progress) {
1561 ioc_err(mrioc, "AdminReqQ submit reset in progress\n");
1562 retval = -EAGAIN;
1563 goto out;
1564 }
1565 areq_entry = (u8 *)mrioc->admin_req_base +
1566 (areq_pi * MPI3MR_ADMIN_REQ_FRAME_SZ);
1567 memset(areq_entry, 0, MPI3MR_ADMIN_REQ_FRAME_SZ);
1568 memcpy(areq_entry, (u8 *)admin_req, admin_req_sz);
1569
1570 if (++areq_pi == max_entries)
1571 areq_pi = 0;
1572 mrioc->admin_req_pi = areq_pi;
1573
1574 writel(mrioc->admin_req_pi, &mrioc->sysif_regs->admin_request_queue_pi);
1575
1576 out:
1577 spin_unlock_irqrestore(&mrioc->admin_req_lock, flags);
1578
1579 return retval;
1580 }
1581
1582 /**
1583 * mpi3mr_free_op_req_q_segments - free request memory segments
1584 * @mrioc: Adapter instance reference
1585 * @q_idx: operational request queue index
1586 *
1587 * Free memory segments allocated for operational request queue
1588 *
1589 * Return: Nothing.
1590 */
mpi3mr_free_op_req_q_segments(struct mpi3mr_ioc * mrioc,u16 q_idx)1591 static void mpi3mr_free_op_req_q_segments(struct mpi3mr_ioc *mrioc, u16 q_idx)
1592 {
1593 u16 j;
1594 int size;
1595 struct segments *segments;
1596
1597 segments = mrioc->req_qinfo[q_idx].q_segments;
1598 if (!segments)
1599 return;
1600
1601 if (mrioc->enable_segqueue) {
1602 size = MPI3MR_OP_REQ_Q_SEG_SIZE;
1603 if (mrioc->req_qinfo[q_idx].q_segment_list) {
1604 dma_free_coherent(&mrioc->pdev->dev,
1605 MPI3MR_MAX_SEG_LIST_SIZE,
1606 mrioc->req_qinfo[q_idx].q_segment_list,
1607 mrioc->req_qinfo[q_idx].q_segment_list_dma);
1608 mrioc->req_qinfo[q_idx].q_segment_list = NULL;
1609 }
1610 } else
1611 size = mrioc->req_qinfo[q_idx].segment_qd *
1612 mrioc->facts.op_req_sz;
1613
1614 for (j = 0; j < mrioc->req_qinfo[q_idx].num_segments; j++) {
1615 if (!segments[j].segment)
1616 continue;
1617 dma_free_coherent(&mrioc->pdev->dev,
1618 size, segments[j].segment, segments[j].segment_dma);
1619 segments[j].segment = NULL;
1620 }
1621 kfree(mrioc->req_qinfo[q_idx].q_segments);
1622 mrioc->req_qinfo[q_idx].q_segments = NULL;
1623 mrioc->req_qinfo[q_idx].qid = 0;
1624 }
1625
1626 /**
1627 * mpi3mr_free_op_reply_q_segments - free reply memory segments
1628 * @mrioc: Adapter instance reference
1629 * @q_idx: operational reply queue index
1630 *
1631 * Free memory segments allocated for operational reply queue
1632 *
1633 * Return: Nothing.
1634 */
mpi3mr_free_op_reply_q_segments(struct mpi3mr_ioc * mrioc,u16 q_idx)1635 static void mpi3mr_free_op_reply_q_segments(struct mpi3mr_ioc *mrioc, u16 q_idx)
1636 {
1637 u16 j;
1638 int size;
1639 struct segments *segments;
1640
1641 segments = mrioc->op_reply_qinfo[q_idx].q_segments;
1642 if (!segments)
1643 return;
1644
1645 if (mrioc->enable_segqueue) {
1646 size = MPI3MR_OP_REP_Q_SEG_SIZE;
1647 if (mrioc->op_reply_qinfo[q_idx].q_segment_list) {
1648 dma_free_coherent(&mrioc->pdev->dev,
1649 MPI3MR_MAX_SEG_LIST_SIZE,
1650 mrioc->op_reply_qinfo[q_idx].q_segment_list,
1651 mrioc->op_reply_qinfo[q_idx].q_segment_list_dma);
1652 mrioc->op_reply_qinfo[q_idx].q_segment_list = NULL;
1653 }
1654 } else
1655 size = mrioc->op_reply_qinfo[q_idx].segment_qd *
1656 mrioc->op_reply_desc_sz;
1657
1658 for (j = 0; j < mrioc->op_reply_qinfo[q_idx].num_segments; j++) {
1659 if (!segments[j].segment)
1660 continue;
1661 dma_free_coherent(&mrioc->pdev->dev,
1662 size, segments[j].segment, segments[j].segment_dma);
1663 segments[j].segment = NULL;
1664 }
1665
1666 kfree(mrioc->op_reply_qinfo[q_idx].q_segments);
1667 mrioc->op_reply_qinfo[q_idx].q_segments = NULL;
1668 mrioc->op_reply_qinfo[q_idx].qid = 0;
1669 }
1670
1671 /**
1672 * mpi3mr_delete_op_reply_q - delete operational reply queue
1673 * @mrioc: Adapter instance reference
1674 * @qidx: operational reply queue index
1675 *
1676 * Delete operatinal reply queue by issuing MPI request
1677 * through admin queue.
1678 *
1679 * Return: 0 on success, non-zero on failure.
1680 */
mpi3mr_delete_op_reply_q(struct mpi3mr_ioc * mrioc,u16 qidx)1681 static int mpi3mr_delete_op_reply_q(struct mpi3mr_ioc *mrioc, u16 qidx)
1682 {
1683 struct mpi3_delete_reply_queue_request delq_req;
1684 struct op_reply_qinfo *op_reply_q = mrioc->op_reply_qinfo + qidx;
1685 int retval = 0;
1686 u16 reply_qid = 0, midx;
1687
1688 reply_qid = op_reply_q->qid;
1689
1690 midx = REPLY_QUEUE_IDX_TO_MSIX_IDX(qidx, mrioc->op_reply_q_offset);
1691
1692 if (!reply_qid) {
1693 retval = -1;
1694 ioc_err(mrioc, "Issue DelRepQ: called with invalid ReqQID\n");
1695 goto out;
1696 }
1697
1698 (op_reply_q->qtype == MPI3MR_DEFAULT_QUEUE) ? mrioc->default_qcount-- :
1699 mrioc->active_poll_qcount--;
1700
1701 memset(&delq_req, 0, sizeof(delq_req));
1702 mutex_lock(&mrioc->init_cmds.mutex);
1703 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
1704 retval = -1;
1705 ioc_err(mrioc, "Issue DelRepQ: Init command is in use\n");
1706 mutex_unlock(&mrioc->init_cmds.mutex);
1707 goto out;
1708 }
1709 mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
1710 mrioc->init_cmds.is_waiting = 1;
1711 mrioc->init_cmds.callback = NULL;
1712 delq_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
1713 delq_req.function = MPI3_FUNCTION_DELETE_REPLY_QUEUE;
1714 delq_req.queue_id = cpu_to_le16(reply_qid);
1715
1716 init_completion(&mrioc->init_cmds.done);
1717 retval = mpi3mr_admin_request_post(mrioc, &delq_req, sizeof(delq_req),
1718 1);
1719 if (retval) {
1720 ioc_err(mrioc, "Issue DelRepQ: Admin Post failed\n");
1721 goto out_unlock;
1722 }
1723 wait_for_completion_timeout(&mrioc->init_cmds.done,
1724 (MPI3MR_INTADMCMD_TIMEOUT * HZ));
1725 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
1726 ioc_err(mrioc, "delete reply queue timed out\n");
1727 mpi3mr_check_rh_fault_ioc(mrioc,
1728 MPI3MR_RESET_FROM_DELREPQ_TIMEOUT);
1729 retval = -1;
1730 goto out_unlock;
1731 }
1732 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
1733 != MPI3_IOCSTATUS_SUCCESS) {
1734 ioc_err(mrioc,
1735 "Issue DelRepQ: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
1736 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK),
1737 mrioc->init_cmds.ioc_loginfo);
1738 retval = -1;
1739 goto out_unlock;
1740 }
1741 mrioc->intr_info[midx].op_reply_q = NULL;
1742
1743 mpi3mr_free_op_reply_q_segments(mrioc, qidx);
1744 out_unlock:
1745 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
1746 mutex_unlock(&mrioc->init_cmds.mutex);
1747 out:
1748
1749 return retval;
1750 }
1751
1752 /**
1753 * mpi3mr_alloc_op_reply_q_segments -Alloc segmented reply pool
1754 * @mrioc: Adapter instance reference
1755 * @qidx: request queue index
1756 *
1757 * Allocate segmented memory pools for operational reply
1758 * queue.
1759 *
1760 * Return: 0 on success, non-zero on failure.
1761 */
mpi3mr_alloc_op_reply_q_segments(struct mpi3mr_ioc * mrioc,u16 qidx)1762 static int mpi3mr_alloc_op_reply_q_segments(struct mpi3mr_ioc *mrioc, u16 qidx)
1763 {
1764 struct op_reply_qinfo *op_reply_q = mrioc->op_reply_qinfo + qidx;
1765 int i, size;
1766 u64 *q_segment_list_entry = NULL;
1767 struct segments *segments;
1768
1769 if (mrioc->enable_segqueue) {
1770 op_reply_q->segment_qd =
1771 MPI3MR_OP_REP_Q_SEG_SIZE / mrioc->op_reply_desc_sz;
1772
1773 size = MPI3MR_OP_REP_Q_SEG_SIZE;
1774
1775 op_reply_q->q_segment_list = dma_alloc_coherent(&mrioc->pdev->dev,
1776 MPI3MR_MAX_SEG_LIST_SIZE, &op_reply_q->q_segment_list_dma,
1777 GFP_KERNEL);
1778 if (!op_reply_q->q_segment_list)
1779 return -ENOMEM;
1780 q_segment_list_entry = (u64 *)op_reply_q->q_segment_list;
1781 } else {
1782 op_reply_q->segment_qd = op_reply_q->num_replies;
1783 size = op_reply_q->num_replies * mrioc->op_reply_desc_sz;
1784 }
1785
1786 op_reply_q->num_segments = DIV_ROUND_UP(op_reply_q->num_replies,
1787 op_reply_q->segment_qd);
1788
1789 op_reply_q->q_segments = kcalloc(op_reply_q->num_segments,
1790 sizeof(struct segments), GFP_KERNEL);
1791 if (!op_reply_q->q_segments)
1792 return -ENOMEM;
1793
1794 segments = op_reply_q->q_segments;
1795 for (i = 0; i < op_reply_q->num_segments; i++) {
1796 segments[i].segment =
1797 dma_alloc_coherent(&mrioc->pdev->dev,
1798 size, &segments[i].segment_dma, GFP_KERNEL);
1799 if (!segments[i].segment)
1800 return -ENOMEM;
1801 if (mrioc->enable_segqueue)
1802 q_segment_list_entry[i] =
1803 (unsigned long)segments[i].segment_dma;
1804 }
1805
1806 return 0;
1807 }
1808
1809 /**
1810 * mpi3mr_alloc_op_req_q_segments - Alloc segmented req pool.
1811 * @mrioc: Adapter instance reference
1812 * @qidx: request queue index
1813 *
1814 * Allocate segmented memory pools for operational request
1815 * queue.
1816 *
1817 * Return: 0 on success, non-zero on failure.
1818 */
mpi3mr_alloc_op_req_q_segments(struct mpi3mr_ioc * mrioc,u16 qidx)1819 static int mpi3mr_alloc_op_req_q_segments(struct mpi3mr_ioc *mrioc, u16 qidx)
1820 {
1821 struct op_req_qinfo *op_req_q = mrioc->req_qinfo + qidx;
1822 int i, size;
1823 u64 *q_segment_list_entry = NULL;
1824 struct segments *segments;
1825
1826 if (mrioc->enable_segqueue) {
1827 op_req_q->segment_qd =
1828 MPI3MR_OP_REQ_Q_SEG_SIZE / mrioc->facts.op_req_sz;
1829
1830 size = MPI3MR_OP_REQ_Q_SEG_SIZE;
1831
1832 op_req_q->q_segment_list = dma_alloc_coherent(&mrioc->pdev->dev,
1833 MPI3MR_MAX_SEG_LIST_SIZE, &op_req_q->q_segment_list_dma,
1834 GFP_KERNEL);
1835 if (!op_req_q->q_segment_list)
1836 return -ENOMEM;
1837 q_segment_list_entry = (u64 *)op_req_q->q_segment_list;
1838
1839 } else {
1840 op_req_q->segment_qd = op_req_q->num_requests;
1841 size = op_req_q->num_requests * mrioc->facts.op_req_sz;
1842 }
1843
1844 op_req_q->num_segments = DIV_ROUND_UP(op_req_q->num_requests,
1845 op_req_q->segment_qd);
1846
1847 op_req_q->q_segments = kcalloc(op_req_q->num_segments,
1848 sizeof(struct segments), GFP_KERNEL);
1849 if (!op_req_q->q_segments)
1850 return -ENOMEM;
1851
1852 segments = op_req_q->q_segments;
1853 for (i = 0; i < op_req_q->num_segments; i++) {
1854 segments[i].segment =
1855 dma_alloc_coherent(&mrioc->pdev->dev,
1856 size, &segments[i].segment_dma, GFP_KERNEL);
1857 if (!segments[i].segment)
1858 return -ENOMEM;
1859 if (mrioc->enable_segqueue)
1860 q_segment_list_entry[i] =
1861 (unsigned long)segments[i].segment_dma;
1862 }
1863
1864 return 0;
1865 }
1866
1867 /**
1868 * mpi3mr_create_op_reply_q - create operational reply queue
1869 * @mrioc: Adapter instance reference
1870 * @qidx: operational reply queue index
1871 *
1872 * Create operatinal reply queue by issuing MPI request
1873 * through admin queue.
1874 *
1875 * Return: 0 on success, non-zero on failure.
1876 */
mpi3mr_create_op_reply_q(struct mpi3mr_ioc * mrioc,u16 qidx)1877 static int mpi3mr_create_op_reply_q(struct mpi3mr_ioc *mrioc, u16 qidx)
1878 {
1879 struct mpi3_create_reply_queue_request create_req;
1880 struct op_reply_qinfo *op_reply_q = mrioc->op_reply_qinfo + qidx;
1881 int retval = 0;
1882 u16 reply_qid = 0, midx;
1883
1884 reply_qid = op_reply_q->qid;
1885
1886 midx = REPLY_QUEUE_IDX_TO_MSIX_IDX(qidx, mrioc->op_reply_q_offset);
1887
1888 if (reply_qid) {
1889 retval = -1;
1890 ioc_err(mrioc, "CreateRepQ: called for duplicate qid %d\n",
1891 reply_qid);
1892
1893 return retval;
1894 }
1895
1896 reply_qid = qidx + 1;
1897 op_reply_q->num_replies = MPI3MR_OP_REP_Q_QD;
1898 if ((mrioc->pdev->device == MPI3_MFGPAGE_DEVID_SAS4116) &&
1899 !mrioc->pdev->revision)
1900 op_reply_q->num_replies = MPI3MR_OP_REP_Q_QD4K;
1901 op_reply_q->ci = 0;
1902 op_reply_q->ephase = 1;
1903 atomic_set(&op_reply_q->pend_ios, 0);
1904 atomic_set(&op_reply_q->in_use, 0);
1905 op_reply_q->enable_irq_poll = false;
1906
1907 if (!op_reply_q->q_segments) {
1908 retval = mpi3mr_alloc_op_reply_q_segments(mrioc, qidx);
1909 if (retval) {
1910 mpi3mr_free_op_reply_q_segments(mrioc, qidx);
1911 goto out;
1912 }
1913 }
1914
1915 memset(&create_req, 0, sizeof(create_req));
1916 mutex_lock(&mrioc->init_cmds.mutex);
1917 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
1918 retval = -1;
1919 ioc_err(mrioc, "CreateRepQ: Init command is in use\n");
1920 goto out_unlock;
1921 }
1922 mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
1923 mrioc->init_cmds.is_waiting = 1;
1924 mrioc->init_cmds.callback = NULL;
1925 create_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
1926 create_req.function = MPI3_FUNCTION_CREATE_REPLY_QUEUE;
1927 create_req.queue_id = cpu_to_le16(reply_qid);
1928
1929 if (midx < (mrioc->intr_info_count - mrioc->requested_poll_qcount))
1930 op_reply_q->qtype = MPI3MR_DEFAULT_QUEUE;
1931 else
1932 op_reply_q->qtype = MPI3MR_POLL_QUEUE;
1933
1934 if (op_reply_q->qtype == MPI3MR_DEFAULT_QUEUE) {
1935 create_req.flags =
1936 MPI3_CREATE_REPLY_QUEUE_FLAGS_INT_ENABLE_ENABLE;
1937 create_req.msix_index =
1938 cpu_to_le16(mrioc->intr_info[midx].msix_index);
1939 } else {
1940 create_req.msix_index = cpu_to_le16(mrioc->intr_info_count - 1);
1941 ioc_info(mrioc, "create reply queue(polled): for qid(%d), midx(%d)\n",
1942 reply_qid, midx);
1943 if (!mrioc->active_poll_qcount)
1944 disable_irq_nosync(pci_irq_vector(mrioc->pdev,
1945 mrioc->intr_info_count - 1));
1946 }
1947
1948 if (mrioc->enable_segqueue) {
1949 create_req.flags |=
1950 MPI3_CREATE_REQUEST_QUEUE_FLAGS_SEGMENTED_SEGMENTED;
1951 create_req.base_address = cpu_to_le64(
1952 op_reply_q->q_segment_list_dma);
1953 } else
1954 create_req.base_address = cpu_to_le64(
1955 op_reply_q->q_segments[0].segment_dma);
1956
1957 create_req.size = cpu_to_le16(op_reply_q->num_replies);
1958
1959 init_completion(&mrioc->init_cmds.done);
1960 retval = mpi3mr_admin_request_post(mrioc, &create_req,
1961 sizeof(create_req), 1);
1962 if (retval) {
1963 ioc_err(mrioc, "CreateRepQ: Admin Post failed\n");
1964 goto out_unlock;
1965 }
1966 wait_for_completion_timeout(&mrioc->init_cmds.done,
1967 (MPI3MR_INTADMCMD_TIMEOUT * HZ));
1968 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
1969 ioc_err(mrioc, "create reply queue timed out\n");
1970 mpi3mr_check_rh_fault_ioc(mrioc,
1971 MPI3MR_RESET_FROM_CREATEREPQ_TIMEOUT);
1972 retval = -1;
1973 goto out_unlock;
1974 }
1975 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
1976 != MPI3_IOCSTATUS_SUCCESS) {
1977 ioc_err(mrioc,
1978 "CreateRepQ: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
1979 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK),
1980 mrioc->init_cmds.ioc_loginfo);
1981 retval = -1;
1982 goto out_unlock;
1983 }
1984 op_reply_q->qid = reply_qid;
1985 if (midx < mrioc->intr_info_count)
1986 mrioc->intr_info[midx].op_reply_q = op_reply_q;
1987
1988 (op_reply_q->qtype == MPI3MR_DEFAULT_QUEUE) ? mrioc->default_qcount++ :
1989 mrioc->active_poll_qcount++;
1990
1991 out_unlock:
1992 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
1993 mutex_unlock(&mrioc->init_cmds.mutex);
1994 out:
1995
1996 return retval;
1997 }
1998
1999 /**
2000 * mpi3mr_create_op_req_q - create operational request queue
2001 * @mrioc: Adapter instance reference
2002 * @idx: operational request queue index
2003 * @reply_qid: Reply queue ID
2004 *
2005 * Create operatinal request queue by issuing MPI request
2006 * through admin queue.
2007 *
2008 * Return: 0 on success, non-zero on failure.
2009 */
mpi3mr_create_op_req_q(struct mpi3mr_ioc * mrioc,u16 idx,u16 reply_qid)2010 static int mpi3mr_create_op_req_q(struct mpi3mr_ioc *mrioc, u16 idx,
2011 u16 reply_qid)
2012 {
2013 struct mpi3_create_request_queue_request create_req;
2014 struct op_req_qinfo *op_req_q = mrioc->req_qinfo + idx;
2015 int retval = 0;
2016 u16 req_qid = 0;
2017
2018 req_qid = op_req_q->qid;
2019
2020 if (req_qid) {
2021 retval = -1;
2022 ioc_err(mrioc, "CreateReqQ: called for duplicate qid %d\n",
2023 req_qid);
2024
2025 return retval;
2026 }
2027 req_qid = idx + 1;
2028
2029 op_req_q->num_requests = MPI3MR_OP_REQ_Q_QD;
2030 op_req_q->ci = 0;
2031 op_req_q->pi = 0;
2032 op_req_q->reply_qid = reply_qid;
2033 spin_lock_init(&op_req_q->q_lock);
2034
2035 if (!op_req_q->q_segments) {
2036 retval = mpi3mr_alloc_op_req_q_segments(mrioc, idx);
2037 if (retval) {
2038 mpi3mr_free_op_req_q_segments(mrioc, idx);
2039 goto out;
2040 }
2041 }
2042
2043 memset(&create_req, 0, sizeof(create_req));
2044 mutex_lock(&mrioc->init_cmds.mutex);
2045 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
2046 retval = -1;
2047 ioc_err(mrioc, "CreateReqQ: Init command is in use\n");
2048 goto out_unlock;
2049 }
2050 mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
2051 mrioc->init_cmds.is_waiting = 1;
2052 mrioc->init_cmds.callback = NULL;
2053 create_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
2054 create_req.function = MPI3_FUNCTION_CREATE_REQUEST_QUEUE;
2055 create_req.queue_id = cpu_to_le16(req_qid);
2056 if (mrioc->enable_segqueue) {
2057 create_req.flags =
2058 MPI3_CREATE_REQUEST_QUEUE_FLAGS_SEGMENTED_SEGMENTED;
2059 create_req.base_address = cpu_to_le64(
2060 op_req_q->q_segment_list_dma);
2061 } else
2062 create_req.base_address = cpu_to_le64(
2063 op_req_q->q_segments[0].segment_dma);
2064 create_req.reply_queue_id = cpu_to_le16(reply_qid);
2065 create_req.size = cpu_to_le16(op_req_q->num_requests);
2066
2067 init_completion(&mrioc->init_cmds.done);
2068 retval = mpi3mr_admin_request_post(mrioc, &create_req,
2069 sizeof(create_req), 1);
2070 if (retval) {
2071 ioc_err(mrioc, "CreateReqQ: Admin Post failed\n");
2072 goto out_unlock;
2073 }
2074 wait_for_completion_timeout(&mrioc->init_cmds.done,
2075 (MPI3MR_INTADMCMD_TIMEOUT * HZ));
2076 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
2077 ioc_err(mrioc, "create request queue timed out\n");
2078 mpi3mr_check_rh_fault_ioc(mrioc,
2079 MPI3MR_RESET_FROM_CREATEREQQ_TIMEOUT);
2080 retval = -1;
2081 goto out_unlock;
2082 }
2083 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
2084 != MPI3_IOCSTATUS_SUCCESS) {
2085 ioc_err(mrioc,
2086 "CreateReqQ: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
2087 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK),
2088 mrioc->init_cmds.ioc_loginfo);
2089 retval = -1;
2090 goto out_unlock;
2091 }
2092 op_req_q->qid = req_qid;
2093
2094 out_unlock:
2095 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
2096 mutex_unlock(&mrioc->init_cmds.mutex);
2097 out:
2098
2099 return retval;
2100 }
2101
2102 /**
2103 * mpi3mr_create_op_queues - create operational queue pairs
2104 * @mrioc: Adapter instance reference
2105 *
2106 * Allocate memory for operational queue meta data and call
2107 * create request and reply queue functions.
2108 *
2109 * Return: 0 on success, non-zero on failures.
2110 */
mpi3mr_create_op_queues(struct mpi3mr_ioc * mrioc)2111 static int mpi3mr_create_op_queues(struct mpi3mr_ioc *mrioc)
2112 {
2113 int retval = 0;
2114 u16 num_queues = 0, i = 0, msix_count_op_q = 1;
2115
2116 num_queues = min_t(int, mrioc->facts.max_op_reply_q,
2117 mrioc->facts.max_op_req_q);
2118
2119 msix_count_op_q =
2120 mrioc->intr_info_count - mrioc->op_reply_q_offset;
2121 if (!mrioc->num_queues)
2122 mrioc->num_queues = min_t(int, num_queues, msix_count_op_q);
2123 /*
2124 * During reset set the num_queues to the number of queues
2125 * that was set before the reset.
2126 */
2127 num_queues = mrioc->num_op_reply_q ?
2128 mrioc->num_op_reply_q : mrioc->num_queues;
2129 ioc_info(mrioc, "trying to create %d operational queue pairs\n",
2130 num_queues);
2131
2132 if (!mrioc->req_qinfo) {
2133 mrioc->req_qinfo = kcalloc(num_queues,
2134 sizeof(struct op_req_qinfo), GFP_KERNEL);
2135 if (!mrioc->req_qinfo) {
2136 retval = -1;
2137 goto out_failed;
2138 }
2139
2140 mrioc->op_reply_qinfo = kzalloc(sizeof(struct op_reply_qinfo) *
2141 num_queues, GFP_KERNEL);
2142 if (!mrioc->op_reply_qinfo) {
2143 retval = -1;
2144 goto out_failed;
2145 }
2146 }
2147
2148 if (mrioc->enable_segqueue)
2149 ioc_info(mrioc,
2150 "allocating operational queues through segmented queues\n");
2151
2152 for (i = 0; i < num_queues; i++) {
2153 if (mpi3mr_create_op_reply_q(mrioc, i)) {
2154 ioc_err(mrioc, "Cannot create OP RepQ %d\n", i);
2155 break;
2156 }
2157 if (mpi3mr_create_op_req_q(mrioc, i,
2158 mrioc->op_reply_qinfo[i].qid)) {
2159 ioc_err(mrioc, "Cannot create OP ReqQ %d\n", i);
2160 mpi3mr_delete_op_reply_q(mrioc, i);
2161 break;
2162 }
2163 }
2164
2165 if (i == 0) {
2166 /* Not even one queue is created successfully*/
2167 retval = -1;
2168 goto out_failed;
2169 }
2170 mrioc->num_op_reply_q = mrioc->num_op_req_q = i;
2171 ioc_info(mrioc,
2172 "successfully created %d operational queue pairs(default/polled) queue = (%d/%d)\n",
2173 mrioc->num_op_reply_q, mrioc->default_qcount,
2174 mrioc->active_poll_qcount);
2175
2176 return retval;
2177 out_failed:
2178 kfree(mrioc->req_qinfo);
2179 mrioc->req_qinfo = NULL;
2180
2181 kfree(mrioc->op_reply_qinfo);
2182 mrioc->op_reply_qinfo = NULL;
2183
2184 return retval;
2185 }
2186
2187 /**
2188 * mpi3mr_op_request_post - Post request to operational queue
2189 * @mrioc: Adapter reference
2190 * @op_req_q: Operational request queue info
2191 * @req: MPI3 request
2192 *
2193 * Post the MPI3 request into operational request queue and
2194 * inform the controller, if the queue is full return
2195 * appropriate error.
2196 *
2197 * Return: 0 on success, non-zero on failure.
2198 */
mpi3mr_op_request_post(struct mpi3mr_ioc * mrioc,struct op_req_qinfo * op_req_q,u8 * req)2199 int mpi3mr_op_request_post(struct mpi3mr_ioc *mrioc,
2200 struct op_req_qinfo *op_req_q, u8 *req)
2201 {
2202 u16 pi = 0, max_entries, reply_qidx = 0, midx;
2203 int retval = 0;
2204 unsigned long flags;
2205 u8 *req_entry;
2206 void *segment_base_addr;
2207 u16 req_sz = mrioc->facts.op_req_sz;
2208 struct segments *segments = op_req_q->q_segments;
2209
2210 reply_qidx = op_req_q->reply_qid - 1;
2211
2212 if (mrioc->unrecoverable)
2213 return -EFAULT;
2214
2215 spin_lock_irqsave(&op_req_q->q_lock, flags);
2216 pi = op_req_q->pi;
2217 max_entries = op_req_q->num_requests;
2218
2219 if (mpi3mr_check_req_qfull(op_req_q)) {
2220 midx = REPLY_QUEUE_IDX_TO_MSIX_IDX(
2221 reply_qidx, mrioc->op_reply_q_offset);
2222 mpi3mr_process_op_reply_q(mrioc, mrioc->intr_info[midx].op_reply_q);
2223
2224 if (mpi3mr_check_req_qfull(op_req_q)) {
2225 retval = -EAGAIN;
2226 goto out;
2227 }
2228 }
2229
2230 if (mrioc->reset_in_progress) {
2231 ioc_err(mrioc, "OpReqQ submit reset in progress\n");
2232 retval = -EAGAIN;
2233 goto out;
2234 }
2235
2236 segment_base_addr = segments[pi / op_req_q->segment_qd].segment;
2237 req_entry = (u8 *)segment_base_addr +
2238 ((pi % op_req_q->segment_qd) * req_sz);
2239
2240 memset(req_entry, 0, req_sz);
2241 memcpy(req_entry, req, MPI3MR_ADMIN_REQ_FRAME_SZ);
2242
2243 if (++pi == max_entries)
2244 pi = 0;
2245 op_req_q->pi = pi;
2246
2247 #ifndef CONFIG_PREEMPT_RT
2248 if (atomic_inc_return(&mrioc->op_reply_qinfo[reply_qidx].pend_ios)
2249 > MPI3MR_IRQ_POLL_TRIGGER_IOCOUNT)
2250 mrioc->op_reply_qinfo[reply_qidx].enable_irq_poll = true;
2251 #else
2252 atomic_inc_return(&mrioc->op_reply_qinfo[reply_qidx].pend_ios);
2253 #endif
2254
2255 writel(op_req_q->pi,
2256 &mrioc->sysif_regs->oper_queue_indexes[reply_qidx].producer_index);
2257
2258 out:
2259 spin_unlock_irqrestore(&op_req_q->q_lock, flags);
2260 return retval;
2261 }
2262
2263 /**
2264 * mpi3mr_check_rh_fault_ioc - check reset history and fault
2265 * controller
2266 * @mrioc: Adapter instance reference
2267 * @reason_code: reason code for the fault.
2268 *
2269 * This routine will save snapdump and fault the controller with
2270 * the given reason code if it is not already in the fault or
2271 * not asynchronosuly reset. This will be used to handle
2272 * initilaization time faults/resets/timeout as in those cases
2273 * immediate soft reset invocation is not required.
2274 *
2275 * Return: None.
2276 */
mpi3mr_check_rh_fault_ioc(struct mpi3mr_ioc * mrioc,u32 reason_code)2277 void mpi3mr_check_rh_fault_ioc(struct mpi3mr_ioc *mrioc, u32 reason_code)
2278 {
2279 u32 ioc_status, host_diagnostic, timeout;
2280
2281 if (mrioc->unrecoverable) {
2282 ioc_err(mrioc, "controller is unrecoverable\n");
2283 return;
2284 }
2285
2286 if (!pci_device_is_present(mrioc->pdev)) {
2287 mrioc->unrecoverable = 1;
2288 ioc_err(mrioc, "controller is not present\n");
2289 return;
2290 }
2291
2292 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
2293 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY) ||
2294 (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT)) {
2295 mpi3mr_print_fault_info(mrioc);
2296 return;
2297 }
2298 mpi3mr_set_diagsave(mrioc);
2299 mpi3mr_issue_reset(mrioc, MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT,
2300 reason_code);
2301 timeout = MPI3_SYSIF_DIAG_SAVE_TIMEOUT * 10;
2302 do {
2303 host_diagnostic = readl(&mrioc->sysif_regs->host_diagnostic);
2304 if (!(host_diagnostic & MPI3_SYSIF_HOST_DIAG_SAVE_IN_PROGRESS))
2305 break;
2306 msleep(100);
2307 } while (--timeout);
2308 }
2309
2310 /**
2311 * mpi3mr_sync_timestamp - Issue time stamp sync request
2312 * @mrioc: Adapter reference
2313 *
2314 * Issue IO unit control MPI request to synchornize firmware
2315 * timestamp with host time.
2316 *
2317 * Return: 0 on success, non-zero on failure.
2318 */
mpi3mr_sync_timestamp(struct mpi3mr_ioc * mrioc)2319 static int mpi3mr_sync_timestamp(struct mpi3mr_ioc *mrioc)
2320 {
2321 ktime_t current_time;
2322 struct mpi3_iounit_control_request iou_ctrl;
2323 int retval = 0;
2324
2325 memset(&iou_ctrl, 0, sizeof(iou_ctrl));
2326 mutex_lock(&mrioc->init_cmds.mutex);
2327 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
2328 retval = -1;
2329 ioc_err(mrioc, "Issue IOUCTL time_stamp: command is in use\n");
2330 mutex_unlock(&mrioc->init_cmds.mutex);
2331 goto out;
2332 }
2333 mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
2334 mrioc->init_cmds.is_waiting = 1;
2335 mrioc->init_cmds.callback = NULL;
2336 iou_ctrl.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
2337 iou_ctrl.function = MPI3_FUNCTION_IO_UNIT_CONTROL;
2338 iou_ctrl.operation = MPI3_CTRL_OP_UPDATE_TIMESTAMP;
2339 current_time = ktime_get_real();
2340 iou_ctrl.param64[0] = cpu_to_le64(ktime_to_ms(current_time));
2341
2342 init_completion(&mrioc->init_cmds.done);
2343 retval = mpi3mr_admin_request_post(mrioc, &iou_ctrl,
2344 sizeof(iou_ctrl), 0);
2345 if (retval) {
2346 ioc_err(mrioc, "Issue IOUCTL time_stamp: Admin Post failed\n");
2347 goto out_unlock;
2348 }
2349
2350 wait_for_completion_timeout(&mrioc->init_cmds.done,
2351 (MPI3MR_INTADMCMD_TIMEOUT * HZ));
2352 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
2353 ioc_err(mrioc, "Issue IOUCTL time_stamp: command timed out\n");
2354 mrioc->init_cmds.is_waiting = 0;
2355 if (!(mrioc->init_cmds.state & MPI3MR_CMD_RESET))
2356 mpi3mr_check_rh_fault_ioc(mrioc,
2357 MPI3MR_RESET_FROM_TSU_TIMEOUT);
2358 retval = -1;
2359 goto out_unlock;
2360 }
2361 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
2362 != MPI3_IOCSTATUS_SUCCESS) {
2363 ioc_err(mrioc,
2364 "Issue IOUCTL time_stamp: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
2365 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK),
2366 mrioc->init_cmds.ioc_loginfo);
2367 retval = -1;
2368 goto out_unlock;
2369 }
2370
2371 out_unlock:
2372 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
2373 mutex_unlock(&mrioc->init_cmds.mutex);
2374
2375 out:
2376 return retval;
2377 }
2378
2379 /**
2380 * mpi3mr_print_pkg_ver - display controller fw package version
2381 * @mrioc: Adapter reference
2382 *
2383 * Retrieve firmware package version from the component image
2384 * header of the controller flash and display it.
2385 *
2386 * Return: 0 on success and non-zero on failure.
2387 */
mpi3mr_print_pkg_ver(struct mpi3mr_ioc * mrioc)2388 static int mpi3mr_print_pkg_ver(struct mpi3mr_ioc *mrioc)
2389 {
2390 struct mpi3_ci_upload_request ci_upload;
2391 int retval = -1;
2392 void *data = NULL;
2393 dma_addr_t data_dma;
2394 struct mpi3_ci_manifest_mpi *manifest;
2395 u32 data_len = sizeof(struct mpi3_ci_manifest_mpi);
2396 u8 sgl_flags = MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST;
2397
2398 data = dma_alloc_coherent(&mrioc->pdev->dev, data_len, &data_dma,
2399 GFP_KERNEL);
2400 if (!data)
2401 return -ENOMEM;
2402
2403 memset(&ci_upload, 0, sizeof(ci_upload));
2404 mutex_lock(&mrioc->init_cmds.mutex);
2405 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
2406 ioc_err(mrioc, "sending get package version failed due to command in use\n");
2407 mutex_unlock(&mrioc->init_cmds.mutex);
2408 goto out;
2409 }
2410 mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
2411 mrioc->init_cmds.is_waiting = 1;
2412 mrioc->init_cmds.callback = NULL;
2413 ci_upload.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
2414 ci_upload.function = MPI3_FUNCTION_CI_UPLOAD;
2415 ci_upload.msg_flags = MPI3_CI_UPLOAD_MSGFLAGS_LOCATION_PRIMARY;
2416 ci_upload.signature1 = cpu_to_le32(MPI3_IMAGE_HEADER_SIGNATURE1_MANIFEST);
2417 ci_upload.image_offset = cpu_to_le32(MPI3_IMAGE_HEADER_SIZE);
2418 ci_upload.segment_size = cpu_to_le32(data_len);
2419
2420 mpi3mr_add_sg_single(&ci_upload.sgl, sgl_flags, data_len,
2421 data_dma);
2422 init_completion(&mrioc->init_cmds.done);
2423 retval = mpi3mr_admin_request_post(mrioc, &ci_upload,
2424 sizeof(ci_upload), 1);
2425 if (retval) {
2426 ioc_err(mrioc, "posting get package version failed\n");
2427 goto out_unlock;
2428 }
2429 wait_for_completion_timeout(&mrioc->init_cmds.done,
2430 (MPI3MR_INTADMCMD_TIMEOUT * HZ));
2431 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
2432 ioc_err(mrioc, "get package version timed out\n");
2433 mpi3mr_check_rh_fault_ioc(mrioc,
2434 MPI3MR_RESET_FROM_GETPKGVER_TIMEOUT);
2435 retval = -1;
2436 goto out_unlock;
2437 }
2438 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
2439 == MPI3_IOCSTATUS_SUCCESS) {
2440 manifest = (struct mpi3_ci_manifest_mpi *) data;
2441 if (manifest->manifest_type == MPI3_CI_MANIFEST_TYPE_MPI) {
2442 ioc_info(mrioc,
2443 "firmware package version(%d.%d.%d.%d.%05d-%05d)\n",
2444 manifest->package_version.gen_major,
2445 manifest->package_version.gen_minor,
2446 manifest->package_version.phase_major,
2447 manifest->package_version.phase_minor,
2448 manifest->package_version.customer_id,
2449 manifest->package_version.build_num);
2450 }
2451 }
2452 retval = 0;
2453 out_unlock:
2454 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
2455 mutex_unlock(&mrioc->init_cmds.mutex);
2456
2457 out:
2458 if (data)
2459 dma_free_coherent(&mrioc->pdev->dev, data_len, data,
2460 data_dma);
2461 return retval;
2462 }
2463
2464 /**
2465 * mpi3mr_watchdog_work - watchdog thread to monitor faults
2466 * @work: work struct
2467 *
2468 * Watch dog work periodically executed (1 second interval) to
2469 * monitor firmware fault and to issue periodic timer sync to
2470 * the firmware.
2471 *
2472 * Return: Nothing.
2473 */
mpi3mr_watchdog_work(struct work_struct * work)2474 static void mpi3mr_watchdog_work(struct work_struct *work)
2475 {
2476 struct mpi3mr_ioc *mrioc =
2477 container_of(work, struct mpi3mr_ioc, watchdog_work.work);
2478 unsigned long flags;
2479 enum mpi3mr_iocstate ioc_state;
2480 u32 fault, host_diagnostic, ioc_status;
2481 u32 reset_reason = MPI3MR_RESET_FROM_FAULT_WATCH;
2482
2483 if (mrioc->reset_in_progress)
2484 return;
2485
2486 if (!mrioc->unrecoverable && !pci_device_is_present(mrioc->pdev)) {
2487 ioc_err(mrioc, "watchdog could not detect the controller\n");
2488 mrioc->unrecoverable = 1;
2489 }
2490
2491 if (mrioc->unrecoverable) {
2492 ioc_err(mrioc,
2493 "flush pending commands for unrecoverable controller\n");
2494 mpi3mr_flush_cmds_for_unrecovered_controller(mrioc);
2495 return;
2496 }
2497
2498 if (mrioc->ts_update_counter++ >= MPI3MR_TSUPDATE_INTERVAL) {
2499 mrioc->ts_update_counter = 0;
2500 mpi3mr_sync_timestamp(mrioc);
2501 }
2502
2503 if ((mrioc->prepare_for_reset) &&
2504 ((mrioc->prepare_for_reset_timeout_counter++) >=
2505 MPI3MR_PREPARE_FOR_RESET_TIMEOUT)) {
2506 mpi3mr_soft_reset_handler(mrioc,
2507 MPI3MR_RESET_FROM_CIACTVRST_TIMER, 1);
2508 return;
2509 }
2510
2511 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
2512 if (ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY) {
2513 mpi3mr_soft_reset_handler(mrioc, MPI3MR_RESET_FROM_FIRMWARE, 0);
2514 return;
2515 }
2516
2517 /*Check for fault state every one second and issue Soft reset*/
2518 ioc_state = mpi3mr_get_iocstate(mrioc);
2519 if (ioc_state != MRIOC_STATE_FAULT)
2520 goto schedule_work;
2521
2522 fault = readl(&mrioc->sysif_regs->fault) & MPI3_SYSIF_FAULT_CODE_MASK;
2523 host_diagnostic = readl(&mrioc->sysif_regs->host_diagnostic);
2524 if (host_diagnostic & MPI3_SYSIF_HOST_DIAG_SAVE_IN_PROGRESS) {
2525 if (!mrioc->diagsave_timeout) {
2526 mpi3mr_print_fault_info(mrioc);
2527 ioc_warn(mrioc, "diag save in progress\n");
2528 }
2529 if ((mrioc->diagsave_timeout++) <= MPI3_SYSIF_DIAG_SAVE_TIMEOUT)
2530 goto schedule_work;
2531 }
2532
2533 mpi3mr_print_fault_info(mrioc);
2534 mrioc->diagsave_timeout = 0;
2535
2536 switch (fault) {
2537 case MPI3_SYSIF_FAULT_CODE_COMPLETE_RESET_NEEDED:
2538 case MPI3_SYSIF_FAULT_CODE_POWER_CYCLE_REQUIRED:
2539 ioc_warn(mrioc,
2540 "controller requires system power cycle, marking controller as unrecoverable\n");
2541 mrioc->unrecoverable = 1;
2542 goto schedule_work;
2543 case MPI3_SYSIF_FAULT_CODE_SOFT_RESET_IN_PROGRESS:
2544 goto schedule_work;
2545 case MPI3_SYSIF_FAULT_CODE_CI_ACTIVATION_RESET:
2546 reset_reason = MPI3MR_RESET_FROM_CIACTIV_FAULT;
2547 break;
2548 default:
2549 break;
2550 }
2551 mpi3mr_soft_reset_handler(mrioc, reset_reason, 0);
2552 return;
2553
2554 schedule_work:
2555 spin_lock_irqsave(&mrioc->watchdog_lock, flags);
2556 if (mrioc->watchdog_work_q)
2557 queue_delayed_work(mrioc->watchdog_work_q,
2558 &mrioc->watchdog_work,
2559 msecs_to_jiffies(MPI3MR_WATCHDOG_INTERVAL));
2560 spin_unlock_irqrestore(&mrioc->watchdog_lock, flags);
2561 return;
2562 }
2563
2564 /**
2565 * mpi3mr_start_watchdog - Start watchdog
2566 * @mrioc: Adapter instance reference
2567 *
2568 * Create and start the watchdog thread to monitor controller
2569 * faults.
2570 *
2571 * Return: Nothing.
2572 */
mpi3mr_start_watchdog(struct mpi3mr_ioc * mrioc)2573 void mpi3mr_start_watchdog(struct mpi3mr_ioc *mrioc)
2574 {
2575 if (mrioc->watchdog_work_q)
2576 return;
2577
2578 INIT_DELAYED_WORK(&mrioc->watchdog_work, mpi3mr_watchdog_work);
2579 snprintf(mrioc->watchdog_work_q_name,
2580 sizeof(mrioc->watchdog_work_q_name), "watchdog_%s%d", mrioc->name,
2581 mrioc->id);
2582 mrioc->watchdog_work_q =
2583 create_singlethread_workqueue(mrioc->watchdog_work_q_name);
2584 if (!mrioc->watchdog_work_q) {
2585 ioc_err(mrioc, "%s: failed (line=%d)\n", __func__, __LINE__);
2586 return;
2587 }
2588
2589 if (mrioc->watchdog_work_q)
2590 queue_delayed_work(mrioc->watchdog_work_q,
2591 &mrioc->watchdog_work,
2592 msecs_to_jiffies(MPI3MR_WATCHDOG_INTERVAL));
2593 }
2594
2595 /**
2596 * mpi3mr_stop_watchdog - Stop watchdog
2597 * @mrioc: Adapter instance reference
2598 *
2599 * Stop the watchdog thread created to monitor controller
2600 * faults.
2601 *
2602 * Return: Nothing.
2603 */
mpi3mr_stop_watchdog(struct mpi3mr_ioc * mrioc)2604 void mpi3mr_stop_watchdog(struct mpi3mr_ioc *mrioc)
2605 {
2606 unsigned long flags;
2607 struct workqueue_struct *wq;
2608
2609 spin_lock_irqsave(&mrioc->watchdog_lock, flags);
2610 wq = mrioc->watchdog_work_q;
2611 mrioc->watchdog_work_q = NULL;
2612 spin_unlock_irqrestore(&mrioc->watchdog_lock, flags);
2613 if (wq) {
2614 if (!cancel_delayed_work_sync(&mrioc->watchdog_work))
2615 flush_workqueue(wq);
2616 destroy_workqueue(wq);
2617 }
2618 }
2619
2620 /**
2621 * mpi3mr_setup_admin_qpair - Setup admin queue pair
2622 * @mrioc: Adapter instance reference
2623 *
2624 * Allocate memory for admin queue pair if required and register
2625 * the admin queue with the controller.
2626 *
2627 * Return: 0 on success, non-zero on failures.
2628 */
mpi3mr_setup_admin_qpair(struct mpi3mr_ioc * mrioc)2629 static int mpi3mr_setup_admin_qpair(struct mpi3mr_ioc *mrioc)
2630 {
2631 int retval = 0;
2632 u32 num_admin_entries = 0;
2633
2634 mrioc->admin_req_q_sz = MPI3MR_ADMIN_REQ_Q_SIZE;
2635 mrioc->num_admin_req = mrioc->admin_req_q_sz /
2636 MPI3MR_ADMIN_REQ_FRAME_SZ;
2637 mrioc->admin_req_ci = mrioc->admin_req_pi = 0;
2638
2639 mrioc->admin_reply_q_sz = MPI3MR_ADMIN_REPLY_Q_SIZE;
2640 mrioc->num_admin_replies = mrioc->admin_reply_q_sz /
2641 MPI3MR_ADMIN_REPLY_FRAME_SZ;
2642 mrioc->admin_reply_ci = 0;
2643 mrioc->admin_reply_ephase = 1;
2644 atomic_set(&mrioc->admin_reply_q_in_use, 0);
2645
2646 if (!mrioc->admin_req_base) {
2647 mrioc->admin_req_base = dma_alloc_coherent(&mrioc->pdev->dev,
2648 mrioc->admin_req_q_sz, &mrioc->admin_req_dma, GFP_KERNEL);
2649
2650 if (!mrioc->admin_req_base) {
2651 retval = -1;
2652 goto out_failed;
2653 }
2654
2655 mrioc->admin_reply_base = dma_alloc_coherent(&mrioc->pdev->dev,
2656 mrioc->admin_reply_q_sz, &mrioc->admin_reply_dma,
2657 GFP_KERNEL);
2658
2659 if (!mrioc->admin_reply_base) {
2660 retval = -1;
2661 goto out_failed;
2662 }
2663 }
2664
2665 num_admin_entries = (mrioc->num_admin_replies << 16) |
2666 (mrioc->num_admin_req);
2667 writel(num_admin_entries, &mrioc->sysif_regs->admin_queue_num_entries);
2668 mpi3mr_writeq(mrioc->admin_req_dma,
2669 &mrioc->sysif_regs->admin_request_queue_address);
2670 mpi3mr_writeq(mrioc->admin_reply_dma,
2671 &mrioc->sysif_regs->admin_reply_queue_address);
2672 writel(mrioc->admin_req_pi, &mrioc->sysif_regs->admin_request_queue_pi);
2673 writel(mrioc->admin_reply_ci, &mrioc->sysif_regs->admin_reply_queue_ci);
2674 return retval;
2675
2676 out_failed:
2677
2678 if (mrioc->admin_reply_base) {
2679 dma_free_coherent(&mrioc->pdev->dev, mrioc->admin_reply_q_sz,
2680 mrioc->admin_reply_base, mrioc->admin_reply_dma);
2681 mrioc->admin_reply_base = NULL;
2682 }
2683 if (mrioc->admin_req_base) {
2684 dma_free_coherent(&mrioc->pdev->dev, mrioc->admin_req_q_sz,
2685 mrioc->admin_req_base, mrioc->admin_req_dma);
2686 mrioc->admin_req_base = NULL;
2687 }
2688 return retval;
2689 }
2690
2691 /**
2692 * mpi3mr_issue_iocfacts - Send IOC Facts
2693 * @mrioc: Adapter instance reference
2694 * @facts_data: Cached IOC facts data
2695 *
2696 * Issue IOC Facts MPI request through admin queue and wait for
2697 * the completion of it or time out.
2698 *
2699 * Return: 0 on success, non-zero on failures.
2700 */
mpi3mr_issue_iocfacts(struct mpi3mr_ioc * mrioc,struct mpi3_ioc_facts_data * facts_data)2701 static int mpi3mr_issue_iocfacts(struct mpi3mr_ioc *mrioc,
2702 struct mpi3_ioc_facts_data *facts_data)
2703 {
2704 struct mpi3_ioc_facts_request iocfacts_req;
2705 void *data = NULL;
2706 dma_addr_t data_dma;
2707 u32 data_len = sizeof(*facts_data);
2708 int retval = 0;
2709 u8 sgl_flags = MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST;
2710
2711 data = dma_alloc_coherent(&mrioc->pdev->dev, data_len, &data_dma,
2712 GFP_KERNEL);
2713
2714 if (!data) {
2715 retval = -1;
2716 goto out;
2717 }
2718
2719 memset(&iocfacts_req, 0, sizeof(iocfacts_req));
2720 mutex_lock(&mrioc->init_cmds.mutex);
2721 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
2722 retval = -1;
2723 ioc_err(mrioc, "Issue IOCFacts: Init command is in use\n");
2724 mutex_unlock(&mrioc->init_cmds.mutex);
2725 goto out;
2726 }
2727 mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
2728 mrioc->init_cmds.is_waiting = 1;
2729 mrioc->init_cmds.callback = NULL;
2730 iocfacts_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
2731 iocfacts_req.function = MPI3_FUNCTION_IOC_FACTS;
2732
2733 mpi3mr_add_sg_single(&iocfacts_req.sgl, sgl_flags, data_len,
2734 data_dma);
2735
2736 init_completion(&mrioc->init_cmds.done);
2737 retval = mpi3mr_admin_request_post(mrioc, &iocfacts_req,
2738 sizeof(iocfacts_req), 1);
2739 if (retval) {
2740 ioc_err(mrioc, "Issue IOCFacts: Admin Post failed\n");
2741 goto out_unlock;
2742 }
2743 wait_for_completion_timeout(&mrioc->init_cmds.done,
2744 (MPI3MR_INTADMCMD_TIMEOUT * HZ));
2745 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
2746 ioc_err(mrioc, "ioc_facts timed out\n");
2747 mpi3mr_check_rh_fault_ioc(mrioc,
2748 MPI3MR_RESET_FROM_IOCFACTS_TIMEOUT);
2749 retval = -1;
2750 goto out_unlock;
2751 }
2752 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
2753 != MPI3_IOCSTATUS_SUCCESS) {
2754 ioc_err(mrioc,
2755 "Issue IOCFacts: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
2756 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK),
2757 mrioc->init_cmds.ioc_loginfo);
2758 retval = -1;
2759 goto out_unlock;
2760 }
2761 memcpy(facts_data, (u8 *)data, data_len);
2762 mpi3mr_process_factsdata(mrioc, facts_data);
2763 out_unlock:
2764 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
2765 mutex_unlock(&mrioc->init_cmds.mutex);
2766
2767 out:
2768 if (data)
2769 dma_free_coherent(&mrioc->pdev->dev, data_len, data, data_dma);
2770
2771 return retval;
2772 }
2773
2774 /**
2775 * mpi3mr_check_reset_dma_mask - Process IOC facts data
2776 * @mrioc: Adapter instance reference
2777 *
2778 * Check whether the new DMA mask requested through IOCFacts by
2779 * firmware needs to be set, if so set it .
2780 *
2781 * Return: 0 on success, non-zero on failure.
2782 */
mpi3mr_check_reset_dma_mask(struct mpi3mr_ioc * mrioc)2783 static inline int mpi3mr_check_reset_dma_mask(struct mpi3mr_ioc *mrioc)
2784 {
2785 struct pci_dev *pdev = mrioc->pdev;
2786 int r;
2787 u64 facts_dma_mask = DMA_BIT_MASK(mrioc->facts.dma_mask);
2788
2789 if (!mrioc->facts.dma_mask || (mrioc->dma_mask <= facts_dma_mask))
2790 return 0;
2791
2792 ioc_info(mrioc, "Changing DMA mask from 0x%016llx to 0x%016llx\n",
2793 mrioc->dma_mask, facts_dma_mask);
2794
2795 r = dma_set_mask_and_coherent(&pdev->dev, facts_dma_mask);
2796 if (r) {
2797 ioc_err(mrioc, "Setting DMA mask to 0x%016llx failed: %d\n",
2798 facts_dma_mask, r);
2799 return r;
2800 }
2801 mrioc->dma_mask = facts_dma_mask;
2802 return r;
2803 }
2804
2805 /**
2806 * mpi3mr_process_factsdata - Process IOC facts data
2807 * @mrioc: Adapter instance reference
2808 * @facts_data: Cached IOC facts data
2809 *
2810 * Convert IOC facts data into cpu endianness and cache it in
2811 * the driver .
2812 *
2813 * Return: Nothing.
2814 */
mpi3mr_process_factsdata(struct mpi3mr_ioc * mrioc,struct mpi3_ioc_facts_data * facts_data)2815 static void mpi3mr_process_factsdata(struct mpi3mr_ioc *mrioc,
2816 struct mpi3_ioc_facts_data *facts_data)
2817 {
2818 u32 ioc_config, req_sz, facts_flags;
2819
2820 if ((le16_to_cpu(facts_data->ioc_facts_data_length)) !=
2821 (sizeof(*facts_data) / 4)) {
2822 ioc_warn(mrioc,
2823 "IOCFactsdata length mismatch driver_sz(%zu) firmware_sz(%d)\n",
2824 sizeof(*facts_data),
2825 le16_to_cpu(facts_data->ioc_facts_data_length) * 4);
2826 }
2827
2828 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
2829 req_sz = 1 << ((ioc_config & MPI3_SYSIF_IOC_CONFIG_OPER_REQ_ENT_SZ) >>
2830 MPI3_SYSIF_IOC_CONFIG_OPER_REQ_ENT_SZ_SHIFT);
2831 if (le16_to_cpu(facts_data->ioc_request_frame_size) != (req_sz / 4)) {
2832 ioc_err(mrioc,
2833 "IOCFacts data reqFrameSize mismatch hw_size(%d) firmware_sz(%d)\n",
2834 req_sz / 4, le16_to_cpu(facts_data->ioc_request_frame_size));
2835 }
2836
2837 memset(&mrioc->facts, 0, sizeof(mrioc->facts));
2838
2839 facts_flags = le32_to_cpu(facts_data->flags);
2840 mrioc->facts.op_req_sz = req_sz;
2841 mrioc->op_reply_desc_sz = 1 << ((ioc_config &
2842 MPI3_SYSIF_IOC_CONFIG_OPER_RPY_ENT_SZ) >>
2843 MPI3_SYSIF_IOC_CONFIG_OPER_RPY_ENT_SZ_SHIFT);
2844
2845 mrioc->facts.ioc_num = facts_data->ioc_number;
2846 mrioc->facts.who_init = facts_data->who_init;
2847 mrioc->facts.max_msix_vectors = le16_to_cpu(facts_data->max_msix_vectors);
2848 mrioc->facts.personality = (facts_flags &
2849 MPI3_IOCFACTS_FLAGS_PERSONALITY_MASK);
2850 mrioc->facts.dma_mask = (facts_flags &
2851 MPI3_IOCFACTS_FLAGS_DMA_ADDRESS_WIDTH_MASK) >>
2852 MPI3_IOCFACTS_FLAGS_DMA_ADDRESS_WIDTH_SHIFT;
2853 mrioc->facts.protocol_flags = facts_data->protocol_flags;
2854 mrioc->facts.mpi_version = le32_to_cpu(facts_data->mpi_version.word);
2855 mrioc->facts.max_reqs = le16_to_cpu(facts_data->max_outstanding_requests);
2856 mrioc->facts.product_id = le16_to_cpu(facts_data->product_id);
2857 mrioc->facts.reply_sz = le16_to_cpu(facts_data->reply_frame_size) * 4;
2858 mrioc->facts.exceptions = le16_to_cpu(facts_data->ioc_exceptions);
2859 mrioc->facts.max_perids = le16_to_cpu(facts_data->max_persistent_id);
2860 mrioc->facts.max_vds = le16_to_cpu(facts_data->max_vds);
2861 mrioc->facts.max_hpds = le16_to_cpu(facts_data->max_host_pds);
2862 mrioc->facts.max_advhpds = le16_to_cpu(facts_data->max_adv_host_pds);
2863 mrioc->facts.max_raid_pds = le16_to_cpu(facts_data->max_raid_pds);
2864 mrioc->facts.max_nvme = le16_to_cpu(facts_data->max_nvme);
2865 mrioc->facts.max_pcie_switches =
2866 le16_to_cpu(facts_data->max_pcie_switches);
2867 mrioc->facts.max_sasexpanders =
2868 le16_to_cpu(facts_data->max_sas_expanders);
2869 mrioc->facts.max_data_length = le16_to_cpu(facts_data->max_data_length);
2870 mrioc->facts.max_sasinitiators =
2871 le16_to_cpu(facts_data->max_sas_initiators);
2872 mrioc->facts.max_enclosures = le16_to_cpu(facts_data->max_enclosures);
2873 mrioc->facts.min_devhandle = le16_to_cpu(facts_data->min_dev_handle);
2874 mrioc->facts.max_devhandle = le16_to_cpu(facts_data->max_dev_handle);
2875 mrioc->facts.max_op_req_q =
2876 le16_to_cpu(facts_data->max_operational_request_queues);
2877 mrioc->facts.max_op_reply_q =
2878 le16_to_cpu(facts_data->max_operational_reply_queues);
2879 mrioc->facts.ioc_capabilities =
2880 le32_to_cpu(facts_data->ioc_capabilities);
2881 mrioc->facts.fw_ver.build_num =
2882 le16_to_cpu(facts_data->fw_version.build_num);
2883 mrioc->facts.fw_ver.cust_id =
2884 le16_to_cpu(facts_data->fw_version.customer_id);
2885 mrioc->facts.fw_ver.ph_minor = facts_data->fw_version.phase_minor;
2886 mrioc->facts.fw_ver.ph_major = facts_data->fw_version.phase_major;
2887 mrioc->facts.fw_ver.gen_minor = facts_data->fw_version.gen_minor;
2888 mrioc->facts.fw_ver.gen_major = facts_data->fw_version.gen_major;
2889 mrioc->msix_count = min_t(int, mrioc->msix_count,
2890 mrioc->facts.max_msix_vectors);
2891 mrioc->facts.sge_mod_mask = facts_data->sge_modifier_mask;
2892 mrioc->facts.sge_mod_value = facts_data->sge_modifier_value;
2893 mrioc->facts.sge_mod_shift = facts_data->sge_modifier_shift;
2894 mrioc->facts.shutdown_timeout =
2895 le16_to_cpu(facts_data->shutdown_timeout);
2896
2897 mrioc->facts.max_dev_per_tg =
2898 facts_data->max_devices_per_throttle_group;
2899 mrioc->facts.io_throttle_data_length =
2900 le16_to_cpu(facts_data->io_throttle_data_length);
2901 mrioc->facts.max_io_throttle_group =
2902 le16_to_cpu(facts_data->max_io_throttle_group);
2903 mrioc->facts.io_throttle_low = le16_to_cpu(facts_data->io_throttle_low);
2904 mrioc->facts.io_throttle_high =
2905 le16_to_cpu(facts_data->io_throttle_high);
2906
2907 if (mrioc->facts.max_data_length ==
2908 MPI3_IOCFACTS_MAX_DATA_LENGTH_NOT_REPORTED)
2909 mrioc->facts.max_data_length = MPI3MR_DEFAULT_MAX_IO_SIZE;
2910 else
2911 mrioc->facts.max_data_length *= MPI3MR_PAGE_SIZE_4K;
2912 /* Store in 512b block count */
2913 if (mrioc->facts.io_throttle_data_length)
2914 mrioc->io_throttle_data_length =
2915 (mrioc->facts.io_throttle_data_length * 2 * 4);
2916 else
2917 /* set the length to 1MB + 1K to disable throttle */
2918 mrioc->io_throttle_data_length = (mrioc->facts.max_data_length / 512) + 2;
2919
2920 mrioc->io_throttle_high = (mrioc->facts.io_throttle_high * 2 * 1024);
2921 mrioc->io_throttle_low = (mrioc->facts.io_throttle_low * 2 * 1024);
2922
2923 ioc_info(mrioc, "ioc_num(%d), maxopQ(%d), maxopRepQ(%d), maxdh(%d),",
2924 mrioc->facts.ioc_num, mrioc->facts.max_op_req_q,
2925 mrioc->facts.max_op_reply_q, mrioc->facts.max_devhandle);
2926 ioc_info(mrioc,
2927 "maxreqs(%d), mindh(%d) maxvectors(%d) maxperids(%d)\n",
2928 mrioc->facts.max_reqs, mrioc->facts.min_devhandle,
2929 mrioc->facts.max_msix_vectors, mrioc->facts.max_perids);
2930 ioc_info(mrioc, "SGEModMask 0x%x SGEModVal 0x%x SGEModShift 0x%x ",
2931 mrioc->facts.sge_mod_mask, mrioc->facts.sge_mod_value,
2932 mrioc->facts.sge_mod_shift);
2933 ioc_info(mrioc, "DMA mask %d InitialPE status 0x%x max_data_len (%d)\n",
2934 mrioc->facts.dma_mask, (facts_flags &
2935 MPI3_IOCFACTS_FLAGS_INITIAL_PORT_ENABLE_MASK), mrioc->facts.max_data_length);
2936 ioc_info(mrioc,
2937 "max_dev_per_throttle_group(%d), max_throttle_groups(%d)\n",
2938 mrioc->facts.max_dev_per_tg, mrioc->facts.max_io_throttle_group);
2939 ioc_info(mrioc,
2940 "io_throttle_data_len(%dKiB), io_throttle_high(%dMiB), io_throttle_low(%dMiB)\n",
2941 mrioc->facts.io_throttle_data_length * 4,
2942 mrioc->facts.io_throttle_high, mrioc->facts.io_throttle_low);
2943 }
2944
2945 /**
2946 * mpi3mr_alloc_reply_sense_bufs - Send IOC Init
2947 * @mrioc: Adapter instance reference
2948 *
2949 * Allocate and initialize the reply free buffers, sense
2950 * buffers, reply free queue and sense buffer queue.
2951 *
2952 * Return: 0 on success, non-zero on failures.
2953 */
mpi3mr_alloc_reply_sense_bufs(struct mpi3mr_ioc * mrioc)2954 static int mpi3mr_alloc_reply_sense_bufs(struct mpi3mr_ioc *mrioc)
2955 {
2956 int retval = 0;
2957 u32 sz, i;
2958
2959 if (mrioc->init_cmds.reply)
2960 return retval;
2961
2962 mrioc->init_cmds.reply = kzalloc(mrioc->reply_sz, GFP_KERNEL);
2963 if (!mrioc->init_cmds.reply)
2964 goto out_failed;
2965
2966 mrioc->bsg_cmds.reply = kzalloc(mrioc->reply_sz, GFP_KERNEL);
2967 if (!mrioc->bsg_cmds.reply)
2968 goto out_failed;
2969
2970 mrioc->transport_cmds.reply = kzalloc(mrioc->reply_sz, GFP_KERNEL);
2971 if (!mrioc->transport_cmds.reply)
2972 goto out_failed;
2973
2974 for (i = 0; i < MPI3MR_NUM_DEVRMCMD; i++) {
2975 mrioc->dev_rmhs_cmds[i].reply = kzalloc(mrioc->reply_sz,
2976 GFP_KERNEL);
2977 if (!mrioc->dev_rmhs_cmds[i].reply)
2978 goto out_failed;
2979 }
2980
2981 for (i = 0; i < MPI3MR_NUM_EVTACKCMD; i++) {
2982 mrioc->evtack_cmds[i].reply = kzalloc(mrioc->reply_sz,
2983 GFP_KERNEL);
2984 if (!mrioc->evtack_cmds[i].reply)
2985 goto out_failed;
2986 }
2987
2988 mrioc->host_tm_cmds.reply = kzalloc(mrioc->reply_sz, GFP_KERNEL);
2989 if (!mrioc->host_tm_cmds.reply)
2990 goto out_failed;
2991
2992 mrioc->pel_cmds.reply = kzalloc(mrioc->reply_sz, GFP_KERNEL);
2993 if (!mrioc->pel_cmds.reply)
2994 goto out_failed;
2995
2996 mrioc->pel_abort_cmd.reply = kzalloc(mrioc->reply_sz, GFP_KERNEL);
2997 if (!mrioc->pel_abort_cmd.reply)
2998 goto out_failed;
2999
3000 mrioc->dev_handle_bitmap_bits = mrioc->facts.max_devhandle;
3001 mrioc->removepend_bitmap = bitmap_zalloc(mrioc->dev_handle_bitmap_bits,
3002 GFP_KERNEL);
3003 if (!mrioc->removepend_bitmap)
3004 goto out_failed;
3005
3006 mrioc->devrem_bitmap = bitmap_zalloc(MPI3MR_NUM_DEVRMCMD, GFP_KERNEL);
3007 if (!mrioc->devrem_bitmap)
3008 goto out_failed;
3009
3010 mrioc->evtack_cmds_bitmap = bitmap_zalloc(MPI3MR_NUM_EVTACKCMD,
3011 GFP_KERNEL);
3012 if (!mrioc->evtack_cmds_bitmap)
3013 goto out_failed;
3014
3015 mrioc->num_reply_bufs = mrioc->facts.max_reqs + MPI3MR_NUM_EVT_REPLIES;
3016 mrioc->reply_free_qsz = mrioc->num_reply_bufs + 1;
3017 mrioc->num_sense_bufs = mrioc->facts.max_reqs / MPI3MR_SENSEBUF_FACTOR;
3018 mrioc->sense_buf_q_sz = mrioc->num_sense_bufs + 1;
3019
3020 /* reply buffer pool, 16 byte align */
3021 sz = mrioc->num_reply_bufs * mrioc->reply_sz;
3022 mrioc->reply_buf_pool = dma_pool_create("reply_buf pool",
3023 &mrioc->pdev->dev, sz, 16, 0);
3024 if (!mrioc->reply_buf_pool) {
3025 ioc_err(mrioc, "reply buf pool: dma_pool_create failed\n");
3026 goto out_failed;
3027 }
3028
3029 mrioc->reply_buf = dma_pool_zalloc(mrioc->reply_buf_pool, GFP_KERNEL,
3030 &mrioc->reply_buf_dma);
3031 if (!mrioc->reply_buf)
3032 goto out_failed;
3033
3034 mrioc->reply_buf_dma_max_address = mrioc->reply_buf_dma + sz;
3035
3036 /* reply free queue, 8 byte align */
3037 sz = mrioc->reply_free_qsz * 8;
3038 mrioc->reply_free_q_pool = dma_pool_create("reply_free_q pool",
3039 &mrioc->pdev->dev, sz, 8, 0);
3040 if (!mrioc->reply_free_q_pool) {
3041 ioc_err(mrioc, "reply_free_q pool: dma_pool_create failed\n");
3042 goto out_failed;
3043 }
3044 mrioc->reply_free_q = dma_pool_zalloc(mrioc->reply_free_q_pool,
3045 GFP_KERNEL, &mrioc->reply_free_q_dma);
3046 if (!mrioc->reply_free_q)
3047 goto out_failed;
3048
3049 /* sense buffer pool, 4 byte align */
3050 sz = mrioc->num_sense_bufs * MPI3MR_SENSE_BUF_SZ;
3051 mrioc->sense_buf_pool = dma_pool_create("sense_buf pool",
3052 &mrioc->pdev->dev, sz, 4, 0);
3053 if (!mrioc->sense_buf_pool) {
3054 ioc_err(mrioc, "sense_buf pool: dma_pool_create failed\n");
3055 goto out_failed;
3056 }
3057 mrioc->sense_buf = dma_pool_zalloc(mrioc->sense_buf_pool, GFP_KERNEL,
3058 &mrioc->sense_buf_dma);
3059 if (!mrioc->sense_buf)
3060 goto out_failed;
3061
3062 /* sense buffer queue, 8 byte align */
3063 sz = mrioc->sense_buf_q_sz * 8;
3064 mrioc->sense_buf_q_pool = dma_pool_create("sense_buf_q pool",
3065 &mrioc->pdev->dev, sz, 8, 0);
3066 if (!mrioc->sense_buf_q_pool) {
3067 ioc_err(mrioc, "sense_buf_q pool: dma_pool_create failed\n");
3068 goto out_failed;
3069 }
3070 mrioc->sense_buf_q = dma_pool_zalloc(mrioc->sense_buf_q_pool,
3071 GFP_KERNEL, &mrioc->sense_buf_q_dma);
3072 if (!mrioc->sense_buf_q)
3073 goto out_failed;
3074
3075 return retval;
3076
3077 out_failed:
3078 retval = -1;
3079 return retval;
3080 }
3081
3082 /**
3083 * mpimr_initialize_reply_sbuf_queues - initialize reply sense
3084 * buffers
3085 * @mrioc: Adapter instance reference
3086 *
3087 * Helper function to initialize reply and sense buffers along
3088 * with some debug prints.
3089 *
3090 * Return: None.
3091 */
mpimr_initialize_reply_sbuf_queues(struct mpi3mr_ioc * mrioc)3092 static void mpimr_initialize_reply_sbuf_queues(struct mpi3mr_ioc *mrioc)
3093 {
3094 u32 sz, i;
3095 dma_addr_t phy_addr;
3096
3097 sz = mrioc->num_reply_bufs * mrioc->reply_sz;
3098 ioc_info(mrioc,
3099 "reply buf pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB), reply_dma(0x%llx)\n",
3100 mrioc->reply_buf, mrioc->num_reply_bufs, mrioc->reply_sz,
3101 (sz / 1024), (unsigned long long)mrioc->reply_buf_dma);
3102 sz = mrioc->reply_free_qsz * 8;
3103 ioc_info(mrioc,
3104 "reply_free_q pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB), reply_dma(0x%llx)\n",
3105 mrioc->reply_free_q, mrioc->reply_free_qsz, 8, (sz / 1024),
3106 (unsigned long long)mrioc->reply_free_q_dma);
3107 sz = mrioc->num_sense_bufs * MPI3MR_SENSE_BUF_SZ;
3108 ioc_info(mrioc,
3109 "sense_buf pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB), sense_dma(0x%llx)\n",
3110 mrioc->sense_buf, mrioc->num_sense_bufs, MPI3MR_SENSE_BUF_SZ,
3111 (sz / 1024), (unsigned long long)mrioc->sense_buf_dma);
3112 sz = mrioc->sense_buf_q_sz * 8;
3113 ioc_info(mrioc,
3114 "sense_buf_q pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB), sense_dma(0x%llx)\n",
3115 mrioc->sense_buf_q, mrioc->sense_buf_q_sz, 8, (sz / 1024),
3116 (unsigned long long)mrioc->sense_buf_q_dma);
3117
3118 /* initialize Reply buffer Queue */
3119 for (i = 0, phy_addr = mrioc->reply_buf_dma;
3120 i < mrioc->num_reply_bufs; i++, phy_addr += mrioc->reply_sz)
3121 mrioc->reply_free_q[i] = cpu_to_le64(phy_addr);
3122 mrioc->reply_free_q[i] = cpu_to_le64(0);
3123
3124 /* initialize Sense Buffer Queue */
3125 for (i = 0, phy_addr = mrioc->sense_buf_dma;
3126 i < mrioc->num_sense_bufs; i++, phy_addr += MPI3MR_SENSE_BUF_SZ)
3127 mrioc->sense_buf_q[i] = cpu_to_le64(phy_addr);
3128 mrioc->sense_buf_q[i] = cpu_to_le64(0);
3129 }
3130
3131 /**
3132 * mpi3mr_issue_iocinit - Send IOC Init
3133 * @mrioc: Adapter instance reference
3134 *
3135 * Issue IOC Init MPI request through admin queue and wait for
3136 * the completion of it or time out.
3137 *
3138 * Return: 0 on success, non-zero on failures.
3139 */
mpi3mr_issue_iocinit(struct mpi3mr_ioc * mrioc)3140 static int mpi3mr_issue_iocinit(struct mpi3mr_ioc *mrioc)
3141 {
3142 struct mpi3_ioc_init_request iocinit_req;
3143 struct mpi3_driver_info_layout *drv_info;
3144 dma_addr_t data_dma;
3145 u32 data_len = sizeof(*drv_info);
3146 int retval = 0;
3147 ktime_t current_time;
3148
3149 drv_info = dma_alloc_coherent(&mrioc->pdev->dev, data_len, &data_dma,
3150 GFP_KERNEL);
3151 if (!drv_info) {
3152 retval = -1;
3153 goto out;
3154 }
3155 mpimr_initialize_reply_sbuf_queues(mrioc);
3156
3157 drv_info->information_length = cpu_to_le32(data_len);
3158 strscpy(drv_info->driver_signature, "Broadcom", sizeof(drv_info->driver_signature));
3159 strscpy(drv_info->os_name, utsname()->sysname, sizeof(drv_info->os_name));
3160 strscpy(drv_info->os_version, utsname()->release, sizeof(drv_info->os_version));
3161 strscpy(drv_info->driver_name, MPI3MR_DRIVER_NAME, sizeof(drv_info->driver_name));
3162 strscpy(drv_info->driver_version, MPI3MR_DRIVER_VERSION, sizeof(drv_info->driver_version));
3163 strscpy(drv_info->driver_release_date, MPI3MR_DRIVER_RELDATE,
3164 sizeof(drv_info->driver_release_date));
3165 drv_info->driver_capabilities = 0;
3166 memcpy((u8 *)&mrioc->driver_info, (u8 *)drv_info,
3167 sizeof(mrioc->driver_info));
3168
3169 memset(&iocinit_req, 0, sizeof(iocinit_req));
3170 mutex_lock(&mrioc->init_cmds.mutex);
3171 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
3172 retval = -1;
3173 ioc_err(mrioc, "Issue IOCInit: Init command is in use\n");
3174 mutex_unlock(&mrioc->init_cmds.mutex);
3175 goto out;
3176 }
3177 mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
3178 mrioc->init_cmds.is_waiting = 1;
3179 mrioc->init_cmds.callback = NULL;
3180 iocinit_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
3181 iocinit_req.function = MPI3_FUNCTION_IOC_INIT;
3182 iocinit_req.mpi_version.mpi3_version.dev = MPI3_VERSION_DEV;
3183 iocinit_req.mpi_version.mpi3_version.unit = MPI3_VERSION_UNIT;
3184 iocinit_req.mpi_version.mpi3_version.major = MPI3_VERSION_MAJOR;
3185 iocinit_req.mpi_version.mpi3_version.minor = MPI3_VERSION_MINOR;
3186 iocinit_req.who_init = MPI3_WHOINIT_HOST_DRIVER;
3187 iocinit_req.reply_free_queue_depth = cpu_to_le16(mrioc->reply_free_qsz);
3188 iocinit_req.reply_free_queue_address =
3189 cpu_to_le64(mrioc->reply_free_q_dma);
3190 iocinit_req.sense_buffer_length = cpu_to_le16(MPI3MR_SENSE_BUF_SZ);
3191 iocinit_req.sense_buffer_free_queue_depth =
3192 cpu_to_le16(mrioc->sense_buf_q_sz);
3193 iocinit_req.sense_buffer_free_queue_address =
3194 cpu_to_le64(mrioc->sense_buf_q_dma);
3195 iocinit_req.driver_information_address = cpu_to_le64(data_dma);
3196
3197 current_time = ktime_get_real();
3198 iocinit_req.time_stamp = cpu_to_le64(ktime_to_ms(current_time));
3199
3200 init_completion(&mrioc->init_cmds.done);
3201 retval = mpi3mr_admin_request_post(mrioc, &iocinit_req,
3202 sizeof(iocinit_req), 1);
3203 if (retval) {
3204 ioc_err(mrioc, "Issue IOCInit: Admin Post failed\n");
3205 goto out_unlock;
3206 }
3207 wait_for_completion_timeout(&mrioc->init_cmds.done,
3208 (MPI3MR_INTADMCMD_TIMEOUT * HZ));
3209 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
3210 mpi3mr_check_rh_fault_ioc(mrioc,
3211 MPI3MR_RESET_FROM_IOCINIT_TIMEOUT);
3212 ioc_err(mrioc, "ioc_init timed out\n");
3213 retval = -1;
3214 goto out_unlock;
3215 }
3216 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
3217 != MPI3_IOCSTATUS_SUCCESS) {
3218 ioc_err(mrioc,
3219 "Issue IOCInit: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
3220 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK),
3221 mrioc->init_cmds.ioc_loginfo);
3222 retval = -1;
3223 goto out_unlock;
3224 }
3225
3226 mrioc->reply_free_queue_host_index = mrioc->num_reply_bufs;
3227 writel(mrioc->reply_free_queue_host_index,
3228 &mrioc->sysif_regs->reply_free_host_index);
3229
3230 mrioc->sbq_host_index = mrioc->num_sense_bufs;
3231 writel(mrioc->sbq_host_index,
3232 &mrioc->sysif_regs->sense_buffer_free_host_index);
3233 out_unlock:
3234 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
3235 mutex_unlock(&mrioc->init_cmds.mutex);
3236
3237 out:
3238 if (drv_info)
3239 dma_free_coherent(&mrioc->pdev->dev, data_len, drv_info,
3240 data_dma);
3241
3242 return retval;
3243 }
3244
3245 /**
3246 * mpi3mr_unmask_events - Unmask events in event mask bitmap
3247 * @mrioc: Adapter instance reference
3248 * @event: MPI event ID
3249 *
3250 * Un mask the specific event by resetting the event_mask
3251 * bitmap.
3252 *
3253 * Return: 0 on success, non-zero on failures.
3254 */
mpi3mr_unmask_events(struct mpi3mr_ioc * mrioc,u16 event)3255 static void mpi3mr_unmask_events(struct mpi3mr_ioc *mrioc, u16 event)
3256 {
3257 u32 desired_event;
3258 u8 word;
3259
3260 if (event >= 128)
3261 return;
3262
3263 desired_event = (1 << (event % 32));
3264 word = event / 32;
3265
3266 mrioc->event_masks[word] &= ~desired_event;
3267 }
3268
3269 /**
3270 * mpi3mr_issue_event_notification - Send event notification
3271 * @mrioc: Adapter instance reference
3272 *
3273 * Issue event notification MPI request through admin queue and
3274 * wait for the completion of it or time out.
3275 *
3276 * Return: 0 on success, non-zero on failures.
3277 */
mpi3mr_issue_event_notification(struct mpi3mr_ioc * mrioc)3278 static int mpi3mr_issue_event_notification(struct mpi3mr_ioc *mrioc)
3279 {
3280 struct mpi3_event_notification_request evtnotify_req;
3281 int retval = 0;
3282 u8 i;
3283
3284 memset(&evtnotify_req, 0, sizeof(evtnotify_req));
3285 mutex_lock(&mrioc->init_cmds.mutex);
3286 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
3287 retval = -1;
3288 ioc_err(mrioc, "Issue EvtNotify: Init command is in use\n");
3289 mutex_unlock(&mrioc->init_cmds.mutex);
3290 goto out;
3291 }
3292 mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
3293 mrioc->init_cmds.is_waiting = 1;
3294 mrioc->init_cmds.callback = NULL;
3295 evtnotify_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
3296 evtnotify_req.function = MPI3_FUNCTION_EVENT_NOTIFICATION;
3297 for (i = 0; i < MPI3_EVENT_NOTIFY_EVENTMASK_WORDS; i++)
3298 evtnotify_req.event_masks[i] =
3299 cpu_to_le32(mrioc->event_masks[i]);
3300 init_completion(&mrioc->init_cmds.done);
3301 retval = mpi3mr_admin_request_post(mrioc, &evtnotify_req,
3302 sizeof(evtnotify_req), 1);
3303 if (retval) {
3304 ioc_err(mrioc, "Issue EvtNotify: Admin Post failed\n");
3305 goto out_unlock;
3306 }
3307 wait_for_completion_timeout(&mrioc->init_cmds.done,
3308 (MPI3MR_INTADMCMD_TIMEOUT * HZ));
3309 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
3310 ioc_err(mrioc, "event notification timed out\n");
3311 mpi3mr_check_rh_fault_ioc(mrioc,
3312 MPI3MR_RESET_FROM_EVTNOTIFY_TIMEOUT);
3313 retval = -1;
3314 goto out_unlock;
3315 }
3316 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
3317 != MPI3_IOCSTATUS_SUCCESS) {
3318 ioc_err(mrioc,
3319 "Issue EvtNotify: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
3320 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK),
3321 mrioc->init_cmds.ioc_loginfo);
3322 retval = -1;
3323 goto out_unlock;
3324 }
3325
3326 out_unlock:
3327 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
3328 mutex_unlock(&mrioc->init_cmds.mutex);
3329 out:
3330 return retval;
3331 }
3332
3333 /**
3334 * mpi3mr_process_event_ack - Process event acknowledgment
3335 * @mrioc: Adapter instance reference
3336 * @event: MPI3 event ID
3337 * @event_ctx: event context
3338 *
3339 * Send event acknowledgment through admin queue and wait for
3340 * it to complete.
3341 *
3342 * Return: 0 on success, non-zero on failures.
3343 */
mpi3mr_process_event_ack(struct mpi3mr_ioc * mrioc,u8 event,u32 event_ctx)3344 int mpi3mr_process_event_ack(struct mpi3mr_ioc *mrioc, u8 event,
3345 u32 event_ctx)
3346 {
3347 struct mpi3_event_ack_request evtack_req;
3348 int retval = 0;
3349
3350 memset(&evtack_req, 0, sizeof(evtack_req));
3351 mutex_lock(&mrioc->init_cmds.mutex);
3352 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
3353 retval = -1;
3354 ioc_err(mrioc, "Send EvtAck: Init command is in use\n");
3355 mutex_unlock(&mrioc->init_cmds.mutex);
3356 goto out;
3357 }
3358 mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
3359 mrioc->init_cmds.is_waiting = 1;
3360 mrioc->init_cmds.callback = NULL;
3361 evtack_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
3362 evtack_req.function = MPI3_FUNCTION_EVENT_ACK;
3363 evtack_req.event = event;
3364 evtack_req.event_context = cpu_to_le32(event_ctx);
3365
3366 init_completion(&mrioc->init_cmds.done);
3367 retval = mpi3mr_admin_request_post(mrioc, &evtack_req,
3368 sizeof(evtack_req), 1);
3369 if (retval) {
3370 ioc_err(mrioc, "Send EvtAck: Admin Post failed\n");
3371 goto out_unlock;
3372 }
3373 wait_for_completion_timeout(&mrioc->init_cmds.done,
3374 (MPI3MR_INTADMCMD_TIMEOUT * HZ));
3375 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
3376 ioc_err(mrioc, "Issue EvtNotify: command timed out\n");
3377 if (!(mrioc->init_cmds.state & MPI3MR_CMD_RESET))
3378 mpi3mr_check_rh_fault_ioc(mrioc,
3379 MPI3MR_RESET_FROM_EVTACK_TIMEOUT);
3380 retval = -1;
3381 goto out_unlock;
3382 }
3383 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
3384 != MPI3_IOCSTATUS_SUCCESS) {
3385 ioc_err(mrioc,
3386 "Send EvtAck: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
3387 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK),
3388 mrioc->init_cmds.ioc_loginfo);
3389 retval = -1;
3390 goto out_unlock;
3391 }
3392
3393 out_unlock:
3394 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
3395 mutex_unlock(&mrioc->init_cmds.mutex);
3396 out:
3397 return retval;
3398 }
3399
3400 /**
3401 * mpi3mr_alloc_chain_bufs - Allocate chain buffers
3402 * @mrioc: Adapter instance reference
3403 *
3404 * Allocate chain buffers and set a bitmap to indicate free
3405 * chain buffers. Chain buffers are used to pass the SGE
3406 * information along with MPI3 SCSI IO requests for host I/O.
3407 *
3408 * Return: 0 on success, non-zero on failure
3409 */
mpi3mr_alloc_chain_bufs(struct mpi3mr_ioc * mrioc)3410 static int mpi3mr_alloc_chain_bufs(struct mpi3mr_ioc *mrioc)
3411 {
3412 int retval = 0;
3413 u32 sz, i;
3414 u16 num_chains;
3415
3416 if (mrioc->chain_sgl_list)
3417 return retval;
3418
3419 num_chains = mrioc->max_host_ios / MPI3MR_CHAINBUF_FACTOR;
3420
3421 if (prot_mask & (SHOST_DIX_TYPE0_PROTECTION
3422 | SHOST_DIX_TYPE1_PROTECTION
3423 | SHOST_DIX_TYPE2_PROTECTION
3424 | SHOST_DIX_TYPE3_PROTECTION))
3425 num_chains += (num_chains / MPI3MR_CHAINBUFDIX_FACTOR);
3426
3427 mrioc->chain_buf_count = num_chains;
3428 sz = sizeof(struct chain_element) * num_chains;
3429 mrioc->chain_sgl_list = kzalloc(sz, GFP_KERNEL);
3430 if (!mrioc->chain_sgl_list)
3431 goto out_failed;
3432
3433 if (mrioc->max_sgl_entries > (mrioc->facts.max_data_length /
3434 MPI3MR_PAGE_SIZE_4K))
3435 mrioc->max_sgl_entries = mrioc->facts.max_data_length /
3436 MPI3MR_PAGE_SIZE_4K;
3437 sz = mrioc->max_sgl_entries * sizeof(struct mpi3_sge_common);
3438 ioc_info(mrioc, "number of sgl entries=%d chain buffer size=%dKB\n",
3439 mrioc->max_sgl_entries, sz/1024);
3440
3441 mrioc->chain_buf_pool = dma_pool_create("chain_buf pool",
3442 &mrioc->pdev->dev, sz, 16, 0);
3443 if (!mrioc->chain_buf_pool) {
3444 ioc_err(mrioc, "chain buf pool: dma_pool_create failed\n");
3445 goto out_failed;
3446 }
3447
3448 for (i = 0; i < num_chains; i++) {
3449 mrioc->chain_sgl_list[i].addr =
3450 dma_pool_zalloc(mrioc->chain_buf_pool, GFP_KERNEL,
3451 &mrioc->chain_sgl_list[i].dma_addr);
3452
3453 if (!mrioc->chain_sgl_list[i].addr)
3454 goto out_failed;
3455 }
3456 mrioc->chain_bitmap = bitmap_zalloc(num_chains, GFP_KERNEL);
3457 if (!mrioc->chain_bitmap)
3458 goto out_failed;
3459 return retval;
3460 out_failed:
3461 retval = -1;
3462 return retval;
3463 }
3464
3465 /**
3466 * mpi3mr_port_enable_complete - Mark port enable complete
3467 * @mrioc: Adapter instance reference
3468 * @drv_cmd: Internal command tracker
3469 *
3470 * Call back for asynchronous port enable request sets the
3471 * driver command to indicate port enable request is complete.
3472 *
3473 * Return: Nothing
3474 */
mpi3mr_port_enable_complete(struct mpi3mr_ioc * mrioc,struct mpi3mr_drv_cmd * drv_cmd)3475 static void mpi3mr_port_enable_complete(struct mpi3mr_ioc *mrioc,
3476 struct mpi3mr_drv_cmd *drv_cmd)
3477 {
3478 drv_cmd->callback = NULL;
3479 mrioc->scan_started = 0;
3480 if (drv_cmd->state & MPI3MR_CMD_RESET)
3481 mrioc->scan_failed = MPI3_IOCSTATUS_INTERNAL_ERROR;
3482 else
3483 mrioc->scan_failed = drv_cmd->ioc_status;
3484 drv_cmd->state = MPI3MR_CMD_NOTUSED;
3485 }
3486
3487 /**
3488 * mpi3mr_issue_port_enable - Issue Port Enable
3489 * @mrioc: Adapter instance reference
3490 * @async: Flag to wait for completion or not
3491 *
3492 * Issue Port Enable MPI request through admin queue and if the
3493 * async flag is not set wait for the completion of the port
3494 * enable or time out.
3495 *
3496 * Return: 0 on success, non-zero on failures.
3497 */
mpi3mr_issue_port_enable(struct mpi3mr_ioc * mrioc,u8 async)3498 int mpi3mr_issue_port_enable(struct mpi3mr_ioc *mrioc, u8 async)
3499 {
3500 struct mpi3_port_enable_request pe_req;
3501 int retval = 0;
3502 u32 pe_timeout = MPI3MR_PORTENABLE_TIMEOUT;
3503
3504 memset(&pe_req, 0, sizeof(pe_req));
3505 mutex_lock(&mrioc->init_cmds.mutex);
3506 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
3507 retval = -1;
3508 ioc_err(mrioc, "Issue PortEnable: Init command is in use\n");
3509 mutex_unlock(&mrioc->init_cmds.mutex);
3510 goto out;
3511 }
3512 mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
3513 if (async) {
3514 mrioc->init_cmds.is_waiting = 0;
3515 mrioc->init_cmds.callback = mpi3mr_port_enable_complete;
3516 } else {
3517 mrioc->init_cmds.is_waiting = 1;
3518 mrioc->init_cmds.callback = NULL;
3519 init_completion(&mrioc->init_cmds.done);
3520 }
3521 pe_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
3522 pe_req.function = MPI3_FUNCTION_PORT_ENABLE;
3523
3524 retval = mpi3mr_admin_request_post(mrioc, &pe_req, sizeof(pe_req), 1);
3525 if (retval) {
3526 ioc_err(mrioc, "Issue PortEnable: Admin Post failed\n");
3527 goto out_unlock;
3528 }
3529 if (async) {
3530 mutex_unlock(&mrioc->init_cmds.mutex);
3531 goto out;
3532 }
3533
3534 wait_for_completion_timeout(&mrioc->init_cmds.done, (pe_timeout * HZ));
3535 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
3536 ioc_err(mrioc, "port enable timed out\n");
3537 retval = -1;
3538 mpi3mr_check_rh_fault_ioc(mrioc, MPI3MR_RESET_FROM_PE_TIMEOUT);
3539 goto out_unlock;
3540 }
3541 mpi3mr_port_enable_complete(mrioc, &mrioc->init_cmds);
3542
3543 out_unlock:
3544 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
3545 mutex_unlock(&mrioc->init_cmds.mutex);
3546 out:
3547 return retval;
3548 }
3549
3550 /* Protocol type to name mapper structure */
3551 static const struct {
3552 u8 protocol;
3553 char *name;
3554 } mpi3mr_protocols[] = {
3555 { MPI3_IOCFACTS_PROTOCOL_SCSI_INITIATOR, "Initiator" },
3556 { MPI3_IOCFACTS_PROTOCOL_SCSI_TARGET, "Target" },
3557 { MPI3_IOCFACTS_PROTOCOL_NVME, "NVMe attachment" },
3558 };
3559
3560 /* Capability to name mapper structure*/
3561 static const struct {
3562 u32 capability;
3563 char *name;
3564 } mpi3mr_capabilities[] = {
3565 { MPI3_IOCFACTS_CAPABILITY_RAID_CAPABLE, "RAID" },
3566 { MPI3_IOCFACTS_CAPABILITY_MULTIPATH_ENABLED, "MultiPath" },
3567 };
3568
3569 /**
3570 * mpi3mr_print_ioc_info - Display controller information
3571 * @mrioc: Adapter instance reference
3572 *
3573 * Display controller personalit, capability, supported
3574 * protocols etc.
3575 *
3576 * Return: Nothing
3577 */
3578 static void
mpi3mr_print_ioc_info(struct mpi3mr_ioc * mrioc)3579 mpi3mr_print_ioc_info(struct mpi3mr_ioc *mrioc)
3580 {
3581 int i = 0, bytes_written = 0;
3582 char personality[16];
3583 char protocol[50] = {0};
3584 char capabilities[100] = {0};
3585 struct mpi3mr_compimg_ver *fwver = &mrioc->facts.fw_ver;
3586
3587 switch (mrioc->facts.personality) {
3588 case MPI3_IOCFACTS_FLAGS_PERSONALITY_EHBA:
3589 strncpy(personality, "Enhanced HBA", sizeof(personality));
3590 break;
3591 case MPI3_IOCFACTS_FLAGS_PERSONALITY_RAID_DDR:
3592 strncpy(personality, "RAID", sizeof(personality));
3593 break;
3594 default:
3595 strncpy(personality, "Unknown", sizeof(personality));
3596 break;
3597 }
3598
3599 ioc_info(mrioc, "Running in %s Personality", personality);
3600
3601 ioc_info(mrioc, "FW version(%d.%d.%d.%d.%d.%d)\n",
3602 fwver->gen_major, fwver->gen_minor, fwver->ph_major,
3603 fwver->ph_minor, fwver->cust_id, fwver->build_num);
3604
3605 for (i = 0; i < ARRAY_SIZE(mpi3mr_protocols); i++) {
3606 if (mrioc->facts.protocol_flags &
3607 mpi3mr_protocols[i].protocol) {
3608 bytes_written += scnprintf(protocol + bytes_written,
3609 sizeof(protocol) - bytes_written, "%s%s",
3610 bytes_written ? "," : "",
3611 mpi3mr_protocols[i].name);
3612 }
3613 }
3614
3615 bytes_written = 0;
3616 for (i = 0; i < ARRAY_SIZE(mpi3mr_capabilities); i++) {
3617 if (mrioc->facts.protocol_flags &
3618 mpi3mr_capabilities[i].capability) {
3619 bytes_written += scnprintf(capabilities + bytes_written,
3620 sizeof(capabilities) - bytes_written, "%s%s",
3621 bytes_written ? "," : "",
3622 mpi3mr_capabilities[i].name);
3623 }
3624 }
3625
3626 ioc_info(mrioc, "Protocol=(%s), Capabilities=(%s)\n",
3627 protocol, capabilities);
3628 }
3629
3630 /**
3631 * mpi3mr_cleanup_resources - Free PCI resources
3632 * @mrioc: Adapter instance reference
3633 *
3634 * Unmap PCI device memory and disable PCI device.
3635 *
3636 * Return: 0 on success and non-zero on failure.
3637 */
mpi3mr_cleanup_resources(struct mpi3mr_ioc * mrioc)3638 void mpi3mr_cleanup_resources(struct mpi3mr_ioc *mrioc)
3639 {
3640 struct pci_dev *pdev = mrioc->pdev;
3641
3642 mpi3mr_cleanup_isr(mrioc);
3643
3644 if (mrioc->sysif_regs) {
3645 iounmap((void __iomem *)mrioc->sysif_regs);
3646 mrioc->sysif_regs = NULL;
3647 }
3648
3649 if (pci_is_enabled(pdev)) {
3650 if (mrioc->bars)
3651 pci_release_selected_regions(pdev, mrioc->bars);
3652 pci_disable_device(pdev);
3653 }
3654 }
3655
3656 /**
3657 * mpi3mr_setup_resources - Enable PCI resources
3658 * @mrioc: Adapter instance reference
3659 *
3660 * Enable PCI device memory, MSI-x registers and set DMA mask.
3661 *
3662 * Return: 0 on success and non-zero on failure.
3663 */
mpi3mr_setup_resources(struct mpi3mr_ioc * mrioc)3664 int mpi3mr_setup_resources(struct mpi3mr_ioc *mrioc)
3665 {
3666 struct pci_dev *pdev = mrioc->pdev;
3667 u32 memap_sz = 0;
3668 int i, retval = 0, capb = 0;
3669 u16 message_control;
3670 u64 dma_mask = mrioc->dma_mask ? mrioc->dma_mask :
3671 ((sizeof(dma_addr_t) > 4) ? DMA_BIT_MASK(64) : DMA_BIT_MASK(32));
3672
3673 if (pci_enable_device_mem(pdev)) {
3674 ioc_err(mrioc, "pci_enable_device_mem: failed\n");
3675 retval = -ENODEV;
3676 goto out_failed;
3677 }
3678
3679 capb = pci_find_capability(pdev, PCI_CAP_ID_MSIX);
3680 if (!capb) {
3681 ioc_err(mrioc, "Unable to find MSI-X Capabilities\n");
3682 retval = -ENODEV;
3683 goto out_failed;
3684 }
3685 mrioc->bars = pci_select_bars(pdev, IORESOURCE_MEM);
3686
3687 if (pci_request_selected_regions(pdev, mrioc->bars,
3688 mrioc->driver_name)) {
3689 ioc_err(mrioc, "pci_request_selected_regions: failed\n");
3690 retval = -ENODEV;
3691 goto out_failed;
3692 }
3693
3694 for (i = 0; (i < DEVICE_COUNT_RESOURCE); i++) {
3695 if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) {
3696 mrioc->sysif_regs_phys = pci_resource_start(pdev, i);
3697 memap_sz = pci_resource_len(pdev, i);
3698 mrioc->sysif_regs =
3699 ioremap(mrioc->sysif_regs_phys, memap_sz);
3700 break;
3701 }
3702 }
3703
3704 pci_set_master(pdev);
3705
3706 retval = dma_set_mask_and_coherent(&pdev->dev, dma_mask);
3707 if (retval) {
3708 if (dma_mask != DMA_BIT_MASK(32)) {
3709 ioc_warn(mrioc, "Setting 64 bit DMA mask failed\n");
3710 dma_mask = DMA_BIT_MASK(32);
3711 retval = dma_set_mask_and_coherent(&pdev->dev,
3712 dma_mask);
3713 }
3714 if (retval) {
3715 mrioc->dma_mask = 0;
3716 ioc_err(mrioc, "Setting 32 bit DMA mask also failed\n");
3717 goto out_failed;
3718 }
3719 }
3720 mrioc->dma_mask = dma_mask;
3721
3722 if (!mrioc->sysif_regs) {
3723 ioc_err(mrioc,
3724 "Unable to map adapter memory or resource not found\n");
3725 retval = -EINVAL;
3726 goto out_failed;
3727 }
3728
3729 pci_read_config_word(pdev, capb + 2, &message_control);
3730 mrioc->msix_count = (message_control & 0x3FF) + 1;
3731
3732 pci_save_state(pdev);
3733
3734 pci_set_drvdata(pdev, mrioc->shost);
3735
3736 mpi3mr_ioc_disable_intr(mrioc);
3737
3738 ioc_info(mrioc, "iomem(0x%016llx), mapped(0x%p), size(%d)\n",
3739 (unsigned long long)mrioc->sysif_regs_phys,
3740 mrioc->sysif_regs, memap_sz);
3741 ioc_info(mrioc, "Number of MSI-X vectors found in capabilities: (%d)\n",
3742 mrioc->msix_count);
3743
3744 if (!reset_devices && poll_queues > 0)
3745 mrioc->requested_poll_qcount = min_t(int, poll_queues,
3746 mrioc->msix_count - 2);
3747 return retval;
3748
3749 out_failed:
3750 mpi3mr_cleanup_resources(mrioc);
3751 return retval;
3752 }
3753
3754 /**
3755 * mpi3mr_enable_events - Enable required events
3756 * @mrioc: Adapter instance reference
3757 *
3758 * This routine unmasks the events required by the driver by
3759 * sennding appropriate event mask bitmapt through an event
3760 * notification request.
3761 *
3762 * Return: 0 on success and non-zero on failure.
3763 */
mpi3mr_enable_events(struct mpi3mr_ioc * mrioc)3764 static int mpi3mr_enable_events(struct mpi3mr_ioc *mrioc)
3765 {
3766 int retval = 0;
3767 u32 i;
3768
3769 for (i = 0; i < MPI3_EVENT_NOTIFY_EVENTMASK_WORDS; i++)
3770 mrioc->event_masks[i] = -1;
3771
3772 mpi3mr_unmask_events(mrioc, MPI3_EVENT_DEVICE_ADDED);
3773 mpi3mr_unmask_events(mrioc, MPI3_EVENT_DEVICE_INFO_CHANGED);
3774 mpi3mr_unmask_events(mrioc, MPI3_EVENT_DEVICE_STATUS_CHANGE);
3775 mpi3mr_unmask_events(mrioc, MPI3_EVENT_ENCL_DEVICE_STATUS_CHANGE);
3776 mpi3mr_unmask_events(mrioc, MPI3_EVENT_ENCL_DEVICE_ADDED);
3777 mpi3mr_unmask_events(mrioc, MPI3_EVENT_SAS_TOPOLOGY_CHANGE_LIST);
3778 mpi3mr_unmask_events(mrioc, MPI3_EVENT_SAS_DISCOVERY);
3779 mpi3mr_unmask_events(mrioc, MPI3_EVENT_SAS_DEVICE_DISCOVERY_ERROR);
3780 mpi3mr_unmask_events(mrioc, MPI3_EVENT_SAS_BROADCAST_PRIMITIVE);
3781 mpi3mr_unmask_events(mrioc, MPI3_EVENT_PCIE_TOPOLOGY_CHANGE_LIST);
3782 mpi3mr_unmask_events(mrioc, MPI3_EVENT_PCIE_ENUMERATION);
3783 mpi3mr_unmask_events(mrioc, MPI3_EVENT_PREPARE_FOR_RESET);
3784 mpi3mr_unmask_events(mrioc, MPI3_EVENT_CABLE_MGMT);
3785 mpi3mr_unmask_events(mrioc, MPI3_EVENT_ENERGY_PACK_CHANGE);
3786
3787 retval = mpi3mr_issue_event_notification(mrioc);
3788 if (retval)
3789 ioc_err(mrioc, "failed to issue event notification %d\n",
3790 retval);
3791 return retval;
3792 }
3793
3794 /**
3795 * mpi3mr_init_ioc - Initialize the controller
3796 * @mrioc: Adapter instance reference
3797 *
3798 * This the controller initialization routine, executed either
3799 * after soft reset or from pci probe callback.
3800 * Setup the required resources, memory map the controller
3801 * registers, create admin and operational reply queue pairs,
3802 * allocate required memory for reply pool, sense buffer pool,
3803 * issue IOC init request to the firmware, unmask the events and
3804 * issue port enable to discover SAS/SATA/NVMe devies and RAID
3805 * volumes.
3806 *
3807 * Return: 0 on success and non-zero on failure.
3808 */
mpi3mr_init_ioc(struct mpi3mr_ioc * mrioc)3809 int mpi3mr_init_ioc(struct mpi3mr_ioc *mrioc)
3810 {
3811 int retval = 0;
3812 u8 retry = 0;
3813 struct mpi3_ioc_facts_data facts_data;
3814 u32 sz;
3815
3816 retry_init:
3817 retval = mpi3mr_bring_ioc_ready(mrioc);
3818 if (retval) {
3819 ioc_err(mrioc, "Failed to bring ioc ready: error %d\n",
3820 retval);
3821 goto out_failed_noretry;
3822 }
3823
3824 retval = mpi3mr_setup_isr(mrioc, 1);
3825 if (retval) {
3826 ioc_err(mrioc, "Failed to setup ISR error %d\n",
3827 retval);
3828 goto out_failed_noretry;
3829 }
3830
3831 retval = mpi3mr_issue_iocfacts(mrioc, &facts_data);
3832 if (retval) {
3833 ioc_err(mrioc, "Failed to Issue IOC Facts %d\n",
3834 retval);
3835 goto out_failed;
3836 }
3837
3838 mrioc->max_host_ios = mrioc->facts.max_reqs - MPI3MR_INTERNAL_CMDS_RESVD;
3839 mrioc->shost->max_sectors = mrioc->facts.max_data_length / 512;
3840 mrioc->num_io_throttle_group = mrioc->facts.max_io_throttle_group;
3841 atomic_set(&mrioc->pend_large_data_sz, 0);
3842
3843 if (reset_devices)
3844 mrioc->max_host_ios = min_t(int, mrioc->max_host_ios,
3845 MPI3MR_HOST_IOS_KDUMP);
3846
3847 if (!(mrioc->facts.ioc_capabilities &
3848 MPI3_IOCFACTS_CAPABILITY_MULTIPATH_ENABLED)) {
3849 mrioc->sas_transport_enabled = 1;
3850 mrioc->scsi_device_channel = 1;
3851 mrioc->shost->max_channel = 1;
3852 mrioc->shost->transportt = mpi3mr_transport_template;
3853 }
3854
3855 mrioc->reply_sz = mrioc->facts.reply_sz;
3856
3857 retval = mpi3mr_check_reset_dma_mask(mrioc);
3858 if (retval) {
3859 ioc_err(mrioc, "Resetting dma mask failed %d\n",
3860 retval);
3861 goto out_failed_noretry;
3862 }
3863
3864 mpi3mr_print_ioc_info(mrioc);
3865
3866 if (!mrioc->cfg_page) {
3867 dprint_init(mrioc, "allocating config page buffers\n");
3868 mrioc->cfg_page_sz = MPI3MR_DEFAULT_CFG_PAGE_SZ;
3869 mrioc->cfg_page = dma_alloc_coherent(&mrioc->pdev->dev,
3870 mrioc->cfg_page_sz, &mrioc->cfg_page_dma, GFP_KERNEL);
3871 if (!mrioc->cfg_page) {
3872 retval = -1;
3873 goto out_failed_noretry;
3874 }
3875 }
3876
3877 if (!mrioc->init_cmds.reply) {
3878 retval = mpi3mr_alloc_reply_sense_bufs(mrioc);
3879 if (retval) {
3880 ioc_err(mrioc,
3881 "%s :Failed to allocated reply sense buffers %d\n",
3882 __func__, retval);
3883 goto out_failed_noretry;
3884 }
3885 }
3886
3887 if (!mrioc->chain_sgl_list) {
3888 retval = mpi3mr_alloc_chain_bufs(mrioc);
3889 if (retval) {
3890 ioc_err(mrioc, "Failed to allocated chain buffers %d\n",
3891 retval);
3892 goto out_failed_noretry;
3893 }
3894 }
3895
3896 retval = mpi3mr_issue_iocinit(mrioc);
3897 if (retval) {
3898 ioc_err(mrioc, "Failed to Issue IOC Init %d\n",
3899 retval);
3900 goto out_failed;
3901 }
3902
3903 retval = mpi3mr_print_pkg_ver(mrioc);
3904 if (retval) {
3905 ioc_err(mrioc, "failed to get package version\n");
3906 goto out_failed;
3907 }
3908
3909 retval = mpi3mr_setup_isr(mrioc, 0);
3910 if (retval) {
3911 ioc_err(mrioc, "Failed to re-setup ISR, error %d\n",
3912 retval);
3913 goto out_failed_noretry;
3914 }
3915
3916 retval = mpi3mr_create_op_queues(mrioc);
3917 if (retval) {
3918 ioc_err(mrioc, "Failed to create OpQueues error %d\n",
3919 retval);
3920 goto out_failed;
3921 }
3922
3923 if (!mrioc->pel_seqnum_virt) {
3924 dprint_init(mrioc, "allocating memory for pel_seqnum_virt\n");
3925 mrioc->pel_seqnum_sz = sizeof(struct mpi3_pel_seq);
3926 mrioc->pel_seqnum_virt = dma_alloc_coherent(&mrioc->pdev->dev,
3927 mrioc->pel_seqnum_sz, &mrioc->pel_seqnum_dma,
3928 GFP_KERNEL);
3929 if (!mrioc->pel_seqnum_virt) {
3930 retval = -ENOMEM;
3931 goto out_failed_noretry;
3932 }
3933 }
3934
3935 if (!mrioc->throttle_groups && mrioc->num_io_throttle_group) {
3936 dprint_init(mrioc, "allocating memory for throttle groups\n");
3937 sz = sizeof(struct mpi3mr_throttle_group_info);
3938 mrioc->throttle_groups = kcalloc(mrioc->num_io_throttle_group, sz, GFP_KERNEL);
3939 if (!mrioc->throttle_groups) {
3940 retval = -1;
3941 goto out_failed_noretry;
3942 }
3943 }
3944
3945 retval = mpi3mr_enable_events(mrioc);
3946 if (retval) {
3947 ioc_err(mrioc, "failed to enable events %d\n",
3948 retval);
3949 goto out_failed;
3950 }
3951
3952 ioc_info(mrioc, "controller initialization completed successfully\n");
3953 return retval;
3954 out_failed:
3955 if (retry < 2) {
3956 retry++;
3957 ioc_warn(mrioc, "retrying controller initialization, retry_count:%d\n",
3958 retry);
3959 mpi3mr_memset_buffers(mrioc);
3960 goto retry_init;
3961 }
3962 retval = -1;
3963 out_failed_noretry:
3964 ioc_err(mrioc, "controller initialization failed\n");
3965 mpi3mr_issue_reset(mrioc, MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT,
3966 MPI3MR_RESET_FROM_CTLR_CLEANUP);
3967 mrioc->unrecoverable = 1;
3968 return retval;
3969 }
3970
3971 /**
3972 * mpi3mr_reinit_ioc - Re-Initialize the controller
3973 * @mrioc: Adapter instance reference
3974 * @is_resume: Called from resume or reset path
3975 *
3976 * This the controller re-initialization routine, executed from
3977 * the soft reset handler or resume callback. Creates
3978 * operational reply queue pairs, allocate required memory for
3979 * reply pool, sense buffer pool, issue IOC init request to the
3980 * firmware, unmask the events and issue port enable to discover
3981 * SAS/SATA/NVMe devices and RAID volumes.
3982 *
3983 * Return: 0 on success and non-zero on failure.
3984 */
mpi3mr_reinit_ioc(struct mpi3mr_ioc * mrioc,u8 is_resume)3985 int mpi3mr_reinit_ioc(struct mpi3mr_ioc *mrioc, u8 is_resume)
3986 {
3987 int retval = 0;
3988 u8 retry = 0;
3989 struct mpi3_ioc_facts_data facts_data;
3990 u32 pe_timeout, ioc_status;
3991
3992 retry_init:
3993 pe_timeout =
3994 (MPI3MR_PORTENABLE_TIMEOUT / MPI3MR_PORTENABLE_POLL_INTERVAL);
3995
3996 dprint_reset(mrioc, "bringing up the controller to ready state\n");
3997 retval = mpi3mr_bring_ioc_ready(mrioc);
3998 if (retval) {
3999 ioc_err(mrioc, "failed to bring to ready state\n");
4000 goto out_failed_noretry;
4001 }
4002
4003 if (is_resume) {
4004 dprint_reset(mrioc, "setting up single ISR\n");
4005 retval = mpi3mr_setup_isr(mrioc, 1);
4006 if (retval) {
4007 ioc_err(mrioc, "failed to setup ISR\n");
4008 goto out_failed_noretry;
4009 }
4010 } else
4011 mpi3mr_ioc_enable_intr(mrioc);
4012
4013 dprint_reset(mrioc, "getting ioc_facts\n");
4014 retval = mpi3mr_issue_iocfacts(mrioc, &facts_data);
4015 if (retval) {
4016 ioc_err(mrioc, "failed to get ioc_facts\n");
4017 goto out_failed;
4018 }
4019
4020 dprint_reset(mrioc, "validating ioc_facts\n");
4021 retval = mpi3mr_revalidate_factsdata(mrioc);
4022 if (retval) {
4023 ioc_err(mrioc, "failed to revalidate ioc_facts data\n");
4024 goto out_failed_noretry;
4025 }
4026
4027 mpi3mr_print_ioc_info(mrioc);
4028
4029 dprint_reset(mrioc, "sending ioc_init\n");
4030 retval = mpi3mr_issue_iocinit(mrioc);
4031 if (retval) {
4032 ioc_err(mrioc, "failed to send ioc_init\n");
4033 goto out_failed;
4034 }
4035
4036 dprint_reset(mrioc, "getting package version\n");
4037 retval = mpi3mr_print_pkg_ver(mrioc);
4038 if (retval) {
4039 ioc_err(mrioc, "failed to get package version\n");
4040 goto out_failed;
4041 }
4042
4043 if (is_resume) {
4044 dprint_reset(mrioc, "setting up multiple ISR\n");
4045 retval = mpi3mr_setup_isr(mrioc, 0);
4046 if (retval) {
4047 ioc_err(mrioc, "failed to re-setup ISR\n");
4048 goto out_failed_noretry;
4049 }
4050 }
4051
4052 dprint_reset(mrioc, "creating operational queue pairs\n");
4053 retval = mpi3mr_create_op_queues(mrioc);
4054 if (retval) {
4055 ioc_err(mrioc, "failed to create operational queue pairs\n");
4056 goto out_failed;
4057 }
4058
4059 if (!mrioc->pel_seqnum_virt) {
4060 dprint_reset(mrioc, "allocating memory for pel_seqnum_virt\n");
4061 mrioc->pel_seqnum_sz = sizeof(struct mpi3_pel_seq);
4062 mrioc->pel_seqnum_virt = dma_alloc_coherent(&mrioc->pdev->dev,
4063 mrioc->pel_seqnum_sz, &mrioc->pel_seqnum_dma,
4064 GFP_KERNEL);
4065 if (!mrioc->pel_seqnum_virt) {
4066 retval = -ENOMEM;
4067 goto out_failed_noretry;
4068 }
4069 }
4070
4071 if (mrioc->shost->nr_hw_queues > mrioc->num_op_reply_q) {
4072 ioc_err(mrioc,
4073 "cannot create minimum number of operational queues expected:%d created:%d\n",
4074 mrioc->shost->nr_hw_queues, mrioc->num_op_reply_q);
4075 retval = -1;
4076 goto out_failed_noretry;
4077 }
4078
4079 dprint_reset(mrioc, "enabling events\n");
4080 retval = mpi3mr_enable_events(mrioc);
4081 if (retval) {
4082 ioc_err(mrioc, "failed to enable events\n");
4083 goto out_failed;
4084 }
4085
4086 mrioc->device_refresh_on = 1;
4087 mpi3mr_add_event_wait_for_device_refresh(mrioc);
4088
4089 ioc_info(mrioc, "sending port enable\n");
4090 retval = mpi3mr_issue_port_enable(mrioc, 1);
4091 if (retval) {
4092 ioc_err(mrioc, "failed to issue port enable\n");
4093 goto out_failed;
4094 }
4095 do {
4096 ssleep(MPI3MR_PORTENABLE_POLL_INTERVAL);
4097 if (mrioc->init_cmds.state == MPI3MR_CMD_NOTUSED)
4098 break;
4099 if (!pci_device_is_present(mrioc->pdev))
4100 mrioc->unrecoverable = 1;
4101 if (mrioc->unrecoverable) {
4102 retval = -1;
4103 goto out_failed_noretry;
4104 }
4105 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
4106 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY) ||
4107 (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT)) {
4108 mpi3mr_print_fault_info(mrioc);
4109 mrioc->init_cmds.is_waiting = 0;
4110 mrioc->init_cmds.callback = NULL;
4111 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
4112 goto out_failed;
4113 }
4114 } while (--pe_timeout);
4115
4116 if (!pe_timeout) {
4117 ioc_err(mrioc, "port enable timed out\n");
4118 mpi3mr_check_rh_fault_ioc(mrioc,
4119 MPI3MR_RESET_FROM_PE_TIMEOUT);
4120 mrioc->init_cmds.is_waiting = 0;
4121 mrioc->init_cmds.callback = NULL;
4122 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
4123 goto out_failed;
4124 } else if (mrioc->scan_failed) {
4125 ioc_err(mrioc,
4126 "port enable failed with status=0x%04x\n",
4127 mrioc->scan_failed);
4128 } else
4129 ioc_info(mrioc, "port enable completed successfully\n");
4130
4131 ioc_info(mrioc, "controller %s completed successfully\n",
4132 (is_resume)?"resume":"re-initialization");
4133 return retval;
4134 out_failed:
4135 if (retry < 2) {
4136 retry++;
4137 ioc_warn(mrioc, "retrying controller %s, retry_count:%d\n",
4138 (is_resume)?"resume":"re-initialization", retry);
4139 mpi3mr_memset_buffers(mrioc);
4140 goto retry_init;
4141 }
4142 retval = -1;
4143 out_failed_noretry:
4144 ioc_err(mrioc, "controller %s is failed\n",
4145 (is_resume)?"resume":"re-initialization");
4146 mpi3mr_issue_reset(mrioc, MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT,
4147 MPI3MR_RESET_FROM_CTLR_CLEANUP);
4148 mrioc->unrecoverable = 1;
4149 return retval;
4150 }
4151
4152 /**
4153 * mpi3mr_memset_op_reply_q_buffers - memset the operational reply queue's
4154 * segments
4155 * @mrioc: Adapter instance reference
4156 * @qidx: Operational reply queue index
4157 *
4158 * Return: Nothing.
4159 */
mpi3mr_memset_op_reply_q_buffers(struct mpi3mr_ioc * mrioc,u16 qidx)4160 static void mpi3mr_memset_op_reply_q_buffers(struct mpi3mr_ioc *mrioc, u16 qidx)
4161 {
4162 struct op_reply_qinfo *op_reply_q = mrioc->op_reply_qinfo + qidx;
4163 struct segments *segments;
4164 int i, size;
4165
4166 if (!op_reply_q->q_segments)
4167 return;
4168
4169 size = op_reply_q->segment_qd * mrioc->op_reply_desc_sz;
4170 segments = op_reply_q->q_segments;
4171 for (i = 0; i < op_reply_q->num_segments; i++)
4172 memset(segments[i].segment, 0, size);
4173 }
4174
4175 /**
4176 * mpi3mr_memset_op_req_q_buffers - memset the operational request queue's
4177 * segments
4178 * @mrioc: Adapter instance reference
4179 * @qidx: Operational request queue index
4180 *
4181 * Return: Nothing.
4182 */
mpi3mr_memset_op_req_q_buffers(struct mpi3mr_ioc * mrioc,u16 qidx)4183 static void mpi3mr_memset_op_req_q_buffers(struct mpi3mr_ioc *mrioc, u16 qidx)
4184 {
4185 struct op_req_qinfo *op_req_q = mrioc->req_qinfo + qidx;
4186 struct segments *segments;
4187 int i, size;
4188
4189 if (!op_req_q->q_segments)
4190 return;
4191
4192 size = op_req_q->segment_qd * mrioc->facts.op_req_sz;
4193 segments = op_req_q->q_segments;
4194 for (i = 0; i < op_req_q->num_segments; i++)
4195 memset(segments[i].segment, 0, size);
4196 }
4197
4198 /**
4199 * mpi3mr_memset_buffers - memset memory for a controller
4200 * @mrioc: Adapter instance reference
4201 *
4202 * clear all the memory allocated for a controller, typically
4203 * called post reset to reuse the memory allocated during the
4204 * controller init.
4205 *
4206 * Return: Nothing.
4207 */
mpi3mr_memset_buffers(struct mpi3mr_ioc * mrioc)4208 void mpi3mr_memset_buffers(struct mpi3mr_ioc *mrioc)
4209 {
4210 u16 i;
4211 struct mpi3mr_throttle_group_info *tg;
4212
4213 mrioc->change_count = 0;
4214 mrioc->active_poll_qcount = 0;
4215 mrioc->default_qcount = 0;
4216 if (mrioc->admin_req_base)
4217 memset(mrioc->admin_req_base, 0, mrioc->admin_req_q_sz);
4218 if (mrioc->admin_reply_base)
4219 memset(mrioc->admin_reply_base, 0, mrioc->admin_reply_q_sz);
4220 atomic_set(&mrioc->admin_reply_q_in_use, 0);
4221
4222 if (mrioc->init_cmds.reply) {
4223 memset(mrioc->init_cmds.reply, 0, sizeof(*mrioc->init_cmds.reply));
4224 memset(mrioc->bsg_cmds.reply, 0,
4225 sizeof(*mrioc->bsg_cmds.reply));
4226 memset(mrioc->host_tm_cmds.reply, 0,
4227 sizeof(*mrioc->host_tm_cmds.reply));
4228 memset(mrioc->pel_cmds.reply, 0,
4229 sizeof(*mrioc->pel_cmds.reply));
4230 memset(mrioc->pel_abort_cmd.reply, 0,
4231 sizeof(*mrioc->pel_abort_cmd.reply));
4232 memset(mrioc->transport_cmds.reply, 0,
4233 sizeof(*mrioc->transport_cmds.reply));
4234 for (i = 0; i < MPI3MR_NUM_DEVRMCMD; i++)
4235 memset(mrioc->dev_rmhs_cmds[i].reply, 0,
4236 sizeof(*mrioc->dev_rmhs_cmds[i].reply));
4237 for (i = 0; i < MPI3MR_NUM_EVTACKCMD; i++)
4238 memset(mrioc->evtack_cmds[i].reply, 0,
4239 sizeof(*mrioc->evtack_cmds[i].reply));
4240 bitmap_clear(mrioc->removepend_bitmap, 0,
4241 mrioc->dev_handle_bitmap_bits);
4242 bitmap_clear(mrioc->devrem_bitmap, 0, MPI3MR_NUM_DEVRMCMD);
4243 bitmap_clear(mrioc->evtack_cmds_bitmap, 0,
4244 MPI3MR_NUM_EVTACKCMD);
4245 }
4246
4247 for (i = 0; i < mrioc->num_queues; i++) {
4248 mrioc->op_reply_qinfo[i].qid = 0;
4249 mrioc->op_reply_qinfo[i].ci = 0;
4250 mrioc->op_reply_qinfo[i].num_replies = 0;
4251 mrioc->op_reply_qinfo[i].ephase = 0;
4252 atomic_set(&mrioc->op_reply_qinfo[i].pend_ios, 0);
4253 atomic_set(&mrioc->op_reply_qinfo[i].in_use, 0);
4254 mpi3mr_memset_op_reply_q_buffers(mrioc, i);
4255
4256 mrioc->req_qinfo[i].ci = 0;
4257 mrioc->req_qinfo[i].pi = 0;
4258 mrioc->req_qinfo[i].num_requests = 0;
4259 mrioc->req_qinfo[i].qid = 0;
4260 mrioc->req_qinfo[i].reply_qid = 0;
4261 spin_lock_init(&mrioc->req_qinfo[i].q_lock);
4262 mpi3mr_memset_op_req_q_buffers(mrioc, i);
4263 }
4264
4265 atomic_set(&mrioc->pend_large_data_sz, 0);
4266 if (mrioc->throttle_groups) {
4267 tg = mrioc->throttle_groups;
4268 for (i = 0; i < mrioc->num_io_throttle_group; i++, tg++) {
4269 tg->id = 0;
4270 tg->fw_qd = 0;
4271 tg->modified_qd = 0;
4272 tg->io_divert = 0;
4273 tg->need_qd_reduction = 0;
4274 tg->high = 0;
4275 tg->low = 0;
4276 tg->qd_reduction = 0;
4277 atomic_set(&tg->pend_large_data_sz, 0);
4278 }
4279 }
4280 }
4281
4282 /**
4283 * mpi3mr_free_mem - Free memory allocated for a controller
4284 * @mrioc: Adapter instance reference
4285 *
4286 * Free all the memory allocated for a controller.
4287 *
4288 * Return: Nothing.
4289 */
mpi3mr_free_mem(struct mpi3mr_ioc * mrioc)4290 void mpi3mr_free_mem(struct mpi3mr_ioc *mrioc)
4291 {
4292 u16 i;
4293 struct mpi3mr_intr_info *intr_info;
4294
4295 mpi3mr_free_enclosure_list(mrioc);
4296
4297 if (mrioc->sense_buf_pool) {
4298 if (mrioc->sense_buf)
4299 dma_pool_free(mrioc->sense_buf_pool, mrioc->sense_buf,
4300 mrioc->sense_buf_dma);
4301 dma_pool_destroy(mrioc->sense_buf_pool);
4302 mrioc->sense_buf = NULL;
4303 mrioc->sense_buf_pool = NULL;
4304 }
4305 if (mrioc->sense_buf_q_pool) {
4306 if (mrioc->sense_buf_q)
4307 dma_pool_free(mrioc->sense_buf_q_pool,
4308 mrioc->sense_buf_q, mrioc->sense_buf_q_dma);
4309 dma_pool_destroy(mrioc->sense_buf_q_pool);
4310 mrioc->sense_buf_q = NULL;
4311 mrioc->sense_buf_q_pool = NULL;
4312 }
4313
4314 if (mrioc->reply_buf_pool) {
4315 if (mrioc->reply_buf)
4316 dma_pool_free(mrioc->reply_buf_pool, mrioc->reply_buf,
4317 mrioc->reply_buf_dma);
4318 dma_pool_destroy(mrioc->reply_buf_pool);
4319 mrioc->reply_buf = NULL;
4320 mrioc->reply_buf_pool = NULL;
4321 }
4322 if (mrioc->reply_free_q_pool) {
4323 if (mrioc->reply_free_q)
4324 dma_pool_free(mrioc->reply_free_q_pool,
4325 mrioc->reply_free_q, mrioc->reply_free_q_dma);
4326 dma_pool_destroy(mrioc->reply_free_q_pool);
4327 mrioc->reply_free_q = NULL;
4328 mrioc->reply_free_q_pool = NULL;
4329 }
4330
4331 for (i = 0; i < mrioc->num_op_req_q; i++)
4332 mpi3mr_free_op_req_q_segments(mrioc, i);
4333
4334 for (i = 0; i < mrioc->num_op_reply_q; i++)
4335 mpi3mr_free_op_reply_q_segments(mrioc, i);
4336
4337 for (i = 0; i < mrioc->intr_info_count; i++) {
4338 intr_info = mrioc->intr_info + i;
4339 intr_info->op_reply_q = NULL;
4340 }
4341
4342 kfree(mrioc->req_qinfo);
4343 mrioc->req_qinfo = NULL;
4344 mrioc->num_op_req_q = 0;
4345
4346 kfree(mrioc->op_reply_qinfo);
4347 mrioc->op_reply_qinfo = NULL;
4348 mrioc->num_op_reply_q = 0;
4349
4350 kfree(mrioc->init_cmds.reply);
4351 mrioc->init_cmds.reply = NULL;
4352
4353 kfree(mrioc->bsg_cmds.reply);
4354 mrioc->bsg_cmds.reply = NULL;
4355
4356 kfree(mrioc->host_tm_cmds.reply);
4357 mrioc->host_tm_cmds.reply = NULL;
4358
4359 kfree(mrioc->pel_cmds.reply);
4360 mrioc->pel_cmds.reply = NULL;
4361
4362 kfree(mrioc->pel_abort_cmd.reply);
4363 mrioc->pel_abort_cmd.reply = NULL;
4364
4365 for (i = 0; i < MPI3MR_NUM_EVTACKCMD; i++) {
4366 kfree(mrioc->evtack_cmds[i].reply);
4367 mrioc->evtack_cmds[i].reply = NULL;
4368 }
4369
4370 bitmap_free(mrioc->removepend_bitmap);
4371 mrioc->removepend_bitmap = NULL;
4372
4373 bitmap_free(mrioc->devrem_bitmap);
4374 mrioc->devrem_bitmap = NULL;
4375
4376 bitmap_free(mrioc->evtack_cmds_bitmap);
4377 mrioc->evtack_cmds_bitmap = NULL;
4378
4379 bitmap_free(mrioc->chain_bitmap);
4380 mrioc->chain_bitmap = NULL;
4381
4382 kfree(mrioc->transport_cmds.reply);
4383 mrioc->transport_cmds.reply = NULL;
4384
4385 for (i = 0; i < MPI3MR_NUM_DEVRMCMD; i++) {
4386 kfree(mrioc->dev_rmhs_cmds[i].reply);
4387 mrioc->dev_rmhs_cmds[i].reply = NULL;
4388 }
4389
4390 if (mrioc->chain_buf_pool) {
4391 for (i = 0; i < mrioc->chain_buf_count; i++) {
4392 if (mrioc->chain_sgl_list[i].addr) {
4393 dma_pool_free(mrioc->chain_buf_pool,
4394 mrioc->chain_sgl_list[i].addr,
4395 mrioc->chain_sgl_list[i].dma_addr);
4396 mrioc->chain_sgl_list[i].addr = NULL;
4397 }
4398 }
4399 dma_pool_destroy(mrioc->chain_buf_pool);
4400 mrioc->chain_buf_pool = NULL;
4401 }
4402
4403 kfree(mrioc->chain_sgl_list);
4404 mrioc->chain_sgl_list = NULL;
4405
4406 if (mrioc->admin_reply_base) {
4407 dma_free_coherent(&mrioc->pdev->dev, mrioc->admin_reply_q_sz,
4408 mrioc->admin_reply_base, mrioc->admin_reply_dma);
4409 mrioc->admin_reply_base = NULL;
4410 }
4411 if (mrioc->admin_req_base) {
4412 dma_free_coherent(&mrioc->pdev->dev, mrioc->admin_req_q_sz,
4413 mrioc->admin_req_base, mrioc->admin_req_dma);
4414 mrioc->admin_req_base = NULL;
4415 }
4416 if (mrioc->cfg_page) {
4417 dma_free_coherent(&mrioc->pdev->dev, mrioc->cfg_page_sz,
4418 mrioc->cfg_page, mrioc->cfg_page_dma);
4419 mrioc->cfg_page = NULL;
4420 }
4421 if (mrioc->pel_seqnum_virt) {
4422 dma_free_coherent(&mrioc->pdev->dev, mrioc->pel_seqnum_sz,
4423 mrioc->pel_seqnum_virt, mrioc->pel_seqnum_dma);
4424 mrioc->pel_seqnum_virt = NULL;
4425 }
4426
4427 kfree(mrioc->throttle_groups);
4428 mrioc->throttle_groups = NULL;
4429
4430 kfree(mrioc->logdata_buf);
4431 mrioc->logdata_buf = NULL;
4432
4433 }
4434
4435 /**
4436 * mpi3mr_issue_ioc_shutdown - shutdown controller
4437 * @mrioc: Adapter instance reference
4438 *
4439 * Send shutodwn notification to the controller and wait for the
4440 * shutdown_timeout for it to be completed.
4441 *
4442 * Return: Nothing.
4443 */
mpi3mr_issue_ioc_shutdown(struct mpi3mr_ioc * mrioc)4444 static void mpi3mr_issue_ioc_shutdown(struct mpi3mr_ioc *mrioc)
4445 {
4446 u32 ioc_config, ioc_status;
4447 u8 retval = 1;
4448 u32 timeout = MPI3MR_DEFAULT_SHUTDOWN_TIME * 10;
4449
4450 ioc_info(mrioc, "Issuing shutdown Notification\n");
4451 if (mrioc->unrecoverable) {
4452 ioc_warn(mrioc,
4453 "IOC is unrecoverable shutdown is not issued\n");
4454 return;
4455 }
4456 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
4457 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_SHUTDOWN_MASK)
4458 == MPI3_SYSIF_IOC_STATUS_SHUTDOWN_IN_PROGRESS) {
4459 ioc_info(mrioc, "shutdown already in progress\n");
4460 return;
4461 }
4462
4463 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
4464 ioc_config |= MPI3_SYSIF_IOC_CONFIG_SHUTDOWN_NORMAL;
4465 ioc_config |= MPI3_SYSIF_IOC_CONFIG_DEVICE_SHUTDOWN_SEND_REQ;
4466
4467 writel(ioc_config, &mrioc->sysif_regs->ioc_configuration);
4468
4469 if (mrioc->facts.shutdown_timeout)
4470 timeout = mrioc->facts.shutdown_timeout * 10;
4471
4472 do {
4473 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
4474 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_SHUTDOWN_MASK)
4475 == MPI3_SYSIF_IOC_STATUS_SHUTDOWN_COMPLETE) {
4476 retval = 0;
4477 break;
4478 }
4479 msleep(100);
4480 } while (--timeout);
4481
4482 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
4483 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
4484
4485 if (retval) {
4486 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_SHUTDOWN_MASK)
4487 == MPI3_SYSIF_IOC_STATUS_SHUTDOWN_IN_PROGRESS)
4488 ioc_warn(mrioc,
4489 "shutdown still in progress after timeout\n");
4490 }
4491
4492 ioc_info(mrioc,
4493 "Base IOC Sts/Config after %s shutdown is (0x%x)/(0x%x)\n",
4494 (!retval) ? "successful" : "failed", ioc_status,
4495 ioc_config);
4496 }
4497
4498 /**
4499 * mpi3mr_cleanup_ioc - Cleanup controller
4500 * @mrioc: Adapter instance reference
4501 *
4502 * controller cleanup handler, Message unit reset or soft reset
4503 * and shutdown notification is issued to the controller.
4504 *
4505 * Return: Nothing.
4506 */
mpi3mr_cleanup_ioc(struct mpi3mr_ioc * mrioc)4507 void mpi3mr_cleanup_ioc(struct mpi3mr_ioc *mrioc)
4508 {
4509 enum mpi3mr_iocstate ioc_state;
4510
4511 dprint_exit(mrioc, "cleaning up the controller\n");
4512 mpi3mr_ioc_disable_intr(mrioc);
4513
4514 ioc_state = mpi3mr_get_iocstate(mrioc);
4515
4516 if ((!mrioc->unrecoverable) && (!mrioc->reset_in_progress) &&
4517 (ioc_state == MRIOC_STATE_READY)) {
4518 if (mpi3mr_issue_and_process_mur(mrioc,
4519 MPI3MR_RESET_FROM_CTLR_CLEANUP))
4520 mpi3mr_issue_reset(mrioc,
4521 MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET,
4522 MPI3MR_RESET_FROM_MUR_FAILURE);
4523 mpi3mr_issue_ioc_shutdown(mrioc);
4524 }
4525 dprint_exit(mrioc, "controller cleanup completed\n");
4526 }
4527
4528 /**
4529 * mpi3mr_drv_cmd_comp_reset - Flush a internal driver command
4530 * @mrioc: Adapter instance reference
4531 * @cmdptr: Internal command tracker
4532 *
4533 * Complete an internal driver commands with state indicating it
4534 * is completed due to reset.
4535 *
4536 * Return: Nothing.
4537 */
mpi3mr_drv_cmd_comp_reset(struct mpi3mr_ioc * mrioc,struct mpi3mr_drv_cmd * cmdptr)4538 static inline void mpi3mr_drv_cmd_comp_reset(struct mpi3mr_ioc *mrioc,
4539 struct mpi3mr_drv_cmd *cmdptr)
4540 {
4541 if (cmdptr->state & MPI3MR_CMD_PENDING) {
4542 cmdptr->state |= MPI3MR_CMD_RESET;
4543 cmdptr->state &= ~MPI3MR_CMD_PENDING;
4544 if (cmdptr->is_waiting) {
4545 complete(&cmdptr->done);
4546 cmdptr->is_waiting = 0;
4547 } else if (cmdptr->callback)
4548 cmdptr->callback(mrioc, cmdptr);
4549 }
4550 }
4551
4552 /**
4553 * mpi3mr_flush_drv_cmds - Flush internaldriver commands
4554 * @mrioc: Adapter instance reference
4555 *
4556 * Flush all internal driver commands post reset
4557 *
4558 * Return: Nothing.
4559 */
mpi3mr_flush_drv_cmds(struct mpi3mr_ioc * mrioc)4560 void mpi3mr_flush_drv_cmds(struct mpi3mr_ioc *mrioc)
4561 {
4562 struct mpi3mr_drv_cmd *cmdptr;
4563 u8 i;
4564
4565 cmdptr = &mrioc->init_cmds;
4566 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
4567
4568 cmdptr = &mrioc->cfg_cmds;
4569 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
4570
4571 cmdptr = &mrioc->bsg_cmds;
4572 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
4573 cmdptr = &mrioc->host_tm_cmds;
4574 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
4575
4576 for (i = 0; i < MPI3MR_NUM_DEVRMCMD; i++) {
4577 cmdptr = &mrioc->dev_rmhs_cmds[i];
4578 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
4579 }
4580
4581 for (i = 0; i < MPI3MR_NUM_EVTACKCMD; i++) {
4582 cmdptr = &mrioc->evtack_cmds[i];
4583 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
4584 }
4585
4586 cmdptr = &mrioc->pel_cmds;
4587 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
4588
4589 cmdptr = &mrioc->pel_abort_cmd;
4590 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
4591
4592 cmdptr = &mrioc->transport_cmds;
4593 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
4594 }
4595
4596 /**
4597 * mpi3mr_pel_wait_post - Issue PEL Wait
4598 * @mrioc: Adapter instance reference
4599 * @drv_cmd: Internal command tracker
4600 *
4601 * Issue PEL Wait MPI request through admin queue and return.
4602 *
4603 * Return: Nothing.
4604 */
mpi3mr_pel_wait_post(struct mpi3mr_ioc * mrioc,struct mpi3mr_drv_cmd * drv_cmd)4605 static void mpi3mr_pel_wait_post(struct mpi3mr_ioc *mrioc,
4606 struct mpi3mr_drv_cmd *drv_cmd)
4607 {
4608 struct mpi3_pel_req_action_wait pel_wait;
4609
4610 mrioc->pel_abort_requested = false;
4611
4612 memset(&pel_wait, 0, sizeof(pel_wait));
4613 drv_cmd->state = MPI3MR_CMD_PENDING;
4614 drv_cmd->is_waiting = 0;
4615 drv_cmd->callback = mpi3mr_pel_wait_complete;
4616 drv_cmd->ioc_status = 0;
4617 drv_cmd->ioc_loginfo = 0;
4618 pel_wait.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_PEL_WAIT);
4619 pel_wait.function = MPI3_FUNCTION_PERSISTENT_EVENT_LOG;
4620 pel_wait.action = MPI3_PEL_ACTION_WAIT;
4621 pel_wait.starting_sequence_number = cpu_to_le32(mrioc->pel_newest_seqnum);
4622 pel_wait.locale = cpu_to_le16(mrioc->pel_locale);
4623 pel_wait.class = cpu_to_le16(mrioc->pel_class);
4624 pel_wait.wait_time = MPI3_PEL_WAITTIME_INFINITE_WAIT;
4625 dprint_bsg_info(mrioc, "sending pel_wait seqnum(%d), class(%d), locale(0x%08x)\n",
4626 mrioc->pel_newest_seqnum, mrioc->pel_class, mrioc->pel_locale);
4627
4628 if (mpi3mr_admin_request_post(mrioc, &pel_wait, sizeof(pel_wait), 0)) {
4629 dprint_bsg_err(mrioc,
4630 "Issuing PELWait: Admin post failed\n");
4631 drv_cmd->state = MPI3MR_CMD_NOTUSED;
4632 drv_cmd->callback = NULL;
4633 drv_cmd->retry_count = 0;
4634 mrioc->pel_enabled = false;
4635 }
4636 }
4637
4638 /**
4639 * mpi3mr_pel_get_seqnum_post - Issue PEL Get Sequence number
4640 * @mrioc: Adapter instance reference
4641 * @drv_cmd: Internal command tracker
4642 *
4643 * Issue PEL get sequence number MPI request through admin queue
4644 * and return.
4645 *
4646 * Return: 0 on success, non-zero on failure.
4647 */
mpi3mr_pel_get_seqnum_post(struct mpi3mr_ioc * mrioc,struct mpi3mr_drv_cmd * drv_cmd)4648 int mpi3mr_pel_get_seqnum_post(struct mpi3mr_ioc *mrioc,
4649 struct mpi3mr_drv_cmd *drv_cmd)
4650 {
4651 struct mpi3_pel_req_action_get_sequence_numbers pel_getseq_req;
4652 u8 sgl_flags = MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST;
4653 int retval = 0;
4654
4655 memset(&pel_getseq_req, 0, sizeof(pel_getseq_req));
4656 mrioc->pel_cmds.state = MPI3MR_CMD_PENDING;
4657 mrioc->pel_cmds.is_waiting = 0;
4658 mrioc->pel_cmds.ioc_status = 0;
4659 mrioc->pel_cmds.ioc_loginfo = 0;
4660 mrioc->pel_cmds.callback = mpi3mr_pel_get_seqnum_complete;
4661 pel_getseq_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_PEL_WAIT);
4662 pel_getseq_req.function = MPI3_FUNCTION_PERSISTENT_EVENT_LOG;
4663 pel_getseq_req.action = MPI3_PEL_ACTION_GET_SEQNUM;
4664 mpi3mr_add_sg_single(&pel_getseq_req.sgl, sgl_flags,
4665 mrioc->pel_seqnum_sz, mrioc->pel_seqnum_dma);
4666
4667 retval = mpi3mr_admin_request_post(mrioc, &pel_getseq_req,
4668 sizeof(pel_getseq_req), 0);
4669 if (retval) {
4670 if (drv_cmd) {
4671 drv_cmd->state = MPI3MR_CMD_NOTUSED;
4672 drv_cmd->callback = NULL;
4673 drv_cmd->retry_count = 0;
4674 }
4675 mrioc->pel_enabled = false;
4676 }
4677
4678 return retval;
4679 }
4680
4681 /**
4682 * mpi3mr_pel_wait_complete - PELWait Completion callback
4683 * @mrioc: Adapter instance reference
4684 * @drv_cmd: Internal command tracker
4685 *
4686 * This is a callback handler for the PELWait request and
4687 * firmware completes a PELWait request when it is aborted or a
4688 * new PEL entry is available. This sends AEN to the application
4689 * and if the PELwait completion is not due to PELAbort then
4690 * this will send a request for new PEL Sequence number
4691 *
4692 * Return: Nothing.
4693 */
mpi3mr_pel_wait_complete(struct mpi3mr_ioc * mrioc,struct mpi3mr_drv_cmd * drv_cmd)4694 static void mpi3mr_pel_wait_complete(struct mpi3mr_ioc *mrioc,
4695 struct mpi3mr_drv_cmd *drv_cmd)
4696 {
4697 struct mpi3_pel_reply *pel_reply = NULL;
4698 u16 ioc_status, pe_log_status;
4699 bool do_retry = false;
4700
4701 if (drv_cmd->state & MPI3MR_CMD_RESET)
4702 goto cleanup_drv_cmd;
4703
4704 ioc_status = drv_cmd->ioc_status & MPI3_IOCSTATUS_STATUS_MASK;
4705 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
4706 ioc_err(mrioc, "%s: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
4707 __func__, ioc_status, drv_cmd->ioc_loginfo);
4708 dprint_bsg_err(mrioc,
4709 "pel_wait: failed with ioc_status(0x%04x), log_info(0x%08x)\n",
4710 ioc_status, drv_cmd->ioc_loginfo);
4711 do_retry = true;
4712 }
4713
4714 if (drv_cmd->state & MPI3MR_CMD_REPLY_VALID)
4715 pel_reply = (struct mpi3_pel_reply *)drv_cmd->reply;
4716
4717 if (!pel_reply) {
4718 dprint_bsg_err(mrioc,
4719 "pel_wait: failed due to no reply\n");
4720 goto out_failed;
4721 }
4722
4723 pe_log_status = le16_to_cpu(pel_reply->pe_log_status);
4724 if ((pe_log_status != MPI3_PEL_STATUS_SUCCESS) &&
4725 (pe_log_status != MPI3_PEL_STATUS_ABORTED)) {
4726 ioc_err(mrioc, "%s: Failed pe_log_status(0x%04x)\n",
4727 __func__, pe_log_status);
4728 dprint_bsg_err(mrioc,
4729 "pel_wait: failed due to pel_log_status(0x%04x)\n",
4730 pe_log_status);
4731 do_retry = true;
4732 }
4733
4734 if (do_retry) {
4735 if (drv_cmd->retry_count < MPI3MR_PEL_RETRY_COUNT) {
4736 drv_cmd->retry_count++;
4737 dprint_bsg_err(mrioc, "pel_wait: retrying(%d)\n",
4738 drv_cmd->retry_count);
4739 mpi3mr_pel_wait_post(mrioc, drv_cmd);
4740 return;
4741 }
4742 dprint_bsg_err(mrioc,
4743 "pel_wait: failed after all retries(%d)\n",
4744 drv_cmd->retry_count);
4745 goto out_failed;
4746 }
4747 atomic64_inc(&event_counter);
4748 if (!mrioc->pel_abort_requested) {
4749 mrioc->pel_cmds.retry_count = 0;
4750 mpi3mr_pel_get_seqnum_post(mrioc, &mrioc->pel_cmds);
4751 }
4752
4753 return;
4754 out_failed:
4755 mrioc->pel_enabled = false;
4756 cleanup_drv_cmd:
4757 drv_cmd->state = MPI3MR_CMD_NOTUSED;
4758 drv_cmd->callback = NULL;
4759 drv_cmd->retry_count = 0;
4760 }
4761
4762 /**
4763 * mpi3mr_pel_get_seqnum_complete - PELGetSeqNum Completion callback
4764 * @mrioc: Adapter instance reference
4765 * @drv_cmd: Internal command tracker
4766 *
4767 * This is a callback handler for the PEL get sequence number
4768 * request and a new PEL wait request will be issued to the
4769 * firmware from this
4770 *
4771 * Return: Nothing.
4772 */
mpi3mr_pel_get_seqnum_complete(struct mpi3mr_ioc * mrioc,struct mpi3mr_drv_cmd * drv_cmd)4773 void mpi3mr_pel_get_seqnum_complete(struct mpi3mr_ioc *mrioc,
4774 struct mpi3mr_drv_cmd *drv_cmd)
4775 {
4776 struct mpi3_pel_reply *pel_reply = NULL;
4777 struct mpi3_pel_seq *pel_seqnum_virt;
4778 u16 ioc_status;
4779 bool do_retry = false;
4780
4781 pel_seqnum_virt = (struct mpi3_pel_seq *)mrioc->pel_seqnum_virt;
4782
4783 if (drv_cmd->state & MPI3MR_CMD_RESET)
4784 goto cleanup_drv_cmd;
4785
4786 ioc_status = drv_cmd->ioc_status & MPI3_IOCSTATUS_STATUS_MASK;
4787 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
4788 dprint_bsg_err(mrioc,
4789 "pel_get_seqnum: failed with ioc_status(0x%04x), log_info(0x%08x)\n",
4790 ioc_status, drv_cmd->ioc_loginfo);
4791 do_retry = true;
4792 }
4793
4794 if (drv_cmd->state & MPI3MR_CMD_REPLY_VALID)
4795 pel_reply = (struct mpi3_pel_reply *)drv_cmd->reply;
4796 if (!pel_reply) {
4797 dprint_bsg_err(mrioc,
4798 "pel_get_seqnum: failed due to no reply\n");
4799 goto out_failed;
4800 }
4801
4802 if (le16_to_cpu(pel_reply->pe_log_status) != MPI3_PEL_STATUS_SUCCESS) {
4803 dprint_bsg_err(mrioc,
4804 "pel_get_seqnum: failed due to pel_log_status(0x%04x)\n",
4805 le16_to_cpu(pel_reply->pe_log_status));
4806 do_retry = true;
4807 }
4808
4809 if (do_retry) {
4810 if (drv_cmd->retry_count < MPI3MR_PEL_RETRY_COUNT) {
4811 drv_cmd->retry_count++;
4812 dprint_bsg_err(mrioc,
4813 "pel_get_seqnum: retrying(%d)\n",
4814 drv_cmd->retry_count);
4815 mpi3mr_pel_get_seqnum_post(mrioc, drv_cmd);
4816 return;
4817 }
4818
4819 dprint_bsg_err(mrioc,
4820 "pel_get_seqnum: failed after all retries(%d)\n",
4821 drv_cmd->retry_count);
4822 goto out_failed;
4823 }
4824 mrioc->pel_newest_seqnum = le32_to_cpu(pel_seqnum_virt->newest) + 1;
4825 drv_cmd->retry_count = 0;
4826 mpi3mr_pel_wait_post(mrioc, drv_cmd);
4827
4828 return;
4829 out_failed:
4830 mrioc->pel_enabled = false;
4831 cleanup_drv_cmd:
4832 drv_cmd->state = MPI3MR_CMD_NOTUSED;
4833 drv_cmd->callback = NULL;
4834 drv_cmd->retry_count = 0;
4835 }
4836
4837 /**
4838 * mpi3mr_soft_reset_handler - Reset the controller
4839 * @mrioc: Adapter instance reference
4840 * @reset_reason: Reset reason code
4841 * @snapdump: Flag to generate snapdump in firmware or not
4842 *
4843 * This is an handler for recovering controller by issuing soft
4844 * reset are diag fault reset. This is a blocking function and
4845 * when one reset is executed if any other resets they will be
4846 * blocked. All BSG requests will be blocked during the reset. If
4847 * controller reset is successful then the controller will be
4848 * reinitalized, otherwise the controller will be marked as not
4849 * recoverable
4850 *
4851 * In snapdump bit is set, the controller is issued with diag
4852 * fault reset so that the firmware can create a snap dump and
4853 * post that the firmware will result in F000 fault and the
4854 * driver will issue soft reset to recover from that.
4855 *
4856 * Return: 0 on success, non-zero on failure.
4857 */
mpi3mr_soft_reset_handler(struct mpi3mr_ioc * mrioc,u32 reset_reason,u8 snapdump)4858 int mpi3mr_soft_reset_handler(struct mpi3mr_ioc *mrioc,
4859 u32 reset_reason, u8 snapdump)
4860 {
4861 int retval = 0, i;
4862 unsigned long flags;
4863 u32 host_diagnostic, timeout = MPI3_SYSIF_DIAG_SAVE_TIMEOUT * 10;
4864
4865 /* Block the reset handler until diag save in progress*/
4866 dprint_reset(mrioc,
4867 "soft_reset_handler: check and block on diagsave_timeout(%d)\n",
4868 mrioc->diagsave_timeout);
4869 while (mrioc->diagsave_timeout)
4870 ssleep(1);
4871 /*
4872 * Block new resets until the currently executing one is finished and
4873 * return the status of the existing reset for all blocked resets
4874 */
4875 dprint_reset(mrioc, "soft_reset_handler: acquiring reset_mutex\n");
4876 if (!mutex_trylock(&mrioc->reset_mutex)) {
4877 ioc_info(mrioc,
4878 "controller reset triggered by %s is blocked due to another reset in progress\n",
4879 mpi3mr_reset_rc_name(reset_reason));
4880 do {
4881 ssleep(1);
4882 } while (mrioc->reset_in_progress == 1);
4883 ioc_info(mrioc,
4884 "returning previous reset result(%d) for the reset triggered by %s\n",
4885 mrioc->prev_reset_result,
4886 mpi3mr_reset_rc_name(reset_reason));
4887 return mrioc->prev_reset_result;
4888 }
4889 ioc_info(mrioc, "controller reset is triggered by %s\n",
4890 mpi3mr_reset_rc_name(reset_reason));
4891
4892 mrioc->device_refresh_on = 0;
4893 mrioc->reset_in_progress = 1;
4894 mrioc->stop_bsgs = 1;
4895 mrioc->prev_reset_result = -1;
4896
4897 if ((!snapdump) && (reset_reason != MPI3MR_RESET_FROM_FAULT_WATCH) &&
4898 (reset_reason != MPI3MR_RESET_FROM_FIRMWARE) &&
4899 (reset_reason != MPI3MR_RESET_FROM_CIACTIV_FAULT)) {
4900 for (i = 0; i < MPI3_EVENT_NOTIFY_EVENTMASK_WORDS; i++)
4901 mrioc->event_masks[i] = -1;
4902
4903 dprint_reset(mrioc, "soft_reset_handler: masking events\n");
4904 mpi3mr_issue_event_notification(mrioc);
4905 }
4906
4907 mpi3mr_wait_for_host_io(mrioc, MPI3MR_RESET_HOST_IOWAIT_TIMEOUT);
4908
4909 mpi3mr_ioc_disable_intr(mrioc);
4910
4911 if (snapdump) {
4912 mpi3mr_set_diagsave(mrioc);
4913 retval = mpi3mr_issue_reset(mrioc,
4914 MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT, reset_reason);
4915 if (!retval) {
4916 do {
4917 host_diagnostic =
4918 readl(&mrioc->sysif_regs->host_diagnostic);
4919 if (!(host_diagnostic &
4920 MPI3_SYSIF_HOST_DIAG_SAVE_IN_PROGRESS))
4921 break;
4922 msleep(100);
4923 } while (--timeout);
4924 }
4925 }
4926
4927 retval = mpi3mr_issue_reset(mrioc,
4928 MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET, reset_reason);
4929 if (retval) {
4930 ioc_err(mrioc, "Failed to issue soft reset to the ioc\n");
4931 goto out;
4932 }
4933 if (mrioc->num_io_throttle_group !=
4934 mrioc->facts.max_io_throttle_group) {
4935 ioc_err(mrioc,
4936 "max io throttle group doesn't match old(%d), new(%d)\n",
4937 mrioc->num_io_throttle_group,
4938 mrioc->facts.max_io_throttle_group);
4939 retval = -EPERM;
4940 goto out;
4941 }
4942
4943 mpi3mr_flush_delayed_cmd_lists(mrioc);
4944 mpi3mr_flush_drv_cmds(mrioc);
4945 bitmap_clear(mrioc->devrem_bitmap, 0, MPI3MR_NUM_DEVRMCMD);
4946 bitmap_clear(mrioc->removepend_bitmap, 0,
4947 mrioc->dev_handle_bitmap_bits);
4948 bitmap_clear(mrioc->evtack_cmds_bitmap, 0, MPI3MR_NUM_EVTACKCMD);
4949 mpi3mr_flush_host_io(mrioc);
4950 mpi3mr_cleanup_fwevt_list(mrioc);
4951 mpi3mr_invalidate_devhandles(mrioc);
4952 mpi3mr_free_enclosure_list(mrioc);
4953
4954 if (mrioc->prepare_for_reset) {
4955 mrioc->prepare_for_reset = 0;
4956 mrioc->prepare_for_reset_timeout_counter = 0;
4957 }
4958 mpi3mr_memset_buffers(mrioc);
4959 retval = mpi3mr_reinit_ioc(mrioc, 0);
4960 if (retval) {
4961 pr_err(IOCNAME "reinit after soft reset failed: reason %d\n",
4962 mrioc->name, reset_reason);
4963 goto out;
4964 }
4965 ssleep(MPI3MR_RESET_TOPOLOGY_SETTLE_TIME);
4966
4967 out:
4968 if (!retval) {
4969 mrioc->diagsave_timeout = 0;
4970 mrioc->reset_in_progress = 0;
4971 mrioc->pel_abort_requested = 0;
4972 if (mrioc->pel_enabled) {
4973 mrioc->pel_cmds.retry_count = 0;
4974 mpi3mr_pel_wait_post(mrioc, &mrioc->pel_cmds);
4975 }
4976
4977 mrioc->device_refresh_on = 0;
4978
4979 mrioc->ts_update_counter = 0;
4980 spin_lock_irqsave(&mrioc->watchdog_lock, flags);
4981 if (mrioc->watchdog_work_q)
4982 queue_delayed_work(mrioc->watchdog_work_q,
4983 &mrioc->watchdog_work,
4984 msecs_to_jiffies(MPI3MR_WATCHDOG_INTERVAL));
4985 spin_unlock_irqrestore(&mrioc->watchdog_lock, flags);
4986 mrioc->stop_bsgs = 0;
4987 if (mrioc->pel_enabled)
4988 atomic64_inc(&event_counter);
4989 } else {
4990 mpi3mr_issue_reset(mrioc,
4991 MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT, reset_reason);
4992 mrioc->device_refresh_on = 0;
4993 mrioc->unrecoverable = 1;
4994 mrioc->reset_in_progress = 0;
4995 retval = -1;
4996 mpi3mr_flush_cmds_for_unrecovered_controller(mrioc);
4997 }
4998 mrioc->prev_reset_result = retval;
4999 mutex_unlock(&mrioc->reset_mutex);
5000 ioc_info(mrioc, "controller reset is %s\n",
5001 ((retval == 0) ? "successful" : "failed"));
5002 return retval;
5003 }
5004
5005
5006 /**
5007 * mpi3mr_free_config_dma_memory - free memory for config page
5008 * @mrioc: Adapter instance reference
5009 * @mem_desc: memory descriptor structure
5010 *
5011 * Check whether the size of the buffer specified by the memory
5012 * descriptor is greater than the default page size if so then
5013 * free the memory pointed by the descriptor.
5014 *
5015 * Return: Nothing.
5016 */
mpi3mr_free_config_dma_memory(struct mpi3mr_ioc * mrioc,struct dma_memory_desc * mem_desc)5017 static void mpi3mr_free_config_dma_memory(struct mpi3mr_ioc *mrioc,
5018 struct dma_memory_desc *mem_desc)
5019 {
5020 if ((mem_desc->size > mrioc->cfg_page_sz) && mem_desc->addr) {
5021 dma_free_coherent(&mrioc->pdev->dev, mem_desc->size,
5022 mem_desc->addr, mem_desc->dma_addr);
5023 mem_desc->addr = NULL;
5024 }
5025 }
5026
5027 /**
5028 * mpi3mr_alloc_config_dma_memory - Alloc memory for config page
5029 * @mrioc: Adapter instance reference
5030 * @mem_desc: Memory descriptor to hold dma memory info
5031 *
5032 * This function allocates new dmaable memory or provides the
5033 * default config page dmaable memory based on the memory size
5034 * described by the descriptor.
5035 *
5036 * Return: 0 on success, non-zero on failure.
5037 */
mpi3mr_alloc_config_dma_memory(struct mpi3mr_ioc * mrioc,struct dma_memory_desc * mem_desc)5038 static int mpi3mr_alloc_config_dma_memory(struct mpi3mr_ioc *mrioc,
5039 struct dma_memory_desc *mem_desc)
5040 {
5041 if (mem_desc->size > mrioc->cfg_page_sz) {
5042 mem_desc->addr = dma_alloc_coherent(&mrioc->pdev->dev,
5043 mem_desc->size, &mem_desc->dma_addr, GFP_KERNEL);
5044 if (!mem_desc->addr)
5045 return -ENOMEM;
5046 } else {
5047 mem_desc->addr = mrioc->cfg_page;
5048 mem_desc->dma_addr = mrioc->cfg_page_dma;
5049 memset(mem_desc->addr, 0, mrioc->cfg_page_sz);
5050 }
5051 return 0;
5052 }
5053
5054 /**
5055 * mpi3mr_post_cfg_req - Issue config requests and wait
5056 * @mrioc: Adapter instance reference
5057 * @cfg_req: Configuration request
5058 * @timeout: Timeout in seconds
5059 * @ioc_status: Pointer to return ioc status
5060 *
5061 * A generic function for posting MPI3 configuration request to
5062 * the firmware. This blocks for the completion of request for
5063 * timeout seconds and if the request times out this function
5064 * faults the controller with proper reason code.
5065 *
5066 * On successful completion of the request this function returns
5067 * appropriate ioc status from the firmware back to the caller.
5068 *
5069 * Return: 0 on success, non-zero on failure.
5070 */
mpi3mr_post_cfg_req(struct mpi3mr_ioc * mrioc,struct mpi3_config_request * cfg_req,int timeout,u16 * ioc_status)5071 static int mpi3mr_post_cfg_req(struct mpi3mr_ioc *mrioc,
5072 struct mpi3_config_request *cfg_req, int timeout, u16 *ioc_status)
5073 {
5074 int retval = 0;
5075
5076 mutex_lock(&mrioc->cfg_cmds.mutex);
5077 if (mrioc->cfg_cmds.state & MPI3MR_CMD_PENDING) {
5078 retval = -1;
5079 ioc_err(mrioc, "sending config request failed due to command in use\n");
5080 mutex_unlock(&mrioc->cfg_cmds.mutex);
5081 goto out;
5082 }
5083 mrioc->cfg_cmds.state = MPI3MR_CMD_PENDING;
5084 mrioc->cfg_cmds.is_waiting = 1;
5085 mrioc->cfg_cmds.callback = NULL;
5086 mrioc->cfg_cmds.ioc_status = 0;
5087 mrioc->cfg_cmds.ioc_loginfo = 0;
5088
5089 cfg_req->host_tag = cpu_to_le16(MPI3MR_HOSTTAG_CFG_CMDS);
5090 cfg_req->function = MPI3_FUNCTION_CONFIG;
5091
5092 init_completion(&mrioc->cfg_cmds.done);
5093 dprint_cfg_info(mrioc, "posting config request\n");
5094 if (mrioc->logging_level & MPI3_DEBUG_CFG_INFO)
5095 dprint_dump(cfg_req, sizeof(struct mpi3_config_request),
5096 "mpi3_cfg_req");
5097 retval = mpi3mr_admin_request_post(mrioc, cfg_req, sizeof(*cfg_req), 1);
5098 if (retval) {
5099 ioc_err(mrioc, "posting config request failed\n");
5100 goto out_unlock;
5101 }
5102 wait_for_completion_timeout(&mrioc->cfg_cmds.done, (timeout * HZ));
5103 if (!(mrioc->cfg_cmds.state & MPI3MR_CMD_COMPLETE)) {
5104 mpi3mr_check_rh_fault_ioc(mrioc,
5105 MPI3MR_RESET_FROM_CFG_REQ_TIMEOUT);
5106 ioc_err(mrioc, "config request timed out\n");
5107 retval = -1;
5108 goto out_unlock;
5109 }
5110 *ioc_status = mrioc->cfg_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK;
5111 if ((*ioc_status) != MPI3_IOCSTATUS_SUCCESS)
5112 dprint_cfg_err(mrioc,
5113 "cfg_page request returned with ioc_status(0x%04x), log_info(0x%08x)\n",
5114 *ioc_status, mrioc->cfg_cmds.ioc_loginfo);
5115
5116 out_unlock:
5117 mrioc->cfg_cmds.state = MPI3MR_CMD_NOTUSED;
5118 mutex_unlock(&mrioc->cfg_cmds.mutex);
5119
5120 out:
5121 return retval;
5122 }
5123
5124 /**
5125 * mpi3mr_process_cfg_req - config page request processor
5126 * @mrioc: Adapter instance reference
5127 * @cfg_req: Configuration request
5128 * @cfg_hdr: Configuration page header
5129 * @timeout: Timeout in seconds
5130 * @ioc_status: Pointer to return ioc status
5131 * @cfg_buf: Memory pointer to copy config page or header
5132 * @cfg_buf_sz: Size of the memory to get config page or header
5133 *
5134 * This is handler for config page read, write and config page
5135 * header read operations.
5136 *
5137 * This function expects the cfg_req to be populated with page
5138 * type, page number, action for the header read and with page
5139 * address for all other operations.
5140 *
5141 * The cfg_hdr can be passed as null for reading required header
5142 * details for read/write pages the cfg_hdr should point valid
5143 * configuration page header.
5144 *
5145 * This allocates dmaable memory based on the size of the config
5146 * buffer and set the SGE of the cfg_req.
5147 *
5148 * For write actions, the config page data has to be passed in
5149 * the cfg_buf and size of the data has to be mentioned in the
5150 * cfg_buf_sz.
5151 *
5152 * For read/header actions, on successful completion of the
5153 * request with successful ioc_status the data will be copied
5154 * into the cfg_buf limited to a minimum of actual page size and
5155 * cfg_buf_sz
5156 *
5157 *
5158 * Return: 0 on success, non-zero on failure.
5159 */
mpi3mr_process_cfg_req(struct mpi3mr_ioc * mrioc,struct mpi3_config_request * cfg_req,struct mpi3_config_page_header * cfg_hdr,int timeout,u16 * ioc_status,void * cfg_buf,u32 cfg_buf_sz)5160 static int mpi3mr_process_cfg_req(struct mpi3mr_ioc *mrioc,
5161 struct mpi3_config_request *cfg_req,
5162 struct mpi3_config_page_header *cfg_hdr, int timeout, u16 *ioc_status,
5163 void *cfg_buf, u32 cfg_buf_sz)
5164 {
5165 struct dma_memory_desc mem_desc;
5166 int retval = -1;
5167 u8 invalid_action = 0;
5168 u8 sgl_flags = MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST;
5169
5170 memset(&mem_desc, 0, sizeof(struct dma_memory_desc));
5171
5172 if (cfg_req->action == MPI3_CONFIG_ACTION_PAGE_HEADER)
5173 mem_desc.size = sizeof(struct mpi3_config_page_header);
5174 else {
5175 if (!cfg_hdr) {
5176 ioc_err(mrioc, "null config header passed for config action(%d), page_type(0x%02x), page_num(%d)\n",
5177 cfg_req->action, cfg_req->page_type,
5178 cfg_req->page_number);
5179 goto out;
5180 }
5181 switch (cfg_hdr->page_attribute & MPI3_CONFIG_PAGEATTR_MASK) {
5182 case MPI3_CONFIG_PAGEATTR_READ_ONLY:
5183 if (cfg_req->action
5184 != MPI3_CONFIG_ACTION_READ_CURRENT)
5185 invalid_action = 1;
5186 break;
5187 case MPI3_CONFIG_PAGEATTR_CHANGEABLE:
5188 if ((cfg_req->action ==
5189 MPI3_CONFIG_ACTION_READ_PERSISTENT) ||
5190 (cfg_req->action ==
5191 MPI3_CONFIG_ACTION_WRITE_PERSISTENT))
5192 invalid_action = 1;
5193 break;
5194 case MPI3_CONFIG_PAGEATTR_PERSISTENT:
5195 default:
5196 break;
5197 }
5198 if (invalid_action) {
5199 ioc_err(mrioc,
5200 "config action(%d) is not allowed for page_type(0x%02x), page_num(%d) with page_attribute(0x%02x)\n",
5201 cfg_req->action, cfg_req->page_type,
5202 cfg_req->page_number, cfg_hdr->page_attribute);
5203 goto out;
5204 }
5205 mem_desc.size = le16_to_cpu(cfg_hdr->page_length) * 4;
5206 cfg_req->page_length = cfg_hdr->page_length;
5207 cfg_req->page_version = cfg_hdr->page_version;
5208 }
5209 if (mpi3mr_alloc_config_dma_memory(mrioc, &mem_desc))
5210 goto out;
5211
5212 mpi3mr_add_sg_single(&cfg_req->sgl, sgl_flags, mem_desc.size,
5213 mem_desc.dma_addr);
5214
5215 if ((cfg_req->action == MPI3_CONFIG_ACTION_WRITE_PERSISTENT) ||
5216 (cfg_req->action == MPI3_CONFIG_ACTION_WRITE_CURRENT)) {
5217 memcpy(mem_desc.addr, cfg_buf, min_t(u16, mem_desc.size,
5218 cfg_buf_sz));
5219 dprint_cfg_info(mrioc, "config buffer to be written\n");
5220 if (mrioc->logging_level & MPI3_DEBUG_CFG_INFO)
5221 dprint_dump(mem_desc.addr, mem_desc.size, "cfg_buf");
5222 }
5223
5224 if (mpi3mr_post_cfg_req(mrioc, cfg_req, timeout, ioc_status))
5225 goto out;
5226
5227 retval = 0;
5228 if ((*ioc_status == MPI3_IOCSTATUS_SUCCESS) &&
5229 (cfg_req->action != MPI3_CONFIG_ACTION_WRITE_PERSISTENT) &&
5230 (cfg_req->action != MPI3_CONFIG_ACTION_WRITE_CURRENT)) {
5231 memcpy(cfg_buf, mem_desc.addr, min_t(u16, mem_desc.size,
5232 cfg_buf_sz));
5233 dprint_cfg_info(mrioc, "config buffer read\n");
5234 if (mrioc->logging_level & MPI3_DEBUG_CFG_INFO)
5235 dprint_dump(mem_desc.addr, mem_desc.size, "cfg_buf");
5236 }
5237
5238 out:
5239 mpi3mr_free_config_dma_memory(mrioc, &mem_desc);
5240 return retval;
5241 }
5242
5243 /**
5244 * mpi3mr_cfg_get_dev_pg0 - Read current device page0
5245 * @mrioc: Adapter instance reference
5246 * @ioc_status: Pointer to return ioc status
5247 * @dev_pg0: Pointer to return device page 0
5248 * @pg_sz: Size of the memory allocated to the page pointer
5249 * @form: The form to be used for addressing the page
5250 * @form_spec: Form specific information like device handle
5251 *
5252 * This is handler for config page read for a specific device
5253 * page0. The ioc_status has the controller returned ioc_status.
5254 * This routine doesn't check ioc_status to decide whether the
5255 * page read is success or not and it is the callers
5256 * responsibility.
5257 *
5258 * Return: 0 on success, non-zero on failure.
5259 */
mpi3mr_cfg_get_dev_pg0(struct mpi3mr_ioc * mrioc,u16 * ioc_status,struct mpi3_device_page0 * dev_pg0,u16 pg_sz,u32 form,u32 form_spec)5260 int mpi3mr_cfg_get_dev_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status,
5261 struct mpi3_device_page0 *dev_pg0, u16 pg_sz, u32 form, u32 form_spec)
5262 {
5263 struct mpi3_config_page_header cfg_hdr;
5264 struct mpi3_config_request cfg_req;
5265 u32 page_address;
5266
5267 memset(dev_pg0, 0, pg_sz);
5268 memset(&cfg_hdr, 0, sizeof(cfg_hdr));
5269 memset(&cfg_req, 0, sizeof(cfg_req));
5270
5271 cfg_req.function = MPI3_FUNCTION_CONFIG;
5272 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
5273 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_DEVICE;
5274 cfg_req.page_number = 0;
5275 cfg_req.page_address = 0;
5276
5277 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
5278 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
5279 ioc_err(mrioc, "device page0 header read failed\n");
5280 goto out_failed;
5281 }
5282 if (*ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5283 ioc_err(mrioc, "device page0 header read failed with ioc_status(0x%04x)\n",
5284 *ioc_status);
5285 goto out_failed;
5286 }
5287 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
5288 page_address = ((form & MPI3_DEVICE_PGAD_FORM_MASK) |
5289 (form_spec & MPI3_DEVICE_PGAD_HANDLE_MASK));
5290 cfg_req.page_address = cpu_to_le32(page_address);
5291 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
5292 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, dev_pg0, pg_sz)) {
5293 ioc_err(mrioc, "device page0 read failed\n");
5294 goto out_failed;
5295 }
5296 return 0;
5297 out_failed:
5298 return -1;
5299 }
5300
5301
5302 /**
5303 * mpi3mr_cfg_get_sas_phy_pg0 - Read current SAS Phy page0
5304 * @mrioc: Adapter instance reference
5305 * @ioc_status: Pointer to return ioc status
5306 * @phy_pg0: Pointer to return SAS Phy page 0
5307 * @pg_sz: Size of the memory allocated to the page pointer
5308 * @form: The form to be used for addressing the page
5309 * @form_spec: Form specific information like phy number
5310 *
5311 * This is handler for config page read for a specific SAS Phy
5312 * page0. The ioc_status has the controller returned ioc_status.
5313 * This routine doesn't check ioc_status to decide whether the
5314 * page read is success or not and it is the callers
5315 * responsibility.
5316 *
5317 * Return: 0 on success, non-zero on failure.
5318 */
mpi3mr_cfg_get_sas_phy_pg0(struct mpi3mr_ioc * mrioc,u16 * ioc_status,struct mpi3_sas_phy_page0 * phy_pg0,u16 pg_sz,u32 form,u32 form_spec)5319 int mpi3mr_cfg_get_sas_phy_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status,
5320 struct mpi3_sas_phy_page0 *phy_pg0, u16 pg_sz, u32 form,
5321 u32 form_spec)
5322 {
5323 struct mpi3_config_page_header cfg_hdr;
5324 struct mpi3_config_request cfg_req;
5325 u32 page_address;
5326
5327 memset(phy_pg0, 0, pg_sz);
5328 memset(&cfg_hdr, 0, sizeof(cfg_hdr));
5329 memset(&cfg_req, 0, sizeof(cfg_req));
5330
5331 cfg_req.function = MPI3_FUNCTION_CONFIG;
5332 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
5333 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_PHY;
5334 cfg_req.page_number = 0;
5335 cfg_req.page_address = 0;
5336
5337 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
5338 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
5339 ioc_err(mrioc, "sas phy page0 header read failed\n");
5340 goto out_failed;
5341 }
5342 if (*ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5343 ioc_err(mrioc, "sas phy page0 header read failed with ioc_status(0x%04x)\n",
5344 *ioc_status);
5345 goto out_failed;
5346 }
5347 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
5348 page_address = ((form & MPI3_SAS_PHY_PGAD_FORM_MASK) |
5349 (form_spec & MPI3_SAS_PHY_PGAD_PHY_NUMBER_MASK));
5350 cfg_req.page_address = cpu_to_le32(page_address);
5351 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
5352 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, phy_pg0, pg_sz)) {
5353 ioc_err(mrioc, "sas phy page0 read failed\n");
5354 goto out_failed;
5355 }
5356 return 0;
5357 out_failed:
5358 return -1;
5359 }
5360
5361 /**
5362 * mpi3mr_cfg_get_sas_phy_pg1 - Read current SAS Phy page1
5363 * @mrioc: Adapter instance reference
5364 * @ioc_status: Pointer to return ioc status
5365 * @phy_pg1: Pointer to return SAS Phy page 1
5366 * @pg_sz: Size of the memory allocated to the page pointer
5367 * @form: The form to be used for addressing the page
5368 * @form_spec: Form specific information like phy number
5369 *
5370 * This is handler for config page read for a specific SAS Phy
5371 * page1. The ioc_status has the controller returned ioc_status.
5372 * This routine doesn't check ioc_status to decide whether the
5373 * page read is success or not and it is the callers
5374 * responsibility.
5375 *
5376 * Return: 0 on success, non-zero on failure.
5377 */
mpi3mr_cfg_get_sas_phy_pg1(struct mpi3mr_ioc * mrioc,u16 * ioc_status,struct mpi3_sas_phy_page1 * phy_pg1,u16 pg_sz,u32 form,u32 form_spec)5378 int mpi3mr_cfg_get_sas_phy_pg1(struct mpi3mr_ioc *mrioc, u16 *ioc_status,
5379 struct mpi3_sas_phy_page1 *phy_pg1, u16 pg_sz, u32 form,
5380 u32 form_spec)
5381 {
5382 struct mpi3_config_page_header cfg_hdr;
5383 struct mpi3_config_request cfg_req;
5384 u32 page_address;
5385
5386 memset(phy_pg1, 0, pg_sz);
5387 memset(&cfg_hdr, 0, sizeof(cfg_hdr));
5388 memset(&cfg_req, 0, sizeof(cfg_req));
5389
5390 cfg_req.function = MPI3_FUNCTION_CONFIG;
5391 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
5392 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_PHY;
5393 cfg_req.page_number = 1;
5394 cfg_req.page_address = 0;
5395
5396 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
5397 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
5398 ioc_err(mrioc, "sas phy page1 header read failed\n");
5399 goto out_failed;
5400 }
5401 if (*ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5402 ioc_err(mrioc, "sas phy page1 header read failed with ioc_status(0x%04x)\n",
5403 *ioc_status);
5404 goto out_failed;
5405 }
5406 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
5407 page_address = ((form & MPI3_SAS_PHY_PGAD_FORM_MASK) |
5408 (form_spec & MPI3_SAS_PHY_PGAD_PHY_NUMBER_MASK));
5409 cfg_req.page_address = cpu_to_le32(page_address);
5410 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
5411 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, phy_pg1, pg_sz)) {
5412 ioc_err(mrioc, "sas phy page1 read failed\n");
5413 goto out_failed;
5414 }
5415 return 0;
5416 out_failed:
5417 return -1;
5418 }
5419
5420
5421 /**
5422 * mpi3mr_cfg_get_sas_exp_pg0 - Read current SAS Expander page0
5423 * @mrioc: Adapter instance reference
5424 * @ioc_status: Pointer to return ioc status
5425 * @exp_pg0: Pointer to return SAS Expander page 0
5426 * @pg_sz: Size of the memory allocated to the page pointer
5427 * @form: The form to be used for addressing the page
5428 * @form_spec: Form specific information like device handle
5429 *
5430 * This is handler for config page read for a specific SAS
5431 * Expander page0. The ioc_status has the controller returned
5432 * ioc_status. This routine doesn't check ioc_status to decide
5433 * whether the page read is success or not and it is the callers
5434 * responsibility.
5435 *
5436 * Return: 0 on success, non-zero on failure.
5437 */
mpi3mr_cfg_get_sas_exp_pg0(struct mpi3mr_ioc * mrioc,u16 * ioc_status,struct mpi3_sas_expander_page0 * exp_pg0,u16 pg_sz,u32 form,u32 form_spec)5438 int mpi3mr_cfg_get_sas_exp_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status,
5439 struct mpi3_sas_expander_page0 *exp_pg0, u16 pg_sz, u32 form,
5440 u32 form_spec)
5441 {
5442 struct mpi3_config_page_header cfg_hdr;
5443 struct mpi3_config_request cfg_req;
5444 u32 page_address;
5445
5446 memset(exp_pg0, 0, pg_sz);
5447 memset(&cfg_hdr, 0, sizeof(cfg_hdr));
5448 memset(&cfg_req, 0, sizeof(cfg_req));
5449
5450 cfg_req.function = MPI3_FUNCTION_CONFIG;
5451 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
5452 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_EXPANDER;
5453 cfg_req.page_number = 0;
5454 cfg_req.page_address = 0;
5455
5456 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
5457 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
5458 ioc_err(mrioc, "expander page0 header read failed\n");
5459 goto out_failed;
5460 }
5461 if (*ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5462 ioc_err(mrioc, "expander page0 header read failed with ioc_status(0x%04x)\n",
5463 *ioc_status);
5464 goto out_failed;
5465 }
5466 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
5467 page_address = ((form & MPI3_SAS_EXPAND_PGAD_FORM_MASK) |
5468 (form_spec & (MPI3_SAS_EXPAND_PGAD_PHYNUM_MASK |
5469 MPI3_SAS_EXPAND_PGAD_HANDLE_MASK)));
5470 cfg_req.page_address = cpu_to_le32(page_address);
5471 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
5472 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, exp_pg0, pg_sz)) {
5473 ioc_err(mrioc, "expander page0 read failed\n");
5474 goto out_failed;
5475 }
5476 return 0;
5477 out_failed:
5478 return -1;
5479 }
5480
5481 /**
5482 * mpi3mr_cfg_get_sas_exp_pg1 - Read current SAS Expander page1
5483 * @mrioc: Adapter instance reference
5484 * @ioc_status: Pointer to return ioc status
5485 * @exp_pg1: Pointer to return SAS Expander page 1
5486 * @pg_sz: Size of the memory allocated to the page pointer
5487 * @form: The form to be used for addressing the page
5488 * @form_spec: Form specific information like phy number
5489 *
5490 * This is handler for config page read for a specific SAS
5491 * Expander page1. The ioc_status has the controller returned
5492 * ioc_status. This routine doesn't check ioc_status to decide
5493 * whether the page read is success or not and it is the callers
5494 * responsibility.
5495 *
5496 * Return: 0 on success, non-zero on failure.
5497 */
mpi3mr_cfg_get_sas_exp_pg1(struct mpi3mr_ioc * mrioc,u16 * ioc_status,struct mpi3_sas_expander_page1 * exp_pg1,u16 pg_sz,u32 form,u32 form_spec)5498 int mpi3mr_cfg_get_sas_exp_pg1(struct mpi3mr_ioc *mrioc, u16 *ioc_status,
5499 struct mpi3_sas_expander_page1 *exp_pg1, u16 pg_sz, u32 form,
5500 u32 form_spec)
5501 {
5502 struct mpi3_config_page_header cfg_hdr;
5503 struct mpi3_config_request cfg_req;
5504 u32 page_address;
5505
5506 memset(exp_pg1, 0, pg_sz);
5507 memset(&cfg_hdr, 0, sizeof(cfg_hdr));
5508 memset(&cfg_req, 0, sizeof(cfg_req));
5509
5510 cfg_req.function = MPI3_FUNCTION_CONFIG;
5511 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
5512 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_EXPANDER;
5513 cfg_req.page_number = 1;
5514 cfg_req.page_address = 0;
5515
5516 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
5517 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
5518 ioc_err(mrioc, "expander page1 header read failed\n");
5519 goto out_failed;
5520 }
5521 if (*ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5522 ioc_err(mrioc, "expander page1 header read failed with ioc_status(0x%04x)\n",
5523 *ioc_status);
5524 goto out_failed;
5525 }
5526 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
5527 page_address = ((form & MPI3_SAS_EXPAND_PGAD_FORM_MASK) |
5528 (form_spec & (MPI3_SAS_EXPAND_PGAD_PHYNUM_MASK |
5529 MPI3_SAS_EXPAND_PGAD_HANDLE_MASK)));
5530 cfg_req.page_address = cpu_to_le32(page_address);
5531 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
5532 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, exp_pg1, pg_sz)) {
5533 ioc_err(mrioc, "expander page1 read failed\n");
5534 goto out_failed;
5535 }
5536 return 0;
5537 out_failed:
5538 return -1;
5539 }
5540
5541 /**
5542 * mpi3mr_cfg_get_enclosure_pg0 - Read current Enclosure page0
5543 * @mrioc: Adapter instance reference
5544 * @ioc_status: Pointer to return ioc status
5545 * @encl_pg0: Pointer to return Enclosure page 0
5546 * @pg_sz: Size of the memory allocated to the page pointer
5547 * @form: The form to be used for addressing the page
5548 * @form_spec: Form specific information like device handle
5549 *
5550 * This is handler for config page read for a specific Enclosure
5551 * page0. The ioc_status has the controller returned ioc_status.
5552 * This routine doesn't check ioc_status to decide whether the
5553 * page read is success or not and it is the callers
5554 * responsibility.
5555 *
5556 * Return: 0 on success, non-zero on failure.
5557 */
mpi3mr_cfg_get_enclosure_pg0(struct mpi3mr_ioc * mrioc,u16 * ioc_status,struct mpi3_enclosure_page0 * encl_pg0,u16 pg_sz,u32 form,u32 form_spec)5558 int mpi3mr_cfg_get_enclosure_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status,
5559 struct mpi3_enclosure_page0 *encl_pg0, u16 pg_sz, u32 form,
5560 u32 form_spec)
5561 {
5562 struct mpi3_config_page_header cfg_hdr;
5563 struct mpi3_config_request cfg_req;
5564 u32 page_address;
5565
5566 memset(encl_pg0, 0, pg_sz);
5567 memset(&cfg_hdr, 0, sizeof(cfg_hdr));
5568 memset(&cfg_req, 0, sizeof(cfg_req));
5569
5570 cfg_req.function = MPI3_FUNCTION_CONFIG;
5571 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
5572 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_ENCLOSURE;
5573 cfg_req.page_number = 0;
5574 cfg_req.page_address = 0;
5575
5576 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
5577 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
5578 ioc_err(mrioc, "enclosure page0 header read failed\n");
5579 goto out_failed;
5580 }
5581 if (*ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5582 ioc_err(mrioc, "enclosure page0 header read failed with ioc_status(0x%04x)\n",
5583 *ioc_status);
5584 goto out_failed;
5585 }
5586 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
5587 page_address = ((form & MPI3_ENCLOS_PGAD_FORM_MASK) |
5588 (form_spec & MPI3_ENCLOS_PGAD_HANDLE_MASK));
5589 cfg_req.page_address = cpu_to_le32(page_address);
5590 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
5591 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, encl_pg0, pg_sz)) {
5592 ioc_err(mrioc, "enclosure page0 read failed\n");
5593 goto out_failed;
5594 }
5595 return 0;
5596 out_failed:
5597 return -1;
5598 }
5599
5600
5601 /**
5602 * mpi3mr_cfg_get_sas_io_unit_pg0 - Read current SASIOUnit page0
5603 * @mrioc: Adapter instance reference
5604 * @sas_io_unit_pg0: Pointer to return SAS IO Unit page 0
5605 * @pg_sz: Size of the memory allocated to the page pointer
5606 *
5607 * This is handler for config page read for the SAS IO Unit
5608 * page0. This routine checks ioc_status to decide whether the
5609 * page read is success or not.
5610 *
5611 * Return: 0 on success, non-zero on failure.
5612 */
mpi3mr_cfg_get_sas_io_unit_pg0(struct mpi3mr_ioc * mrioc,struct mpi3_sas_io_unit_page0 * sas_io_unit_pg0,u16 pg_sz)5613 int mpi3mr_cfg_get_sas_io_unit_pg0(struct mpi3mr_ioc *mrioc,
5614 struct mpi3_sas_io_unit_page0 *sas_io_unit_pg0, u16 pg_sz)
5615 {
5616 struct mpi3_config_page_header cfg_hdr;
5617 struct mpi3_config_request cfg_req;
5618 u16 ioc_status = 0;
5619
5620 memset(sas_io_unit_pg0, 0, pg_sz);
5621 memset(&cfg_hdr, 0, sizeof(cfg_hdr));
5622 memset(&cfg_req, 0, sizeof(cfg_req));
5623
5624 cfg_req.function = MPI3_FUNCTION_CONFIG;
5625 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
5626 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_IO_UNIT;
5627 cfg_req.page_number = 0;
5628 cfg_req.page_address = 0;
5629
5630 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
5631 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
5632 ioc_err(mrioc, "sas io unit page0 header read failed\n");
5633 goto out_failed;
5634 }
5635 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5636 ioc_err(mrioc, "sas io unit page0 header read failed with ioc_status(0x%04x)\n",
5637 ioc_status);
5638 goto out_failed;
5639 }
5640 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
5641
5642 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
5643 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, sas_io_unit_pg0, pg_sz)) {
5644 ioc_err(mrioc, "sas io unit page0 read failed\n");
5645 goto out_failed;
5646 }
5647 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5648 ioc_err(mrioc, "sas io unit page0 read failed with ioc_status(0x%04x)\n",
5649 ioc_status);
5650 goto out_failed;
5651 }
5652 return 0;
5653 out_failed:
5654 return -1;
5655 }
5656
5657 /**
5658 * mpi3mr_cfg_get_sas_io_unit_pg1 - Read current SASIOUnit page1
5659 * @mrioc: Adapter instance reference
5660 * @sas_io_unit_pg1: Pointer to return SAS IO Unit page 1
5661 * @pg_sz: Size of the memory allocated to the page pointer
5662 *
5663 * This is handler for config page read for the SAS IO Unit
5664 * page1. This routine checks ioc_status to decide whether the
5665 * page read is success or not.
5666 *
5667 * Return: 0 on success, non-zero on failure.
5668 */
mpi3mr_cfg_get_sas_io_unit_pg1(struct mpi3mr_ioc * mrioc,struct mpi3_sas_io_unit_page1 * sas_io_unit_pg1,u16 pg_sz)5669 int mpi3mr_cfg_get_sas_io_unit_pg1(struct mpi3mr_ioc *mrioc,
5670 struct mpi3_sas_io_unit_page1 *sas_io_unit_pg1, u16 pg_sz)
5671 {
5672 struct mpi3_config_page_header cfg_hdr;
5673 struct mpi3_config_request cfg_req;
5674 u16 ioc_status = 0;
5675
5676 memset(sas_io_unit_pg1, 0, pg_sz);
5677 memset(&cfg_hdr, 0, sizeof(cfg_hdr));
5678 memset(&cfg_req, 0, sizeof(cfg_req));
5679
5680 cfg_req.function = MPI3_FUNCTION_CONFIG;
5681 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
5682 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_IO_UNIT;
5683 cfg_req.page_number = 1;
5684 cfg_req.page_address = 0;
5685
5686 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
5687 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
5688 ioc_err(mrioc, "sas io unit page1 header read failed\n");
5689 goto out_failed;
5690 }
5691 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5692 ioc_err(mrioc, "sas io unit page1 header read failed with ioc_status(0x%04x)\n",
5693 ioc_status);
5694 goto out_failed;
5695 }
5696 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
5697
5698 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
5699 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, sas_io_unit_pg1, pg_sz)) {
5700 ioc_err(mrioc, "sas io unit page1 read failed\n");
5701 goto out_failed;
5702 }
5703 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5704 ioc_err(mrioc, "sas io unit page1 read failed with ioc_status(0x%04x)\n",
5705 ioc_status);
5706 goto out_failed;
5707 }
5708 return 0;
5709 out_failed:
5710 return -1;
5711 }
5712
5713 /**
5714 * mpi3mr_cfg_set_sas_io_unit_pg1 - Write SASIOUnit page1
5715 * @mrioc: Adapter instance reference
5716 * @sas_io_unit_pg1: Pointer to the SAS IO Unit page 1 to write
5717 * @pg_sz: Size of the memory allocated to the page pointer
5718 *
5719 * This is handler for config page write for the SAS IO Unit
5720 * page1. This routine checks ioc_status to decide whether the
5721 * page read is success or not. This will modify both current
5722 * and persistent page.
5723 *
5724 * Return: 0 on success, non-zero on failure.
5725 */
mpi3mr_cfg_set_sas_io_unit_pg1(struct mpi3mr_ioc * mrioc,struct mpi3_sas_io_unit_page1 * sas_io_unit_pg1,u16 pg_sz)5726 int mpi3mr_cfg_set_sas_io_unit_pg1(struct mpi3mr_ioc *mrioc,
5727 struct mpi3_sas_io_unit_page1 *sas_io_unit_pg1, u16 pg_sz)
5728 {
5729 struct mpi3_config_page_header cfg_hdr;
5730 struct mpi3_config_request cfg_req;
5731 u16 ioc_status = 0;
5732
5733 memset(&cfg_hdr, 0, sizeof(cfg_hdr));
5734 memset(&cfg_req, 0, sizeof(cfg_req));
5735
5736 cfg_req.function = MPI3_FUNCTION_CONFIG;
5737 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
5738 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_IO_UNIT;
5739 cfg_req.page_number = 1;
5740 cfg_req.page_address = 0;
5741
5742 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
5743 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
5744 ioc_err(mrioc, "sas io unit page1 header read failed\n");
5745 goto out_failed;
5746 }
5747 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5748 ioc_err(mrioc, "sas io unit page1 header read failed with ioc_status(0x%04x)\n",
5749 ioc_status);
5750 goto out_failed;
5751 }
5752 cfg_req.action = MPI3_CONFIG_ACTION_WRITE_CURRENT;
5753
5754 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
5755 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, sas_io_unit_pg1, pg_sz)) {
5756 ioc_err(mrioc, "sas io unit page1 write current failed\n");
5757 goto out_failed;
5758 }
5759 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5760 ioc_err(mrioc, "sas io unit page1 write current failed with ioc_status(0x%04x)\n",
5761 ioc_status);
5762 goto out_failed;
5763 }
5764
5765 cfg_req.action = MPI3_CONFIG_ACTION_WRITE_PERSISTENT;
5766
5767 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
5768 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, sas_io_unit_pg1, pg_sz)) {
5769 ioc_err(mrioc, "sas io unit page1 write persistent failed\n");
5770 goto out_failed;
5771 }
5772 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5773 ioc_err(mrioc, "sas io unit page1 write persistent failed with ioc_status(0x%04x)\n",
5774 ioc_status);
5775 goto out_failed;
5776 }
5777 return 0;
5778 out_failed:
5779 return -1;
5780 }
5781
5782 /**
5783 * mpi3mr_cfg_get_driver_pg1 - Read current Driver page1
5784 * @mrioc: Adapter instance reference
5785 * @driver_pg1: Pointer to return Driver page 1
5786 * @pg_sz: Size of the memory allocated to the page pointer
5787 *
5788 * This is handler for config page read for the Driver page1.
5789 * This routine checks ioc_status to decide whether the page
5790 * read is success or not.
5791 *
5792 * Return: 0 on success, non-zero on failure.
5793 */
mpi3mr_cfg_get_driver_pg1(struct mpi3mr_ioc * mrioc,struct mpi3_driver_page1 * driver_pg1,u16 pg_sz)5794 int mpi3mr_cfg_get_driver_pg1(struct mpi3mr_ioc *mrioc,
5795 struct mpi3_driver_page1 *driver_pg1, u16 pg_sz)
5796 {
5797 struct mpi3_config_page_header cfg_hdr;
5798 struct mpi3_config_request cfg_req;
5799 u16 ioc_status = 0;
5800
5801 memset(driver_pg1, 0, pg_sz);
5802 memset(&cfg_hdr, 0, sizeof(cfg_hdr));
5803 memset(&cfg_req, 0, sizeof(cfg_req));
5804
5805 cfg_req.function = MPI3_FUNCTION_CONFIG;
5806 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
5807 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_DRIVER;
5808 cfg_req.page_number = 1;
5809 cfg_req.page_address = 0;
5810
5811 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
5812 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
5813 ioc_err(mrioc, "driver page1 header read failed\n");
5814 goto out_failed;
5815 }
5816 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5817 ioc_err(mrioc, "driver page1 header read failed with ioc_status(0x%04x)\n",
5818 ioc_status);
5819 goto out_failed;
5820 }
5821 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
5822
5823 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
5824 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, driver_pg1, pg_sz)) {
5825 ioc_err(mrioc, "driver page1 read failed\n");
5826 goto out_failed;
5827 }
5828 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5829 ioc_err(mrioc, "driver page1 read failed with ioc_status(0x%04x)\n",
5830 ioc_status);
5831 goto out_failed;
5832 }
5833 return 0;
5834 out_failed:
5835 return -1;
5836 }
5837