xref: /openbmc/u-boot/arch/powerpc/cpu/mpc83xx/pcie.c (revision e8f80a5a)
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright (C) 2007-2009  Freescale Semiconductor, Inc.
4  * Copyright (C) 2008-2009  MontaVista Software, Inc.
5  *
6  * Authors: Tony Li <tony.li@freescale.com>
7  *          Anton Vorontsov <avorontsov@ru.mvista.com>
8  */
9 
10 #include <common.h>
11 #include <pci.h>
12 #include <mpc83xx.h>
13 #include <asm/io.h>
14 
15 DECLARE_GLOBAL_DATA_PTR;
16 
17 #define PCIE_MAX_BUSES 2
18 
19 static struct {
20 	u32 base;
21 	u32 size;
22 } mpc83xx_pcie_cfg_space[] = {
23 	{
24 		.base = CONFIG_SYS_PCIE1_CFG_BASE,
25 		.size = CONFIG_SYS_PCIE1_CFG_SIZE,
26 	},
27 #if defined(CONFIG_SYS_PCIE2_CFG_BASE) && defined(CONFIG_SYS_PCIE2_CFG_SIZE)
28 	{
29 		.base = CONFIG_SYS_PCIE2_CFG_BASE,
30 		.size = CONFIG_SYS_PCIE2_CFG_SIZE,
31 	},
32 #endif
33 };
34 
35 #ifdef CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES
36 
37 /* private structure for mpc83xx pcie hose */
38 static struct mpc83xx_pcie_priv {
39 	u8 index;
40 } pcie_priv[PCIE_MAX_BUSES] = {
41 	{
42 		/* pcie controller 1 */
43 		.index = 0,
44 	},
45 	{
46 		/* pcie controller 2 */
47 		.index = 1,
48 	},
49 };
50 
mpc83xx_pcie_remap_cfg(struct pci_controller * hose,pci_dev_t dev)51 static int mpc83xx_pcie_remap_cfg(struct pci_controller *hose, pci_dev_t dev)
52 {
53 	int bus = PCI_BUS(dev) - hose->first_busno;
54 	immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
55 	struct mpc83xx_pcie_priv *pcie_priv = hose->priv_data;
56 	pex83xx_t *pex = &immr->pciexp[pcie_priv->index];
57 	struct pex_outbound_window *out_win = &pex->bridge.pex_outbound_win[0];
58 	u8 devfn = PCI_DEV(dev) << 3 | PCI_FUNC(dev);
59 	u32 dev_base = bus << 24 | devfn << 16;
60 
61 	if (hose->indirect_type == INDIRECT_TYPE_NO_PCIE_LINK)
62 		return -1;
63 	/*
64 	 * Workaround for the HW bug: for Type 0 configure transactions the
65 	 * PCI-E controller does not check the device number bits and just
66 	 * assumes that the device number bits are 0.
67 	 */
68 	if (devfn & 0xf8)
69 		return -1;
70 
71 	out_le32(&out_win->tarl, dev_base);
72 	return 0;
73 }
74 
75 #define cfg_read(val, addr, type, op) \
76 	do { *val = op((type)(addr)); } while (0)
77 #define cfg_write(val, addr, type, op) \
78 	do { op((type *)(addr), (val)); } while (0)
79 
80 #define cfg_read_err(val) do { *val = -1; } while (0)
81 #define cfg_write_err(val) do { } while (0)
82 
83 #define PCIE_OP(rw, size, type, op)					\
84 static int pcie_##rw##_config_##size(struct pci_controller *hose,	\
85 				     pci_dev_t dev, int offset,		\
86 				     type val)				\
87 {									\
88 	int ret;							\
89 									\
90 	ret = mpc83xx_pcie_remap_cfg(hose, dev);			\
91 	if (ret) {							\
92 		cfg_##rw##_err(val); 					\
93 		return ret; 						\
94 	}								\
95 	cfg_##rw(val, (void *)hose->cfg_addr + offset, type, op);	\
96 	return 0;							\
97 }
98 
PCIE_OP(read,byte,u8 *,in_8)99 PCIE_OP(read, byte, u8 *, in_8)
100 PCIE_OP(read, word, u16 *, in_le16)
101 PCIE_OP(read, dword, u32 *, in_le32)
102 PCIE_OP(write, byte, u8, out_8)
103 PCIE_OP(write, word, u16, out_le16)
104 PCIE_OP(write, dword, u32, out_le32)
105 
106 static void mpc83xx_pcie_register_hose(int bus, struct pci_region *reg,
107 				       u8 link)
108 {
109 	extern void disable_addr_trans(void); /* start.S */
110 	static struct pci_controller pcie_hose[PCIE_MAX_BUSES];
111 	struct pci_controller *hose = &pcie_hose[bus];
112 	int i;
113 
114 	/*
115 	 * There are no spare BATs to remap all PCI-E windows for U-Boot, so
116 	 * disable translations. In general, this is not great solution, and
117 	 * that's why we don't register PCI-E hoses by default.
118 	 */
119 	disable_addr_trans();
120 
121 	for (i = 0; i < 2; i++, reg++) {
122 		if (reg->size == 0)
123 			break;
124 
125 		hose->regions[i] = *reg;
126 		hose->region_count++;
127 	}
128 
129 	i = hose->region_count++;
130 	hose->regions[i].bus_start = 0;
131 	hose->regions[i].phys_start = 0;
132 	hose->regions[i].size = gd->ram_size;
133 	hose->regions[i].flags = PCI_REGION_MEM | PCI_REGION_SYS_MEMORY;
134 
135 	i = hose->region_count++;
136 	hose->regions[i].bus_start = CONFIG_SYS_IMMR;
137 	hose->regions[i].phys_start = CONFIG_SYS_IMMR;
138 	hose->regions[i].size = 0x100000;
139 	hose->regions[i].flags = PCI_REGION_MEM | PCI_REGION_SYS_MEMORY;
140 
141 	hose->first_busno = pci_last_busno() + 1;
142 	hose->last_busno = 0xff;
143 
144 	hose->cfg_addr = (unsigned int *)mpc83xx_pcie_cfg_space[bus].base;
145 
146 	hose->priv_data = &pcie_priv[bus];
147 
148 	pci_set_ops(hose,
149 			pcie_read_config_byte,
150 			pcie_read_config_word,
151 			pcie_read_config_dword,
152 			pcie_write_config_byte,
153 			pcie_write_config_word,
154 			pcie_write_config_dword);
155 
156 	if (!link)
157 		hose->indirect_type = INDIRECT_TYPE_NO_PCIE_LINK;
158 
159 	pci_register_hose(hose);
160 
161 #ifdef CONFIG_PCI_SCAN_SHOW
162 	printf("PCI:   Bus Dev VenId DevId Class Int\n");
163 #endif
164 	/*
165 	 * Hose scan.
166 	 */
167 	hose->last_busno = pci_hose_scan(hose);
168 }
169 
170 #else
171 
mpc83xx_pcie_register_hose(int bus,struct pci_region * reg,u8 link)172 static void mpc83xx_pcie_register_hose(int bus, struct pci_region *reg,
173 				       u8 link) {}
174 
175 #endif /* CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES */
176 
mpc83xx_pcie_init_bus(int bus,struct pci_region * reg)177 static void mpc83xx_pcie_init_bus(int bus, struct pci_region *reg)
178 {
179 	immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
180 	pex83xx_t *pex = &immr->pciexp[bus];
181 	struct pex_outbound_window *out_win;
182 	struct pex_inbound_window *in_win;
183 	void *hose_cfg_base;
184 	unsigned int ram_sz;
185 	unsigned int barl;
186 	unsigned int tar;
187 	u16 reg16;
188 	int i;
189 
190 	/* Enable pex csb bridge inbound & outbound transactions */
191 	out_le32(&pex->bridge.pex_csb_ctrl,
192 		in_le32(&pex->bridge.pex_csb_ctrl) | PEX_CSB_CTRL_OBPIOE |
193 		PEX_CSB_CTRL_IBPIOE);
194 
195 	/* Enable bridge outbound */
196 	out_le32(&pex->bridge.pex_csb_obctrl, PEX_CSB_OBCTRL_PIOE |
197 		PEX_CSB_OBCTRL_MEMWE | PEX_CSB_OBCTRL_IOWE |
198 		PEX_CSB_OBCTRL_CFGWE);
199 
200 	out_win = &pex->bridge.pex_outbound_win[0];
201 	out_le32(&out_win->ar, PEX_OWAR_EN | PEX_OWAR_TYPE_CFG |
202 			mpc83xx_pcie_cfg_space[bus].size);
203 	out_le32(&out_win->bar, mpc83xx_pcie_cfg_space[bus].base);
204 	out_le32(&out_win->tarl, 0);
205 	out_le32(&out_win->tarh, 0);
206 
207 	for (i = 0; i < 2; i++) {
208 		u32 ar;
209 
210 		if (reg[i].size == 0)
211 			break;
212 
213 		out_win = &pex->bridge.pex_outbound_win[i + 1];
214 		out_le32(&out_win->bar, reg[i].phys_start);
215 		out_le32(&out_win->tarl, reg[i].bus_start);
216 		out_le32(&out_win->tarh, 0);
217 		ar = PEX_OWAR_EN | (reg[i].size & PEX_OWAR_SIZE);
218 		if (reg[i].flags & PCI_REGION_IO)
219 			ar |= PEX_OWAR_TYPE_IO;
220 		else
221 			ar |= PEX_OWAR_TYPE_MEM;
222 		out_le32(&out_win->ar, ar);
223 	}
224 
225 	out_le32(&pex->bridge.pex_csb_ibctrl, PEX_CSB_IBCTRL_PIOE);
226 
227 	ram_sz = gd->ram_size;
228 	barl = 0;
229 	tar = 0;
230 	i = 0;
231 	while (ram_sz > 0) {
232 		in_win = &pex->bridge.pex_inbound_win[i];
233 		out_le32(&in_win->barl, barl);
234 		out_le32(&in_win->barh, 0x0);
235 		out_le32(&in_win->tar, tar);
236 		if (ram_sz >= 0x10000000) {
237 			/* The maxium windows size is 256M */
238 			out_le32(&in_win->ar, PEX_IWAR_EN | PEX_IWAR_NSOV |
239 				PEX_IWAR_TYPE_PF | 0x0FFFF000);
240 			barl += 0x10000000;
241 			tar += 0x10000000;
242 			ram_sz -= 0x10000000;
243 		} else {
244 			/* The UM  is not clear here.
245 			 * So, round up to even Mb boundary */
246 
247 			ram_sz = ram_sz >> (20 +
248 					((ram_sz & 0xFFFFF) ? 1 : 0));
249 			if (!(ram_sz % 2))
250 				ram_sz -= 1;
251 			out_le32(&in_win->ar, PEX_IWAR_EN | PEX_IWAR_NSOV |
252 				PEX_IWAR_TYPE_PF | (ram_sz << 20) | 0xFF000);
253 			ram_sz = 0;
254 		}
255 		i++;
256 	}
257 
258 	in_win = &pex->bridge.pex_inbound_win[i];
259 	out_le32(&in_win->barl, CONFIG_SYS_IMMR);
260 	out_le32(&in_win->barh, 0);
261 	out_le32(&in_win->tar, CONFIG_SYS_IMMR);
262 	out_le32(&in_win->ar, PEX_IWAR_EN |
263 		PEX_IWAR_TYPE_NO_PF | PEX_IWAR_SIZE_1M);
264 
265 	/* Enable the host virtual INTX interrupts */
266 	out_le32(&pex->bridge.pex_int_axi_misc_enb,
267 		in_le32(&pex->bridge.pex_int_axi_misc_enb) | 0x1E0);
268 
269 	/* Hose configure header is memory-mapped */
270 	hose_cfg_base = (void *)pex;
271 
272 	get_clocks();
273 	/* Configure the PCIE controller core clock ratio */
274 	out_le32(hose_cfg_base + PEX_GCLK_RATIO,
275 		(((bus ? gd->arch.pciexp2_clk : gd->arch.pciexp1_clk)
276 			/ 1000000) * 16) / 333);
277 	udelay(1000000);
278 
279 	/* Do Type 1 bridge configuration */
280 	out_8(hose_cfg_base + PCI_PRIMARY_BUS, 0);
281 	out_8(hose_cfg_base + PCI_SECONDARY_BUS, 1);
282 	out_8(hose_cfg_base + PCI_SUBORDINATE_BUS, 255);
283 
284 	/*
285 	 * Write to Command register
286 	 */
287 	reg16 = in_le16(hose_cfg_base + PCI_COMMAND);
288 	reg16 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO |
289 			PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
290 	out_le16(hose_cfg_base + PCI_COMMAND, reg16);
291 
292 	/*
293 	 * Clear non-reserved bits in status register.
294 	 */
295 	out_le16(hose_cfg_base + PCI_STATUS, 0xffff);
296 	out_8(hose_cfg_base + PCI_LATENCY_TIMER, 0x80);
297 	out_8(hose_cfg_base + PCI_CACHE_LINE_SIZE, 0x08);
298 
299 	printf("PCIE%d: ", bus);
300 
301 #define PCI_LTSSM	0x404 /* PCIe Link Training, Status State Machine */
302 #define PCI_LTSSM_L0	0x16 /* L0 state */
303 	reg16 = in_le16(hose_cfg_base + PCI_LTSSM);
304 	if (reg16 >= PCI_LTSSM_L0)
305 		printf("link\n");
306 	else
307 		printf("No link\n");
308 
309 	mpc83xx_pcie_register_hose(bus, reg, reg16 >= PCI_LTSSM_L0);
310 }
311 
312 /*
313  * The caller must have already set SCCR, SERDES and the PCIE_LAW BARs
314  * must have been set to cover all of the requested regions.
315  */
mpc83xx_pcie_init(int num_buses,struct pci_region ** reg)316 void mpc83xx_pcie_init(int num_buses, struct pci_region **reg)
317 {
318 	int i;
319 
320 	/*
321 	 * Release PCI RST Output signal.
322 	 * Power on to RST high must be at least 100 ms as per PCI spec.
323 	 * On warm boots only 1 ms is required, but we play it safe.
324 	 */
325 	udelay(100000);
326 
327 	if (num_buses > ARRAY_SIZE(mpc83xx_pcie_cfg_space)) {
328 		printf("Second PCIE host contoller not configured!\n");
329 		num_buses = ARRAY_SIZE(mpc83xx_pcie_cfg_space);
330 	}
331 
332 	for (i = 0; i < num_buses; i++)
333 		mpc83xx_pcie_init_bus(i, reg[i]);
334 }
335