xref: /openbmc/linux/drivers/hwmon/hwmon-vid.c (revision df561f66)
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * hwmon-vid.c - VID/VRM/VRD voltage conversions
4  *
5  * Copyright (c) 2004 Rudolf Marek <r.marek@assembler.cz>
6  *
7  * Partly imported from i2c-vid.h of the lm_sensors project
8  * Copyright (c) 2002 Mark D. Studebaker <mdsxyz123@yahoo.com>
9  * With assistance from Trent Piepho <xyzzy@speakeasy.org>
10  */
11 
12 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
13 
14 #include <linux/module.h>
15 #include <linux/kernel.h>
16 #include <linux/hwmon-vid.h>
17 
18 /*
19  * Common code for decoding VID pins.
20  *
21  * References:
22  *
23  * For VRM 8.4 to 9.1, "VRM x.y DC-DC Converter Design Guidelines",
24  * available at http://developer.intel.com/.
25  *
26  * For VRD 10.0 and up, "VRD x.y Design Guide",
27  * available at http://developer.intel.com/.
28  *
29  * AMD Athlon 64 and AMD Opteron Processors, AMD Publication 26094,
30  * http://support.amd.com/us/Processor_TechDocs/26094.PDF
31  * Table 74. VID Code Voltages
32  * This corresponds to an arbitrary VRM code of 24 in the functions below.
33  * These CPU models (K8 revision <= E) have 5 VID pins. See also:
34  * Revision Guide for AMD Athlon 64 and AMD Opteron Processors, AMD Publication 25759,
35  * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25759.pdf
36  *
37  * AMD NPT Family 0Fh Processors, AMD Publication 32559,
38  * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/32559.pdf
39  * Table 71. VID Code Voltages
40  * This corresponds to an arbitrary VRM code of 25 in the functions below.
41  * These CPU models (K8 revision >= F) have 6 VID pins. See also:
42  * Revision Guide for AMD NPT Family 0Fh Processors, AMD Publication 33610,
43  * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
44  *
45  * The 17 specification is in fact Intel Mobile Voltage Positioning -
46  * (IMVP-II). You can find more information in the datasheet of Max1718
47  * http://www.maxim-ic.com/quick_view2.cfm/qv_pk/2452
48  *
49  * The 13 specification corresponds to the Intel Pentium M series. There
50  * doesn't seem to be any named specification for these. The conversion
51  * tables are detailed directly in the various Pentium M datasheets:
52  * https://www.intel.com/design/intarch/pentiumm/docs_pentiumm.htm
53  *
54  * The 14 specification corresponds to Intel Core series. There
55  * doesn't seem to be any named specification for these. The conversion
56  * tables are detailed directly in the various Pentium Core datasheets:
57  * https://www.intel.com/design/mobile/datashts/309221.htm
58  *
59  * The 110 (VRM 11) specification corresponds to Intel Conroe based series.
60  * https://www.intel.com/design/processor/applnots/313214.htm
61  */
62 
63 /*
64  * vrm is the VRM/VRD document version multiplied by 10.
65  * val is the 4-bit or more VID code.
66  * Returned value is in mV to avoid floating point in the kernel.
67  * Some VID have some bits in uV scale, this is rounded to mV.
68  */
vid_from_reg(int val,u8 vrm)69 int vid_from_reg(int val, u8 vrm)
70 {
71 	int vid;
72 
73 	switch (vrm) {
74 
75 	case 100:		/* VRD 10.0 */
76 		/* compute in uV, round to mV */
77 		val &= 0x3f;
78 		if ((val & 0x1f) == 0x1f)
79 			return 0;
80 		if ((val & 0x1f) <= 0x09 || val == 0x0a)
81 			vid = 1087500 - (val & 0x1f) * 25000;
82 		else
83 			vid = 1862500 - (val & 0x1f) * 25000;
84 		if (val & 0x20)
85 			vid -= 12500;
86 		return (vid + 500) / 1000;
87 
88 	case 110:		/* Intel Conroe */
89 				/* compute in uV, round to mV */
90 		val &= 0xff;
91 		if (val < 0x02 || val > 0xb2)
92 			return 0;
93 		return (1600000 - (val - 2) * 6250 + 500) / 1000;
94 
95 	case 24:		/* Athlon64 & Opteron */
96 		val &= 0x1f;
97 		if (val == 0x1f)
98 			return 0;
99 		fallthrough;
100 	case 25:		/* AMD NPT 0Fh */
101 		val &= 0x3f;
102 		return (val < 32) ? 1550 - 25 * val
103 			: 775 - (25 * (val - 31)) / 2;
104 
105 	case 26:		/* AMD family 10h to 15h, serial VID */
106 		val &= 0x7f;
107 		if (val >= 0x7c)
108 			return 0;
109 		return DIV_ROUND_CLOSEST(15500 - 125 * val, 10);
110 
111 	case 91:		/* VRM 9.1 */
112 	case 90:		/* VRM 9.0 */
113 		val &= 0x1f;
114 		return val == 0x1f ? 0 :
115 				     1850 - val * 25;
116 
117 	case 85:		/* VRM 8.5 */
118 		val &= 0x1f;
119 		return (val & 0x10  ? 25 : 0) +
120 		       ((val & 0x0f) > 0x04 ? 2050 : 1250) -
121 		       ((val & 0x0f) * 50);
122 
123 	case 84:		/* VRM 8.4 */
124 		val &= 0x0f;
125 		fallthrough;
126 	case 82:		/* VRM 8.2 */
127 		val &= 0x1f;
128 		return val == 0x1f ? 0 :
129 		       val & 0x10  ? 5100 - (val) * 100 :
130 				     2050 - (val) * 50;
131 	case 17:		/* Intel IMVP-II */
132 		val &= 0x1f;
133 		return val & 0x10 ? 975 - (val & 0xF) * 25 :
134 				    1750 - val * 50;
135 	case 13:
136 	case 131:
137 		val &= 0x3f;
138 		/* Exception for Eden ULV 500 MHz */
139 		if (vrm == 131 && val == 0x3f)
140 			val++;
141 		return 1708 - val * 16;
142 	case 14:		/* Intel Core */
143 				/* compute in uV, round to mV */
144 		val &= 0x7f;
145 		return val > 0x77 ? 0 : (1500000 - (val * 12500) + 500) / 1000;
146 	default:		/* report 0 for unknown */
147 		if (vrm)
148 			pr_warn("Requested unsupported VRM version (%u)\n",
149 				(unsigned int)vrm);
150 		return 0;
151 	}
152 }
153 EXPORT_SYMBOL(vid_from_reg);
154 
155 /*
156  * After this point is the code to automatically determine which
157  * VRM/VRD specification should be used depending on the CPU.
158  */
159 
160 struct vrm_model {
161 	u8 vendor;
162 	u8 family;
163 	u8 model_from;
164 	u8 model_to;
165 	u8 stepping_to;
166 	u8 vrm_type;
167 };
168 
169 #define ANY 0xFF
170 
171 #ifdef CONFIG_X86
172 
173 /*
174  * The stepping_to parameter is highest acceptable stepping for current line.
175  * The model match must be exact for 4-bit values. For model values 0x10
176  * and above (extended model), all models below the parameter will match.
177  */
178 
179 static struct vrm_model vrm_models[] = {
180 	{X86_VENDOR_AMD, 0x6, 0x0, ANY, ANY, 90},	/* Athlon Duron etc */
181 	{X86_VENDOR_AMD, 0xF, 0x0, 0x3F, ANY, 24},	/* Athlon 64, Opteron */
182 	/*
183 	 * In theory, all NPT family 0Fh processors have 6 VID pins and should
184 	 * thus use vrm 25, however in practice not all mainboards route the
185 	 * 6th VID pin because it is never needed. So we use the 5 VID pin
186 	 * variant (vrm 24) for the models which exist today.
187 	 */
188 	{X86_VENDOR_AMD, 0xF, 0x40, 0x7F, ANY, 24},	/* NPT family 0Fh */
189 	{X86_VENDOR_AMD, 0xF, 0x80, ANY, ANY, 25},	/* future fam. 0Fh */
190 	{X86_VENDOR_AMD, 0x10, 0x0, ANY, ANY, 25},	/* NPT family 10h */
191 	{X86_VENDOR_AMD, 0x11, 0x0, ANY, ANY, 26},	/* family 11h */
192 	{X86_VENDOR_AMD, 0x12, 0x0, ANY, ANY, 26},	/* family 12h */
193 	{X86_VENDOR_AMD, 0x14, 0x0, ANY, ANY, 26},	/* family 14h */
194 	{X86_VENDOR_AMD, 0x15, 0x0, ANY, ANY, 26},	/* family 15h */
195 
196 	{X86_VENDOR_INTEL, 0x6, 0x0, 0x6, ANY, 82},	/* Pentium Pro,
197 							 * Pentium II, Xeon,
198 							 * Mobile Pentium,
199 							 * Celeron */
200 	{X86_VENDOR_INTEL, 0x6, 0x7, 0x7, ANY, 84},	/* Pentium III, Xeon */
201 	{X86_VENDOR_INTEL, 0x6, 0x8, 0x8, ANY, 82},	/* Pentium III, Xeon */
202 	{X86_VENDOR_INTEL, 0x6, 0x9, 0x9, ANY, 13},	/* Pentium M (130 nm) */
203 	{X86_VENDOR_INTEL, 0x6, 0xA, 0xA, ANY, 82},	/* Pentium III Xeon */
204 	{X86_VENDOR_INTEL, 0x6, 0xB, 0xB, ANY, 85},	/* Tualatin */
205 	{X86_VENDOR_INTEL, 0x6, 0xD, 0xD, ANY, 13},	/* Pentium M (90 nm) */
206 	{X86_VENDOR_INTEL, 0x6, 0xE, 0xE, ANY, 14},	/* Intel Core (65 nm) */
207 	{X86_VENDOR_INTEL, 0x6, 0xF, ANY, ANY, 110},	/* Intel Conroe and
208 							 * later */
209 	{X86_VENDOR_INTEL, 0xF, 0x0, 0x0, ANY, 90},	/* P4 */
210 	{X86_VENDOR_INTEL, 0xF, 0x1, 0x1, ANY, 90},	/* P4 Willamette */
211 	{X86_VENDOR_INTEL, 0xF, 0x2, 0x2, ANY, 90},	/* P4 Northwood */
212 	{X86_VENDOR_INTEL, 0xF, 0x3, ANY, ANY, 100},	/* Prescott and above
213 							 * assume VRD 10 */
214 
215 	{X86_VENDOR_CENTAUR, 0x6, 0x7, 0x7, ANY, 85},	/* Eden ESP/Ezra */
216 	{X86_VENDOR_CENTAUR, 0x6, 0x8, 0x8, 0x7, 85},	/* Ezra T */
217 	{X86_VENDOR_CENTAUR, 0x6, 0x9, 0x9, 0x7, 85},	/* Nehemiah */
218 	{X86_VENDOR_CENTAUR, 0x6, 0x9, 0x9, ANY, 17},	/* C3-M, Eden-N */
219 	{X86_VENDOR_CENTAUR, 0x6, 0xA, 0xA, 0x7, 0},	/* No information */
220 	{X86_VENDOR_CENTAUR, 0x6, 0xA, 0xA, ANY, 13},	/* C7-M, C7,
221 							 * Eden (Esther) */
222 	{X86_VENDOR_CENTAUR, 0x6, 0xD, 0xD, ANY, 134},	/* C7-D, C7-M, C7,
223 							 * Eden (Esther) */
224 };
225 
226 /*
227  * Special case for VIA model D: there are two different possible
228  * VID tables, so we have to figure out first, which one must be
229  * used. This resolves temporary drm value 134 to 14 (Intel Core
230  * 7-bit VID), 13 (Pentium M 6-bit VID) or 131 (Pentium M 6-bit VID
231  * + quirk for Eden ULV 500 MHz).
232  * Note: something similar might be needed for model A, I'm not sure.
233  */
get_via_model_d_vrm(void)234 static u8 get_via_model_d_vrm(void)
235 {
236 	unsigned int vid, brand, __maybe_unused dummy;
237 	static const char *brands[4] = {
238 		"C7-M", "C7", "Eden", "C7-D"
239 	};
240 
241 	rdmsr(0x198, dummy, vid);
242 	vid &= 0xff;
243 
244 	rdmsr(0x1154, brand, dummy);
245 	brand = ((brand >> 4) ^ (brand >> 2)) & 0x03;
246 
247 	if (vid > 0x3f) {
248 		pr_info("Using %d-bit VID table for VIA %s CPU\n",
249 			7, brands[brand]);
250 		return 14;
251 	} else {
252 		pr_info("Using %d-bit VID table for VIA %s CPU\n",
253 			6, brands[brand]);
254 		/* Enable quirk for Eden */
255 		return brand == 2 ? 131 : 13;
256 	}
257 }
258 
find_vrm(u8 family,u8 model,u8 stepping,u8 vendor)259 static u8 find_vrm(u8 family, u8 model, u8 stepping, u8 vendor)
260 {
261 	int i;
262 
263 	for (i = 0; i < ARRAY_SIZE(vrm_models); i++) {
264 		if (vendor == vrm_models[i].vendor &&
265 		    family == vrm_models[i].family &&
266 		    model >= vrm_models[i].model_from &&
267 		    model <= vrm_models[i].model_to &&
268 		    stepping <= vrm_models[i].stepping_to)
269 			return vrm_models[i].vrm_type;
270 	}
271 
272 	return 0;
273 }
274 
vid_which_vrm(void)275 u8 vid_which_vrm(void)
276 {
277 	struct cpuinfo_x86 *c = &cpu_data(0);
278 	u8 vrm_ret;
279 
280 	if (c->x86 < 6)		/* Any CPU with family lower than 6 */
281 		return 0;	/* doesn't have VID */
282 
283 	vrm_ret = find_vrm(c->x86, c->x86_model, c->x86_stepping, c->x86_vendor);
284 	if (vrm_ret == 134)
285 		vrm_ret = get_via_model_d_vrm();
286 	if (vrm_ret == 0)
287 		pr_info("Unknown VRM version of your x86 CPU\n");
288 	return vrm_ret;
289 }
290 
291 /* and now for something completely different for the non-x86 world */
292 #else
vid_which_vrm(void)293 u8 vid_which_vrm(void)
294 {
295 	pr_info("Unknown VRM version of your CPU\n");
296 	return 0;
297 }
298 #endif
299 EXPORT_SYMBOL(vid_which_vrm);
300 
301 MODULE_AUTHOR("Rudolf Marek <r.marek@assembler.cz>");
302 
303 MODULE_DESCRIPTION("hwmon-vid driver");
304 MODULE_LICENSE("GPL");
305