xref: /openbmc/linux/drivers/net/ethernet/chelsio/cxgb4/t4fw_api.h (revision 03ab8e6297acd1bc0eedaa050e2a1635c576fd11)
1  /*
2   * This file is part of the Chelsio T4 Ethernet driver for Linux.
3   *
4   * Copyright (c) 2009-2016 Chelsio Communications, Inc. All rights reserved.
5   *
6   * This software is available to you under a choice of one of two
7   * licenses.  You may choose to be licensed under the terms of the GNU
8   * General Public License (GPL) Version 2, available from the file
9   * COPYING in the main directory of this source tree, or the
10   * OpenIB.org BSD license below:
11   *
12   *     Redistribution and use in source and binary forms, with or
13   *     without modification, are permitted provided that the following
14   *     conditions are met:
15   *
16   *      - Redistributions of source code must retain the above
17   *        copyright notice, this list of conditions and the following
18   *        disclaimer.
19   *
20   *      - Redistributions in binary form must reproduce the above
21   *        copyright notice, this list of conditions and the following
22   *        disclaimer in the documentation and/or other materials
23   *        provided with the distribution.
24   *
25   * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26   * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27   * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28   * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29   * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30   * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31   * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32   * SOFTWARE.
33   */
34  
35  #ifndef _T4FW_INTERFACE_H_
36  #define _T4FW_INTERFACE_H_
37  
38  enum fw_retval {
39  	FW_SUCCESS		= 0,	/* completed successfully */
40  	FW_EPERM		= 1,	/* operation not permitted */
41  	FW_ENOENT		= 2,	/* no such file or directory */
42  	FW_EIO			= 5,	/* input/output error; hw bad */
43  	FW_ENOEXEC		= 8,	/* exec format error; inv microcode */
44  	FW_EAGAIN		= 11,	/* try again */
45  	FW_ENOMEM		= 12,	/* out of memory */
46  	FW_EFAULT		= 14,	/* bad address; fw bad */
47  	FW_EBUSY		= 16,	/* resource busy */
48  	FW_EEXIST		= 17,	/* file exists */
49  	FW_ENODEV		= 19,	/* no such device */
50  	FW_EINVAL		= 22,	/* invalid argument */
51  	FW_ENOSPC		= 28,	/* no space left on device */
52  	FW_ENOSYS		= 38,	/* functionality not implemented */
53  	FW_ENODATA		= 61,	/* no data available */
54  	FW_EPROTO		= 71,	/* protocol error */
55  	FW_EADDRINUSE		= 98,	/* address already in use */
56  	FW_EADDRNOTAVAIL	= 99,	/* cannot assigned requested address */
57  	FW_ENETDOWN		= 100,	/* network is down */
58  	FW_ENETUNREACH		= 101,	/* network is unreachable */
59  	FW_ENOBUFS		= 105,	/* no buffer space available */
60  	FW_ETIMEDOUT		= 110,	/* timeout */
61  	FW_EINPROGRESS		= 115,	/* fw internal */
62  	FW_SCSI_ABORT_REQUESTED	= 128,	/* */
63  	FW_SCSI_ABORT_TIMEDOUT	= 129,	/* */
64  	FW_SCSI_ABORTED		= 130,	/* */
65  	FW_SCSI_CLOSE_REQUESTED	= 131,	/* */
66  	FW_ERR_LINK_DOWN	= 132,	/* */
67  	FW_RDEV_NOT_READY	= 133,	/* */
68  	FW_ERR_RDEV_LOST	= 134,	/* */
69  	FW_ERR_RDEV_LOGO	= 135,	/* */
70  	FW_FCOE_NO_XCHG		= 136,	/* */
71  	FW_SCSI_RSP_ERR		= 137,	/* */
72  	FW_ERR_RDEV_IMPL_LOGO	= 138,	/* */
73  	FW_SCSI_UNDER_FLOW_ERR  = 139,	/* */
74  	FW_SCSI_OVER_FLOW_ERR   = 140,	/* */
75  	FW_SCSI_DDP_ERR		= 141,	/* DDP error*/
76  	FW_SCSI_TASK_ERR	= 142,	/* No SCSI tasks available */
77  };
78  
79  #define FW_T4VF_SGE_BASE_ADDR      0x0000
80  #define FW_T4VF_MPS_BASE_ADDR      0x0100
81  #define FW_T4VF_PL_BASE_ADDR       0x0200
82  #define FW_T4VF_MBDATA_BASE_ADDR   0x0240
83  #define FW_T4VF_CIM_BASE_ADDR      0x0300
84  
85  enum fw_wr_opcodes {
86  	FW_FILTER_WR                   = 0x02,
87  	FW_ULPTX_WR                    = 0x04,
88  	FW_TP_WR                       = 0x05,
89  	FW_ETH_TX_PKT_WR               = 0x08,
90  	FW_ETH_TX_EO_WR                = 0x1c,
91  	FW_OFLD_CONNECTION_WR          = 0x2f,
92  	FW_FLOWC_WR                    = 0x0a,
93  	FW_OFLD_TX_DATA_WR             = 0x0b,
94  	FW_CMD_WR                      = 0x10,
95  	FW_ETH_TX_PKT_VM_WR            = 0x11,
96  	FW_RI_RES_WR                   = 0x0c,
97  	FW_RI_INIT_WR                  = 0x0d,
98  	FW_RI_RDMA_WRITE_WR            = 0x14,
99  	FW_RI_SEND_WR                  = 0x15,
100  	FW_RI_RDMA_READ_WR             = 0x16,
101  	FW_RI_RECV_WR                  = 0x17,
102  	FW_RI_BIND_MW_WR               = 0x18,
103  	FW_RI_FR_NSMR_WR               = 0x19,
104  	FW_RI_FR_NSMR_TPTE_WR	       = 0x20,
105  	FW_RI_RDMA_WRITE_CMPL_WR       = 0x21,
106  	FW_RI_INV_LSTAG_WR             = 0x1a,
107  	FW_ISCSI_TX_DATA_WR	       = 0x45,
108  	FW_PTP_TX_PKT_WR               = 0x46,
109  	FW_TLSTX_DATA_WR	       = 0x68,
110  	FW_CRYPTO_LOOKASIDE_WR         = 0X6d,
111  	FW_LASTC2E_WR                  = 0x70,
112  	FW_FILTER2_WR		       = 0x77
113  };
114  
115  struct fw_wr_hdr {
116  	__be32 hi;
117  	__be32 lo;
118  };
119  
120  /* work request opcode (hi) */
121  #define FW_WR_OP_S	24
122  #define FW_WR_OP_M      0xff
123  #define FW_WR_OP_V(x)   ((x) << FW_WR_OP_S)
124  #define FW_WR_OP_G(x)   (((x) >> FW_WR_OP_S) & FW_WR_OP_M)
125  
126  /* atomic flag (hi) - firmware encapsulates CPLs in CPL_BARRIER */
127  #define FW_WR_ATOMIC_S		23
128  #define FW_WR_ATOMIC_V(x)	((x) << FW_WR_ATOMIC_S)
129  
130  /* flush flag (hi) - firmware flushes flushable work request buffered
131   * in the flow context.
132   */
133  #define FW_WR_FLUSH_S     22
134  #define FW_WR_FLUSH_V(x)  ((x) << FW_WR_FLUSH_S)
135  
136  /* completion flag (hi) - firmware generates a cpl_fw6_ack */
137  #define FW_WR_COMPL_S     21
138  #define FW_WR_COMPL_V(x)  ((x) << FW_WR_COMPL_S)
139  #define FW_WR_COMPL_F     FW_WR_COMPL_V(1U)
140  
141  /* work request immediate data length (hi) */
142  #define FW_WR_IMMDLEN_S 0
143  #define FW_WR_IMMDLEN_M 0xff
144  #define FW_WR_IMMDLEN_V(x)      ((x) << FW_WR_IMMDLEN_S)
145  
146  /* egress queue status update to associated ingress queue entry (lo) */
147  #define FW_WR_EQUIQ_S           31
148  #define FW_WR_EQUIQ_V(x)        ((x) << FW_WR_EQUIQ_S)
149  #define FW_WR_EQUIQ_F           FW_WR_EQUIQ_V(1U)
150  
151  /* egress queue status update to egress queue status entry (lo) */
152  #define FW_WR_EQUEQ_S           30
153  #define FW_WR_EQUEQ_V(x)        ((x) << FW_WR_EQUEQ_S)
154  #define FW_WR_EQUEQ_F           FW_WR_EQUEQ_V(1U)
155  
156  /* flow context identifier (lo) */
157  #define FW_WR_FLOWID_S          8
158  #define FW_WR_FLOWID_V(x)       ((x) << FW_WR_FLOWID_S)
159  
160  /* length in units of 16-bytes (lo) */
161  #define FW_WR_LEN16_S           0
162  #define FW_WR_LEN16_V(x)        ((x) << FW_WR_LEN16_S)
163  
164  #define HW_TPL_FR_MT_PR_IV_P_FC         0X32B
165  #define HW_TPL_FR_MT_PR_OV_P_FC         0X327
166  
167  /* filter wr reply code in cookie in CPL_SET_TCB_RPL */
168  enum fw_filter_wr_cookie {
169  	FW_FILTER_WR_SUCCESS,
170  	FW_FILTER_WR_FLT_ADDED,
171  	FW_FILTER_WR_FLT_DELETED,
172  	FW_FILTER_WR_SMT_TBL_FULL,
173  	FW_FILTER_WR_EINVAL,
174  };
175  
176  struct fw_filter_wr {
177  	__be32 op_pkd;
178  	__be32 len16_pkd;
179  	__be64 r3;
180  	__be32 tid_to_iq;
181  	__be32 del_filter_to_l2tix;
182  	__be16 ethtype;
183  	__be16 ethtypem;
184  	__u8   frag_to_ovlan_vldm;
185  	__u8   smac_sel;
186  	__be16 rx_chan_rx_rpl_iq;
187  	__be32 maci_to_matchtypem;
188  	__u8   ptcl;
189  	__u8   ptclm;
190  	__u8   ttyp;
191  	__u8   ttypm;
192  	__be16 ivlan;
193  	__be16 ivlanm;
194  	__be16 ovlan;
195  	__be16 ovlanm;
196  	__u8   lip[16];
197  	__u8   lipm[16];
198  	__u8   fip[16];
199  	__u8   fipm[16];
200  	__be16 lp;
201  	__be16 lpm;
202  	__be16 fp;
203  	__be16 fpm;
204  	__be16 r7;
205  	__u8   sma[6];
206  };
207  
208  struct fw_filter2_wr {
209  	__be32 op_pkd;
210  	__be32 len16_pkd;
211  	__be64 r3;
212  	__be32 tid_to_iq;
213  	__be32 del_filter_to_l2tix;
214  	__be16 ethtype;
215  	__be16 ethtypem;
216  	__u8   frag_to_ovlan_vldm;
217  	__u8   smac_sel;
218  	__be16 rx_chan_rx_rpl_iq;
219  	__be32 maci_to_matchtypem;
220  	__u8   ptcl;
221  	__u8   ptclm;
222  	__u8   ttyp;
223  	__u8   ttypm;
224  	__be16 ivlan;
225  	__be16 ivlanm;
226  	__be16 ovlan;
227  	__be16 ovlanm;
228  	__u8   lip[16];
229  	__u8   lipm[16];
230  	__u8   fip[16];
231  	__u8   fipm[16];
232  	__be16 lp;
233  	__be16 lpm;
234  	__be16 fp;
235  	__be16 fpm;
236  	__be16 r7;
237  	__u8   sma[6];
238  	__be16 r8;
239  	__u8   filter_type_swapmac;
240  	__u8   natmode_to_ulp_type;
241  	__be16 newlport;
242  	__be16 newfport;
243  	__u8   newlip[16];
244  	__u8   newfip[16];
245  	__be32 natseqcheck;
246  	__be32 r9;
247  	__be64 r10;
248  	__be64 r11;
249  	__be64 r12;
250  	__be64 r13;
251  };
252  
253  #define FW_FILTER_WR_TID_S      12
254  #define FW_FILTER_WR_TID_M      0xfffff
255  #define FW_FILTER_WR_TID_V(x)   ((x) << FW_FILTER_WR_TID_S)
256  #define FW_FILTER_WR_TID_G(x)   \
257  	(((x) >> FW_FILTER_WR_TID_S) & FW_FILTER_WR_TID_M)
258  
259  #define FW_FILTER_WR_RQTYPE_S           11
260  #define FW_FILTER_WR_RQTYPE_M           0x1
261  #define FW_FILTER_WR_RQTYPE_V(x)        ((x) << FW_FILTER_WR_RQTYPE_S)
262  #define FW_FILTER_WR_RQTYPE_G(x)        \
263  	(((x) >> FW_FILTER_WR_RQTYPE_S) & FW_FILTER_WR_RQTYPE_M)
264  #define FW_FILTER_WR_RQTYPE_F   FW_FILTER_WR_RQTYPE_V(1U)
265  
266  #define FW_FILTER_WR_NOREPLY_S          10
267  #define FW_FILTER_WR_NOREPLY_M          0x1
268  #define FW_FILTER_WR_NOREPLY_V(x)       ((x) << FW_FILTER_WR_NOREPLY_S)
269  #define FW_FILTER_WR_NOREPLY_G(x)       \
270  	(((x) >> FW_FILTER_WR_NOREPLY_S) & FW_FILTER_WR_NOREPLY_M)
271  #define FW_FILTER_WR_NOREPLY_F  FW_FILTER_WR_NOREPLY_V(1U)
272  
273  #define FW_FILTER_WR_IQ_S       0
274  #define FW_FILTER_WR_IQ_M       0x3ff
275  #define FW_FILTER_WR_IQ_V(x)    ((x) << FW_FILTER_WR_IQ_S)
276  #define FW_FILTER_WR_IQ_G(x)    \
277  	(((x) >> FW_FILTER_WR_IQ_S) & FW_FILTER_WR_IQ_M)
278  
279  #define FW_FILTER_WR_DEL_FILTER_S       31
280  #define FW_FILTER_WR_DEL_FILTER_M       0x1
281  #define FW_FILTER_WR_DEL_FILTER_V(x)    ((x) << FW_FILTER_WR_DEL_FILTER_S)
282  #define FW_FILTER_WR_DEL_FILTER_G(x)    \
283  	(((x) >> FW_FILTER_WR_DEL_FILTER_S) & FW_FILTER_WR_DEL_FILTER_M)
284  #define FW_FILTER_WR_DEL_FILTER_F       FW_FILTER_WR_DEL_FILTER_V(1U)
285  
286  #define FW_FILTER_WR_RPTTID_S           25
287  #define FW_FILTER_WR_RPTTID_M           0x1
288  #define FW_FILTER_WR_RPTTID_V(x)        ((x) << FW_FILTER_WR_RPTTID_S)
289  #define FW_FILTER_WR_RPTTID_G(x)        \
290  	(((x) >> FW_FILTER_WR_RPTTID_S) & FW_FILTER_WR_RPTTID_M)
291  #define FW_FILTER_WR_RPTTID_F   FW_FILTER_WR_RPTTID_V(1U)
292  
293  #define FW_FILTER_WR_DROP_S     24
294  #define FW_FILTER_WR_DROP_M     0x1
295  #define FW_FILTER_WR_DROP_V(x)  ((x) << FW_FILTER_WR_DROP_S)
296  #define FW_FILTER_WR_DROP_G(x)  \
297  	(((x) >> FW_FILTER_WR_DROP_S) & FW_FILTER_WR_DROP_M)
298  #define FW_FILTER_WR_DROP_F     FW_FILTER_WR_DROP_V(1U)
299  
300  #define FW_FILTER_WR_DIRSTEER_S         23
301  #define FW_FILTER_WR_DIRSTEER_M         0x1
302  #define FW_FILTER_WR_DIRSTEER_V(x)      ((x) << FW_FILTER_WR_DIRSTEER_S)
303  #define FW_FILTER_WR_DIRSTEER_G(x)      \
304  	(((x) >> FW_FILTER_WR_DIRSTEER_S) & FW_FILTER_WR_DIRSTEER_M)
305  #define FW_FILTER_WR_DIRSTEER_F FW_FILTER_WR_DIRSTEER_V(1U)
306  
307  #define FW_FILTER_WR_MASKHASH_S         22
308  #define FW_FILTER_WR_MASKHASH_M         0x1
309  #define FW_FILTER_WR_MASKHASH_V(x)      ((x) << FW_FILTER_WR_MASKHASH_S)
310  #define FW_FILTER_WR_MASKHASH_G(x)      \
311  	(((x) >> FW_FILTER_WR_MASKHASH_S) & FW_FILTER_WR_MASKHASH_M)
312  #define FW_FILTER_WR_MASKHASH_F FW_FILTER_WR_MASKHASH_V(1U)
313  
314  #define FW_FILTER_WR_DIRSTEERHASH_S     21
315  #define FW_FILTER_WR_DIRSTEERHASH_M     0x1
316  #define FW_FILTER_WR_DIRSTEERHASH_V(x)  ((x) << FW_FILTER_WR_DIRSTEERHASH_S)
317  #define FW_FILTER_WR_DIRSTEERHASH_G(x)  \
318  	(((x) >> FW_FILTER_WR_DIRSTEERHASH_S) & FW_FILTER_WR_DIRSTEERHASH_M)
319  #define FW_FILTER_WR_DIRSTEERHASH_F     FW_FILTER_WR_DIRSTEERHASH_V(1U)
320  
321  #define FW_FILTER_WR_LPBK_S     20
322  #define FW_FILTER_WR_LPBK_M     0x1
323  #define FW_FILTER_WR_LPBK_V(x)  ((x) << FW_FILTER_WR_LPBK_S)
324  #define FW_FILTER_WR_LPBK_G(x)  \
325  	(((x) >> FW_FILTER_WR_LPBK_S) & FW_FILTER_WR_LPBK_M)
326  #define FW_FILTER_WR_LPBK_F     FW_FILTER_WR_LPBK_V(1U)
327  
328  #define FW_FILTER_WR_DMAC_S     19
329  #define FW_FILTER_WR_DMAC_M     0x1
330  #define FW_FILTER_WR_DMAC_V(x)  ((x) << FW_FILTER_WR_DMAC_S)
331  #define FW_FILTER_WR_DMAC_G(x)  \
332  	(((x) >> FW_FILTER_WR_DMAC_S) & FW_FILTER_WR_DMAC_M)
333  #define FW_FILTER_WR_DMAC_F     FW_FILTER_WR_DMAC_V(1U)
334  
335  #define FW_FILTER_WR_SMAC_S     18
336  #define FW_FILTER_WR_SMAC_M     0x1
337  #define FW_FILTER_WR_SMAC_V(x)  ((x) << FW_FILTER_WR_SMAC_S)
338  #define FW_FILTER_WR_SMAC_G(x)  \
339  	(((x) >> FW_FILTER_WR_SMAC_S) & FW_FILTER_WR_SMAC_M)
340  #define FW_FILTER_WR_SMAC_F     FW_FILTER_WR_SMAC_V(1U)
341  
342  #define FW_FILTER_WR_INSVLAN_S          17
343  #define FW_FILTER_WR_INSVLAN_M          0x1
344  #define FW_FILTER_WR_INSVLAN_V(x)       ((x) << FW_FILTER_WR_INSVLAN_S)
345  #define FW_FILTER_WR_INSVLAN_G(x)       \
346  	(((x) >> FW_FILTER_WR_INSVLAN_S) & FW_FILTER_WR_INSVLAN_M)
347  #define FW_FILTER_WR_INSVLAN_F  FW_FILTER_WR_INSVLAN_V(1U)
348  
349  #define FW_FILTER_WR_RMVLAN_S           16
350  #define FW_FILTER_WR_RMVLAN_M           0x1
351  #define FW_FILTER_WR_RMVLAN_V(x)        ((x) << FW_FILTER_WR_RMVLAN_S)
352  #define FW_FILTER_WR_RMVLAN_G(x)        \
353  	(((x) >> FW_FILTER_WR_RMVLAN_S) & FW_FILTER_WR_RMVLAN_M)
354  #define FW_FILTER_WR_RMVLAN_F   FW_FILTER_WR_RMVLAN_V(1U)
355  
356  #define FW_FILTER_WR_HITCNTS_S          15
357  #define FW_FILTER_WR_HITCNTS_M          0x1
358  #define FW_FILTER_WR_HITCNTS_V(x)       ((x) << FW_FILTER_WR_HITCNTS_S)
359  #define FW_FILTER_WR_HITCNTS_G(x)       \
360  	(((x) >> FW_FILTER_WR_HITCNTS_S) & FW_FILTER_WR_HITCNTS_M)
361  #define FW_FILTER_WR_HITCNTS_F  FW_FILTER_WR_HITCNTS_V(1U)
362  
363  #define FW_FILTER_WR_TXCHAN_S           13
364  #define FW_FILTER_WR_TXCHAN_M           0x3
365  #define FW_FILTER_WR_TXCHAN_V(x)        ((x) << FW_FILTER_WR_TXCHAN_S)
366  #define FW_FILTER_WR_TXCHAN_G(x)        \
367  	(((x) >> FW_FILTER_WR_TXCHAN_S) & FW_FILTER_WR_TXCHAN_M)
368  
369  #define FW_FILTER_WR_PRIO_S     12
370  #define FW_FILTER_WR_PRIO_M     0x1
371  #define FW_FILTER_WR_PRIO_V(x)  ((x) << FW_FILTER_WR_PRIO_S)
372  #define FW_FILTER_WR_PRIO_G(x)  \
373  	(((x) >> FW_FILTER_WR_PRIO_S) & FW_FILTER_WR_PRIO_M)
374  #define FW_FILTER_WR_PRIO_F     FW_FILTER_WR_PRIO_V(1U)
375  
376  #define FW_FILTER_WR_L2TIX_S    0
377  #define FW_FILTER_WR_L2TIX_M    0xfff
378  #define FW_FILTER_WR_L2TIX_V(x) ((x) << FW_FILTER_WR_L2TIX_S)
379  #define FW_FILTER_WR_L2TIX_G(x) \
380  	(((x) >> FW_FILTER_WR_L2TIX_S) & FW_FILTER_WR_L2TIX_M)
381  
382  #define FW_FILTER_WR_FRAG_S     7
383  #define FW_FILTER_WR_FRAG_M     0x1
384  #define FW_FILTER_WR_FRAG_V(x)  ((x) << FW_FILTER_WR_FRAG_S)
385  #define FW_FILTER_WR_FRAG_G(x)  \
386  	(((x) >> FW_FILTER_WR_FRAG_S) & FW_FILTER_WR_FRAG_M)
387  #define FW_FILTER_WR_FRAG_F     FW_FILTER_WR_FRAG_V(1U)
388  
389  #define FW_FILTER_WR_FRAGM_S    6
390  #define FW_FILTER_WR_FRAGM_M    0x1
391  #define FW_FILTER_WR_FRAGM_V(x) ((x) << FW_FILTER_WR_FRAGM_S)
392  #define FW_FILTER_WR_FRAGM_G(x) \
393  	(((x) >> FW_FILTER_WR_FRAGM_S) & FW_FILTER_WR_FRAGM_M)
394  #define FW_FILTER_WR_FRAGM_F    FW_FILTER_WR_FRAGM_V(1U)
395  
396  #define FW_FILTER_WR_IVLAN_VLD_S        5
397  #define FW_FILTER_WR_IVLAN_VLD_M        0x1
398  #define FW_FILTER_WR_IVLAN_VLD_V(x)     ((x) << FW_FILTER_WR_IVLAN_VLD_S)
399  #define FW_FILTER_WR_IVLAN_VLD_G(x)     \
400  	(((x) >> FW_FILTER_WR_IVLAN_VLD_S) & FW_FILTER_WR_IVLAN_VLD_M)
401  #define FW_FILTER_WR_IVLAN_VLD_F        FW_FILTER_WR_IVLAN_VLD_V(1U)
402  
403  #define FW_FILTER_WR_OVLAN_VLD_S        4
404  #define FW_FILTER_WR_OVLAN_VLD_M        0x1
405  #define FW_FILTER_WR_OVLAN_VLD_V(x)     ((x) << FW_FILTER_WR_OVLAN_VLD_S)
406  #define FW_FILTER_WR_OVLAN_VLD_G(x)     \
407  	(((x) >> FW_FILTER_WR_OVLAN_VLD_S) & FW_FILTER_WR_OVLAN_VLD_M)
408  #define FW_FILTER_WR_OVLAN_VLD_F        FW_FILTER_WR_OVLAN_VLD_V(1U)
409  
410  #define FW_FILTER_WR_IVLAN_VLDM_S       3
411  #define FW_FILTER_WR_IVLAN_VLDM_M       0x1
412  #define FW_FILTER_WR_IVLAN_VLDM_V(x)    ((x) << FW_FILTER_WR_IVLAN_VLDM_S)
413  #define FW_FILTER_WR_IVLAN_VLDM_G(x)    \
414  	(((x) >> FW_FILTER_WR_IVLAN_VLDM_S) & FW_FILTER_WR_IVLAN_VLDM_M)
415  #define FW_FILTER_WR_IVLAN_VLDM_F       FW_FILTER_WR_IVLAN_VLDM_V(1U)
416  
417  #define FW_FILTER_WR_OVLAN_VLDM_S       2
418  #define FW_FILTER_WR_OVLAN_VLDM_M       0x1
419  #define FW_FILTER_WR_OVLAN_VLDM_V(x)    ((x) << FW_FILTER_WR_OVLAN_VLDM_S)
420  #define FW_FILTER_WR_OVLAN_VLDM_G(x)    \
421  	(((x) >> FW_FILTER_WR_OVLAN_VLDM_S) & FW_FILTER_WR_OVLAN_VLDM_M)
422  #define FW_FILTER_WR_OVLAN_VLDM_F       FW_FILTER_WR_OVLAN_VLDM_V(1U)
423  
424  #define FW_FILTER_WR_RX_CHAN_S          15
425  #define FW_FILTER_WR_RX_CHAN_M          0x1
426  #define FW_FILTER_WR_RX_CHAN_V(x)       ((x) << FW_FILTER_WR_RX_CHAN_S)
427  #define FW_FILTER_WR_RX_CHAN_G(x)       \
428  	(((x) >> FW_FILTER_WR_RX_CHAN_S) & FW_FILTER_WR_RX_CHAN_M)
429  #define FW_FILTER_WR_RX_CHAN_F  FW_FILTER_WR_RX_CHAN_V(1U)
430  
431  #define FW_FILTER_WR_RX_RPL_IQ_S        0
432  #define FW_FILTER_WR_RX_RPL_IQ_M        0x3ff
433  #define FW_FILTER_WR_RX_RPL_IQ_V(x)     ((x) << FW_FILTER_WR_RX_RPL_IQ_S)
434  #define FW_FILTER_WR_RX_RPL_IQ_G(x)     \
435  	(((x) >> FW_FILTER_WR_RX_RPL_IQ_S) & FW_FILTER_WR_RX_RPL_IQ_M)
436  
437  #define FW_FILTER2_WR_FILTER_TYPE_S	1
438  #define FW_FILTER2_WR_FILTER_TYPE_M	0x1
439  #define FW_FILTER2_WR_FILTER_TYPE_V(x)	((x) << FW_FILTER2_WR_FILTER_TYPE_S)
440  #define FW_FILTER2_WR_FILTER_TYPE_G(x)  \
441  	(((x) >> FW_FILTER2_WR_FILTER_TYPE_S) & FW_FILTER2_WR_FILTER_TYPE_M)
442  #define FW_FILTER2_WR_FILTER_TYPE_F	FW_FILTER2_WR_FILTER_TYPE_V(1U)
443  
444  #define FW_FILTER2_WR_NATMODE_S		5
445  #define FW_FILTER2_WR_NATMODE_M		0x7
446  #define FW_FILTER2_WR_NATMODE_V(x)	((x) << FW_FILTER2_WR_NATMODE_S)
447  #define FW_FILTER2_WR_NATMODE_G(x)      \
448  	(((x) >> FW_FILTER2_WR_NATMODE_S) & FW_FILTER2_WR_NATMODE_M)
449  
450  #define FW_FILTER2_WR_NATFLAGCHECK_S	4
451  #define FW_FILTER2_WR_NATFLAGCHECK_M	0x1
452  #define FW_FILTER2_WR_NATFLAGCHECK_V(x)	((x) << FW_FILTER2_WR_NATFLAGCHECK_S)
453  #define FW_FILTER2_WR_NATFLAGCHECK_G(x) \
454  	(((x) >> FW_FILTER2_WR_NATFLAGCHECK_S) & FW_FILTER2_WR_NATFLAGCHECK_M)
455  #define FW_FILTER2_WR_NATFLAGCHECK_F	FW_FILTER2_WR_NATFLAGCHECK_V(1U)
456  
457  #define FW_FILTER2_WR_ULP_TYPE_S	0
458  #define FW_FILTER2_WR_ULP_TYPE_M	0xf
459  #define FW_FILTER2_WR_ULP_TYPE_V(x)	((x) << FW_FILTER2_WR_ULP_TYPE_S)
460  #define FW_FILTER2_WR_ULP_TYPE_G(x)     \
461  	(((x) >> FW_FILTER2_WR_ULP_TYPE_S) & FW_FILTER2_WR_ULP_TYPE_M)
462  
463  #define FW_FILTER_WR_MACI_S     23
464  #define FW_FILTER_WR_MACI_M     0x1ff
465  #define FW_FILTER_WR_MACI_V(x)  ((x) << FW_FILTER_WR_MACI_S)
466  #define FW_FILTER_WR_MACI_G(x)  \
467  	(((x) >> FW_FILTER_WR_MACI_S) & FW_FILTER_WR_MACI_M)
468  
469  #define FW_FILTER_WR_MACIM_S    14
470  #define FW_FILTER_WR_MACIM_M    0x1ff
471  #define FW_FILTER_WR_MACIM_V(x) ((x) << FW_FILTER_WR_MACIM_S)
472  #define FW_FILTER_WR_MACIM_G(x) \
473  	(((x) >> FW_FILTER_WR_MACIM_S) & FW_FILTER_WR_MACIM_M)
474  
475  #define FW_FILTER_WR_FCOE_S     13
476  #define FW_FILTER_WR_FCOE_M     0x1
477  #define FW_FILTER_WR_FCOE_V(x)  ((x) << FW_FILTER_WR_FCOE_S)
478  #define FW_FILTER_WR_FCOE_G(x)  \
479  	(((x) >> FW_FILTER_WR_FCOE_S) & FW_FILTER_WR_FCOE_M)
480  #define FW_FILTER_WR_FCOE_F     FW_FILTER_WR_FCOE_V(1U)
481  
482  #define FW_FILTER_WR_FCOEM_S    12
483  #define FW_FILTER_WR_FCOEM_M    0x1
484  #define FW_FILTER_WR_FCOEM_V(x) ((x) << FW_FILTER_WR_FCOEM_S)
485  #define FW_FILTER_WR_FCOEM_G(x) \
486  	(((x) >> FW_FILTER_WR_FCOEM_S) & FW_FILTER_WR_FCOEM_M)
487  #define FW_FILTER_WR_FCOEM_F    FW_FILTER_WR_FCOEM_V(1U)
488  
489  #define FW_FILTER_WR_PORT_S     9
490  #define FW_FILTER_WR_PORT_M     0x7
491  #define FW_FILTER_WR_PORT_V(x)  ((x) << FW_FILTER_WR_PORT_S)
492  #define FW_FILTER_WR_PORT_G(x)  \
493  	(((x) >> FW_FILTER_WR_PORT_S) & FW_FILTER_WR_PORT_M)
494  
495  #define FW_FILTER_WR_PORTM_S    6
496  #define FW_FILTER_WR_PORTM_M    0x7
497  #define FW_FILTER_WR_PORTM_V(x) ((x) << FW_FILTER_WR_PORTM_S)
498  #define FW_FILTER_WR_PORTM_G(x) \
499  	(((x) >> FW_FILTER_WR_PORTM_S) & FW_FILTER_WR_PORTM_M)
500  
501  #define FW_FILTER_WR_MATCHTYPE_S        3
502  #define FW_FILTER_WR_MATCHTYPE_M        0x7
503  #define FW_FILTER_WR_MATCHTYPE_V(x)     ((x) << FW_FILTER_WR_MATCHTYPE_S)
504  #define FW_FILTER_WR_MATCHTYPE_G(x)     \
505  	(((x) >> FW_FILTER_WR_MATCHTYPE_S) & FW_FILTER_WR_MATCHTYPE_M)
506  
507  #define FW_FILTER_WR_MATCHTYPEM_S       0
508  #define FW_FILTER_WR_MATCHTYPEM_M       0x7
509  #define FW_FILTER_WR_MATCHTYPEM_V(x)    ((x) << FW_FILTER_WR_MATCHTYPEM_S)
510  #define FW_FILTER_WR_MATCHTYPEM_G(x)    \
511  	(((x) >> FW_FILTER_WR_MATCHTYPEM_S) & FW_FILTER_WR_MATCHTYPEM_M)
512  
513  struct fw_ulptx_wr {
514  	__be32 op_to_compl;
515  	__be32 flowid_len16;
516  	u64 cookie;
517  };
518  
519  #define FW_ULPTX_WR_DATA_S      28
520  #define FW_ULPTX_WR_DATA_M      0x1
521  #define FW_ULPTX_WR_DATA_V(x)   ((x) << FW_ULPTX_WR_DATA_S)
522  #define FW_ULPTX_WR_DATA_G(x)   \
523  	(((x) >> FW_ULPTX_WR_DATA_S) & FW_ULPTX_WR_DATA_M)
524  #define FW_ULPTX_WR_DATA_F      FW_ULPTX_WR_DATA_V(1U)
525  
526  struct fw_tp_wr {
527  	__be32 op_to_immdlen;
528  	__be32 flowid_len16;
529  	u64 cookie;
530  };
531  
532  struct fw_eth_tx_pkt_wr {
533  	__be32 op_immdlen;
534  	__be32 equiq_to_len16;
535  	__be64 r3;
536  };
537  
538  enum fw_eth_tx_eo_type {
539  	FW_ETH_TX_EO_TYPE_UDPSEG = 0,
540  	FW_ETH_TX_EO_TYPE_TCPSEG,
541  };
542  
543  struct fw_eth_tx_eo_wr {
544  	__be32 op_immdlen;
545  	__be32 equiq_to_len16;
546  	__be64 r3;
547  	union fw_eth_tx_eo {
548  		struct fw_eth_tx_eo_udpseg {
549  			__u8   type;
550  			__u8   ethlen;
551  			__be16 iplen;
552  			__u8   udplen;
553  			__u8   rtplen;
554  			__be16 r4;
555  			__be16 mss;
556  			__be16 schedpktsize;
557  			__be32 plen;
558  		} udpseg;
559  		struct fw_eth_tx_eo_tcpseg {
560  			__u8   type;
561  			__u8   ethlen;
562  			__be16 iplen;
563  			__u8   tcplen;
564  			__u8   tsclk_tsoff;
565  			__be16 r4;
566  			__be16 mss;
567  			__be16 r5;
568  			__be32 plen;
569  		} tcpseg;
570  	} u;
571  };
572  
573  #define FW_ETH_TX_EO_WR_IMMDLEN_S	0
574  #define FW_ETH_TX_EO_WR_IMMDLEN_M	0x1ff
575  #define FW_ETH_TX_EO_WR_IMMDLEN_V(x)	((x) << FW_ETH_TX_EO_WR_IMMDLEN_S)
576  #define FW_ETH_TX_EO_WR_IMMDLEN_G(x)	\
577  	(((x) >> FW_ETH_TX_EO_WR_IMMDLEN_S) & FW_ETH_TX_EO_WR_IMMDLEN_M)
578  
579  struct fw_ofld_connection_wr {
580  	__be32 op_compl;
581  	__be32 len16_pkd;
582  	__u64  cookie;
583  	__be64 r2;
584  	__be64 r3;
585  	struct fw_ofld_connection_le {
586  		__be32 version_cpl;
587  		__be32 filter;
588  		__be32 r1;
589  		__be16 lport;
590  		__be16 pport;
591  		union fw_ofld_connection_leip {
592  			struct fw_ofld_connection_le_ipv4 {
593  				__be32 pip;
594  				__be32 lip;
595  				__be64 r0;
596  				__be64 r1;
597  				__be64 r2;
598  			} ipv4;
599  			struct fw_ofld_connection_le_ipv6 {
600  				__be64 pip_hi;
601  				__be64 pip_lo;
602  				__be64 lip_hi;
603  				__be64 lip_lo;
604  			} ipv6;
605  		} u;
606  	} le;
607  	struct fw_ofld_connection_tcb {
608  		__be32 t_state_to_astid;
609  		__be16 cplrxdataack_cplpassacceptrpl;
610  		__be16 rcv_adv;
611  		__be32 rcv_nxt;
612  		__be32 tx_max;
613  		__be64 opt0;
614  		__be32 opt2;
615  		__be32 r1;
616  		__be64 r2;
617  		__be64 r3;
618  	} tcb;
619  };
620  
621  #define FW_OFLD_CONNECTION_WR_VERSION_S                31
622  #define FW_OFLD_CONNECTION_WR_VERSION_M                0x1
623  #define FW_OFLD_CONNECTION_WR_VERSION_V(x)     \
624  	((x) << FW_OFLD_CONNECTION_WR_VERSION_S)
625  #define FW_OFLD_CONNECTION_WR_VERSION_G(x)     \
626  	(((x) >> FW_OFLD_CONNECTION_WR_VERSION_S) & \
627  	FW_OFLD_CONNECTION_WR_VERSION_M)
628  #define FW_OFLD_CONNECTION_WR_VERSION_F        \
629  	FW_OFLD_CONNECTION_WR_VERSION_V(1U)
630  
631  #define FW_OFLD_CONNECTION_WR_CPL_S    30
632  #define FW_OFLD_CONNECTION_WR_CPL_M    0x1
633  #define FW_OFLD_CONNECTION_WR_CPL_V(x) ((x) << FW_OFLD_CONNECTION_WR_CPL_S)
634  #define FW_OFLD_CONNECTION_WR_CPL_G(x) \
635  	(((x) >> FW_OFLD_CONNECTION_WR_CPL_S) & FW_OFLD_CONNECTION_WR_CPL_M)
636  #define FW_OFLD_CONNECTION_WR_CPL_F    FW_OFLD_CONNECTION_WR_CPL_V(1U)
637  
638  #define FW_OFLD_CONNECTION_WR_T_STATE_S                28
639  #define FW_OFLD_CONNECTION_WR_T_STATE_M                0xf
640  #define FW_OFLD_CONNECTION_WR_T_STATE_V(x)     \
641  	((x) << FW_OFLD_CONNECTION_WR_T_STATE_S)
642  #define FW_OFLD_CONNECTION_WR_T_STATE_G(x)     \
643  	(((x) >> FW_OFLD_CONNECTION_WR_T_STATE_S) & \
644  	FW_OFLD_CONNECTION_WR_T_STATE_M)
645  
646  #define FW_OFLD_CONNECTION_WR_RCV_SCALE_S      24
647  #define FW_OFLD_CONNECTION_WR_RCV_SCALE_M      0xf
648  #define FW_OFLD_CONNECTION_WR_RCV_SCALE_V(x)   \
649  	((x) << FW_OFLD_CONNECTION_WR_RCV_SCALE_S)
650  #define FW_OFLD_CONNECTION_WR_RCV_SCALE_G(x)   \
651  	(((x) >> FW_OFLD_CONNECTION_WR_RCV_SCALE_S) & \
652  	FW_OFLD_CONNECTION_WR_RCV_SCALE_M)
653  
654  #define FW_OFLD_CONNECTION_WR_ASTID_S          0
655  #define FW_OFLD_CONNECTION_WR_ASTID_M          0xffffff
656  #define FW_OFLD_CONNECTION_WR_ASTID_V(x)       \
657  	((x) << FW_OFLD_CONNECTION_WR_ASTID_S)
658  #define FW_OFLD_CONNECTION_WR_ASTID_G(x)       \
659  	(((x) >> FW_OFLD_CONNECTION_WR_ASTID_S) & FW_OFLD_CONNECTION_WR_ASTID_M)
660  
661  #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_S   15
662  #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_M   0x1
663  #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_V(x)        \
664  	((x) << FW_OFLD_CONNECTION_WR_CPLRXDATAACK_S)
665  #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_G(x)        \
666  	(((x) >> FW_OFLD_CONNECTION_WR_CPLRXDATAACK_S) & \
667  	FW_OFLD_CONNECTION_WR_CPLRXDATAACK_M)
668  #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_F   \
669  	FW_OFLD_CONNECTION_WR_CPLRXDATAACK_V(1U)
670  
671  #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_S       14
672  #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_M       0x1
673  #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_V(x)    \
674  	((x) << FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_S)
675  #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_G(x)    \
676  	(((x) >> FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_S) & \
677  	FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_M)
678  #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_F       \
679  	FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_V(1U)
680  
681  enum fw_flowc_mnem_tcpstate {
682  	FW_FLOWC_MNEM_TCPSTATE_CLOSED   = 0, /* illegal */
683  	FW_FLOWC_MNEM_TCPSTATE_LISTEN   = 1, /* illegal */
684  	FW_FLOWC_MNEM_TCPSTATE_SYNSENT  = 2, /* illegal */
685  	FW_FLOWC_MNEM_TCPSTATE_SYNRECEIVED = 3, /* illegal */
686  	FW_FLOWC_MNEM_TCPSTATE_ESTABLISHED = 4, /* default */
687  	FW_FLOWC_MNEM_TCPSTATE_CLOSEWAIT = 5, /* got peer close already */
688  	FW_FLOWC_MNEM_TCPSTATE_FINWAIT1 = 6, /* haven't gotten ACK for FIN and
689  					      * will resend FIN - equiv ESTAB
690  					      */
691  	FW_FLOWC_MNEM_TCPSTATE_CLOSING  = 7, /* haven't gotten ACK for FIN and
692  					      * will resend FIN but have
693  					      * received FIN
694  					      */
695  	FW_FLOWC_MNEM_TCPSTATE_LASTACK  = 8, /* haven't gotten ACK for FIN and
696  					      * will resend FIN but have
697  					      * received FIN
698  					      */
699  	FW_FLOWC_MNEM_TCPSTATE_FINWAIT2 = 9, /* sent FIN and got FIN + ACK,
700  					      * waiting for FIN
701  					      */
702  	FW_FLOWC_MNEM_TCPSTATE_TIMEWAIT = 10, /* not expected */
703  };
704  
705  enum fw_flowc_mnem_eostate {
706  	FW_FLOWC_MNEM_EOSTATE_ESTABLISHED = 1, /* default */
707  	/* graceful close, after sending outstanding payload */
708  	FW_FLOWC_MNEM_EOSTATE_CLOSING = 2,
709  };
710  
711  enum fw_flowc_mnem {
712  	FW_FLOWC_MNEM_PFNVFN,		/* PFN [15:8] VFN [7:0] */
713  	FW_FLOWC_MNEM_CH,
714  	FW_FLOWC_MNEM_PORT,
715  	FW_FLOWC_MNEM_IQID,
716  	FW_FLOWC_MNEM_SNDNXT,
717  	FW_FLOWC_MNEM_RCVNXT,
718  	FW_FLOWC_MNEM_SNDBUF,
719  	FW_FLOWC_MNEM_MSS,
720  	FW_FLOWC_MNEM_TXDATAPLEN_MAX,
721  	FW_FLOWC_MNEM_TCPSTATE,
722  	FW_FLOWC_MNEM_EOSTATE,
723  	FW_FLOWC_MNEM_SCHEDCLASS,
724  	FW_FLOWC_MNEM_DCBPRIO,
725  	FW_FLOWC_MNEM_SND_SCALE,
726  	FW_FLOWC_MNEM_RCV_SCALE,
727  	FW_FLOWC_MNEM_ULD_MODE,
728  	FW_FLOWC_MNEM_MAX,
729  };
730  
731  struct fw_flowc_mnemval {
732  	u8 mnemonic;
733  	u8 r4[3];
734  	__be32 val;
735  };
736  
737  struct fw_flowc_wr {
738  	__be32 op_to_nparams;
739  	__be32 flowid_len16;
740  	struct fw_flowc_mnemval mnemval[];
741  };
742  
743  #define FW_FLOWC_WR_NPARAMS_S           0
744  #define FW_FLOWC_WR_NPARAMS_V(x)        ((x) << FW_FLOWC_WR_NPARAMS_S)
745  
746  struct fw_ofld_tx_data_wr {
747  	__be32 op_to_immdlen;
748  	__be32 flowid_len16;
749  	__be32 plen;
750  	__be32 tunnel_to_proxy;
751  };
752  
753  #define FW_OFLD_TX_DATA_WR_ALIGNPLD_S   30
754  #define FW_OFLD_TX_DATA_WR_ALIGNPLD_V(x) ((x) << FW_OFLD_TX_DATA_WR_ALIGNPLD_S)
755  #define FW_OFLD_TX_DATA_WR_ALIGNPLD_F   FW_OFLD_TX_DATA_WR_ALIGNPLD_V(1U)
756  
757  #define FW_OFLD_TX_DATA_WR_SHOVE_S      29
758  #define FW_OFLD_TX_DATA_WR_SHOVE_V(x)   ((x) << FW_OFLD_TX_DATA_WR_SHOVE_S)
759  #define FW_OFLD_TX_DATA_WR_SHOVE_F      FW_OFLD_TX_DATA_WR_SHOVE_V(1U)
760  
761  #define FW_OFLD_TX_DATA_WR_TUNNEL_S     19
762  #define FW_OFLD_TX_DATA_WR_TUNNEL_V(x)  ((x) << FW_OFLD_TX_DATA_WR_TUNNEL_S)
763  
764  #define FW_OFLD_TX_DATA_WR_SAVE_S       18
765  #define FW_OFLD_TX_DATA_WR_SAVE_V(x)    ((x) << FW_OFLD_TX_DATA_WR_SAVE_S)
766  
767  #define FW_OFLD_TX_DATA_WR_FLUSH_S      17
768  #define FW_OFLD_TX_DATA_WR_FLUSH_V(x)   ((x) << FW_OFLD_TX_DATA_WR_FLUSH_S)
769  #define FW_OFLD_TX_DATA_WR_FLUSH_F      FW_OFLD_TX_DATA_WR_FLUSH_V(1U)
770  
771  #define FW_OFLD_TX_DATA_WR_URGENT_S     16
772  #define FW_OFLD_TX_DATA_WR_URGENT_V(x)  ((x) << FW_OFLD_TX_DATA_WR_URGENT_S)
773  
774  #define FW_OFLD_TX_DATA_WR_MORE_S       15
775  #define FW_OFLD_TX_DATA_WR_MORE_V(x)    ((x) << FW_OFLD_TX_DATA_WR_MORE_S)
776  
777  #define FW_OFLD_TX_DATA_WR_ULPMODE_S    10
778  #define FW_OFLD_TX_DATA_WR_ULPMODE_V(x) ((x) << FW_OFLD_TX_DATA_WR_ULPMODE_S)
779  
780  #define FW_OFLD_TX_DATA_WR_ULPSUBMODE_S         6
781  #define FW_OFLD_TX_DATA_WR_ULPSUBMODE_V(x)      \
782  	((x) << FW_OFLD_TX_DATA_WR_ULPSUBMODE_S)
783  
784  struct fw_cmd_wr {
785  	__be32 op_dma;
786  	__be32 len16_pkd;
787  	__be64 cookie_daddr;
788  };
789  
790  #define FW_CMD_WR_DMA_S         17
791  #define FW_CMD_WR_DMA_V(x)      ((x) << FW_CMD_WR_DMA_S)
792  
793  struct fw_eth_tx_pkt_vm_wr {
794  	__be32 op_immdlen;
795  	__be32 equiq_to_len16;
796  	__be32 r3[2];
797  	struct_group(firmware,
798  		u8 ethmacdst[ETH_ALEN];
799  		u8 ethmacsrc[ETH_ALEN];
800  		__be16 ethtype;
801  		__be16 vlantci;
802  	);
803  };
804  
805  #define FW_CMD_MAX_TIMEOUT 10000
806  
807  /*
808   * If a host driver does a HELLO and discovers that there's already a MASTER
809   * selected, we may have to wait for that MASTER to finish issuing RESET,
810   * configuration and INITIALIZE commands.  Also, there's a possibility that
811   * our own HELLO may get lost if it happens right as the MASTER is issuign a
812   * RESET command, so we need to be willing to make a few retries of our HELLO.
813   */
814  #define FW_CMD_HELLO_TIMEOUT	(3 * FW_CMD_MAX_TIMEOUT)
815  #define FW_CMD_HELLO_RETRIES	3
816  
817  
818  enum fw_cmd_opcodes {
819  	FW_LDST_CMD                    = 0x01,
820  	FW_RESET_CMD                   = 0x03,
821  	FW_HELLO_CMD                   = 0x04,
822  	FW_BYE_CMD                     = 0x05,
823  	FW_INITIALIZE_CMD              = 0x06,
824  	FW_CAPS_CONFIG_CMD             = 0x07,
825  	FW_PARAMS_CMD                  = 0x08,
826  	FW_PFVF_CMD                    = 0x09,
827  	FW_IQ_CMD                      = 0x10,
828  	FW_EQ_MNGT_CMD                 = 0x11,
829  	FW_EQ_ETH_CMD                  = 0x12,
830  	FW_EQ_CTRL_CMD                 = 0x13,
831  	FW_EQ_OFLD_CMD                 = 0x21,
832  	FW_VI_CMD                      = 0x14,
833  	FW_VI_MAC_CMD                  = 0x15,
834  	FW_VI_RXMODE_CMD               = 0x16,
835  	FW_VI_ENABLE_CMD               = 0x17,
836  	FW_ACL_MAC_CMD                 = 0x18,
837  	FW_ACL_VLAN_CMD                = 0x19,
838  	FW_VI_STATS_CMD                = 0x1a,
839  	FW_PORT_CMD                    = 0x1b,
840  	FW_PORT_STATS_CMD              = 0x1c,
841  	FW_PORT_LB_STATS_CMD           = 0x1d,
842  	FW_PORT_TRACE_CMD              = 0x1e,
843  	FW_PORT_TRACE_MMAP_CMD         = 0x1f,
844  	FW_RSS_IND_TBL_CMD             = 0x20,
845  	FW_RSS_GLB_CONFIG_CMD          = 0x22,
846  	FW_RSS_VI_CONFIG_CMD           = 0x23,
847  	FW_SCHED_CMD                   = 0x24,
848  	FW_DEVLOG_CMD                  = 0x25,
849  	FW_CLIP_CMD                    = 0x28,
850  	FW_PTP_CMD                     = 0x3e,
851  	FW_HMA_CMD                     = 0x3f,
852  	FW_LASTC2E_CMD                 = 0x40,
853  	FW_ERROR_CMD                   = 0x80,
854  	FW_DEBUG_CMD                   = 0x81,
855  };
856  
857  enum fw_cmd_cap {
858  	FW_CMD_CAP_PF                  = 0x01,
859  	FW_CMD_CAP_DMAQ                = 0x02,
860  	FW_CMD_CAP_PORT                = 0x04,
861  	FW_CMD_CAP_PORTPROMISC         = 0x08,
862  	FW_CMD_CAP_PORTSTATS           = 0x10,
863  	FW_CMD_CAP_VF                  = 0x80,
864  };
865  
866  /*
867   * Generic command header flit0
868   */
869  struct fw_cmd_hdr {
870  	__be32 hi;
871  	__be32 lo;
872  };
873  
874  #define FW_CMD_OP_S             24
875  #define FW_CMD_OP_M             0xff
876  #define FW_CMD_OP_V(x)          ((x) << FW_CMD_OP_S)
877  #define FW_CMD_OP_G(x)          (((x) >> FW_CMD_OP_S) & FW_CMD_OP_M)
878  
879  #define FW_CMD_REQUEST_S        23
880  #define FW_CMD_REQUEST_V(x)     ((x) << FW_CMD_REQUEST_S)
881  #define FW_CMD_REQUEST_F        FW_CMD_REQUEST_V(1U)
882  
883  #define FW_CMD_READ_S           22
884  #define FW_CMD_READ_V(x)        ((x) << FW_CMD_READ_S)
885  #define FW_CMD_READ_F           FW_CMD_READ_V(1U)
886  
887  #define FW_CMD_WRITE_S          21
888  #define FW_CMD_WRITE_V(x)       ((x) << FW_CMD_WRITE_S)
889  #define FW_CMD_WRITE_F          FW_CMD_WRITE_V(1U)
890  
891  #define FW_CMD_EXEC_S           20
892  #define FW_CMD_EXEC_V(x)        ((x) << FW_CMD_EXEC_S)
893  #define FW_CMD_EXEC_F           FW_CMD_EXEC_V(1U)
894  
895  #define FW_CMD_RAMASK_S         20
896  #define FW_CMD_RAMASK_V(x)      ((x) << FW_CMD_RAMASK_S)
897  
898  #define FW_CMD_RETVAL_S         8
899  #define FW_CMD_RETVAL_M         0xff
900  #define FW_CMD_RETVAL_V(x)      ((x) << FW_CMD_RETVAL_S)
901  #define FW_CMD_RETVAL_G(x)      (((x) >> FW_CMD_RETVAL_S) & FW_CMD_RETVAL_M)
902  
903  #define FW_CMD_LEN16_S          0
904  #define FW_CMD_LEN16_V(x)       ((x) << FW_CMD_LEN16_S)
905  
906  #define FW_LEN16(fw_struct)	FW_CMD_LEN16_V(sizeof(fw_struct) / 16)
907  
908  enum fw_ldst_addrspc {
909  	FW_LDST_ADDRSPC_FIRMWARE  = 0x0001,
910  	FW_LDST_ADDRSPC_SGE_EGRC  = 0x0008,
911  	FW_LDST_ADDRSPC_SGE_INGC  = 0x0009,
912  	FW_LDST_ADDRSPC_SGE_FLMC  = 0x000a,
913  	FW_LDST_ADDRSPC_SGE_CONMC = 0x000b,
914  	FW_LDST_ADDRSPC_TP_PIO    = 0x0010,
915  	FW_LDST_ADDRSPC_TP_TM_PIO = 0x0011,
916  	FW_LDST_ADDRSPC_TP_MIB    = 0x0012,
917  	FW_LDST_ADDRSPC_MDIO      = 0x0018,
918  	FW_LDST_ADDRSPC_MPS       = 0x0020,
919  	FW_LDST_ADDRSPC_FUNC      = 0x0028,
920  	FW_LDST_ADDRSPC_FUNC_PCIE = 0x0029,
921  	FW_LDST_ADDRSPC_I2C       = 0x0038,
922  };
923  
924  enum fw_ldst_mps_fid {
925  	FW_LDST_MPS_ATRB,
926  	FW_LDST_MPS_RPLC
927  };
928  
929  enum fw_ldst_func_access_ctl {
930  	FW_LDST_FUNC_ACC_CTL_VIID,
931  	FW_LDST_FUNC_ACC_CTL_FID
932  };
933  
934  enum fw_ldst_func_mod_index {
935  	FW_LDST_FUNC_MPS
936  };
937  
938  struct fw_ldst_cmd {
939  	__be32 op_to_addrspace;
940  	__be32 cycles_to_len16;
941  	union fw_ldst {
942  		struct fw_ldst_addrval {
943  			__be32 addr;
944  			__be32 val;
945  		} addrval;
946  		struct fw_ldst_idctxt {
947  			__be32 physid;
948  			__be32 msg_ctxtflush;
949  			__be32 ctxt_data7;
950  			__be32 ctxt_data6;
951  			__be32 ctxt_data5;
952  			__be32 ctxt_data4;
953  			__be32 ctxt_data3;
954  			__be32 ctxt_data2;
955  			__be32 ctxt_data1;
956  			__be32 ctxt_data0;
957  		} idctxt;
958  		struct fw_ldst_mdio {
959  			__be16 paddr_mmd;
960  			__be16 raddr;
961  			__be16 vctl;
962  			__be16 rval;
963  		} mdio;
964  		struct fw_ldst_cim_rq {
965  			u8 req_first64[8];
966  			u8 req_second64[8];
967  			u8 resp_first64[8];
968  			u8 resp_second64[8];
969  			__be32 r3[2];
970  		} cim_rq;
971  		union fw_ldst_mps {
972  			struct fw_ldst_mps_rplc {
973  				__be16 fid_idx;
974  				__be16 rplcpf_pkd;
975  				__be32 rplc255_224;
976  				__be32 rplc223_192;
977  				__be32 rplc191_160;
978  				__be32 rplc159_128;
979  				__be32 rplc127_96;
980  				__be32 rplc95_64;
981  				__be32 rplc63_32;
982  				__be32 rplc31_0;
983  			} rplc;
984  			struct fw_ldst_mps_atrb {
985  				__be16 fid_mpsid;
986  				__be16 r2[3];
987  				__be32 r3[2];
988  				__be32 r4;
989  				__be32 atrb;
990  				__be16 vlan[16];
991  			} atrb;
992  		} mps;
993  		struct fw_ldst_func {
994  			u8 access_ctl;
995  			u8 mod_index;
996  			__be16 ctl_id;
997  			__be32 offset;
998  			__be64 data0;
999  			__be64 data1;
1000  		} func;
1001  		struct fw_ldst_pcie {
1002  			u8 ctrl_to_fn;
1003  			u8 bnum;
1004  			u8 r;
1005  			u8 ext_r;
1006  			u8 select_naccess;
1007  			u8 pcie_fn;
1008  			__be16 nset_pkd;
1009  			__be32 data[12];
1010  		} pcie;
1011  		struct fw_ldst_i2c_deprecated {
1012  			u8 pid_pkd;
1013  			u8 base;
1014  			u8 boffset;
1015  			u8 data;
1016  			__be32 r9;
1017  		} i2c_deprecated;
1018  		struct fw_ldst_i2c {
1019  			u8 pid;
1020  			u8 did;
1021  			u8 boffset;
1022  			u8 blen;
1023  			__be32 r9;
1024  			__u8   data[48];
1025  		} i2c;
1026  		struct fw_ldst_le {
1027  			__be32 index;
1028  			__be32 r9;
1029  			u8 val[33];
1030  			u8 r11[7];
1031  		} le;
1032  	} u;
1033  };
1034  
1035  #define FW_LDST_CMD_ADDRSPACE_S		0
1036  #define FW_LDST_CMD_ADDRSPACE_V(x)	((x) << FW_LDST_CMD_ADDRSPACE_S)
1037  
1038  #define FW_LDST_CMD_MSG_S       31
1039  #define FW_LDST_CMD_MSG_V(x)	((x) << FW_LDST_CMD_MSG_S)
1040  
1041  #define FW_LDST_CMD_CTXTFLUSH_S		30
1042  #define FW_LDST_CMD_CTXTFLUSH_V(x)	((x) << FW_LDST_CMD_CTXTFLUSH_S)
1043  #define FW_LDST_CMD_CTXTFLUSH_F		FW_LDST_CMD_CTXTFLUSH_V(1U)
1044  
1045  #define FW_LDST_CMD_PADDR_S     8
1046  #define FW_LDST_CMD_PADDR_V(x)	((x) << FW_LDST_CMD_PADDR_S)
1047  
1048  #define FW_LDST_CMD_MMD_S       0
1049  #define FW_LDST_CMD_MMD_V(x)	((x) << FW_LDST_CMD_MMD_S)
1050  
1051  #define FW_LDST_CMD_FID_S       15
1052  #define FW_LDST_CMD_FID_V(x)	((x) << FW_LDST_CMD_FID_S)
1053  
1054  #define FW_LDST_CMD_IDX_S	0
1055  #define FW_LDST_CMD_IDX_V(x)	((x) << FW_LDST_CMD_IDX_S)
1056  
1057  #define FW_LDST_CMD_RPLCPF_S    0
1058  #define FW_LDST_CMD_RPLCPF_V(x)	((x) << FW_LDST_CMD_RPLCPF_S)
1059  
1060  #define FW_LDST_CMD_LC_S        4
1061  #define FW_LDST_CMD_LC_V(x)     ((x) << FW_LDST_CMD_LC_S)
1062  #define FW_LDST_CMD_LC_F	FW_LDST_CMD_LC_V(1U)
1063  
1064  #define FW_LDST_CMD_FN_S        0
1065  #define FW_LDST_CMD_FN_V(x)	((x) << FW_LDST_CMD_FN_S)
1066  
1067  #define FW_LDST_CMD_NACCESS_S           0
1068  #define FW_LDST_CMD_NACCESS_V(x)	((x) << FW_LDST_CMD_NACCESS_S)
1069  
1070  struct fw_reset_cmd {
1071  	__be32 op_to_write;
1072  	__be32 retval_len16;
1073  	__be32 val;
1074  	__be32 halt_pkd;
1075  };
1076  
1077  #define FW_RESET_CMD_HALT_S	31
1078  #define FW_RESET_CMD_HALT_M     0x1
1079  #define FW_RESET_CMD_HALT_V(x)	((x) << FW_RESET_CMD_HALT_S)
1080  #define FW_RESET_CMD_HALT_G(x)  \
1081  	(((x) >> FW_RESET_CMD_HALT_S) & FW_RESET_CMD_HALT_M)
1082  #define FW_RESET_CMD_HALT_F	FW_RESET_CMD_HALT_V(1U)
1083  
1084  enum fw_hellow_cmd {
1085  	fw_hello_cmd_stage_os		= 0x0
1086  };
1087  
1088  struct fw_hello_cmd {
1089  	__be32 op_to_write;
1090  	__be32 retval_len16;
1091  	__be32 err_to_clearinit;
1092  	__be32 fwrev;
1093  };
1094  
1095  #define FW_HELLO_CMD_ERR_S      31
1096  #define FW_HELLO_CMD_ERR_V(x)   ((x) << FW_HELLO_CMD_ERR_S)
1097  #define FW_HELLO_CMD_ERR_F	FW_HELLO_CMD_ERR_V(1U)
1098  
1099  #define FW_HELLO_CMD_INIT_S     30
1100  #define FW_HELLO_CMD_INIT_V(x)  ((x) << FW_HELLO_CMD_INIT_S)
1101  #define FW_HELLO_CMD_INIT_F	FW_HELLO_CMD_INIT_V(1U)
1102  
1103  #define FW_HELLO_CMD_MASTERDIS_S	29
1104  #define FW_HELLO_CMD_MASTERDIS_V(x)	((x) << FW_HELLO_CMD_MASTERDIS_S)
1105  
1106  #define FW_HELLO_CMD_MASTERFORCE_S      28
1107  #define FW_HELLO_CMD_MASTERFORCE_V(x)	((x) << FW_HELLO_CMD_MASTERFORCE_S)
1108  
1109  #define FW_HELLO_CMD_MBMASTER_S		24
1110  #define FW_HELLO_CMD_MBMASTER_M		0xfU
1111  #define FW_HELLO_CMD_MBMASTER_V(x)	((x) << FW_HELLO_CMD_MBMASTER_S)
1112  #define FW_HELLO_CMD_MBMASTER_G(x)	\
1113  	(((x) >> FW_HELLO_CMD_MBMASTER_S) & FW_HELLO_CMD_MBMASTER_M)
1114  
1115  #define FW_HELLO_CMD_MBASYNCNOTINT_S    23
1116  #define FW_HELLO_CMD_MBASYNCNOTINT_V(x)	((x) << FW_HELLO_CMD_MBASYNCNOTINT_S)
1117  
1118  #define FW_HELLO_CMD_MBASYNCNOT_S       20
1119  #define FW_HELLO_CMD_MBASYNCNOT_V(x)	((x) << FW_HELLO_CMD_MBASYNCNOT_S)
1120  
1121  #define FW_HELLO_CMD_STAGE_S		17
1122  #define FW_HELLO_CMD_STAGE_V(x)		((x) << FW_HELLO_CMD_STAGE_S)
1123  
1124  #define FW_HELLO_CMD_CLEARINIT_S        16
1125  #define FW_HELLO_CMD_CLEARINIT_V(x)     ((x) << FW_HELLO_CMD_CLEARINIT_S)
1126  #define FW_HELLO_CMD_CLEARINIT_F	FW_HELLO_CMD_CLEARINIT_V(1U)
1127  
1128  struct fw_bye_cmd {
1129  	__be32 op_to_write;
1130  	__be32 retval_len16;
1131  	__be64 r3;
1132  };
1133  
1134  struct fw_initialize_cmd {
1135  	__be32 op_to_write;
1136  	__be32 retval_len16;
1137  	__be64 r3;
1138  };
1139  
1140  enum fw_caps_config_hm {
1141  	FW_CAPS_CONFIG_HM_PCIE		= 0x00000001,
1142  	FW_CAPS_CONFIG_HM_PL		= 0x00000002,
1143  	FW_CAPS_CONFIG_HM_SGE		= 0x00000004,
1144  	FW_CAPS_CONFIG_HM_CIM		= 0x00000008,
1145  	FW_CAPS_CONFIG_HM_ULPTX		= 0x00000010,
1146  	FW_CAPS_CONFIG_HM_TP		= 0x00000020,
1147  	FW_CAPS_CONFIG_HM_ULPRX		= 0x00000040,
1148  	FW_CAPS_CONFIG_HM_PMRX		= 0x00000080,
1149  	FW_CAPS_CONFIG_HM_PMTX		= 0x00000100,
1150  	FW_CAPS_CONFIG_HM_MC		= 0x00000200,
1151  	FW_CAPS_CONFIG_HM_LE		= 0x00000400,
1152  	FW_CAPS_CONFIG_HM_MPS		= 0x00000800,
1153  	FW_CAPS_CONFIG_HM_XGMAC		= 0x00001000,
1154  	FW_CAPS_CONFIG_HM_CPLSWITCH	= 0x00002000,
1155  	FW_CAPS_CONFIG_HM_T4DBG		= 0x00004000,
1156  	FW_CAPS_CONFIG_HM_MI		= 0x00008000,
1157  	FW_CAPS_CONFIG_HM_I2CM		= 0x00010000,
1158  	FW_CAPS_CONFIG_HM_NCSI		= 0x00020000,
1159  	FW_CAPS_CONFIG_HM_SMB		= 0x00040000,
1160  	FW_CAPS_CONFIG_HM_MA		= 0x00080000,
1161  	FW_CAPS_CONFIG_HM_EDRAM		= 0x00100000,
1162  	FW_CAPS_CONFIG_HM_PMU		= 0x00200000,
1163  	FW_CAPS_CONFIG_HM_UART		= 0x00400000,
1164  	FW_CAPS_CONFIG_HM_SF		= 0x00800000,
1165  };
1166  
1167  enum fw_caps_config_nbm {
1168  	FW_CAPS_CONFIG_NBM_IPMI		= 0x00000001,
1169  	FW_CAPS_CONFIG_NBM_NCSI		= 0x00000002,
1170  };
1171  
1172  enum fw_caps_config_link {
1173  	FW_CAPS_CONFIG_LINK_PPP		= 0x00000001,
1174  	FW_CAPS_CONFIG_LINK_QFC		= 0x00000002,
1175  	FW_CAPS_CONFIG_LINK_DCBX	= 0x00000004,
1176  };
1177  
1178  enum fw_caps_config_switch {
1179  	FW_CAPS_CONFIG_SWITCH_INGRESS	= 0x00000001,
1180  	FW_CAPS_CONFIG_SWITCH_EGRESS	= 0x00000002,
1181  };
1182  
1183  enum fw_caps_config_nic {
1184  	FW_CAPS_CONFIG_NIC		= 0x00000001,
1185  	FW_CAPS_CONFIG_NIC_VM		= 0x00000002,
1186  	FW_CAPS_CONFIG_NIC_HASHFILTER	= 0x00000020,
1187  	FW_CAPS_CONFIG_NIC_ETHOFLD	= 0x00000040,
1188  };
1189  
1190  enum fw_caps_config_ofld {
1191  	FW_CAPS_CONFIG_OFLD		= 0x00000001,
1192  };
1193  
1194  enum fw_caps_config_rdma {
1195  	FW_CAPS_CONFIG_RDMA_RDDP	= 0x00000001,
1196  	FW_CAPS_CONFIG_RDMA_RDMAC	= 0x00000002,
1197  };
1198  
1199  enum fw_caps_config_iscsi {
1200  	FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU = 0x00000001,
1201  	FW_CAPS_CONFIG_ISCSI_TARGET_PDU = 0x00000002,
1202  	FW_CAPS_CONFIG_ISCSI_INITIATOR_CNXOFLD = 0x00000004,
1203  	FW_CAPS_CONFIG_ISCSI_TARGET_CNXOFLD = 0x00000008,
1204  };
1205  
1206  enum fw_caps_config_crypto {
1207  	FW_CAPS_CONFIG_CRYPTO_LOOKASIDE = 0x00000001,
1208  	FW_CAPS_CONFIG_TLS_INLINE = 0x00000002,
1209  	FW_CAPS_CONFIG_IPSEC_INLINE = 0x00000004,
1210  	FW_CAPS_CONFIG_TLS_HW = 0x00000008,
1211  };
1212  
1213  enum fw_caps_config_fcoe {
1214  	FW_CAPS_CONFIG_FCOE_INITIATOR	= 0x00000001,
1215  	FW_CAPS_CONFIG_FCOE_TARGET	= 0x00000002,
1216  	FW_CAPS_CONFIG_FCOE_CTRL_OFLD	= 0x00000004,
1217  };
1218  
1219  enum fw_memtype_cf {
1220  	FW_MEMTYPE_CF_EDC0		= 0x0,
1221  	FW_MEMTYPE_CF_EDC1		= 0x1,
1222  	FW_MEMTYPE_CF_EXTMEM		= 0x2,
1223  	FW_MEMTYPE_CF_FLASH		= 0x4,
1224  	FW_MEMTYPE_CF_INTERNAL		= 0x5,
1225  	FW_MEMTYPE_CF_EXTMEM1           = 0x6,
1226  	FW_MEMTYPE_CF_HMA		= 0x7,
1227  };
1228  
1229  struct fw_caps_config_cmd {
1230  	__be32 op_to_write;
1231  	__be32 cfvalid_to_len16;
1232  	__be32 r2;
1233  	__be32 hwmbitmap;
1234  	__be16 nbmcaps;
1235  	__be16 linkcaps;
1236  	__be16 switchcaps;
1237  	__be16 r3;
1238  	__be16 niccaps;
1239  	__be16 ofldcaps;
1240  	__be16 rdmacaps;
1241  	__be16 cryptocaps;
1242  	__be16 iscsicaps;
1243  	__be16 fcoecaps;
1244  	__be32 cfcsum;
1245  	__be32 finiver;
1246  	__be32 finicsum;
1247  };
1248  
1249  #define FW_CAPS_CONFIG_CMD_CFVALID_S    27
1250  #define FW_CAPS_CONFIG_CMD_CFVALID_V(x) ((x) << FW_CAPS_CONFIG_CMD_CFVALID_S)
1251  #define FW_CAPS_CONFIG_CMD_CFVALID_F    FW_CAPS_CONFIG_CMD_CFVALID_V(1U)
1252  
1253  #define FW_CAPS_CONFIG_CMD_MEMTYPE_CF_S		24
1254  #define FW_CAPS_CONFIG_CMD_MEMTYPE_CF_V(x)	\
1255  	((x) << FW_CAPS_CONFIG_CMD_MEMTYPE_CF_S)
1256  
1257  #define FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_S      16
1258  #define FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_V(x)	\
1259  	((x) << FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_S)
1260  
1261  /*
1262   * params command mnemonics
1263   */
1264  enum fw_params_mnem {
1265  	FW_PARAMS_MNEM_DEV		= 1,	/* device params */
1266  	FW_PARAMS_MNEM_PFVF		= 2,	/* function params */
1267  	FW_PARAMS_MNEM_REG		= 3,	/* limited register access */
1268  	FW_PARAMS_MNEM_DMAQ		= 4,	/* dma queue params */
1269  	FW_PARAMS_MNEM_CHNET            = 5,    /* chnet params */
1270  	FW_PARAMS_MNEM_LAST
1271  };
1272  
1273  /*
1274   * device parameters
1275   */
1276  
1277  #define FW_PARAMS_PARAM_FILTER_MODE_S 16
1278  #define FW_PARAMS_PARAM_FILTER_MODE_M 0xffff
1279  #define FW_PARAMS_PARAM_FILTER_MODE_V(x)          \
1280  	((x) << FW_PARAMS_PARAM_FILTER_MODE_S)
1281  #define FW_PARAMS_PARAM_FILTER_MODE_G(x)          \
1282  	(((x) >> FW_PARAMS_PARAM_FILTER_MODE_S) & \
1283  	FW_PARAMS_PARAM_FILTER_MODE_M)
1284  
1285  #define FW_PARAMS_PARAM_FILTER_MASK_S 0
1286  #define FW_PARAMS_PARAM_FILTER_MASK_M 0xffff
1287  #define FW_PARAMS_PARAM_FILTER_MASK_V(x)          \
1288  	((x) << FW_PARAMS_PARAM_FILTER_MASK_S)
1289  #define FW_PARAMS_PARAM_FILTER_MASK_G(x)          \
1290  	(((x) >> FW_PARAMS_PARAM_FILTER_MASK_S) & \
1291  	FW_PARAMS_PARAM_FILTER_MASK_M)
1292  
1293  enum fw_params_param_dev {
1294  	FW_PARAMS_PARAM_DEV_CCLK	= 0x00, /* chip core clock in khz */
1295  	FW_PARAMS_PARAM_DEV_PORTVEC	= 0x01, /* the port vector */
1296  	FW_PARAMS_PARAM_DEV_NTID	= 0x02, /* reads the number of TIDs
1297  						 * allocated by the device's
1298  						 * Lookup Engine
1299  						 */
1300  	FW_PARAMS_PARAM_DEV_FLOWC_BUFFIFO_SZ = 0x03,
1301  	FW_PARAMS_PARAM_DEV_INTVER_NIC	= 0x04,
1302  	FW_PARAMS_PARAM_DEV_INTVER_VNIC = 0x05,
1303  	FW_PARAMS_PARAM_DEV_INTVER_OFLD = 0x06,
1304  	FW_PARAMS_PARAM_DEV_INTVER_RI	= 0x07,
1305  	FW_PARAMS_PARAM_DEV_INTVER_ISCSIPDU = 0x08,
1306  	FW_PARAMS_PARAM_DEV_INTVER_ISCSI = 0x09,
1307  	FW_PARAMS_PARAM_DEV_INTVER_FCOE = 0x0A,
1308  	FW_PARAMS_PARAM_DEV_FWREV = 0x0B,
1309  	FW_PARAMS_PARAM_DEV_TPREV = 0x0C,
1310  	FW_PARAMS_PARAM_DEV_CF = 0x0D,
1311  	FW_PARAMS_PARAM_DEV_PHYFW = 0x0F,
1312  	FW_PARAMS_PARAM_DEV_DIAG = 0x11,
1313  	FW_PARAMS_PARAM_DEV_MAXORDIRD_QP = 0x13, /* max supported QP IRD/ORD */
1314  	FW_PARAMS_PARAM_DEV_MAXIRD_ADAPTER = 0x14, /* max supported adap IRD */
1315  	FW_PARAMS_PARAM_DEV_ULPTX_MEMWRITE_DSGL = 0x17,
1316  	FW_PARAMS_PARAM_DEV_FWCACHE = 0x18,
1317  	FW_PARAMS_PARAM_DEV_SCFGREV = 0x1A,
1318  	FW_PARAMS_PARAM_DEV_VPDREV = 0x1B,
1319  	FW_PARAMS_PARAM_DEV_RI_FR_NSMR_TPTE_WR	= 0x1C,
1320  	FW_PARAMS_PARAM_DEV_FILTER2_WR  = 0x1D,
1321  	FW_PARAMS_PARAM_DEV_MPSBGMAP	= 0x1E,
1322  	FW_PARAMS_PARAM_DEV_TPCHMAP     = 0x1F,
1323  	FW_PARAMS_PARAM_DEV_HMA_SIZE	= 0x20,
1324  	FW_PARAMS_PARAM_DEV_RDMA_WRITE_WITH_IMM = 0x21,
1325  	FW_PARAMS_PARAM_DEV_PPOD_EDRAM  = 0x23,
1326  	FW_PARAMS_PARAM_DEV_RI_WRITE_CMPL_WR    = 0x24,
1327  	FW_PARAMS_PARAM_DEV_HPFILTER_REGION_SUPPORT = 0x26,
1328  	FW_PARAMS_PARAM_DEV_OPAQUE_VIID_SMT_EXTN = 0x27,
1329  	FW_PARAMS_PARAM_DEV_HASHFILTER_WITH_OFLD = 0x28,
1330  	FW_PARAMS_PARAM_DEV_DBQ_TIMER	= 0x29,
1331  	FW_PARAMS_PARAM_DEV_DBQ_TIMERTICK = 0x2A,
1332  	FW_PARAMS_PARAM_DEV_NUM_TM_CLASS = 0x2B,
1333  	FW_PARAMS_PARAM_DEV_FILTER = 0x2E,
1334  	FW_PARAMS_PARAM_DEV_KTLS_HW = 0x31,
1335  };
1336  
1337  /*
1338   * physical and virtual function parameters
1339   */
1340  enum fw_params_param_pfvf {
1341  	FW_PARAMS_PARAM_PFVF_RWXCAPS	= 0x00,
1342  	FW_PARAMS_PARAM_PFVF_ROUTE_START = 0x01,
1343  	FW_PARAMS_PARAM_PFVF_ROUTE_END = 0x02,
1344  	FW_PARAMS_PARAM_PFVF_CLIP_START = 0x03,
1345  	FW_PARAMS_PARAM_PFVF_CLIP_END = 0x04,
1346  	FW_PARAMS_PARAM_PFVF_FILTER_START = 0x05,
1347  	FW_PARAMS_PARAM_PFVF_FILTER_END = 0x06,
1348  	FW_PARAMS_PARAM_PFVF_SERVER_START = 0x07,
1349  	FW_PARAMS_PARAM_PFVF_SERVER_END = 0x08,
1350  	FW_PARAMS_PARAM_PFVF_TDDP_START = 0x09,
1351  	FW_PARAMS_PARAM_PFVF_TDDP_END = 0x0A,
1352  	FW_PARAMS_PARAM_PFVF_ISCSI_START = 0x0B,
1353  	FW_PARAMS_PARAM_PFVF_ISCSI_END = 0x0C,
1354  	FW_PARAMS_PARAM_PFVF_STAG_START = 0x0D,
1355  	FW_PARAMS_PARAM_PFVF_STAG_END = 0x0E,
1356  	FW_PARAMS_PARAM_PFVF_RQ_START = 0x1F,
1357  	FW_PARAMS_PARAM_PFVF_RQ_END	= 0x10,
1358  	FW_PARAMS_PARAM_PFVF_PBL_START = 0x11,
1359  	FW_PARAMS_PARAM_PFVF_PBL_END	= 0x12,
1360  	FW_PARAMS_PARAM_PFVF_L2T_START = 0x13,
1361  	FW_PARAMS_PARAM_PFVF_L2T_END = 0x14,
1362  	FW_PARAMS_PARAM_PFVF_SQRQ_START = 0x15,
1363  	FW_PARAMS_PARAM_PFVF_SQRQ_END	= 0x16,
1364  	FW_PARAMS_PARAM_PFVF_CQ_START	= 0x17,
1365  	FW_PARAMS_PARAM_PFVF_CQ_END	= 0x18,
1366  	FW_PARAMS_PARAM_PFVF_SRQ_START  = 0x19,
1367  	FW_PARAMS_PARAM_PFVF_SRQ_END    = 0x1A,
1368  	FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH = 0x20,
1369  	FW_PARAMS_PARAM_PFVF_VIID       = 0x24,
1370  	FW_PARAMS_PARAM_PFVF_CPMASK     = 0x25,
1371  	FW_PARAMS_PARAM_PFVF_OCQ_START  = 0x26,
1372  	FW_PARAMS_PARAM_PFVF_OCQ_END    = 0x27,
1373  	FW_PARAMS_PARAM_PFVF_CONM_MAP   = 0x28,
1374  	FW_PARAMS_PARAM_PFVF_IQFLINT_START = 0x29,
1375  	FW_PARAMS_PARAM_PFVF_IQFLINT_END = 0x2A,
1376  	FW_PARAMS_PARAM_PFVF_EQ_START	= 0x2B,
1377  	FW_PARAMS_PARAM_PFVF_EQ_END	= 0x2C,
1378  	FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_START = 0x2D,
1379  	FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_END = 0x2E,
1380  	FW_PARAMS_PARAM_PFVF_ETHOFLD_START = 0x2F,
1381  	FW_PARAMS_PARAM_PFVF_ETHOFLD_END = 0x30,
1382  	FW_PARAMS_PARAM_PFVF_CPLFW4MSG_ENCAP = 0x31,
1383  	FW_PARAMS_PARAM_PFVF_HPFILTER_START = 0x32,
1384  	FW_PARAMS_PARAM_PFVF_HPFILTER_END = 0x33,
1385  	FW_PARAMS_PARAM_PFVF_TLS_START = 0x34,
1386  	FW_PARAMS_PARAM_PFVF_TLS_END = 0x35,
1387  	FW_PARAMS_PARAM_PFVF_RAWF_START = 0x36,
1388  	FW_PARAMS_PARAM_PFVF_RAWF_END = 0x37,
1389  	FW_PARAMS_PARAM_PFVF_NCRYPTO_LOOKASIDE = 0x39,
1390  	FW_PARAMS_PARAM_PFVF_PORT_CAPS32 = 0x3A,
1391  	FW_PARAMS_PARAM_PFVF_PPOD_EDRAM_START = 0x3B,
1392  	FW_PARAMS_PARAM_PFVF_PPOD_EDRAM_END = 0x3C,
1393  	FW_PARAMS_PARAM_PFVF_LINK_STATE = 0x40,
1394  };
1395  
1396  /* Virtual link state as seen by the specified VF */
1397  enum vf_link_states {
1398  	FW_VF_LINK_STATE_AUTO		= 0x00,
1399  	FW_VF_LINK_STATE_ENABLE		= 0x01,
1400  	FW_VF_LINK_STATE_DISABLE	= 0x02,
1401  };
1402  
1403  /*
1404   * dma queue parameters
1405   */
1406  enum fw_params_param_dmaq {
1407  	FW_PARAMS_PARAM_DMAQ_IQ_DCAEN_DCACPU = 0x00,
1408  	FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH = 0x01,
1409  	FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_MNGT = 0x10,
1410  	FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_CTRL = 0x11,
1411  	FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH = 0x12,
1412  	FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH = 0x13,
1413  	FW_PARAMS_PARAM_DMAQ_EQ_TIMERIX	= 0x15,
1414  	FW_PARAMS_PARAM_DMAQ_CONM_CTXT = 0x20,
1415  };
1416  
1417  enum fw_params_param_dev_ktls_hw {
1418  	FW_PARAMS_PARAM_DEV_KTLS_HW_DISABLE      = 0x00,
1419  	FW_PARAMS_PARAM_DEV_KTLS_HW_ENABLE       = 0x01,
1420  	FW_PARAMS_PARAM_DEV_KTLS_HW_USER_ENABLE  = 0x01,
1421  };
1422  
1423  enum fw_params_param_dev_phyfw {
1424  	FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD = 0x00,
1425  	FW_PARAMS_PARAM_DEV_PHYFW_VERSION = 0x01,
1426  };
1427  
1428  enum fw_params_param_dev_diag {
1429  	FW_PARAM_DEV_DIAG_TMP		= 0x00,
1430  	FW_PARAM_DEV_DIAG_VDD		= 0x01,
1431  	FW_PARAM_DEV_DIAG_MAXTMPTHRESH	= 0x02,
1432  };
1433  
1434  enum fw_params_param_dev_filter {
1435  	FW_PARAM_DEV_FILTER_VNIC_MODE   = 0x00,
1436  	FW_PARAM_DEV_FILTER_MODE_MASK   = 0x01,
1437  };
1438  
1439  enum fw_params_param_dev_fwcache {
1440  	FW_PARAM_DEV_FWCACHE_FLUSH      = 0x00,
1441  	FW_PARAM_DEV_FWCACHE_FLUSHINV   = 0x01,
1442  };
1443  
1444  #define FW_PARAMS_MNEM_S	24
1445  #define FW_PARAMS_MNEM_V(x)	((x) << FW_PARAMS_MNEM_S)
1446  
1447  #define FW_PARAMS_PARAM_X_S     16
1448  #define FW_PARAMS_PARAM_X_V(x)	((x) << FW_PARAMS_PARAM_X_S)
1449  
1450  #define FW_PARAMS_PARAM_Y_S	8
1451  #define FW_PARAMS_PARAM_Y_M	0xffU
1452  #define FW_PARAMS_PARAM_Y_V(x)	((x) << FW_PARAMS_PARAM_Y_S)
1453  #define FW_PARAMS_PARAM_Y_G(x)	(((x) >> FW_PARAMS_PARAM_Y_S) &\
1454  		FW_PARAMS_PARAM_Y_M)
1455  
1456  #define FW_PARAMS_PARAM_Z_S	0
1457  #define FW_PARAMS_PARAM_Z_M	0xffu
1458  #define FW_PARAMS_PARAM_Z_V(x)	((x) << FW_PARAMS_PARAM_Z_S)
1459  #define FW_PARAMS_PARAM_Z_G(x)	(((x) >> FW_PARAMS_PARAM_Z_S) &\
1460  		FW_PARAMS_PARAM_Z_M)
1461  
1462  #define FW_PARAMS_PARAM_XYZ_S		0
1463  #define FW_PARAMS_PARAM_XYZ_V(x)	((x) << FW_PARAMS_PARAM_XYZ_S)
1464  
1465  #define FW_PARAMS_PARAM_YZ_S		0
1466  #define FW_PARAMS_PARAM_YZ_V(x)		((x) << FW_PARAMS_PARAM_YZ_S)
1467  
1468  struct fw_params_cmd {
1469  	__be32 op_to_vfn;
1470  	__be32 retval_len16;
1471  	struct fw_params_param {
1472  		__be32 mnem;
1473  		__be32 val;
1474  	} param[7];
1475  };
1476  
1477  #define FW_PARAMS_CMD_PFN_S     8
1478  #define FW_PARAMS_CMD_PFN_V(x)	((x) << FW_PARAMS_CMD_PFN_S)
1479  
1480  #define FW_PARAMS_CMD_VFN_S     0
1481  #define FW_PARAMS_CMD_VFN_V(x)	((x) << FW_PARAMS_CMD_VFN_S)
1482  
1483  struct fw_pfvf_cmd {
1484  	__be32 op_to_vfn;
1485  	__be32 retval_len16;
1486  	__be32 niqflint_niq;
1487  	__be32 type_to_neq;
1488  	__be32 tc_to_nexactf;
1489  	__be32 r_caps_to_nethctrl;
1490  	__be16 nricq;
1491  	__be16 nriqp;
1492  	__be32 r4;
1493  };
1494  
1495  #define FW_PFVF_CMD_PFN_S	8
1496  #define FW_PFVF_CMD_PFN_V(x)	((x) << FW_PFVF_CMD_PFN_S)
1497  
1498  #define FW_PFVF_CMD_VFN_S       0
1499  #define FW_PFVF_CMD_VFN_V(x)	((x) << FW_PFVF_CMD_VFN_S)
1500  
1501  #define FW_PFVF_CMD_NIQFLINT_S          20
1502  #define FW_PFVF_CMD_NIQFLINT_M          0xfff
1503  #define FW_PFVF_CMD_NIQFLINT_V(x)	((x) << FW_PFVF_CMD_NIQFLINT_S)
1504  #define FW_PFVF_CMD_NIQFLINT_G(x)	\
1505  	(((x) >> FW_PFVF_CMD_NIQFLINT_S) & FW_PFVF_CMD_NIQFLINT_M)
1506  
1507  #define FW_PFVF_CMD_NIQ_S       0
1508  #define FW_PFVF_CMD_NIQ_M       0xfffff
1509  #define FW_PFVF_CMD_NIQ_V(x)	((x) << FW_PFVF_CMD_NIQ_S)
1510  #define FW_PFVF_CMD_NIQ_G(x)	\
1511  	(((x) >> FW_PFVF_CMD_NIQ_S) & FW_PFVF_CMD_NIQ_M)
1512  
1513  #define FW_PFVF_CMD_TYPE_S      31
1514  #define FW_PFVF_CMD_TYPE_M      0x1
1515  #define FW_PFVF_CMD_TYPE_V(x)   ((x) << FW_PFVF_CMD_TYPE_S)
1516  #define FW_PFVF_CMD_TYPE_G(x)	\
1517  	(((x) >> FW_PFVF_CMD_TYPE_S) & FW_PFVF_CMD_TYPE_M)
1518  #define FW_PFVF_CMD_TYPE_F      FW_PFVF_CMD_TYPE_V(1U)
1519  
1520  #define FW_PFVF_CMD_CMASK_S     24
1521  #define FW_PFVF_CMD_CMASK_M	0xf
1522  #define FW_PFVF_CMD_CMASK_V(x)	((x) << FW_PFVF_CMD_CMASK_S)
1523  #define FW_PFVF_CMD_CMASK_G(x)	\
1524  	(((x) >> FW_PFVF_CMD_CMASK_S) & FW_PFVF_CMD_CMASK_M)
1525  
1526  #define FW_PFVF_CMD_PMASK_S     20
1527  #define FW_PFVF_CMD_PMASK_M	0xf
1528  #define FW_PFVF_CMD_PMASK_V(x)	((x) << FW_PFVF_CMD_PMASK_S)
1529  #define FW_PFVF_CMD_PMASK_G(x) \
1530  	(((x) >> FW_PFVF_CMD_PMASK_S) & FW_PFVF_CMD_PMASK_M)
1531  
1532  #define FW_PFVF_CMD_NEQ_S       0
1533  #define FW_PFVF_CMD_NEQ_M       0xfffff
1534  #define FW_PFVF_CMD_NEQ_V(x)	((x) << FW_PFVF_CMD_NEQ_S)
1535  #define FW_PFVF_CMD_NEQ_G(x)	\
1536  	(((x) >> FW_PFVF_CMD_NEQ_S) & FW_PFVF_CMD_NEQ_M)
1537  
1538  #define FW_PFVF_CMD_TC_S        24
1539  #define FW_PFVF_CMD_TC_M        0xff
1540  #define FW_PFVF_CMD_TC_V(x)	((x) << FW_PFVF_CMD_TC_S)
1541  #define FW_PFVF_CMD_TC_G(x)	(((x) >> FW_PFVF_CMD_TC_S) & FW_PFVF_CMD_TC_M)
1542  
1543  #define FW_PFVF_CMD_NVI_S       16
1544  #define FW_PFVF_CMD_NVI_M       0xff
1545  #define FW_PFVF_CMD_NVI_V(x)	((x) << FW_PFVF_CMD_NVI_S)
1546  #define FW_PFVF_CMD_NVI_G(x)	(((x) >> FW_PFVF_CMD_NVI_S) & FW_PFVF_CMD_NVI_M)
1547  
1548  #define FW_PFVF_CMD_NEXACTF_S           0
1549  #define FW_PFVF_CMD_NEXACTF_M           0xffff
1550  #define FW_PFVF_CMD_NEXACTF_V(x)	((x) << FW_PFVF_CMD_NEXACTF_S)
1551  #define FW_PFVF_CMD_NEXACTF_G(x)	\
1552  	(((x) >> FW_PFVF_CMD_NEXACTF_S) & FW_PFVF_CMD_NEXACTF_M)
1553  
1554  #define FW_PFVF_CMD_R_CAPS_S    24
1555  #define FW_PFVF_CMD_R_CAPS_M    0xff
1556  #define FW_PFVF_CMD_R_CAPS_V(x) ((x) << FW_PFVF_CMD_R_CAPS_S)
1557  #define FW_PFVF_CMD_R_CAPS_G(x) \
1558  	(((x) >> FW_PFVF_CMD_R_CAPS_S) & FW_PFVF_CMD_R_CAPS_M)
1559  
1560  #define FW_PFVF_CMD_WX_CAPS_S           16
1561  #define FW_PFVF_CMD_WX_CAPS_M           0xff
1562  #define FW_PFVF_CMD_WX_CAPS_V(x)	((x) << FW_PFVF_CMD_WX_CAPS_S)
1563  #define FW_PFVF_CMD_WX_CAPS_G(x)	\
1564  	(((x) >> FW_PFVF_CMD_WX_CAPS_S) & FW_PFVF_CMD_WX_CAPS_M)
1565  
1566  #define FW_PFVF_CMD_NETHCTRL_S          0
1567  #define FW_PFVF_CMD_NETHCTRL_M          0xffff
1568  #define FW_PFVF_CMD_NETHCTRL_V(x)	((x) << FW_PFVF_CMD_NETHCTRL_S)
1569  #define FW_PFVF_CMD_NETHCTRL_G(x)	\
1570  	(((x) >> FW_PFVF_CMD_NETHCTRL_S) & FW_PFVF_CMD_NETHCTRL_M)
1571  
1572  enum fw_iq_type {
1573  	FW_IQ_TYPE_FL_INT_CAP,
1574  	FW_IQ_TYPE_NO_FL_INT_CAP
1575  };
1576  
1577  enum fw_iq_iqtype {
1578  	FW_IQ_IQTYPE_OTHER,
1579  	FW_IQ_IQTYPE_NIC,
1580  	FW_IQ_IQTYPE_OFLD,
1581  };
1582  
1583  struct fw_iq_cmd {
1584  	__be32 op_to_vfn;
1585  	__be32 alloc_to_len16;
1586  	__be16 physiqid;
1587  	__be16 iqid;
1588  	__be16 fl0id;
1589  	__be16 fl1id;
1590  	__be32 type_to_iqandstindex;
1591  	__be16 iqdroprss_to_iqesize;
1592  	__be16 iqsize;
1593  	__be64 iqaddr;
1594  	__be32 iqns_to_fl0congen;
1595  	__be16 fl0dcaen_to_fl0cidxfthresh;
1596  	__be16 fl0size;
1597  	__be64 fl0addr;
1598  	__be32 fl1cngchmap_to_fl1congen;
1599  	__be16 fl1dcaen_to_fl1cidxfthresh;
1600  	__be16 fl1size;
1601  	__be64 fl1addr;
1602  };
1603  
1604  #define FW_IQ_CMD_PFN_S		8
1605  #define FW_IQ_CMD_PFN_V(x)	((x) << FW_IQ_CMD_PFN_S)
1606  
1607  #define FW_IQ_CMD_VFN_S		0
1608  #define FW_IQ_CMD_VFN_V(x)	((x) << FW_IQ_CMD_VFN_S)
1609  
1610  #define FW_IQ_CMD_ALLOC_S	31
1611  #define FW_IQ_CMD_ALLOC_V(x)	((x) << FW_IQ_CMD_ALLOC_S)
1612  #define FW_IQ_CMD_ALLOC_F	FW_IQ_CMD_ALLOC_V(1U)
1613  
1614  #define FW_IQ_CMD_FREE_S	30
1615  #define FW_IQ_CMD_FREE_V(x)	((x) << FW_IQ_CMD_FREE_S)
1616  #define FW_IQ_CMD_FREE_F	FW_IQ_CMD_FREE_V(1U)
1617  
1618  #define FW_IQ_CMD_MODIFY_S	29
1619  #define FW_IQ_CMD_MODIFY_V(x)	((x) << FW_IQ_CMD_MODIFY_S)
1620  #define FW_IQ_CMD_MODIFY_F	FW_IQ_CMD_MODIFY_V(1U)
1621  
1622  #define FW_IQ_CMD_IQSTART_S	28
1623  #define FW_IQ_CMD_IQSTART_V(x)	((x) << FW_IQ_CMD_IQSTART_S)
1624  #define FW_IQ_CMD_IQSTART_F	FW_IQ_CMD_IQSTART_V(1U)
1625  
1626  #define FW_IQ_CMD_IQSTOP_S	27
1627  #define FW_IQ_CMD_IQSTOP_V(x)	((x) << FW_IQ_CMD_IQSTOP_S)
1628  #define FW_IQ_CMD_IQSTOP_F	FW_IQ_CMD_IQSTOP_V(1U)
1629  
1630  #define FW_IQ_CMD_TYPE_S	29
1631  #define FW_IQ_CMD_TYPE_V(x)	((x) << FW_IQ_CMD_TYPE_S)
1632  
1633  #define FW_IQ_CMD_IQASYNCH_S	28
1634  #define FW_IQ_CMD_IQASYNCH_V(x)	((x) << FW_IQ_CMD_IQASYNCH_S)
1635  
1636  #define FW_IQ_CMD_VIID_S	16
1637  #define FW_IQ_CMD_VIID_V(x)	((x) << FW_IQ_CMD_VIID_S)
1638  
1639  #define FW_IQ_CMD_IQANDST_S	15
1640  #define FW_IQ_CMD_IQANDST_V(x)	((x) << FW_IQ_CMD_IQANDST_S)
1641  
1642  #define FW_IQ_CMD_IQANUS_S	14
1643  #define FW_IQ_CMD_IQANUS_V(x)	((x) << FW_IQ_CMD_IQANUS_S)
1644  
1645  #define FW_IQ_CMD_IQANUD_S	12
1646  #define FW_IQ_CMD_IQANUD_V(x)	((x) << FW_IQ_CMD_IQANUD_S)
1647  
1648  #define FW_IQ_CMD_IQANDSTINDEX_S	0
1649  #define FW_IQ_CMD_IQANDSTINDEX_V(x)	((x) << FW_IQ_CMD_IQANDSTINDEX_S)
1650  
1651  #define FW_IQ_CMD_IQDROPRSS_S		15
1652  #define FW_IQ_CMD_IQDROPRSS_V(x)	((x) << FW_IQ_CMD_IQDROPRSS_S)
1653  #define FW_IQ_CMD_IQDROPRSS_F	FW_IQ_CMD_IQDROPRSS_V(1U)
1654  
1655  #define FW_IQ_CMD_IQGTSMODE_S		14
1656  #define FW_IQ_CMD_IQGTSMODE_V(x)	((x) << FW_IQ_CMD_IQGTSMODE_S)
1657  #define FW_IQ_CMD_IQGTSMODE_F		FW_IQ_CMD_IQGTSMODE_V(1U)
1658  
1659  #define FW_IQ_CMD_IQPCIECH_S	12
1660  #define FW_IQ_CMD_IQPCIECH_V(x)	((x) << FW_IQ_CMD_IQPCIECH_S)
1661  
1662  #define FW_IQ_CMD_IQDCAEN_S	11
1663  #define FW_IQ_CMD_IQDCAEN_V(x)	((x) << FW_IQ_CMD_IQDCAEN_S)
1664  
1665  #define FW_IQ_CMD_IQDCACPU_S	6
1666  #define FW_IQ_CMD_IQDCACPU_V(x)	((x) << FW_IQ_CMD_IQDCACPU_S)
1667  
1668  #define FW_IQ_CMD_IQINTCNTTHRESH_S	4
1669  #define FW_IQ_CMD_IQINTCNTTHRESH_V(x)	((x) << FW_IQ_CMD_IQINTCNTTHRESH_S)
1670  
1671  #define FW_IQ_CMD_IQO_S		3
1672  #define FW_IQ_CMD_IQO_V(x)	((x) << FW_IQ_CMD_IQO_S)
1673  #define FW_IQ_CMD_IQO_F		FW_IQ_CMD_IQO_V(1U)
1674  
1675  #define FW_IQ_CMD_IQCPRIO_S	2
1676  #define FW_IQ_CMD_IQCPRIO_V(x)	((x) << FW_IQ_CMD_IQCPRIO_S)
1677  
1678  #define FW_IQ_CMD_IQESIZE_S	0
1679  #define FW_IQ_CMD_IQESIZE_V(x)	((x) << FW_IQ_CMD_IQESIZE_S)
1680  
1681  #define FW_IQ_CMD_IQNS_S	31
1682  #define FW_IQ_CMD_IQNS_V(x)	((x) << FW_IQ_CMD_IQNS_S)
1683  
1684  #define FW_IQ_CMD_IQRO_S	30
1685  #define FW_IQ_CMD_IQRO_V(x)	((x) << FW_IQ_CMD_IQRO_S)
1686  
1687  #define FW_IQ_CMD_IQFLINTIQHSEN_S	28
1688  #define FW_IQ_CMD_IQFLINTIQHSEN_V(x)	((x) << FW_IQ_CMD_IQFLINTIQHSEN_S)
1689  
1690  #define FW_IQ_CMD_IQFLINTCONGEN_S	27
1691  #define FW_IQ_CMD_IQFLINTCONGEN_V(x)	((x) << FW_IQ_CMD_IQFLINTCONGEN_S)
1692  #define FW_IQ_CMD_IQFLINTCONGEN_F	FW_IQ_CMD_IQFLINTCONGEN_V(1U)
1693  
1694  #define FW_IQ_CMD_IQFLINTISCSIC_S	26
1695  #define FW_IQ_CMD_IQFLINTISCSIC_V(x)	((x) << FW_IQ_CMD_IQFLINTISCSIC_S)
1696  
1697  #define FW_IQ_CMD_IQTYPE_S		24
1698  #define FW_IQ_CMD_IQTYPE_M		0x3
1699  #define FW_IQ_CMD_IQTYPE_V(x)		((x) << FW_IQ_CMD_IQTYPE_S)
1700  #define FW_IQ_CMD_IQTYPE_G(x)		\
1701  	(((x) >> FW_IQ_CMD_IQTYPE_S) & FW_IQ_CMD_IQTYPE_M)
1702  
1703  #define FW_IQ_CMD_FL0CNGCHMAP_S		20
1704  #define FW_IQ_CMD_FL0CNGCHMAP_V(x)	((x) << FW_IQ_CMD_FL0CNGCHMAP_S)
1705  
1706  #define FW_IQ_CMD_FL0CACHELOCK_S	15
1707  #define FW_IQ_CMD_FL0CACHELOCK_V(x)	((x) << FW_IQ_CMD_FL0CACHELOCK_S)
1708  
1709  #define FW_IQ_CMD_FL0DBP_S	14
1710  #define FW_IQ_CMD_FL0DBP_V(x)	((x) << FW_IQ_CMD_FL0DBP_S)
1711  
1712  #define FW_IQ_CMD_FL0DATANS_S		13
1713  #define FW_IQ_CMD_FL0DATANS_V(x)	((x) << FW_IQ_CMD_FL0DATANS_S)
1714  
1715  #define FW_IQ_CMD_FL0DATARO_S		12
1716  #define FW_IQ_CMD_FL0DATARO_V(x)	((x) << FW_IQ_CMD_FL0DATARO_S)
1717  #define FW_IQ_CMD_FL0DATARO_F		FW_IQ_CMD_FL0DATARO_V(1U)
1718  
1719  #define FW_IQ_CMD_FL0CONGCIF_S		11
1720  #define FW_IQ_CMD_FL0CONGCIF_V(x)	((x) << FW_IQ_CMD_FL0CONGCIF_S)
1721  #define FW_IQ_CMD_FL0CONGCIF_F		FW_IQ_CMD_FL0CONGCIF_V(1U)
1722  
1723  #define FW_IQ_CMD_FL0ONCHIP_S		10
1724  #define FW_IQ_CMD_FL0ONCHIP_V(x)	((x) << FW_IQ_CMD_FL0ONCHIP_S)
1725  
1726  #define FW_IQ_CMD_FL0STATUSPGNS_S	9
1727  #define FW_IQ_CMD_FL0STATUSPGNS_V(x)	((x) << FW_IQ_CMD_FL0STATUSPGNS_S)
1728  
1729  #define FW_IQ_CMD_FL0STATUSPGRO_S	8
1730  #define FW_IQ_CMD_FL0STATUSPGRO_V(x)	((x) << FW_IQ_CMD_FL0STATUSPGRO_S)
1731  
1732  #define FW_IQ_CMD_FL0FETCHNS_S		7
1733  #define FW_IQ_CMD_FL0FETCHNS_V(x)	((x) << FW_IQ_CMD_FL0FETCHNS_S)
1734  
1735  #define FW_IQ_CMD_FL0FETCHRO_S		6
1736  #define FW_IQ_CMD_FL0FETCHRO_V(x)	((x) << FW_IQ_CMD_FL0FETCHRO_S)
1737  #define FW_IQ_CMD_FL0FETCHRO_F		FW_IQ_CMD_FL0FETCHRO_V(1U)
1738  
1739  #define FW_IQ_CMD_FL0HOSTFCMODE_S	4
1740  #define FW_IQ_CMD_FL0HOSTFCMODE_V(x)	((x) << FW_IQ_CMD_FL0HOSTFCMODE_S)
1741  
1742  #define FW_IQ_CMD_FL0CPRIO_S	3
1743  #define FW_IQ_CMD_FL0CPRIO_V(x)	((x) << FW_IQ_CMD_FL0CPRIO_S)
1744  
1745  #define FW_IQ_CMD_FL0PADEN_S	2
1746  #define FW_IQ_CMD_FL0PADEN_V(x)	((x) << FW_IQ_CMD_FL0PADEN_S)
1747  #define FW_IQ_CMD_FL0PADEN_F	FW_IQ_CMD_FL0PADEN_V(1U)
1748  
1749  #define FW_IQ_CMD_FL0PACKEN_S		1
1750  #define FW_IQ_CMD_FL0PACKEN_V(x)	((x) << FW_IQ_CMD_FL0PACKEN_S)
1751  #define FW_IQ_CMD_FL0PACKEN_F		FW_IQ_CMD_FL0PACKEN_V(1U)
1752  
1753  #define FW_IQ_CMD_FL0CONGEN_S		0
1754  #define FW_IQ_CMD_FL0CONGEN_V(x)	((x) << FW_IQ_CMD_FL0CONGEN_S)
1755  #define FW_IQ_CMD_FL0CONGEN_F		FW_IQ_CMD_FL0CONGEN_V(1U)
1756  
1757  #define FW_IQ_CMD_FL0DCAEN_S	15
1758  #define FW_IQ_CMD_FL0DCAEN_V(x)	((x) << FW_IQ_CMD_FL0DCAEN_S)
1759  
1760  #define FW_IQ_CMD_FL0DCACPU_S		10
1761  #define FW_IQ_CMD_FL0DCACPU_V(x)	((x) << FW_IQ_CMD_FL0DCACPU_S)
1762  
1763  #define FW_IQ_CMD_FL0FBMIN_S	7
1764  #define FW_IQ_CMD_FL0FBMIN_V(x)	((x) << FW_IQ_CMD_FL0FBMIN_S)
1765  
1766  #define FW_IQ_CMD_FL0FBMAX_S	4
1767  #define FW_IQ_CMD_FL0FBMAX_V(x)	((x) << FW_IQ_CMD_FL0FBMAX_S)
1768  
1769  #define FW_IQ_CMD_FL0CIDXFTHRESHO_S	3
1770  #define FW_IQ_CMD_FL0CIDXFTHRESHO_V(x)	((x) << FW_IQ_CMD_FL0CIDXFTHRESHO_S)
1771  #define FW_IQ_CMD_FL0CIDXFTHRESHO_F	FW_IQ_CMD_FL0CIDXFTHRESHO_V(1U)
1772  
1773  #define FW_IQ_CMD_FL0CIDXFTHRESH_S	0
1774  #define FW_IQ_CMD_FL0CIDXFTHRESH_V(x)	((x) << FW_IQ_CMD_FL0CIDXFTHRESH_S)
1775  
1776  #define FW_IQ_CMD_FL1CNGCHMAP_S		20
1777  #define FW_IQ_CMD_FL1CNGCHMAP_V(x)	((x) << FW_IQ_CMD_FL1CNGCHMAP_S)
1778  
1779  #define FW_IQ_CMD_FL1CACHELOCK_S	15
1780  #define FW_IQ_CMD_FL1CACHELOCK_V(x)	((x) << FW_IQ_CMD_FL1CACHELOCK_S)
1781  
1782  #define FW_IQ_CMD_FL1DBP_S	14
1783  #define FW_IQ_CMD_FL1DBP_V(x)	((x) << FW_IQ_CMD_FL1DBP_S)
1784  
1785  #define FW_IQ_CMD_FL1DATANS_S		13
1786  #define FW_IQ_CMD_FL1DATANS_V(x)	((x) << FW_IQ_CMD_FL1DATANS_S)
1787  
1788  #define FW_IQ_CMD_FL1DATARO_S		12
1789  #define FW_IQ_CMD_FL1DATARO_V(x)	((x) << FW_IQ_CMD_FL1DATARO_S)
1790  
1791  #define FW_IQ_CMD_FL1CONGCIF_S		11
1792  #define FW_IQ_CMD_FL1CONGCIF_V(x)	((x) << FW_IQ_CMD_FL1CONGCIF_S)
1793  
1794  #define FW_IQ_CMD_FL1ONCHIP_S		10
1795  #define FW_IQ_CMD_FL1ONCHIP_V(x)	((x) << FW_IQ_CMD_FL1ONCHIP_S)
1796  
1797  #define FW_IQ_CMD_FL1STATUSPGNS_S	9
1798  #define FW_IQ_CMD_FL1STATUSPGNS_V(x)	((x) << FW_IQ_CMD_FL1STATUSPGNS_S)
1799  
1800  #define FW_IQ_CMD_FL1STATUSPGRO_S	8
1801  #define FW_IQ_CMD_FL1STATUSPGRO_V(x)	((x) << FW_IQ_CMD_FL1STATUSPGRO_S)
1802  
1803  #define FW_IQ_CMD_FL1FETCHNS_S		7
1804  #define FW_IQ_CMD_FL1FETCHNS_V(x)	((x) << FW_IQ_CMD_FL1FETCHNS_S)
1805  
1806  #define FW_IQ_CMD_FL1FETCHRO_S		6
1807  #define FW_IQ_CMD_FL1FETCHRO_V(x)	((x) << FW_IQ_CMD_FL1FETCHRO_S)
1808  
1809  #define FW_IQ_CMD_FL1HOSTFCMODE_S	4
1810  #define FW_IQ_CMD_FL1HOSTFCMODE_V(x)	((x) << FW_IQ_CMD_FL1HOSTFCMODE_S)
1811  
1812  #define FW_IQ_CMD_FL1CPRIO_S	3
1813  #define FW_IQ_CMD_FL1CPRIO_V(x)	((x) << FW_IQ_CMD_FL1CPRIO_S)
1814  
1815  #define FW_IQ_CMD_FL1PADEN_S	2
1816  #define FW_IQ_CMD_FL1PADEN_V(x)	((x) << FW_IQ_CMD_FL1PADEN_S)
1817  #define FW_IQ_CMD_FL1PADEN_F	FW_IQ_CMD_FL1PADEN_V(1U)
1818  
1819  #define FW_IQ_CMD_FL1PACKEN_S		1
1820  #define FW_IQ_CMD_FL1PACKEN_V(x)	((x) << FW_IQ_CMD_FL1PACKEN_S)
1821  #define FW_IQ_CMD_FL1PACKEN_F	FW_IQ_CMD_FL1PACKEN_V(1U)
1822  
1823  #define FW_IQ_CMD_FL1CONGEN_S		0
1824  #define FW_IQ_CMD_FL1CONGEN_V(x)	((x) << FW_IQ_CMD_FL1CONGEN_S)
1825  #define FW_IQ_CMD_FL1CONGEN_F	FW_IQ_CMD_FL1CONGEN_V(1U)
1826  
1827  #define FW_IQ_CMD_FL1DCAEN_S	15
1828  #define FW_IQ_CMD_FL1DCAEN_V(x)	((x) << FW_IQ_CMD_FL1DCAEN_S)
1829  
1830  #define FW_IQ_CMD_FL1DCACPU_S		10
1831  #define FW_IQ_CMD_FL1DCACPU_V(x)	((x) << FW_IQ_CMD_FL1DCACPU_S)
1832  
1833  #define FW_IQ_CMD_FL1FBMIN_S	7
1834  #define FW_IQ_CMD_FL1FBMIN_V(x)	((x) << FW_IQ_CMD_FL1FBMIN_S)
1835  
1836  #define FW_IQ_CMD_FL1FBMAX_S	4
1837  #define FW_IQ_CMD_FL1FBMAX_V(x)	((x) << FW_IQ_CMD_FL1FBMAX_S)
1838  
1839  #define FW_IQ_CMD_FL1CIDXFTHRESHO_S	3
1840  #define FW_IQ_CMD_FL1CIDXFTHRESHO_V(x)	((x) << FW_IQ_CMD_FL1CIDXFTHRESHO_S)
1841  #define FW_IQ_CMD_FL1CIDXFTHRESHO_F	FW_IQ_CMD_FL1CIDXFTHRESHO_V(1U)
1842  
1843  #define FW_IQ_CMD_FL1CIDXFTHRESH_S	0
1844  #define FW_IQ_CMD_FL1CIDXFTHRESH_V(x)	((x) << FW_IQ_CMD_FL1CIDXFTHRESH_S)
1845  
1846  struct fw_eq_eth_cmd {
1847  	__be32 op_to_vfn;
1848  	__be32 alloc_to_len16;
1849  	__be32 eqid_pkd;
1850  	__be32 physeqid_pkd;
1851  	__be32 fetchszm_to_iqid;
1852  	__be32 dcaen_to_eqsize;
1853  	__be64 eqaddr;
1854  	__be32 autoequiqe_to_viid;
1855  	__be32 timeren_timerix;
1856  	__be64 r9;
1857  };
1858  
1859  #define FW_EQ_ETH_CMD_PFN_S	8
1860  #define FW_EQ_ETH_CMD_PFN_V(x)	((x) << FW_EQ_ETH_CMD_PFN_S)
1861  
1862  #define FW_EQ_ETH_CMD_VFN_S	0
1863  #define FW_EQ_ETH_CMD_VFN_V(x)	((x) << FW_EQ_ETH_CMD_VFN_S)
1864  
1865  #define FW_EQ_ETH_CMD_ALLOC_S		31
1866  #define FW_EQ_ETH_CMD_ALLOC_V(x)	((x) << FW_EQ_ETH_CMD_ALLOC_S)
1867  #define FW_EQ_ETH_CMD_ALLOC_F	FW_EQ_ETH_CMD_ALLOC_V(1U)
1868  
1869  #define FW_EQ_ETH_CMD_FREE_S	30
1870  #define FW_EQ_ETH_CMD_FREE_V(x)	((x) << FW_EQ_ETH_CMD_FREE_S)
1871  #define FW_EQ_ETH_CMD_FREE_F	FW_EQ_ETH_CMD_FREE_V(1U)
1872  
1873  #define FW_EQ_ETH_CMD_MODIFY_S		29
1874  #define FW_EQ_ETH_CMD_MODIFY_V(x)	((x) << FW_EQ_ETH_CMD_MODIFY_S)
1875  #define FW_EQ_ETH_CMD_MODIFY_F	FW_EQ_ETH_CMD_MODIFY_V(1U)
1876  
1877  #define FW_EQ_ETH_CMD_EQSTART_S		28
1878  #define FW_EQ_ETH_CMD_EQSTART_V(x)	((x) << FW_EQ_ETH_CMD_EQSTART_S)
1879  #define FW_EQ_ETH_CMD_EQSTART_F	FW_EQ_ETH_CMD_EQSTART_V(1U)
1880  
1881  #define FW_EQ_ETH_CMD_EQSTOP_S		27
1882  #define FW_EQ_ETH_CMD_EQSTOP_V(x)	((x) << FW_EQ_ETH_CMD_EQSTOP_S)
1883  #define FW_EQ_ETH_CMD_EQSTOP_F	FW_EQ_ETH_CMD_EQSTOP_V(1U)
1884  
1885  #define FW_EQ_ETH_CMD_EQID_S	0
1886  #define FW_EQ_ETH_CMD_EQID_M	0xfffff
1887  #define FW_EQ_ETH_CMD_EQID_V(x)	((x) << FW_EQ_ETH_CMD_EQID_S)
1888  #define FW_EQ_ETH_CMD_EQID_G(x)	\
1889  	(((x) >> FW_EQ_ETH_CMD_EQID_S) & FW_EQ_ETH_CMD_EQID_M)
1890  
1891  #define FW_EQ_ETH_CMD_PHYSEQID_S	0
1892  #define FW_EQ_ETH_CMD_PHYSEQID_M	0xfffff
1893  #define FW_EQ_ETH_CMD_PHYSEQID_V(x)	((x) << FW_EQ_ETH_CMD_PHYSEQID_S)
1894  #define FW_EQ_ETH_CMD_PHYSEQID_G(x)	\
1895  	(((x) >> FW_EQ_ETH_CMD_PHYSEQID_S) & FW_EQ_ETH_CMD_PHYSEQID_M)
1896  
1897  #define FW_EQ_ETH_CMD_FETCHSZM_S	26
1898  #define FW_EQ_ETH_CMD_FETCHSZM_V(x)	((x) << FW_EQ_ETH_CMD_FETCHSZM_S)
1899  #define FW_EQ_ETH_CMD_FETCHSZM_F	FW_EQ_ETH_CMD_FETCHSZM_V(1U)
1900  
1901  #define FW_EQ_ETH_CMD_STATUSPGNS_S	25
1902  #define FW_EQ_ETH_CMD_STATUSPGNS_V(x)	((x) << FW_EQ_ETH_CMD_STATUSPGNS_S)
1903  
1904  #define FW_EQ_ETH_CMD_STATUSPGRO_S	24
1905  #define FW_EQ_ETH_CMD_STATUSPGRO_V(x)	((x) << FW_EQ_ETH_CMD_STATUSPGRO_S)
1906  
1907  #define FW_EQ_ETH_CMD_FETCHNS_S		23
1908  #define FW_EQ_ETH_CMD_FETCHNS_V(x)	((x) << FW_EQ_ETH_CMD_FETCHNS_S)
1909  
1910  #define FW_EQ_ETH_CMD_FETCHRO_S		22
1911  #define FW_EQ_ETH_CMD_FETCHRO_V(x)	((x) << FW_EQ_ETH_CMD_FETCHRO_S)
1912  #define FW_EQ_ETH_CMD_FETCHRO_F		FW_EQ_ETH_CMD_FETCHRO_V(1U)
1913  
1914  #define FW_EQ_ETH_CMD_HOSTFCMODE_S	20
1915  #define FW_EQ_ETH_CMD_HOSTFCMODE_V(x)	((x) << FW_EQ_ETH_CMD_HOSTFCMODE_S)
1916  
1917  #define FW_EQ_ETH_CMD_CPRIO_S		19
1918  #define FW_EQ_ETH_CMD_CPRIO_V(x)	((x) << FW_EQ_ETH_CMD_CPRIO_S)
1919  
1920  #define FW_EQ_ETH_CMD_ONCHIP_S		18
1921  #define FW_EQ_ETH_CMD_ONCHIP_V(x)	((x) << FW_EQ_ETH_CMD_ONCHIP_S)
1922  
1923  #define FW_EQ_ETH_CMD_PCIECHN_S		16
1924  #define FW_EQ_ETH_CMD_PCIECHN_V(x)	((x) << FW_EQ_ETH_CMD_PCIECHN_S)
1925  
1926  #define FW_EQ_ETH_CMD_IQID_S	0
1927  #define FW_EQ_ETH_CMD_IQID_V(x)	((x) << FW_EQ_ETH_CMD_IQID_S)
1928  
1929  #define FW_EQ_ETH_CMD_DCAEN_S		31
1930  #define FW_EQ_ETH_CMD_DCAEN_V(x)	((x) << FW_EQ_ETH_CMD_DCAEN_S)
1931  
1932  #define FW_EQ_ETH_CMD_DCACPU_S		26
1933  #define FW_EQ_ETH_CMD_DCACPU_V(x)	((x) << FW_EQ_ETH_CMD_DCACPU_S)
1934  
1935  #define FW_EQ_ETH_CMD_FBMIN_S		23
1936  #define FW_EQ_ETH_CMD_FBMIN_V(x)	((x) << FW_EQ_ETH_CMD_FBMIN_S)
1937  
1938  #define FW_EQ_ETH_CMD_FBMAX_S		20
1939  #define FW_EQ_ETH_CMD_FBMAX_V(x)	((x) << FW_EQ_ETH_CMD_FBMAX_S)
1940  
1941  #define FW_EQ_ETH_CMD_CIDXFTHRESHO_S	19
1942  #define FW_EQ_ETH_CMD_CIDXFTHRESHO_V(x)	((x) << FW_EQ_ETH_CMD_CIDXFTHRESHO_S)
1943  
1944  #define FW_EQ_ETH_CMD_CIDXFTHRESH_S	16
1945  #define FW_EQ_ETH_CMD_CIDXFTHRESH_V(x)	((x) << FW_EQ_ETH_CMD_CIDXFTHRESH_S)
1946  
1947  #define FW_EQ_ETH_CMD_EQSIZE_S		0
1948  #define FW_EQ_ETH_CMD_EQSIZE_V(x)	((x) << FW_EQ_ETH_CMD_EQSIZE_S)
1949  
1950  #define FW_EQ_ETH_CMD_AUTOEQUIQE_S	31
1951  #define FW_EQ_ETH_CMD_AUTOEQUIQE_V(x)	((x) << FW_EQ_ETH_CMD_AUTOEQUIQE_S)
1952  #define FW_EQ_ETH_CMD_AUTOEQUIQE_F	FW_EQ_ETH_CMD_AUTOEQUIQE_V(1U)
1953  
1954  #define FW_EQ_ETH_CMD_AUTOEQUEQE_S	30
1955  #define FW_EQ_ETH_CMD_AUTOEQUEQE_V(x)	((x) << FW_EQ_ETH_CMD_AUTOEQUEQE_S)
1956  #define FW_EQ_ETH_CMD_AUTOEQUEQE_F	FW_EQ_ETH_CMD_AUTOEQUEQE_V(1U)
1957  
1958  #define FW_EQ_ETH_CMD_VIID_S	16
1959  #define FW_EQ_ETH_CMD_VIID_V(x)	((x) << FW_EQ_ETH_CMD_VIID_S)
1960  
1961  #define FW_EQ_ETH_CMD_TIMEREN_S		3
1962  #define FW_EQ_ETH_CMD_TIMEREN_M		0x1
1963  #define FW_EQ_ETH_CMD_TIMEREN_V(x)	((x) << FW_EQ_ETH_CMD_TIMEREN_S)
1964  #define FW_EQ_ETH_CMD_TIMEREN_G(x)	\
1965      (((x) >> FW_EQ_ETH_CMD_TIMEREN_S) & FW_EQ_ETH_CMD_TIMEREN_M)
1966  #define FW_EQ_ETH_CMD_TIMEREN_F	FW_EQ_ETH_CMD_TIMEREN_V(1U)
1967  
1968  #define FW_EQ_ETH_CMD_TIMERIX_S		0
1969  #define FW_EQ_ETH_CMD_TIMERIX_M		0x7
1970  #define FW_EQ_ETH_CMD_TIMERIX_V(x)	((x) << FW_EQ_ETH_CMD_TIMERIX_S)
1971  #define FW_EQ_ETH_CMD_TIMERIX_G(x)	\
1972      (((x) >> FW_EQ_ETH_CMD_TIMERIX_S) & FW_EQ_ETH_CMD_TIMERIX_M)
1973  
1974  struct fw_eq_ctrl_cmd {
1975  	__be32 op_to_vfn;
1976  	__be32 alloc_to_len16;
1977  	__be32 cmpliqid_eqid;
1978  	__be32 physeqid_pkd;
1979  	__be32 fetchszm_to_iqid;
1980  	__be32 dcaen_to_eqsize;
1981  	__be64 eqaddr;
1982  };
1983  
1984  #define FW_EQ_CTRL_CMD_PFN_S	8
1985  #define FW_EQ_CTRL_CMD_PFN_V(x)	((x) << FW_EQ_CTRL_CMD_PFN_S)
1986  
1987  #define FW_EQ_CTRL_CMD_VFN_S	0
1988  #define FW_EQ_CTRL_CMD_VFN_V(x)	((x) << FW_EQ_CTRL_CMD_VFN_S)
1989  
1990  #define FW_EQ_CTRL_CMD_ALLOC_S		31
1991  #define FW_EQ_CTRL_CMD_ALLOC_V(x)	((x) << FW_EQ_CTRL_CMD_ALLOC_S)
1992  #define FW_EQ_CTRL_CMD_ALLOC_F		FW_EQ_CTRL_CMD_ALLOC_V(1U)
1993  
1994  #define FW_EQ_CTRL_CMD_FREE_S		30
1995  #define FW_EQ_CTRL_CMD_FREE_V(x)	((x) << FW_EQ_CTRL_CMD_FREE_S)
1996  #define FW_EQ_CTRL_CMD_FREE_F		FW_EQ_CTRL_CMD_FREE_V(1U)
1997  
1998  #define FW_EQ_CTRL_CMD_MODIFY_S		29
1999  #define FW_EQ_CTRL_CMD_MODIFY_V(x)	((x) << FW_EQ_CTRL_CMD_MODIFY_S)
2000  #define FW_EQ_CTRL_CMD_MODIFY_F		FW_EQ_CTRL_CMD_MODIFY_V(1U)
2001  
2002  #define FW_EQ_CTRL_CMD_EQSTART_S	28
2003  #define FW_EQ_CTRL_CMD_EQSTART_V(x)	((x) << FW_EQ_CTRL_CMD_EQSTART_S)
2004  #define FW_EQ_CTRL_CMD_EQSTART_F	FW_EQ_CTRL_CMD_EQSTART_V(1U)
2005  
2006  #define FW_EQ_CTRL_CMD_EQSTOP_S		27
2007  #define FW_EQ_CTRL_CMD_EQSTOP_V(x)	((x) << FW_EQ_CTRL_CMD_EQSTOP_S)
2008  #define FW_EQ_CTRL_CMD_EQSTOP_F		FW_EQ_CTRL_CMD_EQSTOP_V(1U)
2009  
2010  #define FW_EQ_CTRL_CMD_CMPLIQID_S	20
2011  #define FW_EQ_CTRL_CMD_CMPLIQID_V(x)	((x) << FW_EQ_CTRL_CMD_CMPLIQID_S)
2012  
2013  #define FW_EQ_CTRL_CMD_EQID_S		0
2014  #define FW_EQ_CTRL_CMD_EQID_M		0xfffff
2015  #define FW_EQ_CTRL_CMD_EQID_V(x)	((x) << FW_EQ_CTRL_CMD_EQID_S)
2016  #define FW_EQ_CTRL_CMD_EQID_G(x)	\
2017  	(((x) >> FW_EQ_CTRL_CMD_EQID_S) & FW_EQ_CTRL_CMD_EQID_M)
2018  
2019  #define FW_EQ_CTRL_CMD_PHYSEQID_S	0
2020  #define FW_EQ_CTRL_CMD_PHYSEQID_M	0xfffff
2021  #define FW_EQ_CTRL_CMD_PHYSEQID_G(x)	\
2022  	(((x) >> FW_EQ_CTRL_CMD_PHYSEQID_S) & FW_EQ_CTRL_CMD_PHYSEQID_M)
2023  
2024  #define FW_EQ_CTRL_CMD_FETCHSZM_S	26
2025  #define FW_EQ_CTRL_CMD_FETCHSZM_V(x)	((x) << FW_EQ_CTRL_CMD_FETCHSZM_S)
2026  #define FW_EQ_CTRL_CMD_FETCHSZM_F	FW_EQ_CTRL_CMD_FETCHSZM_V(1U)
2027  
2028  #define FW_EQ_CTRL_CMD_STATUSPGNS_S	25
2029  #define FW_EQ_CTRL_CMD_STATUSPGNS_V(x)	((x) << FW_EQ_CTRL_CMD_STATUSPGNS_S)
2030  #define FW_EQ_CTRL_CMD_STATUSPGNS_F	FW_EQ_CTRL_CMD_STATUSPGNS_V(1U)
2031  
2032  #define FW_EQ_CTRL_CMD_STATUSPGRO_S	24
2033  #define FW_EQ_CTRL_CMD_STATUSPGRO_V(x)	((x) << FW_EQ_CTRL_CMD_STATUSPGRO_S)
2034  #define FW_EQ_CTRL_CMD_STATUSPGRO_F	FW_EQ_CTRL_CMD_STATUSPGRO_V(1U)
2035  
2036  #define FW_EQ_CTRL_CMD_FETCHNS_S	23
2037  #define FW_EQ_CTRL_CMD_FETCHNS_V(x)	((x) << FW_EQ_CTRL_CMD_FETCHNS_S)
2038  #define FW_EQ_CTRL_CMD_FETCHNS_F	FW_EQ_CTRL_CMD_FETCHNS_V(1U)
2039  
2040  #define FW_EQ_CTRL_CMD_FETCHRO_S	22
2041  #define FW_EQ_CTRL_CMD_FETCHRO_V(x)	((x) << FW_EQ_CTRL_CMD_FETCHRO_S)
2042  #define FW_EQ_CTRL_CMD_FETCHRO_F	FW_EQ_CTRL_CMD_FETCHRO_V(1U)
2043  
2044  #define FW_EQ_CTRL_CMD_HOSTFCMODE_S	20
2045  #define FW_EQ_CTRL_CMD_HOSTFCMODE_V(x)	((x) << FW_EQ_CTRL_CMD_HOSTFCMODE_S)
2046  
2047  #define FW_EQ_CTRL_CMD_CPRIO_S		19
2048  #define FW_EQ_CTRL_CMD_CPRIO_V(x)	((x) << FW_EQ_CTRL_CMD_CPRIO_S)
2049  
2050  #define FW_EQ_CTRL_CMD_ONCHIP_S		18
2051  #define FW_EQ_CTRL_CMD_ONCHIP_V(x)	((x) << FW_EQ_CTRL_CMD_ONCHIP_S)
2052  
2053  #define FW_EQ_CTRL_CMD_PCIECHN_S	16
2054  #define FW_EQ_CTRL_CMD_PCIECHN_V(x)	((x) << FW_EQ_CTRL_CMD_PCIECHN_S)
2055  
2056  #define FW_EQ_CTRL_CMD_IQID_S		0
2057  #define FW_EQ_CTRL_CMD_IQID_V(x)	((x) << FW_EQ_CTRL_CMD_IQID_S)
2058  
2059  #define FW_EQ_CTRL_CMD_DCAEN_S		31
2060  #define FW_EQ_CTRL_CMD_DCAEN_V(x)	((x) << FW_EQ_CTRL_CMD_DCAEN_S)
2061  
2062  #define FW_EQ_CTRL_CMD_DCACPU_S		26
2063  #define FW_EQ_CTRL_CMD_DCACPU_V(x)	((x) << FW_EQ_CTRL_CMD_DCACPU_S)
2064  
2065  #define FW_EQ_CTRL_CMD_FBMIN_S		23
2066  #define FW_EQ_CTRL_CMD_FBMIN_V(x)	((x) << FW_EQ_CTRL_CMD_FBMIN_S)
2067  
2068  #define FW_EQ_CTRL_CMD_FBMAX_S		20
2069  #define FW_EQ_CTRL_CMD_FBMAX_V(x)	((x) << FW_EQ_CTRL_CMD_FBMAX_S)
2070  
2071  #define FW_EQ_CTRL_CMD_CIDXFTHRESHO_S		19
2072  #define FW_EQ_CTRL_CMD_CIDXFTHRESHO_V(x)	\
2073  	((x) << FW_EQ_CTRL_CMD_CIDXFTHRESHO_S)
2074  
2075  #define FW_EQ_CTRL_CMD_CIDXFTHRESH_S	16
2076  #define FW_EQ_CTRL_CMD_CIDXFTHRESH_V(x)	((x) << FW_EQ_CTRL_CMD_CIDXFTHRESH_S)
2077  
2078  #define FW_EQ_CTRL_CMD_EQSIZE_S		0
2079  #define FW_EQ_CTRL_CMD_EQSIZE_V(x)	((x) << FW_EQ_CTRL_CMD_EQSIZE_S)
2080  
2081  struct fw_eq_ofld_cmd {
2082  	__be32 op_to_vfn;
2083  	__be32 alloc_to_len16;
2084  	__be32 eqid_pkd;
2085  	__be32 physeqid_pkd;
2086  	__be32 fetchszm_to_iqid;
2087  	__be32 dcaen_to_eqsize;
2088  	__be64 eqaddr;
2089  };
2090  
2091  #define FW_EQ_OFLD_CMD_PFN_S	8
2092  #define FW_EQ_OFLD_CMD_PFN_V(x)	((x) << FW_EQ_OFLD_CMD_PFN_S)
2093  
2094  #define FW_EQ_OFLD_CMD_VFN_S	0
2095  #define FW_EQ_OFLD_CMD_VFN_V(x)	((x) << FW_EQ_OFLD_CMD_VFN_S)
2096  
2097  #define FW_EQ_OFLD_CMD_ALLOC_S		31
2098  #define FW_EQ_OFLD_CMD_ALLOC_V(x)	((x) << FW_EQ_OFLD_CMD_ALLOC_S)
2099  #define FW_EQ_OFLD_CMD_ALLOC_F		FW_EQ_OFLD_CMD_ALLOC_V(1U)
2100  
2101  #define FW_EQ_OFLD_CMD_FREE_S		30
2102  #define FW_EQ_OFLD_CMD_FREE_V(x)	((x) << FW_EQ_OFLD_CMD_FREE_S)
2103  #define FW_EQ_OFLD_CMD_FREE_F		FW_EQ_OFLD_CMD_FREE_V(1U)
2104  
2105  #define FW_EQ_OFLD_CMD_MODIFY_S		29
2106  #define FW_EQ_OFLD_CMD_MODIFY_V(x)	((x) << FW_EQ_OFLD_CMD_MODIFY_S)
2107  #define FW_EQ_OFLD_CMD_MODIFY_F		FW_EQ_OFLD_CMD_MODIFY_V(1U)
2108  
2109  #define FW_EQ_OFLD_CMD_EQSTART_S	28
2110  #define FW_EQ_OFLD_CMD_EQSTART_V(x)	((x) << FW_EQ_OFLD_CMD_EQSTART_S)
2111  #define FW_EQ_OFLD_CMD_EQSTART_F	FW_EQ_OFLD_CMD_EQSTART_V(1U)
2112  
2113  #define FW_EQ_OFLD_CMD_EQSTOP_S		27
2114  #define FW_EQ_OFLD_CMD_EQSTOP_V(x)	((x) << FW_EQ_OFLD_CMD_EQSTOP_S)
2115  #define FW_EQ_OFLD_CMD_EQSTOP_F		FW_EQ_OFLD_CMD_EQSTOP_V(1U)
2116  
2117  #define FW_EQ_OFLD_CMD_EQID_S		0
2118  #define FW_EQ_OFLD_CMD_EQID_M		0xfffff
2119  #define FW_EQ_OFLD_CMD_EQID_V(x)	((x) << FW_EQ_OFLD_CMD_EQID_S)
2120  #define FW_EQ_OFLD_CMD_EQID_G(x)	\
2121  	(((x) >> FW_EQ_OFLD_CMD_EQID_S) & FW_EQ_OFLD_CMD_EQID_M)
2122  
2123  #define FW_EQ_OFLD_CMD_PHYSEQID_S	0
2124  #define FW_EQ_OFLD_CMD_PHYSEQID_M	0xfffff
2125  #define FW_EQ_OFLD_CMD_PHYSEQID_G(x)	\
2126  	(((x) >> FW_EQ_OFLD_CMD_PHYSEQID_S) & FW_EQ_OFLD_CMD_PHYSEQID_M)
2127  
2128  #define FW_EQ_OFLD_CMD_FETCHSZM_S	26
2129  #define FW_EQ_OFLD_CMD_FETCHSZM_V(x)	((x) << FW_EQ_OFLD_CMD_FETCHSZM_S)
2130  
2131  #define FW_EQ_OFLD_CMD_STATUSPGNS_S	25
2132  #define FW_EQ_OFLD_CMD_STATUSPGNS_V(x)	((x) << FW_EQ_OFLD_CMD_STATUSPGNS_S)
2133  
2134  #define FW_EQ_OFLD_CMD_STATUSPGRO_S	24
2135  #define FW_EQ_OFLD_CMD_STATUSPGRO_V(x)	((x) << FW_EQ_OFLD_CMD_STATUSPGRO_S)
2136  
2137  #define FW_EQ_OFLD_CMD_FETCHNS_S	23
2138  #define FW_EQ_OFLD_CMD_FETCHNS_V(x)	((x) << FW_EQ_OFLD_CMD_FETCHNS_S)
2139  
2140  #define FW_EQ_OFLD_CMD_FETCHRO_S	22
2141  #define FW_EQ_OFLD_CMD_FETCHRO_V(x)	((x) << FW_EQ_OFLD_CMD_FETCHRO_S)
2142  #define FW_EQ_OFLD_CMD_FETCHRO_F	FW_EQ_OFLD_CMD_FETCHRO_V(1U)
2143  
2144  #define FW_EQ_OFLD_CMD_HOSTFCMODE_S	20
2145  #define FW_EQ_OFLD_CMD_HOSTFCMODE_V(x)	((x) << FW_EQ_OFLD_CMD_HOSTFCMODE_S)
2146  
2147  #define FW_EQ_OFLD_CMD_CPRIO_S		19
2148  #define FW_EQ_OFLD_CMD_CPRIO_V(x)	((x) << FW_EQ_OFLD_CMD_CPRIO_S)
2149  
2150  #define FW_EQ_OFLD_CMD_ONCHIP_S		18
2151  #define FW_EQ_OFLD_CMD_ONCHIP_V(x)	((x) << FW_EQ_OFLD_CMD_ONCHIP_S)
2152  
2153  #define FW_EQ_OFLD_CMD_PCIECHN_S	16
2154  #define FW_EQ_OFLD_CMD_PCIECHN_V(x)	((x) << FW_EQ_OFLD_CMD_PCIECHN_S)
2155  
2156  #define FW_EQ_OFLD_CMD_IQID_S		0
2157  #define FW_EQ_OFLD_CMD_IQID_V(x)	((x) << FW_EQ_OFLD_CMD_IQID_S)
2158  
2159  #define FW_EQ_OFLD_CMD_DCAEN_S		31
2160  #define FW_EQ_OFLD_CMD_DCAEN_V(x)	((x) << FW_EQ_OFLD_CMD_DCAEN_S)
2161  
2162  #define FW_EQ_OFLD_CMD_DCACPU_S		26
2163  #define FW_EQ_OFLD_CMD_DCACPU_V(x)	((x) << FW_EQ_OFLD_CMD_DCACPU_S)
2164  
2165  #define FW_EQ_OFLD_CMD_FBMIN_S		23
2166  #define FW_EQ_OFLD_CMD_FBMIN_V(x)	((x) << FW_EQ_OFLD_CMD_FBMIN_S)
2167  
2168  #define FW_EQ_OFLD_CMD_FBMAX_S		20
2169  #define FW_EQ_OFLD_CMD_FBMAX_V(x)	((x) << FW_EQ_OFLD_CMD_FBMAX_S)
2170  
2171  #define FW_EQ_OFLD_CMD_CIDXFTHRESHO_S		19
2172  #define FW_EQ_OFLD_CMD_CIDXFTHRESHO_V(x)	\
2173  	((x) << FW_EQ_OFLD_CMD_CIDXFTHRESHO_S)
2174  
2175  #define FW_EQ_OFLD_CMD_CIDXFTHRESH_S	16
2176  #define FW_EQ_OFLD_CMD_CIDXFTHRESH_V(x)	((x) << FW_EQ_OFLD_CMD_CIDXFTHRESH_S)
2177  
2178  #define FW_EQ_OFLD_CMD_EQSIZE_S		0
2179  #define FW_EQ_OFLD_CMD_EQSIZE_V(x)	((x) << FW_EQ_OFLD_CMD_EQSIZE_S)
2180  
2181  /*
2182   * Macros for VIID parsing:
2183   * VIID - [10:8] PFN, [7] VI Valid, [6:0] VI number
2184   */
2185  
2186  #define FW_VIID_PFN_S           8
2187  #define FW_VIID_PFN_M           0x7
2188  #define FW_VIID_PFN_G(x)        (((x) >> FW_VIID_PFN_S) & FW_VIID_PFN_M)
2189  
2190  #define FW_VIID_VIVLD_S		7
2191  #define FW_VIID_VIVLD_M		0x1
2192  #define FW_VIID_VIVLD_G(x)	(((x) >> FW_VIID_VIVLD_S) & FW_VIID_VIVLD_M)
2193  
2194  #define FW_VIID_VIN_S		0
2195  #define FW_VIID_VIN_M		0x7F
2196  #define FW_VIID_VIN_G(x)	(((x) >> FW_VIID_VIN_S) & FW_VIID_VIN_M)
2197  
2198  struct fw_vi_cmd {
2199  	__be32 op_to_vfn;
2200  	__be32 alloc_to_len16;
2201  	__be16 type_viid;
2202  	u8 mac[6];
2203  	u8 portid_pkd;
2204  	u8 nmac;
2205  	u8 nmac0[6];
2206  	__be16 rsssize_pkd;
2207  	u8 nmac1[6];
2208  	__be16 idsiiq_pkd;
2209  	u8 nmac2[6];
2210  	__be16 idseiq_pkd;
2211  	u8 nmac3[6];
2212  	__be64 r9;
2213  	__be64 r10;
2214  };
2215  
2216  #define FW_VI_CMD_PFN_S		8
2217  #define FW_VI_CMD_PFN_V(x)	((x) << FW_VI_CMD_PFN_S)
2218  
2219  #define FW_VI_CMD_VFN_S		0
2220  #define FW_VI_CMD_VFN_V(x)	((x) << FW_VI_CMD_VFN_S)
2221  
2222  #define FW_VI_CMD_ALLOC_S	31
2223  #define FW_VI_CMD_ALLOC_V(x)	((x) << FW_VI_CMD_ALLOC_S)
2224  #define FW_VI_CMD_ALLOC_F	FW_VI_CMD_ALLOC_V(1U)
2225  
2226  #define FW_VI_CMD_FREE_S	30
2227  #define FW_VI_CMD_FREE_V(x)	((x) << FW_VI_CMD_FREE_S)
2228  #define FW_VI_CMD_FREE_F	FW_VI_CMD_FREE_V(1U)
2229  
2230  #define FW_VI_CMD_VFVLD_S	24
2231  #define FW_VI_CMD_VFVLD_M	0x1
2232  #define FW_VI_CMD_VFVLD_V(x)	((x) << FW_VI_CMD_VFVLD_S)
2233  #define FW_VI_CMD_VFVLD_G(x)	\
2234  	(((x) >> FW_VI_CMD_VFVLD_S) & FW_VI_CMD_VFVLD_M)
2235  #define FW_VI_CMD_VFVLD_F	FW_VI_CMD_VFVLD_V(1U)
2236  
2237  #define FW_VI_CMD_VIN_S		16
2238  #define FW_VI_CMD_VIN_M		0xff
2239  #define FW_VI_CMD_VIN_V(x)	((x) << FW_VI_CMD_VIN_S)
2240  #define FW_VI_CMD_VIN_G(x)	\
2241  	(((x) >> FW_VI_CMD_VIN_S) & FW_VI_CMD_VIN_M)
2242  
2243  #define FW_VI_CMD_VIID_S	0
2244  #define FW_VI_CMD_VIID_M	0xfff
2245  #define FW_VI_CMD_VIID_V(x)	((x) << FW_VI_CMD_VIID_S)
2246  #define FW_VI_CMD_VIID_G(x)	(((x) >> FW_VI_CMD_VIID_S) & FW_VI_CMD_VIID_M)
2247  
2248  #define FW_VI_CMD_PORTID_S	4
2249  #define FW_VI_CMD_PORTID_M	0xf
2250  #define FW_VI_CMD_PORTID_V(x)	((x) << FW_VI_CMD_PORTID_S)
2251  #define FW_VI_CMD_PORTID_G(x)	\
2252  	(((x) >> FW_VI_CMD_PORTID_S) & FW_VI_CMD_PORTID_M)
2253  
2254  #define FW_VI_CMD_RSSSIZE_S	0
2255  #define FW_VI_CMD_RSSSIZE_M	0x7ff
2256  #define FW_VI_CMD_RSSSIZE_G(x)	\
2257  	(((x) >> FW_VI_CMD_RSSSIZE_S) & FW_VI_CMD_RSSSIZE_M)
2258  
2259  /* Special VI_MAC command index ids */
2260  #define FW_VI_MAC_ADD_MAC		0x3FF
2261  #define FW_VI_MAC_ADD_PERSIST_MAC	0x3FE
2262  #define FW_VI_MAC_MAC_BASED_FREE	0x3FD
2263  #define FW_VI_MAC_ID_BASED_FREE		0x3FC
2264  #define FW_CLS_TCAM_NUM_ENTRIES		336
2265  
2266  enum fw_vi_mac_smac {
2267  	FW_VI_MAC_MPS_TCAM_ENTRY,
2268  	FW_VI_MAC_MPS_TCAM_ONLY,
2269  	FW_VI_MAC_SMT_ONLY,
2270  	FW_VI_MAC_SMT_AND_MPSTCAM
2271  };
2272  
2273  enum fw_vi_mac_result {
2274  	FW_VI_MAC_R_SUCCESS,
2275  	FW_VI_MAC_R_F_NONEXISTENT_NOMEM,
2276  	FW_VI_MAC_R_SMAC_FAIL,
2277  	FW_VI_MAC_R_F_ACL_CHECK
2278  };
2279  
2280  enum fw_vi_mac_entry_types {
2281  	FW_VI_MAC_TYPE_EXACTMAC,
2282  	FW_VI_MAC_TYPE_HASHVEC,
2283  	FW_VI_MAC_TYPE_RAW,
2284  	FW_VI_MAC_TYPE_EXACTMAC_VNI,
2285  };
2286  
2287  struct fw_vi_mac_cmd {
2288  	__be32 op_to_viid;
2289  	__be32 freemacs_to_len16;
2290  	union fw_vi_mac {
2291  		struct fw_vi_mac_exact {
2292  			__be16 valid_to_idx;
2293  			u8 macaddr[6];
2294  		} exact[7];
2295  		struct fw_vi_mac_hash {
2296  			__be64 hashvec;
2297  		} hash;
2298  		struct fw_vi_mac_raw {
2299  			__be32 raw_idx_pkd;
2300  			__be32 data0_pkd;
2301  			__be32 data1[2];
2302  			__be64 data0m_pkd;
2303  			__be32 data1m[2];
2304  		} raw;
2305  		struct fw_vi_mac_vni {
2306  			__be16 valid_to_idx;
2307  			__u8 macaddr[6];
2308  			__be16 r7;
2309  			__u8 macaddr_mask[6];
2310  			__be32 lookup_type_to_vni;
2311  			__be32 vni_mask_pkd;
2312  		} exact_vni[2];
2313  	} u;
2314  };
2315  
2316  #define FW_VI_MAC_CMD_SMTID_S		12
2317  #define FW_VI_MAC_CMD_SMTID_M		0xff
2318  #define FW_VI_MAC_CMD_SMTID_V(x)	((x) << FW_VI_MAC_CMD_SMTID_S)
2319  #define FW_VI_MAC_CMD_SMTID_G(x)	\
2320  	(((x) >> FW_VI_MAC_CMD_SMTID_S) & FW_VI_MAC_CMD_SMTID_M)
2321  
2322  #define FW_VI_MAC_CMD_VIID_S	0
2323  #define FW_VI_MAC_CMD_VIID_V(x)	((x) << FW_VI_MAC_CMD_VIID_S)
2324  
2325  #define FW_VI_MAC_CMD_FREEMACS_S	31
2326  #define FW_VI_MAC_CMD_FREEMACS_V(x)	((x) << FW_VI_MAC_CMD_FREEMACS_S)
2327  
2328  #define FW_VI_MAC_CMD_ENTRY_TYPE_S      23
2329  #define FW_VI_MAC_CMD_ENTRY_TYPE_M      0x7
2330  #define FW_VI_MAC_CMD_ENTRY_TYPE_V(x)   ((x) << FW_VI_MAC_CMD_ENTRY_TYPE_S)
2331  #define FW_VI_MAC_CMD_ENTRY_TYPE_G(x)	\
2332  	(((x) >> FW_VI_MAC_CMD_ENTRY_TYPE_S) & FW_VI_MAC_CMD_ENTRY_TYPE_M)
2333  
2334  #define FW_VI_MAC_CMD_HASHVECEN_S	23
2335  #define FW_VI_MAC_CMD_HASHVECEN_V(x)	((x) << FW_VI_MAC_CMD_HASHVECEN_S)
2336  #define FW_VI_MAC_CMD_HASHVECEN_F	FW_VI_MAC_CMD_HASHVECEN_V(1U)
2337  
2338  #define FW_VI_MAC_CMD_HASHUNIEN_S	22
2339  #define FW_VI_MAC_CMD_HASHUNIEN_V(x)	((x) << FW_VI_MAC_CMD_HASHUNIEN_S)
2340  
2341  #define FW_VI_MAC_CMD_VALID_S		15
2342  #define FW_VI_MAC_CMD_VALID_V(x)	((x) << FW_VI_MAC_CMD_VALID_S)
2343  #define FW_VI_MAC_CMD_VALID_F	FW_VI_MAC_CMD_VALID_V(1U)
2344  
2345  #define FW_VI_MAC_CMD_PRIO_S	12
2346  #define FW_VI_MAC_CMD_PRIO_V(x)	((x) << FW_VI_MAC_CMD_PRIO_S)
2347  
2348  #define FW_VI_MAC_CMD_SMAC_RESULT_S	10
2349  #define FW_VI_MAC_CMD_SMAC_RESULT_M	0x3
2350  #define FW_VI_MAC_CMD_SMAC_RESULT_V(x)	((x) << FW_VI_MAC_CMD_SMAC_RESULT_S)
2351  #define FW_VI_MAC_CMD_SMAC_RESULT_G(x)	\
2352  	(((x) >> FW_VI_MAC_CMD_SMAC_RESULT_S) & FW_VI_MAC_CMD_SMAC_RESULT_M)
2353  
2354  #define FW_VI_MAC_CMD_IDX_S	0
2355  #define FW_VI_MAC_CMD_IDX_M	0x3ff
2356  #define FW_VI_MAC_CMD_IDX_V(x)	((x) << FW_VI_MAC_CMD_IDX_S)
2357  #define FW_VI_MAC_CMD_IDX_G(x)	\
2358  	(((x) >> FW_VI_MAC_CMD_IDX_S) & FW_VI_MAC_CMD_IDX_M)
2359  
2360  #define FW_VI_MAC_CMD_RAW_IDX_S         16
2361  #define FW_VI_MAC_CMD_RAW_IDX_M         0xffff
2362  #define FW_VI_MAC_CMD_RAW_IDX_V(x)      ((x) << FW_VI_MAC_CMD_RAW_IDX_S)
2363  #define FW_VI_MAC_CMD_RAW_IDX_G(x)      \
2364  	(((x) >> FW_VI_MAC_CMD_RAW_IDX_S) & FW_VI_MAC_CMD_RAW_IDX_M)
2365  
2366  #define FW_VI_MAC_CMD_LOOKUP_TYPE_S	31
2367  #define FW_VI_MAC_CMD_LOOKUP_TYPE_M	0x1
2368  #define FW_VI_MAC_CMD_LOOKUP_TYPE_V(x)	((x) << FW_VI_MAC_CMD_LOOKUP_TYPE_S)
2369  #define FW_VI_MAC_CMD_LOOKUP_TYPE_G(x)	\
2370  	(((x) >> FW_VI_MAC_CMD_LOOKUP_TYPE_S) & FW_VI_MAC_CMD_LOOKUP_TYPE_M)
2371  #define FW_VI_MAC_CMD_LOOKUP_TYPE_F	FW_VI_MAC_CMD_LOOKUP_TYPE_V(1U)
2372  
2373  #define FW_VI_MAC_CMD_DIP_HIT_S		30
2374  #define FW_VI_MAC_CMD_DIP_HIT_M		0x1
2375  #define FW_VI_MAC_CMD_DIP_HIT_V(x)	((x) << FW_VI_MAC_CMD_DIP_HIT_S)
2376  #define FW_VI_MAC_CMD_DIP_HIT_G(x)	\
2377  	(((x) >> FW_VI_MAC_CMD_DIP_HIT_S) & FW_VI_MAC_CMD_DIP_HIT_M)
2378  #define FW_VI_MAC_CMD_DIP_HIT_F		FW_VI_MAC_CMD_DIP_HIT_V(1U)
2379  
2380  #define FW_VI_MAC_CMD_VNI_S		0
2381  #define FW_VI_MAC_CMD_VNI_M		0xffffff
2382  #define FW_VI_MAC_CMD_VNI_V(x)		((x) << FW_VI_MAC_CMD_VNI_S)
2383  #define FW_VI_MAC_CMD_VNI_G(x)		\
2384  	(((x) >> FW_VI_MAC_CMD_VNI_S) & FW_VI_MAC_CMD_VNI_M)
2385  
2386  #define FW_VI_MAC_CMD_VNI_MASK_S	0
2387  #define FW_VI_MAC_CMD_VNI_MASK_M	0xffffff
2388  #define FW_VI_MAC_CMD_VNI_MASK_V(x)	((x) << FW_VI_MAC_CMD_VNI_MASK_S)
2389  #define FW_VI_MAC_CMD_VNI_MASK_G(x)	\
2390  	(((x) >> FW_VI_MAC_CMD_VNI_MASK_S) & FW_VI_MAC_CMD_VNI_MASK_M)
2391  
2392  #define FW_RXMODE_MTU_NO_CHG	65535
2393  
2394  struct fw_vi_rxmode_cmd {
2395  	__be32 op_to_viid;
2396  	__be32 retval_len16;
2397  	__be32 mtu_to_vlanexen;
2398  	__be32 r4_lo;
2399  };
2400  
2401  #define FW_VI_RXMODE_CMD_VIID_S		0
2402  #define FW_VI_RXMODE_CMD_VIID_V(x)	((x) << FW_VI_RXMODE_CMD_VIID_S)
2403  
2404  #define FW_VI_RXMODE_CMD_MTU_S		16
2405  #define FW_VI_RXMODE_CMD_MTU_M		0xffff
2406  #define FW_VI_RXMODE_CMD_MTU_V(x)	((x) << FW_VI_RXMODE_CMD_MTU_S)
2407  
2408  #define FW_VI_RXMODE_CMD_PROMISCEN_S	14
2409  #define FW_VI_RXMODE_CMD_PROMISCEN_M	0x3
2410  #define FW_VI_RXMODE_CMD_PROMISCEN_V(x)	((x) << FW_VI_RXMODE_CMD_PROMISCEN_S)
2411  
2412  #define FW_VI_RXMODE_CMD_ALLMULTIEN_S		12
2413  #define FW_VI_RXMODE_CMD_ALLMULTIEN_M		0x3
2414  #define FW_VI_RXMODE_CMD_ALLMULTIEN_V(x)	\
2415  	((x) << FW_VI_RXMODE_CMD_ALLMULTIEN_S)
2416  
2417  #define FW_VI_RXMODE_CMD_BROADCASTEN_S		10
2418  #define FW_VI_RXMODE_CMD_BROADCASTEN_M		0x3
2419  #define FW_VI_RXMODE_CMD_BROADCASTEN_V(x)	\
2420  	((x) << FW_VI_RXMODE_CMD_BROADCASTEN_S)
2421  
2422  #define FW_VI_RXMODE_CMD_VLANEXEN_S	8
2423  #define FW_VI_RXMODE_CMD_VLANEXEN_M	0x3
2424  #define FW_VI_RXMODE_CMD_VLANEXEN_V(x)	((x) << FW_VI_RXMODE_CMD_VLANEXEN_S)
2425  
2426  struct fw_vi_enable_cmd {
2427  	__be32 op_to_viid;
2428  	__be32 ien_to_len16;
2429  	__be16 blinkdur;
2430  	__be16 r3;
2431  	__be32 r4;
2432  };
2433  
2434  #define FW_VI_ENABLE_CMD_VIID_S         0
2435  #define FW_VI_ENABLE_CMD_VIID_V(x)      ((x) << FW_VI_ENABLE_CMD_VIID_S)
2436  
2437  #define FW_VI_ENABLE_CMD_IEN_S		31
2438  #define FW_VI_ENABLE_CMD_IEN_V(x)	((x) << FW_VI_ENABLE_CMD_IEN_S)
2439  
2440  #define FW_VI_ENABLE_CMD_EEN_S		30
2441  #define FW_VI_ENABLE_CMD_EEN_V(x)	((x) << FW_VI_ENABLE_CMD_EEN_S)
2442  
2443  #define FW_VI_ENABLE_CMD_LED_S		29
2444  #define FW_VI_ENABLE_CMD_LED_V(x)	((x) << FW_VI_ENABLE_CMD_LED_S)
2445  #define FW_VI_ENABLE_CMD_LED_F	FW_VI_ENABLE_CMD_LED_V(1U)
2446  
2447  #define FW_VI_ENABLE_CMD_DCB_INFO_S	28
2448  #define FW_VI_ENABLE_CMD_DCB_INFO_V(x)	((x) << FW_VI_ENABLE_CMD_DCB_INFO_S)
2449  
2450  /* VI VF stats offset definitions */
2451  #define VI_VF_NUM_STATS	16
2452  enum fw_vi_stats_vf_index {
2453  	FW_VI_VF_STAT_TX_BCAST_BYTES_IX,
2454  	FW_VI_VF_STAT_TX_BCAST_FRAMES_IX,
2455  	FW_VI_VF_STAT_TX_MCAST_BYTES_IX,
2456  	FW_VI_VF_STAT_TX_MCAST_FRAMES_IX,
2457  	FW_VI_VF_STAT_TX_UCAST_BYTES_IX,
2458  	FW_VI_VF_STAT_TX_UCAST_FRAMES_IX,
2459  	FW_VI_VF_STAT_TX_DROP_FRAMES_IX,
2460  	FW_VI_VF_STAT_TX_OFLD_BYTES_IX,
2461  	FW_VI_VF_STAT_TX_OFLD_FRAMES_IX,
2462  	FW_VI_VF_STAT_RX_BCAST_BYTES_IX,
2463  	FW_VI_VF_STAT_RX_BCAST_FRAMES_IX,
2464  	FW_VI_VF_STAT_RX_MCAST_BYTES_IX,
2465  	FW_VI_VF_STAT_RX_MCAST_FRAMES_IX,
2466  	FW_VI_VF_STAT_RX_UCAST_BYTES_IX,
2467  	FW_VI_VF_STAT_RX_UCAST_FRAMES_IX,
2468  	FW_VI_VF_STAT_RX_ERR_FRAMES_IX
2469  };
2470  
2471  /* VI PF stats offset definitions */
2472  #define VI_PF_NUM_STATS	17
2473  enum fw_vi_stats_pf_index {
2474  	FW_VI_PF_STAT_TX_BCAST_BYTES_IX,
2475  	FW_VI_PF_STAT_TX_BCAST_FRAMES_IX,
2476  	FW_VI_PF_STAT_TX_MCAST_BYTES_IX,
2477  	FW_VI_PF_STAT_TX_MCAST_FRAMES_IX,
2478  	FW_VI_PF_STAT_TX_UCAST_BYTES_IX,
2479  	FW_VI_PF_STAT_TX_UCAST_FRAMES_IX,
2480  	FW_VI_PF_STAT_TX_OFLD_BYTES_IX,
2481  	FW_VI_PF_STAT_TX_OFLD_FRAMES_IX,
2482  	FW_VI_PF_STAT_RX_BYTES_IX,
2483  	FW_VI_PF_STAT_RX_FRAMES_IX,
2484  	FW_VI_PF_STAT_RX_BCAST_BYTES_IX,
2485  	FW_VI_PF_STAT_RX_BCAST_FRAMES_IX,
2486  	FW_VI_PF_STAT_RX_MCAST_BYTES_IX,
2487  	FW_VI_PF_STAT_RX_MCAST_FRAMES_IX,
2488  	FW_VI_PF_STAT_RX_UCAST_BYTES_IX,
2489  	FW_VI_PF_STAT_RX_UCAST_FRAMES_IX,
2490  	FW_VI_PF_STAT_RX_ERR_FRAMES_IX
2491  };
2492  
2493  struct fw_vi_stats_cmd {
2494  	__be32 op_to_viid;
2495  	__be32 retval_len16;
2496  	union fw_vi_stats {
2497  		struct fw_vi_stats_ctl {
2498  			__be16 nstats_ix;
2499  			__be16 r6;
2500  			__be32 r7;
2501  			__be64 stat0;
2502  			__be64 stat1;
2503  			__be64 stat2;
2504  			__be64 stat3;
2505  			__be64 stat4;
2506  			__be64 stat5;
2507  		} ctl;
2508  		struct fw_vi_stats_pf {
2509  			__be64 tx_bcast_bytes;
2510  			__be64 tx_bcast_frames;
2511  			__be64 tx_mcast_bytes;
2512  			__be64 tx_mcast_frames;
2513  			__be64 tx_ucast_bytes;
2514  			__be64 tx_ucast_frames;
2515  			__be64 tx_offload_bytes;
2516  			__be64 tx_offload_frames;
2517  			__be64 rx_pf_bytes;
2518  			__be64 rx_pf_frames;
2519  			__be64 rx_bcast_bytes;
2520  			__be64 rx_bcast_frames;
2521  			__be64 rx_mcast_bytes;
2522  			__be64 rx_mcast_frames;
2523  			__be64 rx_ucast_bytes;
2524  			__be64 rx_ucast_frames;
2525  			__be64 rx_err_frames;
2526  		} pf;
2527  		struct fw_vi_stats_vf {
2528  			__be64 tx_bcast_bytes;
2529  			__be64 tx_bcast_frames;
2530  			__be64 tx_mcast_bytes;
2531  			__be64 tx_mcast_frames;
2532  			__be64 tx_ucast_bytes;
2533  			__be64 tx_ucast_frames;
2534  			__be64 tx_drop_frames;
2535  			__be64 tx_offload_bytes;
2536  			__be64 tx_offload_frames;
2537  			__be64 rx_bcast_bytes;
2538  			__be64 rx_bcast_frames;
2539  			__be64 rx_mcast_bytes;
2540  			__be64 rx_mcast_frames;
2541  			__be64 rx_ucast_bytes;
2542  			__be64 rx_ucast_frames;
2543  			__be64 rx_err_frames;
2544  		} vf;
2545  	} u;
2546  };
2547  
2548  #define FW_VI_STATS_CMD_VIID_S		0
2549  #define FW_VI_STATS_CMD_VIID_V(x)	((x) << FW_VI_STATS_CMD_VIID_S)
2550  
2551  #define FW_VI_STATS_CMD_NSTATS_S	12
2552  #define FW_VI_STATS_CMD_NSTATS_V(x)	((x) << FW_VI_STATS_CMD_NSTATS_S)
2553  
2554  #define FW_VI_STATS_CMD_IX_S	0
2555  #define FW_VI_STATS_CMD_IX_V(x)	((x) << FW_VI_STATS_CMD_IX_S)
2556  
2557  struct fw_acl_mac_cmd {
2558  	__be32 op_to_vfn;
2559  	__be32 en_to_len16;
2560  	u8 nmac;
2561  	u8 r3[7];
2562  	__be16 r4;
2563  	u8 macaddr0[6];
2564  	__be16 r5;
2565  	u8 macaddr1[6];
2566  	__be16 r6;
2567  	u8 macaddr2[6];
2568  	__be16 r7;
2569  	u8 macaddr3[6];
2570  };
2571  
2572  #define FW_ACL_MAC_CMD_PFN_S	8
2573  #define FW_ACL_MAC_CMD_PFN_V(x)	((x) << FW_ACL_MAC_CMD_PFN_S)
2574  
2575  #define FW_ACL_MAC_CMD_VFN_S	0
2576  #define FW_ACL_MAC_CMD_VFN_V(x)	((x) << FW_ACL_MAC_CMD_VFN_S)
2577  
2578  #define FW_ACL_MAC_CMD_EN_S	31
2579  #define FW_ACL_MAC_CMD_EN_V(x)	((x) << FW_ACL_MAC_CMD_EN_S)
2580  
2581  struct fw_acl_vlan_cmd {
2582  	__be32 op_to_vfn;
2583  	__be32 en_to_len16;
2584  	u8 nvlan;
2585  	u8 dropnovlan_fm;
2586  	u8 r3_lo[6];
2587  	__be16 vlanid[16];
2588  };
2589  
2590  #define FW_ACL_VLAN_CMD_PFN_S		8
2591  #define FW_ACL_VLAN_CMD_PFN_V(x)	((x) << FW_ACL_VLAN_CMD_PFN_S)
2592  
2593  #define FW_ACL_VLAN_CMD_VFN_S		0
2594  #define FW_ACL_VLAN_CMD_VFN_V(x)	((x) << FW_ACL_VLAN_CMD_VFN_S)
2595  
2596  #define FW_ACL_VLAN_CMD_EN_S		31
2597  #define FW_ACL_VLAN_CMD_EN_M		0x1
2598  #define FW_ACL_VLAN_CMD_EN_V(x)		((x) << FW_ACL_VLAN_CMD_EN_S)
2599  #define FW_ACL_VLAN_CMD_EN_G(x)         \
2600  	(((x) >> S_FW_ACL_VLAN_CMD_EN_S) & FW_ACL_VLAN_CMD_EN_M)
2601  #define FW_ACL_VLAN_CMD_EN_F            FW_ACL_VLAN_CMD_EN_V(1U)
2602  
2603  #define FW_ACL_VLAN_CMD_DROPNOVLAN_S	7
2604  #define FW_ACL_VLAN_CMD_DROPNOVLAN_V(x)	((x) << FW_ACL_VLAN_CMD_DROPNOVLAN_S)
2605  #define FW_ACL_VLAN_CMD_DROPNOVLAN_F    FW_ACL_VLAN_CMD_DROPNOVLAN_V(1U)
2606  
2607  #define FW_ACL_VLAN_CMD_FM_S		6
2608  #define FW_ACL_VLAN_CMD_FM_M		0x1
2609  #define FW_ACL_VLAN_CMD_FM_V(x)         ((x) << FW_ACL_VLAN_CMD_FM_S)
2610  #define FW_ACL_VLAN_CMD_FM_G(x)         \
2611  	(((x) >> FW_ACL_VLAN_CMD_FM_S) & FW_ACL_VLAN_CMD_FM_M)
2612  #define FW_ACL_VLAN_CMD_FM_F            FW_ACL_VLAN_CMD_FM_V(1U)
2613  
2614  /* old 16-bit port capabilities bitmap (fw_port_cap16_t) */
2615  enum fw_port_cap {
2616  	FW_PORT_CAP_SPEED_100M		= 0x0001,
2617  	FW_PORT_CAP_SPEED_1G		= 0x0002,
2618  	FW_PORT_CAP_SPEED_25G		= 0x0004,
2619  	FW_PORT_CAP_SPEED_10G		= 0x0008,
2620  	FW_PORT_CAP_SPEED_40G		= 0x0010,
2621  	FW_PORT_CAP_SPEED_100G		= 0x0020,
2622  	FW_PORT_CAP_FC_RX		= 0x0040,
2623  	FW_PORT_CAP_FC_TX		= 0x0080,
2624  	FW_PORT_CAP_ANEG		= 0x0100,
2625  	FW_PORT_CAP_MDIAUTO		= 0x0200,
2626  	FW_PORT_CAP_MDISTRAIGHT		= 0x0400,
2627  	FW_PORT_CAP_FEC_RS		= 0x0800,
2628  	FW_PORT_CAP_FEC_BASER_RS	= 0x1000,
2629  	FW_PORT_CAP_FORCE_PAUSE		= 0x2000,
2630  	FW_PORT_CAP_802_3_PAUSE		= 0x4000,
2631  	FW_PORT_CAP_802_3_ASM_DIR	= 0x8000,
2632  };
2633  
2634  #define FW_PORT_CAP_SPEED_S     0
2635  #define FW_PORT_CAP_SPEED_M     0x3f
2636  #define FW_PORT_CAP_SPEED_V(x)  ((x) << FW_PORT_CAP_SPEED_S)
2637  #define FW_PORT_CAP_SPEED_G(x) \
2638  	(((x) >> FW_PORT_CAP_SPEED_S) & FW_PORT_CAP_SPEED_M)
2639  
2640  enum fw_port_mdi {
2641  	FW_PORT_CAP_MDI_UNCHANGED,
2642  	FW_PORT_CAP_MDI_AUTO,
2643  	FW_PORT_CAP_MDI_F_STRAIGHT,
2644  	FW_PORT_CAP_MDI_F_CROSSOVER
2645  };
2646  
2647  #define FW_PORT_CAP_MDI_S 9
2648  #define FW_PORT_CAP_MDI_V(x) ((x) << FW_PORT_CAP_MDI_S)
2649  
2650  /* new 32-bit port capabilities bitmap (fw_port_cap32_t) */
2651  #define	FW_PORT_CAP32_SPEED_100M	0x00000001UL
2652  #define	FW_PORT_CAP32_SPEED_1G		0x00000002UL
2653  #define	FW_PORT_CAP32_SPEED_10G		0x00000004UL
2654  #define	FW_PORT_CAP32_SPEED_25G		0x00000008UL
2655  #define	FW_PORT_CAP32_SPEED_40G		0x00000010UL
2656  #define	FW_PORT_CAP32_SPEED_50G		0x00000020UL
2657  #define	FW_PORT_CAP32_SPEED_100G	0x00000040UL
2658  #define	FW_PORT_CAP32_SPEED_200G	0x00000080UL
2659  #define	FW_PORT_CAP32_SPEED_400G	0x00000100UL
2660  #define	FW_PORT_CAP32_SPEED_RESERVED1	0x00000200UL
2661  #define	FW_PORT_CAP32_SPEED_RESERVED2	0x00000400UL
2662  #define	FW_PORT_CAP32_SPEED_RESERVED3	0x00000800UL
2663  #define	FW_PORT_CAP32_RESERVED1		0x0000f000UL
2664  #define	FW_PORT_CAP32_FC_RX		0x00010000UL
2665  #define	FW_PORT_CAP32_FC_TX		0x00020000UL
2666  #define	FW_PORT_CAP32_802_3_PAUSE	0x00040000UL
2667  #define	FW_PORT_CAP32_802_3_ASM_DIR	0x00080000UL
2668  #define	FW_PORT_CAP32_ANEG		0x00100000UL
2669  #define	FW_PORT_CAP32_MDIAUTO		0x00200000UL
2670  #define	FW_PORT_CAP32_MDISTRAIGHT	0x00400000UL
2671  #define	FW_PORT_CAP32_FEC_RS		0x00800000UL
2672  #define	FW_PORT_CAP32_FEC_BASER_RS	0x01000000UL
2673  #define	FW_PORT_CAP32_FEC_RESERVED1	0x02000000UL
2674  #define	FW_PORT_CAP32_FEC_RESERVED2	0x04000000UL
2675  #define	FW_PORT_CAP32_FEC_RESERVED3	0x08000000UL
2676  #define FW_PORT_CAP32_FORCE_PAUSE	0x10000000UL
2677  #define FW_PORT_CAP32_RESERVED2		0xe0000000UL
2678  
2679  #define FW_PORT_CAP32_SPEED_S	0
2680  #define FW_PORT_CAP32_SPEED_M	0xfff
2681  #define FW_PORT_CAP32_SPEED_V(x)	((x) << FW_PORT_CAP32_SPEED_S)
2682  #define FW_PORT_CAP32_SPEED_G(x) \
2683  	(((x) >> FW_PORT_CAP32_SPEED_S) & FW_PORT_CAP32_SPEED_M)
2684  
2685  #define FW_PORT_CAP32_FC_S	16
2686  #define FW_PORT_CAP32_FC_M	0x3
2687  #define FW_PORT_CAP32_FC_V(x)	((x) << FW_PORT_CAP32_FC_S)
2688  #define FW_PORT_CAP32_FC_G(x) \
2689  	(((x) >> FW_PORT_CAP32_FC_S) & FW_PORT_CAP32_FC_M)
2690  
2691  #define FW_PORT_CAP32_802_3_S	18
2692  #define FW_PORT_CAP32_802_3_M	0x3
2693  #define FW_PORT_CAP32_802_3_V(x)	((x) << FW_PORT_CAP32_802_3_S)
2694  #define FW_PORT_CAP32_802_3_G(x) \
2695  	(((x) >> FW_PORT_CAP32_802_3_S) & FW_PORT_CAP32_802_3_M)
2696  
2697  #define FW_PORT_CAP32_ANEG_S	20
2698  #define FW_PORT_CAP32_ANEG_M	0x1
2699  #define FW_PORT_CAP32_ANEG_V(x)	((x) << FW_PORT_CAP32_ANEG_S)
2700  #define FW_PORT_CAP32_ANEG_G(x) \
2701  	(((x) >> FW_PORT_CAP32_ANEG_S) & FW_PORT_CAP32_ANEG_M)
2702  
2703  enum fw_port_mdi32 {
2704  	FW_PORT_CAP32_MDI_UNCHANGED,
2705  	FW_PORT_CAP32_MDI_AUTO,
2706  	FW_PORT_CAP32_MDI_F_STRAIGHT,
2707  	FW_PORT_CAP32_MDI_F_CROSSOVER
2708  };
2709  
2710  #define FW_PORT_CAP32_MDI_S 21
2711  #define FW_PORT_CAP32_MDI_M 3
2712  #define FW_PORT_CAP32_MDI_V(x) ((x) << FW_PORT_CAP32_MDI_S)
2713  #define FW_PORT_CAP32_MDI_G(x) \
2714  	(((x) >> FW_PORT_CAP32_MDI_S) & FW_PORT_CAP32_MDI_M)
2715  
2716  #define FW_PORT_CAP32_FEC_S	23
2717  #define FW_PORT_CAP32_FEC_M	0x1f
2718  #define FW_PORT_CAP32_FEC_V(x)	((x) << FW_PORT_CAP32_FEC_S)
2719  #define FW_PORT_CAP32_FEC_G(x) \
2720  	(((x) >> FW_PORT_CAP32_FEC_S) & FW_PORT_CAP32_FEC_M)
2721  
2722  /* macros to isolate various 32-bit Port Capabilities sub-fields */
2723  #define CAP32_SPEED(__cap32) \
2724  	(FW_PORT_CAP32_SPEED_V(FW_PORT_CAP32_SPEED_M) & __cap32)
2725  
2726  #define CAP32_FEC(__cap32) \
2727  	(FW_PORT_CAP32_FEC_V(FW_PORT_CAP32_FEC_M) & __cap32)
2728  
2729  enum fw_port_action {
2730  	FW_PORT_ACTION_L1_CFG		= 0x0001,
2731  	FW_PORT_ACTION_L2_CFG		= 0x0002,
2732  	FW_PORT_ACTION_GET_PORT_INFO	= 0x0003,
2733  	FW_PORT_ACTION_L2_PPP_CFG	= 0x0004,
2734  	FW_PORT_ACTION_L2_DCB_CFG	= 0x0005,
2735  	FW_PORT_ACTION_DCB_READ_TRANS	= 0x0006,
2736  	FW_PORT_ACTION_DCB_READ_RECV	= 0x0007,
2737  	FW_PORT_ACTION_DCB_READ_DET	= 0x0008,
2738  	FW_PORT_ACTION_L1_CFG32		= 0x0009,
2739  	FW_PORT_ACTION_GET_PORT_INFO32	= 0x000a,
2740  	FW_PORT_ACTION_LOW_PWR_TO_NORMAL = 0x0010,
2741  	FW_PORT_ACTION_L1_LOW_PWR_EN	= 0x0011,
2742  	FW_PORT_ACTION_L2_WOL_MODE_EN	= 0x0012,
2743  	FW_PORT_ACTION_LPBK_TO_NORMAL	= 0x0020,
2744  	FW_PORT_ACTION_L1_LPBK		= 0x0021,
2745  	FW_PORT_ACTION_L1_PMA_LPBK	= 0x0022,
2746  	FW_PORT_ACTION_L1_PCS_LPBK	= 0x0023,
2747  	FW_PORT_ACTION_L1_PHYXS_CSIDE_LPBK = 0x0024,
2748  	FW_PORT_ACTION_L1_PHYXS_ESIDE_LPBK = 0x0025,
2749  	FW_PORT_ACTION_PHY_RESET	= 0x0040,
2750  	FW_PORT_ACTION_PMA_RESET	= 0x0041,
2751  	FW_PORT_ACTION_PCS_RESET	= 0x0042,
2752  	FW_PORT_ACTION_PHYXS_RESET	= 0x0043,
2753  	FW_PORT_ACTION_DTEXS_REEST	= 0x0044,
2754  	FW_PORT_ACTION_AN_RESET		= 0x0045
2755  };
2756  
2757  enum fw_port_l2cfg_ctlbf {
2758  	FW_PORT_L2_CTLBF_OVLAN0	= 0x01,
2759  	FW_PORT_L2_CTLBF_OVLAN1	= 0x02,
2760  	FW_PORT_L2_CTLBF_OVLAN2	= 0x04,
2761  	FW_PORT_L2_CTLBF_OVLAN3	= 0x08,
2762  	FW_PORT_L2_CTLBF_IVLAN	= 0x10,
2763  	FW_PORT_L2_CTLBF_TXIPG	= 0x20
2764  };
2765  
2766  enum fw_port_dcb_versions {
2767  	FW_PORT_DCB_VER_UNKNOWN,
2768  	FW_PORT_DCB_VER_CEE1D0,
2769  	FW_PORT_DCB_VER_CEE1D01,
2770  	FW_PORT_DCB_VER_IEEE,
2771  	FW_PORT_DCB_VER_AUTO = 7
2772  };
2773  
2774  enum fw_port_dcb_cfg {
2775  	FW_PORT_DCB_CFG_PG	= 0x01,
2776  	FW_PORT_DCB_CFG_PFC	= 0x02,
2777  	FW_PORT_DCB_CFG_APPL	= 0x04
2778  };
2779  
2780  enum fw_port_dcb_cfg_rc {
2781  	FW_PORT_DCB_CFG_SUCCESS	= 0x0,
2782  	FW_PORT_DCB_CFG_ERROR	= 0x1
2783  };
2784  
2785  enum fw_port_dcb_type {
2786  	FW_PORT_DCB_TYPE_PGID		= 0x00,
2787  	FW_PORT_DCB_TYPE_PGRATE		= 0x01,
2788  	FW_PORT_DCB_TYPE_PRIORATE	= 0x02,
2789  	FW_PORT_DCB_TYPE_PFC		= 0x03,
2790  	FW_PORT_DCB_TYPE_APP_ID		= 0x04,
2791  	FW_PORT_DCB_TYPE_CONTROL	= 0x05,
2792  };
2793  
2794  enum fw_port_dcb_feature_state {
2795  	FW_PORT_DCB_FEATURE_STATE_PENDING = 0x0,
2796  	FW_PORT_DCB_FEATURE_STATE_SUCCESS = 0x1,
2797  	FW_PORT_DCB_FEATURE_STATE_ERROR	= 0x2,
2798  	FW_PORT_DCB_FEATURE_STATE_TIMEOUT = 0x3,
2799  };
2800  
2801  struct fw_port_cmd {
2802  	__be32 op_to_portid;
2803  	__be32 action_to_len16;
2804  	union fw_port {
2805  		struct fw_port_l1cfg {
2806  			__be32 rcap;
2807  			__be32 r;
2808  		} l1cfg;
2809  		struct fw_port_l2cfg {
2810  			__u8   ctlbf;
2811  			__u8   ovlan3_to_ivlan0;
2812  			__be16 ivlantype;
2813  			__be16 txipg_force_pinfo;
2814  			__be16 mtu;
2815  			__be16 ovlan0mask;
2816  			__be16 ovlan0type;
2817  			__be16 ovlan1mask;
2818  			__be16 ovlan1type;
2819  			__be16 ovlan2mask;
2820  			__be16 ovlan2type;
2821  			__be16 ovlan3mask;
2822  			__be16 ovlan3type;
2823  		} l2cfg;
2824  		struct fw_port_info {
2825  			__be32 lstatus_to_modtype;
2826  			__be16 pcap;
2827  			__be16 acap;
2828  			__be16 mtu;
2829  			__u8   cbllen;
2830  			__u8   auxlinfo;
2831  			__u8   dcbxdis_pkd;
2832  			__u8   r8_lo;
2833  			__be16 lpacap;
2834  			__be64 r9;
2835  		} info;
2836  		struct fw_port_diags {
2837  			__u8   diagop;
2838  			__u8   r[3];
2839  			__be32 diagval;
2840  		} diags;
2841  		union fw_port_dcb {
2842  			struct fw_port_dcb_pgid {
2843  				__u8   type;
2844  				__u8   apply_pkd;
2845  				__u8   r10_lo[2];
2846  				__be32 pgid;
2847  				__be64 r11;
2848  			} pgid;
2849  			struct fw_port_dcb_pgrate {
2850  				__u8   type;
2851  				__u8   apply_pkd;
2852  				__u8   r10_lo[5];
2853  				__u8   num_tcs_supported;
2854  				__u8   pgrate[8];
2855  				__u8   tsa[8];
2856  			} pgrate;
2857  			struct fw_port_dcb_priorate {
2858  				__u8   type;
2859  				__u8   apply_pkd;
2860  				__u8   r10_lo[6];
2861  				__u8   strict_priorate[8];
2862  			} priorate;
2863  			struct fw_port_dcb_pfc {
2864  				__u8   type;
2865  				__u8   pfcen;
2866  				__u8   r10[5];
2867  				__u8   max_pfc_tcs;
2868  				__be64 r11;
2869  			} pfc;
2870  			struct fw_port_app_priority {
2871  				__u8   type;
2872  				__u8   r10[2];
2873  				__u8   idx;
2874  				__u8   user_prio_map;
2875  				__u8   sel_field;
2876  				__be16 protocolid;
2877  				__be64 r12;
2878  			} app_priority;
2879  			struct fw_port_dcb_control {
2880  				__u8   type;
2881  				__u8   all_syncd_pkd;
2882  				__be16 dcb_version_to_app_state;
2883  				__be32 r11;
2884  				__be64 r12;
2885  			} control;
2886  		} dcb;
2887  		struct fw_port_l1cfg32 {
2888  			__be32 rcap32;
2889  			__be32 r;
2890  		} l1cfg32;
2891  		struct fw_port_info32 {
2892  			__be32 lstatus32_to_cbllen32;
2893  			__be32 auxlinfo32_mtu32;
2894  			__be32 linkattr32;
2895  			__be32 pcaps32;
2896  			__be32 acaps32;
2897  			__be32 lpacaps32;
2898  		} info32;
2899  	} u;
2900  };
2901  
2902  #define FW_PORT_CMD_READ_S	22
2903  #define FW_PORT_CMD_READ_V(x)	((x) << FW_PORT_CMD_READ_S)
2904  #define FW_PORT_CMD_READ_F	FW_PORT_CMD_READ_V(1U)
2905  
2906  #define FW_PORT_CMD_PORTID_S	0
2907  #define FW_PORT_CMD_PORTID_M	0xf
2908  #define FW_PORT_CMD_PORTID_V(x)	((x) << FW_PORT_CMD_PORTID_S)
2909  #define FW_PORT_CMD_PORTID_G(x)	\
2910  	(((x) >> FW_PORT_CMD_PORTID_S) & FW_PORT_CMD_PORTID_M)
2911  
2912  #define FW_PORT_CMD_ACTION_S	16
2913  #define FW_PORT_CMD_ACTION_M	0xffff
2914  #define FW_PORT_CMD_ACTION_V(x)	((x) << FW_PORT_CMD_ACTION_S)
2915  #define FW_PORT_CMD_ACTION_G(x)	\
2916  	(((x) >> FW_PORT_CMD_ACTION_S) & FW_PORT_CMD_ACTION_M)
2917  
2918  #define FW_PORT_CMD_OVLAN3_S	7
2919  #define FW_PORT_CMD_OVLAN3_V(x)	((x) << FW_PORT_CMD_OVLAN3_S)
2920  
2921  #define FW_PORT_CMD_OVLAN2_S	6
2922  #define FW_PORT_CMD_OVLAN2_V(x)	((x) << FW_PORT_CMD_OVLAN2_S)
2923  
2924  #define FW_PORT_CMD_OVLAN1_S	5
2925  #define FW_PORT_CMD_OVLAN1_V(x)	((x) << FW_PORT_CMD_OVLAN1_S)
2926  
2927  #define FW_PORT_CMD_OVLAN0_S	4
2928  #define FW_PORT_CMD_OVLAN0_V(x)	((x) << FW_PORT_CMD_OVLAN0_S)
2929  
2930  #define FW_PORT_CMD_IVLAN0_S	3
2931  #define FW_PORT_CMD_IVLAN0_V(x)	((x) << FW_PORT_CMD_IVLAN0_S)
2932  
2933  #define FW_PORT_CMD_TXIPG_S	3
2934  #define FW_PORT_CMD_TXIPG_V(x)	((x) << FW_PORT_CMD_TXIPG_S)
2935  
2936  #define FW_PORT_CMD_LSTATUS_S           31
2937  #define FW_PORT_CMD_LSTATUS_M           0x1
2938  #define FW_PORT_CMD_LSTATUS_V(x)        ((x) << FW_PORT_CMD_LSTATUS_S)
2939  #define FW_PORT_CMD_LSTATUS_G(x)        \
2940  	(((x) >> FW_PORT_CMD_LSTATUS_S) & FW_PORT_CMD_LSTATUS_M)
2941  #define FW_PORT_CMD_LSTATUS_F   FW_PORT_CMD_LSTATUS_V(1U)
2942  
2943  #define FW_PORT_CMD_LSPEED_S	24
2944  #define FW_PORT_CMD_LSPEED_M	0x3f
2945  #define FW_PORT_CMD_LSPEED_V(x)	((x) << FW_PORT_CMD_LSPEED_S)
2946  #define FW_PORT_CMD_LSPEED_G(x)	\
2947  	(((x) >> FW_PORT_CMD_LSPEED_S) & FW_PORT_CMD_LSPEED_M)
2948  
2949  #define FW_PORT_CMD_TXPAUSE_S		23
2950  #define FW_PORT_CMD_TXPAUSE_V(x)	((x) << FW_PORT_CMD_TXPAUSE_S)
2951  #define FW_PORT_CMD_TXPAUSE_F	FW_PORT_CMD_TXPAUSE_V(1U)
2952  
2953  #define FW_PORT_CMD_RXPAUSE_S		22
2954  #define FW_PORT_CMD_RXPAUSE_V(x)	((x) << FW_PORT_CMD_RXPAUSE_S)
2955  #define FW_PORT_CMD_RXPAUSE_F	FW_PORT_CMD_RXPAUSE_V(1U)
2956  
2957  #define FW_PORT_CMD_MDIOCAP_S		21
2958  #define FW_PORT_CMD_MDIOCAP_V(x)	((x) << FW_PORT_CMD_MDIOCAP_S)
2959  #define FW_PORT_CMD_MDIOCAP_F	FW_PORT_CMD_MDIOCAP_V(1U)
2960  
2961  #define FW_PORT_CMD_MDIOADDR_S		16
2962  #define FW_PORT_CMD_MDIOADDR_M		0x1f
2963  #define FW_PORT_CMD_MDIOADDR_G(x)	\
2964  	(((x) >> FW_PORT_CMD_MDIOADDR_S) & FW_PORT_CMD_MDIOADDR_M)
2965  
2966  #define FW_PORT_CMD_LPTXPAUSE_S		15
2967  #define FW_PORT_CMD_LPTXPAUSE_V(x)	((x) << FW_PORT_CMD_LPTXPAUSE_S)
2968  #define FW_PORT_CMD_LPTXPAUSE_F	FW_PORT_CMD_LPTXPAUSE_V(1U)
2969  
2970  #define FW_PORT_CMD_LPRXPAUSE_S		14
2971  #define FW_PORT_CMD_LPRXPAUSE_V(x)	((x) << FW_PORT_CMD_LPRXPAUSE_S)
2972  #define FW_PORT_CMD_LPRXPAUSE_F	FW_PORT_CMD_LPRXPAUSE_V(1U)
2973  
2974  #define FW_PORT_CMD_PTYPE_S	8
2975  #define FW_PORT_CMD_PTYPE_M	0x1f
2976  #define FW_PORT_CMD_PTYPE_G(x)	\
2977  	(((x) >> FW_PORT_CMD_PTYPE_S) & FW_PORT_CMD_PTYPE_M)
2978  
2979  #define FW_PORT_CMD_LINKDNRC_S		5
2980  #define FW_PORT_CMD_LINKDNRC_M		0x7
2981  #define FW_PORT_CMD_LINKDNRC_G(x)	\
2982  	(((x) >> FW_PORT_CMD_LINKDNRC_S) & FW_PORT_CMD_LINKDNRC_M)
2983  
2984  #define FW_PORT_CMD_MODTYPE_S		0
2985  #define FW_PORT_CMD_MODTYPE_M		0x1f
2986  #define FW_PORT_CMD_MODTYPE_V(x)	((x) << FW_PORT_CMD_MODTYPE_S)
2987  #define FW_PORT_CMD_MODTYPE_G(x)	\
2988  	(((x) >> FW_PORT_CMD_MODTYPE_S) & FW_PORT_CMD_MODTYPE_M)
2989  
2990  #define FW_PORT_CMD_DCBXDIS_S		7
2991  #define FW_PORT_CMD_DCBXDIS_V(x)	((x) << FW_PORT_CMD_DCBXDIS_S)
2992  #define FW_PORT_CMD_DCBXDIS_F	FW_PORT_CMD_DCBXDIS_V(1U)
2993  
2994  #define FW_PORT_CMD_APPLY_S	7
2995  #define FW_PORT_CMD_APPLY_V(x)	((x) << FW_PORT_CMD_APPLY_S)
2996  #define FW_PORT_CMD_APPLY_F	FW_PORT_CMD_APPLY_V(1U)
2997  
2998  #define FW_PORT_CMD_ALL_SYNCD_S		7
2999  #define FW_PORT_CMD_ALL_SYNCD_V(x)	((x) << FW_PORT_CMD_ALL_SYNCD_S)
3000  #define FW_PORT_CMD_ALL_SYNCD_F	FW_PORT_CMD_ALL_SYNCD_V(1U)
3001  
3002  #define FW_PORT_CMD_DCB_VERSION_S	12
3003  #define FW_PORT_CMD_DCB_VERSION_M	0x7
3004  #define FW_PORT_CMD_DCB_VERSION_G(x)	\
3005  	(((x) >> FW_PORT_CMD_DCB_VERSION_S) & FW_PORT_CMD_DCB_VERSION_M)
3006  
3007  #define FW_PORT_CMD_LSTATUS32_S		31
3008  #define FW_PORT_CMD_LSTATUS32_M		0x1
3009  #define FW_PORT_CMD_LSTATUS32_V(x)	((x) << FW_PORT_CMD_LSTATUS32_S)
3010  #define FW_PORT_CMD_LSTATUS32_G(x)	\
3011  	(((x) >> FW_PORT_CMD_LSTATUS32_S) & FW_PORT_CMD_LSTATUS32_M)
3012  #define FW_PORT_CMD_LSTATUS32_F	FW_PORT_CMD_LSTATUS32_V(1U)
3013  
3014  #define FW_PORT_CMD_LINKDNRC32_S	28
3015  #define FW_PORT_CMD_LINKDNRC32_M	0x7
3016  #define FW_PORT_CMD_LINKDNRC32_V(x)	((x) << FW_PORT_CMD_LINKDNRC32_S)
3017  #define FW_PORT_CMD_LINKDNRC32_G(x)	\
3018  	(((x) >> FW_PORT_CMD_LINKDNRC32_S) & FW_PORT_CMD_LINKDNRC32_M)
3019  
3020  #define FW_PORT_CMD_DCBXDIS32_S		27
3021  #define FW_PORT_CMD_DCBXDIS32_M		0x1
3022  #define FW_PORT_CMD_DCBXDIS32_V(x)	((x) << FW_PORT_CMD_DCBXDIS32_S)
3023  #define FW_PORT_CMD_DCBXDIS32_G(x)	\
3024  	(((x) >> FW_PORT_CMD_DCBXDIS32_S) & FW_PORT_CMD_DCBXDIS32_M)
3025  #define FW_PORT_CMD_DCBXDIS32_F	FW_PORT_CMD_DCBXDIS32_V(1U)
3026  
3027  #define FW_PORT_CMD_MDIOCAP32_S		26
3028  #define FW_PORT_CMD_MDIOCAP32_M		0x1
3029  #define FW_PORT_CMD_MDIOCAP32_V(x)	((x) << FW_PORT_CMD_MDIOCAP32_S)
3030  #define FW_PORT_CMD_MDIOCAP32_G(x)	\
3031  	(((x) >> FW_PORT_CMD_MDIOCAP32_S) & FW_PORT_CMD_MDIOCAP32_M)
3032  #define FW_PORT_CMD_MDIOCAP32_F	FW_PORT_CMD_MDIOCAP32_V(1U)
3033  
3034  #define FW_PORT_CMD_MDIOADDR32_S	21
3035  #define FW_PORT_CMD_MDIOADDR32_M	0x1f
3036  #define FW_PORT_CMD_MDIOADDR32_V(x)	((x) << FW_PORT_CMD_MDIOADDR32_S)
3037  #define FW_PORT_CMD_MDIOADDR32_G(x)	\
3038  	(((x) >> FW_PORT_CMD_MDIOADDR32_S) & FW_PORT_CMD_MDIOADDR32_M)
3039  
3040  #define FW_PORT_CMD_PORTTYPE32_S	13
3041  #define FW_PORT_CMD_PORTTYPE32_M	0xff
3042  #define FW_PORT_CMD_PORTTYPE32_V(x)	((x) << FW_PORT_CMD_PORTTYPE32_S)
3043  #define FW_PORT_CMD_PORTTYPE32_G(x)	\
3044  	(((x) >> FW_PORT_CMD_PORTTYPE32_S) & FW_PORT_CMD_PORTTYPE32_M)
3045  
3046  #define FW_PORT_CMD_MODTYPE32_S		8
3047  #define FW_PORT_CMD_MODTYPE32_M		0x1f
3048  #define FW_PORT_CMD_MODTYPE32_V(x)	((x) << FW_PORT_CMD_MODTYPE32_S)
3049  #define FW_PORT_CMD_MODTYPE32_G(x)	\
3050  	(((x) >> FW_PORT_CMD_MODTYPE32_S) & FW_PORT_CMD_MODTYPE32_M)
3051  
3052  #define FW_PORT_CMD_CBLLEN32_S		0
3053  #define FW_PORT_CMD_CBLLEN32_M		0xff
3054  #define FW_PORT_CMD_CBLLEN32_V(x)	((x) << FW_PORT_CMD_CBLLEN32_S)
3055  #define FW_PORT_CMD_CBLLEN32_G(x)	\
3056  	(((x) >> FW_PORT_CMD_CBLLEN32_S) & FW_PORT_CMD_CBLLEN32_M)
3057  
3058  #define FW_PORT_CMD_AUXLINFO32_S	24
3059  #define FW_PORT_CMD_AUXLINFO32_M	0xff
3060  #define FW_PORT_CMD_AUXLINFO32_V(x)	((x) << FW_PORT_CMD_AUXLINFO32_S)
3061  #define FW_PORT_CMD_AUXLINFO32_G(x)	\
3062  	(((x) >> FW_PORT_CMD_AUXLINFO32_S) & FW_PORT_CMD_AUXLINFO32_M)
3063  
3064  #define FW_PORT_AUXLINFO32_KX4_S	2
3065  #define FW_PORT_AUXLINFO32_KX4_M	0x1
3066  #define FW_PORT_AUXLINFO32_KX4_V(x) \
3067  	((x) << FW_PORT_AUXLINFO32_KX4_S)
3068  #define FW_PORT_AUXLINFO32_KX4_G(x) \
3069  	(((x) >> FW_PORT_AUXLINFO32_KX4_S) & FW_PORT_AUXLINFO32_KX4_M)
3070  #define FW_PORT_AUXLINFO32_KX4_F	FW_PORT_AUXLINFO32_KX4_V(1U)
3071  
3072  #define FW_PORT_AUXLINFO32_KR_S	1
3073  #define FW_PORT_AUXLINFO32_KR_M	0x1
3074  #define FW_PORT_AUXLINFO32_KR_V(x) \
3075  	((x) << FW_PORT_AUXLINFO32_KR_S)
3076  #define FW_PORT_AUXLINFO32_KR_G(x) \
3077  	(((x) >> FW_PORT_AUXLINFO32_KR_S) & FW_PORT_AUXLINFO32_KR_M)
3078  #define FW_PORT_AUXLINFO32_KR_F	FW_PORT_AUXLINFO32_KR_V(1U)
3079  
3080  #define FW_PORT_CMD_MTU32_S	0
3081  #define FW_PORT_CMD_MTU32_M	0xffff
3082  #define FW_PORT_CMD_MTU32_V(x)	((x) << FW_PORT_CMD_MTU32_S)
3083  #define FW_PORT_CMD_MTU32_G(x)	\
3084  	(((x) >> FW_PORT_CMD_MTU32_S) & FW_PORT_CMD_MTU32_M)
3085  
3086  enum fw_port_type {
3087  	FW_PORT_TYPE_FIBER_XFI,
3088  	FW_PORT_TYPE_FIBER_XAUI,
3089  	FW_PORT_TYPE_BT_SGMII,
3090  	FW_PORT_TYPE_BT_XFI,
3091  	FW_PORT_TYPE_BT_XAUI,
3092  	FW_PORT_TYPE_KX4,
3093  	FW_PORT_TYPE_CX4,
3094  	FW_PORT_TYPE_KX,
3095  	FW_PORT_TYPE_KR,
3096  	FW_PORT_TYPE_SFP,
3097  	FW_PORT_TYPE_BP_AP,
3098  	FW_PORT_TYPE_BP4_AP,
3099  	FW_PORT_TYPE_QSFP_10G,
3100  	FW_PORT_TYPE_QSA,
3101  	FW_PORT_TYPE_QSFP,
3102  	FW_PORT_TYPE_BP40_BA,
3103  	FW_PORT_TYPE_KR4_100G,
3104  	FW_PORT_TYPE_CR4_QSFP,
3105  	FW_PORT_TYPE_CR_QSFP,
3106  	FW_PORT_TYPE_CR2_QSFP,
3107  	FW_PORT_TYPE_SFP28,
3108  	FW_PORT_TYPE_KR_SFP28,
3109  	FW_PORT_TYPE_KR_XLAUI,
3110  
3111  	FW_PORT_TYPE_NONE = FW_PORT_CMD_PTYPE_M
3112  };
3113  
3114  enum fw_port_module_type {
3115  	FW_PORT_MOD_TYPE_NA,
3116  	FW_PORT_MOD_TYPE_LR,
3117  	FW_PORT_MOD_TYPE_SR,
3118  	FW_PORT_MOD_TYPE_ER,
3119  	FW_PORT_MOD_TYPE_TWINAX_PASSIVE,
3120  	FW_PORT_MOD_TYPE_TWINAX_ACTIVE,
3121  	FW_PORT_MOD_TYPE_LRM,
3122  	FW_PORT_MOD_TYPE_ERROR		= FW_PORT_CMD_MODTYPE_M - 3,
3123  	FW_PORT_MOD_TYPE_UNKNOWN	= FW_PORT_CMD_MODTYPE_M - 2,
3124  	FW_PORT_MOD_TYPE_NOTSUPPORTED	= FW_PORT_CMD_MODTYPE_M - 1,
3125  
3126  	FW_PORT_MOD_TYPE_NONE = FW_PORT_CMD_MODTYPE_M
3127  };
3128  
3129  enum fw_port_mod_sub_type {
3130  	FW_PORT_MOD_SUB_TYPE_NA,
3131  	FW_PORT_MOD_SUB_TYPE_MV88E114X = 0x1,
3132  	FW_PORT_MOD_SUB_TYPE_TN8022 = 0x2,
3133  	FW_PORT_MOD_SUB_TYPE_AQ1202 = 0x3,
3134  	FW_PORT_MOD_SUB_TYPE_88x3120 = 0x4,
3135  	FW_PORT_MOD_SUB_TYPE_BCM84834 = 0x5,
3136  	FW_PORT_MOD_SUB_TYPE_BT_VSC8634 = 0x8,
3137  
3138  	/* The following will never been in the VPD.  They are TWINAX cable
3139  	 * lengths decoded from SFP+ module i2c PROMs.  These should
3140  	 * almost certainly go somewhere else ...
3141  	 */
3142  	FW_PORT_MOD_SUB_TYPE_TWINAX_1 = 0x9,
3143  	FW_PORT_MOD_SUB_TYPE_TWINAX_3 = 0xA,
3144  	FW_PORT_MOD_SUB_TYPE_TWINAX_5 = 0xB,
3145  	FW_PORT_MOD_SUB_TYPE_TWINAX_7 = 0xC,
3146  };
3147  
3148  enum fw_port_stats_tx_index {
3149  	FW_STAT_TX_PORT_BYTES_IX = 0,
3150  	FW_STAT_TX_PORT_FRAMES_IX,
3151  	FW_STAT_TX_PORT_BCAST_IX,
3152  	FW_STAT_TX_PORT_MCAST_IX,
3153  	FW_STAT_TX_PORT_UCAST_IX,
3154  	FW_STAT_TX_PORT_ERROR_IX,
3155  	FW_STAT_TX_PORT_64B_IX,
3156  	FW_STAT_TX_PORT_65B_127B_IX,
3157  	FW_STAT_TX_PORT_128B_255B_IX,
3158  	FW_STAT_TX_PORT_256B_511B_IX,
3159  	FW_STAT_TX_PORT_512B_1023B_IX,
3160  	FW_STAT_TX_PORT_1024B_1518B_IX,
3161  	FW_STAT_TX_PORT_1519B_MAX_IX,
3162  	FW_STAT_TX_PORT_DROP_IX,
3163  	FW_STAT_TX_PORT_PAUSE_IX,
3164  	FW_STAT_TX_PORT_PPP0_IX,
3165  	FW_STAT_TX_PORT_PPP1_IX,
3166  	FW_STAT_TX_PORT_PPP2_IX,
3167  	FW_STAT_TX_PORT_PPP3_IX,
3168  	FW_STAT_TX_PORT_PPP4_IX,
3169  	FW_STAT_TX_PORT_PPP5_IX,
3170  	FW_STAT_TX_PORT_PPP6_IX,
3171  	FW_STAT_TX_PORT_PPP7_IX,
3172  	FW_NUM_PORT_TX_STATS
3173  };
3174  
3175  enum fw_port_stat_rx_index {
3176  	FW_STAT_RX_PORT_BYTES_IX = 0,
3177  	FW_STAT_RX_PORT_FRAMES_IX,
3178  	FW_STAT_RX_PORT_BCAST_IX,
3179  	FW_STAT_RX_PORT_MCAST_IX,
3180  	FW_STAT_RX_PORT_UCAST_IX,
3181  	FW_STAT_RX_PORT_MTU_ERROR_IX,
3182  	FW_STAT_RX_PORT_MTU_CRC_ERROR_IX,
3183  	FW_STAT_RX_PORT_CRC_ERROR_IX,
3184  	FW_STAT_RX_PORT_LEN_ERROR_IX,
3185  	FW_STAT_RX_PORT_SYM_ERROR_IX,
3186  	FW_STAT_RX_PORT_64B_IX,
3187  	FW_STAT_RX_PORT_65B_127B_IX,
3188  	FW_STAT_RX_PORT_128B_255B_IX,
3189  	FW_STAT_RX_PORT_256B_511B_IX,
3190  	FW_STAT_RX_PORT_512B_1023B_IX,
3191  	FW_STAT_RX_PORT_1024B_1518B_IX,
3192  	FW_STAT_RX_PORT_1519B_MAX_IX,
3193  	FW_STAT_RX_PORT_PAUSE_IX,
3194  	FW_STAT_RX_PORT_PPP0_IX,
3195  	FW_STAT_RX_PORT_PPP1_IX,
3196  	FW_STAT_RX_PORT_PPP2_IX,
3197  	FW_STAT_RX_PORT_PPP3_IX,
3198  	FW_STAT_RX_PORT_PPP4_IX,
3199  	FW_STAT_RX_PORT_PPP5_IX,
3200  	FW_STAT_RX_PORT_PPP6_IX,
3201  	FW_STAT_RX_PORT_PPP7_IX,
3202  	FW_STAT_RX_PORT_LESS_64B_IX,
3203  	FW_STAT_RX_PORT_MAC_ERROR_IX,
3204  	FW_NUM_PORT_RX_STATS
3205  };
3206  
3207  /* port stats */
3208  #define FW_NUM_PORT_STATS (FW_NUM_PORT_TX_STATS + FW_NUM_PORT_RX_STATS)
3209  
3210  struct fw_port_stats_cmd {
3211  	__be32 op_to_portid;
3212  	__be32 retval_len16;
3213  	union fw_port_stats {
3214  		struct fw_port_stats_ctl {
3215  			u8 nstats_bg_bm;
3216  			u8 tx_ix;
3217  			__be16 r6;
3218  			__be32 r7;
3219  			__be64 stat0;
3220  			__be64 stat1;
3221  			__be64 stat2;
3222  			__be64 stat3;
3223  			__be64 stat4;
3224  			__be64 stat5;
3225  		} ctl;
3226  		struct fw_port_stats_all {
3227  			__be64 tx_bytes;
3228  			__be64 tx_frames;
3229  			__be64 tx_bcast;
3230  			__be64 tx_mcast;
3231  			__be64 tx_ucast;
3232  			__be64 tx_error;
3233  			__be64 tx_64b;
3234  			__be64 tx_65b_127b;
3235  			__be64 tx_128b_255b;
3236  			__be64 tx_256b_511b;
3237  			__be64 tx_512b_1023b;
3238  			__be64 tx_1024b_1518b;
3239  			__be64 tx_1519b_max;
3240  			__be64 tx_drop;
3241  			__be64 tx_pause;
3242  			__be64 tx_ppp0;
3243  			__be64 tx_ppp1;
3244  			__be64 tx_ppp2;
3245  			__be64 tx_ppp3;
3246  			__be64 tx_ppp4;
3247  			__be64 tx_ppp5;
3248  			__be64 tx_ppp6;
3249  			__be64 tx_ppp7;
3250  			__be64 rx_bytes;
3251  			__be64 rx_frames;
3252  			__be64 rx_bcast;
3253  			__be64 rx_mcast;
3254  			__be64 rx_ucast;
3255  			__be64 rx_mtu_error;
3256  			__be64 rx_mtu_crc_error;
3257  			__be64 rx_crc_error;
3258  			__be64 rx_len_error;
3259  			__be64 rx_sym_error;
3260  			__be64 rx_64b;
3261  			__be64 rx_65b_127b;
3262  			__be64 rx_128b_255b;
3263  			__be64 rx_256b_511b;
3264  			__be64 rx_512b_1023b;
3265  			__be64 rx_1024b_1518b;
3266  			__be64 rx_1519b_max;
3267  			__be64 rx_pause;
3268  			__be64 rx_ppp0;
3269  			__be64 rx_ppp1;
3270  			__be64 rx_ppp2;
3271  			__be64 rx_ppp3;
3272  			__be64 rx_ppp4;
3273  			__be64 rx_ppp5;
3274  			__be64 rx_ppp6;
3275  			__be64 rx_ppp7;
3276  			__be64 rx_less_64b;
3277  			__be64 rx_bg_drop;
3278  			__be64 rx_bg_trunc;
3279  		} all;
3280  	} u;
3281  };
3282  
3283  /* port loopback stats */
3284  #define FW_NUM_LB_STATS 16
3285  enum fw_port_lb_stats_index {
3286  	FW_STAT_LB_PORT_BYTES_IX,
3287  	FW_STAT_LB_PORT_FRAMES_IX,
3288  	FW_STAT_LB_PORT_BCAST_IX,
3289  	FW_STAT_LB_PORT_MCAST_IX,
3290  	FW_STAT_LB_PORT_UCAST_IX,
3291  	FW_STAT_LB_PORT_ERROR_IX,
3292  	FW_STAT_LB_PORT_64B_IX,
3293  	FW_STAT_LB_PORT_65B_127B_IX,
3294  	FW_STAT_LB_PORT_128B_255B_IX,
3295  	FW_STAT_LB_PORT_256B_511B_IX,
3296  	FW_STAT_LB_PORT_512B_1023B_IX,
3297  	FW_STAT_LB_PORT_1024B_1518B_IX,
3298  	FW_STAT_LB_PORT_1519B_MAX_IX,
3299  	FW_STAT_LB_PORT_DROP_FRAMES_IX
3300  };
3301  
3302  struct fw_port_lb_stats_cmd {
3303  	__be32 op_to_lbport;
3304  	__be32 retval_len16;
3305  	union fw_port_lb_stats {
3306  		struct fw_port_lb_stats_ctl {
3307  			u8 nstats_bg_bm;
3308  			u8 ix_pkd;
3309  			__be16 r6;
3310  			__be32 r7;
3311  			__be64 stat0;
3312  			__be64 stat1;
3313  			__be64 stat2;
3314  			__be64 stat3;
3315  			__be64 stat4;
3316  			__be64 stat5;
3317  		} ctl;
3318  		struct fw_port_lb_stats_all {
3319  			__be64 tx_bytes;
3320  			__be64 tx_frames;
3321  			__be64 tx_bcast;
3322  			__be64 tx_mcast;
3323  			__be64 tx_ucast;
3324  			__be64 tx_error;
3325  			__be64 tx_64b;
3326  			__be64 tx_65b_127b;
3327  			__be64 tx_128b_255b;
3328  			__be64 tx_256b_511b;
3329  			__be64 tx_512b_1023b;
3330  			__be64 tx_1024b_1518b;
3331  			__be64 tx_1519b_max;
3332  			__be64 rx_lb_drop;
3333  			__be64 rx_lb_trunc;
3334  		} all;
3335  	} u;
3336  };
3337  
3338  enum fw_ptp_subop {
3339  	/* none */
3340  	FW_PTP_SC_INIT_TIMER            = 0x00,
3341  	FW_PTP_SC_TX_TYPE               = 0x01,
3342  	/* init */
3343  	FW_PTP_SC_RXTIME_STAMP          = 0x08,
3344  	FW_PTP_SC_RDRX_TYPE             = 0x09,
3345  	/* ts */
3346  	FW_PTP_SC_ADJ_FREQ              = 0x10,
3347  	FW_PTP_SC_ADJ_TIME              = 0x11,
3348  	FW_PTP_SC_ADJ_FTIME             = 0x12,
3349  	FW_PTP_SC_WALL_CLOCK            = 0x13,
3350  	FW_PTP_SC_GET_TIME              = 0x14,
3351  	FW_PTP_SC_SET_TIME              = 0x15,
3352  };
3353  
3354  struct fw_ptp_cmd {
3355  	__be32 op_to_portid;
3356  	__be32 retval_len16;
3357  	union fw_ptp {
3358  		struct fw_ptp_sc {
3359  			__u8   sc;
3360  			__u8   r3[7];
3361  		} scmd;
3362  		struct fw_ptp_init {
3363  			__u8   sc;
3364  			__u8   txchan;
3365  			__be16 absid;
3366  			__be16 mode;
3367  			__be16 r3;
3368  		} init;
3369  		struct fw_ptp_ts {
3370  			__u8   sc;
3371  			__u8   sign;
3372  			__be16 r3;
3373  			__be32 ppb;
3374  			__be64 tm;
3375  		} ts;
3376  	} u;
3377  	__be64 r3;
3378  };
3379  
3380  #define FW_PTP_CMD_PORTID_S             0
3381  #define FW_PTP_CMD_PORTID_M             0xf
3382  #define FW_PTP_CMD_PORTID_V(x)          ((x) << FW_PTP_CMD_PORTID_S)
3383  #define FW_PTP_CMD_PORTID_G(x)          \
3384  	(((x) >> FW_PTP_CMD_PORTID_S) & FW_PTP_CMD_PORTID_M)
3385  
3386  struct fw_rss_ind_tbl_cmd {
3387  	__be32 op_to_viid;
3388  	__be32 retval_len16;
3389  	__be16 niqid;
3390  	__be16 startidx;
3391  	__be32 r3;
3392  	__be32 iq0_to_iq2;
3393  	__be32 iq3_to_iq5;
3394  	__be32 iq6_to_iq8;
3395  	__be32 iq9_to_iq11;
3396  	__be32 iq12_to_iq14;
3397  	__be32 iq15_to_iq17;
3398  	__be32 iq18_to_iq20;
3399  	__be32 iq21_to_iq23;
3400  	__be32 iq24_to_iq26;
3401  	__be32 iq27_to_iq29;
3402  	__be32 iq30_iq31;
3403  	__be32 r15_lo;
3404  };
3405  
3406  #define FW_RSS_IND_TBL_CMD_VIID_S	0
3407  #define FW_RSS_IND_TBL_CMD_VIID_V(x)	((x) << FW_RSS_IND_TBL_CMD_VIID_S)
3408  
3409  #define FW_RSS_IND_TBL_CMD_IQ0_S	20
3410  #define FW_RSS_IND_TBL_CMD_IQ0_V(x)	((x) << FW_RSS_IND_TBL_CMD_IQ0_S)
3411  
3412  #define FW_RSS_IND_TBL_CMD_IQ1_S	10
3413  #define FW_RSS_IND_TBL_CMD_IQ1_V(x)	((x) << FW_RSS_IND_TBL_CMD_IQ1_S)
3414  
3415  #define FW_RSS_IND_TBL_CMD_IQ2_S	0
3416  #define FW_RSS_IND_TBL_CMD_IQ2_V(x)	((x) << FW_RSS_IND_TBL_CMD_IQ2_S)
3417  
3418  struct fw_rss_glb_config_cmd {
3419  	__be32 op_to_write;
3420  	__be32 retval_len16;
3421  	union fw_rss_glb_config {
3422  		struct fw_rss_glb_config_manual {
3423  			__be32 mode_pkd;
3424  			__be32 r3;
3425  			__be64 r4;
3426  			__be64 r5;
3427  		} manual;
3428  		struct fw_rss_glb_config_basicvirtual {
3429  			__be32 mode_pkd;
3430  			__be32 synmapen_to_hashtoeplitz;
3431  			__be64 r8;
3432  			__be64 r9;
3433  		} basicvirtual;
3434  	} u;
3435  };
3436  
3437  #define FW_RSS_GLB_CONFIG_CMD_MODE_S	28
3438  #define FW_RSS_GLB_CONFIG_CMD_MODE_M	0xf
3439  #define FW_RSS_GLB_CONFIG_CMD_MODE_V(x)	((x) << FW_RSS_GLB_CONFIG_CMD_MODE_S)
3440  #define FW_RSS_GLB_CONFIG_CMD_MODE_G(x)	\
3441  	(((x) >> FW_RSS_GLB_CONFIG_CMD_MODE_S) & FW_RSS_GLB_CONFIG_CMD_MODE_M)
3442  
3443  #define FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL	0
3444  #define FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL	1
3445  
3446  #define FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_S	8
3447  #define FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_V(x)	\
3448  	((x) << FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_S)
3449  #define FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_F	\
3450  	FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_V(1U)
3451  
3452  #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_S		7
3453  #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_V(x)	\
3454  	((x) << FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_S)
3455  #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_F	\
3456  	FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_V(1U)
3457  
3458  #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_S		6
3459  #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_V(x)	\
3460  	((x) << FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_S)
3461  #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_F	\
3462  	FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_V(1U)
3463  
3464  #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_S		5
3465  #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_V(x)	\
3466  	((x) << FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_S)
3467  #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_F	\
3468  	FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_V(1U)
3469  
3470  #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_S		4
3471  #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_V(x)	\
3472  	((x) << FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_S)
3473  #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_F	\
3474  	FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_V(1U)
3475  
3476  #define FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_S	3
3477  #define FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_V(x)	\
3478  	((x) << FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_S)
3479  #define FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_F	\
3480  	FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_V(1U)
3481  
3482  #define FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_S	2
3483  #define FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_V(x)	\
3484  	((x) << FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_S)
3485  #define FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_F	\
3486  	FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_V(1U)
3487  
3488  #define FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_S	1
3489  #define FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_V(x)	\
3490  	((x) << FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_S)
3491  #define FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_F	\
3492  	FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_V(1U)
3493  
3494  #define FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_S	0
3495  #define FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_V(x)	\
3496  	((x) << FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_S)
3497  #define FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_F	\
3498  	FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_V(1U)
3499  
3500  struct fw_rss_vi_config_cmd {
3501  	__be32 op_to_viid;
3502  #define FW_RSS_VI_CONFIG_CMD_VIID(x) ((x) << 0)
3503  	__be32 retval_len16;
3504  	union fw_rss_vi_config {
3505  		struct fw_rss_vi_config_manual {
3506  			__be64 r3;
3507  			__be64 r4;
3508  			__be64 r5;
3509  		} manual;
3510  		struct fw_rss_vi_config_basicvirtual {
3511  			__be32 r6;
3512  			__be32 defaultq_to_udpen;
3513  			__be64 r9;
3514  			__be64 r10;
3515  		} basicvirtual;
3516  	} u;
3517  };
3518  
3519  #define FW_RSS_VI_CONFIG_CMD_VIID_S	0
3520  #define FW_RSS_VI_CONFIG_CMD_VIID_V(x)	((x) << FW_RSS_VI_CONFIG_CMD_VIID_S)
3521  
3522  #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_S		16
3523  #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_M		0x3ff
3524  #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_V(x)	\
3525  	((x) << FW_RSS_VI_CONFIG_CMD_DEFAULTQ_S)
3526  #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_G(x)	\
3527  	(((x) >> FW_RSS_VI_CONFIG_CMD_DEFAULTQ_S) & \
3528  	 FW_RSS_VI_CONFIG_CMD_DEFAULTQ_M)
3529  
3530  #define FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_S	4
3531  #define FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_V(x)	\
3532  	((x) << FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_S)
3533  #define FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_F	\
3534  	FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_V(1U)
3535  
3536  #define FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_S	3
3537  #define FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_V(x)	\
3538  	((x) << FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_S)
3539  #define FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_F	\
3540  	FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_V(1U)
3541  
3542  #define FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_S	2
3543  #define FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_V(x)	\
3544  	((x) << FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_S)
3545  #define FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_F	\
3546  	FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_V(1U)
3547  
3548  #define FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_S	1
3549  #define FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_V(x)	\
3550  	((x) << FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_S)
3551  #define FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_F	\
3552  	FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_V(1U)
3553  
3554  #define FW_RSS_VI_CONFIG_CMD_UDPEN_S	0
3555  #define FW_RSS_VI_CONFIG_CMD_UDPEN_V(x)	((x) << FW_RSS_VI_CONFIG_CMD_UDPEN_S)
3556  #define FW_RSS_VI_CONFIG_CMD_UDPEN_F	FW_RSS_VI_CONFIG_CMD_UDPEN_V(1U)
3557  
3558  enum fw_sched_sc {
3559  	FW_SCHED_SC_PARAMS		= 1,
3560  };
3561  
3562  struct fw_sched_cmd {
3563  	__be32 op_to_write;
3564  	__be32 retval_len16;
3565  	union fw_sched {
3566  		struct fw_sched_config {
3567  			__u8   sc;
3568  			__u8   type;
3569  			__u8   minmaxen;
3570  			__u8   r3[5];
3571  			__u8   nclasses[4];
3572  			__be32 r4;
3573  		} config;
3574  		struct fw_sched_params {
3575  			__u8   sc;
3576  			__u8   type;
3577  			__u8   level;
3578  			__u8   mode;
3579  			__u8   unit;
3580  			__u8   rate;
3581  			__u8   ch;
3582  			__u8   cl;
3583  			__be32 min;
3584  			__be32 max;
3585  			__be16 weight;
3586  			__be16 pktsize;
3587  			__be16 burstsize;
3588  			__be16 r4;
3589  		} params;
3590  	} u;
3591  };
3592  
3593  struct fw_clip_cmd {
3594  	__be32 op_to_write;
3595  	__be32 alloc_to_len16;
3596  	__be64 ip_hi;
3597  	__be64 ip_lo;
3598  	__be32 r4[2];
3599  };
3600  
3601  #define FW_CLIP_CMD_ALLOC_S     31
3602  #define FW_CLIP_CMD_ALLOC_V(x)  ((x) << FW_CLIP_CMD_ALLOC_S)
3603  #define FW_CLIP_CMD_ALLOC_F     FW_CLIP_CMD_ALLOC_V(1U)
3604  
3605  #define FW_CLIP_CMD_FREE_S      30
3606  #define FW_CLIP_CMD_FREE_V(x)   ((x) << FW_CLIP_CMD_FREE_S)
3607  #define FW_CLIP_CMD_FREE_F      FW_CLIP_CMD_FREE_V(1U)
3608  
3609  enum fw_error_type {
3610  	FW_ERROR_TYPE_EXCEPTION		= 0x0,
3611  	FW_ERROR_TYPE_HWMODULE		= 0x1,
3612  	FW_ERROR_TYPE_WR		= 0x2,
3613  	FW_ERROR_TYPE_ACL		= 0x3,
3614  };
3615  
3616  struct fw_error_cmd {
3617  	__be32 op_to_type;
3618  	__be32 len16_pkd;
3619  	union fw_error {
3620  		struct fw_error_exception {
3621  			__be32 info[6];
3622  		} exception;
3623  		struct fw_error_hwmodule {
3624  			__be32 regaddr;
3625  			__be32 regval;
3626  		} hwmodule;
3627  		struct fw_error_wr {
3628  			__be16 cidx;
3629  			__be16 pfn_vfn;
3630  			__be32 eqid;
3631  			u8 wrhdr[16];
3632  		} wr;
3633  		struct fw_error_acl {
3634  			__be16 cidx;
3635  			__be16 pfn_vfn;
3636  			__be32 eqid;
3637  			__be16 mv_pkd;
3638  			u8 val[6];
3639  			__be64 r4;
3640  		} acl;
3641  	} u;
3642  };
3643  
3644  struct fw_debug_cmd {
3645  	__be32 op_type;
3646  	__be32 len16_pkd;
3647  	union fw_debug {
3648  		struct fw_debug_assert {
3649  			__be32 fcid;
3650  			__be32 line;
3651  			__be32 x;
3652  			__be32 y;
3653  			u8 filename_0_7[8];
3654  			u8 filename_8_15[8];
3655  			__be64 r3;
3656  		} assert;
3657  		struct fw_debug_prt {
3658  			__be16 dprtstridx;
3659  			__be16 r3[3];
3660  			__be32 dprtstrparam0;
3661  			__be32 dprtstrparam1;
3662  			__be32 dprtstrparam2;
3663  			__be32 dprtstrparam3;
3664  		} prt;
3665  	} u;
3666  };
3667  
3668  #define FW_DEBUG_CMD_TYPE_S	0
3669  #define FW_DEBUG_CMD_TYPE_M	0xff
3670  #define FW_DEBUG_CMD_TYPE_G(x)	\
3671  	(((x) >> FW_DEBUG_CMD_TYPE_S) & FW_DEBUG_CMD_TYPE_M)
3672  
3673  struct fw_hma_cmd {
3674  	__be32 op_pkd;
3675  	__be32 retval_len16;
3676  	__be32 mode_to_pcie_params;
3677  	__be32 naddr_size;
3678  	__be32 addr_size_pkd;
3679  	__be32 r6;
3680  	__be64 phy_address[5];
3681  };
3682  
3683  #define FW_HMA_CMD_MODE_S	31
3684  #define FW_HMA_CMD_MODE_M	0x1
3685  #define FW_HMA_CMD_MODE_V(x)	((x) << FW_HMA_CMD_MODE_S)
3686  #define FW_HMA_CMD_MODE_G(x)	\
3687  	(((x) >> FW_HMA_CMD_MODE_S) & FW_HMA_CMD_MODE_M)
3688  #define FW_HMA_CMD_MODE_F	FW_HMA_CMD_MODE_V(1U)
3689  
3690  #define FW_HMA_CMD_SOC_S	30
3691  #define FW_HMA_CMD_SOC_M	0x1
3692  #define FW_HMA_CMD_SOC_V(x)	((x) << FW_HMA_CMD_SOC_S)
3693  #define FW_HMA_CMD_SOC_G(x)	(((x) >> FW_HMA_CMD_SOC_S) & FW_HMA_CMD_SOC_M)
3694  #define FW_HMA_CMD_SOC_F	FW_HMA_CMD_SOC_V(1U)
3695  
3696  #define FW_HMA_CMD_EOC_S	29
3697  #define FW_HMA_CMD_EOC_M	0x1
3698  #define FW_HMA_CMD_EOC_V(x)	((x) << FW_HMA_CMD_EOC_S)
3699  #define FW_HMA_CMD_EOC_G(x)	(((x) >> FW_HMA_CMD_EOC_S) & FW_HMA_CMD_EOC_M)
3700  #define FW_HMA_CMD_EOC_F	FW_HMA_CMD_EOC_V(1U)
3701  
3702  #define FW_HMA_CMD_PCIE_PARAMS_S	0
3703  #define FW_HMA_CMD_PCIE_PARAMS_M	0x7ffffff
3704  #define FW_HMA_CMD_PCIE_PARAMS_V(x)	((x) << FW_HMA_CMD_PCIE_PARAMS_S)
3705  #define FW_HMA_CMD_PCIE_PARAMS_G(x)	\
3706  	(((x) >> FW_HMA_CMD_PCIE_PARAMS_S) & FW_HMA_CMD_PCIE_PARAMS_M)
3707  
3708  #define FW_HMA_CMD_NADDR_S	12
3709  #define FW_HMA_CMD_NADDR_M	0x3f
3710  #define FW_HMA_CMD_NADDR_V(x)	((x) << FW_HMA_CMD_NADDR_S)
3711  #define FW_HMA_CMD_NADDR_G(x)	\
3712  	(((x) >> FW_HMA_CMD_NADDR_S) & FW_HMA_CMD_NADDR_M)
3713  
3714  #define FW_HMA_CMD_SIZE_S	0
3715  #define FW_HMA_CMD_SIZE_M	0xfff
3716  #define FW_HMA_CMD_SIZE_V(x)	((x) << FW_HMA_CMD_SIZE_S)
3717  #define FW_HMA_CMD_SIZE_G(x)	\
3718  	(((x) >> FW_HMA_CMD_SIZE_S) & FW_HMA_CMD_SIZE_M)
3719  
3720  #define FW_HMA_CMD_ADDR_SIZE_S		11
3721  #define FW_HMA_CMD_ADDR_SIZE_M		0x1fffff
3722  #define FW_HMA_CMD_ADDR_SIZE_V(x)	((x) << FW_HMA_CMD_ADDR_SIZE_S)
3723  #define FW_HMA_CMD_ADDR_SIZE_G(x)	\
3724  	(((x) >> FW_HMA_CMD_ADDR_SIZE_S) & FW_HMA_CMD_ADDR_SIZE_M)
3725  
3726  enum pcie_fw_eval {
3727  	PCIE_FW_EVAL_CRASH = 0,
3728  };
3729  
3730  #define PCIE_FW_ERR_S		31
3731  #define PCIE_FW_ERR_V(x)	((x) << PCIE_FW_ERR_S)
3732  #define PCIE_FW_ERR_F		PCIE_FW_ERR_V(1U)
3733  
3734  #define PCIE_FW_INIT_S		30
3735  #define PCIE_FW_INIT_V(x)	((x) << PCIE_FW_INIT_S)
3736  #define PCIE_FW_INIT_F		PCIE_FW_INIT_V(1U)
3737  
3738  #define PCIE_FW_HALT_S          29
3739  #define PCIE_FW_HALT_V(x)       ((x) << PCIE_FW_HALT_S)
3740  #define PCIE_FW_HALT_F          PCIE_FW_HALT_V(1U)
3741  
3742  #define PCIE_FW_EVAL_S		24
3743  #define PCIE_FW_EVAL_M		0x7
3744  #define PCIE_FW_EVAL_G(x)	(((x) >> PCIE_FW_EVAL_S) & PCIE_FW_EVAL_M)
3745  
3746  #define PCIE_FW_MASTER_VLD_S	15
3747  #define PCIE_FW_MASTER_VLD_V(x)	((x) << PCIE_FW_MASTER_VLD_S)
3748  #define PCIE_FW_MASTER_VLD_F	PCIE_FW_MASTER_VLD_V(1U)
3749  
3750  #define PCIE_FW_MASTER_S	12
3751  #define PCIE_FW_MASTER_M	0x7
3752  #define PCIE_FW_MASTER_V(x)	((x) << PCIE_FW_MASTER_S)
3753  #define PCIE_FW_MASTER_G(x)	(((x) >> PCIE_FW_MASTER_S) & PCIE_FW_MASTER_M)
3754  
3755  struct fw_hdr {
3756  	u8 ver;
3757  	u8 chip;			/* terminator chip type */
3758  	__be16	len512;			/* bin length in units of 512-bytes */
3759  	__be32	fw_ver;			/* firmware version */
3760  	__be32	tp_microcode_ver;
3761  	u8 intfver_nic;
3762  	u8 intfver_vnic;
3763  	u8 intfver_ofld;
3764  	u8 intfver_ri;
3765  	u8 intfver_iscsipdu;
3766  	u8 intfver_iscsi;
3767  	u8 intfver_fcoepdu;
3768  	u8 intfver_fcoe;
3769  	__u32   reserved2;
3770  	__u32   reserved3;
3771  	__u32   reserved4;
3772  	__be32  flags;
3773  	__be32  reserved6[23];
3774  };
3775  
3776  enum fw_hdr_chip {
3777  	FW_HDR_CHIP_T4,
3778  	FW_HDR_CHIP_T5,
3779  	FW_HDR_CHIP_T6
3780  };
3781  
3782  #define FW_HDR_FW_VER_MAJOR_S	24
3783  #define FW_HDR_FW_VER_MAJOR_M	0xff
3784  #define FW_HDR_FW_VER_MAJOR_V(x) \
3785  	((x) << FW_HDR_FW_VER_MAJOR_S)
3786  #define FW_HDR_FW_VER_MAJOR_G(x) \
3787  	(((x) >> FW_HDR_FW_VER_MAJOR_S) & FW_HDR_FW_VER_MAJOR_M)
3788  
3789  #define FW_HDR_FW_VER_MINOR_S	16
3790  #define FW_HDR_FW_VER_MINOR_M	0xff
3791  #define FW_HDR_FW_VER_MINOR_V(x) \
3792  	((x) << FW_HDR_FW_VER_MINOR_S)
3793  #define FW_HDR_FW_VER_MINOR_G(x) \
3794  	(((x) >> FW_HDR_FW_VER_MINOR_S) & FW_HDR_FW_VER_MINOR_M)
3795  
3796  #define FW_HDR_FW_VER_MICRO_S	8
3797  #define FW_HDR_FW_VER_MICRO_M	0xff
3798  #define FW_HDR_FW_VER_MICRO_V(x) \
3799  	((x) << FW_HDR_FW_VER_MICRO_S)
3800  #define FW_HDR_FW_VER_MICRO_G(x) \
3801  	(((x) >> FW_HDR_FW_VER_MICRO_S) & FW_HDR_FW_VER_MICRO_M)
3802  
3803  #define FW_HDR_FW_VER_BUILD_S	0
3804  #define FW_HDR_FW_VER_BUILD_M	0xff
3805  #define FW_HDR_FW_VER_BUILD_V(x) \
3806  	((x) << FW_HDR_FW_VER_BUILD_S)
3807  #define FW_HDR_FW_VER_BUILD_G(x) \
3808  	(((x) >> FW_HDR_FW_VER_BUILD_S) & FW_HDR_FW_VER_BUILD_M)
3809  
3810  enum fw_hdr_intfver {
3811  	FW_HDR_INTFVER_NIC      = 0x00,
3812  	FW_HDR_INTFVER_VNIC     = 0x00,
3813  	FW_HDR_INTFVER_OFLD     = 0x00,
3814  	FW_HDR_INTFVER_RI       = 0x00,
3815  	FW_HDR_INTFVER_ISCSIPDU = 0x00,
3816  	FW_HDR_INTFVER_ISCSI    = 0x00,
3817  	FW_HDR_INTFVER_FCOEPDU  = 0x00,
3818  	FW_HDR_INTFVER_FCOE     = 0x00,
3819  };
3820  
3821  enum fw_hdr_flags {
3822  	FW_HDR_FLAGS_RESET_HALT = 0x00000001,
3823  };
3824  
3825  /* length of the formatting string  */
3826  #define FW_DEVLOG_FMT_LEN	192
3827  
3828  /* maximum number of the formatting string parameters */
3829  #define FW_DEVLOG_FMT_PARAMS_NUM 8
3830  
3831  /* priority levels */
3832  enum fw_devlog_level {
3833  	FW_DEVLOG_LEVEL_EMERG	= 0x0,
3834  	FW_DEVLOG_LEVEL_CRIT	= 0x1,
3835  	FW_DEVLOG_LEVEL_ERR	= 0x2,
3836  	FW_DEVLOG_LEVEL_NOTICE	= 0x3,
3837  	FW_DEVLOG_LEVEL_INFO	= 0x4,
3838  	FW_DEVLOG_LEVEL_DEBUG	= 0x5,
3839  	FW_DEVLOG_LEVEL_MAX	= 0x5,
3840  };
3841  
3842  /* facilities that may send a log message */
3843  enum fw_devlog_facility {
3844  	FW_DEVLOG_FACILITY_CORE		= 0x00,
3845  	FW_DEVLOG_FACILITY_CF		= 0x01,
3846  	FW_DEVLOG_FACILITY_SCHED	= 0x02,
3847  	FW_DEVLOG_FACILITY_TIMER	= 0x04,
3848  	FW_DEVLOG_FACILITY_RES		= 0x06,
3849  	FW_DEVLOG_FACILITY_HW		= 0x08,
3850  	FW_DEVLOG_FACILITY_FLR		= 0x10,
3851  	FW_DEVLOG_FACILITY_DMAQ		= 0x12,
3852  	FW_DEVLOG_FACILITY_PHY		= 0x14,
3853  	FW_DEVLOG_FACILITY_MAC		= 0x16,
3854  	FW_DEVLOG_FACILITY_PORT		= 0x18,
3855  	FW_DEVLOG_FACILITY_VI		= 0x1A,
3856  	FW_DEVLOG_FACILITY_FILTER	= 0x1C,
3857  	FW_DEVLOG_FACILITY_ACL		= 0x1E,
3858  	FW_DEVLOG_FACILITY_TM		= 0x20,
3859  	FW_DEVLOG_FACILITY_QFC		= 0x22,
3860  	FW_DEVLOG_FACILITY_DCB		= 0x24,
3861  	FW_DEVLOG_FACILITY_ETH		= 0x26,
3862  	FW_DEVLOG_FACILITY_OFLD		= 0x28,
3863  	FW_DEVLOG_FACILITY_RI		= 0x2A,
3864  	FW_DEVLOG_FACILITY_ISCSI	= 0x2C,
3865  	FW_DEVLOG_FACILITY_FCOE		= 0x2E,
3866  	FW_DEVLOG_FACILITY_FOISCSI	= 0x30,
3867  	FW_DEVLOG_FACILITY_FOFCOE	= 0x32,
3868  	FW_DEVLOG_FACILITY_CHNET        = 0x34,
3869  	FW_DEVLOG_FACILITY_MAX          = 0x34,
3870  };
3871  
3872  /* log message format */
3873  struct fw_devlog_e {
3874  	__be64	timestamp;
3875  	__be32	seqno;
3876  	__be16	reserved1;
3877  	__u8	level;
3878  	__u8	facility;
3879  	__u8	fmt[FW_DEVLOG_FMT_LEN];
3880  	__be32	params[FW_DEVLOG_FMT_PARAMS_NUM];
3881  	__be32	reserved3[4];
3882  };
3883  
3884  struct fw_devlog_cmd {
3885  	__be32 op_to_write;
3886  	__be32 retval_len16;
3887  	__u8   level;
3888  	__u8   r2[7];
3889  	__be32 memtype_devlog_memaddr16_devlog;
3890  	__be32 memsize_devlog;
3891  	__be32 r3[2];
3892  };
3893  
3894  #define FW_DEVLOG_CMD_MEMTYPE_DEVLOG_S		28
3895  #define FW_DEVLOG_CMD_MEMTYPE_DEVLOG_M		0xf
3896  #define FW_DEVLOG_CMD_MEMTYPE_DEVLOG_G(x)	\
3897  	(((x) >> FW_DEVLOG_CMD_MEMTYPE_DEVLOG_S) & \
3898  	 FW_DEVLOG_CMD_MEMTYPE_DEVLOG_M)
3899  
3900  #define FW_DEVLOG_CMD_MEMADDR16_DEVLOG_S	0
3901  #define FW_DEVLOG_CMD_MEMADDR16_DEVLOG_M	0xfffffff
3902  #define FW_DEVLOG_CMD_MEMADDR16_DEVLOG_G(x)	\
3903  	(((x) >> FW_DEVLOG_CMD_MEMADDR16_DEVLOG_S) & \
3904  	 FW_DEVLOG_CMD_MEMADDR16_DEVLOG_M)
3905  
3906  /* P C I E   F W   P F 7   R E G I S T E R */
3907  
3908  /* PF7 stores the Firmware Device Log parameters which allows Host Drivers to
3909   * access the "devlog" which needing to contact firmware.  The encoding is
3910   * mostly the same as that returned by the DEVLOG command except for the size
3911   * which is encoded as the number of entries in multiples-1 of 128 here rather
3912   * than the memory size as is done in the DEVLOG command.  Thus, 0 means 128
3913   * and 15 means 2048.  This of course in turn constrains the allowed values
3914   * for the devlog size ...
3915   */
3916  #define PCIE_FW_PF_DEVLOG		7
3917  
3918  #define PCIE_FW_PF_DEVLOG_NENTRIES128_S	28
3919  #define PCIE_FW_PF_DEVLOG_NENTRIES128_M	0xf
3920  #define PCIE_FW_PF_DEVLOG_NENTRIES128_V(x) \
3921  	((x) << PCIE_FW_PF_DEVLOG_NENTRIES128_S)
3922  #define PCIE_FW_PF_DEVLOG_NENTRIES128_G(x) \
3923  	(((x) >> PCIE_FW_PF_DEVLOG_NENTRIES128_S) & \
3924  	 PCIE_FW_PF_DEVLOG_NENTRIES128_M)
3925  
3926  #define PCIE_FW_PF_DEVLOG_ADDR16_S	4
3927  #define PCIE_FW_PF_DEVLOG_ADDR16_M	0xffffff
3928  #define PCIE_FW_PF_DEVLOG_ADDR16_V(x)	((x) << PCIE_FW_PF_DEVLOG_ADDR16_S)
3929  #define PCIE_FW_PF_DEVLOG_ADDR16_G(x) \
3930  	(((x) >> PCIE_FW_PF_DEVLOG_ADDR16_S) & PCIE_FW_PF_DEVLOG_ADDR16_M)
3931  
3932  #define PCIE_FW_PF_DEVLOG_MEMTYPE_S	0
3933  #define PCIE_FW_PF_DEVLOG_MEMTYPE_M	0xf
3934  #define PCIE_FW_PF_DEVLOG_MEMTYPE_V(x)	((x) << PCIE_FW_PF_DEVLOG_MEMTYPE_S)
3935  #define PCIE_FW_PF_DEVLOG_MEMTYPE_G(x) \
3936  	(((x) >> PCIE_FW_PF_DEVLOG_MEMTYPE_S) & PCIE_FW_PF_DEVLOG_MEMTYPE_M)
3937  
3938  #define MAX_IMM_OFLD_TX_DATA_WR_LEN (0xff + sizeof(struct fw_ofld_tx_data_wr))
3939  
3940  struct fw_crypto_lookaside_wr {
3941  	__be32 op_to_cctx_size;
3942  	__be32 len16_pkd;
3943  	__be32 session_id;
3944  	__be32 rx_chid_to_rx_q_id;
3945  	__be32 key_addr;
3946  	__be32 pld_size_hash_size;
3947  	__be64 cookie;
3948  };
3949  
3950  #define FW_CRYPTO_LOOKASIDE_WR_OPCODE_S 24
3951  #define FW_CRYPTO_LOOKASIDE_WR_OPCODE_M 0xff
3952  #define FW_CRYPTO_LOOKASIDE_WR_OPCODE_V(x) \
3953  	((x) << FW_CRYPTO_LOOKASIDE_WR_OPCODE_S)
3954  #define FW_CRYPTO_LOOKASIDE_WR_OPCODE_G(x) \
3955  	(((x) >> FW_CRYPTO_LOOKASIDE_WR_OPCODE_S) & \
3956  	 FW_CRYPTO_LOOKASIDE_WR_OPCODE_M)
3957  
3958  #define FW_CRYPTO_LOOKASIDE_WR_COMPL_S 23
3959  #define FW_CRYPTO_LOOKASIDE_WR_COMPL_M 0x1
3960  #define FW_CRYPTO_LOOKASIDE_WR_COMPL_V(x) \
3961  	((x) << FW_CRYPTO_LOOKASIDE_WR_COMPL_S)
3962  #define FW_CRYPTO_LOOKASIDE_WR_COMPL_G(x) \
3963  	(((x) >> FW_CRYPTO_LOOKASIDE_WR_COMPL_S) & \
3964  	 FW_CRYPTO_LOOKASIDE_WR_COMPL_M)
3965  #define FW_CRYPTO_LOOKASIDE_WR_COMPL_F FW_CRYPTO_LOOKASIDE_WR_COMPL_V(1U)
3966  
3967  #define FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_S 15
3968  #define FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_M 0xff
3969  #define FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_V(x) \
3970  	((x) << FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_S)
3971  #define FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_G(x) \
3972  	(((x) >> FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_S) & \
3973  	 FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_M)
3974  
3975  #define FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_S 5
3976  #define FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_M 0x3
3977  #define FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_V(x) \
3978  	((x) << FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_S)
3979  #define FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_G(x) \
3980  	(((x) >> FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_S) & \
3981  	 FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_M)
3982  
3983  #define FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_S 0
3984  #define FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_M 0x1f
3985  #define FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_V(x) \
3986  	((x) << FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_S)
3987  #define FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_G(x) \
3988  	(((x) >> FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_S) & \
3989  	 FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_M)
3990  
3991  #define FW_CRYPTO_LOOKASIDE_WR_LEN16_S 0
3992  #define FW_CRYPTO_LOOKASIDE_WR_LEN16_M 0xff
3993  #define FW_CRYPTO_LOOKASIDE_WR_LEN16_V(x) \
3994  	((x) << FW_CRYPTO_LOOKASIDE_WR_LEN16_S)
3995  #define FW_CRYPTO_LOOKASIDE_WR_LEN16_G(x) \
3996  	(((x) >> FW_CRYPTO_LOOKASIDE_WR_LEN16_S) & \
3997  	 FW_CRYPTO_LOOKASIDE_WR_LEN16_M)
3998  
3999  #define FW_CRYPTO_LOOKASIDE_WR_RX_CHID_S 29
4000  #define FW_CRYPTO_LOOKASIDE_WR_RX_CHID_M 0x3
4001  #define FW_CRYPTO_LOOKASIDE_WR_RX_CHID_V(x) \
4002  	((x) << FW_CRYPTO_LOOKASIDE_WR_RX_CHID_S)
4003  #define FW_CRYPTO_LOOKASIDE_WR_RX_CHID_G(x) \
4004  	(((x) >> FW_CRYPTO_LOOKASIDE_WR_RX_CHID_S) & \
4005  	 FW_CRYPTO_LOOKASIDE_WR_RX_CHID_M)
4006  
4007  #define FW_CRYPTO_LOOKASIDE_WR_LCB_S  27
4008  #define FW_CRYPTO_LOOKASIDE_WR_LCB_M  0x3
4009  #define FW_CRYPTO_LOOKASIDE_WR_LCB_V(x) \
4010  	((x) << FW_CRYPTO_LOOKASIDE_WR_LCB_S)
4011  #define FW_CRYPTO_LOOKASIDE_WR_LCB_G(x) \
4012  	(((x) >> FW_CRYPTO_LOOKASIDE_WR_LCB_S) & FW_CRYPTO_LOOKASIDE_WR_LCB_M)
4013  
4014  #define FW_CRYPTO_LOOKASIDE_WR_PHASH_S 25
4015  #define FW_CRYPTO_LOOKASIDE_WR_PHASH_M 0x3
4016  #define FW_CRYPTO_LOOKASIDE_WR_PHASH_V(x) \
4017  	((x) << FW_CRYPTO_LOOKASIDE_WR_PHASH_S)
4018  #define FW_CRYPTO_LOOKASIDE_WR_PHASH_G(x) \
4019  	(((x) >> FW_CRYPTO_LOOKASIDE_WR_PHASH_S) & \
4020  	 FW_CRYPTO_LOOKASIDE_WR_PHASH_M)
4021  
4022  #define FW_CRYPTO_LOOKASIDE_WR_IV_S   23
4023  #define FW_CRYPTO_LOOKASIDE_WR_IV_M   0x3
4024  #define FW_CRYPTO_LOOKASIDE_WR_IV_V(x) \
4025  	((x) << FW_CRYPTO_LOOKASIDE_WR_IV_S)
4026  #define FW_CRYPTO_LOOKASIDE_WR_IV_G(x) \
4027  	(((x) >> FW_CRYPTO_LOOKASIDE_WR_IV_S) & FW_CRYPTO_LOOKASIDE_WR_IV_M)
4028  
4029  #define FW_CRYPTO_LOOKASIDE_WR_FQIDX_S   15
4030  #define FW_CRYPTO_LOOKASIDE_WR_FQIDX_M   0xff
4031  #define FW_CRYPTO_LOOKASIDE_WR_FQIDX_V(x) \
4032  	((x) << FW_CRYPTO_LOOKASIDE_WR_FQIDX_S)
4033  #define FW_CRYPTO_LOOKASIDE_WR_FQIDX_G(x) \
4034  	(((x) >> FW_CRYPTO_LOOKASIDE_WR_FQIDX_S) & \
4035  	 FW_CRYPTO_LOOKASIDE_WR_FQIDX_M)
4036  
4037  #define FW_CRYPTO_LOOKASIDE_WR_TX_CH_S 10
4038  #define FW_CRYPTO_LOOKASIDE_WR_TX_CH_M 0x3
4039  #define FW_CRYPTO_LOOKASIDE_WR_TX_CH_V(x) \
4040  	((x) << FW_CRYPTO_LOOKASIDE_WR_TX_CH_S)
4041  #define FW_CRYPTO_LOOKASIDE_WR_TX_CH_G(x) \
4042  	(((x) >> FW_CRYPTO_LOOKASIDE_WR_TX_CH_S) & \
4043  	 FW_CRYPTO_LOOKASIDE_WR_TX_CH_M)
4044  
4045  #define FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_S 0
4046  #define FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_M 0x3ff
4047  #define FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_V(x) \
4048  	((x) << FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_S)
4049  #define FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_G(x) \
4050  	(((x) >> FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_S) & \
4051  	 FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_M)
4052  
4053  #define FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_S 24
4054  #define FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_M 0xff
4055  #define FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_V(x) \
4056  	((x) << FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_S)
4057  #define FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_G(x) \
4058  	(((x) >> FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_S) & \
4059  	 FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_M)
4060  
4061  #define FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_S 17
4062  #define FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_M 0x7f
4063  #define FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_V(x) \
4064  	((x) << FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_S)
4065  #define FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_G(x) \
4066  	(((x) >> FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_S) & \
4067  	 FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_M)
4068  
4069  struct fw_tlstx_data_wr {
4070  	__be32 op_to_immdlen;
4071  	__be32 flowid_len16;
4072  	__be32 plen;
4073  	__be32 lsodisable_to_flags;
4074  	__be32 r5;
4075  	__be32 ctxloc_to_exp;
4076  	__be16 mfs;
4077  	__be16 adjustedplen_pkd;
4078  	__be16 expinplenmax_pkd;
4079  	u8   pdusinplenmax_pkd;
4080  	u8   r10;
4081  };
4082  
4083  #define FW_TLSTX_DATA_WR_OPCODE_S       24
4084  #define FW_TLSTX_DATA_WR_OPCODE_M       0xff
4085  #define FW_TLSTX_DATA_WR_OPCODE_V(x)    ((x) << FW_TLSTX_DATA_WR_OPCODE_S)
4086  #define FW_TLSTX_DATA_WR_OPCODE_G(x)    \
4087  	(((x) >> FW_TLSTX_DATA_WR_OPCODE_S) & FW_TLSTX_DATA_WR_OPCODE_M)
4088  
4089  #define FW_TLSTX_DATA_WR_COMPL_S        21
4090  #define FW_TLSTX_DATA_WR_COMPL_M        0x1
4091  #define FW_TLSTX_DATA_WR_COMPL_V(x)     ((x) << FW_TLSTX_DATA_WR_COMPL_S)
4092  #define FW_TLSTX_DATA_WR_COMPL_G(x)     \
4093  	(((x) >> FW_TLSTX_DATA_WR_COMPL_S) & FW_TLSTX_DATA_WR_COMPL_M)
4094  #define FW_TLSTX_DATA_WR_COMPL_F        FW_TLSTX_DATA_WR_COMPL_V(1U)
4095  
4096  #define FW_TLSTX_DATA_WR_IMMDLEN_S      0
4097  #define FW_TLSTX_DATA_WR_IMMDLEN_M      0xff
4098  #define FW_TLSTX_DATA_WR_IMMDLEN_V(x)   ((x) << FW_TLSTX_DATA_WR_IMMDLEN_S)
4099  #define FW_TLSTX_DATA_WR_IMMDLEN_G(x)   \
4100  	(((x) >> FW_TLSTX_DATA_WR_IMMDLEN_S) & FW_TLSTX_DATA_WR_IMMDLEN_M)
4101  
4102  #define FW_TLSTX_DATA_WR_FLOWID_S       8
4103  #define FW_TLSTX_DATA_WR_FLOWID_M       0xfffff
4104  #define FW_TLSTX_DATA_WR_FLOWID_V(x)    ((x) << FW_TLSTX_DATA_WR_FLOWID_S)
4105  #define FW_TLSTX_DATA_WR_FLOWID_G(x)    \
4106  	(((x) >> FW_TLSTX_DATA_WR_FLOWID_S) & FW_TLSTX_DATA_WR_FLOWID_M)
4107  
4108  #define FW_TLSTX_DATA_WR_LEN16_S        0
4109  #define FW_TLSTX_DATA_WR_LEN16_M        0xff
4110  #define FW_TLSTX_DATA_WR_LEN16_V(x)     ((x) << FW_TLSTX_DATA_WR_LEN16_S)
4111  #define FW_TLSTX_DATA_WR_LEN16_G(x)     \
4112  	(((x) >> FW_TLSTX_DATA_WR_LEN16_S) & FW_TLSTX_DATA_WR_LEN16_M)
4113  
4114  #define FW_TLSTX_DATA_WR_LSODISABLE_S   31
4115  #define FW_TLSTX_DATA_WR_LSODISABLE_M   0x1
4116  #define FW_TLSTX_DATA_WR_LSODISABLE_V(x) \
4117  	((x) << FW_TLSTX_DATA_WR_LSODISABLE_S)
4118  #define FW_TLSTX_DATA_WR_LSODISABLE_G(x) \
4119  	(((x) >> FW_TLSTX_DATA_WR_LSODISABLE_S) & FW_TLSTX_DATA_WR_LSODISABLE_M)
4120  #define FW_TLSTX_DATA_WR_LSODISABLE_F   FW_TLSTX_DATA_WR_LSODISABLE_V(1U)
4121  
4122  #define FW_TLSTX_DATA_WR_ALIGNPLD_S     30
4123  #define FW_TLSTX_DATA_WR_ALIGNPLD_M     0x1
4124  #define FW_TLSTX_DATA_WR_ALIGNPLD_V(x)  ((x) << FW_TLSTX_DATA_WR_ALIGNPLD_S)
4125  #define FW_TLSTX_DATA_WR_ALIGNPLD_G(x)  \
4126  	(((x) >> FW_TLSTX_DATA_WR_ALIGNPLD_S) & FW_TLSTX_DATA_WR_ALIGNPLD_M)
4127  #define FW_TLSTX_DATA_WR_ALIGNPLD_F     FW_TLSTX_DATA_WR_ALIGNPLD_V(1U)
4128  
4129  #define FW_TLSTX_DATA_WR_ALIGNPLDSHOVE_S 29
4130  #define FW_TLSTX_DATA_WR_ALIGNPLDSHOVE_M 0x1
4131  #define FW_TLSTX_DATA_WR_ALIGNPLDSHOVE_V(x) \
4132  	((x) << FW_TLSTX_DATA_WR_ALIGNPLDSHOVE_S)
4133  #define FW_TLSTX_DATA_WR_ALIGNPLDSHOVE_G(x) \
4134  	(((x) >> FW_TLSTX_DATA_WR_ALIGNPLDSHOVE_S) & \
4135  	FW_TLSTX_DATA_WR_ALIGNPLDSHOVE_M)
4136  #define FW_TLSTX_DATA_WR_ALIGNPLDSHOVE_F FW_TLSTX_DATA_WR_ALIGNPLDSHOVE_V(1U)
4137  
4138  #define FW_TLSTX_DATA_WR_FLAGS_S        0
4139  #define FW_TLSTX_DATA_WR_FLAGS_M        0xfffffff
4140  #define FW_TLSTX_DATA_WR_FLAGS_V(x)     ((x) << FW_TLSTX_DATA_WR_FLAGS_S)
4141  #define FW_TLSTX_DATA_WR_FLAGS_G(x)     \
4142  	(((x) >> FW_TLSTX_DATA_WR_FLAGS_S) & FW_TLSTX_DATA_WR_FLAGS_M)
4143  
4144  #define FW_TLSTX_DATA_WR_CTXLOC_S       30
4145  #define FW_TLSTX_DATA_WR_CTXLOC_M       0x3
4146  #define FW_TLSTX_DATA_WR_CTXLOC_V(x)    ((x) << FW_TLSTX_DATA_WR_CTXLOC_S)
4147  #define FW_TLSTX_DATA_WR_CTXLOC_G(x)    \
4148  	(((x) >> FW_TLSTX_DATA_WR_CTXLOC_S) & FW_TLSTX_DATA_WR_CTXLOC_M)
4149  
4150  #define FW_TLSTX_DATA_WR_IVDSGL_S       29
4151  #define FW_TLSTX_DATA_WR_IVDSGL_M       0x1
4152  #define FW_TLSTX_DATA_WR_IVDSGL_V(x)    ((x) << FW_TLSTX_DATA_WR_IVDSGL_S)
4153  #define FW_TLSTX_DATA_WR_IVDSGL_G(x)    \
4154  	(((x) >> FW_TLSTX_DATA_WR_IVDSGL_S) & FW_TLSTX_DATA_WR_IVDSGL_M)
4155  #define FW_TLSTX_DATA_WR_IVDSGL_F       FW_TLSTX_DATA_WR_IVDSGL_V(1U)
4156  
4157  #define FW_TLSTX_DATA_WR_KEYSIZE_S      24
4158  #define FW_TLSTX_DATA_WR_KEYSIZE_M      0x1f
4159  #define FW_TLSTX_DATA_WR_KEYSIZE_V(x)   ((x) << FW_TLSTX_DATA_WR_KEYSIZE_S)
4160  #define FW_TLSTX_DATA_WR_KEYSIZE_G(x)   \
4161  	(((x) >> FW_TLSTX_DATA_WR_KEYSIZE_S) & FW_TLSTX_DATA_WR_KEYSIZE_M)
4162  
4163  #define FW_TLSTX_DATA_WR_NUMIVS_S       14
4164  #define FW_TLSTX_DATA_WR_NUMIVS_M       0xff
4165  #define FW_TLSTX_DATA_WR_NUMIVS_V(x)    ((x) << FW_TLSTX_DATA_WR_NUMIVS_S)
4166  #define FW_TLSTX_DATA_WR_NUMIVS_G(x)    \
4167  	(((x) >> FW_TLSTX_DATA_WR_NUMIVS_S) & FW_TLSTX_DATA_WR_NUMIVS_M)
4168  
4169  #define FW_TLSTX_DATA_WR_EXP_S          0
4170  #define FW_TLSTX_DATA_WR_EXP_M          0x3fff
4171  #define FW_TLSTX_DATA_WR_EXP_V(x)       ((x) << FW_TLSTX_DATA_WR_EXP_S)
4172  #define FW_TLSTX_DATA_WR_EXP_G(x)       \
4173  	(((x) >> FW_TLSTX_DATA_WR_EXP_S) & FW_TLSTX_DATA_WR_EXP_M)
4174  
4175  #define FW_TLSTX_DATA_WR_ADJUSTEDPLEN_S 1
4176  #define FW_TLSTX_DATA_WR_ADJUSTEDPLEN_V(x) \
4177  	((x) << FW_TLSTX_DATA_WR_ADJUSTEDPLEN_S)
4178  
4179  #define FW_TLSTX_DATA_WR_EXPINPLENMAX_S 4
4180  #define FW_TLSTX_DATA_WR_EXPINPLENMAX_V(x) \
4181  	((x) << FW_TLSTX_DATA_WR_EXPINPLENMAX_S)
4182  
4183  #define FW_TLSTX_DATA_WR_PDUSINPLENMAX_S 2
4184  #define FW_TLSTX_DATA_WR_PDUSINPLENMAX_V(x) \
4185  	((x) << FW_TLSTX_DATA_WR_PDUSINPLENMAX_S)
4186  
4187  #endif /* _T4FW_INTERFACE_H_ */
4188