1 /*
2 * S390x MMU related functions
3 *
4 * Copyright (c) 2011 Alexander Graf
5 * Copyright (c) 2015 Thomas Huth, IBM Corporation
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18 #include "qemu/osdep.h"
19 #include "qemu/error-report.h"
20 #include "exec/address-spaces.h"
21 #include "cpu.h"
22 #include "s390x-internal.h"
23 #include "kvm/kvm_s390x.h"
24 #include "sysemu/kvm.h"
25 #include "sysemu/tcg.h"
26 #include "exec/exec-all.h"
27 #include "exec/page-protection.h"
28 #include "hw/hw.h"
29 #include "hw/s390x/storage-keys.h"
30 #include "hw/boards.h"
31
32 /* Fetch/store bits in the translation exception code: */
33 #define FS_READ 0x800
34 #define FS_WRITE 0x400
35
trigger_access_exception(CPUS390XState * env,uint32_t type,uint64_t tec)36 static void trigger_access_exception(CPUS390XState *env, uint32_t type,
37 uint64_t tec)
38 {
39 S390CPU *cpu = env_archcpu(env);
40
41 if (kvm_enabled()) {
42 kvm_s390_access_exception(cpu, type, tec);
43 } else {
44 CPUState *cs = env_cpu(env);
45 if (type != PGM_ADDRESSING) {
46 stq_phys(cs->as, env->psa + offsetof(LowCore, trans_exc_code), tec);
47 }
48 trigger_pgm_exception(env, type);
49 }
50 }
51
52 /* check whether the address would be proteted by Low-Address Protection */
is_low_address(uint64_t addr)53 static bool is_low_address(uint64_t addr)
54 {
55 return addr <= 511 || (addr >= 4096 && addr <= 4607);
56 }
57
58 /* check whether Low-Address Protection is enabled for mmu_translate() */
lowprot_enabled(const CPUS390XState * env,uint64_t asc)59 static bool lowprot_enabled(const CPUS390XState *env, uint64_t asc)
60 {
61 if (!(env->cregs[0] & CR0_LOWPROT)) {
62 return false;
63 }
64 if (!(env->psw.mask & PSW_MASK_DAT)) {
65 return true;
66 }
67
68 /* Check the private-space control bit */
69 switch (asc) {
70 case PSW_ASC_PRIMARY:
71 return !(env->cregs[1] & ASCE_PRIVATE_SPACE);
72 case PSW_ASC_SECONDARY:
73 return !(env->cregs[7] & ASCE_PRIVATE_SPACE);
74 case PSW_ASC_HOME:
75 return !(env->cregs[13] & ASCE_PRIVATE_SPACE);
76 default:
77 /* We don't support access register mode */
78 error_report("unsupported addressing mode");
79 exit(1);
80 }
81 }
82
83 /**
84 * Translate real address to absolute (= physical)
85 * address by taking care of the prefix mapping.
86 */
mmu_real2abs(CPUS390XState * env,target_ulong raddr)87 target_ulong mmu_real2abs(CPUS390XState *env, target_ulong raddr)
88 {
89 if (raddr < 0x2000) {
90 return raddr + env->psa; /* Map the lowcore. */
91 } else if (raddr >= env->psa && raddr < env->psa + 0x2000) {
92 return raddr - env->psa; /* Map the 0 page. */
93 }
94 return raddr;
95 }
96
mmu_absolute_addr_valid(target_ulong addr,bool is_write)97 bool mmu_absolute_addr_valid(target_ulong addr, bool is_write)
98 {
99 return address_space_access_valid(&address_space_memory,
100 addr & TARGET_PAGE_MASK,
101 TARGET_PAGE_SIZE, is_write,
102 MEMTXATTRS_UNSPECIFIED);
103 }
104
read_table_entry(CPUS390XState * env,hwaddr gaddr,uint64_t * entry)105 static inline bool read_table_entry(CPUS390XState *env, hwaddr gaddr,
106 uint64_t *entry)
107 {
108 CPUState *cs = env_cpu(env);
109
110 /*
111 * According to the PoP, these table addresses are "unpredictably real
112 * or absolute". Also, "it is unpredictable whether the address wraps
113 * or an addressing exception is recognized".
114 *
115 * We treat them as absolute addresses and don't wrap them.
116 */
117 if (unlikely(address_space_read(cs->as, gaddr, MEMTXATTRS_UNSPECIFIED,
118 entry, sizeof(*entry)) !=
119 MEMTX_OK)) {
120 return false;
121 }
122 *entry = be64_to_cpu(*entry);
123 return true;
124 }
125
mmu_translate_asce(CPUS390XState * env,target_ulong vaddr,uint64_t asc,uint64_t asce,target_ulong * raddr,int * flags)126 static int mmu_translate_asce(CPUS390XState *env, target_ulong vaddr,
127 uint64_t asc, uint64_t asce, target_ulong *raddr,
128 int *flags)
129 {
130 const bool edat1 = (env->cregs[0] & CR0_EDAT) &&
131 s390_has_feat(S390_FEAT_EDAT);
132 const bool edat2 = edat1 && s390_has_feat(S390_FEAT_EDAT_2);
133 const bool iep = (env->cregs[0] & CR0_IEP) &&
134 s390_has_feat(S390_FEAT_INSTRUCTION_EXEC_PROT);
135 const int asce_tl = asce & ASCE_TABLE_LENGTH;
136 const int asce_p = asce & ASCE_PRIVATE_SPACE;
137 hwaddr gaddr = asce & ASCE_ORIGIN;
138 uint64_t entry;
139
140 if (asce & ASCE_REAL_SPACE) {
141 /* direct mapping */
142 *raddr = vaddr;
143 return 0;
144 }
145
146 switch (asce & ASCE_TYPE_MASK) {
147 case ASCE_TYPE_REGION1:
148 if (VADDR_REGION1_TL(vaddr) > asce_tl) {
149 return PGM_REG_FIRST_TRANS;
150 }
151 gaddr += VADDR_REGION1_TX(vaddr) * 8;
152 break;
153 case ASCE_TYPE_REGION2:
154 if (VADDR_REGION1_TX(vaddr)) {
155 return PGM_ASCE_TYPE;
156 }
157 if (VADDR_REGION2_TL(vaddr) > asce_tl) {
158 return PGM_REG_SEC_TRANS;
159 }
160 gaddr += VADDR_REGION2_TX(vaddr) * 8;
161 break;
162 case ASCE_TYPE_REGION3:
163 if (VADDR_REGION1_TX(vaddr) || VADDR_REGION2_TX(vaddr)) {
164 return PGM_ASCE_TYPE;
165 }
166 if (VADDR_REGION3_TL(vaddr) > asce_tl) {
167 return PGM_REG_THIRD_TRANS;
168 }
169 gaddr += VADDR_REGION3_TX(vaddr) * 8;
170 break;
171 case ASCE_TYPE_SEGMENT:
172 if (VADDR_REGION1_TX(vaddr) || VADDR_REGION2_TX(vaddr) ||
173 VADDR_REGION3_TX(vaddr)) {
174 return PGM_ASCE_TYPE;
175 }
176 if (VADDR_SEGMENT_TL(vaddr) > asce_tl) {
177 return PGM_SEGMENT_TRANS;
178 }
179 gaddr += VADDR_SEGMENT_TX(vaddr) * 8;
180 break;
181 }
182
183 switch (asce & ASCE_TYPE_MASK) {
184 case ASCE_TYPE_REGION1:
185 if (!read_table_entry(env, gaddr, &entry)) {
186 return PGM_ADDRESSING;
187 }
188 if (entry & REGION_ENTRY_I) {
189 return PGM_REG_FIRST_TRANS;
190 }
191 if ((entry & REGION_ENTRY_TT) != REGION_ENTRY_TT_REGION1) {
192 return PGM_TRANS_SPEC;
193 }
194 if (VADDR_REGION2_TL(vaddr) < (entry & REGION_ENTRY_TF) >> 6 ||
195 VADDR_REGION2_TL(vaddr) > (entry & REGION_ENTRY_TL)) {
196 return PGM_REG_SEC_TRANS;
197 }
198 if (edat1 && (entry & REGION_ENTRY_P)) {
199 *flags &= ~PAGE_WRITE;
200 }
201 gaddr = (entry & REGION_ENTRY_ORIGIN) + VADDR_REGION2_TX(vaddr) * 8;
202 /* fall through */
203 case ASCE_TYPE_REGION2:
204 if (!read_table_entry(env, gaddr, &entry)) {
205 return PGM_ADDRESSING;
206 }
207 if (entry & REGION_ENTRY_I) {
208 return PGM_REG_SEC_TRANS;
209 }
210 if ((entry & REGION_ENTRY_TT) != REGION_ENTRY_TT_REGION2) {
211 return PGM_TRANS_SPEC;
212 }
213 if (VADDR_REGION3_TL(vaddr) < (entry & REGION_ENTRY_TF) >> 6 ||
214 VADDR_REGION3_TL(vaddr) > (entry & REGION_ENTRY_TL)) {
215 return PGM_REG_THIRD_TRANS;
216 }
217 if (edat1 && (entry & REGION_ENTRY_P)) {
218 *flags &= ~PAGE_WRITE;
219 }
220 gaddr = (entry & REGION_ENTRY_ORIGIN) + VADDR_REGION3_TX(vaddr) * 8;
221 /* fall through */
222 case ASCE_TYPE_REGION3:
223 if (!read_table_entry(env, gaddr, &entry)) {
224 return PGM_ADDRESSING;
225 }
226 if (entry & REGION_ENTRY_I) {
227 return PGM_REG_THIRD_TRANS;
228 }
229 if ((entry & REGION_ENTRY_TT) != REGION_ENTRY_TT_REGION3) {
230 return PGM_TRANS_SPEC;
231 }
232 if (edat2 && (entry & REGION3_ENTRY_CR) && asce_p) {
233 return PGM_TRANS_SPEC;
234 }
235 if (edat1 && (entry & REGION_ENTRY_P)) {
236 *flags &= ~PAGE_WRITE;
237 }
238 if (edat2 && (entry & REGION3_ENTRY_FC)) {
239 if (iep && (entry & REGION3_ENTRY_IEP)) {
240 *flags &= ~PAGE_EXEC;
241 }
242 *raddr = (entry & REGION3_ENTRY_RFAA) |
243 (vaddr & ~REGION3_ENTRY_RFAA);
244 return 0;
245 }
246 if (VADDR_SEGMENT_TL(vaddr) < (entry & REGION_ENTRY_TF) >> 6 ||
247 VADDR_SEGMENT_TL(vaddr) > (entry & REGION_ENTRY_TL)) {
248 return PGM_SEGMENT_TRANS;
249 }
250 gaddr = (entry & REGION_ENTRY_ORIGIN) + VADDR_SEGMENT_TX(vaddr) * 8;
251 /* fall through */
252 case ASCE_TYPE_SEGMENT:
253 if (!read_table_entry(env, gaddr, &entry)) {
254 return PGM_ADDRESSING;
255 }
256 if (entry & SEGMENT_ENTRY_I) {
257 return PGM_SEGMENT_TRANS;
258 }
259 if ((entry & SEGMENT_ENTRY_TT) != SEGMENT_ENTRY_TT_SEGMENT) {
260 return PGM_TRANS_SPEC;
261 }
262 if ((entry & SEGMENT_ENTRY_CS) && asce_p) {
263 return PGM_TRANS_SPEC;
264 }
265 if (entry & SEGMENT_ENTRY_P) {
266 *flags &= ~PAGE_WRITE;
267 }
268 if (edat1 && (entry & SEGMENT_ENTRY_FC)) {
269 if (iep && (entry & SEGMENT_ENTRY_IEP)) {
270 *flags &= ~PAGE_EXEC;
271 }
272 *raddr = (entry & SEGMENT_ENTRY_SFAA) |
273 (vaddr & ~SEGMENT_ENTRY_SFAA);
274 return 0;
275 }
276 gaddr = (entry & SEGMENT_ENTRY_ORIGIN) + VADDR_PAGE_TX(vaddr) * 8;
277 break;
278 }
279
280 if (!read_table_entry(env, gaddr, &entry)) {
281 return PGM_ADDRESSING;
282 }
283 if (entry & PAGE_ENTRY_I) {
284 return PGM_PAGE_TRANS;
285 }
286 if (entry & PAGE_ENTRY_0) {
287 return PGM_TRANS_SPEC;
288 }
289 if (entry & PAGE_ENTRY_P) {
290 *flags &= ~PAGE_WRITE;
291 }
292 if (iep && (entry & PAGE_ENTRY_IEP)) {
293 *flags &= ~PAGE_EXEC;
294 }
295
296 *raddr = entry & TARGET_PAGE_MASK;
297 return 0;
298 }
299
mmu_handle_skey(target_ulong addr,int rw,int * flags)300 static void mmu_handle_skey(target_ulong addr, int rw, int *flags)
301 {
302 static S390SKeysClass *skeyclass;
303 static S390SKeysState *ss;
304 uint8_t key, old_key;
305
306 /*
307 * We expect to be called with an absolute address that has already been
308 * validated, such that we can reliably use it to lookup the storage key.
309 */
310 if (unlikely(!ss)) {
311 ss = s390_get_skeys_device();
312 skeyclass = S390_SKEYS_GET_CLASS(ss);
313 }
314
315 /*
316 * Don't enable storage keys if they are still disabled, i.e., no actual
317 * storage key instruction was issued yet.
318 */
319 if (!skeyclass->skeys_are_enabled(ss)) {
320 return;
321 }
322
323 /*
324 * Whenever we create a new TLB entry, we set the storage key reference
325 * bit. In case we allow write accesses, we set the storage key change
326 * bit. Whenever the guest changes the storage key, we have to flush the
327 * TLBs of all CPUs (the whole TLB or all affected entries), so that the
328 * next reference/change will result in an MMU fault and make us properly
329 * update the storage key here.
330 *
331 * Note 1: "record of references ... is not necessarily accurate",
332 * "change bit may be set in case no storing has occurred".
333 * -> We can set reference/change bits even on exceptions.
334 * Note 2: certain accesses seem to ignore storage keys. For example,
335 * DAT translation does not set reference bits for table accesses.
336 *
337 * TODO: key-controlled protection. Only CPU accesses make use of the
338 * PSW key. CSS accesses are different - we have to pass in the key.
339 *
340 * TODO: we have races between getting and setting the key.
341 */
342 if (s390_skeys_get(ss, addr / TARGET_PAGE_SIZE, 1, &key)) {
343 return;
344 }
345 old_key = key;
346
347 switch (rw) {
348 case MMU_DATA_LOAD:
349 case MMU_INST_FETCH:
350 /*
351 * The TLB entry has to remain write-protected on read-faults if
352 * the storage key does not indicate a change already. Otherwise
353 * we might miss setting the change bit on write accesses.
354 */
355 if (!(key & SK_C)) {
356 *flags &= ~PAGE_WRITE;
357 }
358 break;
359 case MMU_DATA_STORE:
360 key |= SK_C;
361 break;
362 default:
363 g_assert_not_reached();
364 }
365
366 /* Any store/fetch sets the reference bit */
367 key |= SK_R;
368
369 if (key != old_key) {
370 s390_skeys_set(ss, addr / TARGET_PAGE_SIZE, 1, &key);
371 }
372 }
373
374 /**
375 * Translate a virtual (logical) address into a physical (absolute) address.
376 * @param vaddr the virtual address
377 * @param rw 0 = read, 1 = write, 2 = code fetch, < 0 = load real address
378 * @param asc address space control (one of the PSW_ASC_* modes)
379 * @param raddr the translated address is stored to this pointer
380 * @param flags the PAGE_READ/WRITE/EXEC flags are stored to this pointer
381 * @param tec the translation exception code if stored to this pointer if
382 * there is an exception to raise
383 * @return 0 = success, != 0, the exception to raise
384 */
mmu_translate(CPUS390XState * env,target_ulong vaddr,int rw,uint64_t asc,target_ulong * raddr,int * flags,uint64_t * tec)385 int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc,
386 target_ulong *raddr, int *flags, uint64_t *tec)
387 {
388 uint64_t asce;
389 int r;
390
391 *tec = (vaddr & TARGET_PAGE_MASK) | (asc >> 46) |
392 (rw == MMU_DATA_STORE ? FS_WRITE : FS_READ);
393 *flags = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
394
395 if (is_low_address(vaddr & TARGET_PAGE_MASK) && lowprot_enabled(env, asc)) {
396 /*
397 * If any part of this page is currently protected, make sure the
398 * TLB entry will not be reused.
399 *
400 * As the protected range is always the first 512 bytes of the
401 * two first pages, we are able to catch all writes to these areas
402 * just by looking at the start address (triggering the tlb miss).
403 */
404 *flags |= PAGE_WRITE_INV;
405 if (is_low_address(vaddr) && rw == MMU_DATA_STORE) {
406 /* LAP sets bit 56 */
407 *tec |= 0x80;
408 return PGM_PROTECTION;
409 }
410 }
411
412 vaddr &= TARGET_PAGE_MASK;
413
414 if (rw != MMU_S390_LRA && !(env->psw.mask & PSW_MASK_DAT)) {
415 *raddr = vaddr;
416 goto nodat;
417 }
418
419 switch (asc) {
420 case PSW_ASC_PRIMARY:
421 asce = env->cregs[1];
422 break;
423 case PSW_ASC_HOME:
424 asce = env->cregs[13];
425 break;
426 case PSW_ASC_SECONDARY:
427 asce = env->cregs[7];
428 break;
429 case PSW_ASC_ACCREG:
430 default:
431 hw_error("guest switched to unknown asc mode\n");
432 break;
433 }
434
435 /* perform the DAT translation */
436 r = mmu_translate_asce(env, vaddr, asc, asce, raddr, flags);
437 if (unlikely(r)) {
438 return r;
439 }
440
441 /* check for DAT protection */
442 if (unlikely(rw == MMU_DATA_STORE && !(*flags & PAGE_WRITE))) {
443 /* DAT sets bit 61 only */
444 *tec |= 0x4;
445 return PGM_PROTECTION;
446 }
447
448 /* check for Instruction-Execution-Protection */
449 if (unlikely(rw == MMU_INST_FETCH && !(*flags & PAGE_EXEC))) {
450 /* IEP sets bit 56 and 61 */
451 *tec |= 0x84;
452 return PGM_PROTECTION;
453 }
454
455 nodat:
456 if (rw >= 0) {
457 /* Convert real address -> absolute address */
458 *raddr = mmu_real2abs(env, *raddr);
459
460 if (!mmu_absolute_addr_valid(*raddr, rw == MMU_DATA_STORE)) {
461 *tec = 0; /* unused */
462 return PGM_ADDRESSING;
463 }
464
465 mmu_handle_skey(*raddr, rw, flags);
466 }
467 return 0;
468 }
469
470 /**
471 * translate_pages: Translate a set of consecutive logical page addresses
472 * to absolute addresses. This function is used for TCG and old KVM without
473 * the MEMOP interface.
474 */
translate_pages(S390CPU * cpu,vaddr addr,int nr_pages,target_ulong * pages,bool is_write,uint64_t * tec)475 static int translate_pages(S390CPU *cpu, vaddr addr, int nr_pages,
476 target_ulong *pages, bool is_write, uint64_t *tec)
477 {
478 uint64_t asc = cpu->env.psw.mask & PSW_MASK_ASC;
479 CPUS390XState *env = &cpu->env;
480 int ret, i, pflags;
481
482 for (i = 0; i < nr_pages; i++) {
483 ret = mmu_translate(env, addr, is_write, asc, &pages[i], &pflags, tec);
484 if (ret) {
485 return ret;
486 }
487 addr += TARGET_PAGE_SIZE;
488 }
489
490 return 0;
491 }
492
s390_cpu_pv_mem_rw(S390CPU * cpu,unsigned int offset,void * hostbuf,int len,bool is_write)493 int s390_cpu_pv_mem_rw(S390CPU *cpu, unsigned int offset, void *hostbuf,
494 int len, bool is_write)
495 {
496 int ret;
497
498 if (kvm_enabled()) {
499 ret = kvm_s390_mem_op_pv(cpu, offset, hostbuf, len, is_write);
500 } else {
501 /* Protected Virtualization is a KVM/Hardware only feature */
502 g_assert_not_reached();
503 }
504 return ret;
505 }
506
507 /**
508 * s390_cpu_virt_mem_rw:
509 * @laddr: the logical start address
510 * @ar: the access register number
511 * @hostbuf: buffer in host memory. NULL = do only checks w/o copying
512 * @len: length that should be transferred
513 * @is_write: true = write, false = read
514 * Returns: 0 on success, non-zero if an exception occurred
515 *
516 * Copy from/to guest memory using logical addresses. Note that we inject a
517 * program interrupt in case there is an error while accessing the memory.
518 *
519 * This function will always return (also for TCG), make sure to call
520 * s390_cpu_virt_mem_handle_exc() to properly exit the CPU loop.
521 */
s390_cpu_virt_mem_rw(S390CPU * cpu,vaddr laddr,uint8_t ar,void * hostbuf,int len,bool is_write)522 int s390_cpu_virt_mem_rw(S390CPU *cpu, vaddr laddr, uint8_t ar, void *hostbuf,
523 int len, bool is_write)
524 {
525 int currlen, nr_pages, i;
526 target_ulong *pages;
527 uint64_t tec;
528 int ret;
529
530 if (kvm_enabled()) {
531 ret = kvm_s390_mem_op(cpu, laddr, ar, hostbuf, len, is_write);
532 if (ret >= 0) {
533 return ret;
534 }
535 }
536
537 nr_pages = (((laddr & ~TARGET_PAGE_MASK) + len - 1) >> TARGET_PAGE_BITS)
538 + 1;
539 pages = g_malloc(nr_pages * sizeof(*pages));
540
541 ret = translate_pages(cpu, laddr, nr_pages, pages, is_write, &tec);
542 if (ret) {
543 trigger_access_exception(&cpu->env, ret, tec);
544 } else if (hostbuf != NULL) {
545 /* Copy data by stepping through the area page by page */
546 for (i = 0; i < nr_pages; i++) {
547 currlen = MIN(len, TARGET_PAGE_SIZE - (laddr % TARGET_PAGE_SIZE));
548 cpu_physical_memory_rw(pages[i] | (laddr & ~TARGET_PAGE_MASK),
549 hostbuf, currlen, is_write);
550 laddr += currlen;
551 hostbuf += currlen;
552 len -= currlen;
553 }
554 }
555
556 g_free(pages);
557 return ret;
558 }
559
s390_cpu_virt_mem_handle_exc(S390CPU * cpu,uintptr_t ra)560 void s390_cpu_virt_mem_handle_exc(S390CPU *cpu, uintptr_t ra)
561 {
562 /* KVM will handle the interrupt automatically, TCG has to exit the TB */
563 #ifdef CONFIG_TCG
564 if (tcg_enabled()) {
565 cpu_loop_exit_restore(CPU(cpu), ra);
566 }
567 #endif
568 }
569
570 /**
571 * Translate a real address into a physical (absolute) address.
572 * @param raddr the real address
573 * @param rw 0 = read, 1 = write, 2 = code fetch
574 * @param addr the translated address is stored to this pointer
575 * @param flags the PAGE_READ/WRITE/EXEC flags are stored to this pointer
576 * @return 0 = success, != 0, the exception to raise
577 */
mmu_translate_real(CPUS390XState * env,target_ulong raddr,int rw,target_ulong * addr,int * flags,uint64_t * tec)578 int mmu_translate_real(CPUS390XState *env, target_ulong raddr, int rw,
579 target_ulong *addr, int *flags, uint64_t *tec)
580 {
581 const bool lowprot_enabled = env->cregs[0] & CR0_LOWPROT;
582
583 *flags = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
584 if (is_low_address(raddr & TARGET_PAGE_MASK) && lowprot_enabled) {
585 /* see comment in mmu_translate() how this works */
586 *flags |= PAGE_WRITE_INV;
587 if (is_low_address(raddr) && rw == MMU_DATA_STORE) {
588 /* LAP sets bit 56 */
589 *tec = (raddr & TARGET_PAGE_MASK) | FS_WRITE | 0x80;
590 return PGM_PROTECTION;
591 }
592 }
593
594 *addr = mmu_real2abs(env, raddr & TARGET_PAGE_MASK);
595
596 if (!mmu_absolute_addr_valid(*addr, rw == MMU_DATA_STORE)) {
597 /* unused */
598 *tec = 0;
599 return PGM_ADDRESSING;
600 }
601
602 mmu_handle_skey(*addr, rw, flags);
603 return 0;
604 }
605