xref: /openbmc/linux/drivers/video/fbdev/i810/i810.h (revision 775a8a56)
1 /*-*- linux-c -*-
2  *  linux/drivers/video/i810.h -- Intel 810 General Definitions/Declarations
3  *
4  *      Copyright (C) 2001 Antonino Daplas<adaplas@pol.net>
5  *      All Rights Reserved
6  *
7  *
8  *  This file is subject to the terms and conditions of the GNU General Public
9  *  License. See the file COPYING in the main directory of this archive for
10  *  more details.
11  */
12 
13 #ifndef __I810_H__
14 #define __I810_H__
15 
16 #include <linux/list.h>
17 #include <linux/agp_backend.h>
18 #include <linux/fb.h>
19 #include <linux/i2c.h>
20 #include <linux/i2c-algo-bit.h>
21 #include <video/vga.h>
22 
23 /* Fence */
24 #define TILEWALK_X            (0 << 12)
25 #define TILEWALK_Y            (1 << 12)
26 
27 /* Raster ops */
28 #define COLOR_COPY_ROP        0xF0
29 #define PAT_COPY_ROP          0xCC
30 #define CLEAR_ROP             0x00
31 #define WHITE_ROP             0xFF
32 #define INVERT_ROP            0x55
33 #define XOR_ROP               0x5A
34 
35 /* 2D Engine definitions */
36 #define SOLIDPATTERN          0x80000000
37 #define NONSOLID              0x00000000
38 #define BPP8                  (0 << 24)
39 #define BPP16                 (1 << 24)
40 #define BPP24                 (2 << 24)
41 
42 #define PIXCONF8              (2 << 16)
43 #define PIXCONF15             (4 << 16)
44 #define PIXCONF16             (5 << 16)
45 #define PIXCONF24             (6 << 16)
46 #define PIXCONF32             (7 << 16)
47 
48 #define DYN_COLOR_EN          (1 << 26)
49 #define DYN_COLOR_DIS         (0 << 26)
50 #define INCREMENT             0x00000000
51 #define DECREMENT             (0x01 << 30)
52 #define ARB_ON                0x00000001
53 #define ARB_OFF               0x00000000
54 #define SYNC_FLIP             0x00000000
55 #define ASYNC_FLIP            0x00000040
56 #define OPTYPE_MASK           0xE0000000
57 #define PARSER_MASK           0x001F8000
58 #define D2_MASK               0x001FC000         /* 2D mask */
59 
60 /* Instruction type */
61 /* There are more but pertains to 3D */
62 #define PARSER                0x00000000
63 #define BLIT                  (0x02 << 29)
64 #define RENDER                (0x03 << 29)
65 
66 /* Parser */
67 #define NOP                   0x00               /* No operation, padding */
68 #define BP_INT                (0x01 << 23)         /* Breakpoint interrupt */
69 #define USR_INT               (0x02 << 23)         /* User interrupt */
70 #define WAIT_FOR_EVNT         (0x03 << 23)         /* Wait for event */
71 #define FLUSH                 (0x04 << 23)
72 #define CONTEXT_SEL           (0x05 << 23)
73 #define REPORT_HEAD           (0x07 << 23)
74 #define ARB_ON_OFF            (0x08 << 23)
75 #define OVERLAY_FLIP          (0x11 << 23)
76 #define LOAD_SCAN_INC         (0x12 << 23)
77 #define LOAD_SCAN_EX          (0x13 << 23)
78 #define FRONT_BUFFER          (0x14 << 23)
79 #define DEST_BUFFER           (0x15 << 23)
80 #define Z_BUFFER              (0x16 << 23)
81 
82 #define STORE_DWORD_IMM       (0x20 << 23)
83 #define STORE_DWORD_IDX       (0x21 << 23)
84 #define BATCH_BUFFER          (0x30 << 23)
85 
86 /* Blit */
87 #define SETUP_BLIT                      0x00
88 #define SETUP_MONO_PATTERN_SL_BLT       (0x10 << 22)
89 #define PIXEL_BLT                       (0x20 << 22)
90 #define SCANLINE_BLT                    (0x21 << 22)
91 #define TEXT_BLT                        (0x22 << 22)
92 #define TEXT_IMM_BLT                    (0x30 << 22)
93 #define COLOR_BLT                       (0x40 << 22)
94 #define MONO_PAT_BLIT                   (0x42 << 22)
95 #define SOURCE_COPY_BLIT                (0x43 << 22)
96 #define MONO_SOURCE_COPY_BLIT           (0x44 << 22)
97 #define SOURCE_COPY_IMMEDIATE           (0x60 << 22)
98 #define MONO_SOURCE_COPY_IMMEDIATE      (0x61 << 22)
99 
100 #define VERSION_MAJOR            0
101 #define VERSION_MINOR            9
102 #define VERSION_TEENIE           0
103 #define BRANCH_VERSION           ""
104 
105 
106 /* mvo: intel i815 */
107 #ifndef PCI_DEVICE_ID_INTEL_82815_100
108   #define PCI_DEVICE_ID_INTEL_82815_100           0x1102
109 #endif
110 #ifndef PCI_DEVICE_ID_INTEL_82815_NOAGP
111   #define PCI_DEVICE_ID_INTEL_82815_NOAGP         0x1112
112 #endif
113 #ifndef PCI_DEVICE_ID_INTEL_82815_FULL_CTRL
114   #define PCI_DEVICE_ID_INTEL_82815_FULL_CTRL     0x1130
115 #endif
116 
117 /* General Defines */
118 #define I810_PAGESIZE               4096
119 #define MAX_DMA_SIZE                (1024 * 4096)
120 #define SAREA_SIZE                  4096
121 #define PCI_I810_MISCC              0x72
122 #define MMIO_SIZE                   (512*1024)
123 #define GTT_SIZE                    (16*1024)
124 #define RINGBUFFER_SIZE             (64*1024)
125 #define CURSOR_SIZE                 4096
126 #define OFF                         0
127 #define ON                          1
128 #define MAX_KEY                     256
129 #define WAIT_COUNT                  10000000
130 #define IRING_PAD                   8
131 #define FONTDATAMAX                 8192
132 /* Masks (AND ops) and OR's */
133 #define FB_START_MASK               (0x3f << (32 - 6))
134 #define MMIO_ADDR_MASK              (0x1FFF << (32 - 13))
135 #define FREQ_MASK                   (1 << 4)
136 #define SCR_OFF                     0x20
137 #define DRAM_ON                     0x08
138 #define DRAM_OFF                    0xE7
139 #define PG_ENABLE_MASK              0x01
140 #define RING_SIZE_MASK              (RINGBUFFER_SIZE - 1)
141 
142 /* defines for restoring registers partially */
143 #define ADDR_MAP_MASK               (0x07 << 5)
144 #define DISP_CTRL                   ~0
145 #define PIXCONF_0                   (0x64 << 8)
146 #define PIXCONF_2                   (0xF3 << 24)
147 #define PIXCONF_1                   (0xF0 << 16)
148 #define MN_MASK                     0x3FF03FF
149 #define P_OR                        (0x7 << 4)
150 #define DAC_BIT                     (1 << 16)
151 #define INTERLACE_BIT               (1 << 7)
152 #define IER_MASK                    (3 << 13)
153 #define IMR_MASK                    (3 << 13)
154 
155 /* Power Management */
156 #define DPMS_MASK                   0xF0000
157 #define POWERON                     0x00000
158 #define STANDBY                     0x20000
159 #define SUSPEND                     0x80000
160 #define POWERDOWN                   0xA0000
161 #define EMR_MASK                    ~0x3F
162 #define FW_BLC_MASK                 ~(0x3F|(7 << 8)|(0x3F << 12)|(7 << 20))
163 
164 /* Ringbuffer */
165 #define RBUFFER_START_MASK          0xFFFFF000
166 #define RBUFFER_SIZE_MASK           0x001FF000
167 #define RBUFFER_HEAD_MASK           0x001FFFFC
168 #define RBUFFER_TAIL_MASK           0x001FFFF8
169 
170 /* Video Timings */
171 #define REF_FREQ                    24000000
172 #define TARGET_N_MAX                30
173 
174 #define MAX_PIXELCLOCK              230000000
175 #define MIN_PIXELCLOCK               15000000
176 #define VFMAX                       60
177 #define VFMIN                       60
178 #define HFMAX                       30000
179 #define HFMIN                       29000
180 
181 /* Cursor */
182 #define CURSOR_ENABLE_MASK          0x1000
183 #define CURSOR_MODE_64_TRANS        4
184 #define CURSOR_MODE_64_XOR	    5
185 #define CURSOR_MODE_64_3C	    6
186 #define COORD_INACTIVE              0
187 #define COORD_ACTIVE                (1 << 4)
188 #define EXTENDED_PALETTE	    1
189 
190 /* AGP Memory Types*/
191 #define AGP_NORMAL_MEMORY           0
192 #define AGP_DCACHE_MEMORY	    1
193 #define AGP_PHYSICAL_MEMORY         2
194 
195 /* Allocated resource Flags */
196 #define FRAMEBUFFER_REQ             1
197 #define MMIO_REQ                    2
198 #define PCI_DEVICE_ENABLED          4
199 #define HAS_FONTCACHE               8
200 
201 /* driver flags */
202 #define HAS_ACCELERATION            2
203 #define ALWAYS_SYNC                 4
204 #define LOCKUP                      8
205 
206 struct gtt_data {
207 	struct agp_memory *i810_fb_memory;
208 	struct agp_memory *i810_cursor_memory;
209 };
210 
211 struct mode_registers {
212 	u32 pixclock, M, N, P;
213 	u8 cr00, cr01, cr02, cr03;
214 	u8 cr04, cr05, cr06, cr07;
215 	u8 cr09, cr10, cr11, cr12;
216 	u8 cr13, cr15, cr16, cr30;
217 	u8 cr31, cr32, cr33, cr35, cr39;
218 	u32 bpp8_100, bpp16_100;
219 	u32 bpp24_100, bpp8_133;
220 	u32 bpp16_133, bpp24_133;
221 	u8 msr;
222 };
223 
224 struct heap_data {
225         unsigned long physical;
226 	__u8 __iomem *virtual;
227 	u32 offset;
228 	u32 size;
229 };
230 
231 struct state_registers {
232 	u32 dclk_1d, dclk_2d, dclk_0ds;
233 	u32 pixconf, fw_blc, pgtbl_ctl;
234 	u32 fence0, hws_pga, dplystas;
235 	u16 bltcntl, hwstam, ier, iir, imr;
236 	u8 cr00, cr01, cr02, cr03, cr04;
237 	u8 cr05, cr06, cr07, cr08, cr09;
238 	u8 cr10, cr11, cr12, cr13, cr14;
239 	u8 cr15, cr16, cr17, cr80, gr10;
240 	u8 cr30, cr31, cr32, cr33, cr35;
241 	u8 cr39, cr41, cr70, sr01, msr;
242 };
243 
244 struct i810fb_par;
245 
246 struct i810fb_i2c_chan {
247 	struct i810fb_par *par;
248 	struct i2c_adapter adapter;
249 	struct i2c_algo_bit_data algo;
250 	unsigned long ddc_base;
251 };
252 
253 struct i810fb_par {
254 	struct mode_registers    regs;
255 	struct state_registers   hw_state;
256 	struct gtt_data          i810_gtt;
257 	struct fb_ops            i810fb_ops;
258 	struct pci_dev           *dev;
259 	struct heap_data         aperture;
260 	struct heap_data         fb;
261 	struct heap_data         iring;
262 	struct heap_data         cursor_heap;
263 	struct vgastate          state;
264 	struct i810fb_i2c_chan   chan[3];
265 	struct mutex		 open_lock;
266 	unsigned int		 use_count;
267 	u32 pseudo_palette[16];
268 	unsigned long mmio_start_phys;
269 	u8 __iomem *mmio_start_virtual;
270 	u8 *edid;
271 	u32 pitch;
272 	u32 pixconf;
273 	u32 watermark;
274 	u32 mem_freq;
275 	u32 res_flags;
276 	u32 dev_flags;
277 	u32 cur_tail;
278 	u32 depth;
279 	u32 blit_bpp;
280 	u32 ovract;
281 	u32 cur_state;
282 	u32 ddc_num;
283 	int wc_cookie;
284 	u16 bltcntl;
285 	u8 interlace;
286 };
287 
288 /*
289  * Register I/O
290  */
291 #define i810_readb(where, mmio) readb(mmio + where)
292 #define i810_readw(where, mmio) readw(mmio + where)
293 #define i810_readl(where, mmio) readl(mmio + where)
294 #define i810_writeb(where, mmio, val) writeb(val, mmio + where)
295 #define i810_writew(where, mmio, val) writew(val, mmio + where)
296 #define i810_writel(where, mmio, val) writel(val, mmio + where)
297 
298 #endif /* __I810_H__ */
299