1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the r8a73a4 SoC
4 *
5 * Copyright (C) 2013 Renesas Solutions Corp.
6 * Copyright (C) 2013 Magnus Damm
7 */
8
9#include <dt-bindings/clock/r8a73a4-clock.h>
10#include <dt-bindings/interrupt-controller/arm-gic.h>
11#include <dt-bindings/interrupt-controller/irq.h>
12
13/ {
14	compatible = "renesas,r8a73a4";
15	interrupt-parent = <&gic>;
16	#address-cells = <2>;
17	#size-cells = <2>;
18
19	cpus {
20		#address-cells = <1>;
21		#size-cells = <0>;
22
23		cpu0: cpu@0 {
24			device_type = "cpu";
25			compatible = "arm,cortex-a15";
26			reg = <0>;
27			clocks = <&cpg_clocks R8A73A4_CLK_Z>;
28			clock-frequency = <1500000000>;
29			power-domains = <&pd_a2sl>;
30			next-level-cache = <&L2_CA15>;
31		};
32
33		L2_CA15: cache-controller-0 {
34			compatible = "cache";
35			clocks = <&cpg_clocks R8A73A4_CLK_Z>;
36			power-domains = <&pd_a3sm>;
37			cache-unified;
38			cache-level = <2>;
39		};
40
41		L2_CA7: cache-controller-1 {
42			compatible = "cache";
43			clocks = <&cpg_clocks R8A73A4_CLK_Z2>;
44			power-domains = <&pd_a3km>;
45			cache-unified;
46			cache-level = <2>;
47		};
48	};
49
50	ptm {
51		compatible = "arm,coresight-etm3x";
52		power-domains = <&pd_d4>;
53	};
54
55	timer {
56		compatible = "arm,armv7-timer";
57		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
58			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
59			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
60			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
61	};
62
63	dbsc1: memory-controller@e6790000 {
64		compatible = "renesas,dbsc-r8a73a4";
65		reg = <0 0xe6790000 0 0x10000>;
66		power-domains = <&pd_a3bc>;
67	};
68
69	dbsc2: memory-controller@e67a0000 {
70		compatible = "renesas,dbsc-r8a73a4";
71		reg = <0 0xe67a0000 0 0x10000>;
72		power-domains = <&pd_a3bc>;
73	};
74
75	i2c5: i2c@e60b0000 {
76		#address-cells = <1>;
77		#size-cells = <0>;
78		compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
79		reg = <0 0xe60b0000 0 0x428>;
80		interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
81		clocks = <&mstp4_clks R8A73A4_CLK_IIC5>;
82		power-domains = <&pd_a3sp>;
83
84		status = "disabled";
85	};
86
87	cmt1: timer@e6130000 {
88		compatible = "renesas,r8a73a4-cmt1", "renesas,rcar-gen2-cmt1";
89		reg = <0 0xe6130000 0 0x1004>;
90		interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
91			     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
92			     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
93			     <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
94			     <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
95			     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
96			     <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
97			     <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
98		clocks = <&mstp3_clks R8A73A4_CLK_CMT1>;
99		clock-names = "fck";
100		power-domains = <&pd_c5>;
101		status = "disabled";
102	};
103
104	irqc0: interrupt-controller@e61c0000 {
105		compatible = "renesas,irqc-r8a73a4", "renesas,irqc";
106		#interrupt-cells = <2>;
107		interrupt-controller;
108		reg = <0 0xe61c0000 0 0x200>;
109		interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
110			     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
111			     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
112			     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
113			     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
114			     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
115			     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
116			     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
117			     <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
118			     <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
119			     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
120			     <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
121			     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
122			     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
123			     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
124			     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
125			     <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
126			     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
127			     <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
128			     <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
129			     <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
130			     <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
131			     <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
132			     <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
133			     <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
134			     <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
135			     <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
136			     <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
137			     <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
138			     <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
139			     <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
140			     <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
141		clocks = <&mstp4_clks R8A73A4_CLK_IRQC>;
142		power-domains = <&pd_c4>;
143	};
144
145	irqc1: interrupt-controller@e61c0200 {
146		compatible = "renesas,irqc-r8a73a4", "renesas,irqc";
147		#interrupt-cells = <2>;
148		interrupt-controller;
149		reg = <0 0xe61c0200 0 0x200>;
150		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
151			     <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
152			     <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
153			     <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
154			     <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
155			     <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
156			     <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
157			     <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
158			     <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
159			     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
160			     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
161			     <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
162			     <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
163			     <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
164			     <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
165			     <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
166			     <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
167			     <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
168			     <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
169			     <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
170			     <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
171			     <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
172			     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
173			     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
174			     <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
175			     <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
176		clocks = <&mstp4_clks R8A73A4_CLK_IRQC>;
177		power-domains = <&pd_c4>;
178	};
179
180	pfc: pinctrl@e6050000 {
181		compatible = "renesas,pfc-r8a73a4";
182		reg = <0 0xe6050000 0 0x9000>;
183		gpio-controller;
184		#gpio-cells = <2>;
185		gpio-ranges =
186			<&pfc 0 0 31>, <&pfc 32 32 9>,
187			<&pfc 64 64 22>, <&pfc 96 96 31>,
188			<&pfc 128 128 7>, <&pfc 160 160 19>,
189			<&pfc 192 192 31>, <&pfc 224 224 27>,
190			<&pfc 256 256 28>, <&pfc 288 288 21>,
191			<&pfc 320 320 10>;
192		interrupts-extended =
193			<&irqc0  0 0>, <&irqc0  1 0>, <&irqc0  2 0>, <&irqc0  3 0>,
194			<&irqc0  4 0>, <&irqc0  5 0>, <&irqc0  6 0>, <&irqc0  7 0>,
195			<&irqc0  8 0>, <&irqc0  9 0>, <&irqc0 10 0>, <&irqc0 11 0>,
196			<&irqc0 12 0>, <&irqc0 13 0>, <&irqc0 14 0>, <&irqc0 15 0>,
197			<&irqc0 16 0>, <&irqc0 17 0>, <&irqc0 18 0>, <&irqc0 19 0>,
198			<&irqc0 20 0>, <&irqc0 21 0>, <&irqc0 22 0>, <&irqc0 23 0>,
199			<&irqc0 24 0>, <&irqc0 25 0>, <&irqc0 26 0>, <&irqc0 27 0>,
200			<&irqc0 28 0>, <&irqc0 29 0>, <&irqc0 30 0>, <&irqc0 31 0>,
201			<&irqc1  0 0>, <&irqc1  1 0>, <&irqc1  2 0>, <&irqc1  3 0>,
202			<&irqc1  4 0>, <&irqc1  5 0>, <&irqc1  6 0>, <&irqc1  7 0>,
203			<&irqc1  8 0>, <&irqc1  9 0>, <&irqc1 10 0>, <&irqc1 11 0>,
204			<&irqc1 12 0>, <&irqc1 13 0>, <&irqc1 14 0>, <&irqc1 15 0>,
205			<&irqc1 16 0>, <&irqc1 17 0>, <&irqc1 18 0>, <&irqc1 19 0>,
206			<&irqc1 20 0>, <&irqc1 21 0>, <&irqc1 22 0>, <&irqc1 23 0>,
207			<&irqc1 24 0>, <&irqc1 25 0>;
208		power-domains = <&pd_c5>;
209	};
210
211	thermal@e61f0000 {
212		compatible = "renesas,thermal-r8a73a4", "renesas,rcar-thermal";
213		reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>,
214			 <0 0xe61f0200 0 0x38>, <0 0xe61f0300 0 0x38>;
215		interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
216		clocks = <&mstp5_clks R8A73A4_CLK_THERMAL>;
217		power-domains = <&pd_c5>;
218	};
219
220	i2c0: i2c@e6500000 {
221		#address-cells = <1>;
222		#size-cells = <0>;
223		compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
224		reg = <0 0xe6500000 0 0x428>;
225		interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
226		clocks = <&mstp3_clks R8A73A4_CLK_IIC0>;
227		power-domains = <&pd_a3sp>;
228		status = "disabled";
229	};
230
231	i2c1: i2c@e6510000 {
232		#address-cells = <1>;
233		#size-cells = <0>;
234		compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
235		reg = <0 0xe6510000 0 0x428>;
236		interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
237		clocks = <&mstp3_clks R8A73A4_CLK_IIC1>;
238		power-domains = <&pd_a3sp>;
239		status = "disabled";
240	};
241
242	i2c2: i2c@e6520000 {
243		#address-cells = <1>;
244		#size-cells = <0>;
245		compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
246		reg = <0 0xe6520000 0 0x428>;
247		interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
248		clocks = <&mstp3_clks R8A73A4_CLK_IIC2>;
249		power-domains = <&pd_a3sp>;
250		status = "disabled";
251	};
252
253	i2c3: i2c@e6530000 {
254		#address-cells = <1>;
255		#size-cells = <0>;
256		compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
257		reg = <0 0xe6530000 0 0x428>;
258		interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
259		clocks = <&mstp4_clks R8A73A4_CLK_IIC3>;
260		power-domains = <&pd_a3sp>;
261		status = "disabled";
262	};
263
264	i2c4: i2c@e6540000 {
265		#address-cells = <1>;
266		#size-cells = <0>;
267		compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
268		reg = <0 0xe6540000 0 0x428>;
269		interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
270		clocks = <&mstp4_clks R8A73A4_CLK_IIC4>;
271		power-domains = <&pd_a3sp>;
272		status = "disabled";
273	};
274
275	i2c6: i2c@e6550000 {
276		#address-cells = <1>;
277		#size-cells = <0>;
278		compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
279		reg = <0 0xe6550000 0 0x428>;
280		interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
281		clocks = <&mstp3_clks R8A73A4_CLK_IIC6>;
282		power-domains = <&pd_a3sp>;
283		status = "disabled";
284	};
285
286	i2c7: i2c@e6560000 {
287		#address-cells = <1>;
288		#size-cells = <0>;
289		compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
290		reg = <0 0xe6560000 0 0x428>;
291		interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
292		clocks = <&mstp3_clks R8A73A4_CLK_IIC7>;
293		power-domains = <&pd_a3sp>;
294		status = "disabled";
295	};
296
297	i2c8: i2c@e6570000 {
298		#address-cells = <1>;
299		#size-cells = <0>;
300		compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
301		reg = <0 0xe6570000 0 0x428>;
302		interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
303		clocks = <&mstp5_clks R8A73A4_CLK_IIC8>;
304		power-domains = <&pd_a3sp>;
305		status = "disabled";
306	};
307
308	scifb0: serial@e6c20000 {
309		compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
310		reg = <0 0xe6c20000 0 0x100>;
311		interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
312		clocks = <&mstp2_clks R8A73A4_CLK_SCIFB0>;
313		clock-names = "fck";
314		power-domains = <&pd_a3sp>;
315		status = "disabled";
316	};
317
318	scifb1: serial@e6c30000 {
319		compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
320		reg = <0 0xe6c30000 0 0x100>;
321		interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
322		clocks = <&mstp2_clks R8A73A4_CLK_SCIFB1>;
323		clock-names = "fck";
324		power-domains = <&pd_a3sp>;
325		status = "disabled";
326	};
327
328	scifa0: serial@e6c40000 {
329		compatible = "renesas,scifa-r8a73a4", "renesas,scifa";
330		reg = <0 0xe6c40000 0 0x100>;
331		interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
332		clocks = <&mstp2_clks R8A73A4_CLK_SCIFA0>;
333		clock-names = "fck";
334		power-domains = <&pd_a3sp>;
335		status = "disabled";
336	};
337
338	scifa1: serial@e6c50000 {
339		compatible = "renesas,scifa-r8a73a4", "renesas,scifa";
340		reg = <0 0xe6c50000 0 0x100>;
341		interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
342		clocks = <&mstp2_clks R8A73A4_CLK_SCIFA1>;
343		clock-names = "fck";
344		power-domains = <&pd_a3sp>;
345		status = "disabled";
346	};
347
348	scifb2: serial@e6ce0000 {
349		compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
350		reg = <0 0xe6ce0000 0 0x100>;
351		interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
352		clocks = <&mstp2_clks R8A73A4_CLK_SCIFB2>;
353		clock-names = "fck";
354		power-domains = <&pd_a3sp>;
355		status = "disabled";
356	};
357
358	scifb3: serial@e6cf0000 {
359		compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
360		reg = <0 0xe6cf0000 0 0x100>;
361		interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
362		clocks = <&mstp2_clks R8A73A4_CLK_SCIFB3>;
363		clock-names = "fck";
364		power-domains = <&pd_c4>;
365		status = "disabled";
366	};
367
368	sdhi0: mmc@ee100000 {
369		compatible = "renesas,sdhi-r8a73a4";
370		reg = <0 0xee100000 0 0x100>;
371		interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
372		clocks = <&mstp3_clks R8A73A4_CLK_SDHI0>;
373		power-domains = <&pd_a3sp>;
374		cap-sd-highspeed;
375		status = "disabled";
376	};
377
378	sdhi1: mmc@ee120000 {
379		compatible = "renesas,sdhi-r8a73a4";
380		reg = <0 0xee120000 0 0x100>;
381		interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
382		clocks = <&mstp3_clks R8A73A4_CLK_SDHI1>;
383		power-domains = <&pd_a3sp>;
384		cap-sd-highspeed;
385		status = "disabled";
386	};
387
388	sdhi2: mmc@ee140000 {
389		compatible = "renesas,sdhi-r8a73a4";
390		reg = <0 0xee140000 0 0x100>;
391		interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
392		clocks = <&mstp3_clks R8A73A4_CLK_SDHI2>;
393		power-domains = <&pd_a3sp>;
394		cap-sd-highspeed;
395		status = "disabled";
396	};
397
398	mmcif0: mmc@ee200000 {
399		compatible = "renesas,mmcif-r8a73a4", "renesas,sh-mmcif";
400		reg = <0 0xee200000 0 0x80>;
401		interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
402		clocks = <&mstp3_clks R8A73A4_CLK_MMCIF0>;
403		power-domains = <&pd_a3sp>;
404		reg-io-width = <4>;
405		status = "disabled";
406	};
407
408	mmcif1: mmc@ee220000 {
409		compatible = "renesas,mmcif-r8a73a4", "renesas,sh-mmcif";
410		reg = <0 0xee220000 0 0x80>;
411		interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
412		clocks = <&mstp3_clks R8A73A4_CLK_MMCIF1>;
413		power-domains = <&pd_a3sp>;
414		reg-io-width = <4>;
415		status = "disabled";
416	};
417
418	gic: interrupt-controller@f1001000 {
419		compatible = "arm,gic-400";
420		#interrupt-cells = <3>;
421		#address-cells = <0>;
422		interrupt-controller;
423		reg = <0 0xf1001000 0 0x1000>,
424			<0 0xf1002000 0 0x2000>,
425			<0 0xf1004000 0 0x2000>,
426			<0 0xf1006000 0 0x2000>;
427		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
428		clocks = <&mstp4_clks R8A73A4_CLK_INTC_SYS>;
429		clock-names = "clk";
430		power-domains = <&pd_c4>;
431	};
432
433	bsc: bus@fec10000 {
434		compatible = "renesas,bsc-r8a73a4", "renesas,bsc",
435			     "simple-pm-bus";
436		#address-cells = <1>;
437		#size-cells = <1>;
438		ranges = <0 0 0 0x20000000>;
439		reg = <0 0xfec10000 0 0x400>;
440		clocks = <&zb_clk>;
441		power-domains = <&pd_c4>;
442	};
443
444	clocks {
445		#address-cells = <2>;
446		#size-cells = <2>;
447		ranges;
448
449		/* External root clocks */
450		extalr_clk: extalr {
451			compatible = "fixed-clock";
452			#clock-cells = <0>;
453			/* This value must be overridden by the board. */
454			clock-frequency = <0>;
455		};
456		extal1_clk: extal1 {
457			compatible = "fixed-clock";
458			#clock-cells = <0>;
459			/* This value must be overridden by the board. */
460			clock-frequency = <0>;
461		};
462		extal2_clk: extal2 {
463			compatible = "fixed-clock";
464			#clock-cells = <0>;
465			/* This value must be overridden by the board. */
466			clock-frequency = <0>;
467		};
468		fsiack_clk: fsiack {
469			compatible = "fixed-clock";
470			#clock-cells = <0>;
471			/* This value must be overridden by the board. */
472			clock-frequency = <0>;
473		};
474		fsibck_clk: fsibck {
475			compatible = "fixed-clock";
476			#clock-cells = <0>;
477			/* This value must be overridden by the board. */
478			clock-frequency = <0>;
479		};
480
481		/* Special CPG clocks */
482		cpg_clocks: cpg_clocks@e6150000 {
483			compatible = "renesas,r8a73a4-cpg-clocks";
484			reg = <0 0xe6150000 0 0x10000>;
485			clocks = <&extal1_clk>, <&extal2_clk>;
486			#clock-cells = <1>;
487			clock-output-names = "main", "pll0", "pll1", "pll2",
488					     "pll2s", "pll2h", "z", "z2",
489					     "i", "m3", "b", "m1", "m2",
490					     "zx", "zs", "hp";
491		};
492
493		/* Variable factor clocks (DIV6) */
494		zb_clk: zb_clk@e6150010 {
495			compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
496			reg = <0 0xe6150010 0 4>;
497			clocks = <&pll1_div2_clk>, <0>,
498				 <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>;
499			#clock-cells = <0>;
500			clock-output-names = "zb";
501		};
502		sdhi0_clk: sdhi0ck@e6150074 {
503			compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
504			reg = <0 0xe6150074 0 4>;
505			clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
506				 <0>, <&extal2_clk>;
507			#clock-cells = <0>;
508		};
509		sdhi1_clk: sdhi1ck@e6150078 {
510			compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
511			reg = <0 0xe6150078 0 4>;
512			clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
513				 <0>, <&extal2_clk>;
514			#clock-cells = <0>;
515		};
516		sdhi2_clk: sdhi2ck@e615007c {
517			compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
518			reg = <0 0xe615007c 0 4>;
519			clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
520				 <0>, <&extal2_clk>;
521			#clock-cells = <0>;
522		};
523		mmc0_clk: mmc0@e6150240 {
524			compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
525			reg = <0 0xe6150240 0 4>;
526			clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
527				 <0>, <&extal2_clk>;
528			#clock-cells = <0>;
529		};
530		mmc1_clk: mmc1@e6150244 {
531			compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
532			reg = <0 0xe6150244 0 4>;
533			clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
534				 <0>, <&extal2_clk>;
535			#clock-cells = <0>;
536		};
537		vclk1_clk: vclk1@e6150008 {
538			compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
539			reg = <0 0xe6150008 0 4>;
540			clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
541				 <0>, <&extal2_clk>, <&main_div2_clk>,
542				 <&extalr_clk>, <0>, <0>;
543			#clock-cells = <0>;
544		};
545		vclk2_clk: vclk2@e615000c {
546			compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
547			reg = <0 0xe615000c 0 4>;
548			clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
549				 <0>, <&extal2_clk>, <&main_div2_clk>,
550				 <&extalr_clk>, <0>, <0>;
551			#clock-cells = <0>;
552		};
553		vclk3_clk: vclk3@e615001c {
554			compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
555			reg = <0 0xe615001c 0 4>;
556			clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
557				 <0>, <&extal2_clk>, <&main_div2_clk>,
558				 <&extalr_clk>, <0>, <0>;
559			#clock-cells = <0>;
560		};
561		vclk4_clk: vclk4@e6150014 {
562			compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
563			reg = <0 0xe6150014 0 4>;
564			clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
565				 <0>, <&extal2_clk>, <&main_div2_clk>,
566				 <&extalr_clk>, <0>, <0>;
567			#clock-cells = <0>;
568		};
569		vclk5_clk: vclk5@e6150034 {
570			compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
571			reg = <0 0xe6150034 0 4>;
572			clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
573				 <0>, <&extal2_clk>, <&main_div2_clk>,
574				 <&extalr_clk>, <0>, <0>;
575			#clock-cells = <0>;
576		};
577		fsia_clk: fsia@e6150018 {
578			compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
579			reg = <0 0xe6150018 0 4>;
580			clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
581				 <&fsiack_clk>, <0>;
582			#clock-cells = <0>;
583		};
584		fsib_clk: fsib@e6150090 {
585			compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
586			reg = <0 0xe6150090 0 4>;
587			clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
588				 <&fsibck_clk>, <0>;
589			#clock-cells = <0>;
590		};
591		mp_clk: mp@e6150080 {
592			compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
593			reg = <0 0xe6150080 0 4>;
594			clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
595				 <&extal2_clk>, <&extal2_clk>;
596			#clock-cells = <0>;
597		};
598		m4_clk: m4@e6150098 {
599			compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
600			reg = <0 0xe6150098 0 4>;
601			clocks = <&cpg_clocks R8A73A4_CLK_PLL2S>;
602			#clock-cells = <0>;
603		};
604		hsi_clk: hsi@e615026c {
605			compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
606			reg = <0 0xe615026c 0 4>;
607			clocks = <&cpg_clocks R8A73A4_CLK_PLL2H>, <&pll1_div2_clk>,
608				 <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>;
609			#clock-cells = <0>;
610		};
611		spuv_clk: spuv@e6150094 {
612			compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
613			reg = <0 0xe6150094 0 4>;
614			clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
615				 <&extal2_clk>, <&extal2_clk>;
616			#clock-cells = <0>;
617		};
618
619		/* Fixed factor clocks */
620		main_div2_clk: main_div2 {
621			compatible = "fixed-factor-clock";
622			clocks = <&cpg_clocks R8A73A4_CLK_MAIN>;
623			#clock-cells = <0>;
624			clock-div = <2>;
625			clock-mult = <1>;
626		};
627		pll0_div2_clk: pll0_div2 {
628			compatible = "fixed-factor-clock";
629			clocks = <&cpg_clocks R8A73A4_CLK_PLL0>;
630			#clock-cells = <0>;
631			clock-div = <2>;
632			clock-mult = <1>;
633		};
634		pll1_div2_clk: pll1_div2 {
635			compatible = "fixed-factor-clock";
636			clocks = <&cpg_clocks R8A73A4_CLK_PLL1>;
637			#clock-cells = <0>;
638			clock-div = <2>;
639			clock-mult = <1>;
640		};
641		extal1_div2_clk: extal1_div2 {
642			compatible = "fixed-factor-clock";
643			clocks = <&extal1_clk>;
644			#clock-cells = <0>;
645			clock-div = <2>;
646			clock-mult = <1>;
647		};
648
649		/* Gate clocks */
650		mstp2_clks: mstp2_clks@e6150138 {
651			compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
652			reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
653			clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
654				 <&mp_clk>, <&mp_clk>, <&cpg_clocks R8A73A4_CLK_HP>;
655			#clock-cells = <1>;
656			clock-indices = <
657				R8A73A4_CLK_SCIFA0 R8A73A4_CLK_SCIFA1
658				R8A73A4_CLK_SCIFB0 R8A73A4_CLK_SCIFB1
659				R8A73A4_CLK_SCIFB2 R8A73A4_CLK_SCIFB3
660				R8A73A4_CLK_DMAC
661			>;
662			clock-output-names =
663				"scifa0", "scifa1", "scifb0", "scifb1",
664				"scifb2", "scifb3", "dmac";
665		};
666		mstp3_clks: mstp3_clks@e615013c {
667			compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
668			reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
669			clocks = <&cpg_clocks R8A73A4_CLK_HP>, <&mmc1_clk>,
670				 <&sdhi2_clk>, <&sdhi1_clk>, <&sdhi0_clk>,
671				 <&mmc0_clk>, <&cpg_clocks R8A73A4_CLK_HP>,
672				 <&cpg_clocks R8A73A4_CLK_HP>, <&cpg_clocks
673				 R8A73A4_CLK_HP>, <&cpg_clocks
674				 R8A73A4_CLK_HP>, <&extalr_clk>;
675			#clock-cells = <1>;
676			clock-indices = <
677				R8A73A4_CLK_IIC2 R8A73A4_CLK_MMCIF1
678				R8A73A4_CLK_SDHI2 R8A73A4_CLK_SDHI1
679				R8A73A4_CLK_SDHI0 R8A73A4_CLK_MMCIF0
680				R8A73A4_CLK_IIC6 R8A73A4_CLK_IIC7
681				R8A73A4_CLK_IIC0 R8A73A4_CLK_IIC1
682				R8A73A4_CLK_CMT1
683			>;
684			clock-output-names =
685				"iic2", "mmcif1", "sdhi2", "sdhi1", "sdhi0",
686				"mmcif0", "iic6", "iic7", "iic0", "iic1",
687				"cmt1";
688		};
689		mstp4_clks: mstp4_clks@e6150140 {
690			compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
691			reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
692			clocks = <&main_div2_clk>, <&cpg_clocks R8A73A4_CLK_ZS>,
693				 <&main_div2_clk>,
694				 <&cpg_clocks R8A73A4_CLK_HP>,
695				 <&cpg_clocks R8A73A4_CLK_HP>;
696			#clock-cells = <1>;
697			clock-indices = <
698				R8A73A4_CLK_IRQC R8A73A4_CLK_INTC_SYS
699				R8A73A4_CLK_IIC5 R8A73A4_CLK_IIC4
700				R8A73A4_CLK_IIC3
701			>;
702			clock-output-names =
703				"irqc", "intc-sys", "iic5", "iic4", "iic3";
704		};
705		mstp5_clks: mstp5_clks@e6150144 {
706			compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
707			reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
708			clocks = <&extal2_clk>, <&cpg_clocks R8A73A4_CLK_HP>;
709			#clock-cells = <1>;
710			clock-indices = <
711				R8A73A4_CLK_THERMAL R8A73A4_CLK_IIC8
712			>;
713			clock-output-names =
714				"thermal", "iic8";
715		};
716	};
717
718	prr: chipid@ff000044 {
719		compatible = "renesas,prr";
720		reg = <0 0xff000044 0 4>;
721	};
722
723	sysc: system-controller@e6180000 {
724		compatible = "renesas,sysc-r8a73a4", "renesas,sysc-rmobile";
725		reg = <0 0xe6180000 0 0x8000>, <0 0xe6188000 0 0x8000>;
726
727		pm-domains {
728			pd_c5: c5 {
729				#address-cells = <1>;
730				#size-cells = <0>;
731				#power-domain-cells = <0>;
732
733				pd_c4: c4@0 {
734					reg = <0>;
735					#address-cells = <1>;
736					#size-cells = <0>;
737					#power-domain-cells = <0>;
738
739					pd_a3sg: a3sg@16 {
740						reg = <16>;
741						#power-domain-cells = <0>;
742					};
743
744					pd_a3ex: a3ex@17 {
745						reg = <17>;
746						#power-domain-cells = <0>;
747					};
748
749					pd_a3sp: a3sp@18 {
750						reg = <18>;
751						#address-cells = <1>;
752						#size-cells = <0>;
753						#power-domain-cells = <0>;
754
755						pd_a2us: a2us@19 {
756							reg = <19>;
757							#power-domain-cells = <0>;
758						};
759					};
760
761					pd_a3sm: a3sm@20 {
762						reg = <20>;
763						#address-cells = <1>;
764						#size-cells = <0>;
765						#power-domain-cells = <0>;
766
767						pd_a2sl: a2sl@21 {
768							reg = <21>;
769							#power-domain-cells = <0>;
770						};
771					};
772
773					pd_a3km: a3km@22 {
774						reg = <22>;
775						#address-cells = <1>;
776						#size-cells = <0>;
777						#power-domain-cells = <0>;
778
779						pd_a2kl: a2kl@23 {
780							reg = <23>;
781							#power-domain-cells = <0>;
782						};
783					};
784				};
785
786				pd_c4ma: c4ma@1 {
787					reg = <1>;
788					#power-domain-cells = <0>;
789				};
790
791				pd_c4cl: c4cl@2 {
792					reg = <2>;
793					#power-domain-cells = <0>;
794				};
795
796				pd_d4: d4@3 {
797					reg = <3>;
798					#power-domain-cells = <0>;
799				};
800
801				pd_a4bc: a4bc@4 {
802					reg = <4>;
803					#address-cells = <1>;
804					#size-cells = <0>;
805					#power-domain-cells = <0>;
806
807					pd_a3bc: a3bc@5 {
808						reg = <5>;
809						#power-domain-cells = <0>;
810					};
811				};
812
813				pd_a4l: a4l@6 {
814					reg = <6>;
815					#power-domain-cells = <0>;
816				};
817
818				pd_a4lc: a4lc@7 {
819					reg = <7>;
820					#power-domain-cells = <0>;
821				};
822
823				pd_a4mp: a4mp@8 {
824					reg = <8>;
825					#address-cells = <1>;
826					#size-cells = <0>;
827					#power-domain-cells = <0>;
828
829					pd_a3mp: a3mp@9 {
830						reg = <9>;
831						#power-domain-cells = <0>;
832					};
833
834					pd_a3vc: a3vc@10 {
835						reg = <10>;
836						#power-domain-cells = <0>;
837					};
838				};
839
840				pd_a4sf: a4sf@11 {
841					reg = <11>;
842					#power-domain-cells = <0>;
843				};
844
845				pd_a3r: a3r@12 {
846					reg = <12>;
847					#address-cells = <1>;
848					#size-cells = <0>;
849					#power-domain-cells = <0>;
850
851					pd_a2rv: a2rv@13 {
852						reg = <13>;
853						#power-domain-cells = <0>;
854					};
855
856					pd_a2is: a2is@14 {
857						reg = <14>;
858						#power-domain-cells = <0>;
859					};
860				};
861			};
862		};
863	};
864};
865