1 /*
2  * Copyright (C) 2019  Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included
12  * in all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18  * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20  */
21 
22 #ifndef _vcn_3_0_0_OFFSET_HEADER
23 #define _vcn_3_0_0_OFFSET_HEADER
24 
25 // addressBlock: uvd0_mmsch_dec
26 // base address: 0x1e000
27 #define mmMMSCH_UCODE_ADDR                                                                             0x0000
28 #define mmMMSCH_UCODE_ADDR_BASE_IDX                                                                    0
29 #define mmMMSCH_UCODE_DATA                                                                             0x0001
30 #define mmMMSCH_UCODE_DATA_BASE_IDX                                                                    0
31 #define mmMMSCH_SRAM_ADDR                                                                              0x0002
32 #define mmMMSCH_SRAM_ADDR_BASE_IDX                                                                     0
33 #define mmMMSCH_SRAM_DATA                                                                              0x0003
34 #define mmMMSCH_SRAM_DATA_BASE_IDX                                                                     0
35 #define mmMMSCH_VF_SRAM_OFFSET                                                                         0x0004
36 #define mmMMSCH_VF_SRAM_OFFSET_BASE_IDX                                                                0
37 #define mmMMSCH_DB_SRAM_OFFSET                                                                         0x0005
38 #define mmMMSCH_DB_SRAM_OFFSET_BASE_IDX                                                                0
39 #define mmMMSCH_CTX_SRAM_OFFSET                                                                        0x0006
40 #define mmMMSCH_CTX_SRAM_OFFSET_BASE_IDX                                                               0
41 #define mmMMSCH_CTL                                                                                    0x0007
42 #define mmMMSCH_CTL_BASE_IDX                                                                           0
43 #define mmMMSCH_INTR                                                                                   0x0008
44 #define mmMMSCH_INTR_BASE_IDX                                                                          0
45 #define mmMMSCH_INTR_ACK                                                                               0x0009
46 #define mmMMSCH_INTR_ACK_BASE_IDX                                                                      0
47 #define mmMMSCH_INTR_STATUS                                                                            0x000a
48 #define mmMMSCH_INTR_STATUS_BASE_IDX                                                                   0
49 #define mmMMSCH_VF_VMID                                                                                0x000b
50 #define mmMMSCH_VF_VMID_BASE_IDX                                                                       0
51 #define mmMMSCH_VF_CTX_ADDR_LO                                                                         0x000c
52 #define mmMMSCH_VF_CTX_ADDR_LO_BASE_IDX                                                                0
53 #define mmMMSCH_VF_CTX_ADDR_HI                                                                         0x000d
54 #define mmMMSCH_VF_CTX_ADDR_HI_BASE_IDX                                                                0
55 #define mmMMSCH_VF_CTX_SIZE                                                                            0x000e
56 #define mmMMSCH_VF_CTX_SIZE_BASE_IDX                                                                   0
57 #define mmMMSCH_VF_GPCOM_ADDR_LO                                                                       0x000f
58 #define mmMMSCH_VF_GPCOM_ADDR_LO_BASE_IDX                                                              0
59 #define mmMMSCH_VF_GPCOM_ADDR_HI                                                                       0x0010
60 #define mmMMSCH_VF_GPCOM_ADDR_HI_BASE_IDX                                                              0
61 #define mmMMSCH_VF_GPCOM_SIZE                                                                          0x0011
62 #define mmMMSCH_VF_GPCOM_SIZE_BASE_IDX                                                                 0
63 #define mmMMSCH_VF_MAILBOX_HOST                                                                        0x0012
64 #define mmMMSCH_VF_MAILBOX_HOST_BASE_IDX                                                               0
65 #define mmMMSCH_VF_MAILBOX_RESP                                                                        0x0013
66 #define mmMMSCH_VF_MAILBOX_RESP_BASE_IDX                                                               0
67 #define mmMMSCH_VF_MAILBOX_0                                                                           0x0014
68 #define mmMMSCH_VF_MAILBOX_0_BASE_IDX                                                                  0
69 #define mmMMSCH_VF_MAILBOX_0_RESP                                                                      0x0015
70 #define mmMMSCH_VF_MAILBOX_0_RESP_BASE_IDX                                                             0
71 #define mmMMSCH_VF_MAILBOX_1                                                                           0x0016
72 #define mmMMSCH_VF_MAILBOX_1_BASE_IDX                                                                  0
73 #define mmMMSCH_VF_MAILBOX_1_RESP                                                                      0x0017
74 #define mmMMSCH_VF_MAILBOX_1_RESP_BASE_IDX                                                             0
75 #define mmMMSCH_CNTL                                                                                   0x001c
76 #define mmMMSCH_CNTL_BASE_IDX                                                                          0
77 #define mmMMSCH_NONCACHE_OFFSET0                                                                       0x001d
78 #define mmMMSCH_NONCACHE_OFFSET0_BASE_IDX                                                              0
79 #define mmMMSCH_NONCACHE_SIZE0                                                                         0x001e
80 #define mmMMSCH_NONCACHE_SIZE0_BASE_IDX                                                                0
81 #define mmMMSCH_NONCACHE_OFFSET1                                                                       0x001f
82 #define mmMMSCH_NONCACHE_OFFSET1_BASE_IDX                                                              0
83 #define mmMMSCH_NONCACHE_SIZE1                                                                         0x0020
84 #define mmMMSCH_NONCACHE_SIZE1_BASE_IDX                                                                0
85 #define mmMMSCH_PROC_STATE1                                                                            0x0026
86 #define mmMMSCH_PROC_STATE1_BASE_IDX                                                                   0
87 #define mmMMSCH_LAST_MC_ADDR                                                                           0x0027
88 #define mmMMSCH_LAST_MC_ADDR_BASE_IDX                                                                  0
89 #define mmMMSCH_LAST_MEM_ACCESS_HI                                                                     0x0028
90 #define mmMMSCH_LAST_MEM_ACCESS_HI_BASE_IDX                                                            0
91 #define mmMMSCH_LAST_MEM_ACCESS_LO                                                                     0x0029
92 #define mmMMSCH_LAST_MEM_ACCESS_LO_BASE_IDX                                                            0
93 #define mmMMSCH_IOV_ACTIVE_FCN_ID                                                                      0x002a
94 #define mmMMSCH_IOV_ACTIVE_FCN_ID_BASE_IDX                                                             0
95 #define mmMMSCH_SCRATCH_0                                                                              0x002b
96 #define mmMMSCH_SCRATCH_0_BASE_IDX                                                                     0
97 #define mmMMSCH_SCRATCH_1                                                                              0x002c
98 #define mmMMSCH_SCRATCH_1_BASE_IDX                                                                     0
99 #define mmMMSCH_GPUIOV_SCH_BLOCK_0                                                                     0x002d
100 #define mmMMSCH_GPUIOV_SCH_BLOCK_0_BASE_IDX                                                            0
101 #define mmMMSCH_GPUIOV_CMD_CONTROL_0                                                                   0x002e
102 #define mmMMSCH_GPUIOV_CMD_CONTROL_0_BASE_IDX                                                          0
103 #define mmMMSCH_GPUIOV_CMD_STATUS_0                                                                    0x002f
104 #define mmMMSCH_GPUIOV_CMD_STATUS_0_BASE_IDX                                                           0
105 #define mmMMSCH_GPUIOV_VM_BUSY_STATUS_0                                                                0x0030
106 #define mmMMSCH_GPUIOV_VM_BUSY_STATUS_0_BASE_IDX                                                       0
107 #define mmMMSCH_GPUIOV_ACTIVE_FCNS_0                                                                   0x0031
108 #define mmMMSCH_GPUIOV_ACTIVE_FCNS_0_BASE_IDX                                                          0
109 #define mmMMSCH_GPUIOV_ACTIVE_FCN_ID_0                                                                 0x0032
110 #define mmMMSCH_GPUIOV_ACTIVE_FCN_ID_0_BASE_IDX                                                        0
111 #define mmMMSCH_GPUIOV_DW6_0                                                                           0x0033
112 #define mmMMSCH_GPUIOV_DW6_0_BASE_IDX                                                                  0
113 #define mmMMSCH_GPUIOV_DW7_0                                                                           0x0034
114 #define mmMMSCH_GPUIOV_DW7_0_BASE_IDX                                                                  0
115 #define mmMMSCH_GPUIOV_DW8_0                                                                           0x0035
116 #define mmMMSCH_GPUIOV_DW8_0_BASE_IDX                                                                  0
117 #define mmMMSCH_GPUIOV_SCH_BLOCK_1                                                                     0x0036
118 #define mmMMSCH_GPUIOV_SCH_BLOCK_1_BASE_IDX                                                            0
119 #define mmMMSCH_GPUIOV_CMD_CONTROL_1                                                                   0x0037
120 #define mmMMSCH_GPUIOV_CMD_CONTROL_1_BASE_IDX                                                          0
121 #define mmMMSCH_GPUIOV_CMD_STATUS_1                                                                    0x0038
122 #define mmMMSCH_GPUIOV_CMD_STATUS_1_BASE_IDX                                                           0
123 #define mmMMSCH_GPUIOV_VM_BUSY_STATUS_1                                                                0x0039
124 #define mmMMSCH_GPUIOV_VM_BUSY_STATUS_1_BASE_IDX                                                       0
125 #define mmMMSCH_GPUIOV_ACTIVE_FCNS_1                                                                   0x003a
126 #define mmMMSCH_GPUIOV_ACTIVE_FCNS_1_BASE_IDX                                                          0
127 #define mmMMSCH_GPUIOV_ACTIVE_FCN_ID_1                                                                 0x003b
128 #define mmMMSCH_GPUIOV_ACTIVE_FCN_ID_1_BASE_IDX                                                        0
129 #define mmMMSCH_GPUIOV_DW6_1                                                                           0x003c
130 #define mmMMSCH_GPUIOV_DW6_1_BASE_IDX                                                                  0
131 #define mmMMSCH_GPUIOV_DW7_1                                                                           0x003d
132 #define mmMMSCH_GPUIOV_DW7_1_BASE_IDX                                                                  0
133 #define mmMMSCH_GPUIOV_DW8_1                                                                           0x003e
134 #define mmMMSCH_GPUIOV_DW8_1_BASE_IDX                                                                  0
135 #define mmMMSCH_GPUIOV_CNTXT                                                                           0x003f
136 #define mmMMSCH_GPUIOV_CNTXT_BASE_IDX                                                                  0
137 #define mmMMSCH_SCRATCH_2                                                                              0x0040
138 #define mmMMSCH_SCRATCH_2_BASE_IDX                                                                     0
139 #define mmMMSCH_SCRATCH_3                                                                              0x0041
140 #define mmMMSCH_SCRATCH_3_BASE_IDX                                                                     0
141 #define mmMMSCH_SCRATCH_4                                                                              0x0042
142 #define mmMMSCH_SCRATCH_4_BASE_IDX                                                                     0
143 #define mmMMSCH_SCRATCH_5                                                                              0x0043
144 #define mmMMSCH_SCRATCH_5_BASE_IDX                                                                     0
145 #define mmMMSCH_SCRATCH_6                                                                              0x0044
146 #define mmMMSCH_SCRATCH_6_BASE_IDX                                                                     0
147 #define mmMMSCH_SCRATCH_7                                                                              0x0045
148 #define mmMMSCH_SCRATCH_7_BASE_IDX                                                                     0
149 #define mmMMSCH_VFID_FIFO_HEAD_0                                                                       0x0046
150 #define mmMMSCH_VFID_FIFO_HEAD_0_BASE_IDX                                                              0
151 #define mmMMSCH_VFID_FIFO_TAIL_0                                                                       0x0047
152 #define mmMMSCH_VFID_FIFO_TAIL_0_BASE_IDX                                                              0
153 #define mmMMSCH_VFID_FIFO_HEAD_1                                                                       0x0048
154 #define mmMMSCH_VFID_FIFO_HEAD_1_BASE_IDX                                                              0
155 #define mmMMSCH_VFID_FIFO_TAIL_1                                                                       0x0049
156 #define mmMMSCH_VFID_FIFO_TAIL_1_BASE_IDX                                                              0
157 #define mmMMSCH_NACK_STATUS                                                                            0x004a
158 #define mmMMSCH_NACK_STATUS_BASE_IDX                                                                   0
159 #define mmMMSCH_VF_MAILBOX0_DATA                                                                       0x004b
160 #define mmMMSCH_VF_MAILBOX0_DATA_BASE_IDX                                                              0
161 #define mmMMSCH_VF_MAILBOX1_DATA                                                                       0x004c
162 #define mmMMSCH_VF_MAILBOX1_DATA_BASE_IDX                                                              0
163 #define mmMMSCH_GPUIOV_SCH_BLOCK_IP_0                                                                  0x004d
164 #define mmMMSCH_GPUIOV_SCH_BLOCK_IP_0_BASE_IDX                                                         0
165 #define mmMMSCH_GPUIOV_CMD_STATUS_IP_0                                                                 0x004e
166 #define mmMMSCH_GPUIOV_CMD_STATUS_IP_0_BASE_IDX                                                        0
167 #define mmMMSCH_GPUIOV_ACTIVE_FCN_ID_IP_0                                                              0x004f
168 #define mmMMSCH_GPUIOV_ACTIVE_FCN_ID_IP_0_BASE_IDX                                                     0
169 #define mmMMSCH_GPUIOV_SCH_BLOCK_IP_1                                                                  0x0050
170 #define mmMMSCH_GPUIOV_SCH_BLOCK_IP_1_BASE_IDX                                                         0
171 #define mmMMSCH_GPUIOV_CMD_STATUS_IP_1                                                                 0x0051
172 #define mmMMSCH_GPUIOV_CMD_STATUS_IP_1_BASE_IDX                                                        0
173 #define mmMMSCH_GPUIOV_ACTIVE_FCN_ID_IP_1                                                              0x0052
174 #define mmMMSCH_GPUIOV_ACTIVE_FCN_ID_IP_1_BASE_IDX                                                     0
175 #define mmMMSCH_GPUIOV_CNTXT_IP                                                                        0x0053
176 #define mmMMSCH_GPUIOV_CNTXT_IP_BASE_IDX                                                               0
177 #define mmMMSCH_GPUIOV_SCH_BLOCK_2                                                                     0x0054
178 #define mmMMSCH_GPUIOV_SCH_BLOCK_2_BASE_IDX                                                            0
179 #define mmMMSCH_GPUIOV_CMD_CONTROL_2                                                                   0x0055
180 #define mmMMSCH_GPUIOV_CMD_CONTROL_2_BASE_IDX                                                          0
181 #define mmMMSCH_GPUIOV_CMD_STATUS_2                                                                    0x0056
182 #define mmMMSCH_GPUIOV_CMD_STATUS_2_BASE_IDX                                                           0
183 #define mmMMSCH_GPUIOV_VM_BUSY_STATUS_2                                                                0x0057
184 #define mmMMSCH_GPUIOV_VM_BUSY_STATUS_2_BASE_IDX                                                       0
185 #define mmMMSCH_GPUIOV_ACTIVE_FCNS_2                                                                   0x0058
186 #define mmMMSCH_GPUIOV_ACTIVE_FCNS_2_BASE_IDX                                                          0
187 #define mmMMSCH_GPUIOV_ACTIVE_FCN_ID_2                                                                 0x0059
188 #define mmMMSCH_GPUIOV_ACTIVE_FCN_ID_2_BASE_IDX                                                        0
189 #define mmMMSCH_GPUIOV_DW6_2                                                                           0x005a
190 #define mmMMSCH_GPUIOV_DW6_2_BASE_IDX                                                                  0
191 #define mmMMSCH_GPUIOV_DW7_2                                                                           0x005b
192 #define mmMMSCH_GPUIOV_DW7_2_BASE_IDX                                                                  0
193 #define mmMMSCH_GPUIOV_DW8_2                                                                           0x005c
194 #define mmMMSCH_GPUIOV_DW8_2_BASE_IDX                                                                  0
195 #define mmMMSCH_GPUIOV_SCH_BLOCK_IP_2                                                                  0x005d
196 #define mmMMSCH_GPUIOV_SCH_BLOCK_IP_2_BASE_IDX                                                         0
197 #define mmMMSCH_GPUIOV_CMD_STATUS_IP_2                                                                 0x005e
198 #define mmMMSCH_GPUIOV_CMD_STATUS_IP_2_BASE_IDX                                                        0
199 #define mmMMSCH_GPUIOV_ACTIVE_FCN_ID_IP_2                                                              0x005f
200 #define mmMMSCH_GPUIOV_ACTIVE_FCN_ID_IP_2_BASE_IDX                                                     0
201 #define mmMMSCH_VFID_FIFO_HEAD_2                                                                       0x0060
202 #define mmMMSCH_VFID_FIFO_HEAD_2_BASE_IDX                                                              0
203 #define mmMMSCH_VFID_FIFO_TAIL_2                                                                       0x0061
204 #define mmMMSCH_VFID_FIFO_TAIL_2_BASE_IDX                                                              0
205 #define mmMMSCH_VM_BUSY_STATUS_0                                                                       0x0062
206 #define mmMMSCH_VM_BUSY_STATUS_0_BASE_IDX                                                              0
207 #define mmMMSCH_VM_BUSY_STATUS_1                                                                       0x0063
208 #define mmMMSCH_VM_BUSY_STATUS_1_BASE_IDX                                                              0
209 #define mmMMSCH_VM_BUSY_STATUS_2                                                                       0x0064
210 #define mmMMSCH_VM_BUSY_STATUS_2_BASE_IDX                                                              0
211 
212 
213 // addressBlock: uvd0_jpegnpdec
214 // base address: 0x1e200
215 #define mmUVD_JPEG_CNTL                                                                                0x0080
216 #define mmUVD_JPEG_CNTL_BASE_IDX                                                                       0
217 #define mmUVD_JPEG_RB_BASE                                                                             0x0081
218 #define mmUVD_JPEG_RB_BASE_BASE_IDX                                                                    0
219 #define mmUVD_JPEG_RB_WPTR                                                                             0x0082
220 #define mmUVD_JPEG_RB_WPTR_BASE_IDX                                                                    0
221 #define mmUVD_JPEG_RB_RPTR                                                                             0x0083
222 #define mmUVD_JPEG_RB_RPTR_BASE_IDX                                                                    0
223 #define mmUVD_JPEG_RB_SIZE                                                                             0x0084
224 #define mmUVD_JPEG_RB_SIZE_BASE_IDX                                                                    0
225 #define mmUVD_JPEG_DEC_CNT                                                                             0x0085
226 #define mmUVD_JPEG_DEC_CNT_BASE_IDX                                                                    0
227 #define mmUVD_JPEG_SPS_INFO                                                                            0x0086
228 #define mmUVD_JPEG_SPS_INFO_BASE_IDX                                                                   0
229 #define mmUVD_JPEG_SPS1_INFO                                                                           0x0087
230 #define mmUVD_JPEG_SPS1_INFO_BASE_IDX                                                                  0
231 #define mmUVD_JPEG_RE_TIMER                                                                            0x0088
232 #define mmUVD_JPEG_RE_TIMER_BASE_IDX                                                                   0
233 #define mmUVD_JPEG_DEC_SCRATCH0                                                                        0x0089
234 #define mmUVD_JPEG_DEC_SCRATCH0_BASE_IDX                                                               0
235 #define mmUVD_JPEG_INT_EN                                                                              0x008a
236 #define mmUVD_JPEG_INT_EN_BASE_IDX                                                                     0
237 #define mmUVD_JPEG_INT_STAT                                                                            0x008b
238 #define mmUVD_JPEG_INT_STAT_BASE_IDX                                                                   0
239 #define mmUVD_JPEG_TIER_CNTL0                                                                          0x008d
240 #define mmUVD_JPEG_TIER_CNTL0_BASE_IDX                                                                 0
241 #define mmUVD_JPEG_TIER_CNTL1                                                                          0x008e
242 #define mmUVD_JPEG_TIER_CNTL1_BASE_IDX                                                                 0
243 #define mmUVD_JPEG_TIER_CNTL2                                                                          0x008f
244 #define mmUVD_JPEG_TIER_CNTL2_BASE_IDX                                                                 0
245 #define mmUVD_JPEG_TIER_STATUS                                                                         0x0090
246 #define mmUVD_JPEG_TIER_STATUS_BASE_IDX                                                                0
247 #define mmUVD_JPEG_OUTBUF_CNTL                                                                         0x009c
248 #define mmUVD_JPEG_OUTBUF_CNTL_BASE_IDX                                                                0
249 #define mmUVD_JPEG_OUTBUF_WPTR                                                                         0x009d
250 #define mmUVD_JPEG_OUTBUF_WPTR_BASE_IDX                                                                0
251 #define mmUVD_JPEG_OUTBUF_RPTR                                                                         0x009e
252 #define mmUVD_JPEG_OUTBUF_RPTR_BASE_IDX                                                                0
253 #define mmUVD_JPEG_PITCH                                                                               0x009f
254 #define mmUVD_JPEG_PITCH_BASE_IDX                                                                      0
255 #define mmUVD_JPEG_UV_PITCH                                                                            0x00a0
256 #define mmUVD_JPEG_UV_PITCH_BASE_IDX                                                                   0
257 #define mmJPEG_DEC_Y_GFX10_TILING_SURFACE                                                              0x00a4
258 #define mmJPEG_DEC_Y_GFX10_TILING_SURFACE_BASE_IDX                                                     0
259 #define mmJPEG_DEC_UV_GFX10_TILING_SURFACE                                                             0x00a5
260 #define mmJPEG_DEC_UV_GFX10_TILING_SURFACE_BASE_IDX                                                    0
261 #define mmJPEG_DEC_GFX10_ADDR_CONFIG                                                                   0x00a6
262 #define mmJPEG_DEC_GFX10_ADDR_CONFIG_BASE_IDX                                                          0
263 #define mmJPEG_DEC_ADDR_MODE                                                                           0x00a7
264 #define mmJPEG_DEC_ADDR_MODE_BASE_IDX                                                                  0
265 #define mmUVD_JPEG_OUTPUT_XY                                                                           0x00a8
266 #define mmUVD_JPEG_OUTPUT_XY_BASE_IDX                                                                  0
267 #define mmUVD_JPEG_GPCOM_CMD                                                                           0x00a9
268 #define mmUVD_JPEG_GPCOM_CMD_BASE_IDX                                                                  0
269 #define mmUVD_JPEG_GPCOM_DATA0                                                                         0x00aa
270 #define mmUVD_JPEG_GPCOM_DATA0_BASE_IDX                                                                0
271 #define mmUVD_JPEG_GPCOM_DATA1                                                                         0x00ab
272 #define mmUVD_JPEG_GPCOM_DATA1_BASE_IDX                                                                0
273 #define mmUVD_JPEG_INDEX                                                                               0x00ac
274 #define mmUVD_JPEG_INDEX_BASE_IDX                                                                      0
275 #define mmUVD_JPEG_DATA                                                                                0x00ad
276 #define mmUVD_JPEG_DATA_BASE_IDX                                                                       0
277 #define mmUVD_JPEG_SCRATCH1                                                                            0x00ae
278 #define mmUVD_JPEG_SCRATCH1_BASE_IDX                                                                   0
279 #define mmUVD_JPEG_DEC_SOFT_RST                                                                        0x00af
280 #define mmUVD_JPEG_DEC_SOFT_RST_BASE_IDX                                                               0
281 
282 
283 // addressBlock: uvd0_uvd_jpeg_enc_sclk_dec
284 // base address: 0x1e380
285 #define mmUVD_JPEG_ENC_SPS_INFO                                                                        0x00e0
286 #define mmUVD_JPEG_ENC_SPS_INFO_BASE_IDX                                                               0
287 #define mmUVD_JPEG_ENC_SPS_INFO1                                                                       0x00e1
288 #define mmUVD_JPEG_ENC_SPS_INFO1_BASE_IDX                                                              0
289 #define mmUVD_JPEG_ENC_TBL_SIZE                                                                        0x00e2
290 #define mmUVD_JPEG_ENC_TBL_SIZE_BASE_IDX                                                               0
291 #define mmUVD_JPEG_ENC_TBL_CNTL                                                                        0x00e3
292 #define mmUVD_JPEG_ENC_TBL_CNTL_BASE_IDX                                                               0
293 #define mmUVD_JPEG_ENC_MC_REQ_CNTL                                                                     0x00e4
294 #define mmUVD_JPEG_ENC_MC_REQ_CNTL_BASE_IDX                                                            0
295 #define mmUVD_JPEG_ENC_STATUS                                                                          0x00e5
296 #define mmUVD_JPEG_ENC_STATUS_BASE_IDX                                                                 0
297 #define mmUVD_JPEG_ENC_PITCH                                                                           0x00e6
298 #define mmUVD_JPEG_ENC_PITCH_BASE_IDX                                                                  0
299 #define mmUVD_JPEG_ENC_LUMA_BASE                                                                       0x00e7
300 #define mmUVD_JPEG_ENC_LUMA_BASE_BASE_IDX                                                              0
301 #define mmUVD_JPEG_ENC_CHROMAU_BASE                                                                    0x00e8
302 #define mmUVD_JPEG_ENC_CHROMAU_BASE_BASE_IDX                                                           0
303 #define mmUVD_JPEG_ENC_CHROMAV_BASE                                                                    0x00e9
304 #define mmUVD_JPEG_ENC_CHROMAV_BASE_BASE_IDX                                                           0
305 #define mmJPEG_ENC_Y_GFX10_TILING_SURFACE                                                              0x00ea
306 #define mmJPEG_ENC_Y_GFX10_TILING_SURFACE_BASE_IDX                                                     0
307 #define mmJPEG_ENC_UV_GFX10_TILING_SURFACE                                                             0x00eb
308 #define mmJPEG_ENC_UV_GFX10_TILING_SURFACE_BASE_IDX                                                    0
309 #define mmJPEG_ENC_GFX10_ADDR_CONFIG                                                                   0x00ec
310 #define mmJPEG_ENC_GFX10_ADDR_CONFIG_BASE_IDX                                                          0
311 #define mmJPEG_ENC_ADDR_MODE                                                                           0x00ed
312 #define mmJPEG_ENC_ADDR_MODE_BASE_IDX                                                                  0
313 #define mmUVD_JPEG_ENC_GPCOM_CMD                                                                       0x00ee
314 #define mmUVD_JPEG_ENC_GPCOM_CMD_BASE_IDX                                                              0
315 #define mmUVD_JPEG_ENC_GPCOM_DATA0                                                                     0x00ef
316 #define mmUVD_JPEG_ENC_GPCOM_DATA0_BASE_IDX                                                            0
317 #define mmUVD_JPEG_ENC_GPCOM_DATA1                                                                     0x00f0
318 #define mmUVD_JPEG_ENC_GPCOM_DATA1_BASE_IDX                                                            0
319 #define mmUVD_JPEG_TBL_DAT0                                                                            0x00f1
320 #define mmUVD_JPEG_TBL_DAT0_BASE_IDX                                                                   0
321 #define mmUVD_JPEG_TBL_DAT1                                                                            0x00f2
322 #define mmUVD_JPEG_TBL_DAT1_BASE_IDX                                                                   0
323 #define mmUVD_JPEG_TBL_IDX                                                                             0x00f3
324 #define mmUVD_JPEG_TBL_IDX_BASE_IDX                                                                    0
325 #define mmUVD_JPEG_ENC_CGC_CNTL                                                                        0x00f5
326 #define mmUVD_JPEG_ENC_CGC_CNTL_BASE_IDX                                                               0
327 #define mmUVD_JPEG_ENC_SCRATCH0                                                                        0x00f6
328 #define mmUVD_JPEG_ENC_SCRATCH0_BASE_IDX                                                               0
329 #define mmUVD_JPEG_ENC_SOFT_RST                                                                        0x00f7
330 #define mmUVD_JPEG_ENC_SOFT_RST_BASE_IDX                                                               0
331 
332 
333 // addressBlock: uvd0_uvd_jrbc_dec
334 // base address: 0x1e400
335 #define mmUVD_JRBC_RB_WPTR                                                                             0x0100
336 #define mmUVD_JRBC_RB_WPTR_BASE_IDX                                                                    0
337 #define mmUVD_JRBC_RB_CNTL                                                                             0x0101
338 #define mmUVD_JRBC_RB_CNTL_BASE_IDX                                                                    0
339 #define mmUVD_JRBC_IB_SIZE                                                                             0x0102
340 #define mmUVD_JRBC_IB_SIZE_BASE_IDX                                                                    0
341 #define mmUVD_JRBC_URGENT_CNTL                                                                         0x0103
342 #define mmUVD_JRBC_URGENT_CNTL_BASE_IDX                                                                0
343 #define mmUVD_JRBC_RB_REF_DATA                                                                         0x0104
344 #define mmUVD_JRBC_RB_REF_DATA_BASE_IDX                                                                0
345 #define mmUVD_JRBC_RB_COND_RD_TIMER                                                                    0x0105
346 #define mmUVD_JRBC_RB_COND_RD_TIMER_BASE_IDX                                                           0
347 #define mmUVD_JRBC_SOFT_RESET                                                                          0x0108
348 #define mmUVD_JRBC_SOFT_RESET_BASE_IDX                                                                 0
349 #define mmUVD_JRBC_STATUS                                                                              0x0109
350 #define mmUVD_JRBC_STATUS_BASE_IDX                                                                     0
351 #define mmUVD_JRBC_RB_RPTR                                                                             0x010a
352 #define mmUVD_JRBC_RB_RPTR_BASE_IDX                                                                    0
353 #define mmUVD_JRBC_RB_BUF_STATUS                                                                       0x010b
354 #define mmUVD_JRBC_RB_BUF_STATUS_BASE_IDX                                                              0
355 #define mmUVD_JRBC_IB_BUF_STATUS                                                                       0x010c
356 #define mmUVD_JRBC_IB_BUF_STATUS_BASE_IDX                                                              0
357 #define mmUVD_JRBC_IB_SIZE_UPDATE                                                                      0x010d
358 #define mmUVD_JRBC_IB_SIZE_UPDATE_BASE_IDX                                                             0
359 #define mmUVD_JRBC_IB_COND_RD_TIMER                                                                    0x010e
360 #define mmUVD_JRBC_IB_COND_RD_TIMER_BASE_IDX                                                           0
361 #define mmUVD_JRBC_IB_REF_DATA                                                                         0x010f
362 #define mmUVD_JRBC_IB_REF_DATA_BASE_IDX                                                                0
363 #define mmUVD_JPEG_PREEMPT_CMD                                                                         0x0110
364 #define mmUVD_JPEG_PREEMPT_CMD_BASE_IDX                                                                0
365 #define mmUVD_JPEG_PREEMPT_FENCE_DATA0                                                                 0x0111
366 #define mmUVD_JPEG_PREEMPT_FENCE_DATA0_BASE_IDX                                                        0
367 #define mmUVD_JPEG_PREEMPT_FENCE_DATA1                                                                 0x0112
368 #define mmUVD_JPEG_PREEMPT_FENCE_DATA1_BASE_IDX                                                        0
369 #define mmUVD_JRBC_RB_SIZE                                                                             0x0113
370 #define mmUVD_JRBC_RB_SIZE_BASE_IDX                                                                    0
371 #define mmUVD_JRBC_SCRATCH0                                                                            0x0114
372 #define mmUVD_JRBC_SCRATCH0_BASE_IDX                                                                   0
373 
374 
375 // addressBlock: uvd0_uvd_jrbc_enc_dec
376 // base address: 0x1e480
377 #define mmUVD_JRBC_ENC_RB_WPTR                                                                         0x0120
378 #define mmUVD_JRBC_ENC_RB_WPTR_BASE_IDX                                                                0
379 #define mmUVD_JRBC_ENC_RB_CNTL                                                                         0x0121
380 #define mmUVD_JRBC_ENC_RB_CNTL_BASE_IDX                                                                0
381 #define mmUVD_JRBC_ENC_IB_SIZE                                                                         0x0122
382 #define mmUVD_JRBC_ENC_IB_SIZE_BASE_IDX                                                                0
383 #define mmUVD_JRBC_ENC_URGENT_CNTL                                                                     0x0123
384 #define mmUVD_JRBC_ENC_URGENT_CNTL_BASE_IDX                                                            0
385 #define mmUVD_JRBC_ENC_RB_REF_DATA                                                                     0x0124
386 #define mmUVD_JRBC_ENC_RB_REF_DATA_BASE_IDX                                                            0
387 #define mmUVD_JRBC_ENC_RB_COND_RD_TIMER                                                                0x0125
388 #define mmUVD_JRBC_ENC_RB_COND_RD_TIMER_BASE_IDX                                                       0
389 #define mmUVD_JRBC_ENC_SOFT_RESET                                                                      0x0128
390 #define mmUVD_JRBC_ENC_SOFT_RESET_BASE_IDX                                                             0
391 #define mmUVD_JRBC_ENC_STATUS                                                                          0x0129
392 #define mmUVD_JRBC_ENC_STATUS_BASE_IDX                                                                 0
393 #define mmUVD_JRBC_ENC_RB_RPTR                                                                         0x012a
394 #define mmUVD_JRBC_ENC_RB_RPTR_BASE_IDX                                                                0
395 #define mmUVD_JRBC_ENC_RB_BUF_STATUS                                                                   0x012b
396 #define mmUVD_JRBC_ENC_RB_BUF_STATUS_BASE_IDX                                                          0
397 #define mmUVD_JRBC_ENC_IB_BUF_STATUS                                                                   0x012c
398 #define mmUVD_JRBC_ENC_IB_BUF_STATUS_BASE_IDX                                                          0
399 #define mmUVD_JRBC_ENC_IB_SIZE_UPDATE                                                                  0x012d
400 #define mmUVD_JRBC_ENC_IB_SIZE_UPDATE_BASE_IDX                                                         0
401 #define mmUVD_JRBC_ENC_IB_COND_RD_TIMER                                                                0x012e
402 #define mmUVD_JRBC_ENC_IB_COND_RD_TIMER_BASE_IDX                                                       0
403 #define mmUVD_JRBC_ENC_IB_REF_DATA                                                                     0x012f
404 #define mmUVD_JRBC_ENC_IB_REF_DATA_BASE_IDX                                                            0
405 #define mmUVD_JPEG_ENC_PREEMPT_CMD                                                                     0x0130
406 #define mmUVD_JPEG_ENC_PREEMPT_CMD_BASE_IDX                                                            0
407 #define mmUVD_JPEG_ENC_PREEMPT_FENCE_DATA0                                                             0x0131
408 #define mmUVD_JPEG_ENC_PREEMPT_FENCE_DATA0_BASE_IDX                                                    0
409 #define mmUVD_JPEG_ENC_PREEMPT_FENCE_DATA1                                                             0x0132
410 #define mmUVD_JPEG_ENC_PREEMPT_FENCE_DATA1_BASE_IDX                                                    0
411 #define mmUVD_JRBC_ENC_RB_SIZE                                                                         0x0133
412 #define mmUVD_JRBC_ENC_RB_SIZE_BASE_IDX                                                                0
413 #define mmUVD_JRBC_ENC_SCRATCH0                                                                        0x0134
414 #define mmUVD_JRBC_ENC_SCRATCH0_BASE_IDX                                                               0
415 
416 
417 // addressBlock: uvd0_uvd_jmi_dec
418 // base address: 0x1e500
419 #define mmUVD_JADP_MCIF_URGENT_CTRL                                                                    0x0141
420 #define mmUVD_JADP_MCIF_URGENT_CTRL_BASE_IDX                                                           0
421 #define mmUVD_JMI_URGENT_CTRL                                                                          0x0142
422 #define mmUVD_JMI_URGENT_CTRL_BASE_IDX                                                                 0
423 #define mmUVD_JPEG_DEC_PF_CTRL                                                                         0x0143
424 #define mmUVD_JPEG_DEC_PF_CTRL_BASE_IDX                                                                0
425 #define mmUVD_JPEG_ENC_PF_CTRL                                                                         0x0144
426 #define mmUVD_JPEG_ENC_PF_CTRL_BASE_IDX                                                                0
427 #define mmUVD_JMI_CTRL                                                                                 0x0145
428 #define mmUVD_JMI_CTRL_BASE_IDX                                                                        0
429 #define mmUVD_LMI_JRBC_CTRL                                                                            0x0146
430 #define mmUVD_LMI_JRBC_CTRL_BASE_IDX                                                                   0
431 #define mmUVD_LMI_JPEG_CTRL                                                                            0x0147
432 #define mmUVD_LMI_JPEG_CTRL_BASE_IDX                                                                   0
433 #define mmUVD_JMI_EJRBC_CTRL                                                                           0x0148
434 #define mmUVD_JMI_EJRBC_CTRL_BASE_IDX                                                                  0
435 #define mmUVD_LMI_EJPEG_CTRL                                                                           0x0149
436 #define mmUVD_LMI_EJPEG_CTRL_BASE_IDX                                                                  0
437 #define mmUVD_JMI_SCALER_CTRL                                                                          0x014a
438 #define mmUVD_JMI_SCALER_CTRL_BASE_IDX                                                                 0
439 #define mmJPEG_LMI_DROP                                                                                0x014b
440 #define mmJPEG_LMI_DROP_BASE_IDX                                                                       0
441 #define mmUVD_JMI_EJPEG_DROP                                                                           0x014c
442 #define mmUVD_JMI_EJPEG_DROP_BASE_IDX                                                                  0
443 #define mmJPEG_MEMCHECK_CLAMPING                                                                       0x014d
444 #define mmJPEG_MEMCHECK_CLAMPING_BASE_IDX                                                              0
445 #define mmUVD_JMI_EJPEG_MEMCHECK_CLAMPING                                                              0x014e
446 #define mmUVD_JMI_EJPEG_MEMCHECK_CLAMPING_BASE_IDX                                                     0
447 #define mmUVD_LMI_JRBC_IB_VMID                                                                         0x014f
448 #define mmUVD_LMI_JRBC_IB_VMID_BASE_IDX                                                                0
449 #define mmUVD_LMI_JRBC_RB_VMID                                                                         0x0150
450 #define mmUVD_LMI_JRBC_RB_VMID_BASE_IDX                                                                0
451 #define mmUVD_LMI_JPEG_VMID                                                                            0x0151
452 #define mmUVD_LMI_JPEG_VMID_BASE_IDX                                                                   0
453 #define mmUVD_JMI_ENC_JRBC_IB_VMID                                                                     0x0152
454 #define mmUVD_JMI_ENC_JRBC_IB_VMID_BASE_IDX                                                            0
455 #define mmUVD_JMI_ENC_JRBC_RB_VMID                                                                     0x0153
456 #define mmUVD_JMI_ENC_JRBC_RB_VMID_BASE_IDX                                                            0
457 #define mmUVD_JMI_ENC_JPEG_VMID                                                                        0x0154
458 #define mmUVD_JMI_ENC_JPEG_VMID_BASE_IDX                                                               0
459 #define mmJPEG_MEMCHECK_SAFE_ADDR                                                                      0x0157
460 #define mmJPEG_MEMCHECK_SAFE_ADDR_BASE_IDX                                                             0
461 #define mmJPEG_MEMCHECK_SAFE_ADDR_64BIT                                                                0x0158
462 #define mmJPEG_MEMCHECK_SAFE_ADDR_64BIT_BASE_IDX                                                       0
463 #define mmUVD_JMI_LAT_CTRL                                                                             0x0159
464 #define mmUVD_JMI_LAT_CTRL_BASE_IDX                                                                    0
465 #define mmUVD_JMI_LAT_CNTR                                                                             0x015a
466 #define mmUVD_JMI_LAT_CNTR_BASE_IDX                                                                    0
467 #define mmUVD_JMI_AVG_LAT_CNTR                                                                         0x015b
468 #define mmUVD_JMI_AVG_LAT_CNTR_BASE_IDX                                                                0
469 #define mmUVD_JMI_PERFMON_CTRL                                                                         0x015c
470 #define mmUVD_JMI_PERFMON_CTRL_BASE_IDX                                                                0
471 #define mmUVD_JMI_PERFMON_COUNT_LO                                                                     0x015d
472 #define mmUVD_JMI_PERFMON_COUNT_LO_BASE_IDX                                                            0
473 #define mmUVD_JMI_PERFMON_COUNT_HI                                                                     0x015e
474 #define mmUVD_JMI_PERFMON_COUNT_HI_BASE_IDX                                                            0
475 #define mmUVD_JMI_CLEAN_STATUS                                                                         0x015f
476 #define mmUVD_JMI_CLEAN_STATUS_BASE_IDX                                                                0
477 #define mmUVD_LMI_JPEG_READ_64BIT_BAR_LOW                                                              0x0160
478 #define mmUVD_LMI_JPEG_READ_64BIT_BAR_LOW_BASE_IDX                                                     0
479 #define mmUVD_LMI_JPEG_READ_64BIT_BAR_HIGH                                                             0x0161
480 #define mmUVD_LMI_JPEG_READ_64BIT_BAR_HIGH_BASE_IDX                                                    0
481 #define mmUVD_LMI_JPEG_WRITE_64BIT_BAR_LOW                                                             0x0162
482 #define mmUVD_LMI_JPEG_WRITE_64BIT_BAR_LOW_BASE_IDX                                                    0
483 #define mmUVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH                                                            0x0163
484 #define mmUVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH_BASE_IDX                                                   0
485 #define mmUVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW                                                     0x0164
486 #define mmUVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW_BASE_IDX                                            0
487 #define mmUVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH                                                    0x0165
488 #define mmUVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH_BASE_IDX                                           0
489 #define mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW                                                                0x0166
490 #define mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW_BASE_IDX                                                       0
491 #define mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH                                                               0x0167
492 #define mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH_BASE_IDX                                                      0
493 #define mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW                                                                0x0168
494 #define mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW_BASE_IDX                                                       0
495 #define mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH                                                               0x0169
496 #define mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH_BASE_IDX                                                      0
497 #define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW                                                         0x016a
498 #define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_BASE_IDX                                                0
499 #define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH                                                        0x016b
500 #define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_BASE_IDX                                               0
501 #define mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW                                                         0x016c
502 #define mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW_BASE_IDX                                                0
503 #define mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH                                                        0x016d
504 #define mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH_BASE_IDX                                               0
505 #define mmUVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW                                                         0x016e
506 #define mmUVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW_BASE_IDX                                                0
507 #define mmUVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH                                                        0x016f
508 #define mmUVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH_BASE_IDX                                               0
509 #define mmUVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_LOW                                                         0x0170
510 #define mmUVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_LOW_BASE_IDX                                                0
511 #define mmUVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_HIGH                                                        0x0171
512 #define mmUVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_HIGH_BASE_IDX                                               0
513 #define mmUVD_JMI_PEL_RD_64BIT_BAR_LOW                                                                 0x0172
514 #define mmUVD_JMI_PEL_RD_64BIT_BAR_LOW_BASE_IDX                                                        0
515 #define mmUVD_JMI_PEL_RD_64BIT_BAR_HIGH                                                                0x0173
516 #define mmUVD_JMI_PEL_RD_64BIT_BAR_HIGH_BASE_IDX                                                       0
517 #define mmUVD_JMI_BS_WR_64BIT_BAR_LOW                                                                  0x0174
518 #define mmUVD_JMI_BS_WR_64BIT_BAR_LOW_BASE_IDX                                                         0
519 #define mmUVD_JMI_BS_WR_64BIT_BAR_HIGH                                                                 0x0175
520 #define mmUVD_JMI_BS_WR_64BIT_BAR_HIGH_BASE_IDX                                                        0
521 #define mmUVD_JMI_SCALAR_RD_64BIT_BAR_LOW                                                              0x0176
522 #define mmUVD_JMI_SCALAR_RD_64BIT_BAR_LOW_BASE_IDX                                                     0
523 #define mmUVD_JMI_SCALAR_RD_64BIT_BAR_HIGH                                                             0x0177
524 #define mmUVD_JMI_SCALAR_RD_64BIT_BAR_HIGH_BASE_IDX                                                    0
525 #define mmUVD_JMI_SCALAR_WR_64BIT_BAR_LOW                                                              0x0178
526 #define mmUVD_JMI_SCALAR_WR_64BIT_BAR_LOW_BASE_IDX                                                     0
527 #define mmUVD_JMI_SCALAR_WR_64BIT_BAR_HIGH                                                             0x0179
528 #define mmUVD_JMI_SCALAR_WR_64BIT_BAR_HIGH_BASE_IDX                                                    0
529 #define mmUVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_LOW                                                    0x017a
530 #define mmUVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_LOW_BASE_IDX                                           0
531 #define mmUVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_HIGH                                                   0x017b
532 #define mmUVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_HIGH_BASE_IDX                                          0
533 #define mmUVD_LMI_EJRBC_RB_64BIT_BAR_LOW                                                               0x017c
534 #define mmUVD_LMI_EJRBC_RB_64BIT_BAR_LOW_BASE_IDX                                                      0
535 #define mmUVD_LMI_EJRBC_RB_64BIT_BAR_HIGH                                                              0x017d
536 #define mmUVD_LMI_EJRBC_RB_64BIT_BAR_HIGH_BASE_IDX                                                     0
537 #define mmUVD_LMI_EJRBC_IB_64BIT_BAR_LOW                                                               0x017e
538 #define mmUVD_LMI_EJRBC_IB_64BIT_BAR_LOW_BASE_IDX                                                      0
539 #define mmUVD_LMI_EJRBC_IB_64BIT_BAR_HIGH                                                              0x017f
540 #define mmUVD_LMI_EJRBC_IB_64BIT_BAR_HIGH_BASE_IDX                                                     0
541 #define mmUVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_LOW                                                        0x0180
542 #define mmUVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_LOW_BASE_IDX                                               0
543 #define mmUVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_HIGH                                                       0x0181
544 #define mmUVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_HIGH_BASE_IDX                                              0
545 #define mmUVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_LOW                                                        0x0182
546 #define mmUVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_LOW_BASE_IDX                                               0
547 #define mmUVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_HIGH                                                       0x0183
548 #define mmUVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_HIGH_BASE_IDX                                              0
549 #define mmUVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_LOW                                                        0x0184
550 #define mmUVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_LOW_BASE_IDX                                               0
551 #define mmUVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_HIGH                                                       0x0185
552 #define mmUVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_HIGH_BASE_IDX                                              0
553 #define mmUVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_LOW                                                        0x0186
554 #define mmUVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_LOW_BASE_IDX                                               0
555 #define mmUVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_HIGH                                                       0x0187
556 #define mmUVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_HIGH_BASE_IDX                                              0
557 #define mmUVD_LMI_JPEG_PREEMPT_VMID                                                                    0x0188
558 #define mmUVD_LMI_JPEG_PREEMPT_VMID_BASE_IDX                                                           0
559 #define mmUVD_LMI_ENC_JPEG_PREEMPT_VMID                                                                0x0189
560 #define mmUVD_LMI_ENC_JPEG_PREEMPT_VMID_BASE_IDX                                                       0
561 #define mmUVD_LMI_JPEG2_VMID                                                                           0x018a
562 #define mmUVD_LMI_JPEG2_VMID_BASE_IDX                                                                  0
563 #define mmUVD_LMI_JPEG2_READ_64BIT_BAR_LOW                                                             0x018b
564 #define mmUVD_LMI_JPEG2_READ_64BIT_BAR_LOW_BASE_IDX                                                    0
565 #define mmUVD_LMI_JPEG2_READ_64BIT_BAR_HIGH                                                            0x018c
566 #define mmUVD_LMI_JPEG2_READ_64BIT_BAR_HIGH_BASE_IDX                                                   0
567 #define mmUVD_LMI_JPEG2_WRITE_64BIT_BAR_LOW                                                            0x018d
568 #define mmUVD_LMI_JPEG2_WRITE_64BIT_BAR_LOW_BASE_IDX                                                   0
569 #define mmUVD_LMI_JPEG2_WRITE_64BIT_BAR_HIGH                                                           0x018e
570 #define mmUVD_LMI_JPEG2_WRITE_64BIT_BAR_HIGH_BASE_IDX                                                  0
571 #define mmUVD_LMI_JPEG_CTRL2                                                                           0x018f
572 #define mmUVD_LMI_JPEG_CTRL2_BASE_IDX                                                                  0
573 #define mmUVD_JMI_DEC_SWAP_CNTL                                                                        0x0190
574 #define mmUVD_JMI_DEC_SWAP_CNTL_BASE_IDX                                                               0
575 #define mmUVD_JMI_ENC_SWAP_CNTL                                                                        0x0191
576 #define mmUVD_JMI_ENC_SWAP_CNTL_BASE_IDX                                                               0
577 #define mmUVD_JMI_CNTL                                                                                 0x0192
578 #define mmUVD_JMI_CNTL_BASE_IDX                                                                        0
579 #define mmUVD_JMI_ATOMIC_CNTL                                                                          0x0193
580 #define mmUVD_JMI_ATOMIC_CNTL_BASE_IDX                                                                 0
581 #define mmUVD_JMI_ATOMIC_CNTL2                                                                         0x0194
582 #define mmUVD_JMI_ATOMIC_CNTL2_BASE_IDX                                                                0
583 #define mmUVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_LOW                                                     0x0195
584 #define mmUVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_LOW_BASE_IDX                                            0
585 #define mmUVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_HIGH                                                    0x0196
586 #define mmUVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_HIGH_BASE_IDX                                           0
587 #define mmUVD_JMI_ATOMIC_USER1_WRITE_64BIT_BAR_LOW                                                     0x0197
588 #define mmUVD_JMI_ATOMIC_USER1_WRITE_64BIT_BAR_LOW_BASE_IDX                                            0
589 #define mmUVD_JMI_ATOMIC_USER1_WRITE_64BIT_BAR_HIGH                                                    0x0198
590 #define mmUVD_JMI_ATOMIC_USER1_WRITE_64BIT_BAR_HIGH_BASE_IDX                                           0
591 #define mmJPEG2_LMI_DROP                                                                               0x0199
592 #define mmJPEG2_LMI_DROP_BASE_IDX                                                                      0
593 #define mmUVD_JMI_HUFF_FENCE_64BIT_BAR_LOW                                                             0x019a
594 #define mmUVD_JMI_HUFF_FENCE_64BIT_BAR_LOW_BASE_IDX                                                    0
595 #define mmUVD_JMI_HUFF_FENCE_64BIT_BAR_HIGH                                                            0x019b
596 #define mmUVD_JMI_HUFF_FENCE_64BIT_BAR_HIGH_BASE_IDX                                                   0
597 #define mmUVD_JMI_DEC_SWAP_CNTL2                                                                       0x019c
598 #define mmUVD_JMI_DEC_SWAP_CNTL2_BASE_IDX                                                              0
599 #define mmUVD_JPEG_DEC2_PF_CTRL                                                                        0x019f
600 #define mmUVD_JPEG_DEC2_PF_CTRL_BASE_IDX                                                               0
601 
602 
603 // addressBlock: uvd0_uvd_jpeg_common_dec
604 // base address: 0x1e700
605 #define mmJPEG_SOFT_RESET_STATUS                                                                       0x01c0
606 #define mmJPEG_SOFT_RESET_STATUS_BASE_IDX                                                              0
607 #define mmJPEG_SYS_INT_EN                                                                              0x01c1
608 #define mmJPEG_SYS_INT_EN_BASE_IDX                                                                     0
609 #define mmJPEG_SYS_INT_STATUS                                                                          0x01c2
610 #define mmJPEG_SYS_INT_STATUS_BASE_IDX                                                                 0
611 #define mmJPEG_SYS_INT_ACK                                                                             0x01c3
612 #define mmJPEG_SYS_INT_ACK_BASE_IDX                                                                    0
613 #define mmJPEG_MEMCHECK_SYS_INT_EN                                                                     0x01c4
614 #define mmJPEG_MEMCHECK_SYS_INT_EN_BASE_IDX                                                            0
615 #define mmJPEG_MEMCHECK_SYS_INT_STAT                                                                   0x01c5
616 #define mmJPEG_MEMCHECK_SYS_INT_STAT_BASE_IDX                                                          0
617 #define mmJPEG_MEMCHECK_SYS_INT_ACK                                                                    0x01c6
618 #define mmJPEG_MEMCHECK_SYS_INT_ACK_BASE_IDX                                                           0
619 #define mmUVD_JPEG_IOV_ACTIVE_FCN_ID                                                                   0x01c7
620 #define mmUVD_JPEG_IOV_ACTIVE_FCN_ID_BASE_IDX                                                          0
621 #define mmJPEG_MASTINT_EN                                                                              0x01c8
622 #define mmJPEG_MASTINT_EN_BASE_IDX                                                                     0
623 #define mmJPEG_IH_CTRL                                                                                 0x01c9
624 #define mmJPEG_IH_CTRL_BASE_IDX                                                                        0
625 #define mmJRBBM_ARB_CTRL                                                                               0x01cb
626 #define mmJRBBM_ARB_CTRL_BASE_IDX                                                                      0
627 
628 
629 // addressBlock: uvd0_uvd_jpeg_common_sclk_dec
630 // base address: 0x1e780
631 #define mmJPEG_CGC_GATE                                                                                0x01e0
632 #define mmJPEG_CGC_GATE_BASE_IDX                                                                       0
633 #define mmJPEG_CGC_CTRL                                                                                0x01e1
634 #define mmJPEG_CGC_CTRL_BASE_IDX                                                                       0
635 #define mmJPEG_CGC_STATUS                                                                              0x01e2
636 #define mmJPEG_CGC_STATUS_BASE_IDX                                                                     0
637 #define mmJPEG_COMN_CGC_MEM_CTRL                                                                       0x01e3
638 #define mmJPEG_COMN_CGC_MEM_CTRL_BASE_IDX                                                              0
639 #define mmJPEG_DEC_CGC_MEM_CTRL                                                                        0x01e4
640 #define mmJPEG_DEC_CGC_MEM_CTRL_BASE_IDX                                                               0
641 #define mmJPEG2_DEC_CGC_MEM_CTRL                                                                       0x01e5
642 #define mmJPEG2_DEC_CGC_MEM_CTRL_BASE_IDX                                                              0
643 #define mmJPEG_ENC_CGC_MEM_CTRL                                                                        0x01e6
644 #define mmJPEG_ENC_CGC_MEM_CTRL_BASE_IDX                                                               0
645 #define mmJPEG_SOFT_RESET2                                                                             0x01e7
646 #define mmJPEG_SOFT_RESET2_BASE_IDX                                                                    0
647 #define mmJPEG_PERF_BANK_CONF                                                                          0x01e8
648 #define mmJPEG_PERF_BANK_CONF_BASE_IDX                                                                 0
649 #define mmJPEG_PERF_BANK_EVENT_SEL                                                                     0x01e9
650 #define mmJPEG_PERF_BANK_EVENT_SEL_BASE_IDX                                                            0
651 #define mmJPEG_PERF_BANK_COUNT0                                                                        0x01ea
652 #define mmJPEG_PERF_BANK_COUNT0_BASE_IDX                                                               0
653 #define mmJPEG_PERF_BANK_COUNT1                                                                        0x01eb
654 #define mmJPEG_PERF_BANK_COUNT1_BASE_IDX                                                               0
655 #define mmJPEG_PERF_BANK_COUNT2                                                                        0x01ec
656 #define mmJPEG_PERF_BANK_COUNT2_BASE_IDX                                                               0
657 #define mmJPEG_PERF_BANK_COUNT3                                                                        0x01ed
658 #define mmJPEG_PERF_BANK_COUNT3_BASE_IDX                                                               0
659 
660 
661 // addressBlock: uvd0_uvd_pg_dec
662 // base address: 0x1f800
663 #define mmUVD_PGFSM_CONFIG                                                                             0x0000
664 #define mmUVD_PGFSM_CONFIG_BASE_IDX                                                                    1
665 #define mmUVD_PGFSM_STATUS                                                                             0x0001
666 #define mmUVD_PGFSM_STATUS_BASE_IDX                                                                    1
667 #define mmUVD_POWER_STATUS                                                                             0x0004
668 #define mmUVD_POWER_STATUS_BASE_IDX                                                                    1
669 #define mmUVD_PG_IND_INDEX                                                                             0x0005
670 #define mmUVD_PG_IND_INDEX_BASE_IDX                                                                    1
671 #define mmUVD_PG_IND_DATA                                                                              0x0006
672 #define mmUVD_PG_IND_DATA_BASE_IDX                                                                     1
673 #define mmCC_UVD_HARVESTING                                                                            0x0007
674 #define mmCC_UVD_HARVESTING_BASE_IDX                                                                   1
675 #define mmUVD_JPEG_POWER_STATUS                                                                        0x000a
676 #define mmUVD_JPEG_POWER_STATUS_BASE_IDX                                                               1
677 #define mmUVD_MC_DJPEG_RD_SPACE                                                                        0x000d
678 #define mmUVD_MC_DJPEG_RD_SPACE_BASE_IDX                                                               1
679 #define mmUVD_MC_DJPEG_WR_SPACE                                                                        0x000e
680 #define mmUVD_MC_DJPEG_WR_SPACE_BASE_IDX                                                               1
681 #define mmUVD_MC_EJPEG_RD_SPACE                                                                        0x000f
682 #define mmUVD_MC_EJPEG_RD_SPACE_BASE_IDX                                                               1
683 #define mmUVD_MC_EJPEG_WR_SPACE                                                                        0x0010
684 #define mmUVD_MC_EJPEG_WR_SPACE_BASE_IDX                                                               1
685 #define mmUVD_DPG_LMA_CTL                                                                              0x0011
686 #define mmUVD_DPG_LMA_CTL_BASE_IDX                                                                     1
687 #define mmUVD_DPG_LMA_DATA                                                                             0x0012
688 #define mmUVD_DPG_LMA_DATA_BASE_IDX                                                                    1
689 #define mmUVD_DPG_LMA_MASK                                                                             0x0013
690 #define mmUVD_DPG_LMA_MASK_BASE_IDX                                                                    1
691 #define mmUVD_DPG_PAUSE                                                                                0x0014
692 #define mmUVD_DPG_PAUSE_BASE_IDX                                                                       1
693 #define mmUVD_SCRATCH1                                                                                 0x0015
694 #define mmUVD_SCRATCH1_BASE_IDX                                                                        1
695 #define mmUVD_SCRATCH2                                                                                 0x0016
696 #define mmUVD_SCRATCH2_BASE_IDX                                                                        1
697 #define mmUVD_SCRATCH3                                                                                 0x0017
698 #define mmUVD_SCRATCH3_BASE_IDX                                                                        1
699 #define mmUVD_SCRATCH4                                                                                 0x0018
700 #define mmUVD_SCRATCH4_BASE_IDX                                                                        1
701 #define mmUVD_SCRATCH5                                                                                 0x0019
702 #define mmUVD_SCRATCH5_BASE_IDX                                                                        1
703 #define mmUVD_SCRATCH6                                                                                 0x001a
704 #define mmUVD_SCRATCH6_BASE_IDX                                                                        1
705 #define mmUVD_SCRATCH7                                                                                 0x001b
706 #define mmUVD_SCRATCH7_BASE_IDX                                                                        1
707 #define mmUVD_SCRATCH8                                                                                 0x001c
708 #define mmUVD_SCRATCH8_BASE_IDX                                                                        1
709 #define mmUVD_SCRATCH9                                                                                 0x001d
710 #define mmUVD_SCRATCH9_BASE_IDX                                                                        1
711 #define mmUVD_SCRATCH10                                                                                0x001e
712 #define mmUVD_SCRATCH10_BASE_IDX                                                                       1
713 #define mmUVD_SCRATCH11                                                                                0x001f
714 #define mmUVD_SCRATCH11_BASE_IDX                                                                       1
715 #define mmUVD_SCRATCH12                                                                                0x0020
716 #define mmUVD_SCRATCH12_BASE_IDX                                                                       1
717 #define mmUVD_SCRATCH13                                                                                0x0021
718 #define mmUVD_SCRATCH13_BASE_IDX                                                                       1
719 #define mmUVD_SCRATCH14                                                                                0x0022
720 #define mmUVD_SCRATCH14_BASE_IDX                                                                       1
721 #define mmUVD_FREE_COUNTER_REG                                                                         0x0024
722 #define mmUVD_FREE_COUNTER_REG_BASE_IDX                                                                1
723 #define mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW                                                         0x0025
724 #define mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW_BASE_IDX                                                1
725 #define mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH                                                        0x0026
726 #define mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH_BASE_IDX                                               1
727 #define mmUVD_DPG_VCPU_CACHE_OFFSET0                                                                   0x0027
728 #define mmUVD_DPG_VCPU_CACHE_OFFSET0_BASE_IDX                                                          1
729 #define mmUVD_DPG_LMI_VCPU_CACHE_VMID                                                                  0x0028
730 #define mmUVD_DPG_LMI_VCPU_CACHE_VMID_BASE_IDX                                                         1
731 #define mmUVD_REG_FILTER_EN                                                                            0x0029
732 #define mmUVD_REG_FILTER_EN_BASE_IDX                                                                   1
733 #define mmCC_UVD_VCPU_ERR_DETECT_BOT_LO                                                                0x0031
734 #define mmCC_UVD_VCPU_ERR_DETECT_BOT_LO_BASE_IDX                                                       1
735 #define mmCC_UVD_VCPU_ERR_DETECT_BOT_HI                                                                0x0032
736 #define mmCC_UVD_VCPU_ERR_DETECT_BOT_HI_BASE_IDX                                                       1
737 #define mmCC_UVD_VCPU_ERR_DETECT_TOP_LO                                                                0x0033
738 #define mmCC_UVD_VCPU_ERR_DETECT_TOP_LO_BASE_IDX                                                       1
739 #define mmCC_UVD_VCPU_ERR_DETECT_TOP_HI                                                                0x0034
740 #define mmCC_UVD_VCPU_ERR_DETECT_TOP_HI_BASE_IDX                                                       1
741 #define mmCC_UVD_VCPU_ERR                                                                              0x0035
742 #define mmCC_UVD_VCPU_ERR_BASE_IDX                                                                     1
743 #define mmCC_UVD_VCPU_ERR_INST_ADDR_LO                                                                 0x0036
744 #define mmCC_UVD_VCPU_ERR_INST_ADDR_LO_BASE_IDX                                                        1
745 #define mmCC_UVD_VCPU_ERR_INST_ADDR_HI                                                                 0x0037
746 #define mmCC_UVD_VCPU_ERR_INST_ADDR_HI_BASE_IDX                                                        1
747 #define mmUVD_PF_STATUS                                                                                0x0039
748 #define mmUVD_PF_STATUS_BASE_IDX                                                                       1
749 #define mmUVD_FW_VERSION                                                                               0x003a
750 #define mmUVD_FW_VERSION_BASE_IDX                                                                      1
751 #define mmUVD_DPG_CLK_EN_VCPU_REPORT                                                                   0x003c
752 #define mmUVD_DPG_CLK_EN_VCPU_REPORT_BASE_IDX                                                          1
753 #define mmUVD_SECURITY_REG_VIO_REPORT                                                                  0x003f
754 #define mmUVD_SECURITY_REG_VIO_REPORT_BASE_IDX                                                         1
755 #define mmUVD_LMI_MMSCH_NC_SPACE                                                                       0x0045
756 #define mmUVD_LMI_MMSCH_NC_SPACE_BASE_IDX                                                              1
757 #define mmUVD_LMI_ATOMIC_SPACE                                                                         0x0046
758 #define mmUVD_LMI_ATOMIC_SPACE_BASE_IDX                                                                1
759 #define mmUVD_GFX10_ADDR_CONFIG                                                                        0x004a
760 #define mmUVD_GFX10_ADDR_CONFIG_BASE_IDX                                                               1
761 #define mmUVD_GPCNT2_CNTL                                                                              0x004b
762 #define mmUVD_GPCNT2_CNTL_BASE_IDX                                                                     1
763 #define mmUVD_GPCNT2_TARGET_LOWER                                                                      0x004c
764 #define mmUVD_GPCNT2_TARGET_LOWER_BASE_IDX                                                             1
765 #define mmUVD_GPCNT2_STATUS_LOWER                                                                      0x004d
766 #define mmUVD_GPCNT2_STATUS_LOWER_BASE_IDX                                                             1
767 #define mmUVD_GPCNT2_TARGET_UPPER                                                                      0x004e
768 #define mmUVD_GPCNT2_TARGET_UPPER_BASE_IDX                                                             1
769 #define mmUVD_GPCNT2_STATUS_UPPER                                                                      0x004f
770 #define mmUVD_GPCNT2_STATUS_UPPER_BASE_IDX                                                             1
771 #define mmUVD_GPCNT3_CNTL                                                                              0x0050
772 #define mmUVD_GPCNT3_CNTL_BASE_IDX                                                                     1
773 #define mmUVD_GPCNT3_TARGET_LOWER                                                                      0x0051
774 #define mmUVD_GPCNT3_TARGET_LOWER_BASE_IDX                                                             1
775 #define mmUVD_GPCNT3_STATUS_LOWER                                                                      0x0052
776 #define mmUVD_GPCNT3_STATUS_LOWER_BASE_IDX                                                             1
777 #define mmUVD_GPCNT3_TARGET_UPPER                                                                      0x0053
778 #define mmUVD_GPCNT3_TARGET_UPPER_BASE_IDX                                                             1
779 #define mmUVD_GPCNT3_STATUS_UPPER                                                                      0x0054
780 #define mmUVD_GPCNT3_STATUS_UPPER_BASE_IDX                                                             1
781 #define mmUVD_VCLK_DS_CNTL                                                                             0x0055
782 #define mmUVD_VCLK_DS_CNTL_BASE_IDX                                                                    1
783 #define mmUVD_DCLK_DS_CNTL                                                                             0x0056
784 #define mmUVD_DCLK_DS_CNTL_BASE_IDX                                                                    1
785 #define mmUVD_TSC_LOWER                                                                                0x0057
786 #define mmUVD_TSC_LOWER_BASE_IDX                                                                       1
787 #define mmUVD_TSC_UPPER                                                                                0x0058
788 #define mmUVD_TSC_UPPER_BASE_IDX                                                                       1
789 #define mmVCN_FEATURES                                                                                 0x0059
790 #define mmVCN_FEATURES_BASE_IDX                                                                        1
791 #define mmUVD_GPUIOV_STATUS                                                                            0x005d
792 #define mmUVD_GPUIOV_STATUS_BASE_IDX                                                                   1
793 
794 
795 // addressBlock: uvd0_uvddec
796 // base address: 0x1fa00
797 #define mmUVD_STATUS                                                                                   0x0080
798 #define mmUVD_STATUS_BASE_IDX                                                                          1
799 #define mmUVD_ENC_PIPE_BUSY                                                                            0x0081
800 #define mmUVD_ENC_PIPE_BUSY_BASE_IDX                                                                   1
801 #define mmUVD_FW_POWER_STATUS                                                                          0x0082
802 #define mmUVD_FW_POWER_STATUS_BASE_IDX                                                                 1
803 #define mmUVD_CNTL                                                                                     0x0083
804 #define mmUVD_CNTL_BASE_IDX                                                                            1
805 #define mmUVD_SOFT_RESET                                                                               0x0084
806 #define mmUVD_SOFT_RESET_BASE_IDX                                                                      1
807 #define mmUVD_SOFT_RESET2                                                                              0x0085
808 #define mmUVD_SOFT_RESET2_BASE_IDX                                                                     1
809 #define mmUVD_MMSCH_SOFT_RESET                                                                         0x0086
810 #define mmUVD_MMSCH_SOFT_RESET_BASE_IDX                                                                1
811 #define mmUVD_WIG_CTRL                                                                                 0x0087
812 #define mmUVD_WIG_CTRL_BASE_IDX                                                                        1
813 #define mmUVD_CGC_GATE                                                                                 0x0088
814 #define mmUVD_CGC_GATE_BASE_IDX                                                                        1
815 #define mmUVD_CGC_STATUS                                                                               0x0089
816 #define mmUVD_CGC_STATUS_BASE_IDX                                                                      1
817 #define mmUVD_CGC_CTRL                                                                                 0x008a
818 #define mmUVD_CGC_CTRL_BASE_IDX                                                                        1
819 #define mmUVD_CGC_UDEC_STATUS                                                                          0x008b
820 #define mmUVD_CGC_UDEC_STATUS_BASE_IDX                                                                 1
821 #define mmUVD_SUVD_CGC_GATE                                                                            0x008c
822 #define mmUVD_SUVD_CGC_GATE_BASE_IDX                                                                   1
823 #define mmUVD_SUVD_CGC_STATUS                                                                          0x008d
824 #define mmUVD_SUVD_CGC_STATUS_BASE_IDX                                                                 1
825 #define mmUVD_SUVD_CGC_CTRL                                                                            0x008e
826 #define mmUVD_SUVD_CGC_CTRL_BASE_IDX                                                                   1
827 #define mmUVD_GPCOM_VCPU_CMD                                                                           0x008f
828 #define mmUVD_GPCOM_VCPU_CMD_BASE_IDX                                                                  1
829 #define mmUVD_GPCOM_VCPU_DATA0                                                                         0x0090
830 #define mmUVD_GPCOM_VCPU_DATA0_BASE_IDX                                                                1
831 #define mmUVD_GPCOM_VCPU_DATA1                                                                         0x0091
832 #define mmUVD_GPCOM_VCPU_DATA1_BASE_IDX                                                                1
833 #define mmUVD_GPCOM_SYS_CMD                                                                            0x0092
834 #define mmUVD_GPCOM_SYS_CMD_BASE_IDX                                                                   1
835 #define mmUVD_GPCOM_SYS_DATA0                                                                          0x0093
836 #define mmUVD_GPCOM_SYS_DATA0_BASE_IDX                                                                 1
837 #define mmUVD_GPCOM_SYS_DATA1                                                                          0x0094
838 #define mmUVD_GPCOM_SYS_DATA1_BASE_IDX                                                                 1
839 #define mmUVD_VCPU_INT_EN                                                                              0x0095
840 #define mmUVD_VCPU_INT_EN_BASE_IDX                                                                     1
841 #define mmUVD_VCPU_INT_STATUS                                                                          0x0096
842 #define mmUVD_VCPU_INT_STATUS_BASE_IDX                                                                 1
843 #define mmUVD_VCPU_INT_ACK                                                                             0x0097
844 #define mmUVD_VCPU_INT_ACK_BASE_IDX                                                                    1
845 #define mmUVD_VCPU_INT_ROUTE                                                                           0x0098
846 #define mmUVD_VCPU_INT_ROUTE_BASE_IDX                                                                  1
847 #define mmUVD_DRV_FW_MSG                                                                               0x0099
848 #define mmUVD_DRV_FW_MSG_BASE_IDX                                                                      1
849 #define mmUVD_FW_DRV_MSG_ACK                                                                           0x009a
850 #define mmUVD_FW_DRV_MSG_ACK_BASE_IDX                                                                  1
851 #define mmUVD_SUVD_INT_EN                                                                              0x009b
852 #define mmUVD_SUVD_INT_EN_BASE_IDX                                                                     1
853 #define mmUVD_SUVD_INT_STATUS                                                                          0x009c
854 #define mmUVD_SUVD_INT_STATUS_BASE_IDX                                                                 1
855 #define mmUVD_SUVD_INT_ACK                                                                             0x009d
856 #define mmUVD_SUVD_INT_ACK_BASE_IDX                                                                    1
857 #define mmUVD_ENC_VCPU_INT_EN                                                                          0x009e
858 #define mmUVD_ENC_VCPU_INT_EN_BASE_IDX                                                                 1
859 #define mmUVD_ENC_VCPU_INT_STATUS                                                                      0x009f
860 #define mmUVD_ENC_VCPU_INT_STATUS_BASE_IDX                                                             1
861 #define mmUVD_ENC_VCPU_INT_ACK                                                                         0x00a0
862 #define mmUVD_ENC_VCPU_INT_ACK_BASE_IDX                                                                1
863 #define mmUVD_MASTINT_EN                                                                               0x00a1
864 #define mmUVD_MASTINT_EN_BASE_IDX                                                                      1
865 #define mmUVD_SYS_INT_EN                                                                               0x00a2
866 #define mmUVD_SYS_INT_EN_BASE_IDX                                                                      1
867 #define mmUVD_SYS_INT_STATUS                                                                           0x00a3
868 #define mmUVD_SYS_INT_STATUS_BASE_IDX                                                                  1
869 #define mmUVD_SYS_INT_ACK                                                                              0x00a4
870 #define mmUVD_SYS_INT_ACK_BASE_IDX                                                                     1
871 #define mmUVD_JOB_DONE                                                                                 0x00a5
872 #define mmUVD_JOB_DONE_BASE_IDX                                                                        1
873 #define mmUVD_CBUF_ID                                                                                  0x00a6
874 #define mmUVD_CBUF_ID_BASE_IDX                                                                         1
875 #define mmUVD_CONTEXT_ID                                                                               0x00a7
876 #define mmUVD_CONTEXT_ID_BASE_IDX                                                                      1
877 #define mmUVD_CONTEXT_ID2                                                                              0x00a8
878 #define mmUVD_CONTEXT_ID2_BASE_IDX                                                                     1
879 #define mmUVD_NO_OP                                                                                    0x00a9
880 #define mmUVD_NO_OP_BASE_IDX                                                                           1
881 #define mmUVD_RB_BASE_LO                                                                               0x00aa
882 #define mmUVD_RB_BASE_LO_BASE_IDX                                                                      1
883 #define mmUVD_RB_BASE_HI                                                                               0x00ab
884 #define mmUVD_RB_BASE_HI_BASE_IDX                                                                      1
885 #define mmUVD_RB_SIZE                                                                                  0x00ac
886 #define mmUVD_RB_SIZE_BASE_IDX                                                                         1
887 #define mmUVD_RB_RPTR                                                                                  0x00ad
888 #define mmUVD_RB_RPTR_BASE_IDX                                                                         1
889 #define mmUVD_RB_WPTR                                                                                  0x00ae
890 #define mmUVD_RB_WPTR_BASE_IDX                                                                         1
891 #define mmUVD_RB_BASE_LO2                                                                              0x00af
892 #define mmUVD_RB_BASE_LO2_BASE_IDX                                                                     1
893 #define mmUVD_RB_BASE_HI2                                                                              0x00b0
894 #define mmUVD_RB_BASE_HI2_BASE_IDX                                                                     1
895 #define mmUVD_RB_SIZE2                                                                                 0x00b1
896 #define mmUVD_RB_SIZE2_BASE_IDX                                                                        1
897 #define mmUVD_RB_RPTR2                                                                                 0x00b2
898 #define mmUVD_RB_RPTR2_BASE_IDX                                                                        1
899 #define mmUVD_RB_WPTR2                                                                                 0x00b3
900 #define mmUVD_RB_WPTR2_BASE_IDX                                                                        1
901 #define mmUVD_RB_BASE_LO3                                                                              0x00b4
902 #define mmUVD_RB_BASE_LO3_BASE_IDX                                                                     1
903 #define mmUVD_RB_BASE_HI3                                                                              0x00b5
904 #define mmUVD_RB_BASE_HI3_BASE_IDX                                                                     1
905 #define mmUVD_RB_SIZE3                                                                                 0x00b6
906 #define mmUVD_RB_SIZE3_BASE_IDX                                                                        1
907 #define mmUVD_RB_RPTR3                                                                                 0x00b7
908 #define mmUVD_RB_RPTR3_BASE_IDX                                                                        1
909 #define mmUVD_RB_WPTR3                                                                                 0x00b8
910 #define mmUVD_RB_WPTR3_BASE_IDX                                                                        1
911 #define mmUVD_RB_BASE_LO4                                                                              0x00b9
912 #define mmUVD_RB_BASE_LO4_BASE_IDX                                                                     1
913 #define mmUVD_RB_BASE_HI4                                                                              0x00ba
914 #define mmUVD_RB_BASE_HI4_BASE_IDX                                                                     1
915 #define mmUVD_RB_SIZE4                                                                                 0x00bb
916 #define mmUVD_RB_SIZE4_BASE_IDX                                                                        1
917 #define mmUVD_RB_RPTR4                                                                                 0x00bc
918 #define mmUVD_RB_RPTR4_BASE_IDX                                                                        1
919 #define mmUVD_RB_WPTR4                                                                                 0x00bd
920 #define mmUVD_RB_WPTR4_BASE_IDX                                                                        1
921 #define mmUVD_OUT_RB_BASE_LO                                                                           0x00be
922 #define mmUVD_OUT_RB_BASE_LO_BASE_IDX                                                                  1
923 #define mmUVD_OUT_RB_BASE_HI                                                                           0x00bf
924 #define mmUVD_OUT_RB_BASE_HI_BASE_IDX                                                                  1
925 #define mmUVD_OUT_RB_SIZE                                                                              0x00c0
926 #define mmUVD_OUT_RB_SIZE_BASE_IDX                                                                     1
927 #define mmUVD_OUT_RB_RPTR                                                                              0x00c1
928 #define mmUVD_OUT_RB_RPTR_BASE_IDX                                                                     1
929 #define mmUVD_OUT_RB_WPTR                                                                              0x00c2
930 #define mmUVD_OUT_RB_WPTR_BASE_IDX                                                                     1
931 #define mmUVD_IOV_ACTIVE_FCN_ID                                                                        0x00c3
932 #define mmUVD_IOV_ACTIVE_FCN_ID_BASE_IDX                                                               1
933 #define mmUVD_IOV_MAILBOX                                                                              0x00c4
934 #define mmUVD_IOV_MAILBOX_BASE_IDX                                                                     1
935 #define mmUVD_IOV_MAILBOX_RESP                                                                         0x00c5
936 #define mmUVD_IOV_MAILBOX_RESP_BASE_IDX                                                                1
937 #define mmUVD_RB_ARB_CTRL                                                                              0x00c6
938 #define mmUVD_RB_ARB_CTRL_BASE_IDX                                                                     1
939 #define mmUVD_CTX_INDEX                                                                                0x00c7
940 #define mmUVD_CTX_INDEX_BASE_IDX                                                                       1
941 #define mmUVD_CTX_DATA                                                                                 0x00c8
942 #define mmUVD_CTX_DATA_BASE_IDX                                                                        1
943 #define mmUVD_CXW_WR                                                                                   0x00c9
944 #define mmUVD_CXW_WR_BASE_IDX                                                                          1
945 #define mmUVD_CXW_WR_INT_ID                                                                            0x00ca
946 #define mmUVD_CXW_WR_INT_ID_BASE_IDX                                                                   1
947 #define mmUVD_CXW_WR_INT_CTX_ID                                                                        0x00cb
948 #define mmUVD_CXW_WR_INT_CTX_ID_BASE_IDX                                                               1
949 #define mmUVD_CXW_INT_ID                                                                               0x00cc
950 #define mmUVD_CXW_INT_ID_BASE_IDX                                                                      1
951 #define mmUVD_MPEG2_ERROR                                                                              0x00cd
952 #define mmUVD_MPEG2_ERROR_BASE_IDX                                                                     1
953 #define mmUVD_TOP_CTRL                                                                                 0x00cf
954 #define mmUVD_TOP_CTRL_BASE_IDX                                                                        1
955 #define mmUVD_YBASE                                                                                    0x00d0
956 #define mmUVD_YBASE_BASE_IDX                                                                           1
957 #define mmUVD_UVBASE                                                                                   0x00d1
958 #define mmUVD_UVBASE_BASE_IDX                                                                          1
959 #define mmUVD_PITCH                                                                                    0x00d2
960 #define mmUVD_PITCH_BASE_IDX                                                                           1
961 #define mmUVD_WIDTH                                                                                    0x00d3
962 #define mmUVD_WIDTH_BASE_IDX                                                                           1
963 #define mmUVD_HEIGHT                                                                                   0x00d4
964 #define mmUVD_HEIGHT_BASE_IDX                                                                          1
965 #define mmUVD_PICCOUNT                                                                                 0x00d5
966 #define mmUVD_PICCOUNT_BASE_IDX                                                                        1
967 #define mmUVD_MPRD_INITIAL_XY                                                                          0x00d6
968 #define mmUVD_MPRD_INITIAL_XY_BASE_IDX                                                                 1
969 #define mmUVD_MPEG2_CTRL                                                                               0x00d7
970 #define mmUVD_MPEG2_CTRL_BASE_IDX                                                                      1
971 #define mmUVD_MB_CTL_BUF_BASE                                                                          0x00d8
972 #define mmUVD_MB_CTL_BUF_BASE_BASE_IDX                                                                 1
973 #define mmUVD_PIC_CTL_BUF_BASE                                                                         0x00d9
974 #define mmUVD_PIC_CTL_BUF_BASE_BASE_IDX                                                                1
975 #define mmUVD_DXVA_BUF_SIZE                                                                            0x00da
976 #define mmUVD_DXVA_BUF_SIZE_BASE_IDX                                                                   1
977 #define mmUVD_SCRATCH_NP                                                                               0x00db
978 #define mmUVD_SCRATCH_NP_BASE_IDX                                                                      1
979 #define mmUVD_CLK_SWT_HANDSHAKE                                                                        0x00dc
980 #define mmUVD_CLK_SWT_HANDSHAKE_BASE_IDX                                                               1
981 #define mmUVD_VERSION                                                                                  0x00dd
982 #define mmUVD_VERSION_BASE_IDX                                                                         1
983 #define mmUVD_GP_SCRATCH0                                                                              0x00de
984 #define mmUVD_GP_SCRATCH0_BASE_IDX                                                                     1
985 #define mmUVD_GP_SCRATCH1                                                                              0x00df
986 #define mmUVD_GP_SCRATCH1_BASE_IDX                                                                     1
987 #define mmUVD_GP_SCRATCH2                                                                              0x00e0
988 #define mmUVD_GP_SCRATCH2_BASE_IDX                                                                     1
989 #define mmUVD_GP_SCRATCH3                                                                              0x00e1
990 #define mmUVD_GP_SCRATCH3_BASE_IDX                                                                     1
991 #define mmUVD_GP_SCRATCH4                                                                              0x00e2
992 #define mmUVD_GP_SCRATCH4_BASE_IDX                                                                     1
993 #define mmUVD_GP_SCRATCH5                                                                              0x00e3
994 #define mmUVD_GP_SCRATCH5_BASE_IDX                                                                     1
995 #define mmUVD_GP_SCRATCH6                                                                              0x00e4
996 #define mmUVD_GP_SCRATCH6_BASE_IDX                                                                     1
997 #define mmUVD_GP_SCRATCH7                                                                              0x00e5
998 #define mmUVD_GP_SCRATCH7_BASE_IDX                                                                     1
999 #define mmUVD_GP_SCRATCH8                                                                              0x00e6
1000 #define mmUVD_GP_SCRATCH8_BASE_IDX                                                                     1
1001 #define mmUVD_GP_SCRATCH9                                                                              0x00e7
1002 #define mmUVD_GP_SCRATCH9_BASE_IDX                                                                     1
1003 #define mmUVD_GP_SCRATCH10                                                                             0x00e8
1004 #define mmUVD_GP_SCRATCH10_BASE_IDX                                                                    1
1005 #define mmUVD_GP_SCRATCH11                                                                             0x00e9
1006 #define mmUVD_GP_SCRATCH11_BASE_IDX                                                                    1
1007 #define mmUVD_GP_SCRATCH12                                                                             0x00ea
1008 #define mmUVD_GP_SCRATCH12_BASE_IDX                                                                    1
1009 #define mmUVD_GP_SCRATCH13                                                                             0x00eb
1010 #define mmUVD_GP_SCRATCH13_BASE_IDX                                                                    1
1011 #define mmUVD_GP_SCRATCH14                                                                             0x00ec
1012 #define mmUVD_GP_SCRATCH14_BASE_IDX                                                                    1
1013 #define mmUVD_GP_SCRATCH15                                                                             0x00ed
1014 #define mmUVD_GP_SCRATCH15_BASE_IDX                                                                    1
1015 #define mmUVD_GP_SCRATCH16                                                                             0x00ee
1016 #define mmUVD_GP_SCRATCH16_BASE_IDX                                                                    1
1017 #define mmUVD_GP_SCRATCH17                                                                             0x00ef
1018 #define mmUVD_GP_SCRATCH17_BASE_IDX                                                                    1
1019 #define mmUVD_GP_SCRATCH18                                                                             0x00f0
1020 #define mmUVD_GP_SCRATCH18_BASE_IDX                                                                    1
1021 #define mmUVD_GP_SCRATCH19                                                                             0x00f1
1022 #define mmUVD_GP_SCRATCH19_BASE_IDX                                                                    1
1023 #define mmUVD_GP_SCRATCH20                                                                             0x00f2
1024 #define mmUVD_GP_SCRATCH20_BASE_IDX                                                                    1
1025 #define mmUVD_GP_SCRATCH21                                                                             0x00f3
1026 #define mmUVD_GP_SCRATCH21_BASE_IDX                                                                    1
1027 #define mmUVD_GP_SCRATCH22                                                                             0x00f4
1028 #define mmUVD_GP_SCRATCH22_BASE_IDX                                                                    1
1029 #define mmUVD_GP_SCRATCH23                                                                             0x00f5
1030 #define mmUVD_GP_SCRATCH23_BASE_IDX                                                                    1
1031 #define mmUVD_AUDIO_RB_BASE_LO                                                                         0x00f6
1032 #define mmUVD_AUDIO_RB_BASE_LO_BASE_IDX                                                                1
1033 #define mmUVD_AUDIO_RB_BASE_HI                                                                         0x00f7
1034 #define mmUVD_AUDIO_RB_BASE_HI_BASE_IDX                                                                1
1035 #define mmUVD_AUDIO_RB_SIZE                                                                            0x00f8
1036 #define mmUVD_AUDIO_RB_SIZE_BASE_IDX                                                                   1
1037 #define mmUVD_AUDIO_RB_RPTR                                                                            0x00f9
1038 #define mmUVD_AUDIO_RB_RPTR_BASE_IDX                                                                   1
1039 #define mmUVD_AUDIO_RB_WPTR                                                                            0x00fa
1040 #define mmUVD_AUDIO_RB_WPTR_BASE_IDX                                                                   1
1041 #define mmUVD_VCPU_INT_STATUS2                                                                         0x00fb
1042 #define mmUVD_VCPU_INT_STATUS2_BASE_IDX                                                                1
1043 #define mmUVD_VCPU_INT_ACK2                                                                            0x00fc
1044 #define mmUVD_VCPU_INT_ACK2_BASE_IDX                                                                   1
1045 #define mmUVD_VCPU_INT_EN2                                                                             0x00fd
1046 #define mmUVD_VCPU_INT_EN2_BASE_IDX                                                                    1
1047 #define mmUVD_SUVD_CGC_STATUS2                                                                         0x00fe
1048 #define mmUVD_SUVD_CGC_STATUS2_BASE_IDX                                                                1
1049 #define mmUVD_SUVD_CGC_GATE2                                                                           0x00ff
1050 #define mmUVD_SUVD_CGC_GATE2_BASE_IDX                                                                  1
1051 #define mmUVD_SUVD_INT_STATUS2                                                                         0x0100
1052 #define mmUVD_SUVD_INT_STATUS2_BASE_IDX                                                                1
1053 #define mmUVD_SUVD_INT_EN2                                                                             0x0101
1054 #define mmUVD_SUVD_INT_EN2_BASE_IDX                                                                    1
1055 #define mmUVD_SUVD_INT_ACK2                                                                            0x0102
1056 #define mmUVD_SUVD_INT_ACK2_BASE_IDX                                                                   1
1057 
1058 
1059 // addressBlock: uvd0_ecpudec
1060 // base address: 0x1fd00
1061 #define mmUVD_VCPU_CACHE_OFFSET0                                                                       0x0140
1062 #define mmUVD_VCPU_CACHE_OFFSET0_BASE_IDX                                                              1
1063 #define mmUVD_VCPU_CACHE_SIZE0                                                                         0x0141
1064 #define mmUVD_VCPU_CACHE_SIZE0_BASE_IDX                                                                1
1065 #define mmUVD_VCPU_CACHE_OFFSET1                                                                       0x0142
1066 #define mmUVD_VCPU_CACHE_OFFSET1_BASE_IDX                                                              1
1067 #define mmUVD_VCPU_CACHE_SIZE1                                                                         0x0143
1068 #define mmUVD_VCPU_CACHE_SIZE1_BASE_IDX                                                                1
1069 #define mmUVD_VCPU_CACHE_OFFSET2                                                                       0x0144
1070 #define mmUVD_VCPU_CACHE_OFFSET2_BASE_IDX                                                              1
1071 #define mmUVD_VCPU_CACHE_SIZE2                                                                         0x0145
1072 #define mmUVD_VCPU_CACHE_SIZE2_BASE_IDX                                                                1
1073 #define mmUVD_VCPU_CACHE_OFFSET3                                                                       0x0146
1074 #define mmUVD_VCPU_CACHE_OFFSET3_BASE_IDX                                                              1
1075 #define mmUVD_VCPU_CACHE_SIZE3                                                                         0x0147
1076 #define mmUVD_VCPU_CACHE_SIZE3_BASE_IDX                                                                1
1077 #define mmUVD_VCPU_CACHE_OFFSET4                                                                       0x0148
1078 #define mmUVD_VCPU_CACHE_OFFSET4_BASE_IDX                                                              1
1079 #define mmUVD_VCPU_CACHE_SIZE4                                                                         0x0149
1080 #define mmUVD_VCPU_CACHE_SIZE4_BASE_IDX                                                                1
1081 #define mmUVD_VCPU_CACHE_OFFSET5                                                                       0x014a
1082 #define mmUVD_VCPU_CACHE_OFFSET5_BASE_IDX                                                              1
1083 #define mmUVD_VCPU_CACHE_SIZE5                                                                         0x014b
1084 #define mmUVD_VCPU_CACHE_SIZE5_BASE_IDX                                                                1
1085 #define mmUVD_VCPU_CACHE_OFFSET6                                                                       0x014c
1086 #define mmUVD_VCPU_CACHE_OFFSET6_BASE_IDX                                                              1
1087 #define mmUVD_VCPU_CACHE_SIZE6                                                                         0x014d
1088 #define mmUVD_VCPU_CACHE_SIZE6_BASE_IDX                                                                1
1089 #define mmUVD_VCPU_CACHE_OFFSET7                                                                       0x014e
1090 #define mmUVD_VCPU_CACHE_OFFSET7_BASE_IDX                                                              1
1091 #define mmUVD_VCPU_CACHE_SIZE7                                                                         0x014f
1092 #define mmUVD_VCPU_CACHE_SIZE7_BASE_IDX                                                                1
1093 #define mmUVD_VCPU_CACHE_OFFSET8                                                                       0x0150
1094 #define mmUVD_VCPU_CACHE_OFFSET8_BASE_IDX                                                              1
1095 #define mmUVD_VCPU_CACHE_SIZE8                                                                         0x0151
1096 #define mmUVD_VCPU_CACHE_SIZE8_BASE_IDX                                                                1
1097 #define mmUVD_VCPU_NONCACHE_OFFSET0                                                                    0x0152
1098 #define mmUVD_VCPU_NONCACHE_OFFSET0_BASE_IDX                                                           1
1099 #define mmUVD_VCPU_NONCACHE_SIZE0                                                                      0x0153
1100 #define mmUVD_VCPU_NONCACHE_SIZE0_BASE_IDX                                                             1
1101 #define mmUVD_VCPU_NONCACHE_OFFSET1                                                                    0x0154
1102 #define mmUVD_VCPU_NONCACHE_OFFSET1_BASE_IDX                                                           1
1103 #define mmUVD_VCPU_NONCACHE_SIZE1                                                                      0x0155
1104 #define mmUVD_VCPU_NONCACHE_SIZE1_BASE_IDX                                                             1
1105 #define mmUVD_VCPU_CNTL                                                                                0x0156
1106 #define mmUVD_VCPU_CNTL_BASE_IDX                                                                       1
1107 #define mmUVD_VCPU_PRID                                                                                0x0157
1108 #define mmUVD_VCPU_PRID_BASE_IDX                                                                       1
1109 #define mmUVD_VCPU_TRCE                                                                                0x0158
1110 #define mmUVD_VCPU_TRCE_BASE_IDX                                                                       1
1111 #define mmUVD_VCPU_TRCE_RD                                                                             0x0159
1112 #define mmUVD_VCPU_TRCE_RD_BASE_IDX                                                                    1
1113 #define mmUVD_VCPU_IND_INDEX                                                                           0x015b
1114 #define mmUVD_VCPU_IND_INDEX_BASE_IDX                                                                  1
1115 #define mmUVD_VCPU_IND_DATA                                                                            0x015c
1116 #define mmUVD_VCPU_IND_DATA_BASE_IDX                                                                   1
1117 
1118 
1119 // addressBlock: uvd0_uvd_mpcdec
1120 // base address: 0x20310
1121 #define mmUVD_MP_SWAP_CNTL                                                                             0x02c4
1122 #define mmUVD_MP_SWAP_CNTL_BASE_IDX                                                                    1
1123 #define mmUVD_MP_SWAP_CNTL2                                                                            0x02c5
1124 #define mmUVD_MP_SWAP_CNTL2_BASE_IDX                                                                   1
1125 #define mmUVD_MPC_LUMA_SRCH                                                                            0x02c6
1126 #define mmUVD_MPC_LUMA_SRCH_BASE_IDX                                                                   1
1127 #define mmUVD_MPC_LUMA_HIT                                                                             0x02c7
1128 #define mmUVD_MPC_LUMA_HIT_BASE_IDX                                                                    1
1129 #define mmUVD_MPC_LUMA_HITPEND                                                                         0x02c8
1130 #define mmUVD_MPC_LUMA_HITPEND_BASE_IDX                                                                1
1131 #define mmUVD_MPC_CHROMA_SRCH                                                                          0x02c9
1132 #define mmUVD_MPC_CHROMA_SRCH_BASE_IDX                                                                 1
1133 #define mmUVD_MPC_CHROMA_HIT                                                                           0x02ca
1134 #define mmUVD_MPC_CHROMA_HIT_BASE_IDX                                                                  1
1135 #define mmUVD_MPC_CHROMA_HITPEND                                                                       0x02cb
1136 #define mmUVD_MPC_CHROMA_HITPEND_BASE_IDX                                                              1
1137 #define mmUVD_MPC_CNTL                                                                                 0x02cc
1138 #define mmUVD_MPC_CNTL_BASE_IDX                                                                        1
1139 #define mmUVD_MPC_PITCH                                                                                0x02cd
1140 #define mmUVD_MPC_PITCH_BASE_IDX                                                                       1
1141 #define mmUVD_MPC_SET_MUXA0                                                                            0x02ce
1142 #define mmUVD_MPC_SET_MUXA0_BASE_IDX                                                                   1
1143 #define mmUVD_MPC_SET_MUXA1                                                                            0x02cf
1144 #define mmUVD_MPC_SET_MUXA1_BASE_IDX                                                                   1
1145 #define mmUVD_MPC_SET_MUXB0                                                                            0x02d0
1146 #define mmUVD_MPC_SET_MUXB0_BASE_IDX                                                                   1
1147 #define mmUVD_MPC_SET_MUXB1                                                                            0x02d1
1148 #define mmUVD_MPC_SET_MUXB1_BASE_IDX                                                                   1
1149 #define mmUVD_MPC_SET_MUX                                                                              0x02d2
1150 #define mmUVD_MPC_SET_MUX_BASE_IDX                                                                     1
1151 #define mmUVD_MPC_SET_ALU                                                                              0x02d3
1152 #define mmUVD_MPC_SET_ALU_BASE_IDX                                                                     1
1153 #define mmUVD_MPC_PERF0                                                                                0x02d4
1154 #define mmUVD_MPC_PERF0_BASE_IDX                                                                       1
1155 #define mmUVD_MPC_PERF1                                                                                0x02d5
1156 #define mmUVD_MPC_PERF1_BASE_IDX                                                                       1
1157 #define mmUVD_MPC_IND_INDEX                                                                            0x02d6
1158 #define mmUVD_MPC_IND_INDEX_BASE_IDX                                                                   1
1159 #define mmUVD_MPC_IND_DATA                                                                             0x02d7
1160 #define mmUVD_MPC_IND_DATA_BASE_IDX                                                                    1
1161 
1162 
1163 // addressBlock: uvd0_uvd_rbcdec
1164 // base address: 0x20370
1165 #define mmUVD_RBC_IB_SIZE                                                                              0x02dc
1166 #define mmUVD_RBC_IB_SIZE_BASE_IDX                                                                     1
1167 #define mmUVD_RBC_IB_SIZE_UPDATE                                                                       0x02dd
1168 #define mmUVD_RBC_IB_SIZE_UPDATE_BASE_IDX                                                              1
1169 #define mmUVD_RBC_RB_CNTL                                                                              0x02de
1170 #define mmUVD_RBC_RB_CNTL_BASE_IDX                                                                     1
1171 #define mmUVD_RBC_RB_RPTR_ADDR                                                                         0x02df
1172 #define mmUVD_RBC_RB_RPTR_ADDR_BASE_IDX                                                                1
1173 #define mmUVD_RBC_RB_RPTR                                                                              0x02e0
1174 #define mmUVD_RBC_RB_RPTR_BASE_IDX                                                                     1
1175 #define mmUVD_RBC_RB_WPTR                                                                              0x02e1
1176 #define mmUVD_RBC_RB_WPTR_BASE_IDX                                                                     1
1177 #define mmUVD_RBC_VCPU_ACCESS                                                                          0x02e2
1178 #define mmUVD_RBC_VCPU_ACCESS_BASE_IDX                                                                 1
1179 #define mmUVD_FW_SEMAPHORE_CNTL                                                                        0x02e3
1180 #define mmUVD_FW_SEMAPHORE_CNTL_BASE_IDX                                                               1
1181 #define mmUVD_RBC_READ_REQ_URGENT_CNTL                                                                 0x02e5
1182 #define mmUVD_RBC_READ_REQ_URGENT_CNTL_BASE_IDX                                                        1
1183 #define mmUVD_RBC_RB_WPTR_CNTL                                                                         0x02e6
1184 #define mmUVD_RBC_RB_WPTR_CNTL_BASE_IDX                                                                1
1185 #define mmUVD_RBC_WPTR_STATUS                                                                          0x02e7
1186 #define mmUVD_RBC_WPTR_STATUS_BASE_IDX                                                                 1
1187 #define mmUVD_RBC_WPTR_POLL_CNTL                                                                       0x02e8
1188 #define mmUVD_RBC_WPTR_POLL_CNTL_BASE_IDX                                                              1
1189 #define mmUVD_RBC_WPTR_POLL_ADDR                                                                       0x02e9
1190 #define mmUVD_RBC_WPTR_POLL_ADDR_BASE_IDX                                                              1
1191 #define mmUVD_SEMA_CMD                                                                                 0x02ea
1192 #define mmUVD_SEMA_CMD_BASE_IDX                                                                        1
1193 #define mmUVD_SEMA_ADDR_LOW                                                                            0x02eb
1194 #define mmUVD_SEMA_ADDR_LOW_BASE_IDX                                                                   1
1195 #define mmUVD_SEMA_ADDR_HIGH                                                                           0x02ec
1196 #define mmUVD_SEMA_ADDR_HIGH_BASE_IDX                                                                  1
1197 #define mmUVD_ENGINE_CNTL                                                                              0x02ed
1198 #define mmUVD_ENGINE_CNTL_BASE_IDX                                                                     1
1199 #define mmUVD_SEMA_TIMEOUT_STATUS                                                                      0x02ee
1200 #define mmUVD_SEMA_TIMEOUT_STATUS_BASE_IDX                                                             1
1201 #define mmUVD_SEMA_CNTL                                                                                0x02ef
1202 #define mmUVD_SEMA_CNTL_BASE_IDX                                                                       1
1203 #define mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL                                                      0x02f0
1204 #define mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL_BASE_IDX                                             1
1205 #define mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL                                                             0x02f1
1206 #define mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL_BASE_IDX                                                    1
1207 #define mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL                                                        0x02f2
1208 #define mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL_BASE_IDX                                               1
1209 #define mmUVD_JOB_START                                                                                0x02f3
1210 #define mmUVD_JOB_START_BASE_IDX                                                                       1
1211 #define mmUVD_RBC_BUF_STATUS                                                                           0x02f4
1212 #define mmUVD_RBC_BUF_STATUS_BASE_IDX                                                                  1
1213 #define mmUVD_RBC_SWAP_CNTL                                                                            0x02f5
1214 #define mmUVD_RBC_SWAP_CNTL_BASE_IDX                                                                   1
1215 
1216 
1217 // addressBlock: uvd0_lmi_adpdec
1218 // base address: 0x20870
1219 #define mmUVD_LMI_RE_64BIT_BAR_LOW                                                                     0x041c
1220 #define mmUVD_LMI_RE_64BIT_BAR_LOW_BASE_IDX                                                            1
1221 #define mmUVD_LMI_RE_64BIT_BAR_HIGH                                                                    0x041d
1222 #define mmUVD_LMI_RE_64BIT_BAR_HIGH_BASE_IDX                                                           1
1223 #define mmUVD_LMI_IT_64BIT_BAR_LOW                                                                     0x041e
1224 #define mmUVD_LMI_IT_64BIT_BAR_LOW_BASE_IDX                                                            1
1225 #define mmUVD_LMI_IT_64BIT_BAR_HIGH                                                                    0x041f
1226 #define mmUVD_LMI_IT_64BIT_BAR_HIGH_BASE_IDX                                                           1
1227 #define mmUVD_LMI_MP_64BIT_BAR_LOW                                                                     0x0420
1228 #define mmUVD_LMI_MP_64BIT_BAR_LOW_BASE_IDX                                                            1
1229 #define mmUVD_LMI_MP_64BIT_BAR_HIGH                                                                    0x0421
1230 #define mmUVD_LMI_MP_64BIT_BAR_HIGH_BASE_IDX                                                           1
1231 #define mmUVD_LMI_CM_64BIT_BAR_LOW                                                                     0x0422
1232 #define mmUVD_LMI_CM_64BIT_BAR_LOW_BASE_IDX                                                            1
1233 #define mmUVD_LMI_CM_64BIT_BAR_HIGH                                                                    0x0423
1234 #define mmUVD_LMI_CM_64BIT_BAR_HIGH_BASE_IDX                                                           1
1235 #define mmUVD_LMI_DB_64BIT_BAR_LOW                                                                     0x0424
1236 #define mmUVD_LMI_DB_64BIT_BAR_LOW_BASE_IDX                                                            1
1237 #define mmUVD_LMI_DB_64BIT_BAR_HIGH                                                                    0x0425
1238 #define mmUVD_LMI_DB_64BIT_BAR_HIGH_BASE_IDX                                                           1
1239 #define mmUVD_LMI_DBW_64BIT_BAR_LOW                                                                    0x0426
1240 #define mmUVD_LMI_DBW_64BIT_BAR_LOW_BASE_IDX                                                           1
1241 #define mmUVD_LMI_DBW_64BIT_BAR_HIGH                                                                   0x0427
1242 #define mmUVD_LMI_DBW_64BIT_BAR_HIGH_BASE_IDX                                                          1
1243 #define mmUVD_LMI_IDCT_64BIT_BAR_LOW                                                                   0x0428
1244 #define mmUVD_LMI_IDCT_64BIT_BAR_LOW_BASE_IDX                                                          1
1245 #define mmUVD_LMI_IDCT_64BIT_BAR_HIGH                                                                  0x0429
1246 #define mmUVD_LMI_IDCT_64BIT_BAR_HIGH_BASE_IDX                                                         1
1247 #define mmUVD_LMI_MPRD_S0_64BIT_BAR_LOW                                                                0x042a
1248 #define mmUVD_LMI_MPRD_S0_64BIT_BAR_LOW_BASE_IDX                                                       1
1249 #define mmUVD_LMI_MPRD_S0_64BIT_BAR_HIGH                                                               0x042b
1250 #define mmUVD_LMI_MPRD_S0_64BIT_BAR_HIGH_BASE_IDX                                                      1
1251 #define mmUVD_LMI_MPRD_S1_64BIT_BAR_LOW                                                                0x042c
1252 #define mmUVD_LMI_MPRD_S1_64BIT_BAR_LOW_BASE_IDX                                                       1
1253 #define mmUVD_LMI_MPRD_S1_64BIT_BAR_HIGH                                                               0x042d
1254 #define mmUVD_LMI_MPRD_S1_64BIT_BAR_HIGH_BASE_IDX                                                      1
1255 #define mmUVD_LMI_MPRD_DBW_64BIT_BAR_LOW                                                               0x042e
1256 #define mmUVD_LMI_MPRD_DBW_64BIT_BAR_LOW_BASE_IDX                                                      1
1257 #define mmUVD_LMI_MPRD_DBW_64BIT_BAR_HIGH                                                              0x042f
1258 #define mmUVD_LMI_MPRD_DBW_64BIT_BAR_HIGH_BASE_IDX                                                     1
1259 #define mmUVD_LMI_MPC_64BIT_BAR_LOW                                                                    0x0430
1260 #define mmUVD_LMI_MPC_64BIT_BAR_LOW_BASE_IDX                                                           1
1261 #define mmUVD_LMI_MPC_64BIT_BAR_HIGH                                                                   0x0431
1262 #define mmUVD_LMI_MPC_64BIT_BAR_HIGH_BASE_IDX                                                          1
1263 #define mmUVD_LMI_RBC_RB_64BIT_BAR_LOW                                                                 0x0432
1264 #define mmUVD_LMI_RBC_RB_64BIT_BAR_LOW_BASE_IDX                                                        1
1265 #define mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH                                                                0x0433
1266 #define mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH_BASE_IDX                                                       1
1267 #define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW                                                                 0x0434
1268 #define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_BASE_IDX                                                        1
1269 #define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH                                                                0x0435
1270 #define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_BASE_IDX                                                       1
1271 #define mmUVD_LMI_LBSI_64BIT_BAR_LOW                                                                   0x0436
1272 #define mmUVD_LMI_LBSI_64BIT_BAR_LOW_BASE_IDX                                                          1
1273 #define mmUVD_LMI_LBSI_64BIT_BAR_HIGH                                                                  0x0437
1274 #define mmUVD_LMI_LBSI_64BIT_BAR_HIGH_BASE_IDX                                                         1
1275 #define mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW                                                               0x0438
1276 #define mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW_BASE_IDX                                                      1
1277 #define mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH                                                              0x0439
1278 #define mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH_BASE_IDX                                                     1
1279 #define mmUVD_LMI_VCPU_NC1_64BIT_BAR_LOW                                                               0x043a
1280 #define mmUVD_LMI_VCPU_NC1_64BIT_BAR_LOW_BASE_IDX                                                      1
1281 #define mmUVD_LMI_VCPU_NC1_64BIT_BAR_HIGH                                                              0x043b
1282 #define mmUVD_LMI_VCPU_NC1_64BIT_BAR_HIGH_BASE_IDX                                                     1
1283 #define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW                                                             0x043c
1284 #define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW_BASE_IDX                                                    1
1285 #define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH                                                            0x043d
1286 #define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH_BASE_IDX                                                   1
1287 #define mmUVD_LMI_CENC_64BIT_BAR_LOW                                                                   0x043e
1288 #define mmUVD_LMI_CENC_64BIT_BAR_LOW_BASE_IDX                                                          1
1289 #define mmUVD_LMI_CENC_64BIT_BAR_HIGH                                                                  0x043f
1290 #define mmUVD_LMI_CENC_64BIT_BAR_HIGH_BASE_IDX                                                         1
1291 #define mmUVD_LMI_SRE_64BIT_BAR_LOW                                                                    0x0440
1292 #define mmUVD_LMI_SRE_64BIT_BAR_LOW_BASE_IDX                                                           1
1293 #define mmUVD_LMI_SRE_64BIT_BAR_HIGH                                                                   0x0441
1294 #define mmUVD_LMI_SRE_64BIT_BAR_HIGH_BASE_IDX                                                          1
1295 #define mmUVD_LMI_MIF_GPGPU_64BIT_BAR_LOW                                                              0x0442
1296 #define mmUVD_LMI_MIF_GPGPU_64BIT_BAR_LOW_BASE_IDX                                                     1
1297 #define mmUVD_LMI_MIF_GPGPU_64BIT_BAR_HIGH                                                             0x0443
1298 #define mmUVD_LMI_MIF_GPGPU_64BIT_BAR_HIGH_BASE_IDX                                                    1
1299 #define mmUVD_LMI_MIF_CURR_LUMA_64BIT_BAR_LOW                                                          0x0444
1300 #define mmUVD_LMI_MIF_CURR_LUMA_64BIT_BAR_LOW_BASE_IDX                                                 1
1301 #define mmUVD_LMI_MIF_CURR_LUMA_64BIT_BAR_HIGH                                                         0x0445
1302 #define mmUVD_LMI_MIF_CURR_LUMA_64BIT_BAR_HIGH_BASE_IDX                                                1
1303 #define mmUVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_LOW                                                        0x0446
1304 #define mmUVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_LOW_BASE_IDX                                               1
1305 #define mmUVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_HIGH                                                       0x0447
1306 #define mmUVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_HIGH_BASE_IDX                                              1
1307 #define mmUVD_LMI_MIF_REF_64BIT_BAR_LOW                                                                0x0448
1308 #define mmUVD_LMI_MIF_REF_64BIT_BAR_LOW_BASE_IDX                                                       1
1309 #define mmUVD_LMI_MIF_REF_64BIT_BAR_HIGH                                                               0x0449
1310 #define mmUVD_LMI_MIF_REF_64BIT_BAR_HIGH_BASE_IDX                                                      1
1311 #define mmUVD_LMI_MIF_DBW_64BIT_BAR_LOW                                                                0x044a
1312 #define mmUVD_LMI_MIF_DBW_64BIT_BAR_LOW_BASE_IDX                                                       1
1313 #define mmUVD_LMI_MIF_DBW_64BIT_BAR_HIGH                                                               0x044b
1314 #define mmUVD_LMI_MIF_DBW_64BIT_BAR_HIGH_BASE_IDX                                                      1
1315 #define mmUVD_LMI_MIF_CM_COLOC_64BIT_BAR_LOW                                                           0x044c
1316 #define mmUVD_LMI_MIF_CM_COLOC_64BIT_BAR_LOW_BASE_IDX                                                  1
1317 #define mmUVD_LMI_MIF_CM_COLOC_64BIT_BAR_HIGH                                                          0x044d
1318 #define mmUVD_LMI_MIF_CM_COLOC_64BIT_BAR_HIGH_BASE_IDX                                                 1
1319 #define mmUVD_LMI_MIF_BSP0_64BIT_BAR_LOW                                                               0x044e
1320 #define mmUVD_LMI_MIF_BSP0_64BIT_BAR_LOW_BASE_IDX                                                      1
1321 #define mmUVD_LMI_MIF_BSP0_64BIT_BAR_HIGH                                                              0x044f
1322 #define mmUVD_LMI_MIF_BSP0_64BIT_BAR_HIGH_BASE_IDX                                                     1
1323 #define mmUVD_LMI_MIF_BSP1_64BIT_BAR_LOW                                                               0x0450
1324 #define mmUVD_LMI_MIF_BSP1_64BIT_BAR_LOW_BASE_IDX                                                      1
1325 #define mmUVD_LMI_MIF_BSP1_64BIT_BAR_HIGH                                                              0x0451
1326 #define mmUVD_LMI_MIF_BSP1_64BIT_BAR_HIGH_BASE_IDX                                                     1
1327 #define mmUVD_LMI_MIF_BSP2_64BIT_BAR_LOW                                                               0x0452
1328 #define mmUVD_LMI_MIF_BSP2_64BIT_BAR_LOW_BASE_IDX                                                      1
1329 #define mmUVD_LMI_MIF_BSP2_64BIT_BAR_HIGH                                                              0x0453
1330 #define mmUVD_LMI_MIF_BSP2_64BIT_BAR_HIGH_BASE_IDX                                                     1
1331 #define mmUVD_LMI_MIF_BSP3_64BIT_BAR_LOW                                                               0x0454
1332 #define mmUVD_LMI_MIF_BSP3_64BIT_BAR_LOW_BASE_IDX                                                      1
1333 #define mmUVD_LMI_MIF_BSP3_64BIT_BAR_HIGH                                                              0x0455
1334 #define mmUVD_LMI_MIF_BSP3_64BIT_BAR_HIGH_BASE_IDX                                                     1
1335 #define mmUVD_LMI_MIF_BSD0_64BIT_BAR_LOW                                                               0x0456
1336 #define mmUVD_LMI_MIF_BSD0_64BIT_BAR_LOW_BASE_IDX                                                      1
1337 #define mmUVD_LMI_MIF_BSD0_64BIT_BAR_HIGH                                                              0x0457
1338 #define mmUVD_LMI_MIF_BSD0_64BIT_BAR_HIGH_BASE_IDX                                                     1
1339 #define mmUVD_LMI_MIF_BSD1_64BIT_BAR_LOW                                                               0x0458
1340 #define mmUVD_LMI_MIF_BSD1_64BIT_BAR_LOW_BASE_IDX                                                      1
1341 #define mmUVD_LMI_MIF_BSD1_64BIT_BAR_HIGH                                                              0x0459
1342 #define mmUVD_LMI_MIF_BSD1_64BIT_BAR_HIGH_BASE_IDX                                                     1
1343 #define mmUVD_LMI_MIF_BSD2_64BIT_BAR_LOW                                                               0x045a
1344 #define mmUVD_LMI_MIF_BSD2_64BIT_BAR_LOW_BASE_IDX                                                      1
1345 #define mmUVD_LMI_MIF_BSD2_64BIT_BAR_HIGH                                                              0x045b
1346 #define mmUVD_LMI_MIF_BSD2_64BIT_BAR_HIGH_BASE_IDX                                                     1
1347 #define mmUVD_LMI_MIF_BSD3_64BIT_BAR_LOW                                                               0x045c
1348 #define mmUVD_LMI_MIF_BSD3_64BIT_BAR_LOW_BASE_IDX                                                      1
1349 #define mmUVD_LMI_MIF_BSD3_64BIT_BAR_HIGH                                                              0x045d
1350 #define mmUVD_LMI_MIF_BSD3_64BIT_BAR_HIGH_BASE_IDX                                                     1
1351 #define mmUVD_LMI_MIF_BSD4_64BIT_BAR_LOW                                                               0x045e
1352 #define mmUVD_LMI_MIF_BSD4_64BIT_BAR_LOW_BASE_IDX                                                      1
1353 #define mmUVD_LMI_MIF_BSD4_64BIT_BAR_HIGH                                                              0x045f
1354 #define mmUVD_LMI_MIF_BSD4_64BIT_BAR_HIGH_BASE_IDX                                                     1
1355 #define mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW                                                            0x0468
1356 #define mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW_BASE_IDX                                                   1
1357 #define mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH                                                           0x0469
1358 #define mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH_BASE_IDX                                                  1
1359 #define mmUVD_LMI_VCPU_CACHE8_64BIT_BAR_LOW                                                            0x046a
1360 #define mmUVD_LMI_VCPU_CACHE8_64BIT_BAR_LOW_BASE_IDX                                                   1
1361 #define mmUVD_LMI_VCPU_CACHE8_64BIT_BAR_HIGH                                                           0x046b
1362 #define mmUVD_LMI_VCPU_CACHE8_64BIT_BAR_HIGH_BASE_IDX                                                  1
1363 #define mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW                                                            0x046c
1364 #define mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW_BASE_IDX                                                   1
1365 #define mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH                                                           0x046d
1366 #define mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH_BASE_IDX                                                  1
1367 #define mmUVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW                                                            0x046e
1368 #define mmUVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW_BASE_IDX                                                   1
1369 #define mmUVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH                                                           0x046f
1370 #define mmUVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH_BASE_IDX                                                  1
1371 #define mmUVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW                                                            0x0470
1372 #define mmUVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW_BASE_IDX                                                   1
1373 #define mmUVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH                                                           0x0471
1374 #define mmUVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH_BASE_IDX                                                  1
1375 #define mmUVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW                                                            0x0472
1376 #define mmUVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW_BASE_IDX                                                   1
1377 #define mmUVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH                                                           0x0473
1378 #define mmUVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH_BASE_IDX                                                  1
1379 #define mmUVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW                                                            0x0474
1380 #define mmUVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW_BASE_IDX                                                   1
1381 #define mmUVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH                                                           0x0475
1382 #define mmUVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH_BASE_IDX                                                  1
1383 #define mmUVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW                                                            0x0476
1384 #define mmUVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW_BASE_IDX                                                   1
1385 #define mmUVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH                                                           0x0477
1386 #define mmUVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH_BASE_IDX                                                  1
1387 #define mmUVD_LMI_MIF_SCLR_64BIT_BAR_LOW                                                               0x0478
1388 #define mmUVD_LMI_MIF_SCLR_64BIT_BAR_LOW_BASE_IDX                                                      1
1389 #define mmUVD_LMI_MIF_SCLR_64BIT_BAR_HIGH                                                              0x0479
1390 #define mmUVD_LMI_MIF_SCLR_64BIT_BAR_HIGH_BASE_IDX                                                     1
1391 #define mmUVD_LMI_MIF_SCLR2_64BIT_BAR_LOW                                                              0x047a
1392 #define mmUVD_LMI_MIF_SCLR2_64BIT_BAR_LOW_BASE_IDX                                                     1
1393 #define mmUVD_LMI_MIF_SCLR2_64BIT_BAR_HIGH                                                             0x047b
1394 #define mmUVD_LMI_MIF_SCLR2_64BIT_BAR_HIGH_BASE_IDX                                                    1
1395 #define mmUVD_LMI_SPH_64BIT_BAR_HIGH                                                                   0x047c
1396 #define mmUVD_LMI_SPH_64BIT_BAR_HIGH_BASE_IDX                                                          1
1397 #define mmUVD_LMI_MMSCH_NC0_64BIT_BAR_LOW                                                              0x047d
1398 #define mmUVD_LMI_MMSCH_NC0_64BIT_BAR_LOW_BASE_IDX                                                     1
1399 #define mmUVD_LMI_MMSCH_NC0_64BIT_BAR_HIGH                                                             0x047e
1400 #define mmUVD_LMI_MMSCH_NC0_64BIT_BAR_HIGH_BASE_IDX                                                    1
1401 #define mmUVD_LMI_MMSCH_NC1_64BIT_BAR_LOW                                                              0x047f
1402 #define mmUVD_LMI_MMSCH_NC1_64BIT_BAR_LOW_BASE_IDX                                                     1
1403 #define mmUVD_LMI_MMSCH_NC1_64BIT_BAR_HIGH                                                             0x0480
1404 #define mmUVD_LMI_MMSCH_NC1_64BIT_BAR_HIGH_BASE_IDX                                                    1
1405 #define mmUVD_LMI_MMSCH_NC2_64BIT_BAR_LOW                                                              0x0481
1406 #define mmUVD_LMI_MMSCH_NC2_64BIT_BAR_LOW_BASE_IDX                                                     1
1407 #define mmUVD_LMI_MMSCH_NC2_64BIT_BAR_HIGH                                                             0x0482
1408 #define mmUVD_LMI_MMSCH_NC2_64BIT_BAR_HIGH_BASE_IDX                                                    1
1409 #define mmUVD_LMI_MMSCH_NC3_64BIT_BAR_LOW                                                              0x0483
1410 #define mmUVD_LMI_MMSCH_NC3_64BIT_BAR_LOW_BASE_IDX                                                     1
1411 #define mmUVD_LMI_MMSCH_NC3_64BIT_BAR_HIGH                                                             0x0484
1412 #define mmUVD_LMI_MMSCH_NC3_64BIT_BAR_HIGH_BASE_IDX                                                    1
1413 #define mmUVD_LMI_MMSCH_NC4_64BIT_BAR_LOW                                                              0x0485
1414 #define mmUVD_LMI_MMSCH_NC4_64BIT_BAR_LOW_BASE_IDX                                                     1
1415 #define mmUVD_LMI_MMSCH_NC4_64BIT_BAR_HIGH                                                             0x0486
1416 #define mmUVD_LMI_MMSCH_NC4_64BIT_BAR_HIGH_BASE_IDX                                                    1
1417 #define mmUVD_LMI_MMSCH_NC5_64BIT_BAR_LOW                                                              0x0487
1418 #define mmUVD_LMI_MMSCH_NC5_64BIT_BAR_LOW_BASE_IDX                                                     1
1419 #define mmUVD_LMI_MMSCH_NC5_64BIT_BAR_HIGH                                                             0x0488
1420 #define mmUVD_LMI_MMSCH_NC5_64BIT_BAR_HIGH_BASE_IDX                                                    1
1421 #define mmUVD_LMI_MMSCH_NC6_64BIT_BAR_LOW                                                              0x0489
1422 #define mmUVD_LMI_MMSCH_NC6_64BIT_BAR_LOW_BASE_IDX                                                     1
1423 #define mmUVD_LMI_MMSCH_NC6_64BIT_BAR_HIGH                                                             0x048a
1424 #define mmUVD_LMI_MMSCH_NC6_64BIT_BAR_HIGH_BASE_IDX                                                    1
1425 #define mmUVD_LMI_MMSCH_NC7_64BIT_BAR_LOW                                                              0x048b
1426 #define mmUVD_LMI_MMSCH_NC7_64BIT_BAR_LOW_BASE_IDX                                                     1
1427 #define mmUVD_LMI_MMSCH_NC7_64BIT_BAR_HIGH                                                             0x048c
1428 #define mmUVD_LMI_MMSCH_NC7_64BIT_BAR_HIGH_BASE_IDX                                                    1
1429 #define mmUVD_LMI_MMSCH_NC_VMID                                                                        0x048d
1430 #define mmUVD_LMI_MMSCH_NC_VMID_BASE_IDX                                                               1
1431 #define mmUVD_LMI_MMSCH_CTRL                                                                           0x048e
1432 #define mmUVD_LMI_MMSCH_CTRL_BASE_IDX                                                                  1
1433 #define mmUVD_MMSCH_LMI_STATUS                                                                         0x048f
1434 #define mmUVD_MMSCH_LMI_STATUS_BASE_IDX                                                                1
1435 #define mmUVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_LOW                                                    0x0490
1436 #define mmUVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_LOW_BASE_IDX                                           1
1437 #define mmUVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_HIGH                                                   0x0491
1438 #define mmUVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_HIGH_BASE_IDX                                          1
1439 #define mmUVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_LOW                                                  0x0492
1440 #define mmUVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_LOW_BASE_IDX                                         1
1441 #define mmUVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_HIGH                                                 0x0493
1442 #define mmUVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_HIGH_BASE_IDX                                        1
1443 #define mmUVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_LOW                                                       0x0494
1444 #define mmUVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_LOW_BASE_IDX                                              1
1445 #define mmUVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_HIGH                                                      0x0495
1446 #define mmUVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_HIGH_BASE_IDX                                             1
1447 #define mmUVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_LOW                                                     0x0496
1448 #define mmUVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_LOW_BASE_IDX                                            1
1449 #define mmUVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_HIGH                                                    0x0497
1450 #define mmUVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_HIGH_BASE_IDX                                           1
1451 #define mmUVD_ADP_ATOMIC_CONFIG                                                                        0x0499
1452 #define mmUVD_ADP_ATOMIC_CONFIG_BASE_IDX                                                               1
1453 #define mmUVD_LMI_ARB_CTRL2                                                                            0x049a
1454 #define mmUVD_LMI_ARB_CTRL2_BASE_IDX                                                                   1
1455 #define mmUVD_LMI_VCPU_CACHE_VMIDS_MULTI                                                               0x049f
1456 #define mmUVD_LMI_VCPU_CACHE_VMIDS_MULTI_BASE_IDX                                                      1
1457 #define mmUVD_LMI_VCPU_NC_VMIDS_MULTI                                                                  0x04a0
1458 #define mmUVD_LMI_VCPU_NC_VMIDS_MULTI_BASE_IDX                                                         1
1459 #define mmUVD_LMI_LAT_CTRL                                                                             0x04a1
1460 #define mmUVD_LMI_LAT_CTRL_BASE_IDX                                                                    1
1461 #define mmUVD_LMI_LAT_CNTR                                                                             0x04a2
1462 #define mmUVD_LMI_LAT_CNTR_BASE_IDX                                                                    1
1463 #define mmUVD_LMI_AVG_LAT_CNTR                                                                         0x04a3
1464 #define mmUVD_LMI_AVG_LAT_CNTR_BASE_IDX                                                                1
1465 #define mmUVD_LMI_SPH                                                                                  0x04a4
1466 #define mmUVD_LMI_SPH_BASE_IDX                                                                         1
1467 #define mmUVD_LMI_VCPU_CACHE_VMID                                                                      0x04a5
1468 #define mmUVD_LMI_VCPU_CACHE_VMID_BASE_IDX                                                             1
1469 #define mmUVD_LMI_CTRL2                                                                                0x04a6
1470 #define mmUVD_LMI_CTRL2_BASE_IDX                                                                       1
1471 #define mmUVD_LMI_URGENT_CTRL                                                                          0x04a7
1472 #define mmUVD_LMI_URGENT_CTRL_BASE_IDX                                                                 1
1473 #define mmUVD_LMI_CTRL                                                                                 0x04a8
1474 #define mmUVD_LMI_CTRL_BASE_IDX                                                                        1
1475 #define mmUVD_LMI_STATUS                                                                               0x04a9
1476 #define mmUVD_LMI_STATUS_BASE_IDX                                                                      1
1477 #define mmUVD_LMI_PERFMON_CTRL                                                                         0x04ac
1478 #define mmUVD_LMI_PERFMON_CTRL_BASE_IDX                                                                1
1479 #define mmUVD_LMI_PERFMON_COUNT_LO                                                                     0x04ad
1480 #define mmUVD_LMI_PERFMON_COUNT_LO_BASE_IDX                                                            1
1481 #define mmUVD_LMI_PERFMON_COUNT_HI                                                                     0x04ae
1482 #define mmUVD_LMI_PERFMON_COUNT_HI_BASE_IDX                                                            1
1483 #define mmUVD_LMI_ADP_SWAP_CNTL                                                                        0x04af
1484 #define mmUVD_LMI_ADP_SWAP_CNTL_BASE_IDX                                                               1
1485 #define mmUVD_LMI_RBC_RB_VMID                                                                          0x04b0
1486 #define mmUVD_LMI_RBC_RB_VMID_BASE_IDX                                                                 1
1487 #define mmUVD_LMI_RBC_IB_VMID                                                                          0x04b1
1488 #define mmUVD_LMI_RBC_IB_VMID_BASE_IDX                                                                 1
1489 #define mmUVD_LMI_MC_CREDITS                                                                           0x04b2
1490 #define mmUVD_LMI_MC_CREDITS_BASE_IDX                                                                  1
1491 #define mmUVD_LMI_ADP_IND_INDEX                                                                        0x04b6
1492 #define mmUVD_LMI_ADP_IND_INDEX_BASE_IDX                                                               1
1493 #define mmUVD_LMI_ADP_IND_DATA                                                                         0x04b7
1494 #define mmUVD_LMI_ADP_IND_DATA_BASE_IDX                                                                1
1495 #define mmUVD_LMI_ADP_PF_EN                                                                            0x04b8
1496 #define mmUVD_LMI_ADP_PF_EN_BASE_IDX                                                                   1
1497 #define mmUVD_LMI_ADP_CNN_CTRL                                                                         0x04b9
1498 #define mmUVD_LMI_ADP_CNN_CTRL_BASE_IDX                                                                1
1499 #define mmUVD_LMI_PREF_CTRL                                                                            0x04ba
1500 #define mmUVD_LMI_PREF_CTRL_BASE_IDX                                                                   1
1501 #define mmUVD_LMI_MIF_REF_LUMA_64BIT_BAR_LOW                                                           0x04d5
1502 #define mmUVD_LMI_MIF_REF_LUMA_64BIT_BAR_LOW_BASE_IDX                                                  1
1503 #define mmUVD_LMI_MIF_REF_LUMA_64BIT_BAR_HIGH                                                          0x04d6
1504 #define mmUVD_LMI_MIF_REF_LUMA_64BIT_BAR_HIGH_BASE_IDX                                                 1
1505 
1506 
1507 // addressBlock: uvdctxind
1508 // base address: 0x0
1509 #define ixUVD_CGC_MEM_CTRL                                                                             0x0000
1510 #define ixUVD_CGC_CTRL2                                                                                0x0001
1511 #define ixUVD_CGC_MEM_DS_CTRL                                                                          0x0002
1512 #define ixUVD_CGC_MEM_SD_CTRL                                                                          0x0003
1513 #define ixUVD_SW_SCRATCH_00                                                                            0x0004
1514 #define ixUVD_SW_SCRATCH_01                                                                            0x0005
1515 #define ixUVD_SW_SCRATCH_02                                                                            0x0006
1516 #define ixUVD_SW_SCRATCH_03                                                                            0x0007
1517 #define ixUVD_SW_SCRATCH_04                                                                            0x0008
1518 #define ixUVD_SW_SCRATCH_05                                                                            0x0009
1519 #define ixUVD_SW_SCRATCH_06                                                                            0x000a
1520 #define ixUVD_SW_SCRATCH_07                                                                            0x000b
1521 #define ixUVD_SW_SCRATCH_08                                                                            0x000c
1522 #define ixUVD_SW_SCRATCH_09                                                                            0x000d
1523 #define ixUVD_SW_SCRATCH_10                                                                            0x000e
1524 #define ixUVD_SW_SCRATCH_11                                                                            0x000f
1525 #define ixUVD_SW_SCRATCH_12                                                                            0x0010
1526 #define ixUVD_SW_SCRATCH_13                                                                            0x0011
1527 #define ixUVD_SW_SCRATCH_14                                                                            0x0012
1528 #define ixUVD_SW_SCRATCH_15                                                                            0x0013
1529 #define ixUVD_MEMCHECK_SYS_INT_EN                                                                      0x0014
1530 #define ixUVD_MEMCHECK_SYS_INT_STAT                                                                    0x0015
1531 #define ixUVD_MEMCHECK_SYS_INT_ACK                                                                     0x0016
1532 #define ixUVD_MEMCHECK_VCPU_INT_EN                                                                     0x0017
1533 #define ixUVD_MEMCHECK_VCPU_INT_STAT                                                                   0x0018
1534 #define ixUVD_MEMCHECK_VCPU_INT_ACK                                                                    0x0019
1535 #define ixUVD_MEMCHECK2_SYS_INT_STAT                                                                   0x001a
1536 #define ixUVD_MEMCHECK2_SYS_INT_ACK                                                                    0x001b
1537 #define ixUVD_MEMCHECK2_VCPU_INT_STAT                                                                  0x001c
1538 #define ixUVD_MEMCHECK2_VCPU_INT_ACK                                                                   0x001d
1539 #define ixUVD_IH_SEM_CTRL                                                                              0x001e
1540 
1541 
1542 #endif
1543