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Searched defs:mmDP3_DP_DPHY_BS_SR_SWAP_CNTL (Results 1 – 12 of 12) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/display/dc/dce100/
H A Ddce100_resource.c90 #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x4DDC macro
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dce112/
H A Ddce112_resource.c89 #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x4DDC macro
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dce110/
H A Ddce110_resource.c95 #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x4DDC macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_11_0_d.h4560 #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x4ddc macro
H A Ddce_11_2_d.h5792 #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x4ddc macro
H A Ddce_12_0_offset.h11150 #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL … macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_0_1_offset.h9038 #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL … macro
H A Ddcn_2_1_0_offset.h10941 #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL … macro
H A Ddcn_1_0_offset.h9377 #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL … macro
H A Ddcn_3_0_2_offset.h10660 #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL … macro
H A Ddcn_2_0_0_offset.h12028 #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL … macro
H A Ddcn_3_0_0_offset.h11796 #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL … macro