1 /* SPDX-License-Identifier: GPL-2.0
2  *
3  * Copyright 2016-2020 HabanaLabs, Ltd.
4  * All Rights Reserved.
5  *
6  */
7 
8 /************************************
9  ** This is an auto-generated file **
10  **       DO NOT EDIT BELOW        **
11  ************************************/
12 
13 #ifndef ASIC_REG_DCORE0_HMMU0_STLB_REGS_H_
14 #define ASIC_REG_DCORE0_HMMU0_STLB_REGS_H_
15 
16 /*
17  *****************************************
18  *   DCORE0_HMMU0_STLB
19  *   (Prototype: STLB)
20  *****************************************
21  */
22 
23 #define mmDCORE0_HMMU0_STLB_BUSY 0x4081000
24 
25 #define mmDCORE0_HMMU0_STLB_ASID 0x4081004
26 
27 #define mmDCORE0_HMMU0_STLB_HOP0_PA43_12 0x4081008
28 
29 #define mmDCORE0_HMMU0_STLB_HOP0_PA63_44 0x408100C
30 
31 #define mmDCORE0_HMMU0_STLB_CACHE_INV 0x4081010
32 
33 #define mmDCORE0_HMMU0_STLB_CACHE_INV_BASE_39_8 0x4081014
34 
35 #define mmDCORE0_HMMU0_STLB_CACHE_INV_BASE_63_40 0x4081018
36 
37 #define mmDCORE0_HMMU0_STLB_STLB_FEATURE_EN 0x408101C
38 
39 #define mmDCORE0_HMMU0_STLB_STLB_AXI_CACHE 0x4081020
40 
41 #define mmDCORE0_HMMU0_STLB_HOP_CONFIGURATION 0x4081024
42 
43 #define mmDCORE0_HMMU0_STLB_LINK_LIST_LOOKUP_MASK_63_32 0x4081028
44 
45 #define mmDCORE0_HMMU0_STLB_LINK_LIST_LOOKUP_MASK_31_0 0x408102C
46 
47 #define mmDCORE0_HMMU0_STLB_INV_ALL_START 0x4081034
48 
49 #define mmDCORE0_HMMU0_STLB_INV_ALL_SET 0x4081038
50 
51 #define mmDCORE0_HMMU0_STLB_INV_PS 0x408103C
52 
53 #define mmDCORE0_HMMU0_STLB_INV_CONSUMER_INDEX 0x4081040
54 
55 #define mmDCORE0_HMMU0_STLB_INV_HIT_COUNT 0x4081044
56 
57 #define mmDCORE0_HMMU0_STLB_INV_SET 0x4081048
58 
59 #define mmDCORE0_HMMU0_STLB_SRAM_INIT 0x408104C
60 
61 #define mmDCORE0_HMMU0_STLB_MEM_CACHE_INVALIDATION 0x4081050
62 
63 #define mmDCORE0_HMMU0_STLB_MEM_CACHE_INV_STATUS 0x4081054
64 
65 #define mmDCORE0_HMMU0_STLB_MEM_CACHE_BASE_38_7 0x4081058
66 
67 #define mmDCORE0_HMMU0_STLB_MEM_CACHE_BASE_63_39 0x408105C
68 
69 #define mmDCORE0_HMMU0_STLB_MEM_CACHE_CONFIG 0x4081060
70 
71 #define mmDCORE0_HMMU0_STLB_SET_THRESHOLD_HOP5 0x4081064
72 
73 #define mmDCORE0_HMMU0_STLB_SET_THRESHOLD_HOP4 0x4081068
74 
75 #define mmDCORE0_HMMU0_STLB_SET_THRESHOLD_HOP3 0x408106C
76 
77 #define mmDCORE0_HMMU0_STLB_SET_THRESHOLD_HOP2 0x4081070
78 
79 #define mmDCORE0_HMMU0_STLB_SET_THRESHOLD_HOP1 0x4081074
80 
81 #define mmDCORE0_HMMU0_STLB_SET_THRESHOLD_HOP0 0x4081078
82 
83 #define mmDCORE0_HMMU0_STLB_MULTI_HIT_INTERRUPT_CLR 0x408107C
84 
85 #define mmDCORE0_HMMU0_STLB_MULTI_HIT_INTERRUPT_MASK 0x4081080
86 
87 #define mmDCORE0_HMMU0_STLB_MEM_L0_CACHE_CFG 0x4081084
88 
89 #define mmDCORE0_HMMU0_STLB_MEM_READ_ARPROT 0x4081088
90 
91 #define mmDCORE0_HMMU0_STLB_RANGE_CACHE_INVALIDATION 0x408108C
92 
93 #define mmDCORE0_HMMU0_STLB_RANGE_INV_START_LSB 0x4081090
94 
95 #define mmDCORE0_HMMU0_STLB_RANGE_INV_START_MSB 0x4081094
96 
97 #define mmDCORE0_HMMU0_STLB_RANGE_INV_END_LSB 0x4081098
98 
99 #define mmDCORE0_HMMU0_STLB_RANGE_INV_END_MSB 0x408109C
100 
101 #define mmDCORE0_HMMU0_STLB_ASID_SCRAMBLER_CTRL 0x4081100
102 
103 #define mmDCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_0 0x4081104
104 
105 #define mmDCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_1 0x4081108
106 
107 #define mmDCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_2 0x408110C
108 
109 #define mmDCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_3 0x4081110
110 
111 #define mmDCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_4 0x4081114
112 
113 #define mmDCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_5 0x4081118
114 
115 #define mmDCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_6 0x408111C
116 
117 #define mmDCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_7 0x4081120
118 
119 #define mmDCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_8 0x4081124
120 
121 #define mmDCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_9 0x4081128
122 
123 #define mmDCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_10 0x408112C
124 
125 #define mmDCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_11 0x4081130
126 
127 #define mmDCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_12 0x4081134
128 
129 #define mmDCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_13 0x4081138
130 
131 #define mmDCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_14 0x408113C
132 
133 #define mmDCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_15 0x4081140
134 
135 #define mmDCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_16 0x4081144
136 
137 #define mmDCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_17 0x4081148
138 
139 #define mmDCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_18 0x408114C
140 
141 #endif /* ASIC_REG_DCORE0_HMMU0_STLB_REGS_H_ */
142