1 // SPDX-License-Identifier: MIT 2 #ifndef _dcn_3_0_0_OFFSET_HEADER 3 #define _dcn_3_0_0_OFFSET_HEADER 4 5 6 7 // addressBlock: dce_dc_mmhubbub_vga_dispdec 8 // base address: 0x0 9 #define mmVGA_MEM_WRITE_PAGE_ADDR 0x0000 10 #define mmVGA_MEM_WRITE_PAGE_ADDR 0x0000 11 #define mmVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX 0 12 #define mmVGA_MEM_READ_PAGE_ADDR 0x0001 13 #define mmVGA_MEM_READ_PAGE_ADDR_BASE_IDX 0 14 #define mmVGA_RENDER_CONTROL 0x0000 15 #define mmVGA_RENDER_CONTROL_BASE_IDX 1 16 #define mmVGA_SEQUENCER_RESET_CONTROL 0x0001 17 #define mmVGA_SEQUENCER_RESET_CONTROL_BASE_IDX 1 18 #define mmVGA_MODE_CONTROL 0x0002 19 #define mmVGA_MODE_CONTROL_BASE_IDX 1 20 #define mmVGA_SURFACE_PITCH_SELECT 0x0003 21 #define mmVGA_SURFACE_PITCH_SELECT_BASE_IDX 1 22 #define mmVGA_MEMORY_BASE_ADDRESS 0x0004 23 #define mmVGA_MEMORY_BASE_ADDRESS_BASE_IDX 1 24 #define mmVGA_DISPBUF1_SURFACE_ADDR 0x0006 25 #define mmVGA_DISPBUF1_SURFACE_ADDR_BASE_IDX 1 26 #define mmVGA_DISPBUF2_SURFACE_ADDR 0x0008 27 #define mmVGA_DISPBUF2_SURFACE_ADDR_BASE_IDX 1 28 #define mmVGA_MEMORY_BASE_ADDRESS_HIGH 0x0009 29 #define mmVGA_MEMORY_BASE_ADDRESS_HIGH_BASE_IDX 1 30 #define mmVGA_HDP_CONTROL 0x000a 31 #define mmVGA_HDP_CONTROL_BASE_IDX 1 32 #define mmVGA_CACHE_CONTROL 0x000b 33 #define mmVGA_CACHE_CONTROL_BASE_IDX 1 34 #define mmD1VGA_CONTROL 0x000c 35 #define mmD1VGA_CONTROL_BASE_IDX 1 36 #define mmD2VGA_CONTROL 0x000e 37 #define mmD2VGA_CONTROL_BASE_IDX 1 38 #define mmVGA_STATUS 0x0010 39 #define mmVGA_STATUS_BASE_IDX 1 40 #define mmVGA_INTERRUPT_CONTROL 0x0011 41 #define mmVGA_INTERRUPT_CONTROL_BASE_IDX 1 42 #define mmVGA_STATUS_CLEAR 0x0012 43 #define mmVGA_STATUS_CLEAR_BASE_IDX 1 44 #define mmVGA_INTERRUPT_STATUS 0x0013 45 #define mmVGA_INTERRUPT_STATUS_BASE_IDX 1 46 #define mmVGA_MAIN_CONTROL 0x0014 47 #define mmVGA_MAIN_CONTROL_BASE_IDX 1 48 #define mmVGA_TEST_CONTROL 0x0015 49 #define mmVGA_TEST_CONTROL_BASE_IDX 1 50 #define mmVGA_QOS_CTRL 0x0018 51 #define mmVGA_QOS_CTRL_BASE_IDX 1 52 #define mmCRTC8_IDX 0x002d 53 #define mmCRTC8_IDX_BASE_IDX 1 54 #define mmCRTC8_DATA 0x002d 55 #define mmCRTC8_DATA_BASE_IDX 1 56 #define mmGENFC_WT 0x002e 57 #define mmGENFC_WT_BASE_IDX 1 58 #define mmGENS1 0x002e 59 #define mmGENS1_BASE_IDX 1 60 #define mmATTRDW 0x0030 61 #define mmATTRDW_BASE_IDX 1 62 #define mmATTRX 0x0030 63 #define mmATTRX_BASE_IDX 1 64 #define mmATTRDR 0x0030 65 #define mmATTRDR_BASE_IDX 1 66 #define mmGENMO_WT 0x0030 67 #define mmGENMO_WT_BASE_IDX 1 68 #define mmGENS0 0x0030 69 #define mmGENS0_BASE_IDX 1 70 #define mmGENENB 0x0030 71 #define mmGENENB_BASE_IDX 1 72 #define mmSEQ8_IDX 0x0031 73 #define mmSEQ8_IDX_BASE_IDX 1 74 #define mmSEQ8_DATA 0x0031 75 #define mmSEQ8_DATA_BASE_IDX 1 76 #define mmDAC_MASK 0x0031 77 #define mmDAC_MASK_BASE_IDX 1 78 #define mmDAC_R_INDEX 0x0031 79 #define mmDAC_R_INDEX_BASE_IDX 1 80 #define mmDAC_W_INDEX 0x0032 81 #define mmDAC_W_INDEX_BASE_IDX 1 82 #define mmDAC_DATA 0x0032 83 #define mmDAC_DATA_BASE_IDX 1 84 #define mmGENFC_RD 0x0032 85 #define mmGENFC_RD_BASE_IDX 1 86 #define mmGENMO_RD 0x0033 87 #define mmGENMO_RD_BASE_IDX 1 88 #define mmGRPH8_IDX 0x0033 89 #define mmGRPH8_IDX_BASE_IDX 1 90 #define mmGRPH8_DATA 0x0033 91 #define mmGRPH8_DATA_BASE_IDX 1 92 #define mmCRTC8_IDX_1 0x0035 93 #define mmCRTC8_IDX_1_BASE_IDX 1 94 #define mmCRTC8_DATA_1 0x0035 95 #define mmCRTC8_DATA_1_BASE_IDX 1 96 #define mmGENFC_WT_1 0x0036 97 #define mmGENFC_WT_1_BASE_IDX 1 98 #define mmGENS1_1 0x0036 99 #define mmGENS1_1_BASE_IDX 1 100 #define mmD3VGA_CONTROL 0x0038 101 #define mmD3VGA_CONTROL_BASE_IDX 1 102 #define mmD4VGA_CONTROL 0x0039 103 #define mmD4VGA_CONTROL_BASE_IDX 1 104 #define mmD5VGA_CONTROL 0x003a 105 #define mmD5VGA_CONTROL_BASE_IDX 1 106 #define mmD6VGA_CONTROL 0x003b 107 #define mmD6VGA_CONTROL_BASE_IDX 1 108 #define mmVGA_SOURCE_SELECT 0x003c 109 #define mmVGA_SOURCE_SELECT_BASE_IDX 1 110 111 112 // addressBlock: dce_dc_dccg_dccg_dispdec 113 // base address: 0x0 114 #define mmPHYPLLA_PIXCLK_RESYNC_CNTL 0x0040 115 #define mmPHYPLLA_PIXCLK_RESYNC_CNTL_BASE_IDX 1 116 #define mmPHYPLLB_PIXCLK_RESYNC_CNTL 0x0041 117 #define mmPHYPLLB_PIXCLK_RESYNC_CNTL_BASE_IDX 1 118 #define mmPHYPLLC_PIXCLK_RESYNC_CNTL 0x0042 119 #define mmPHYPLLC_PIXCLK_RESYNC_CNTL_BASE_IDX 1 120 #define mmPHYPLLD_PIXCLK_RESYNC_CNTL 0x0043 121 #define mmPHYPLLD_PIXCLK_RESYNC_CNTL_BASE_IDX 1 122 #define mmDP_DTO_DBUF_EN 0x0044 123 #define mmDP_DTO_DBUF_EN_BASE_IDX 1 124 #define mmDSCCLK3_DTO_PARAM 0x0045 125 #define mmDSCCLK3_DTO_PARAM_BASE_IDX 1 126 #define mmDSCCLK4_DTO_PARAM 0x0046 127 #define mmDSCCLK4_DTO_PARAM_BASE_IDX 1 128 #define mmDSCCLK5_DTO_PARAM 0x0047 129 #define mmDSCCLK5_DTO_PARAM_BASE_IDX 1 130 #define mmDPREFCLK_CGTT_BLK_CTRL_REG 0x0048 131 #define mmDPREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 132 #define mmREFCLK_CNTL 0x0049 133 #define mmREFCLK_CNTL_BASE_IDX 1 134 #define mmREFCLK_CGTT_BLK_CTRL_REG 0x004b 135 #define mmREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 136 #define mmPHYPLLE_PIXCLK_RESYNC_CNTL 0x004c 137 #define mmPHYPLLE_PIXCLK_RESYNC_CNTL_BASE_IDX 1 138 #define mmDCCG_PERFMON_CNTL2 0x004e 139 #define mmDCCG_PERFMON_CNTL2_BASE_IDX 1 140 #define mmDCCG_DS_DTO_INCR 0x0053 141 #define mmDCCG_DS_DTO_INCR_BASE_IDX 1 142 #define mmDCCG_DS_DTO_MODULO 0x0054 143 #define mmDCCG_DS_DTO_MODULO_BASE_IDX 1 144 #define mmDCCG_DS_CNTL 0x0055 145 #define mmDCCG_DS_CNTL_BASE_IDX 1 146 #define mmDCCG_DS_HW_CAL_INTERVAL 0x0056 147 #define mmDCCG_DS_HW_CAL_INTERVAL_BASE_IDX 1 148 #define mmDPREFCLK_CNTL 0x0058 149 #define mmDPREFCLK_CNTL_BASE_IDX 1 150 #define mmDCE_VERSION 0x005e 151 #define mmDCE_VERSION_BASE_IDX 1 152 #define mmDCCG_GTC_CNTL 0x0060 153 #define mmDCCG_GTC_CNTL_BASE_IDX 1 154 #define mmDCCG_GTC_DTO_INCR 0x0061 155 #define mmDCCG_GTC_DTO_INCR_BASE_IDX 1 156 #define mmDCCG_GTC_DTO_MODULO 0x0062 157 #define mmDCCG_GTC_DTO_MODULO_BASE_IDX 1 158 #define mmDCCG_GTC_CURRENT 0x0063 159 #define mmDCCG_GTC_CURRENT_BASE_IDX 1 160 #define mmDSCCLK0_DTO_PARAM 0x006c 161 #define mmDSCCLK0_DTO_PARAM_BASE_IDX 1 162 #define mmDSCCLK1_DTO_PARAM 0x006d 163 #define mmDSCCLK1_DTO_PARAM_BASE_IDX 1 164 #define mmDSCCLK2_DTO_PARAM 0x006e 165 #define mmDSCCLK2_DTO_PARAM_BASE_IDX 1 166 #define mmMILLISECOND_TIME_BASE_DIV 0x0070 167 #define mmMILLISECOND_TIME_BASE_DIV_BASE_IDX 1 168 #define mmDISPCLK_FREQ_CHANGE_CNTL 0x0071 169 #define mmDISPCLK_FREQ_CHANGE_CNTL_BASE_IDX 1 170 #define mmDC_MEM_GLOBAL_PWR_REQ_CNTL 0x0072 171 #define mmDC_MEM_GLOBAL_PWR_REQ_CNTL_BASE_IDX 1 172 #define mmDCCG_PERFMON_CNTL 0x0073 173 #define mmDCCG_PERFMON_CNTL_BASE_IDX 1 174 #define mmDCCG_GATE_DISABLE_CNTL 0x0074 175 #define mmDCCG_GATE_DISABLE_CNTL_BASE_IDX 1 176 #define mmDISPCLK_CGTT_BLK_CTRL_REG 0x0075 177 #define mmDISPCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 178 #define mmSOCCLK_CGTT_BLK_CTRL_REG 0x0076 179 #define mmSOCCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 180 #define mmDCCG_CAC_STATUS 0x0077 181 #define mmDCCG_CAC_STATUS_BASE_IDX 1 182 #define mmMICROSECOND_TIME_BASE_DIV 0x007b 183 #define mmMICROSECOND_TIME_BASE_DIV_BASE_IDX 1 184 #define mmDCCG_GATE_DISABLE_CNTL2 0x007c 185 #define mmDCCG_GATE_DISABLE_CNTL2_BASE_IDX 1 186 #define mmSYMCLK_CGTT_BLK_CTRL_REG 0x007d 187 #define mmSYMCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 188 #define mmPHYPLLF_PIXCLK_RESYNC_CNTL 0x007e 189 #define mmPHYPLLF_PIXCLK_RESYNC_CNTL_BASE_IDX 1 190 #define mmDCCG_DISP_CNTL_REG 0x007f 191 #define mmDCCG_DISP_CNTL_REG_BASE_IDX 1 192 #define mmOTG0_PIXEL_RATE_CNTL 0x0080 193 #define mmOTG0_PIXEL_RATE_CNTL_BASE_IDX 1 194 #define mmDP_DTO0_PHASE 0x0081 195 #define mmDP_DTO0_PHASE_BASE_IDX 1 196 #define mmDP_DTO0_MODULO 0x0082 197 #define mmDP_DTO0_MODULO_BASE_IDX 1 198 #define mmOTG0_PHYPLL_PIXEL_RATE_CNTL 0x0083 199 #define mmOTG0_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 200 #define mmOTG1_PIXEL_RATE_CNTL 0x0084 201 #define mmOTG1_PIXEL_RATE_CNTL_BASE_IDX 1 202 #define mmDP_DTO1_PHASE 0x0085 203 #define mmDP_DTO1_PHASE_BASE_IDX 1 204 #define mmDP_DTO1_MODULO 0x0086 205 #define mmDP_DTO1_MODULO_BASE_IDX 1 206 #define mmOTG1_PHYPLL_PIXEL_RATE_CNTL 0x0087 207 #define mmOTG1_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 208 #define mmOTG2_PIXEL_RATE_CNTL 0x0088 209 #define mmOTG2_PIXEL_RATE_CNTL_BASE_IDX 1 210 #define mmDP_DTO2_PHASE 0x0089 211 #define mmDP_DTO2_PHASE_BASE_IDX 1 212 #define mmDP_DTO2_MODULO 0x008a 213 #define mmDP_DTO2_MODULO_BASE_IDX 1 214 #define mmOTG2_PHYPLL_PIXEL_RATE_CNTL 0x008b 215 #define mmOTG2_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 216 #define mmOTG3_PIXEL_RATE_CNTL 0x008c 217 #define mmOTG3_PIXEL_RATE_CNTL_BASE_IDX 1 218 #define mmDP_DTO3_PHASE 0x008d 219 #define mmDP_DTO3_PHASE_BASE_IDX 1 220 #define mmDP_DTO3_MODULO 0x008e 221 #define mmDP_DTO3_MODULO_BASE_IDX 1 222 #define mmOTG3_PHYPLL_PIXEL_RATE_CNTL 0x008f 223 #define mmOTG3_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 224 #define mmOTG4_PIXEL_RATE_CNTL 0x0090 225 #define mmOTG4_PIXEL_RATE_CNTL_BASE_IDX 1 226 #define mmDP_DTO4_PHASE 0x0091 227 #define mmDP_DTO4_PHASE_BASE_IDX 1 228 #define mmDP_DTO4_MODULO 0x0092 229 #define mmDP_DTO4_MODULO_BASE_IDX 1 230 #define mmOTG4_PHYPLL_PIXEL_RATE_CNTL 0x0093 231 #define mmOTG4_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 232 #define mmOTG5_PIXEL_RATE_CNTL 0x0094 233 #define mmOTG5_PIXEL_RATE_CNTL_BASE_IDX 1 234 #define mmDP_DTO5_PHASE 0x0095 235 #define mmDP_DTO5_PHASE_BASE_IDX 1 236 #define mmDP_DTO5_MODULO 0x0096 237 #define mmDP_DTO5_MODULO_BASE_IDX 1 238 #define mmOTG5_PHYPLL_PIXEL_RATE_CNTL 0x0097 239 #define mmOTG5_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 240 #define mmDPPCLK_CGTT_BLK_CTRL_REG 0x0098 241 #define mmDPPCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 242 #define mmDPPCLK0_DTO_PARAM 0x0099 243 #define mmDPPCLK0_DTO_PARAM_BASE_IDX 1 244 #define mmDPPCLK1_DTO_PARAM 0x009a 245 #define mmDPPCLK1_DTO_PARAM_BASE_IDX 1 246 #define mmDPPCLK2_DTO_PARAM 0x009b 247 #define mmDPPCLK2_DTO_PARAM_BASE_IDX 1 248 #define mmDPPCLK3_DTO_PARAM 0x009c 249 #define mmDPPCLK3_DTO_PARAM_BASE_IDX 1 250 #define mmDPPCLK4_DTO_PARAM 0x009d 251 #define mmDPPCLK4_DTO_PARAM_BASE_IDX 1 252 #define mmDPPCLK5_DTO_PARAM 0x009e 253 #define mmDPPCLK5_DTO_PARAM_BASE_IDX 1 254 #define mmDCCG_CAC_STATUS2 0x009f 255 #define mmDCCG_CAC_STATUS2_BASE_IDX 1 256 #define mmSYMCLKA_CLOCK_ENABLE 0x00a0 257 #define mmSYMCLKA_CLOCK_ENABLE_BASE_IDX 1 258 #define mmSYMCLKB_CLOCK_ENABLE 0x00a1 259 #define mmSYMCLKB_CLOCK_ENABLE_BASE_IDX 1 260 #define mmSYMCLKC_CLOCK_ENABLE 0x00a2 261 #define mmSYMCLKC_CLOCK_ENABLE_BASE_IDX 1 262 #define mmSYMCLKD_CLOCK_ENABLE 0x00a3 263 #define mmSYMCLKD_CLOCK_ENABLE_BASE_IDX 1 264 #define mmSYMCLKE_CLOCK_ENABLE 0x00a4 265 #define mmSYMCLKE_CLOCK_ENABLE_BASE_IDX 1 266 #define mmSYMCLKF_CLOCK_ENABLE 0x00a5 267 #define mmSYMCLKF_CLOCK_ENABLE_BASE_IDX 1 268 #define mmDCCG_SOFT_RESET 0x00a6 269 #define mmDCCG_SOFT_RESET_BASE_IDX 1 270 #define mmDSCCLK_DTO_CTRL 0x00a7 271 #define mmDSCCLK_DTO_CTRL_BASE_IDX 1 272 #define mmDCCG_AUDIO_DTO_SOURCE 0x00ab 273 #define mmDCCG_AUDIO_DTO_SOURCE_BASE_IDX 1 274 #define mmDCCG_AUDIO_DTO0_PHASE 0x00ac 275 #define mmDCCG_AUDIO_DTO0_PHASE_BASE_IDX 1 276 #define mmDCCG_AUDIO_DTO0_MODULE 0x00ad 277 #define mmDCCG_AUDIO_DTO0_MODULE_BASE_IDX 1 278 #define mmDCCG_AUDIO_DTO1_PHASE 0x00ae 279 #define mmDCCG_AUDIO_DTO1_PHASE_BASE_IDX 1 280 #define mmDCCG_AUDIO_DTO1_MODULE 0x00af 281 #define mmDCCG_AUDIO_DTO1_MODULE_BASE_IDX 1 282 #define mmDCCG_VSYNC_OTG0_LATCH_VALUE 0x00b0 283 #define mmDCCG_VSYNC_OTG0_LATCH_VALUE_BASE_IDX 1 284 #define mmDCCG_VSYNC_OTG1_LATCH_VALUE 0x00b1 285 #define mmDCCG_VSYNC_OTG1_LATCH_VALUE_BASE_IDX 1 286 #define mmDCCG_VSYNC_OTG2_LATCH_VALUE 0x00b2 287 #define mmDCCG_VSYNC_OTG2_LATCH_VALUE_BASE_IDX 1 288 #define mmDCCG_VSYNC_OTG3_LATCH_VALUE 0x00b3 289 #define mmDCCG_VSYNC_OTG3_LATCH_VALUE_BASE_IDX 1 290 #define mmDCCG_VSYNC_OTG4_LATCH_VALUE 0x00b4 291 #define mmDCCG_VSYNC_OTG4_LATCH_VALUE_BASE_IDX 1 292 #define mmDCCG_VSYNC_OTG5_LATCH_VALUE 0x00b5 293 #define mmDCCG_VSYNC_OTG5_LATCH_VALUE_BASE_IDX 1 294 #define mmDPPCLK_DTO_CTRL 0x00b6 295 #define mmDPPCLK_DTO_CTRL_BASE_IDX 1 296 #define mmDCCG_VSYNC_CNT_CTRL 0x00b8 297 #define mmDCCG_VSYNC_CNT_CTRL_BASE_IDX 1 298 #define mmDCCG_VSYNC_CNT_INT_CTRL 0x00b9 299 #define mmDCCG_VSYNC_CNT_INT_CTRL_BASE_IDX 1 300 #define mmFORCE_SYMCLK_DISABLE 0x00ba 301 #define mmFORCE_SYMCLK_DISABLE_BASE_IDX 1 302 #define mmPHYASYMCLK_CLOCK_CNTL 0x0052 303 #define mmPHYASYMCLK_CLOCK_CNTL_BASE_IDX 2 304 #define mmPHYBSYMCLK_CLOCK_CNTL 0x0053 305 #define mmPHYBSYMCLK_CLOCK_CNTL_BASE_IDX 2 306 #define mmPHYCSYMCLK_CLOCK_CNTL 0x0054 307 #define mmPHYCSYMCLK_CLOCK_CNTL_BASE_IDX 2 308 #define mmPHYDSYMCLK_CLOCK_CNTL 0x0055 309 #define mmPHYDSYMCLK_CLOCK_CNTL_BASE_IDX 2 310 #define mmPHYESYMCLK_CLOCK_CNTL 0x0056 311 #define mmPHYESYMCLK_CLOCK_CNTL_BASE_IDX 2 312 #define mmPHYFSYMCLK_CLOCK_CNTL 0x0057 313 #define mmPHYFSYMCLK_CLOCK_CNTL_BASE_IDX 2 314 315 316 // addressBlock: dce_dc_dccg_dccg_dfs_dispdec 317 // base address: 0x0 318 #define mmDENTIST_DISPCLK_CNTL 0x0064 319 #define mmDENTIST_DISPCLK_CNTL_BASE_IDX 1 320 321 322 // addressBlock: dce_dc_dccg_dccg_dcperfmon0_dc_perfmon_dispdec 323 // base address: 0x0 324 #define mmDC_PERFMON0_PERFCOUNTER_CNTL 0x0000 325 #define mmDC_PERFMON0_PERFCOUNTER_CNTL_BASE_IDX 2 326 #define mmDC_PERFMON0_PERFCOUNTER_CNTL2 0x0001 327 #define mmDC_PERFMON0_PERFCOUNTER_CNTL2_BASE_IDX 2 328 #define mmDC_PERFMON0_PERFCOUNTER_STATE 0x0002 329 #define mmDC_PERFMON0_PERFCOUNTER_STATE_BASE_IDX 2 330 #define mmDC_PERFMON0_PERFMON_CNTL 0x0003 331 #define mmDC_PERFMON0_PERFMON_CNTL_BASE_IDX 2 332 #define mmDC_PERFMON0_PERFMON_CNTL2 0x0004 333 #define mmDC_PERFMON0_PERFMON_CNTL2_BASE_IDX 2 334 #define mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC 0x0005 335 #define mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 336 #define mmDC_PERFMON0_PERFMON_CVALUE_LOW 0x0006 337 #define mmDC_PERFMON0_PERFMON_CVALUE_LOW_BASE_IDX 2 338 #define mmDC_PERFMON0_PERFMON_HI 0x0007 339 #define mmDC_PERFMON0_PERFMON_HI_BASE_IDX 2 340 #define mmDC_PERFMON0_PERFMON_LOW 0x0008 341 #define mmDC_PERFMON0_PERFMON_LOW_BASE_IDX 2 342 343 344 // addressBlock: dce_dc_dccg_dccg_dcperfmon1_dc_perfmon_dispdec 345 // base address: 0x30 346 #define mmDC_PERFMON1_PERFCOUNTER_CNTL 0x000c 347 #define mmDC_PERFMON1_PERFCOUNTER_CNTL_BASE_IDX 2 348 #define mmDC_PERFMON1_PERFCOUNTER_CNTL2 0x000d 349 #define mmDC_PERFMON1_PERFCOUNTER_CNTL2_BASE_IDX 2 350 #define mmDC_PERFMON1_PERFCOUNTER_STATE 0x000e 351 #define mmDC_PERFMON1_PERFCOUNTER_STATE_BASE_IDX 2 352 #define mmDC_PERFMON1_PERFMON_CNTL 0x000f 353 #define mmDC_PERFMON1_PERFMON_CNTL_BASE_IDX 2 354 #define mmDC_PERFMON1_PERFMON_CNTL2 0x0010 355 #define mmDC_PERFMON1_PERFMON_CNTL2_BASE_IDX 2 356 #define mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC 0x0011 357 #define mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 358 #define mmDC_PERFMON1_PERFMON_CVALUE_LOW 0x0012 359 #define mmDC_PERFMON1_PERFMON_CVALUE_LOW_BASE_IDX 2 360 #define mmDC_PERFMON1_PERFMON_HI 0x0013 361 #define mmDC_PERFMON1_PERFMON_HI_BASE_IDX 2 362 #define mmDC_PERFMON1_PERFMON_LOW 0x0014 363 #define mmDC_PERFMON1_PERFMON_LOW_BASE_IDX 2 364 365 366 // addressBlock: dce_dc_dmu_dc_pg_dispdec 367 // base address: 0x0 368 #define mmDOMAIN0_PG_CONFIG 0x0080 369 #define mmDOMAIN0_PG_CONFIG_BASE_IDX 2 370 #define mmDOMAIN0_PG_STATUS 0x0081 371 #define mmDOMAIN0_PG_STATUS_BASE_IDX 2 372 #define mmDOMAIN1_PG_CONFIG 0x0082 373 #define mmDOMAIN1_PG_CONFIG_BASE_IDX 2 374 #define mmDOMAIN1_PG_STATUS 0x0083 375 #define mmDOMAIN1_PG_STATUS_BASE_IDX 2 376 #define mmDOMAIN2_PG_CONFIG 0x0084 377 #define mmDOMAIN2_PG_CONFIG_BASE_IDX 2 378 #define mmDOMAIN2_PG_STATUS 0x0085 379 #define mmDOMAIN2_PG_STATUS_BASE_IDX 2 380 #define mmDOMAIN3_PG_CONFIG 0x0086 381 #define mmDOMAIN3_PG_CONFIG_BASE_IDX 2 382 #define mmDOMAIN3_PG_STATUS 0x0087 383 #define mmDOMAIN3_PG_STATUS_BASE_IDX 2 384 #define mmDOMAIN4_PG_CONFIG 0x0088 385 #define mmDOMAIN4_PG_CONFIG_BASE_IDX 2 386 #define mmDOMAIN4_PG_STATUS 0x0089 387 #define mmDOMAIN4_PG_STATUS_BASE_IDX 2 388 #define mmDOMAIN5_PG_CONFIG 0x008a 389 #define mmDOMAIN5_PG_CONFIG_BASE_IDX 2 390 #define mmDOMAIN5_PG_STATUS 0x008b 391 #define mmDOMAIN5_PG_STATUS_BASE_IDX 2 392 #define mmDOMAIN6_PG_CONFIG 0x008c 393 #define mmDOMAIN6_PG_CONFIG_BASE_IDX 2 394 #define mmDOMAIN6_PG_STATUS 0x008d 395 #define mmDOMAIN6_PG_STATUS_BASE_IDX 2 396 #define mmDOMAIN7_PG_CONFIG 0x008e 397 #define mmDOMAIN7_PG_CONFIG_BASE_IDX 2 398 #define mmDOMAIN7_PG_STATUS 0x008f 399 #define mmDOMAIN7_PG_STATUS_BASE_IDX 2 400 #define mmDOMAIN8_PG_CONFIG 0x0090 401 #define mmDOMAIN8_PG_CONFIG_BASE_IDX 2 402 #define mmDOMAIN8_PG_STATUS 0x0091 403 #define mmDOMAIN8_PG_STATUS_BASE_IDX 2 404 #define mmDOMAIN9_PG_CONFIG 0x0092 405 #define mmDOMAIN9_PG_CONFIG_BASE_IDX 2 406 #define mmDOMAIN9_PG_STATUS 0x0093 407 #define mmDOMAIN9_PG_STATUS_BASE_IDX 2 408 #define mmDOMAIN10_PG_CONFIG 0x0094 409 #define mmDOMAIN10_PG_CONFIG_BASE_IDX 2 410 #define mmDOMAIN10_PG_STATUS 0x0095 411 #define mmDOMAIN10_PG_STATUS_BASE_IDX 2 412 #define mmDOMAIN11_PG_CONFIG 0x0096 413 #define mmDOMAIN11_PG_CONFIG_BASE_IDX 2 414 #define mmDOMAIN11_PG_STATUS 0x0097 415 #define mmDOMAIN11_PG_STATUS_BASE_IDX 2 416 #define mmDOMAIN16_PG_CONFIG 0x00a1 417 #define mmDOMAIN16_PG_CONFIG_BASE_IDX 2 418 #define mmDOMAIN16_PG_STATUS 0x00a2 419 #define mmDOMAIN16_PG_STATUS_BASE_IDX 2 420 #define mmDOMAIN17_PG_CONFIG 0x00a3 421 #define mmDOMAIN17_PG_CONFIG_BASE_IDX 2 422 #define mmDOMAIN17_PG_STATUS 0x00a4 423 #define mmDOMAIN17_PG_STATUS_BASE_IDX 2 424 #define mmDOMAIN18_PG_CONFIG 0x00a5 425 #define mmDOMAIN18_PG_CONFIG_BASE_IDX 2 426 #define mmDOMAIN18_PG_STATUS 0x00a6 427 #define mmDOMAIN18_PG_STATUS_BASE_IDX 2 428 #define mmDOMAIN19_PG_CONFIG 0x00a7 429 #define mmDOMAIN19_PG_CONFIG_BASE_IDX 2 430 #define mmDOMAIN19_PG_STATUS 0x00a8 431 #define mmDOMAIN19_PG_STATUS_BASE_IDX 2 432 #define mmDOMAIN20_PG_CONFIG 0x00a9 433 #define mmDOMAIN20_PG_CONFIG_BASE_IDX 2 434 #define mmDOMAIN20_PG_STATUS 0x00aa 435 #define mmDOMAIN20_PG_STATUS_BASE_IDX 2 436 #define mmDOMAIN21_PG_CONFIG 0x00ab 437 #define mmDOMAIN21_PG_CONFIG_BASE_IDX 2 438 #define mmDOMAIN21_PG_STATUS 0x00ac 439 #define mmDOMAIN21_PG_STATUS_BASE_IDX 2 440 #define mmDCPG_INTERRUPT_STATUS 0x00ad 441 #define mmDCPG_INTERRUPT_STATUS_BASE_IDX 2 442 #define mmDCPG_INTERRUPT_STATUS_2 0x00ae 443 #define mmDCPG_INTERRUPT_STATUS_2_BASE_IDX 2 444 #define mmDCPG_INTERRUPT_CONTROL_1 0x00af 445 #define mmDCPG_INTERRUPT_CONTROL_1_BASE_IDX 2 446 #define mmDCPG_INTERRUPT_CONTROL_2 0x00b0 447 #define mmDCPG_INTERRUPT_CONTROL_2_BASE_IDX 2 448 #define mmDCPG_INTERRUPT_CONTROL_3 0x00b1 449 #define mmDCPG_INTERRUPT_CONTROL_3_BASE_IDX 2 450 #define mmDC_IP_REQUEST_CNTL 0x00b2 451 #define mmDC_IP_REQUEST_CNTL_BASE_IDX 2 452 453 454 // addressBlock: dce_dc_dmu_dmu_dcperfmon_dc_perfmon_dispdec 455 // base address: 0x2f8 456 #define mmDC_PERFMON2_PERFCOUNTER_CNTL 0x00be 457 #define mmDC_PERFMON2_PERFCOUNTER_CNTL_BASE_IDX 2 458 #define mmDC_PERFMON2_PERFCOUNTER_CNTL2 0x00bf 459 #define mmDC_PERFMON2_PERFCOUNTER_CNTL2_BASE_IDX 2 460 #define mmDC_PERFMON2_PERFCOUNTER_STATE 0x00c0 461 #define mmDC_PERFMON2_PERFCOUNTER_STATE_BASE_IDX 2 462 #define mmDC_PERFMON2_PERFMON_CNTL 0x00c1 463 #define mmDC_PERFMON2_PERFMON_CNTL_BASE_IDX 2 464 #define mmDC_PERFMON2_PERFMON_CNTL2 0x00c2 465 #define mmDC_PERFMON2_PERFMON_CNTL2_BASE_IDX 2 466 #define mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC 0x00c3 467 #define mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 468 #define mmDC_PERFMON2_PERFMON_CVALUE_LOW 0x00c4 469 #define mmDC_PERFMON2_PERFMON_CVALUE_LOW_BASE_IDX 2 470 #define mmDC_PERFMON2_PERFMON_HI 0x00c5 471 #define mmDC_PERFMON2_PERFMON_HI_BASE_IDX 2 472 #define mmDC_PERFMON2_PERFMON_LOW 0x00c6 473 #define mmDC_PERFMON2_PERFMON_LOW_BASE_IDX 2 474 475 476 // addressBlock: dce_dc_dmu_dmu_misc_dispdec 477 // base address: 0x0 478 #define mmCC_DC_PIPE_DIS 0x00ca 479 #define mmCC_DC_PIPE_DIS_BASE_IDX 2 480 #define mmDMU_CLK_CNTL 0x00cb 481 #define mmDMU_CLK_CNTL_BASE_IDX 2 482 #define mmDMU_MEM_PWR_CNTL 0x00cc 483 #define mmDMU_MEM_PWR_CNTL_BASE_IDX 2 484 #define mmDMCU_SMU_INTERRUPT_CNTL 0x00cd 485 #define mmDMCU_SMU_INTERRUPT_CNTL_BASE_IDX 2 486 #define mmSMU_INTERRUPT_CONTROL 0x00ce 487 #define mmSMU_INTERRUPT_CONTROL_BASE_IDX 2 488 #define mmDMU_MISC_ALLOW_DS_FORCE 0x00d6 489 #define mmDMU_MISC_ALLOW_DS_FORCE_BASE_IDX 2 490 491 492 // addressBlock: dce_dc_dmu_dmcu_dispdec 493 // base address: 0x0 494 #define mmDMCU_CTRL 0x00da 495 #define mmDMCU_CTRL_BASE_IDX 2 496 #define mmDMCU_STATUS 0x00db 497 #define mmDMCU_STATUS_BASE_IDX 2 498 #define mmDMCU_PC_START_ADDR 0x00dc 499 #define mmDMCU_PC_START_ADDR_BASE_IDX 2 500 #define mmDMCU_FW_START_ADDR 0x00dd 501 #define mmDMCU_FW_START_ADDR_BASE_IDX 2 502 #define mmDMCU_FW_END_ADDR 0x00de 503 #define mmDMCU_FW_END_ADDR_BASE_IDX 2 504 #define mmDMCU_FW_ISR_START_ADDR 0x00df 505 #define mmDMCU_FW_ISR_START_ADDR_BASE_IDX 2 506 #define mmDMCU_FW_CS_HI 0x00e0 507 #define mmDMCU_FW_CS_HI_BASE_IDX 2 508 #define mmDMCU_FW_CS_LO 0x00e1 509 #define mmDMCU_FW_CS_LO_BASE_IDX 2 510 #define mmDMCU_RAM_ACCESS_CTRL 0x00e2 511 #define mmDMCU_RAM_ACCESS_CTRL_BASE_IDX 2 512 #define mmDMCU_ERAM_WR_CTRL 0x00e3 513 #define mmDMCU_ERAM_WR_CTRL_BASE_IDX 2 514 #define mmDMCU_ERAM_WR_DATA 0x00e4 515 #define mmDMCU_ERAM_WR_DATA_BASE_IDX 2 516 #define mmDMCU_ERAM_RD_CTRL 0x00e5 517 #define mmDMCU_ERAM_RD_CTRL_BASE_IDX 2 518 #define mmDMCU_ERAM_RD_DATA 0x00e6 519 #define mmDMCU_ERAM_RD_DATA_BASE_IDX 2 520 #define mmDMCU_IRAM_WR_CTRL 0x00e7 521 #define mmDMCU_IRAM_WR_CTRL_BASE_IDX 2 522 #define mmDMCU_IRAM_WR_DATA 0x00e8 523 #define mmDMCU_IRAM_WR_DATA_BASE_IDX 2 524 #define mmDMCU_IRAM_RD_CTRL 0x00e9 525 #define mmDMCU_IRAM_RD_CTRL_BASE_IDX 2 526 #define mmDMCU_IRAM_RD_DATA 0x00ea 527 #define mmDMCU_IRAM_RD_DATA_BASE_IDX 2 528 #define mmDMCU_EVENT_TRIGGER 0x00eb 529 #define mmDMCU_EVENT_TRIGGER_BASE_IDX 2 530 #define mmDMCU_UC_INTERNAL_INT_STATUS 0x00ec 531 #define mmDMCU_UC_INTERNAL_INT_STATUS_BASE_IDX 2 532 #define mmDMCU_SS_INTERRUPT_CNTL_STATUS 0x00ed 533 #define mmDMCU_SS_INTERRUPT_CNTL_STATUS_BASE_IDX 2 534 #define mmDMCU_INTERRUPT_STATUS 0x00ee 535 #define mmDMCU_INTERRUPT_STATUS_BASE_IDX 2 536 #define mmDMCU_INTERRUPT_STATUS_1 0x00ef 537 #define mmDMCU_INTERRUPT_STATUS_1_BASE_IDX 2 538 #define mmDMCU_INTERRUPT_TO_HOST_EN_MASK 0x00f0 539 #define mmDMCU_INTERRUPT_TO_HOST_EN_MASK_BASE_IDX 2 540 #define mmDMCU_INTERRUPT_TO_UC_EN_MASK 0x00f1 541 #define mmDMCU_INTERRUPT_TO_UC_EN_MASK_BASE_IDX 2 542 #define mmDMCU_INTERRUPT_TO_UC_EN_MASK_1 0x00f2 543 #define mmDMCU_INTERRUPT_TO_UC_EN_MASK_1_BASE_IDX 2 544 #define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL 0x00f3 545 #define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_BASE_IDX 2 546 #define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1 0x00f4 547 #define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1_BASE_IDX 2 548 #define mmDC_DMCU_SCRATCH 0x00f5 549 #define mmDC_DMCU_SCRATCH_BASE_IDX 2 550 #define mmDMCU_INT_CNT 0x00f6 551 #define mmDMCU_INT_CNT_BASE_IDX 2 552 #define mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS 0x00f7 553 #define mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS_BASE_IDX 2 554 #define mmDMCU_UC_CLK_GATING_CNTL 0x00f8 555 #define mmDMCU_UC_CLK_GATING_CNTL_BASE_IDX 2 556 #define mmMASTER_COMM_DATA_REG1 0x00f9 557 #define mmMASTER_COMM_DATA_REG1_BASE_IDX 2 558 #define mmMASTER_COMM_DATA_REG2 0x00fa 559 #define mmMASTER_COMM_DATA_REG2_BASE_IDX 2 560 #define mmMASTER_COMM_DATA_REG3 0x00fb 561 #define mmMASTER_COMM_DATA_REG3_BASE_IDX 2 562 #define mmMASTER_COMM_CMD_REG 0x00fc 563 #define mmMASTER_COMM_CMD_REG_BASE_IDX 2 564 #define mmMASTER_COMM_CNTL_REG 0x00fd 565 #define mmMASTER_COMM_CNTL_REG_BASE_IDX 2 566 #define mmSLAVE_COMM_DATA_REG1 0x00fe 567 #define mmSLAVE_COMM_DATA_REG1_BASE_IDX 2 568 #define mmSLAVE_COMM_DATA_REG2 0x00ff 569 #define mmSLAVE_COMM_DATA_REG2_BASE_IDX 2 570 #define mmSLAVE_COMM_DATA_REG3 0x0100 571 #define mmSLAVE_COMM_DATA_REG3_BASE_IDX 2 572 #define mmSLAVE_COMM_CMD_REG 0x0101 573 #define mmSLAVE_COMM_CMD_REG_BASE_IDX 2 574 #define mmSLAVE_COMM_CNTL_REG 0x0102 575 #define mmSLAVE_COMM_CNTL_REG_BASE_IDX 2 576 #define mmDMCU_PERFMON_INTERRUPT_STATUS1 0x0105 577 #define mmDMCU_PERFMON_INTERRUPT_STATUS1_BASE_IDX 2 578 #define mmDMCU_PERFMON_INTERRUPT_STATUS2 0x0106 579 #define mmDMCU_PERFMON_INTERRUPT_STATUS2_BASE_IDX 2 580 #define mmDMCU_PERFMON_INTERRUPT_STATUS3 0x0107 581 #define mmDMCU_PERFMON_INTERRUPT_STATUS3_BASE_IDX 2 582 #define mmDMCU_PERFMON_INTERRUPT_STATUS4 0x0108 583 #define mmDMCU_PERFMON_INTERRUPT_STATUS4_BASE_IDX 2 584 #define mmDMCU_PERFMON_INTERRUPT_STATUS5 0x0109 585 #define mmDMCU_PERFMON_INTERRUPT_STATUS5_BASE_IDX 2 586 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1 0x010a 587 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1_BASE_IDX 2 588 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2 0x010b 589 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2_BASE_IDX 2 590 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3 0x010c 591 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3_BASE_IDX 2 592 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4 0x010d 593 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4_BASE_IDX 2 594 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5 0x010e 595 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5_BASE_IDX 2 596 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 0x010f 597 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1_BASE_IDX 2 598 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2 0x0110 599 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2_BASE_IDX 2 600 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3 0x0111 601 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3_BASE_IDX 2 602 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4 0x0112 603 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4_BASE_IDX 2 604 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5 0x0113 605 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5_BASE_IDX 2 606 #define mmDMCU_DPRX_INTERRUPT_STATUS1 0x0114 607 #define mmDMCU_DPRX_INTERRUPT_STATUS1_BASE_IDX 2 608 #define mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1 0x0115 609 #define mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1_BASE_IDX 2 610 #define mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 0x0116 611 #define mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1_BASE_IDX 2 612 #define mmDMCU_INTERRUPT_STATUS_CONTINUE 0x0119 613 #define mmDMCU_INTERRUPT_STATUS_CONTINUE_BASE_IDX 2 614 #define mmDMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE 0x011a 615 #define mmDMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE_BASE_IDX 2 616 #define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE 0x011b 617 #define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE_BASE_IDX 2 618 #define mmDMCU_INT_CNT_CONTINUE 0x011c 619 #define mmDMCU_INT_CNT_CONTINUE_BASE_IDX 2 620 #define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2 0x011d 621 #define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2_BASE_IDX 2 622 #define mmDMCU_INTERRUPT_STATUS_2 0x011e 623 #define mmDMCU_INTERRUPT_STATUS_2_BASE_IDX 2 624 #define mmDMCU_INTERRUPT_TO_UC_EN_MASK_2 0x011f 625 #define mmDMCU_INTERRUPT_TO_UC_EN_MASK_2_BASE_IDX 2 626 #define mmDMCU_INT_CNT_CONT2 0x0120 627 #define mmDMCU_INT_CNT_CONT2_BASE_IDX 2 628 #define mmDMCU_INT_CNT_CONT3 0x0121 629 #define mmDMCU_INT_CNT_CONT3_BASE_IDX 2 630 #define mmDMCU_INT_CNT_CONT4 0x0122 631 #define mmDMCU_INT_CNT_CONT4_BASE_IDX 2 632 #define mmDMCU_INT_CNT_CONT5 0x0123 633 #define mmDMCU_INT_CNT_CONT5_BASE_IDX 2 634 635 636 // addressBlock: dce_dc_dmu_ihc_dispdec 637 // base address: 0x0 638 #define mmDC_GPU_TIMER_START_POSITION_V_UPDATE 0x0126 639 #define mmDC_GPU_TIMER_START_POSITION_V_UPDATE_BASE_IDX 2 640 #define mmDC_GPU_TIMER_START_POSITION_VSTARTUP 0x0127 641 #define mmDC_GPU_TIMER_START_POSITION_VSTARTUP_BASE_IDX 2 642 #define mmDC_GPU_TIMER_READ 0x0128 643 #define mmDC_GPU_TIMER_READ_BASE_IDX 2 644 #define mmDC_GPU_TIMER_READ_CNTL 0x0129 645 #define mmDC_GPU_TIMER_READ_CNTL_BASE_IDX 2 646 #define mmDISP_INTERRUPT_STATUS 0x012a 647 #define mmDISP_INTERRUPT_STATUS_BASE_IDX 2 648 #define mmDISP_INTERRUPT_STATUS_CONTINUE 0x012b 649 #define mmDISP_INTERRUPT_STATUS_CONTINUE_BASE_IDX 2 650 #define mmDISP_INTERRUPT_STATUS_CONTINUE2 0x012c 651 #define mmDISP_INTERRUPT_STATUS_CONTINUE2_BASE_IDX 2 652 #define mmDISP_INTERRUPT_STATUS_CONTINUE3 0x012d 653 #define mmDISP_INTERRUPT_STATUS_CONTINUE3_BASE_IDX 2 654 #define mmDISP_INTERRUPT_STATUS_CONTINUE4 0x012e 655 #define mmDISP_INTERRUPT_STATUS_CONTINUE4_BASE_IDX 2 656 #define mmDISP_INTERRUPT_STATUS_CONTINUE5 0x012f 657 #define mmDISP_INTERRUPT_STATUS_CONTINUE5_BASE_IDX 2 658 #define mmDISP_INTERRUPT_STATUS_CONTINUE6 0x0130 659 #define mmDISP_INTERRUPT_STATUS_CONTINUE6_BASE_IDX 2 660 #define mmDISP_INTERRUPT_STATUS_CONTINUE7 0x0131 661 #define mmDISP_INTERRUPT_STATUS_CONTINUE7_BASE_IDX 2 662 #define mmDISP_INTERRUPT_STATUS_CONTINUE8 0x0132 663 #define mmDISP_INTERRUPT_STATUS_CONTINUE8_BASE_IDX 2 664 #define mmDISP_INTERRUPT_STATUS_CONTINUE9 0x0133 665 #define mmDISP_INTERRUPT_STATUS_CONTINUE9_BASE_IDX 2 666 #define mmDISP_INTERRUPT_STATUS_CONTINUE10 0x0134 667 #define mmDISP_INTERRUPT_STATUS_CONTINUE10_BASE_IDX 2 668 #define mmDISP_INTERRUPT_STATUS_CONTINUE11 0x0135 669 #define mmDISP_INTERRUPT_STATUS_CONTINUE11_BASE_IDX 2 670 #define mmDISP_INTERRUPT_STATUS_CONTINUE12 0x0136 671 #define mmDISP_INTERRUPT_STATUS_CONTINUE12_BASE_IDX 2 672 #define mmDISP_INTERRUPT_STATUS_CONTINUE13 0x0137 673 #define mmDISP_INTERRUPT_STATUS_CONTINUE13_BASE_IDX 2 674 #define mmDISP_INTERRUPT_STATUS_CONTINUE14 0x0138 675 #define mmDISP_INTERRUPT_STATUS_CONTINUE14_BASE_IDX 2 676 #define mmDISP_INTERRUPT_STATUS_CONTINUE15 0x0139 677 #define mmDISP_INTERRUPT_STATUS_CONTINUE15_BASE_IDX 2 678 #define mmDISP_INTERRUPT_STATUS_CONTINUE16 0x013a 679 #define mmDISP_INTERRUPT_STATUS_CONTINUE16_BASE_IDX 2 680 #define mmDISP_INTERRUPT_STATUS_CONTINUE17 0x013b 681 #define mmDISP_INTERRUPT_STATUS_CONTINUE17_BASE_IDX 2 682 #define mmDISP_INTERRUPT_STATUS_CONTINUE18 0x013c 683 #define mmDISP_INTERRUPT_STATUS_CONTINUE18_BASE_IDX 2 684 #define mmDISP_INTERRUPT_STATUS_CONTINUE19 0x013d 685 #define mmDISP_INTERRUPT_STATUS_CONTINUE19_BASE_IDX 2 686 #define mmDISP_INTERRUPT_STATUS_CONTINUE20 0x013e 687 #define mmDISP_INTERRUPT_STATUS_CONTINUE20_BASE_IDX 2 688 #define mmDISP_INTERRUPT_STATUS_CONTINUE21 0x013f 689 #define mmDISP_INTERRUPT_STATUS_CONTINUE21_BASE_IDX 2 690 #define mmDISP_INTERRUPT_STATUS_CONTINUE22 0x0140 691 #define mmDISP_INTERRUPT_STATUS_CONTINUE22_BASE_IDX 2 692 #define mmDC_GPU_TIMER_START_POSITION_VREADY 0x0141 693 #define mmDC_GPU_TIMER_START_POSITION_VREADY_BASE_IDX 2 694 #define mmDC_GPU_TIMER_START_POSITION_FLIP 0x0142 695 #define mmDC_GPU_TIMER_START_POSITION_FLIP_BASE_IDX 2 696 #define mmDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK 0x0143 697 #define mmDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK_BASE_IDX 2 698 #define mmDC_GPU_TIMER_START_POSITION_FLIP_AWAY 0x0144 699 #define mmDC_GPU_TIMER_START_POSITION_FLIP_AWAY_BASE_IDX 2 700 #define mmDISP_INTERRUPT_STATUS_CONTINUE23 0x0145 701 #define mmDISP_INTERRUPT_STATUS_CONTINUE23_BASE_IDX 2 702 #define mmDISP_INTERRUPT_STATUS_CONTINUE24 0x0146 703 #define mmDISP_INTERRUPT_STATUS_CONTINUE24_BASE_IDX 2 704 #define mmDISP_INTERRUPT_STATUS_CONTINUE25 0x0147 705 #define mmDISP_INTERRUPT_STATUS_CONTINUE25_BASE_IDX 2 706 #define mmDCCG_INTERRUPT_DEST 0x0148 707 #define mmDCCG_INTERRUPT_DEST_BASE_IDX 2 708 #define mmDMU_INTERRUPT_DEST 0x0149 709 #define mmDMU_INTERRUPT_DEST_BASE_IDX 2 710 #define mmDMU_INTERRUPT_DEST2 0x014a 711 #define mmDMU_INTERRUPT_DEST2_BASE_IDX 2 712 #define mmDCPG_INTERRUPT_DEST 0x014b 713 #define mmDCPG_INTERRUPT_DEST_BASE_IDX 2 714 #define mmDCPG_INTERRUPT_DEST2 0x014c 715 #define mmDCPG_INTERRUPT_DEST2_BASE_IDX 2 716 #define mmMMHUBBUB_INTERRUPT_DEST 0x014d 717 #define mmMMHUBBUB_INTERRUPT_DEST_BASE_IDX 2 718 #define mmWB_INTERRUPT_DEST 0x014e 719 #define mmWB_INTERRUPT_DEST_BASE_IDX 2 720 #define mmDCHUB_INTERRUPT_DEST 0x014f 721 #define mmDCHUB_INTERRUPT_DEST_BASE_IDX 2 722 #define mmDCHUB_PERFCOUNTER_INTERRUPT_DEST 0x0150 723 #define mmDCHUB_PERFCOUNTER_INTERRUPT_DEST_BASE_IDX 2 724 #define mmDCHUB_INTERRUPT_DEST2 0x0151 725 #define mmDCHUB_INTERRUPT_DEST2_BASE_IDX 2 726 #define mmDPP_PERFCOUNTER_INTERRUPT_DEST 0x0152 727 #define mmDPP_PERFCOUNTER_INTERRUPT_DEST_BASE_IDX 2 728 #define mmMPC_INTERRUPT_DEST 0x0153 729 #define mmMPC_INTERRUPT_DEST_BASE_IDX 2 730 #define mmOPP_INTERRUPT_DEST 0x0154 731 #define mmOPP_INTERRUPT_DEST_BASE_IDX 2 732 #define mmOPTC_INTERRUPT_DEST 0x0155 733 #define mmOPTC_INTERRUPT_DEST_BASE_IDX 2 734 #define mmOTG0_INTERRUPT_DEST 0x0156 735 #define mmOTG0_INTERRUPT_DEST_BASE_IDX 2 736 #define mmOTG1_INTERRUPT_DEST 0x0157 737 #define mmOTG1_INTERRUPT_DEST_BASE_IDX 2 738 #define mmOTG2_INTERRUPT_DEST 0x0158 739 #define mmOTG2_INTERRUPT_DEST_BASE_IDX 2 740 #define mmOTG3_INTERRUPT_DEST 0x0159 741 #define mmOTG3_INTERRUPT_DEST_BASE_IDX 2 742 #define mmOTG4_INTERRUPT_DEST 0x015a 743 #define mmOTG4_INTERRUPT_DEST_BASE_IDX 2 744 #define mmOTG5_INTERRUPT_DEST 0x015b 745 #define mmOTG5_INTERRUPT_DEST_BASE_IDX 2 746 #define mmDIG_INTERRUPT_DEST 0x015c 747 #define mmDIG_INTERRUPT_DEST_BASE_IDX 2 748 #define mmI2C_DDC_HPD_INTERRUPT_DEST 0x015d 749 #define mmI2C_DDC_HPD_INTERRUPT_DEST_BASE_IDX 2 750 #define mmDIO_INTERRUPT_DEST 0x015f 751 #define mmDIO_INTERRUPT_DEST_BASE_IDX 2 752 #define mmDCIO_INTERRUPT_DEST 0x0160 753 #define mmDCIO_INTERRUPT_DEST_BASE_IDX 2 754 #define mmHPD_INTERRUPT_DEST 0x0161 755 #define mmHPD_INTERRUPT_DEST_BASE_IDX 2 756 #define mmAZ_INTERRUPT_DEST 0x0162 757 #define mmAZ_INTERRUPT_DEST_BASE_IDX 2 758 #define mmAUX_INTERRUPT_DEST 0x0163 759 #define mmAUX_INTERRUPT_DEST_BASE_IDX 2 760 #define mmDSC_INTERRUPT_DEST 0x0164 761 #define mmDSC_INTERRUPT_DEST_BASE_IDX 2 762 763 764 // addressBlock: dce_dc_dmu_fgsec_dispdec 765 // base address: 0x0 766 #define mmDMCUB_RBBMIF_SEC_CNTL 0x017a 767 #define mmDMCUB_RBBMIF_SEC_CNTL_BASE_IDX 2 768 769 770 // addressBlock: dce_dc_dmu_rbbmif_dispdec 771 // base address: 0x0 772 #define mmRBBMIF_TIMEOUT 0x017f 773 #define mmRBBMIF_TIMEOUT_BASE_IDX 2 774 #define mmRBBMIF_STATUS 0x0180 775 #define mmRBBMIF_STATUS_BASE_IDX 2 776 #define mmRBBMIF_STATUS_2 0x0181 777 #define mmRBBMIF_STATUS_2_BASE_IDX 2 778 #define mmRBBMIF_INT_STATUS 0x0182 779 #define mmRBBMIF_INT_STATUS_BASE_IDX 2 780 #define mmRBBMIF_TIMEOUT_DIS 0x0183 781 #define mmRBBMIF_TIMEOUT_DIS_BASE_IDX 2 782 #define mmRBBMIF_TIMEOUT_DIS_2 0x0184 783 #define mmRBBMIF_TIMEOUT_DIS_2_BASE_IDX 2 784 #define mmRBBMIF_STATUS_FLAG 0x0185 785 #define mmRBBMIF_STATUS_FLAG_BASE_IDX 2 786 787 788 // addressBlock: dce_dc_dmu_dmcub_dispdec 789 // base address: 0x0 790 #define mmDMCUB_REGION0_OFFSET 0x018e 791 #define mmDMCUB_REGION0_OFFSET_BASE_IDX 2 792 #define mmDMCUB_REGION0_OFFSET_HIGH 0x018f 793 #define mmDMCUB_REGION0_OFFSET_HIGH_BASE_IDX 2 794 #define mmDMCUB_REGION1_OFFSET 0x0190 795 #define mmDMCUB_REGION1_OFFSET_BASE_IDX 2 796 #define mmDMCUB_REGION1_OFFSET_HIGH 0x0191 797 #define mmDMCUB_REGION1_OFFSET_HIGH_BASE_IDX 2 798 #define mmDMCUB_REGION2_OFFSET 0x0192 799 #define mmDMCUB_REGION2_OFFSET_BASE_IDX 2 800 #define mmDMCUB_REGION2_OFFSET_HIGH 0x0193 801 #define mmDMCUB_REGION2_OFFSET_HIGH_BASE_IDX 2 802 #define mmDMCUB_REGION4_OFFSET 0x0196 803 #define mmDMCUB_REGION4_OFFSET_BASE_IDX 2 804 #define mmDMCUB_REGION4_OFFSET_HIGH 0x0197 805 #define mmDMCUB_REGION4_OFFSET_HIGH_BASE_IDX 2 806 #define mmDMCUB_REGION5_OFFSET 0x0198 807 #define mmDMCUB_REGION5_OFFSET_BASE_IDX 2 808 #define mmDMCUB_REGION5_OFFSET_HIGH 0x0199 809 #define mmDMCUB_REGION5_OFFSET_HIGH_BASE_IDX 2 810 #define mmDMCUB_REGION6_OFFSET 0x019a 811 #define mmDMCUB_REGION6_OFFSET_BASE_IDX 2 812 #define mmDMCUB_REGION6_OFFSET_HIGH 0x019b 813 #define mmDMCUB_REGION6_OFFSET_HIGH_BASE_IDX 2 814 #define mmDMCUB_REGION7_OFFSET 0x019c 815 #define mmDMCUB_REGION7_OFFSET_BASE_IDX 2 816 #define mmDMCUB_REGION7_OFFSET_HIGH 0x019d 817 #define mmDMCUB_REGION7_OFFSET_HIGH_BASE_IDX 2 818 #define mmDMCUB_REGION0_TOP_ADDRESS 0x019e 819 #define mmDMCUB_REGION0_TOP_ADDRESS_BASE_IDX 2 820 #define mmDMCUB_REGION1_TOP_ADDRESS 0x019f 821 #define mmDMCUB_REGION1_TOP_ADDRESS_BASE_IDX 2 822 #define mmDMCUB_REGION2_TOP_ADDRESS 0x01a0 823 #define mmDMCUB_REGION2_TOP_ADDRESS_BASE_IDX 2 824 #define mmDMCUB_REGION4_TOP_ADDRESS 0x01a1 825 #define mmDMCUB_REGION4_TOP_ADDRESS_BASE_IDX 2 826 #define mmDMCUB_REGION5_TOP_ADDRESS 0x01a2 827 #define mmDMCUB_REGION5_TOP_ADDRESS_BASE_IDX 2 828 #define mmDMCUB_REGION6_TOP_ADDRESS 0x01a3 829 #define mmDMCUB_REGION6_TOP_ADDRESS_BASE_IDX 2 830 #define mmDMCUB_REGION7_TOP_ADDRESS 0x01a4 831 #define mmDMCUB_REGION7_TOP_ADDRESS_BASE_IDX 2 832 #define mmDMCUB_REGION3_CW0_BASE_ADDRESS 0x01a5 833 #define mmDMCUB_REGION3_CW0_BASE_ADDRESS_BASE_IDX 2 834 #define mmDMCUB_REGION3_CW1_BASE_ADDRESS 0x01a6 835 #define mmDMCUB_REGION3_CW1_BASE_ADDRESS_BASE_IDX 2 836 #define mmDMCUB_REGION3_CW2_BASE_ADDRESS 0x01a7 837 #define mmDMCUB_REGION3_CW2_BASE_ADDRESS_BASE_IDX 2 838 #define mmDMCUB_REGION3_CW3_BASE_ADDRESS 0x01a8 839 #define mmDMCUB_REGION3_CW3_BASE_ADDRESS_BASE_IDX 2 840 #define mmDMCUB_REGION3_CW4_BASE_ADDRESS 0x01a9 841 #define mmDMCUB_REGION3_CW4_BASE_ADDRESS_BASE_IDX 2 842 #define mmDMCUB_REGION3_CW5_BASE_ADDRESS 0x01aa 843 #define mmDMCUB_REGION3_CW5_BASE_ADDRESS_BASE_IDX 2 844 #define mmDMCUB_REGION3_CW6_BASE_ADDRESS 0x01ab 845 #define mmDMCUB_REGION3_CW6_BASE_ADDRESS_BASE_IDX 2 846 #define mmDMCUB_REGION3_CW7_BASE_ADDRESS 0x01ac 847 #define mmDMCUB_REGION3_CW7_BASE_ADDRESS_BASE_IDX 2 848 #define mmDMCUB_REGION3_CW0_TOP_ADDRESS 0x01ad 849 #define mmDMCUB_REGION3_CW0_TOP_ADDRESS_BASE_IDX 2 850 #define mmDMCUB_REGION3_CW1_TOP_ADDRESS 0x01ae 851 #define mmDMCUB_REGION3_CW1_TOP_ADDRESS_BASE_IDX 2 852 #define mmDMCUB_REGION3_CW2_TOP_ADDRESS 0x01af 853 #define mmDMCUB_REGION3_CW2_TOP_ADDRESS_BASE_IDX 2 854 #define mmDMCUB_REGION3_CW3_TOP_ADDRESS 0x01b0 855 #define mmDMCUB_REGION3_CW3_TOP_ADDRESS_BASE_IDX 2 856 #define mmDMCUB_REGION3_CW4_TOP_ADDRESS 0x01b1 857 #define mmDMCUB_REGION3_CW4_TOP_ADDRESS_BASE_IDX 2 858 #define mmDMCUB_REGION3_CW5_TOP_ADDRESS 0x01b2 859 #define mmDMCUB_REGION3_CW5_TOP_ADDRESS_BASE_IDX 2 860 #define mmDMCUB_REGION3_CW6_TOP_ADDRESS 0x01b3 861 #define mmDMCUB_REGION3_CW6_TOP_ADDRESS_BASE_IDX 2 862 #define mmDMCUB_REGION3_CW7_TOP_ADDRESS 0x01b4 863 #define mmDMCUB_REGION3_CW7_TOP_ADDRESS_BASE_IDX 2 864 #define mmDMCUB_REGION3_CW0_OFFSET 0x01b5 865 #define mmDMCUB_REGION3_CW0_OFFSET_BASE_IDX 2 866 #define mmDMCUB_REGION3_CW0_OFFSET_HIGH 0x01b6 867 #define mmDMCUB_REGION3_CW0_OFFSET_HIGH_BASE_IDX 2 868 #define mmDMCUB_REGION3_CW1_OFFSET 0x01b7 869 #define mmDMCUB_REGION3_CW1_OFFSET_BASE_IDX 2 870 #define mmDMCUB_REGION3_CW1_OFFSET_HIGH 0x01b8 871 #define mmDMCUB_REGION3_CW1_OFFSET_HIGH_BASE_IDX 2 872 #define mmDMCUB_REGION3_CW2_OFFSET 0x01b9 873 #define mmDMCUB_REGION3_CW2_OFFSET_BASE_IDX 2 874 #define mmDMCUB_REGION3_CW2_OFFSET_HIGH 0x01ba 875 #define mmDMCUB_REGION3_CW2_OFFSET_HIGH_BASE_IDX 2 876 #define mmDMCUB_REGION3_CW3_OFFSET 0x01bb 877 #define mmDMCUB_REGION3_CW3_OFFSET_BASE_IDX 2 878 #define mmDMCUB_REGION3_CW3_OFFSET_HIGH 0x01bc 879 #define mmDMCUB_REGION3_CW3_OFFSET_HIGH_BASE_IDX 2 880 #define mmDMCUB_REGION3_CW4_OFFSET 0x01bd 881 #define mmDMCUB_REGION3_CW4_OFFSET_BASE_IDX 2 882 #define mmDMCUB_REGION3_CW4_OFFSET_HIGH 0x01be 883 #define mmDMCUB_REGION3_CW4_OFFSET_HIGH_BASE_IDX 2 884 #define mmDMCUB_REGION3_CW5_OFFSET 0x01bf 885 #define mmDMCUB_REGION3_CW5_OFFSET_BASE_IDX 2 886 #define mmDMCUB_REGION3_CW5_OFFSET_HIGH 0x01c0 887 #define mmDMCUB_REGION3_CW5_OFFSET_HIGH_BASE_IDX 2 888 #define mmDMCUB_REGION3_CW6_OFFSET 0x01c1 889 #define mmDMCUB_REGION3_CW6_OFFSET_BASE_IDX 2 890 #define mmDMCUB_REGION3_CW6_OFFSET_HIGH 0x01c2 891 #define mmDMCUB_REGION3_CW6_OFFSET_HIGH_BASE_IDX 2 892 #define mmDMCUB_REGION3_CW7_OFFSET 0x01c3 893 #define mmDMCUB_REGION3_CW7_OFFSET_BASE_IDX 2 894 #define mmDMCUB_REGION3_CW7_OFFSET_HIGH 0x01c4 895 #define mmDMCUB_REGION3_CW7_OFFSET_HIGH_BASE_IDX 2 896 #define mmDMCUB_INTERRUPT_ENABLE 0x01c5 897 #define mmDMCUB_INTERRUPT_ENABLE_BASE_IDX 2 898 #define mmDMCUB_INTERRUPT_ACK 0x01c6 899 #define mmDMCUB_INTERRUPT_ACK_BASE_IDX 2 900 #define mmDMCUB_INTERRUPT_STATUS 0x01c7 901 #define mmDMCUB_INTERRUPT_STATUS_BASE_IDX 2 902 #define mmDMCUB_INTERRUPT_TYPE 0x01c8 903 #define mmDMCUB_INTERRUPT_TYPE_BASE_IDX 2 904 #define mmDMCUB_EXT_INTERRUPT_STATUS 0x01c9 905 #define mmDMCUB_EXT_INTERRUPT_STATUS_BASE_IDX 2 906 #define mmDMCUB_EXT_INTERRUPT_CTXID 0x01ca 907 #define mmDMCUB_EXT_INTERRUPT_CTXID_BASE_IDX 2 908 #define mmDMCUB_EXT_INTERRUPT_ACK 0x01cb 909 #define mmDMCUB_EXT_INTERRUPT_ACK_BASE_IDX 2 910 #define mmDMCUB_INST_FETCH_FAULT_ADDR 0x01cc 911 #define mmDMCUB_INST_FETCH_FAULT_ADDR_BASE_IDX 2 912 #define mmDMCUB_DATA_WRITE_FAULT_ADDR 0x01cd 913 #define mmDMCUB_DATA_WRITE_FAULT_ADDR_BASE_IDX 2 914 #define mmDMCUB_SEC_CNTL 0x01ce 915 #define mmDMCUB_SEC_CNTL_BASE_IDX 2 916 #define mmDMCUB_MEM_CNTL 0x01cf 917 #define mmDMCUB_MEM_CNTL_BASE_IDX 2 918 #define mmDMCUB_INBOX0_BASE_ADDRESS 0x01d0 919 #define mmDMCUB_INBOX0_BASE_ADDRESS_BASE_IDX 2 920 #define mmDMCUB_INBOX0_SIZE 0x01d1 921 #define mmDMCUB_INBOX0_SIZE_BASE_IDX 2 922 #define mmDMCUB_INBOX0_WPTR 0x01d2 923 #define mmDMCUB_INBOX0_WPTR_BASE_IDX 2 924 #define mmDMCUB_INBOX0_RPTR 0x01d3 925 #define mmDMCUB_INBOX0_RPTR_BASE_IDX 2 926 #define mmDMCUB_INBOX1_BASE_ADDRESS 0x01d4 927 #define mmDMCUB_INBOX1_BASE_ADDRESS_BASE_IDX 2 928 #define mmDMCUB_INBOX1_SIZE 0x01d5 929 #define mmDMCUB_INBOX1_SIZE_BASE_IDX 2 930 #define mmDMCUB_INBOX1_WPTR 0x01d6 931 #define mmDMCUB_INBOX1_WPTR_BASE_IDX 2 932 #define mmDMCUB_INBOX1_RPTR 0x01d7 933 #define mmDMCUB_INBOX1_RPTR_BASE_IDX 2 934 #define mmDMCUB_OUTBOX0_BASE_ADDRESS 0x01d8 935 #define mmDMCUB_OUTBOX0_BASE_ADDRESS_BASE_IDX 2 936 #define mmDMCUB_OUTBOX0_SIZE 0x01d9 937 #define mmDMCUB_OUTBOX0_SIZE_BASE_IDX 2 938 #define mmDMCUB_OUTBOX0_WPTR 0x01da 939 #define mmDMCUB_OUTBOX0_WPTR_BASE_IDX 2 940 #define mmDMCUB_OUTBOX0_RPTR 0x01db 941 #define mmDMCUB_OUTBOX0_RPTR_BASE_IDX 2 942 #define mmDMCUB_OUTBOX1_BASE_ADDRESS 0x01dc 943 #define mmDMCUB_OUTBOX1_BASE_ADDRESS_BASE_IDX 2 944 #define mmDMCUB_OUTBOX1_SIZE 0x01dd 945 #define mmDMCUB_OUTBOX1_SIZE_BASE_IDX 2 946 #define mmDMCUB_OUTBOX1_WPTR 0x01de 947 #define mmDMCUB_OUTBOX1_WPTR_BASE_IDX 2 948 #define mmDMCUB_OUTBOX1_RPTR 0x01df 949 #define mmDMCUB_OUTBOX1_RPTR_BASE_IDX 2 950 #define mmDMCUB_TIMER_TRIGGER0 0x01e0 951 #define mmDMCUB_TIMER_TRIGGER0_BASE_IDX 2 952 #define mmDMCUB_TIMER_TRIGGER1 0x01e1 953 #define mmDMCUB_TIMER_TRIGGER1_BASE_IDX 2 954 #define mmDMCUB_TIMER_WINDOW 0x01e2 955 #define mmDMCUB_TIMER_WINDOW_BASE_IDX 2 956 #define mmDMCUB_SCRATCH0 0x01e3 957 #define mmDMCUB_SCRATCH0_BASE_IDX 2 958 #define mmDMCUB_SCRATCH1 0x01e4 959 #define mmDMCUB_SCRATCH1_BASE_IDX 2 960 #define mmDMCUB_SCRATCH2 0x01e5 961 #define mmDMCUB_SCRATCH2_BASE_IDX 2 962 #define mmDMCUB_SCRATCH3 0x01e6 963 #define mmDMCUB_SCRATCH3_BASE_IDX 2 964 #define mmDMCUB_SCRATCH4 0x01e7 965 #define mmDMCUB_SCRATCH4_BASE_IDX 2 966 #define mmDMCUB_SCRATCH5 0x01e8 967 #define mmDMCUB_SCRATCH5_BASE_IDX 2 968 #define mmDMCUB_SCRATCH6 0x01e9 969 #define mmDMCUB_SCRATCH6_BASE_IDX 2 970 #define mmDMCUB_SCRATCH7 0x01ea 971 #define mmDMCUB_SCRATCH7_BASE_IDX 2 972 #define mmDMCUB_SCRATCH8 0x01eb 973 #define mmDMCUB_SCRATCH8_BASE_IDX 2 974 #define mmDMCUB_SCRATCH9 0x01ec 975 #define mmDMCUB_SCRATCH9_BASE_IDX 2 976 #define mmDMCUB_SCRATCH10 0x01ed 977 #define mmDMCUB_SCRATCH10_BASE_IDX 2 978 #define mmDMCUB_SCRATCH11 0x01ee 979 #define mmDMCUB_SCRATCH11_BASE_IDX 2 980 #define mmDMCUB_SCRATCH12 0x01ef 981 #define mmDMCUB_SCRATCH12_BASE_IDX 2 982 #define mmDMCUB_SCRATCH13 0x01f0 983 #define mmDMCUB_SCRATCH13_BASE_IDX 2 984 #define mmDMCUB_SCRATCH14 0x01f1 985 #define mmDMCUB_SCRATCH14_BASE_IDX 2 986 #define mmDMCUB_SCRATCH15 0x01f2 987 #define mmDMCUB_SCRATCH15_BASE_IDX 2 988 #define mmDMCUB_CNTL 0x01f6 989 #define mmDMCUB_CNTL_BASE_IDX 2 990 #define mmDMCUB_GPINT_DATAIN0 0x01f7 991 #define mmDMCUB_GPINT_DATAIN0_BASE_IDX 2 992 #define mmDMCUB_GPINT_DATAIN1 0x01f8 993 #define mmDMCUB_GPINT_DATAIN1_BASE_IDX 2 994 #define mmDMCUB_GPINT_DATAOUT 0x01f9 995 #define mmDMCUB_GPINT_DATAOUT_BASE_IDX 2 996 #define mmDMCUB_UNDEFINED_ADDRESS_FAULT_ADDR 0x01fa 997 #define mmDMCUB_UNDEFINED_ADDRESS_FAULT_ADDR_BASE_IDX 2 998 #define mmDMCUB_LS_WAKE_INT_ENABLE 0x01fb 999 #define mmDMCUB_LS_WAKE_INT_ENABLE_BASE_IDX 2 1000 #define mmDMCUB_MEM_PWR_CNTL 0x01fc 1001 #define mmDMCUB_MEM_PWR_CNTL_BASE_IDX 2 1002 #define mmDMCUB_TIMER_CURRENT 0x01fd 1003 #define mmDMCUB_TIMER_CURRENT_BASE_IDX 2 1004 #define mmDMCUB_PROC_ID 0x01ff 1005 #define mmDMCUB_PROC_ID_BASE_IDX 2 1006 1007 1008 // addressBlock: dce_dc_mmhubbub_mcif_wb0_dispdec 1009 // base address: 0x0 1010 #define mmMCIF_WB_BUFMGR_SW_CONTROL 0x0272 1011 #define mmMCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX 2 1012 #define mmMCIF_WB_BUFMGR_STATUS 0x0274 1013 #define mmMCIF_WB_BUFMGR_STATUS_BASE_IDX 2 1014 #define mmMCIF_WB_BUF_PITCH 0x0275 1015 #define mmMCIF_WB_BUF_PITCH_BASE_IDX 2 1016 #define mmMCIF_WB_BUF_1_STATUS 0x0276 1017 #define mmMCIF_WB_BUF_1_STATUS_BASE_IDX 2 1018 #define mmMCIF_WB_BUF_1_STATUS2 0x0277 1019 #define mmMCIF_WB_BUF_1_STATUS2_BASE_IDX 2 1020 #define mmMCIF_WB_BUF_2_STATUS 0x0278 1021 #define mmMCIF_WB_BUF_2_STATUS_BASE_IDX 2 1022 #define mmMCIF_WB_BUF_2_STATUS2 0x0279 1023 #define mmMCIF_WB_BUF_2_STATUS2_BASE_IDX 2 1024 #define mmMCIF_WB_BUF_3_STATUS 0x027a 1025 #define mmMCIF_WB_BUF_3_STATUS_BASE_IDX 2 1026 #define mmMCIF_WB_BUF_3_STATUS2 0x027b 1027 #define mmMCIF_WB_BUF_3_STATUS2_BASE_IDX 2 1028 #define mmMCIF_WB_BUF_4_STATUS 0x027c 1029 #define mmMCIF_WB_BUF_4_STATUS_BASE_IDX 2 1030 #define mmMCIF_WB_BUF_4_STATUS2 0x027d 1031 #define mmMCIF_WB_BUF_4_STATUS2_BASE_IDX 2 1032 #define mmMCIF_WB_ARBITRATION_CONTROL 0x027e 1033 #define mmMCIF_WB_ARBITRATION_CONTROL_BASE_IDX 2 1034 #define mmMCIF_WB_SCLK_CHANGE 0x027f 1035 #define mmMCIF_WB_SCLK_CHANGE_BASE_IDX 2 1036 #define mmMCIF_WB_BUF_1_ADDR_Y 0x0282 1037 #define mmMCIF_WB_BUF_1_ADDR_Y_BASE_IDX 2 1038 #define mmMCIF_WB_BUF_1_ADDR_C 0x0284 1039 #define mmMCIF_WB_BUF_1_ADDR_C_BASE_IDX 2 1040 #define mmMCIF_WB_BUF_2_ADDR_Y 0x0286 1041 #define mmMCIF_WB_BUF_2_ADDR_Y_BASE_IDX 2 1042 #define mmMCIF_WB_BUF_2_ADDR_C 0x0288 1043 #define mmMCIF_WB_BUF_2_ADDR_C_BASE_IDX 2 1044 #define mmMCIF_WB_BUF_3_ADDR_Y 0x028a 1045 #define mmMCIF_WB_BUF_3_ADDR_Y_BASE_IDX 2 1046 #define mmMCIF_WB_BUF_3_ADDR_C 0x028c 1047 #define mmMCIF_WB_BUF_3_ADDR_C_BASE_IDX 2 1048 #define mmMCIF_WB_BUF_4_ADDR_Y 0x028e 1049 #define mmMCIF_WB_BUF_4_ADDR_Y_BASE_IDX 2 1050 #define mmMCIF_WB_BUF_4_ADDR_C 0x0290 1051 #define mmMCIF_WB_BUF_4_ADDR_C_BASE_IDX 2 1052 #define mmMCIF_WB_BUFMGR_VCE_CONTROL 0x0292 1053 #define mmMCIF_WB_BUFMGR_VCE_CONTROL_BASE_IDX 2 1054 #define mmMCIF_WB_NB_PSTATE_CONTROL 0x0293 1055 #define mmMCIF_WB_NB_PSTATE_CONTROL_BASE_IDX 2 1056 #define mmMCIF_WB_CLOCK_GATER_CONTROL 0x0294 1057 #define mmMCIF_WB_CLOCK_GATER_CONTROL_BASE_IDX 2 1058 #define mmMCIF_WB_SELF_REFRESH_CONTROL 0x0296 1059 #define mmMCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX 2 1060 #define mmMULTI_LEVEL_QOS_CTRL 0x0297 1061 #define mmMULTI_LEVEL_QOS_CTRL_BASE_IDX 2 1062 #define mmMCIF_WB_BUF_LUMA_SIZE 0x0299 1063 #define mmMCIF_WB_BUF_LUMA_SIZE_BASE_IDX 2 1064 #define mmMCIF_WB_BUF_CHROMA_SIZE 0x029a 1065 #define mmMCIF_WB_BUF_CHROMA_SIZE_BASE_IDX 2 1066 #define mmMCIF_WB_BUF_1_ADDR_Y_HIGH 0x029b 1067 #define mmMCIF_WB_BUF_1_ADDR_Y_HIGH_BASE_IDX 2 1068 #define mmMCIF_WB_BUF_1_ADDR_C_HIGH 0x029c 1069 #define mmMCIF_WB_BUF_1_ADDR_C_HIGH_BASE_IDX 2 1070 #define mmMCIF_WB_BUF_2_ADDR_Y_HIGH 0x029d 1071 #define mmMCIF_WB_BUF_2_ADDR_Y_HIGH_BASE_IDX 2 1072 #define mmMCIF_WB_BUF_2_ADDR_C_HIGH 0x029e 1073 #define mmMCIF_WB_BUF_2_ADDR_C_HIGH_BASE_IDX 2 1074 #define mmMCIF_WB_BUF_3_ADDR_Y_HIGH 0x029f 1075 #define mmMCIF_WB_BUF_3_ADDR_Y_HIGH_BASE_IDX 2 1076 #define mmMCIF_WB_BUF_3_ADDR_C_HIGH 0x02a0 1077 #define mmMCIF_WB_BUF_3_ADDR_C_HIGH_BASE_IDX 2 1078 #define mmMCIF_WB_BUF_4_ADDR_Y_HIGH 0x02a1 1079 #define mmMCIF_WB_BUF_4_ADDR_Y_HIGH_BASE_IDX 2 1080 #define mmMCIF_WB_BUF_4_ADDR_C_HIGH 0x02a2 1081 #define mmMCIF_WB_BUF_4_ADDR_C_HIGH_BASE_IDX 2 1082 #define mmMCIF_WB_BUF_1_RESOLUTION 0x02a3 1083 #define mmMCIF_WB_BUF_1_RESOLUTION_BASE_IDX 2 1084 #define mmMCIF_WB_BUF_2_RESOLUTION 0x02a4 1085 #define mmMCIF_WB_BUF_2_RESOLUTION_BASE_IDX 2 1086 #define mmMCIF_WB_BUF_3_RESOLUTION 0x02a5 1087 #define mmMCIF_WB_BUF_3_RESOLUTION_BASE_IDX 2 1088 #define mmMCIF_WB_BUF_4_RESOLUTION 0x02a6 1089 #define mmMCIF_WB_BUF_4_RESOLUTION_BASE_IDX 2 1090 #define mmMCIF_WB_DRAM_SPEED_CHANGE_DURATION_VBI 0x02a7 1091 #define mmMCIF_WB_DRAM_SPEED_CHANGE_DURATION_VBI_BASE_IDX 2 1092 #define mmMCIF_WB_VMID_CONTROL 0x02a8 1093 #define mmMCIF_WB_VMID_CONTROL_BASE_IDX 2 1094 #define mmMCIF_WB_MIN_TTO 0x02a9 1095 #define mmMCIF_WB_MIN_TTO_BASE_IDX 2 1096 1097 1098 // addressBlock: dce_dc_mmhubbub_mmhubbub_dispdec 1099 // base address: 0x0 1100 #define mmMCIF_WB_NB_PSTATE_LATENCY_WATERMARK 0x02aa 1101 #define mmMCIF_WB_NB_PSTATE_LATENCY_WATERMARK_BASE_IDX 2 1102 #define mmMCIF_WB_WATERMARK 0x02ab 1103 #define mmMCIF_WB_WATERMARK_BASE_IDX 2 1104 #define mmMMHUBBUB_WARMUP_CONFIG 0x02ac 1105 #define mmMMHUBBUB_WARMUP_CONFIG_BASE_IDX 2 1106 #define mmMMHUBBUB_WARMUP_CONTROL_STATUS 0x02ad 1107 #define mmMMHUBBUB_WARMUP_CONTROL_STATUS_BASE_IDX 2 1108 #define mmMMHUBBUB_WARMUP_BASE_ADDR_LOW 0x02ae 1109 #define mmMMHUBBUB_WARMUP_BASE_ADDR_LOW_BASE_IDX 2 1110 #define mmMMHUBBUB_WARMUP_BASE_ADDR_HIGH 0x02af 1111 #define mmMMHUBBUB_WARMUP_BASE_ADDR_HIGH_BASE_IDX 2 1112 #define mmMMHUBBUB_WARMUP_ADDR_REGION 0x02b0 1113 #define mmMMHUBBUB_WARMUP_ADDR_REGION_BASE_IDX 2 1114 #define mmMMHUBBUB_MIN_TTO 0x02b1 1115 #define mmMMHUBBUB_MIN_TTO_BASE_IDX 2 1116 #define mmWBIF_SMU_WM_CONTROL 0x0333 1117 #define mmWBIF_SMU_WM_CONTROL_BASE_IDX 2 1118 #define mmWBIF0_MISC_CTRL 0x0334 1119 #define mmWBIF0_MISC_CTRL_BASE_IDX 2 1120 #define mmWBIF0_PHASE0_OUTSTANDING_COUNTER 0x0335 1121 #define mmWBIF0_PHASE0_OUTSTANDING_COUNTER_BASE_IDX 2 1122 #define mmWBIF0_PHASE1_OUTSTANDING_COUNTER 0x0336 1123 #define mmWBIF0_PHASE1_OUTSTANDING_COUNTER_BASE_IDX 2 1124 #define mmVGA_SRC_SPLIT_CNTL 0x033d 1125 #define mmVGA_SRC_SPLIT_CNTL_BASE_IDX 2 1126 #define mmMMHUBBUB_MEM_PWR_STATUS 0x033e 1127 #define mmMMHUBBUB_MEM_PWR_STATUS_BASE_IDX 2 1128 #define mmMMHUBBUB_MEM_PWR_CNTL 0x033f 1129 #define mmMMHUBBUB_MEM_PWR_CNTL_BASE_IDX 2 1130 #define mmMMHUBBUB_CLOCK_CNTL 0x0340 1131 #define mmMMHUBBUB_CLOCK_CNTL_BASE_IDX 2 1132 #define mmMMHUBBUB_SOFT_RESET 0x0341 1133 #define mmMMHUBBUB_SOFT_RESET_BASE_IDX 2 1134 #define mmDMU_IF_ERR_STATUS 0x0345 1135 #define mmDMU_IF_ERR_STATUS_BASE_IDX 2 1136 #define mmMMHUBBUB_CLIENT_UNIT_ID 0x0346 1137 #define mmMMHUBBUB_CLIENT_UNIT_ID_BASE_IDX 2 1138 #define mmMMHUBBUB_WARMUP_VMID_CONTROL 0x0348 1139 #define mmMMHUBBUB_WARMUP_VMID_CONTROL_BASE_IDX 2 1140 1141 1142 // addressBlock: dce_dc_mmhubbub_vgaif_dispdec 1143 // base address: 0x0 1144 #define mmMCIF_CONTROL 0x034a 1145 #define mmMCIF_CONTROL_BASE_IDX 2 1146 #define mmMCIF_WRITE_COMBINE_CONTROL 0x034b 1147 #define mmMCIF_WRITE_COMBINE_CONTROL_BASE_IDX 2 1148 #define mmMCIF_PHASE0_OUTSTANDING_COUNTER 0x034e 1149 #define mmMCIF_PHASE0_OUTSTANDING_COUNTER_BASE_IDX 2 1150 #define mmMCIF_PHASE1_OUTSTANDING_COUNTER 0x034f 1151 #define mmMCIF_PHASE1_OUTSTANDING_COUNTER_BASE_IDX 2 1152 #define mmMCIF_PHASE2_OUTSTANDING_COUNTER 0x0350 1153 #define mmMCIF_PHASE2_OUTSTANDING_COUNTER_BASE_IDX 2 1154 1155 1156 // addressBlock: dce_dc_mmhubbub_mmhubbub_dcperfmon_dc_perfmon_dispdec 1157 // base address: 0xd48 1158 #define mmDC_PERFMON3_PERFCOUNTER_CNTL 0x0352 1159 #define mmDC_PERFMON3_PERFCOUNTER_CNTL_BASE_IDX 2 1160 #define mmDC_PERFMON3_PERFCOUNTER_CNTL2 0x0353 1161 #define mmDC_PERFMON3_PERFCOUNTER_CNTL2_BASE_IDX 2 1162 #define mmDC_PERFMON3_PERFCOUNTER_STATE 0x0354 1163 #define mmDC_PERFMON3_PERFCOUNTER_STATE_BASE_IDX 2 1164 #define mmDC_PERFMON3_PERFMON_CNTL 0x0355 1165 #define mmDC_PERFMON3_PERFMON_CNTL_BASE_IDX 2 1166 #define mmDC_PERFMON3_PERFMON_CNTL2 0x0356 1167 #define mmDC_PERFMON3_PERFMON_CNTL2_BASE_IDX 2 1168 #define mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC 0x0357 1169 #define mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 1170 #define mmDC_PERFMON3_PERFMON_CVALUE_LOW 0x0358 1171 #define mmDC_PERFMON3_PERFMON_CVALUE_LOW_BASE_IDX 2 1172 #define mmDC_PERFMON3_PERFMON_HI 0x0359 1173 #define mmDC_PERFMON3_PERFMON_HI_BASE_IDX 2 1174 #define mmDC_PERFMON3_PERFMON_LOW 0x035a 1175 #define mmDC_PERFMON3_PERFMON_LOW_BASE_IDX 2 1176 1177 1178 // addressBlock: dce_dc_hda_azf0stream0_dispdec 1179 // base address: 0x0 1180 #define mmAZF0STREAM0_AZALIA_STREAM_INDEX 0x035e 1181 #define mmAZF0STREAM0_AZALIA_STREAM_INDEX_BASE_IDX 2 1182 #define mmAZF0STREAM0_AZALIA_STREAM_DATA 0x035f 1183 #define mmAZF0STREAM0_AZALIA_STREAM_DATA_BASE_IDX 2 1184 1185 1186 // addressBlock: dce_dc_hda_azf0stream1_dispdec 1187 // base address: 0x8 1188 #define mmAZF0STREAM1_AZALIA_STREAM_INDEX 0x0360 1189 #define mmAZF0STREAM1_AZALIA_STREAM_INDEX_BASE_IDX 2 1190 #define mmAZF0STREAM1_AZALIA_STREAM_DATA 0x0361 1191 #define mmAZF0STREAM1_AZALIA_STREAM_DATA_BASE_IDX 2 1192 1193 1194 // addressBlock: dce_dc_hda_azf0stream2_dispdec 1195 // base address: 0x10 1196 #define mmAZF0STREAM2_AZALIA_STREAM_INDEX 0x0362 1197 #define mmAZF0STREAM2_AZALIA_STREAM_INDEX_BASE_IDX 2 1198 #define mmAZF0STREAM2_AZALIA_STREAM_DATA 0x0363 1199 #define mmAZF0STREAM2_AZALIA_STREAM_DATA_BASE_IDX 2 1200 1201 1202 // addressBlock: dce_dc_hda_azf0stream3_dispdec 1203 // base address: 0x18 1204 #define mmAZF0STREAM3_AZALIA_STREAM_INDEX 0x0364 1205 #define mmAZF0STREAM3_AZALIA_STREAM_INDEX_BASE_IDX 2 1206 #define mmAZF0STREAM3_AZALIA_STREAM_DATA 0x0365 1207 #define mmAZF0STREAM3_AZALIA_STREAM_DATA_BASE_IDX 2 1208 1209 1210 // addressBlock: dce_dc_hda_azf0stream4_dispdec 1211 // base address: 0x20 1212 #define mmAZF0STREAM4_AZALIA_STREAM_INDEX 0x0366 1213 #define mmAZF0STREAM4_AZALIA_STREAM_INDEX_BASE_IDX 2 1214 #define mmAZF0STREAM4_AZALIA_STREAM_DATA 0x0367 1215 #define mmAZF0STREAM4_AZALIA_STREAM_DATA_BASE_IDX 2 1216 1217 1218 // addressBlock: dce_dc_hda_azf0stream5_dispdec 1219 // base address: 0x28 1220 #define mmAZF0STREAM5_AZALIA_STREAM_INDEX 0x0368 1221 #define mmAZF0STREAM5_AZALIA_STREAM_INDEX_BASE_IDX 2 1222 #define mmAZF0STREAM5_AZALIA_STREAM_DATA 0x0369 1223 #define mmAZF0STREAM5_AZALIA_STREAM_DATA_BASE_IDX 2 1224 1225 1226 // addressBlock: dce_dc_hda_azf0stream6_dispdec 1227 // base address: 0x30 1228 #define mmAZF0STREAM6_AZALIA_STREAM_INDEX 0x036a 1229 #define mmAZF0STREAM6_AZALIA_STREAM_INDEX_BASE_IDX 2 1230 #define mmAZF0STREAM6_AZALIA_STREAM_DATA 0x036b 1231 #define mmAZF0STREAM6_AZALIA_STREAM_DATA_BASE_IDX 2 1232 1233 1234 // addressBlock: dce_dc_hda_azf0stream7_dispdec 1235 // base address: 0x38 1236 #define mmAZF0STREAM7_AZALIA_STREAM_INDEX 0x036c 1237 #define mmAZF0STREAM7_AZALIA_STREAM_INDEX_BASE_IDX 2 1238 #define mmAZF0STREAM7_AZALIA_STREAM_DATA 0x036d 1239 #define mmAZF0STREAM7_AZALIA_STREAM_DATA_BASE_IDX 2 1240 1241 1242 // addressBlock: dce_dc_hda_az_misc_dispdec 1243 // base address: 0x0 1244 #define mmAZ_CLOCK_CNTL 0x0372 1245 #define mmAZ_CLOCK_CNTL_BASE_IDX 2 1246 1247 1248 // addressBlock: dce_dc_hda_az_dcperfmon_dc_perfmon_dispdec 1249 // base address: 0xde8 1250 #define mmDC_PERFMON4_PERFCOUNTER_CNTL 0x037a 1251 #define mmDC_PERFMON4_PERFCOUNTER_CNTL_BASE_IDX 2 1252 #define mmDC_PERFMON4_PERFCOUNTER_CNTL2 0x037b 1253 #define mmDC_PERFMON4_PERFCOUNTER_CNTL2_BASE_IDX 2 1254 #define mmDC_PERFMON4_PERFCOUNTER_STATE 0x037c 1255 #define mmDC_PERFMON4_PERFCOUNTER_STATE_BASE_IDX 2 1256 #define mmDC_PERFMON4_PERFMON_CNTL 0x037d 1257 #define mmDC_PERFMON4_PERFMON_CNTL_BASE_IDX 2 1258 #define mmDC_PERFMON4_PERFMON_CNTL2 0x037e 1259 #define mmDC_PERFMON4_PERFMON_CNTL2_BASE_IDX 2 1260 #define mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC 0x037f 1261 #define mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 1262 #define mmDC_PERFMON4_PERFMON_CVALUE_LOW 0x0380 1263 #define mmDC_PERFMON4_PERFMON_CVALUE_LOW_BASE_IDX 2 1264 #define mmDC_PERFMON4_PERFMON_HI 0x0381 1265 #define mmDC_PERFMON4_PERFMON_HI_BASE_IDX 2 1266 #define mmDC_PERFMON4_PERFMON_LOW 0x0382 1267 #define mmDC_PERFMON4_PERFMON_LOW_BASE_IDX 2 1268 1269 1270 // addressBlock: dce_dc_hda_azf0endpoint0_dispdec 1271 // base address: 0x0 1272 #define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0386 1273 #define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 1274 #define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0387 1275 #define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 1276 1277 1278 // addressBlock: dce_dc_hda_azf0endpoint1_dispdec 1279 // base address: 0x18 1280 #define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x038c 1281 #define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 1282 #define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA 0x038d 1283 #define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 1284 1285 1286 // addressBlock: dce_dc_hda_azf0endpoint2_dispdec 1287 // base address: 0x30 1288 #define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0392 1289 #define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 1290 #define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0393 1291 #define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 1292 1293 1294 // addressBlock: dce_dc_hda_azf0endpoint3_dispdec 1295 // base address: 0x48 1296 #define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0398 1297 #define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 1298 #define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0399 1299 #define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 1300 1301 1302 // addressBlock: dce_dc_hda_azf0endpoint4_dispdec 1303 // base address: 0x60 1304 #define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x039e 1305 #define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 1306 #define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA 0x039f 1307 #define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 1308 1309 1310 // addressBlock: dce_dc_hda_azf0endpoint5_dispdec 1311 // base address: 0x78 1312 #define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x03a4 1313 #define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 1314 #define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA 0x03a5 1315 #define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 1316 1317 1318 // addressBlock: dce_dc_hda_azf0endpoint6_dispdec 1319 // base address: 0x90 1320 #define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x03aa 1321 #define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 1322 #define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA 0x03ab 1323 #define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 1324 1325 1326 // addressBlock: dce_dc_hda_azf0endpoint7_dispdec 1327 // base address: 0xa8 1328 #define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x03b0 1329 #define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 1330 #define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA 0x03b1 1331 #define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 1332 1333 1334 // addressBlock: dce_dc_hda_azf0controller_dispdec 1335 // base address: 0x0 1336 #define mmAZALIA_CONTROLLER_CLOCK_GATING 0x03c2 1337 #define mmAZALIA_CONTROLLER_CLOCK_GATING_BASE_IDX 2 1338 #define mmAZALIA_AUDIO_DTO 0x03c3 1339 #define mmAZALIA_AUDIO_DTO_BASE_IDX 2 1340 #define mmAZALIA_AUDIO_DTO_CONTROL 0x03c4 1341 #define mmAZALIA_AUDIO_DTO_CONTROL_BASE_IDX 2 1342 #define mmAZALIA_SOCCLK_CONTROL 0x03c5 1343 #define mmAZALIA_SOCCLK_CONTROL_BASE_IDX 2 1344 #define mmAZALIA_UNDERFLOW_FILLER_SAMPLE 0x03c6 1345 #define mmAZALIA_UNDERFLOW_FILLER_SAMPLE_BASE_IDX 2 1346 #define mmAZALIA_DATA_DMA_CONTROL 0x03c7 1347 #define mmAZALIA_DATA_DMA_CONTROL_BASE_IDX 2 1348 #define mmAZALIA_BDL_DMA_CONTROL 0x03c8 1349 #define mmAZALIA_BDL_DMA_CONTROL_BASE_IDX 2 1350 #define mmAZALIA_RIRB_AND_DP_CONTROL 0x03c9 1351 #define mmAZALIA_RIRB_AND_DP_CONTROL_BASE_IDX 2 1352 #define mmAZALIA_CORB_DMA_CONTROL 0x03ca 1353 #define mmAZALIA_CORB_DMA_CONTROL_BASE_IDX 2 1354 #define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER 0x03d1 1355 #define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER_BASE_IDX 2 1356 #define mmAZALIA_CYCLIC_BUFFER_SYNC 0x03d2 1357 #define mmAZALIA_CYCLIC_BUFFER_SYNC_BASE_IDX 2 1358 #define mmAZALIA_GLOBAL_CAPABILITIES 0x03d3 1359 #define mmAZALIA_GLOBAL_CAPABILITIES_BASE_IDX 2 1360 #define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY 0x03d4 1361 #define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY_BASE_IDX 2 1362 #define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL 0x03d5 1363 #define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL_BASE_IDX 2 1364 #define mmAZALIA_INPUT_PAYLOAD_CAPABILITY 0x03d6 1365 #define mmAZALIA_INPUT_PAYLOAD_CAPABILITY_BASE_IDX 2 1366 #define mmAZALIA_INPUT_CRC0_CONTROL0 0x03d9 1367 #define mmAZALIA_INPUT_CRC0_CONTROL0_BASE_IDX 2 1368 #define mmAZALIA_INPUT_CRC0_CONTROL1 0x03da 1369 #define mmAZALIA_INPUT_CRC0_CONTROL1_BASE_IDX 2 1370 #define mmAZALIA_INPUT_CRC0_CONTROL2 0x03db 1371 #define mmAZALIA_INPUT_CRC0_CONTROL2_BASE_IDX 2 1372 #define mmAZALIA_INPUT_CRC0_CONTROL3 0x03dc 1373 #define mmAZALIA_INPUT_CRC0_CONTROL3_BASE_IDX 2 1374 #define mmAZALIA_INPUT_CRC0_RESULT 0x03dd 1375 #define mmAZALIA_INPUT_CRC0_RESULT_BASE_IDX 2 1376 #define mmAZALIA_INPUT_CRC1_CONTROL0 0x03de 1377 #define mmAZALIA_INPUT_CRC1_CONTROL0_BASE_IDX 2 1378 #define mmAZALIA_INPUT_CRC1_CONTROL1 0x03df 1379 #define mmAZALIA_INPUT_CRC1_CONTROL1_BASE_IDX 2 1380 #define mmAZALIA_INPUT_CRC1_CONTROL2 0x03e0 1381 #define mmAZALIA_INPUT_CRC1_CONTROL2_BASE_IDX 2 1382 #define mmAZALIA_INPUT_CRC1_CONTROL3 0x03e1 1383 #define mmAZALIA_INPUT_CRC1_CONTROL3_BASE_IDX 2 1384 #define mmAZALIA_INPUT_CRC1_RESULT 0x03e2 1385 #define mmAZALIA_INPUT_CRC1_RESULT_BASE_IDX 2 1386 #define mmAZALIA_CRC0_CONTROL0 0x03e3 1387 #define mmAZALIA_CRC0_CONTROL0_BASE_IDX 2 1388 #define mmAZALIA_CRC0_CONTROL1 0x03e4 1389 #define mmAZALIA_CRC0_CONTROL1_BASE_IDX 2 1390 #define mmAZALIA_CRC0_CONTROL2 0x03e5 1391 #define mmAZALIA_CRC0_CONTROL2_BASE_IDX 2 1392 #define mmAZALIA_CRC0_CONTROL3 0x03e6 1393 #define mmAZALIA_CRC0_CONTROL3_BASE_IDX 2 1394 #define mmAZALIA_CRC0_RESULT 0x03e7 1395 #define mmAZALIA_CRC0_RESULT_BASE_IDX 2 1396 #define mmAZALIA_CRC1_CONTROL0 0x03e8 1397 #define mmAZALIA_CRC1_CONTROL0_BASE_IDX 2 1398 #define mmAZALIA_CRC1_CONTROL1 0x03e9 1399 #define mmAZALIA_CRC1_CONTROL1_BASE_IDX 2 1400 #define mmAZALIA_CRC1_CONTROL2 0x03ea 1401 #define mmAZALIA_CRC1_CONTROL2_BASE_IDX 2 1402 #define mmAZALIA_CRC1_CONTROL3 0x03eb 1403 #define mmAZALIA_CRC1_CONTROL3_BASE_IDX 2 1404 #define mmAZALIA_CRC1_RESULT 0x03ec 1405 #define mmAZALIA_CRC1_RESULT_BASE_IDX 2 1406 #define mmAZALIA_MEM_PWR_CTRL 0x03ee 1407 #define mmAZALIA_MEM_PWR_CTRL_BASE_IDX 2 1408 #define mmAZALIA_MEM_PWR_STATUS 0x03ef 1409 #define mmAZALIA_MEM_PWR_STATUS_BASE_IDX 2 1410 1411 1412 // addressBlock: dce_dc_hda_azf0root_dispdec 1413 // base address: 0x0 1414 #define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x0406 1415 #define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_BASE_IDX 2 1416 #define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID 0x0407 1417 #define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID_BASE_IDX 2 1418 #define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL 0x0408 1419 #define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL_BASE_IDX 2 1420 #define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL 0x0409 1421 #define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL_BASE_IDX 2 1422 #define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x040a 1423 #define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_BASE_IDX 2 1424 #define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x040b 1425 #define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES_BASE_IDX 2 1426 #define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x040c 1427 #define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_BASE_IDX 2 1428 #define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x040d 1429 #define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES_BASE_IDX 2 1430 #define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE 0x040e 1431 #define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE_BASE_IDX 2 1432 #define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET 0x040f 1433 #define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET_BASE_IDX 2 1434 #define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x0410 1435 #define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_BASE_IDX 2 1436 #define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x0411 1437 #define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION_BASE_IDX 2 1438 #define mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY 0x0412 1439 #define mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX 2 1440 #define mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY 0x0413 1441 #define mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX 2 1442 #define mmAZALIA_F0_GTC_GROUP_OFFSET0 0x0415 1443 #define mmAZALIA_F0_GTC_GROUP_OFFSET0_BASE_IDX 2 1444 #define mmAZALIA_F0_GTC_GROUP_OFFSET1 0x0416 1445 #define mmAZALIA_F0_GTC_GROUP_OFFSET1_BASE_IDX 2 1446 #define mmAZALIA_F0_GTC_GROUP_OFFSET2 0x0417 1447 #define mmAZALIA_F0_GTC_GROUP_OFFSET2_BASE_IDX 2 1448 #define mmAZALIA_F0_GTC_GROUP_OFFSET3 0x0418 1449 #define mmAZALIA_F0_GTC_GROUP_OFFSET3_BASE_IDX 2 1450 #define mmAZALIA_F0_GTC_GROUP_OFFSET4 0x0419 1451 #define mmAZALIA_F0_GTC_GROUP_OFFSET4_BASE_IDX 2 1452 #define mmAZALIA_F0_GTC_GROUP_OFFSET5 0x041a 1453 #define mmAZALIA_F0_GTC_GROUP_OFFSET5_BASE_IDX 2 1454 #define mmAZALIA_F0_GTC_GROUP_OFFSET6 0x041b 1455 #define mmAZALIA_F0_GTC_GROUP_OFFSET6_BASE_IDX 2 1456 #define mmREG_DC_AUDIO_PORT_CONNECTIVITY 0x041c 1457 #define mmREG_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX 2 1458 #define mmREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY 0x041d 1459 #define mmREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX 2 1460 1461 1462 // addressBlock: dce_dc_hda_azf0stream8_dispdec 1463 // base address: 0x320 1464 #define mmAZF0STREAM8_AZALIA_STREAM_INDEX 0x0426 1465 #define mmAZF0STREAM8_AZALIA_STREAM_INDEX_BASE_IDX 2 1466 #define mmAZF0STREAM8_AZALIA_STREAM_DATA 0x0427 1467 #define mmAZF0STREAM8_AZALIA_STREAM_DATA_BASE_IDX 2 1468 1469 1470 // addressBlock: dce_dc_hda_azf0stream9_dispdec 1471 // base address: 0x328 1472 #define mmAZF0STREAM9_AZALIA_STREAM_INDEX 0x0428 1473 #define mmAZF0STREAM9_AZALIA_STREAM_INDEX_BASE_IDX 2 1474 #define mmAZF0STREAM9_AZALIA_STREAM_DATA 0x0429 1475 #define mmAZF0STREAM9_AZALIA_STREAM_DATA_BASE_IDX 2 1476 1477 1478 // addressBlock: dce_dc_hda_azf0stream10_dispdec 1479 // base address: 0x330 1480 #define mmAZF0STREAM10_AZALIA_STREAM_INDEX 0x042a 1481 #define mmAZF0STREAM10_AZALIA_STREAM_INDEX_BASE_IDX 2 1482 #define mmAZF0STREAM10_AZALIA_STREAM_DATA 0x042b 1483 #define mmAZF0STREAM10_AZALIA_STREAM_DATA_BASE_IDX 2 1484 1485 1486 // addressBlock: dce_dc_hda_azf0stream11_dispdec 1487 // base address: 0x338 1488 #define mmAZF0STREAM11_AZALIA_STREAM_INDEX 0x042c 1489 #define mmAZF0STREAM11_AZALIA_STREAM_INDEX_BASE_IDX 2 1490 #define mmAZF0STREAM11_AZALIA_STREAM_DATA 0x042d 1491 #define mmAZF0STREAM11_AZALIA_STREAM_DATA_BASE_IDX 2 1492 1493 1494 // addressBlock: dce_dc_hda_azf0stream12_dispdec 1495 // base address: 0x340 1496 #define mmAZF0STREAM12_AZALIA_STREAM_INDEX 0x042e 1497 #define mmAZF0STREAM12_AZALIA_STREAM_INDEX_BASE_IDX 2 1498 #define mmAZF0STREAM12_AZALIA_STREAM_DATA 0x042f 1499 #define mmAZF0STREAM12_AZALIA_STREAM_DATA_BASE_IDX 2 1500 1501 1502 // addressBlock: dce_dc_hda_azf0stream13_dispdec 1503 // base address: 0x348 1504 #define mmAZF0STREAM13_AZALIA_STREAM_INDEX 0x0430 1505 #define mmAZF0STREAM13_AZALIA_STREAM_INDEX_BASE_IDX 2 1506 #define mmAZF0STREAM13_AZALIA_STREAM_DATA 0x0431 1507 #define mmAZF0STREAM13_AZALIA_STREAM_DATA_BASE_IDX 2 1508 1509 1510 // addressBlock: dce_dc_hda_azf0stream14_dispdec 1511 // base address: 0x350 1512 #define mmAZF0STREAM14_AZALIA_STREAM_INDEX 0x0432 1513 #define mmAZF0STREAM14_AZALIA_STREAM_INDEX_BASE_IDX 2 1514 #define mmAZF0STREAM14_AZALIA_STREAM_DATA 0x0433 1515 #define mmAZF0STREAM14_AZALIA_STREAM_DATA_BASE_IDX 2 1516 1517 1518 // addressBlock: dce_dc_hda_azf0stream15_dispdec 1519 // base address: 0x358 1520 #define mmAZF0STREAM15_AZALIA_STREAM_INDEX 0x0434 1521 #define mmAZF0STREAM15_AZALIA_STREAM_INDEX_BASE_IDX 2 1522 #define mmAZF0STREAM15_AZALIA_STREAM_DATA 0x0435 1523 #define mmAZF0STREAM15_AZALIA_STREAM_DATA_BASE_IDX 2 1524 1525 1526 // addressBlock: dce_dc_hda_azf0inputendpoint0_dispdec 1527 // base address: 0x0 1528 #define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x043a 1529 #define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 1530 #define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x043b 1531 #define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 1532 1533 1534 // addressBlock: dce_dc_hda_azf0inputendpoint1_dispdec 1535 // base address: 0x10 1536 #define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x043e 1537 #define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 1538 #define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x043f 1539 #define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 1540 1541 1542 // addressBlock: dce_dc_hda_azf0inputendpoint2_dispdec 1543 // base address: 0x20 1544 #define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0442 1545 #define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 1546 #define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0443 1547 #define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 1548 1549 1550 // addressBlock: dce_dc_hda_azf0inputendpoint3_dispdec 1551 // base address: 0x30 1552 #define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0446 1553 #define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 1554 #define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0447 1555 #define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 1556 1557 1558 // addressBlock: dce_dc_hda_azf0inputendpoint4_dispdec 1559 // base address: 0x40 1560 #define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x044a 1561 #define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 1562 #define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x044b 1563 #define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 1564 1565 1566 // addressBlock: dce_dc_hda_azf0inputendpoint5_dispdec 1567 // base address: 0x50 1568 #define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x044e 1569 #define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 1570 #define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x044f 1571 #define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 1572 1573 1574 // addressBlock: dce_dc_hda_azf0inputendpoint6_dispdec 1575 // base address: 0x60 1576 #define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0452 1577 #define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 1578 #define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0453 1579 #define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 1580 1581 1582 // addressBlock: dce_dc_hda_azf0inputendpoint7_dispdec 1583 // base address: 0x70 1584 #define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0456 1585 #define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 1586 #define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0457 1587 #define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 1588 1589 1590 // addressBlock: dce_dc_dchubbub_hubbub_sdpif_dispdec 1591 // base address: 0x0 1592 #define mmDCHUBBUB_SDPIF_CFG0 0x048f 1593 #define mmDCHUBBUB_SDPIF_CFG0_BASE_IDX 2 1594 #define mmVM_REQUEST_PHYSICAL 0x0490 1595 #define mmVM_REQUEST_PHYSICAL_BASE_IDX 2 1596 #define mmDCHUBBUB_FORCE_IO_STATUS_0 0x0491 1597 #define mmDCHUBBUB_FORCE_IO_STATUS_0_BASE_IDX 2 1598 #define mmDCHUBBUB_FORCE_IO_STATUS_1 0x0492 1599 #define mmDCHUBBUB_FORCE_IO_STATUS_1_BASE_IDX 2 1600 #define mmDCN_VM_FB_LOCATION_BASE 0x0493 1601 #define mmDCN_VM_FB_LOCATION_BASE_BASE_IDX 2 1602 #define mmDCN_VM_FB_LOCATION_TOP 0x0494 1603 #define mmDCN_VM_FB_LOCATION_TOP_BASE_IDX 2 1604 #define mmDCN_VM_FB_OFFSET 0x0495 1605 #define mmDCN_VM_FB_OFFSET_BASE_IDX 2 1606 #define mmDCN_VM_AGP_BOT 0x0496 1607 #define mmDCN_VM_AGP_BOT_BASE_IDX 2 1608 #define mmDCN_VM_AGP_TOP 0x0497 1609 #define mmDCN_VM_AGP_TOP_BASE_IDX 2 1610 #define mmDCN_VM_AGP_BASE 0x0498 1611 #define mmDCN_VM_AGP_BASE_BASE_IDX 2 1612 #define mmDCN_VM_LOCAL_HBM_ADDRESS_START 0x0499 1613 #define mmDCN_VM_LOCAL_HBM_ADDRESS_START_BASE_IDX 2 1614 #define mmDCN_VM_LOCAL_HBM_ADDRESS_END 0x049a 1615 #define mmDCN_VM_LOCAL_HBM_ADDRESS_END_BASE_IDX 2 1616 #define mmDCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL 0x049b 1617 #define mmDCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_BASE_IDX 2 1618 #define mmDCHUBBUB_SDPIF_MEM_PWR_CTRL 0x04ba 1619 #define mmDCHUBBUB_SDPIF_MEM_PWR_CTRL_BASE_IDX 2 1620 #define mmDCHUBBUB_SDPIF_MEM_PWR_STATUS 0x04bb 1621 #define mmDCHUBBUB_SDPIF_MEM_PWR_STATUS_BASE_IDX 2 1622 #define mmDCHUBBUB_SDPIF_CFG1 0x04bf 1623 #define mmDCHUBBUB_SDPIF_CFG1_BASE_IDX 2 1624 #define mmDCHUBBUB_SDPIF_CFG2 0x04c0 1625 #define mmDCHUBBUB_SDPIF_CFG2_BASE_IDX 2 1626 1627 1628 // addressBlock: dce_dc_dchubbub_hubbub_ret_path_dispdec 1629 // base address: 0x0 1630 #define mmDCHUBBUB_RET_PATH_DCC_CFG 0x04cf 1631 #define mmDCHUBBUB_RET_PATH_DCC_CFG_BASE_IDX 2 1632 #define mmDCHUBBUB_RET_PATH_DCC_CFG0_0 0x04d0 1633 #define mmDCHUBBUB_RET_PATH_DCC_CFG0_0_BASE_IDX 2 1634 #define mmDCHUBBUB_RET_PATH_DCC_CFG0_1 0x04d1 1635 #define mmDCHUBBUB_RET_PATH_DCC_CFG0_1_BASE_IDX 2 1636 #define mmDCHUBBUB_RET_PATH_DCC_CFG1_0 0x04d2 1637 #define mmDCHUBBUB_RET_PATH_DCC_CFG1_0_BASE_IDX 2 1638 #define mmDCHUBBUB_RET_PATH_DCC_CFG1_1 0x04d3 1639 #define mmDCHUBBUB_RET_PATH_DCC_CFG1_1_BASE_IDX 2 1640 #define mmDCHUBBUB_RET_PATH_DCC_CFG2_0 0x04d4 1641 #define mmDCHUBBUB_RET_PATH_DCC_CFG2_0_BASE_IDX 2 1642 #define mmDCHUBBUB_RET_PATH_DCC_CFG2_1 0x04d5 1643 #define mmDCHUBBUB_RET_PATH_DCC_CFG2_1_BASE_IDX 2 1644 #define mmDCHUBBUB_RET_PATH_DCC_CFG3_0 0x04d6 1645 #define mmDCHUBBUB_RET_PATH_DCC_CFG3_0_BASE_IDX 2 1646 #define mmDCHUBBUB_RET_PATH_DCC_CFG3_1 0x04d7 1647 #define mmDCHUBBUB_RET_PATH_DCC_CFG3_1_BASE_IDX 2 1648 #define mmDCHUBBUB_RET_PATH_DCC_CFG4_0 0x04d8 1649 #define mmDCHUBBUB_RET_PATH_DCC_CFG4_0_BASE_IDX 2 1650 #define mmDCHUBBUB_RET_PATH_DCC_CFG4_1 0x04d9 1651 #define mmDCHUBBUB_RET_PATH_DCC_CFG4_1_BASE_IDX 2 1652 #define mmDCHUBBUB_RET_PATH_DCC_CFG5_0 0x04da 1653 #define mmDCHUBBUB_RET_PATH_DCC_CFG5_0_BASE_IDX 2 1654 #define mmDCHUBBUB_RET_PATH_DCC_CFG5_1 0x04db 1655 #define mmDCHUBBUB_RET_PATH_DCC_CFG5_1_BASE_IDX 2 1656 #define mmDCHUBBUB_RET_PATH_DCC_CFG6_0 0x04dc 1657 #define mmDCHUBBUB_RET_PATH_DCC_CFG6_0_BASE_IDX 2 1658 #define mmDCHUBBUB_RET_PATH_DCC_CFG6_1 0x04dd 1659 #define mmDCHUBBUB_RET_PATH_DCC_CFG6_1_BASE_IDX 2 1660 #define mmDCHUBBUB_RET_PATH_DCC_CFG7_0 0x04de 1661 #define mmDCHUBBUB_RET_PATH_DCC_CFG7_0_BASE_IDX 2 1662 #define mmDCHUBBUB_RET_PATH_DCC_CFG7_1 0x04df 1663 #define mmDCHUBBUB_RET_PATH_DCC_CFG7_1_BASE_IDX 2 1664 #define mmDCHUBBUB_RET_PATH_DCC_CFG8_0 0x04e0 1665 #define mmDCHUBBUB_RET_PATH_DCC_CFG8_0_BASE_IDX 2 1666 #define mmDCHUBBUB_RET_PATH_DCC_CFG8_1 0x04e1 1667 #define mmDCHUBBUB_RET_PATH_DCC_CFG8_1_BASE_IDX 2 1668 #define mmDCHUBBUB_RET_PATH_DCC_CFG9_0 0x04e2 1669 #define mmDCHUBBUB_RET_PATH_DCC_CFG9_0_BASE_IDX 2 1670 #define mmDCHUBBUB_RET_PATH_DCC_CFG9_1 0x04e3 1671 #define mmDCHUBBUB_RET_PATH_DCC_CFG9_1_BASE_IDX 2 1672 #define mmDCHUBBUB_RET_PATH_DCC_CFG10_0 0x04e4 1673 #define mmDCHUBBUB_RET_PATH_DCC_CFG10_0_BASE_IDX 2 1674 #define mmDCHUBBUB_RET_PATH_DCC_CFG10_1 0x04e5 1675 #define mmDCHUBBUB_RET_PATH_DCC_CFG10_1_BASE_IDX 2 1676 #define mmDCHUBBUB_RET_PATH_DCC_CFG11_0 0x04e6 1677 #define mmDCHUBBUB_RET_PATH_DCC_CFG11_0_BASE_IDX 2 1678 #define mmDCHUBBUB_RET_PATH_DCC_CFG11_1 0x04e7 1679 #define mmDCHUBBUB_RET_PATH_DCC_CFG11_1_BASE_IDX 2 1680 #define mmDCHUBBUB_RET_PATH_MEM_PWR_CTRL 0x04ef 1681 #define mmDCHUBBUB_RET_PATH_MEM_PWR_CTRL_BASE_IDX 2 1682 #define mmDCHUBBUB_RET_PATH_MEM_PWR_STATUS 0x04f0 1683 #define mmDCHUBBUB_RET_PATH_MEM_PWR_STATUS_BASE_IDX 2 1684 #define mmDCHUBBUB_CRC_CTRL 0x04f1 1685 #define mmDCHUBBUB_CRC_CTRL_BASE_IDX 2 1686 #define mmDCHUBBUB_CRC0_VAL_R_G 0x04f2 1687 #define mmDCHUBBUB_CRC0_VAL_R_G_BASE_IDX 2 1688 #define mmDCHUBBUB_CRC0_VAL_B_A 0x04f3 1689 #define mmDCHUBBUB_CRC0_VAL_B_A_BASE_IDX 2 1690 #define mmDCHUBBUB_CRC1_VAL_R_G 0x04f4 1691 #define mmDCHUBBUB_CRC1_VAL_R_G_BASE_IDX 2 1692 #define mmDCHUBBUB_CRC1_VAL_B_A 0x04f5 1693 #define mmDCHUBBUB_CRC1_VAL_B_A_BASE_IDX 2 1694 1695 1696 // addressBlock: dce_dc_dchubbub_hubbub_dispdec 1697 // base address: 0x0 1698 #define mmDCHUBBUB_ARB_DF_REQ_OUTSTAND 0x0505 1699 #define mmDCHUBBUB_ARB_DF_REQ_OUTSTAND_BASE_IDX 2 1700 #define mmDCHUBBUB_ARB_SAT_LEVEL 0x0506 1701 #define mmDCHUBBUB_ARB_SAT_LEVEL_BASE_IDX 2 1702 #define mmDCHUBBUB_ARB_QOS_FORCE 0x0507 1703 #define mmDCHUBBUB_ARB_QOS_FORCE_BASE_IDX 2 1704 #define mmDCHUBBUB_ARB_DRAM_STATE_CNTL 0x0508 1705 #define mmDCHUBBUB_ARB_DRAM_STATE_CNTL_BASE_IDX 2 1706 #define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A 0x0509 1707 #define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A_BASE_IDX 2 1708 #define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A 0x050a 1709 #define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A_BASE_IDX 2 1710 #define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A 0x050b 1711 #define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A_BASE_IDX 2 1712 #define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A 0x050c 1713 #define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A_BASE_IDX 2 1714 #define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A 0x050d 1715 #define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A_BASE_IDX 2 1716 #define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B 0x050e 1717 #define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B_BASE_IDX 2 1718 #define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B 0x050f 1719 #define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B_BASE_IDX 2 1720 #define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B 0x0510 1721 #define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B_BASE_IDX 2 1722 #define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B 0x0511 1723 #define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B_BASE_IDX 2 1724 #define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B 0x0512 1725 #define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B_BASE_IDX 2 1726 #define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C 0x0513 1727 #define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C_BASE_IDX 2 1728 #define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C 0x0514 1729 #define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C_BASE_IDX 2 1730 #define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C 0x0515 1731 #define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C_BASE_IDX 2 1732 #define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C 0x0516 1733 #define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C_BASE_IDX 2 1734 #define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C 0x0517 1735 #define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C_BASE_IDX 2 1736 #define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D 0x0518 1737 #define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D_BASE_IDX 2 1738 #define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D 0x0519 1739 #define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D_BASE_IDX 2 1740 #define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D 0x051a 1741 #define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D_BASE_IDX 2 1742 #define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D 0x051b 1743 #define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D_BASE_IDX 2 1744 #define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D 0x051c 1745 #define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D_BASE_IDX 2 1746 #define mmDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL 0x051d 1747 #define mmDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL_BASE_IDX 2 1748 #define mmDCHUBBUB_ARB_TIMEOUT_ENABLE 0x051e 1749 #define mmDCHUBBUB_ARB_TIMEOUT_ENABLE_BASE_IDX 2 1750 #define mmDCHUBBUB_GLOBAL_TIMER_CNTL 0x051f 1751 #define mmDCHUBBUB_GLOBAL_TIMER_CNTL_BASE_IDX 2 1752 #define mmSURFACE_CHECK0_ADDRESS_LSB 0x0520 1753 #define mmSURFACE_CHECK0_ADDRESS_LSB_BASE_IDX 2 1754 #define mmSURFACE_CHECK0_ADDRESS_MSB 0x0521 1755 #define mmSURFACE_CHECK0_ADDRESS_MSB_BASE_IDX 2 1756 #define mmSURFACE_CHECK1_ADDRESS_LSB 0x0522 1757 #define mmSURFACE_CHECK1_ADDRESS_LSB_BASE_IDX 2 1758 #define mmSURFACE_CHECK1_ADDRESS_MSB 0x0523 1759 #define mmSURFACE_CHECK1_ADDRESS_MSB_BASE_IDX 2 1760 #define mmSURFACE_CHECK2_ADDRESS_LSB 0x0524 1761 #define mmSURFACE_CHECK2_ADDRESS_LSB_BASE_IDX 2 1762 #define mmSURFACE_CHECK2_ADDRESS_MSB 0x0525 1763 #define mmSURFACE_CHECK2_ADDRESS_MSB_BASE_IDX 2 1764 #define mmSURFACE_CHECK3_ADDRESS_LSB 0x0526 1765 #define mmSURFACE_CHECK3_ADDRESS_LSB_BASE_IDX 2 1766 #define mmSURFACE_CHECK3_ADDRESS_MSB 0x0527 1767 #define mmSURFACE_CHECK3_ADDRESS_MSB_BASE_IDX 2 1768 #define mmVTG0_CONTROL 0x0528 1769 #define mmVTG0_CONTROL_BASE_IDX 2 1770 #define mmVTG1_CONTROL 0x0529 1771 #define mmVTG1_CONTROL_BASE_IDX 2 1772 #define mmVTG2_CONTROL 0x052a 1773 #define mmVTG2_CONTROL_BASE_IDX 2 1774 #define mmVTG3_CONTROL 0x052b 1775 #define mmVTG3_CONTROL_BASE_IDX 2 1776 #define mmVTG4_CONTROL 0x052c 1777 #define mmVTG4_CONTROL_BASE_IDX 2 1778 #define mmVTG5_CONTROL 0x052d 1779 #define mmVTG5_CONTROL_BASE_IDX 2 1780 #define mmDCHUBBUB_SOFT_RESET 0x052e 1781 #define mmDCHUBBUB_SOFT_RESET_BASE_IDX 2 1782 #define mmDCHUBBUB_CLOCK_CNTL 0x052f 1783 #define mmDCHUBBUB_CLOCK_CNTL_BASE_IDX 2 1784 #define mmDCFCLK_CNTL 0x0530 1785 #define mmDCFCLK_CNTL_BASE_IDX 2 1786 #define mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL 0x0531 1787 #define mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL_BASE_IDX 2 1788 #define mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2 0x0532 1789 #define mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2_BASE_IDX 2 1790 #define mmDCHUBBUB_VLINE_SNAPSHOT 0x0533 1791 #define mmDCHUBBUB_VLINE_SNAPSHOT_BASE_IDX 2 1792 #define mmDCHUBBUB_CTRL_STATUS 0x0534 1793 #define mmDCHUBBUB_CTRL_STATUS_BASE_IDX 2 1794 #define mmDCHUBBUB_TIMEOUT_DETECTION_CTRL1 0x053a 1795 #define mmDCHUBBUB_TIMEOUT_DETECTION_CTRL1_BASE_IDX 2 1796 #define mmDCHUBBUB_TIMEOUT_DETECTION_CTRL2 0x053b 1797 #define mmDCHUBBUB_TIMEOUT_DETECTION_CTRL2_BASE_IDX 2 1798 #define mmDCHUBBUB_TIMEOUT_INTERRUPT_STATUS 0x053c 1799 #define mmDCHUBBUB_TIMEOUT_INTERRUPT_STATUS_BASE_IDX 2 1800 #define mmDCHUBBUB_TEST_DEBUG_INDEX 0x053d 1801 #define mmDCHUBBUB_TEST_DEBUG_INDEX_BASE_IDX 2 1802 #define mmDCHUBBUB_TEST_DEBUG_DATA 0x053e 1803 #define mmDCHUBBUB_TEST_DEBUG_DATA_BASE_IDX 2 1804 #define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_A 0x053f 1805 #define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_A_BASE_IDX 2 1806 #define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_A 0x0540 1807 #define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_A_BASE_IDX 2 1808 #define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_B 0x0541 1809 #define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_B_BASE_IDX 2 1810 #define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_B 0x0542 1811 #define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_B_BASE_IDX 2 1812 #define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_C 0x0543 1813 #define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_C_BASE_IDX 2 1814 #define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_C 0x0544 1815 #define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_C_BASE_IDX 2 1816 #define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_D 0x0545 1817 #define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_D_BASE_IDX 2 1818 #define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_D 0x0546 1819 #define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_D_BASE_IDX 2 1820 #define mmFMON_CTRL 0x0548 1821 #define mmFMON_CTRL_BASE_IDX 2 1822 #define mmFMON_CTRL_1 0x0548 1823 #define mmFMON_CTRL_1_BASE_IDX 2 1824 1825 1826 // addressBlock: dce_dc_dchubbub_dchubbub_dcperfmon_dc_perfmon_dispdec 1827 // base address: 0x1534 1828 #define mmDC_PERFMON5_PERFCOUNTER_CNTL 0x054d 1829 #define mmDC_PERFMON5_PERFCOUNTER_CNTL_BASE_IDX 2 1830 #define mmDC_PERFMON5_PERFCOUNTER_CNTL2 0x054e 1831 #define mmDC_PERFMON5_PERFCOUNTER_CNTL2_BASE_IDX 2 1832 #define mmDC_PERFMON5_PERFCOUNTER_STATE 0x054f 1833 #define mmDC_PERFMON5_PERFCOUNTER_STATE_BASE_IDX 2 1834 #define mmDC_PERFMON5_PERFMON_CNTL 0x0550 1835 #define mmDC_PERFMON5_PERFMON_CNTL_BASE_IDX 2 1836 #define mmDC_PERFMON5_PERFMON_CNTL2 0x0551 1837 #define mmDC_PERFMON5_PERFMON_CNTL2_BASE_IDX 2 1838 #define mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC 0x0552 1839 #define mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 1840 #define mmDC_PERFMON5_PERFMON_CVALUE_LOW 0x0553 1841 #define mmDC_PERFMON5_PERFMON_CVALUE_LOW_BASE_IDX 2 1842 #define mmDC_PERFMON5_PERFMON_HI 0x0554 1843 #define mmDC_PERFMON5_PERFMON_HI_BASE_IDX 2 1844 #define mmDC_PERFMON5_PERFMON_LOW 0x0555 1845 #define mmDC_PERFMON5_PERFMON_LOW_BASE_IDX 2 1846 1847 1848 // addressBlock: dce_dc_dchubbub_hubbub_vmrq_if_dispdec 1849 // base address: 0x0 1850 #define mmDCN_VM_CONTEXT0_CNTL 0x0559 1851 #define mmDCN_VM_CONTEXT0_CNTL_BASE_IDX 2 1852 #define mmDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 0x055a 1853 #define mmDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 1854 #define mmDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 0x055b 1855 #define mmDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 1856 #define mmDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 0x055c 1857 #define mmDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 1858 #define mmDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 0x055d 1859 #define mmDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 1860 #define mmDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 0x055e 1861 #define mmDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 1862 #define mmDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 0x055f 1863 #define mmDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 1864 #define mmDCN_VM_CONTEXT1_CNTL 0x0560 1865 #define mmDCN_VM_CONTEXT1_CNTL_BASE_IDX 2 1866 #define mmDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 0x0561 1867 #define mmDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 1868 #define mmDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 0x0562 1869 #define mmDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 1870 #define mmDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 0x0563 1871 #define mmDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 1872 #define mmDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 0x0564 1873 #define mmDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 1874 #define mmDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 0x0565 1875 #define mmDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 1876 #define mmDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 0x0566 1877 #define mmDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 1878 #define mmDCN_VM_CONTEXT2_CNTL 0x0567 1879 #define mmDCN_VM_CONTEXT2_CNTL_BASE_IDX 2 1880 #define mmDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 0x0568 1881 #define mmDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 1882 #define mmDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 0x0569 1883 #define mmDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 1884 #define mmDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 0x056a 1885 #define mmDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 1886 #define mmDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 0x056b 1887 #define mmDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 1888 #define mmDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 0x056c 1889 #define mmDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 1890 #define mmDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 0x056d 1891 #define mmDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 1892 #define mmDCN_VM_CONTEXT3_CNTL 0x056e 1893 #define mmDCN_VM_CONTEXT3_CNTL_BASE_IDX 2 1894 #define mmDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 0x056f 1895 #define mmDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 1896 #define mmDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 0x0570 1897 #define mmDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 1898 #define mmDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 0x0571 1899 #define mmDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 1900 #define mmDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 0x0572 1901 #define mmDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 1902 #define mmDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 0x0573 1903 #define mmDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 1904 #define mmDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 0x0574 1905 #define mmDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 1906 #define mmDCN_VM_CONTEXT4_CNTL 0x0575 1907 #define mmDCN_VM_CONTEXT4_CNTL_BASE_IDX 2 1908 #define mmDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 0x0576 1909 #define mmDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 1910 #define mmDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 0x0577 1911 #define mmDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 1912 #define mmDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 0x0578 1913 #define mmDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 1914 #define mmDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 0x0579 1915 #define mmDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 1916 #define mmDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 0x057a 1917 #define mmDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 1918 #define mmDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 0x057b 1919 #define mmDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 1920 #define mmDCN_VM_CONTEXT5_CNTL 0x057c 1921 #define mmDCN_VM_CONTEXT5_CNTL_BASE_IDX 2 1922 #define mmDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 0x057d 1923 #define mmDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 1924 #define mmDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 0x057e 1925 #define mmDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 1926 #define mmDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 0x057f 1927 #define mmDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 1928 #define mmDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 0x0580 1929 #define mmDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 1930 #define mmDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 0x0581 1931 #define mmDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 1932 #define mmDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 0x0582 1933 #define mmDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 1934 #define mmDCN_VM_CONTEXT6_CNTL 0x0583 1935 #define mmDCN_VM_CONTEXT6_CNTL_BASE_IDX 2 1936 #define mmDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 0x0584 1937 #define mmDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 1938 #define mmDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 0x0585 1939 #define mmDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 1940 #define mmDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 0x0586 1941 #define mmDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 1942 #define mmDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 0x0587 1943 #define mmDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 1944 #define mmDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 0x0588 1945 #define mmDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 1946 #define mmDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 0x0589 1947 #define mmDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 1948 #define mmDCN_VM_CONTEXT7_CNTL 0x058a 1949 #define mmDCN_VM_CONTEXT7_CNTL_BASE_IDX 2 1950 #define mmDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 0x058b 1951 #define mmDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 1952 #define mmDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 0x058c 1953 #define mmDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 1954 #define mmDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 0x058d 1955 #define mmDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 1956 #define mmDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 0x058e 1957 #define mmDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 1958 #define mmDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 0x058f 1959 #define mmDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 1960 #define mmDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 0x0590 1961 #define mmDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 1962 #define mmDCN_VM_CONTEXT8_CNTL 0x0591 1963 #define mmDCN_VM_CONTEXT8_CNTL_BASE_IDX 2 1964 #define mmDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 0x0592 1965 #define mmDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 1966 #define mmDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 0x0593 1967 #define mmDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 1968 #define mmDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 0x0594 1969 #define mmDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 1970 #define mmDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 0x0595 1971 #define mmDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 1972 #define mmDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 0x0596 1973 #define mmDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 1974 #define mmDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 0x0597 1975 #define mmDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 1976 #define mmDCN_VM_CONTEXT9_CNTL 0x0598 1977 #define mmDCN_VM_CONTEXT9_CNTL_BASE_IDX 2 1978 #define mmDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 0x0599 1979 #define mmDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 1980 #define mmDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 0x059a 1981 #define mmDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 1982 #define mmDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 0x059b 1983 #define mmDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 1984 #define mmDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 0x059c 1985 #define mmDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 1986 #define mmDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 0x059d 1987 #define mmDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 1988 #define mmDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 0x059e 1989 #define mmDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 1990 #define mmDCN_VM_CONTEXT10_CNTL 0x059f 1991 #define mmDCN_VM_CONTEXT10_CNTL_BASE_IDX 2 1992 #define mmDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 0x05a0 1993 #define mmDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 1994 #define mmDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 0x05a1 1995 #define mmDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 1996 #define mmDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 0x05a2 1997 #define mmDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 1998 #define mmDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 0x05a3 1999 #define mmDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 2000 #define mmDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 0x05a4 2001 #define mmDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 2002 #define mmDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 0x05a5 2003 #define mmDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 2004 #define mmDCN_VM_CONTEXT11_CNTL 0x05a6 2005 #define mmDCN_VM_CONTEXT11_CNTL_BASE_IDX 2 2006 #define mmDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 0x05a7 2007 #define mmDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 2008 #define mmDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 0x05a8 2009 #define mmDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 2010 #define mmDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 0x05a9 2011 #define mmDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 2012 #define mmDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 0x05aa 2013 #define mmDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 2014 #define mmDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 0x05ab 2015 #define mmDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 2016 #define mmDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 0x05ac 2017 #define mmDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 2018 #define mmDCN_VM_CONTEXT12_CNTL 0x05ad 2019 #define mmDCN_VM_CONTEXT12_CNTL_BASE_IDX 2 2020 #define mmDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 0x05ae 2021 #define mmDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 2022 #define mmDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 0x05af 2023 #define mmDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 2024 #define mmDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 0x05b0 2025 #define mmDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 2026 #define mmDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 0x05b1 2027 #define mmDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 2028 #define mmDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 0x05b2 2029 #define mmDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 2030 #define mmDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 0x05b3 2031 #define mmDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 2032 #define mmDCN_VM_CONTEXT13_CNTL 0x05b4 2033 #define mmDCN_VM_CONTEXT13_CNTL_BASE_IDX 2 2034 #define mmDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 0x05b5 2035 #define mmDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 2036 #define mmDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 0x05b6 2037 #define mmDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 2038 #define mmDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 0x05b7 2039 #define mmDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 2040 #define mmDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 0x05b8 2041 #define mmDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 2042 #define mmDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 0x05b9 2043 #define mmDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 2044 #define mmDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 0x05ba 2045 #define mmDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 2046 #define mmDCN_VM_CONTEXT14_CNTL 0x05bb 2047 #define mmDCN_VM_CONTEXT14_CNTL_BASE_IDX 2 2048 #define mmDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 0x05bc 2049 #define mmDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 2050 #define mmDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 0x05bd 2051 #define mmDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 2052 #define mmDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 0x05be 2053 #define mmDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 2054 #define mmDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 0x05bf 2055 #define mmDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 2056 #define mmDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 0x05c0 2057 #define mmDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 2058 #define mmDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 0x05c1 2059 #define mmDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 2060 #define mmDCN_VM_CONTEXT15_CNTL 0x05c2 2061 #define mmDCN_VM_CONTEXT15_CNTL_BASE_IDX 2 2062 #define mmDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 0x05c3 2063 #define mmDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 2064 #define mmDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 0x05c4 2065 #define mmDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 2066 #define mmDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 0x05c5 2067 #define mmDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 2068 #define mmDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 0x05c6 2069 #define mmDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 2070 #define mmDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 0x05c7 2071 #define mmDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 2072 #define mmDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 0x05c8 2073 #define mmDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 2074 #define mmDCN_VM_DEFAULT_ADDR_MSB 0x05c9 2075 #define mmDCN_VM_DEFAULT_ADDR_MSB_BASE_IDX 2 2076 #define mmDCN_VM_DEFAULT_ADDR_LSB 0x05ca 2077 #define mmDCN_VM_DEFAULT_ADDR_LSB_BASE_IDX 2 2078 #define mmDCN_VM_FAULT_CNTL 0x05cb 2079 #define mmDCN_VM_FAULT_CNTL_BASE_IDX 2 2080 #define mmDCN_VM_FAULT_STATUS 0x05cc 2081 #define mmDCN_VM_FAULT_STATUS_BASE_IDX 2 2082 #define mmDCN_VM_FAULT_ADDR_MSB 0x05cd 2083 #define mmDCN_VM_FAULT_ADDR_MSB_BASE_IDX 2 2084 #define mmDCN_VM_FAULT_ADDR_LSB 0x05ce 2085 #define mmDCN_VM_FAULT_ADDR_LSB_BASE_IDX 2 2086 2087 2088 // addressBlock: dce_dc_dcbubp0_dispdec_hubp_dispdec 2089 // base address: 0x0 2090 #define mmHUBP0_DCSURF_SURFACE_CONFIG 0x05e5 2091 #define mmHUBP0_DCSURF_SURFACE_CONFIG_BASE_IDX 2 2092 #define mmHUBP0_DCSURF_ADDR_CONFIG 0x05e6 2093 #define mmHUBP0_DCSURF_ADDR_CONFIG_BASE_IDX 2 2094 #define mmHUBP0_DCSURF_TILING_CONFIG 0x05e7 2095 #define mmHUBP0_DCSURF_TILING_CONFIG_BASE_IDX 2 2096 #define mmHUBP0_DCSURF_PRI_VIEWPORT_START 0x05e9 2097 #define mmHUBP0_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2 2098 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION 0x05ea 2099 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 2100 #define mmHUBP0_DCSURF_PRI_VIEWPORT_START_C 0x05eb 2101 #define mmHUBP0_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2 2102 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x05ec 2103 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2 2104 #define mmHUBP0_DCSURF_SEC_VIEWPORT_START 0x05ed 2105 #define mmHUBP0_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2 2106 #define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION 0x05ee 2107 #define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2 2108 #define mmHUBP0_DCSURF_SEC_VIEWPORT_START_C 0x05ef 2109 #define mmHUBP0_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2 2110 #define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x05f0 2111 #define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2 2112 #define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG 0x05f1 2113 #define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2 2114 #define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG_C 0x05f2 2115 #define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2 2116 #define mmHUBP0_DCHUBP_CNTL 0x05f3 2117 #define mmHUBP0_DCHUBP_CNTL_BASE_IDX 2 2118 #define mmHUBP0_HUBP_CLK_CNTL 0x05f4 2119 #define mmHUBP0_HUBP_CLK_CNTL_BASE_IDX 2 2120 #define mmHUBP0_DCHUBP_VMPG_CONFIG 0x05f5 2121 #define mmHUBP0_DCHUBP_VMPG_CONFIG_BASE_IDX 2 2122 #define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x05fb 2123 #define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2 2124 #define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x05fc 2125 #define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2 2126 #define mmHUBP0_HUBPREQ_DEBUG_DB 0x05f6 2127 #define mmHUBP0_HUBPREQ_DEBUG_DB_BASE_IDX 2 2128 #define mmHUBP0_HUBPREQ_DEBUG 0x05f7 2129 #define mmHUBP0_HUBPREQ_DEBUG_BASE_IDX 2 2130 2131 2132 // addressBlock: dce_dc_dcbubp0_dispdec_hubpreq_dispdec 2133 // base address: 0x0 2134 #define mmHUBPREQ0_DCSURF_SURFACE_PITCH 0x0607 2135 #define mmHUBPREQ0_DCSURF_SURFACE_PITCH_BASE_IDX 2 2136 #define mmHUBPREQ0_DCSURF_SURFACE_PITCH_C 0x0608 2137 #define mmHUBPREQ0_DCSURF_SURFACE_PITCH_C_BASE_IDX 2 2138 #define mmHUBPREQ0_VMID_SETTINGS_0 0x0609 2139 #define mmHUBPREQ0_VMID_SETTINGS_0_BASE_IDX 2 2140 #define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS 0x060a 2141 #define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2 2142 #define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x060b 2143 #define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2144 #define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x060c 2145 #define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2 2146 #define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x060d 2147 #define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 2148 #define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS 0x060e 2149 #define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2 2150 #define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x060f 2151 #define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2152 #define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x0610 2153 #define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2 2154 #define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x0611 2155 #define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 2156 #define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x0612 2157 #define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2 2158 #define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x0613 2159 #define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2160 #define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x0614 2161 #define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 2162 #define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x0615 2163 #define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 2164 #define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x0616 2165 #define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2 2166 #define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x0617 2167 #define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2168 #define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x0618 2169 #define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 2170 #define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x0619 2171 #define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 2172 #define mmHUBPREQ0_DCSURF_SURFACE_CONTROL 0x061a 2173 #define mmHUBPREQ0_DCSURF_SURFACE_CONTROL_BASE_IDX 2 2174 #define mmHUBPREQ0_DCSURF_FLIP_CONTROL 0x061b 2175 #define mmHUBPREQ0_DCSURF_FLIP_CONTROL_BASE_IDX 2 2176 #define mmHUBPREQ0_DCSURF_FLIP_CONTROL2 0x061c 2177 #define mmHUBPREQ0_DCSURF_FLIP_CONTROL2_BASE_IDX 2 2178 #define mmHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT 0x0620 2179 #define mmHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2 2180 #define mmHUBPREQ0_DCSURF_SURFACE_INUSE 0x0621 2181 #define mmHUBPREQ0_DCSURF_SURFACE_INUSE_BASE_IDX 2 2182 #define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH 0x0622 2183 #define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2 2184 #define mmHUBPREQ0_DCSURF_SURFACE_INUSE_C 0x0623 2185 #define mmHUBPREQ0_DCSURF_SURFACE_INUSE_C_BASE_IDX 2 2186 #define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C 0x0624 2187 #define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2 2188 #define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE 0x0625 2189 #define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2 2190 #define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x0626 2191 #define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2 2192 #define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C 0x0627 2193 #define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2 2194 #define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x0628 2195 #define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2 2196 #define mmHUBPREQ0_DCN_EXPANSION_MODE 0x0629 2197 #define mmHUBPREQ0_DCN_EXPANSION_MODE_BASE_IDX 2 2198 #define mmHUBPREQ0_DCN_TTU_QOS_WM 0x062a 2199 #define mmHUBPREQ0_DCN_TTU_QOS_WM_BASE_IDX 2 2200 #define mmHUBPREQ0_DCN_GLOBAL_TTU_CNTL 0x062b 2201 #define mmHUBPREQ0_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2 2202 #define mmHUBPREQ0_DCN_SURF0_TTU_CNTL0 0x062c 2203 #define mmHUBPREQ0_DCN_SURF0_TTU_CNTL0_BASE_IDX 2 2204 #define mmHUBPREQ0_DCN_SURF0_TTU_CNTL1 0x062d 2205 #define mmHUBPREQ0_DCN_SURF0_TTU_CNTL1_BASE_IDX 2 2206 #define mmHUBPREQ0_DCN_SURF1_TTU_CNTL0 0x062e 2207 #define mmHUBPREQ0_DCN_SURF1_TTU_CNTL0_BASE_IDX 2 2208 #define mmHUBPREQ0_DCN_SURF1_TTU_CNTL1 0x062f 2209 #define mmHUBPREQ0_DCN_SURF1_TTU_CNTL1_BASE_IDX 2 2210 #define mmHUBPREQ0_DCN_CUR0_TTU_CNTL0 0x0630 2211 #define mmHUBPREQ0_DCN_CUR0_TTU_CNTL0_BASE_IDX 2 2212 #define mmHUBPREQ0_DCN_CUR0_TTU_CNTL1 0x0631 2213 #define mmHUBPREQ0_DCN_CUR0_TTU_CNTL1_BASE_IDX 2 2214 #define mmHUBPREQ0_DCN_CUR1_TTU_CNTL0 0x0632 2215 #define mmHUBPREQ0_DCN_CUR1_TTU_CNTL0_BASE_IDX 2 2216 #define mmHUBPREQ0_DCN_CUR1_TTU_CNTL1 0x0633 2217 #define mmHUBPREQ0_DCN_CUR1_TTU_CNTL1_BASE_IDX 2 2218 #define mmHUBPREQ0_DCN_DMDATA_VM_CNTL 0x0634 2219 #define mmHUBPREQ0_DCN_DMDATA_VM_CNTL_BASE_IDX 2 2220 #define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x0635 2221 #define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2 2222 #define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x0636 2223 #define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2 2224 #define mmHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL 0x0643 2225 #define mmHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2 2226 #define mmHUBPREQ0_BLANK_OFFSET_0 0x0644 2227 #define mmHUBPREQ0_BLANK_OFFSET_0_BASE_IDX 2 2228 #define mmHUBPREQ0_BLANK_OFFSET_1 0x0645 2229 #define mmHUBPREQ0_BLANK_OFFSET_1_BASE_IDX 2 2230 #define mmHUBPREQ0_DST_DIMENSIONS 0x0646 2231 #define mmHUBPREQ0_DST_DIMENSIONS_BASE_IDX 2 2232 #define mmHUBPREQ0_DST_AFTER_SCALER 0x0647 2233 #define mmHUBPREQ0_DST_AFTER_SCALER_BASE_IDX 2 2234 #define mmHUBPREQ0_PREFETCH_SETTINGS 0x0648 2235 #define mmHUBPREQ0_PREFETCH_SETTINGS_BASE_IDX 2 2236 #define mmHUBPREQ0_PREFETCH_SETTINGS_C 0x0649 2237 #define mmHUBPREQ0_PREFETCH_SETTINGS_C_BASE_IDX 2 2238 #define mmHUBPREQ0_VBLANK_PARAMETERS_0 0x064a 2239 #define mmHUBPREQ0_VBLANK_PARAMETERS_0_BASE_IDX 2 2240 #define mmHUBPREQ0_VBLANK_PARAMETERS_1 0x064b 2241 #define mmHUBPREQ0_VBLANK_PARAMETERS_1_BASE_IDX 2 2242 #define mmHUBPREQ0_VBLANK_PARAMETERS_2 0x064c 2243 #define mmHUBPREQ0_VBLANK_PARAMETERS_2_BASE_IDX 2 2244 #define mmHUBPREQ0_VBLANK_PARAMETERS_3 0x064d 2245 #define mmHUBPREQ0_VBLANK_PARAMETERS_3_BASE_IDX 2 2246 #define mmHUBPREQ0_VBLANK_PARAMETERS_4 0x064e 2247 #define mmHUBPREQ0_VBLANK_PARAMETERS_4_BASE_IDX 2 2248 #define mmHUBPREQ0_FLIP_PARAMETERS_0 0x064f 2249 #define mmHUBPREQ0_FLIP_PARAMETERS_0_BASE_IDX 2 2250 #define mmHUBPREQ0_FLIP_PARAMETERS_1 0x0650 2251 #define mmHUBPREQ0_FLIP_PARAMETERS_1_BASE_IDX 2 2252 #define mmHUBPREQ0_FLIP_PARAMETERS_2 0x0651 2253 #define mmHUBPREQ0_FLIP_PARAMETERS_2_BASE_IDX 2 2254 #define mmHUBPREQ0_NOM_PARAMETERS_0 0x0652 2255 #define mmHUBPREQ0_NOM_PARAMETERS_0_BASE_IDX 2 2256 #define mmHUBPREQ0_NOM_PARAMETERS_1 0x0653 2257 #define mmHUBPREQ0_NOM_PARAMETERS_1_BASE_IDX 2 2258 #define mmHUBPREQ0_NOM_PARAMETERS_2 0x0654 2259 #define mmHUBPREQ0_NOM_PARAMETERS_2_BASE_IDX 2 2260 #define mmHUBPREQ0_NOM_PARAMETERS_3 0x0655 2261 #define mmHUBPREQ0_NOM_PARAMETERS_3_BASE_IDX 2 2262 #define mmHUBPREQ0_NOM_PARAMETERS_4 0x0656 2263 #define mmHUBPREQ0_NOM_PARAMETERS_4_BASE_IDX 2 2264 #define mmHUBPREQ0_NOM_PARAMETERS_5 0x0657 2265 #define mmHUBPREQ0_NOM_PARAMETERS_5_BASE_IDX 2 2266 #define mmHUBPREQ0_NOM_PARAMETERS_6 0x0658 2267 #define mmHUBPREQ0_NOM_PARAMETERS_6_BASE_IDX 2 2268 #define mmHUBPREQ0_NOM_PARAMETERS_7 0x0659 2269 #define mmHUBPREQ0_NOM_PARAMETERS_7_BASE_IDX 2 2270 #define mmHUBPREQ0_PER_LINE_DELIVERY_PRE 0x065a 2271 #define mmHUBPREQ0_PER_LINE_DELIVERY_PRE_BASE_IDX 2 2272 #define mmHUBPREQ0_PER_LINE_DELIVERY 0x065b 2273 #define mmHUBPREQ0_PER_LINE_DELIVERY_BASE_IDX 2 2274 #define mmHUBPREQ0_CURSOR_SETTINGS 0x065c 2275 #define mmHUBPREQ0_CURSOR_SETTINGS_BASE_IDX 2 2276 #define mmHUBPREQ0_REF_FREQ_TO_PIX_FREQ 0x065d 2277 #define mmHUBPREQ0_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2 2278 #define mmHUBPREQ0_DST_Y_DELTA_DRQ_LIMIT 0x065e 2279 #define mmHUBPREQ0_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2 2280 #define mmHUBPREQ0_HUBPREQ_MEM_PWR_CTRL 0x065f 2281 #define mmHUBPREQ0_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2 2282 #define mmHUBPREQ0_HUBPREQ_MEM_PWR_STATUS 0x0660 2283 #define mmHUBPREQ0_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2 2284 #define mmHUBPREQ0_VBLANK_PARAMETERS_5 0x0663 2285 #define mmHUBPREQ0_VBLANK_PARAMETERS_5_BASE_IDX 2 2286 #define mmHUBPREQ0_VBLANK_PARAMETERS_6 0x0664 2287 #define mmHUBPREQ0_VBLANK_PARAMETERS_6_BASE_IDX 2 2288 #define mmHUBPREQ0_FLIP_PARAMETERS_3 0x0665 2289 #define mmHUBPREQ0_FLIP_PARAMETERS_3_BASE_IDX 2 2290 #define mmHUBPREQ0_FLIP_PARAMETERS_4 0x0666 2291 #define mmHUBPREQ0_FLIP_PARAMETERS_4_BASE_IDX 2 2292 #define mmHUBPREQ0_FLIP_PARAMETERS_5 0x0667 2293 #define mmHUBPREQ0_FLIP_PARAMETERS_5_BASE_IDX 2 2294 #define mmHUBPREQ0_FLIP_PARAMETERS_6 0x0668 2295 #define mmHUBPREQ0_FLIP_PARAMETERS_6_BASE_IDX 2 2296 2297 2298 // addressBlock: dce_dc_dcbubp0_dispdec_hubpret_dispdec 2299 // base address: 0x0 2300 #define mmHUBPRET0_HUBPRET_CONTROL 0x066c 2301 #define mmHUBPRET0_HUBPRET_CONTROL_BASE_IDX 2 2302 #define mmHUBPRET0_HUBPRET_MEM_PWR_CTRL 0x066d 2303 #define mmHUBPRET0_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2 2304 #define mmHUBPRET0_HUBPRET_MEM_PWR_STATUS 0x066e 2305 #define mmHUBPRET0_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2 2306 #define mmHUBPRET0_HUBPRET_READ_LINE_CTRL0 0x066f 2307 #define mmHUBPRET0_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2 2308 #define mmHUBPRET0_HUBPRET_READ_LINE_CTRL1 0x0670 2309 #define mmHUBPRET0_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2 2310 #define mmHUBPRET0_HUBPRET_READ_LINE0 0x0671 2311 #define mmHUBPRET0_HUBPRET_READ_LINE0_BASE_IDX 2 2312 #define mmHUBPRET0_HUBPRET_READ_LINE1 0x0672 2313 #define mmHUBPRET0_HUBPRET_READ_LINE1_BASE_IDX 2 2314 #define mmHUBPRET0_HUBPRET_INTERRUPT 0x0673 2315 #define mmHUBPRET0_HUBPRET_INTERRUPT_BASE_IDX 2 2316 #define mmHUBPRET0_HUBPRET_READ_LINE_VALUE 0x0674 2317 #define mmHUBPRET0_HUBPRET_READ_LINE_VALUE_BASE_IDX 2 2318 #define mmHUBPRET0_HUBPRET_READ_LINE_STATUS 0x0675 2319 #define mmHUBPRET0_HUBPRET_READ_LINE_STATUS_BASE_IDX 2 2320 2321 2322 // addressBlock: dce_dc_dcbubp0_dispdec_cursor0_dispdec 2323 // base address: 0x0 2324 #define mmCURSOR0_0_CURSOR_CONTROL 0x0678 2325 #define mmCURSOR0_0_CURSOR_CONTROL_BASE_IDX 2 2326 #define mmCURSOR0_0_CURSOR_SURFACE_ADDRESS 0x0679 2327 #define mmCURSOR0_0_CURSOR_SURFACE_ADDRESS_BASE_IDX 2 2328 #define mmCURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH 0x067a 2329 #define mmCURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2330 #define mmCURSOR0_0_CURSOR_SIZE 0x067b 2331 #define mmCURSOR0_0_CURSOR_SIZE_BASE_IDX 2 2332 #define mmCURSOR0_0_CURSOR_POSITION 0x067c 2333 #define mmCURSOR0_0_CURSOR_POSITION_BASE_IDX 2 2334 #define mmCURSOR0_0_CURSOR_HOT_SPOT 0x067d 2335 #define mmCURSOR0_0_CURSOR_HOT_SPOT_BASE_IDX 2 2336 #define mmCURSOR0_0_CURSOR_STEREO_CONTROL 0x067e 2337 #define mmCURSOR0_0_CURSOR_STEREO_CONTROL_BASE_IDX 2 2338 #define mmCURSOR0_0_CURSOR_DST_OFFSET 0x067f 2339 #define mmCURSOR0_0_CURSOR_DST_OFFSET_BASE_IDX 2 2340 #define mmCURSOR0_0_CURSOR_MEM_PWR_CTRL 0x0680 2341 #define mmCURSOR0_0_CURSOR_MEM_PWR_CTRL_BASE_IDX 2 2342 #define mmCURSOR0_0_CURSOR_MEM_PWR_STATUS 0x0681 2343 #define mmCURSOR0_0_CURSOR_MEM_PWR_STATUS_BASE_IDX 2 2344 #define mmCURSOR0_0_DMDATA_ADDRESS_HIGH 0x0682 2345 #define mmCURSOR0_0_DMDATA_ADDRESS_HIGH_BASE_IDX 2 2346 #define mmCURSOR0_0_DMDATA_ADDRESS_LOW 0x0683 2347 #define mmCURSOR0_0_DMDATA_ADDRESS_LOW_BASE_IDX 2 2348 #define mmCURSOR0_0_DMDATA_CNTL 0x0684 2349 #define mmCURSOR0_0_DMDATA_CNTL_BASE_IDX 2 2350 #define mmCURSOR0_0_DMDATA_QOS_CNTL 0x0685 2351 #define mmCURSOR0_0_DMDATA_QOS_CNTL_BASE_IDX 2 2352 #define mmCURSOR0_0_DMDATA_STATUS 0x0686 2353 #define mmCURSOR0_0_DMDATA_STATUS_BASE_IDX 2 2354 #define mmCURSOR0_0_DMDATA_SW_CNTL 0x0687 2355 #define mmCURSOR0_0_DMDATA_SW_CNTL_BASE_IDX 2 2356 #define mmCURSOR0_0_DMDATA_SW_DATA 0x0688 2357 #define mmCURSOR0_0_DMDATA_SW_DATA_BASE_IDX 2 2358 2359 2360 // addressBlock: dce_dc_dcbubp0_dispdec_hubp_dcperfmon_dc_perfmon_dispdec 2361 // base address: 0x1a74 2362 #define mmDC_PERFMON6_PERFCOUNTER_CNTL 0x069d 2363 #define mmDC_PERFMON6_PERFCOUNTER_CNTL_BASE_IDX 2 2364 #define mmDC_PERFMON6_PERFCOUNTER_CNTL2 0x069e 2365 #define mmDC_PERFMON6_PERFCOUNTER_CNTL2_BASE_IDX 2 2366 #define mmDC_PERFMON6_PERFCOUNTER_STATE 0x069f 2367 #define mmDC_PERFMON6_PERFCOUNTER_STATE_BASE_IDX 2 2368 #define mmDC_PERFMON6_PERFMON_CNTL 0x06a0 2369 #define mmDC_PERFMON6_PERFMON_CNTL_BASE_IDX 2 2370 #define mmDC_PERFMON6_PERFMON_CNTL2 0x06a1 2371 #define mmDC_PERFMON6_PERFMON_CNTL2_BASE_IDX 2 2372 #define mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC 0x06a2 2373 #define mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 2374 #define mmDC_PERFMON6_PERFMON_CVALUE_LOW 0x06a3 2375 #define mmDC_PERFMON6_PERFMON_CVALUE_LOW_BASE_IDX 2 2376 #define mmDC_PERFMON6_PERFMON_HI 0x06a4 2377 #define mmDC_PERFMON6_PERFMON_HI_BASE_IDX 2 2378 #define mmDC_PERFMON6_PERFMON_LOW 0x06a5 2379 #define mmDC_PERFMON6_PERFMON_LOW_BASE_IDX 2 2380 2381 2382 // addressBlock: dce_dc_dcbubp1_dispdec_hubp_dispdec 2383 // base address: 0x370 2384 #define mmHUBP1_DCSURF_SURFACE_CONFIG 0x06c1 2385 #define mmHUBP1_DCSURF_SURFACE_CONFIG_BASE_IDX 2 2386 #define mmHUBP1_DCSURF_ADDR_CONFIG 0x06c2 2387 #define mmHUBP1_DCSURF_ADDR_CONFIG_BASE_IDX 2 2388 #define mmHUBP1_DCSURF_TILING_CONFIG 0x06c3 2389 #define mmHUBP1_DCSURF_TILING_CONFIG_BASE_IDX 2 2390 #define mmHUBP1_DCSURF_PRI_VIEWPORT_START 0x06c5 2391 #define mmHUBP1_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2 2392 #define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION 0x06c6 2393 #define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 2394 #define mmHUBP1_DCSURF_PRI_VIEWPORT_START_C 0x06c7 2395 #define mmHUBP1_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2 2396 #define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x06c8 2397 #define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2 2398 #define mmHUBP1_DCSURF_SEC_VIEWPORT_START 0x06c9 2399 #define mmHUBP1_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2 2400 #define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION 0x06ca 2401 #define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2 2402 #define mmHUBP1_DCSURF_SEC_VIEWPORT_START_C 0x06cb 2403 #define mmHUBP1_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2 2404 #define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x06cc 2405 #define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2 2406 #define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG 0x06cd 2407 #define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2 2408 #define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG_C 0x06ce 2409 #define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2 2410 #define mmHUBP1_DCHUBP_CNTL 0x06cf 2411 #define mmHUBP1_DCHUBP_CNTL_BASE_IDX 2 2412 #define mmHUBP1_HUBP_CLK_CNTL 0x06d0 2413 #define mmHUBP1_HUBP_CLK_CNTL_BASE_IDX 2 2414 #define mmHUBP1_DCHUBP_VMPG_CONFIG 0x06d1 2415 #define mmHUBP1_DCHUBP_VMPG_CONFIG_BASE_IDX 2 2416 #define mmHUBP1_HUBPREQ_DEBUG_DB 0x06d2 2417 #define mmHUBP1_HUBPREQ_DEBUG_DB_BASE_IDX 2 2418 #define mmHUBP1_HUBPREQ_DEBUG 0x06d3 2419 #define mmHUBP1_HUBPREQ_DEBUG_BASE_IDX 2 2420 #define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x06d7 2421 #define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2 2422 #define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x06d8 2423 #define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2 2424 2425 2426 // addressBlock: dce_dc_dcbubp1_dispdec_hubpreq_dispdec 2427 // base address: 0x370 2428 #define mmHUBPREQ1_DCSURF_SURFACE_PITCH 0x06e3 2429 #define mmHUBPREQ1_DCSURF_SURFACE_PITCH_BASE_IDX 2 2430 #define mmHUBPREQ1_DCSURF_SURFACE_PITCH_C 0x06e4 2431 #define mmHUBPREQ1_DCSURF_SURFACE_PITCH_C_BASE_IDX 2 2432 #define mmHUBPREQ1_VMID_SETTINGS_0 0x06e5 2433 #define mmHUBPREQ1_VMID_SETTINGS_0_BASE_IDX 2 2434 #define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS 0x06e6 2435 #define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2 2436 #define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x06e7 2437 #define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2438 #define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x06e8 2439 #define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2 2440 #define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x06e9 2441 #define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 2442 #define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS 0x06ea 2443 #define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2 2444 #define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x06eb 2445 #define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2446 #define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x06ec 2447 #define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2 2448 #define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x06ed 2449 #define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 2450 #define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x06ee 2451 #define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2 2452 #define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x06ef 2453 #define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2454 #define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x06f0 2455 #define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 2456 #define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x06f1 2457 #define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 2458 #define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x06f2 2459 #define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2 2460 #define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x06f3 2461 #define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2462 #define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x06f4 2463 #define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 2464 #define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x06f5 2465 #define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 2466 #define mmHUBPREQ1_DCSURF_SURFACE_CONTROL 0x06f6 2467 #define mmHUBPREQ1_DCSURF_SURFACE_CONTROL_BASE_IDX 2 2468 #define mmHUBPREQ1_DCSURF_FLIP_CONTROL 0x06f7 2469 #define mmHUBPREQ1_DCSURF_FLIP_CONTROL_BASE_IDX 2 2470 #define mmHUBPREQ1_DCSURF_FLIP_CONTROL2 0x06f8 2471 #define mmHUBPREQ1_DCSURF_FLIP_CONTROL2_BASE_IDX 2 2472 #define mmHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT 0x06fc 2473 #define mmHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2 2474 #define mmHUBPREQ1_DCSURF_SURFACE_INUSE 0x06fd 2475 #define mmHUBPREQ1_DCSURF_SURFACE_INUSE_BASE_IDX 2 2476 #define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH 0x06fe 2477 #define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2 2478 #define mmHUBPREQ1_DCSURF_SURFACE_INUSE_C 0x06ff 2479 #define mmHUBPREQ1_DCSURF_SURFACE_INUSE_C_BASE_IDX 2 2480 #define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C 0x0700 2481 #define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2 2482 #define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE 0x0701 2483 #define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2 2484 #define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x0702 2485 #define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2 2486 #define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C 0x0703 2487 #define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2 2488 #define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x0704 2489 #define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2 2490 #define mmHUBPREQ1_DCN_EXPANSION_MODE 0x0705 2491 #define mmHUBPREQ1_DCN_EXPANSION_MODE_BASE_IDX 2 2492 #define mmHUBPREQ1_DCN_TTU_QOS_WM 0x0706 2493 #define mmHUBPREQ1_DCN_TTU_QOS_WM_BASE_IDX 2 2494 #define mmHUBPREQ1_DCN_GLOBAL_TTU_CNTL 0x0707 2495 #define mmHUBPREQ1_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2 2496 #define mmHUBPREQ1_DCN_SURF0_TTU_CNTL0 0x0708 2497 #define mmHUBPREQ1_DCN_SURF0_TTU_CNTL0_BASE_IDX 2 2498 #define mmHUBPREQ1_DCN_SURF0_TTU_CNTL1 0x0709 2499 #define mmHUBPREQ1_DCN_SURF0_TTU_CNTL1_BASE_IDX 2 2500 #define mmHUBPREQ1_DCN_SURF1_TTU_CNTL0 0x070a 2501 #define mmHUBPREQ1_DCN_SURF1_TTU_CNTL0_BASE_IDX 2 2502 #define mmHUBPREQ1_DCN_SURF1_TTU_CNTL1 0x070b 2503 #define mmHUBPREQ1_DCN_SURF1_TTU_CNTL1_BASE_IDX 2 2504 #define mmHUBPREQ1_DCN_CUR0_TTU_CNTL0 0x070c 2505 #define mmHUBPREQ1_DCN_CUR0_TTU_CNTL0_BASE_IDX 2 2506 #define mmHUBPREQ1_DCN_CUR0_TTU_CNTL1 0x070d 2507 #define mmHUBPREQ1_DCN_CUR0_TTU_CNTL1_BASE_IDX 2 2508 #define mmHUBPREQ1_DCN_CUR1_TTU_CNTL0 0x070e 2509 #define mmHUBPREQ1_DCN_CUR1_TTU_CNTL0_BASE_IDX 2 2510 #define mmHUBPREQ1_DCN_CUR1_TTU_CNTL1 0x070f 2511 #define mmHUBPREQ1_DCN_CUR1_TTU_CNTL1_BASE_IDX 2 2512 #define mmHUBPREQ1_DCN_DMDATA_VM_CNTL 0x0710 2513 #define mmHUBPREQ1_DCN_DMDATA_VM_CNTL_BASE_IDX 2 2514 #define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x0711 2515 #define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2 2516 #define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x0712 2517 #define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2 2518 #define mmHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL 0x071f 2519 #define mmHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2 2520 #define mmHUBPREQ1_BLANK_OFFSET_0 0x0720 2521 #define mmHUBPREQ1_BLANK_OFFSET_0_BASE_IDX 2 2522 #define mmHUBPREQ1_BLANK_OFFSET_1 0x0721 2523 #define mmHUBPREQ1_BLANK_OFFSET_1_BASE_IDX 2 2524 #define mmHUBPREQ1_DST_DIMENSIONS 0x0722 2525 #define mmHUBPREQ1_DST_DIMENSIONS_BASE_IDX 2 2526 #define mmHUBPREQ1_DST_AFTER_SCALER 0x0723 2527 #define mmHUBPREQ1_DST_AFTER_SCALER_BASE_IDX 2 2528 #define mmHUBPREQ1_PREFETCH_SETTINGS 0x0724 2529 #define mmHUBPREQ1_PREFETCH_SETTINGS_BASE_IDX 2 2530 #define mmHUBPREQ1_PREFETCH_SETTINGS_C 0x0725 2531 #define mmHUBPREQ1_PREFETCH_SETTINGS_C_BASE_IDX 2 2532 #define mmHUBPREQ1_VBLANK_PARAMETERS_0 0x0726 2533 #define mmHUBPREQ1_VBLANK_PARAMETERS_0_BASE_IDX 2 2534 #define mmHUBPREQ1_VBLANK_PARAMETERS_1 0x0727 2535 #define mmHUBPREQ1_VBLANK_PARAMETERS_1_BASE_IDX 2 2536 #define mmHUBPREQ1_VBLANK_PARAMETERS_2 0x0728 2537 #define mmHUBPREQ1_VBLANK_PARAMETERS_2_BASE_IDX 2 2538 #define mmHUBPREQ1_VBLANK_PARAMETERS_3 0x0729 2539 #define mmHUBPREQ1_VBLANK_PARAMETERS_3_BASE_IDX 2 2540 #define mmHUBPREQ1_VBLANK_PARAMETERS_4 0x072a 2541 #define mmHUBPREQ1_VBLANK_PARAMETERS_4_BASE_IDX 2 2542 #define mmHUBPREQ1_FLIP_PARAMETERS_0 0x072b 2543 #define mmHUBPREQ1_FLIP_PARAMETERS_0_BASE_IDX 2 2544 #define mmHUBPREQ1_FLIP_PARAMETERS_1 0x072c 2545 #define mmHUBPREQ1_FLIP_PARAMETERS_1_BASE_IDX 2 2546 #define mmHUBPREQ1_FLIP_PARAMETERS_2 0x072d 2547 #define mmHUBPREQ1_FLIP_PARAMETERS_2_BASE_IDX 2 2548 #define mmHUBPREQ1_NOM_PARAMETERS_0 0x072e 2549 #define mmHUBPREQ1_NOM_PARAMETERS_0_BASE_IDX 2 2550 #define mmHUBPREQ1_NOM_PARAMETERS_1 0x072f 2551 #define mmHUBPREQ1_NOM_PARAMETERS_1_BASE_IDX 2 2552 #define mmHUBPREQ1_NOM_PARAMETERS_2 0x0730 2553 #define mmHUBPREQ1_NOM_PARAMETERS_2_BASE_IDX 2 2554 #define mmHUBPREQ1_NOM_PARAMETERS_3 0x0731 2555 #define mmHUBPREQ1_NOM_PARAMETERS_3_BASE_IDX 2 2556 #define mmHUBPREQ1_NOM_PARAMETERS_4 0x0732 2557 #define mmHUBPREQ1_NOM_PARAMETERS_4_BASE_IDX 2 2558 #define mmHUBPREQ1_NOM_PARAMETERS_5 0x0733 2559 #define mmHUBPREQ1_NOM_PARAMETERS_5_BASE_IDX 2 2560 #define mmHUBPREQ1_NOM_PARAMETERS_6 0x0734 2561 #define mmHUBPREQ1_NOM_PARAMETERS_6_BASE_IDX 2 2562 #define mmHUBPREQ1_NOM_PARAMETERS_7 0x0735 2563 #define mmHUBPREQ1_NOM_PARAMETERS_7_BASE_IDX 2 2564 #define mmHUBPREQ1_PER_LINE_DELIVERY_PRE 0x0736 2565 #define mmHUBPREQ1_PER_LINE_DELIVERY_PRE_BASE_IDX 2 2566 #define mmHUBPREQ1_PER_LINE_DELIVERY 0x0737 2567 #define mmHUBPREQ1_PER_LINE_DELIVERY_BASE_IDX 2 2568 #define mmHUBPREQ1_CURSOR_SETTINGS 0x0738 2569 #define mmHUBPREQ1_CURSOR_SETTINGS_BASE_IDX 2 2570 #define mmHUBPREQ1_REF_FREQ_TO_PIX_FREQ 0x0739 2571 #define mmHUBPREQ1_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2 2572 #define mmHUBPREQ1_DST_Y_DELTA_DRQ_LIMIT 0x073a 2573 #define mmHUBPREQ1_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2 2574 #define mmHUBPREQ1_HUBPREQ_MEM_PWR_CTRL 0x073b 2575 #define mmHUBPREQ1_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2 2576 #define mmHUBPREQ1_HUBPREQ_MEM_PWR_STATUS 0x073c 2577 #define mmHUBPREQ1_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2 2578 #define mmHUBPREQ1_VBLANK_PARAMETERS_5 0x073f 2579 #define mmHUBPREQ1_VBLANK_PARAMETERS_5_BASE_IDX 2 2580 #define mmHUBPREQ1_VBLANK_PARAMETERS_6 0x0740 2581 #define mmHUBPREQ1_VBLANK_PARAMETERS_6_BASE_IDX 2 2582 #define mmHUBPREQ1_FLIP_PARAMETERS_3 0x0741 2583 #define mmHUBPREQ1_FLIP_PARAMETERS_3_BASE_IDX 2 2584 #define mmHUBPREQ1_FLIP_PARAMETERS_4 0x0742 2585 #define mmHUBPREQ1_FLIP_PARAMETERS_4_BASE_IDX 2 2586 #define mmHUBPREQ1_FLIP_PARAMETERS_5 0x0743 2587 #define mmHUBPREQ1_FLIP_PARAMETERS_5_BASE_IDX 2 2588 #define mmHUBPREQ1_FLIP_PARAMETERS_6 0x0744 2589 #define mmHUBPREQ1_FLIP_PARAMETERS_6_BASE_IDX 2 2590 2591 2592 // addressBlock: dce_dc_dcbubp1_dispdec_hubpret_dispdec 2593 // base address: 0x370 2594 #define mmHUBPRET1_HUBPRET_CONTROL 0x0748 2595 #define mmHUBPRET1_HUBPRET_CONTROL_BASE_IDX 2 2596 #define mmHUBPRET1_HUBPRET_MEM_PWR_CTRL 0x0749 2597 #define mmHUBPRET1_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2 2598 #define mmHUBPRET1_HUBPRET_MEM_PWR_STATUS 0x074a 2599 #define mmHUBPRET1_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2 2600 #define mmHUBPRET1_HUBPRET_READ_LINE_CTRL0 0x074b 2601 #define mmHUBPRET1_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2 2602 #define mmHUBPRET1_HUBPRET_READ_LINE_CTRL1 0x074c 2603 #define mmHUBPRET1_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2 2604 #define mmHUBPRET1_HUBPRET_READ_LINE0 0x074d 2605 #define mmHUBPRET1_HUBPRET_READ_LINE0_BASE_IDX 2 2606 #define mmHUBPRET1_HUBPRET_READ_LINE1 0x074e 2607 #define mmHUBPRET1_HUBPRET_READ_LINE1_BASE_IDX 2 2608 #define mmHUBPRET1_HUBPRET_INTERRUPT 0x074f 2609 #define mmHUBPRET1_HUBPRET_INTERRUPT_BASE_IDX 2 2610 #define mmHUBPRET1_HUBPRET_READ_LINE_VALUE 0x0750 2611 #define mmHUBPRET1_HUBPRET_READ_LINE_VALUE_BASE_IDX 2 2612 #define mmHUBPRET1_HUBPRET_READ_LINE_STATUS 0x0751 2613 #define mmHUBPRET1_HUBPRET_READ_LINE_STATUS_BASE_IDX 2 2614 2615 2616 // addressBlock: dce_dc_dcbubp1_dispdec_cursor0_dispdec 2617 // base address: 0x370 2618 #define mmCURSOR0_1_CURSOR_CONTROL 0x0754 2619 #define mmCURSOR0_1_CURSOR_CONTROL_BASE_IDX 2 2620 #define mmCURSOR0_1_CURSOR_SURFACE_ADDRESS 0x0755 2621 #define mmCURSOR0_1_CURSOR_SURFACE_ADDRESS_BASE_IDX 2 2622 #define mmCURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH 0x0756 2623 #define mmCURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2624 #define mmCURSOR0_1_CURSOR_SIZE 0x0757 2625 #define mmCURSOR0_1_CURSOR_SIZE_BASE_IDX 2 2626 #define mmCURSOR0_1_CURSOR_POSITION 0x0758 2627 #define mmCURSOR0_1_CURSOR_POSITION_BASE_IDX 2 2628 #define mmCURSOR0_1_CURSOR_HOT_SPOT 0x0759 2629 #define mmCURSOR0_1_CURSOR_HOT_SPOT_BASE_IDX 2 2630 #define mmCURSOR0_1_CURSOR_STEREO_CONTROL 0x075a 2631 #define mmCURSOR0_1_CURSOR_STEREO_CONTROL_BASE_IDX 2 2632 #define mmCURSOR0_1_CURSOR_DST_OFFSET 0x075b 2633 #define mmCURSOR0_1_CURSOR_DST_OFFSET_BASE_IDX 2 2634 #define mmCURSOR0_1_CURSOR_MEM_PWR_CTRL 0x075c 2635 #define mmCURSOR0_1_CURSOR_MEM_PWR_CTRL_BASE_IDX 2 2636 #define mmCURSOR0_1_CURSOR_MEM_PWR_STATUS 0x075d 2637 #define mmCURSOR0_1_CURSOR_MEM_PWR_STATUS_BASE_IDX 2 2638 #define mmCURSOR0_1_DMDATA_ADDRESS_HIGH 0x075e 2639 #define mmCURSOR0_1_DMDATA_ADDRESS_HIGH_BASE_IDX 2 2640 #define mmCURSOR0_1_DMDATA_ADDRESS_LOW 0x075f 2641 #define mmCURSOR0_1_DMDATA_ADDRESS_LOW_BASE_IDX 2 2642 #define mmCURSOR0_1_DMDATA_CNTL 0x0760 2643 #define mmCURSOR0_1_DMDATA_CNTL_BASE_IDX 2 2644 #define mmCURSOR0_1_DMDATA_QOS_CNTL 0x0761 2645 #define mmCURSOR0_1_DMDATA_QOS_CNTL_BASE_IDX 2 2646 #define mmCURSOR0_1_DMDATA_STATUS 0x0762 2647 #define mmCURSOR0_1_DMDATA_STATUS_BASE_IDX 2 2648 #define mmCURSOR0_1_DMDATA_SW_CNTL 0x0763 2649 #define mmCURSOR0_1_DMDATA_SW_CNTL_BASE_IDX 2 2650 #define mmCURSOR0_1_DMDATA_SW_DATA 0x0764 2651 #define mmCURSOR0_1_DMDATA_SW_DATA_BASE_IDX 2 2652 2653 2654 // addressBlock: dce_dc_dcbubp1_dispdec_hubp_dcperfmon_dc_perfmon_dispdec 2655 // base address: 0x1de4 2656 #define mmDC_PERFMON7_PERFCOUNTER_CNTL 0x0779 2657 #define mmDC_PERFMON7_PERFCOUNTER_CNTL_BASE_IDX 2 2658 #define mmDC_PERFMON7_PERFCOUNTER_CNTL2 0x077a 2659 #define mmDC_PERFMON7_PERFCOUNTER_CNTL2_BASE_IDX 2 2660 #define mmDC_PERFMON7_PERFCOUNTER_STATE 0x077b 2661 #define mmDC_PERFMON7_PERFCOUNTER_STATE_BASE_IDX 2 2662 #define mmDC_PERFMON7_PERFMON_CNTL 0x077c 2663 #define mmDC_PERFMON7_PERFMON_CNTL_BASE_IDX 2 2664 #define mmDC_PERFMON7_PERFMON_CNTL2 0x077d 2665 #define mmDC_PERFMON7_PERFMON_CNTL2_BASE_IDX 2 2666 #define mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC 0x077e 2667 #define mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 2668 #define mmDC_PERFMON7_PERFMON_CVALUE_LOW 0x077f 2669 #define mmDC_PERFMON7_PERFMON_CVALUE_LOW_BASE_IDX 2 2670 #define mmDC_PERFMON7_PERFMON_HI 0x0780 2671 #define mmDC_PERFMON7_PERFMON_HI_BASE_IDX 2 2672 #define mmDC_PERFMON7_PERFMON_LOW 0x0781 2673 #define mmDC_PERFMON7_PERFMON_LOW_BASE_IDX 2 2674 2675 2676 // addressBlock: dce_dc_dcbubp2_dispdec_hubp_dispdec 2677 // base address: 0x6e0 2678 #define mmHUBP2_DCSURF_SURFACE_CONFIG 0x079d 2679 #define mmHUBP2_DCSURF_SURFACE_CONFIG_BASE_IDX 2 2680 #define mmHUBP2_DCSURF_ADDR_CONFIG 0x079e 2681 #define mmHUBP2_DCSURF_ADDR_CONFIG_BASE_IDX 2 2682 #define mmHUBP2_DCSURF_TILING_CONFIG 0x079f 2683 #define mmHUBP2_DCSURF_TILING_CONFIG_BASE_IDX 2 2684 #define mmHUBP2_DCSURF_PRI_VIEWPORT_START 0x07a1 2685 #define mmHUBP2_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2 2686 #define mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION 0x07a2 2687 #define mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 2688 #define mmHUBP2_DCSURF_PRI_VIEWPORT_START_C 0x07a3 2689 #define mmHUBP2_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2 2690 #define mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x07a4 2691 #define mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2 2692 #define mmHUBP2_DCSURF_SEC_VIEWPORT_START 0x07a5 2693 #define mmHUBP2_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2 2694 #define mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION 0x07a6 2695 #define mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2 2696 #define mmHUBP2_DCSURF_SEC_VIEWPORT_START_C 0x07a7 2697 #define mmHUBP2_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2 2698 #define mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x07a8 2699 #define mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2 2700 #define mmHUBP2_DCHUBP_REQ_SIZE_CONFIG 0x07a9 2701 #define mmHUBP2_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2 2702 #define mmHUBP2_DCHUBP_REQ_SIZE_CONFIG_C 0x07aa 2703 #define mmHUBP2_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2 2704 #define mmHUBP2_DCHUBP_CNTL 0x07ab 2705 #define mmHUBP2_DCHUBP_CNTL_BASE_IDX 2 2706 #define mmHUBP2_HUBP_CLK_CNTL 0x07ac 2707 #define mmHUBP2_HUBP_CLK_CNTL_BASE_IDX 2 2708 #define mmHUBP2_DCHUBP_VMPG_CONFIG 0x07ad 2709 #define mmHUBP2_DCHUBP_VMPG_CONFIG_BASE_IDX 2 2710 #define mmHUBP2_HUBPREQ_DEBUG_DB 0x07ae 2711 #define mmHUBP2_HUBPREQ_DEBUG_DB_BASE_IDX 2 2712 #define mmHUBP2_HUBPREQ_DEBUG 0x07af 2713 #define mmHUBP2_HUBPREQ_DEBUG_BASE_IDX 2 2714 #define mmHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x07b3 2715 #define mmHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2 2716 #define mmHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x07b4 2717 #define mmHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2 2718 2719 2720 // addressBlock: dce_dc_dcbubp2_dispdec_hubpreq_dispdec 2721 // base address: 0x6e0 2722 #define mmHUBPREQ2_DCSURF_SURFACE_PITCH 0x07bf 2723 #define mmHUBPREQ2_DCSURF_SURFACE_PITCH_BASE_IDX 2 2724 #define mmHUBPREQ2_DCSURF_SURFACE_PITCH_C 0x07c0 2725 #define mmHUBPREQ2_DCSURF_SURFACE_PITCH_C_BASE_IDX 2 2726 #define mmHUBPREQ2_VMID_SETTINGS_0 0x07c1 2727 #define mmHUBPREQ2_VMID_SETTINGS_0_BASE_IDX 2 2728 #define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS 0x07c2 2729 #define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2 2730 #define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x07c3 2731 #define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2732 #define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x07c4 2733 #define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2 2734 #define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x07c5 2735 #define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 2736 #define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS 0x07c6 2737 #define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2 2738 #define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x07c7 2739 #define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2740 #define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x07c8 2741 #define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2 2742 #define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x07c9 2743 #define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 2744 #define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x07ca 2745 #define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2 2746 #define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x07cb 2747 #define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2748 #define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x07cc 2749 #define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 2750 #define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x07cd 2751 #define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 2752 #define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x07ce 2753 #define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2 2754 #define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x07cf 2755 #define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2756 #define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x07d0 2757 #define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 2758 #define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x07d1 2759 #define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 2760 #define mmHUBPREQ2_DCSURF_SURFACE_CONTROL 0x07d2 2761 #define mmHUBPREQ2_DCSURF_SURFACE_CONTROL_BASE_IDX 2 2762 #define mmHUBPREQ2_DCSURF_FLIP_CONTROL 0x07d3 2763 #define mmHUBPREQ2_DCSURF_FLIP_CONTROL_BASE_IDX 2 2764 #define mmHUBPREQ2_DCSURF_FLIP_CONTROL2 0x07d4 2765 #define mmHUBPREQ2_DCSURF_FLIP_CONTROL2_BASE_IDX 2 2766 #define mmHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT 0x07d8 2767 #define mmHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2 2768 #define mmHUBPREQ2_DCSURF_SURFACE_INUSE 0x07d9 2769 #define mmHUBPREQ2_DCSURF_SURFACE_INUSE_BASE_IDX 2 2770 #define mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH 0x07da 2771 #define mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2 2772 #define mmHUBPREQ2_DCSURF_SURFACE_INUSE_C 0x07db 2773 #define mmHUBPREQ2_DCSURF_SURFACE_INUSE_C_BASE_IDX 2 2774 #define mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C 0x07dc 2775 #define mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2 2776 #define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE 0x07dd 2777 #define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2 2778 #define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x07de 2779 #define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2 2780 #define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C 0x07df 2781 #define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2 2782 #define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x07e0 2783 #define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2 2784 #define mmHUBPREQ2_DCN_EXPANSION_MODE 0x07e1 2785 #define mmHUBPREQ2_DCN_EXPANSION_MODE_BASE_IDX 2 2786 #define mmHUBPREQ2_DCN_TTU_QOS_WM 0x07e2 2787 #define mmHUBPREQ2_DCN_TTU_QOS_WM_BASE_IDX 2 2788 #define mmHUBPREQ2_DCN_GLOBAL_TTU_CNTL 0x07e3 2789 #define mmHUBPREQ2_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2 2790 #define mmHUBPREQ2_DCN_SURF0_TTU_CNTL0 0x07e4 2791 #define mmHUBPREQ2_DCN_SURF0_TTU_CNTL0_BASE_IDX 2 2792 #define mmHUBPREQ2_DCN_SURF0_TTU_CNTL1 0x07e5 2793 #define mmHUBPREQ2_DCN_SURF0_TTU_CNTL1_BASE_IDX 2 2794 #define mmHUBPREQ2_DCN_SURF1_TTU_CNTL0 0x07e6 2795 #define mmHUBPREQ2_DCN_SURF1_TTU_CNTL0_BASE_IDX 2 2796 #define mmHUBPREQ2_DCN_SURF1_TTU_CNTL1 0x07e7 2797 #define mmHUBPREQ2_DCN_SURF1_TTU_CNTL1_BASE_IDX 2 2798 #define mmHUBPREQ2_DCN_CUR0_TTU_CNTL0 0x07e8 2799 #define mmHUBPREQ2_DCN_CUR0_TTU_CNTL0_BASE_IDX 2 2800 #define mmHUBPREQ2_DCN_CUR0_TTU_CNTL1 0x07e9 2801 #define mmHUBPREQ2_DCN_CUR0_TTU_CNTL1_BASE_IDX 2 2802 #define mmHUBPREQ2_DCN_CUR1_TTU_CNTL0 0x07ea 2803 #define mmHUBPREQ2_DCN_CUR1_TTU_CNTL0_BASE_IDX 2 2804 #define mmHUBPREQ2_DCN_CUR1_TTU_CNTL1 0x07eb 2805 #define mmHUBPREQ2_DCN_CUR1_TTU_CNTL1_BASE_IDX 2 2806 #define mmHUBPREQ2_DCN_DMDATA_VM_CNTL 0x07ec 2807 #define mmHUBPREQ2_DCN_DMDATA_VM_CNTL_BASE_IDX 2 2808 #define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x07ed 2809 #define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2 2810 #define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x07ee 2811 #define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2 2812 #define mmHUBPREQ2_DCN_VM_MX_L1_TLB_CNTL 0x07fb 2813 #define mmHUBPREQ2_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2 2814 #define mmHUBPREQ2_BLANK_OFFSET_0 0x07fc 2815 #define mmHUBPREQ2_BLANK_OFFSET_0_BASE_IDX 2 2816 #define mmHUBPREQ2_BLANK_OFFSET_1 0x07fd 2817 #define mmHUBPREQ2_BLANK_OFFSET_1_BASE_IDX 2 2818 #define mmHUBPREQ2_DST_DIMENSIONS 0x07fe 2819 #define mmHUBPREQ2_DST_DIMENSIONS_BASE_IDX 2 2820 #define mmHUBPREQ2_DST_AFTER_SCALER 0x07ff 2821 #define mmHUBPREQ2_DST_AFTER_SCALER_BASE_IDX 2 2822 #define mmHUBPREQ2_PREFETCH_SETTINGS 0x0800 2823 #define mmHUBPREQ2_PREFETCH_SETTINGS_BASE_IDX 2 2824 #define mmHUBPREQ2_PREFETCH_SETTINGS_C 0x0801 2825 #define mmHUBPREQ2_PREFETCH_SETTINGS_C_BASE_IDX 2 2826 #define mmHUBPREQ2_VBLANK_PARAMETERS_0 0x0802 2827 #define mmHUBPREQ2_VBLANK_PARAMETERS_0_BASE_IDX 2 2828 #define mmHUBPREQ2_VBLANK_PARAMETERS_1 0x0803 2829 #define mmHUBPREQ2_VBLANK_PARAMETERS_1_BASE_IDX 2 2830 #define mmHUBPREQ2_VBLANK_PARAMETERS_2 0x0804 2831 #define mmHUBPREQ2_VBLANK_PARAMETERS_2_BASE_IDX 2 2832 #define mmHUBPREQ2_VBLANK_PARAMETERS_3 0x0805 2833 #define mmHUBPREQ2_VBLANK_PARAMETERS_3_BASE_IDX 2 2834 #define mmHUBPREQ2_VBLANK_PARAMETERS_4 0x0806 2835 #define mmHUBPREQ2_VBLANK_PARAMETERS_4_BASE_IDX 2 2836 #define mmHUBPREQ2_FLIP_PARAMETERS_0 0x0807 2837 #define mmHUBPREQ2_FLIP_PARAMETERS_0_BASE_IDX 2 2838 #define mmHUBPREQ2_FLIP_PARAMETERS_1 0x0808 2839 #define mmHUBPREQ2_FLIP_PARAMETERS_1_BASE_IDX 2 2840 #define mmHUBPREQ2_FLIP_PARAMETERS_2 0x0809 2841 #define mmHUBPREQ2_FLIP_PARAMETERS_2_BASE_IDX 2 2842 #define mmHUBPREQ2_NOM_PARAMETERS_0 0x080a 2843 #define mmHUBPREQ2_NOM_PARAMETERS_0_BASE_IDX 2 2844 #define mmHUBPREQ2_NOM_PARAMETERS_1 0x080b 2845 #define mmHUBPREQ2_NOM_PARAMETERS_1_BASE_IDX 2 2846 #define mmHUBPREQ2_NOM_PARAMETERS_2 0x080c 2847 #define mmHUBPREQ2_NOM_PARAMETERS_2_BASE_IDX 2 2848 #define mmHUBPREQ2_NOM_PARAMETERS_3 0x080d 2849 #define mmHUBPREQ2_NOM_PARAMETERS_3_BASE_IDX 2 2850 #define mmHUBPREQ2_NOM_PARAMETERS_4 0x080e 2851 #define mmHUBPREQ2_NOM_PARAMETERS_4_BASE_IDX 2 2852 #define mmHUBPREQ2_NOM_PARAMETERS_5 0x080f 2853 #define mmHUBPREQ2_NOM_PARAMETERS_5_BASE_IDX 2 2854 #define mmHUBPREQ2_NOM_PARAMETERS_6 0x0810 2855 #define mmHUBPREQ2_NOM_PARAMETERS_6_BASE_IDX 2 2856 #define mmHUBPREQ2_NOM_PARAMETERS_7 0x0811 2857 #define mmHUBPREQ2_NOM_PARAMETERS_7_BASE_IDX 2 2858 #define mmHUBPREQ2_PER_LINE_DELIVERY_PRE 0x0812 2859 #define mmHUBPREQ2_PER_LINE_DELIVERY_PRE_BASE_IDX 2 2860 #define mmHUBPREQ2_PER_LINE_DELIVERY 0x0813 2861 #define mmHUBPREQ2_PER_LINE_DELIVERY_BASE_IDX 2 2862 #define mmHUBPREQ2_CURSOR_SETTINGS 0x0814 2863 #define mmHUBPREQ2_CURSOR_SETTINGS_BASE_IDX 2 2864 #define mmHUBPREQ2_REF_FREQ_TO_PIX_FREQ 0x0815 2865 #define mmHUBPREQ2_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2 2866 #define mmHUBPREQ2_DST_Y_DELTA_DRQ_LIMIT 0x0816 2867 #define mmHUBPREQ2_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2 2868 #define mmHUBPREQ2_HUBPREQ_MEM_PWR_CTRL 0x0817 2869 #define mmHUBPREQ2_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2 2870 #define mmHUBPREQ2_HUBPREQ_MEM_PWR_STATUS 0x0818 2871 #define mmHUBPREQ2_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2 2872 #define mmHUBPREQ2_VBLANK_PARAMETERS_5 0x081b 2873 #define mmHUBPREQ2_VBLANK_PARAMETERS_5_BASE_IDX 2 2874 #define mmHUBPREQ2_VBLANK_PARAMETERS_6 0x081c 2875 #define mmHUBPREQ2_VBLANK_PARAMETERS_6_BASE_IDX 2 2876 #define mmHUBPREQ2_FLIP_PARAMETERS_3 0x081d 2877 #define mmHUBPREQ2_FLIP_PARAMETERS_3_BASE_IDX 2 2878 #define mmHUBPREQ2_FLIP_PARAMETERS_4 0x081e 2879 #define mmHUBPREQ2_FLIP_PARAMETERS_4_BASE_IDX 2 2880 #define mmHUBPREQ2_FLIP_PARAMETERS_5 0x081f 2881 #define mmHUBPREQ2_FLIP_PARAMETERS_5_BASE_IDX 2 2882 #define mmHUBPREQ2_FLIP_PARAMETERS_6 0x0820 2883 #define mmHUBPREQ2_FLIP_PARAMETERS_6_BASE_IDX 2 2884 2885 2886 // addressBlock: dce_dc_dcbubp2_dispdec_hubpret_dispdec 2887 // base address: 0x6e0 2888 #define mmHUBPRET2_HUBPRET_CONTROL 0x0824 2889 #define mmHUBPRET2_HUBPRET_CONTROL_BASE_IDX 2 2890 #define mmHUBPRET2_HUBPRET_MEM_PWR_CTRL 0x0825 2891 #define mmHUBPRET2_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2 2892 #define mmHUBPRET2_HUBPRET_MEM_PWR_STATUS 0x0826 2893 #define mmHUBPRET2_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2 2894 #define mmHUBPRET2_HUBPRET_READ_LINE_CTRL0 0x0827 2895 #define mmHUBPRET2_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2 2896 #define mmHUBPRET2_HUBPRET_READ_LINE_CTRL1 0x0828 2897 #define mmHUBPRET2_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2 2898 #define mmHUBPRET2_HUBPRET_READ_LINE0 0x0829 2899 #define mmHUBPRET2_HUBPRET_READ_LINE0_BASE_IDX 2 2900 #define mmHUBPRET2_HUBPRET_READ_LINE1 0x082a 2901 #define mmHUBPRET2_HUBPRET_READ_LINE1_BASE_IDX 2 2902 #define mmHUBPRET2_HUBPRET_INTERRUPT 0x082b 2903 #define mmHUBPRET2_HUBPRET_INTERRUPT_BASE_IDX 2 2904 #define mmHUBPRET2_HUBPRET_READ_LINE_VALUE 0x082c 2905 #define mmHUBPRET2_HUBPRET_READ_LINE_VALUE_BASE_IDX 2 2906 #define mmHUBPRET2_HUBPRET_READ_LINE_STATUS 0x082d 2907 #define mmHUBPRET2_HUBPRET_READ_LINE_STATUS_BASE_IDX 2 2908 2909 2910 // addressBlock: dce_dc_dcbubp2_dispdec_cursor0_dispdec 2911 // base address: 0x6e0 2912 #define mmCURSOR0_2_CURSOR_CONTROL 0x0830 2913 #define mmCURSOR0_2_CURSOR_CONTROL_BASE_IDX 2 2914 #define mmCURSOR0_2_CURSOR_SURFACE_ADDRESS 0x0831 2915 #define mmCURSOR0_2_CURSOR_SURFACE_ADDRESS_BASE_IDX 2 2916 #define mmCURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH 0x0832 2917 #define mmCURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2918 #define mmCURSOR0_2_CURSOR_SIZE 0x0833 2919 #define mmCURSOR0_2_CURSOR_SIZE_BASE_IDX 2 2920 #define mmCURSOR0_2_CURSOR_POSITION 0x0834 2921 #define mmCURSOR0_2_CURSOR_POSITION_BASE_IDX 2 2922 #define mmCURSOR0_2_CURSOR_HOT_SPOT 0x0835 2923 #define mmCURSOR0_2_CURSOR_HOT_SPOT_BASE_IDX 2 2924 #define mmCURSOR0_2_CURSOR_STEREO_CONTROL 0x0836 2925 #define mmCURSOR0_2_CURSOR_STEREO_CONTROL_BASE_IDX 2 2926 #define mmCURSOR0_2_CURSOR_DST_OFFSET 0x0837 2927 #define mmCURSOR0_2_CURSOR_DST_OFFSET_BASE_IDX 2 2928 #define mmCURSOR0_2_CURSOR_MEM_PWR_CTRL 0x0838 2929 #define mmCURSOR0_2_CURSOR_MEM_PWR_CTRL_BASE_IDX 2 2930 #define mmCURSOR0_2_CURSOR_MEM_PWR_STATUS 0x0839 2931 #define mmCURSOR0_2_CURSOR_MEM_PWR_STATUS_BASE_IDX 2 2932 #define mmCURSOR0_2_DMDATA_ADDRESS_HIGH 0x083a 2933 #define mmCURSOR0_2_DMDATA_ADDRESS_HIGH_BASE_IDX 2 2934 #define mmCURSOR0_2_DMDATA_ADDRESS_LOW 0x083b 2935 #define mmCURSOR0_2_DMDATA_ADDRESS_LOW_BASE_IDX 2 2936 #define mmCURSOR0_2_DMDATA_CNTL 0x083c 2937 #define mmCURSOR0_2_DMDATA_CNTL_BASE_IDX 2 2938 #define mmCURSOR0_2_DMDATA_QOS_CNTL 0x083d 2939 #define mmCURSOR0_2_DMDATA_QOS_CNTL_BASE_IDX 2 2940 #define mmCURSOR0_2_DMDATA_STATUS 0x083e 2941 #define mmCURSOR0_2_DMDATA_STATUS_BASE_IDX 2 2942 #define mmCURSOR0_2_DMDATA_SW_CNTL 0x083f 2943 #define mmCURSOR0_2_DMDATA_SW_CNTL_BASE_IDX 2 2944 #define mmCURSOR0_2_DMDATA_SW_DATA 0x0840 2945 #define mmCURSOR0_2_DMDATA_SW_DATA_BASE_IDX 2 2946 2947 2948 // addressBlock: dce_dc_dcbubp2_dispdec_hubp_dcperfmon_dc_perfmon_dispdec 2949 // base address: 0x2154 2950 #define mmDC_PERFMON8_PERFCOUNTER_CNTL 0x0855 2951 #define mmDC_PERFMON8_PERFCOUNTER_CNTL_BASE_IDX 2 2952 #define mmDC_PERFMON8_PERFCOUNTER_CNTL2 0x0856 2953 #define mmDC_PERFMON8_PERFCOUNTER_CNTL2_BASE_IDX 2 2954 #define mmDC_PERFMON8_PERFCOUNTER_STATE 0x0857 2955 #define mmDC_PERFMON8_PERFCOUNTER_STATE_BASE_IDX 2 2956 #define mmDC_PERFMON8_PERFMON_CNTL 0x0858 2957 #define mmDC_PERFMON8_PERFMON_CNTL_BASE_IDX 2 2958 #define mmDC_PERFMON8_PERFMON_CNTL2 0x0859 2959 #define mmDC_PERFMON8_PERFMON_CNTL2_BASE_IDX 2 2960 #define mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC 0x085a 2961 #define mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 2962 #define mmDC_PERFMON8_PERFMON_CVALUE_LOW 0x085b 2963 #define mmDC_PERFMON8_PERFMON_CVALUE_LOW_BASE_IDX 2 2964 #define mmDC_PERFMON8_PERFMON_HI 0x085c 2965 #define mmDC_PERFMON8_PERFMON_HI_BASE_IDX 2 2966 #define mmDC_PERFMON8_PERFMON_LOW 0x085d 2967 #define mmDC_PERFMON8_PERFMON_LOW_BASE_IDX 2 2968 2969 2970 // addressBlock: dce_dc_dcbubp3_dispdec_hubp_dispdec 2971 // base address: 0xa50 2972 #define mmHUBP3_DCSURF_SURFACE_CONFIG 0x0879 2973 #define mmHUBP3_DCSURF_SURFACE_CONFIG_BASE_IDX 2 2974 #define mmHUBP3_DCSURF_ADDR_CONFIG 0x087a 2975 #define mmHUBP3_DCSURF_ADDR_CONFIG_BASE_IDX 2 2976 #define mmHUBP3_DCSURF_TILING_CONFIG 0x087b 2977 #define mmHUBP3_DCSURF_TILING_CONFIG_BASE_IDX 2 2978 #define mmHUBP3_DCSURF_PRI_VIEWPORT_START 0x087d 2979 #define mmHUBP3_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2 2980 #define mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION 0x087e 2981 #define mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 2982 #define mmHUBP3_DCSURF_PRI_VIEWPORT_START_C 0x087f 2983 #define mmHUBP3_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2 2984 #define mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x0880 2985 #define mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2 2986 #define mmHUBP3_DCSURF_SEC_VIEWPORT_START 0x0881 2987 #define mmHUBP3_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2 2988 #define mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION 0x0882 2989 #define mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2 2990 #define mmHUBP3_DCSURF_SEC_VIEWPORT_START_C 0x0883 2991 #define mmHUBP3_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2 2992 #define mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x0884 2993 #define mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2 2994 #define mmHUBP3_DCHUBP_REQ_SIZE_CONFIG 0x0885 2995 #define mmHUBP3_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2 2996 #define mmHUBP3_DCHUBP_REQ_SIZE_CONFIG_C 0x0886 2997 #define mmHUBP3_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2 2998 #define mmHUBP3_DCHUBP_CNTL 0x0887 2999 #define mmHUBP3_DCHUBP_CNTL_BASE_IDX 2 3000 #define mmHUBP3_HUBP_CLK_CNTL 0x0888 3001 #define mmHUBP3_HUBP_CLK_CNTL_BASE_IDX 2 3002 #define mmHUBP3_DCHUBP_VMPG_CONFIG 0x0889 3003 #define mmHUBP3_DCHUBP_VMPG_CONFIG_BASE_IDX 2 3004 #define mmHUBP3_HUBPREQ_DEBUG_DB 0x088a 3005 #define mmHUBP3_HUBPREQ_DEBUG_DB_BASE_IDX 2 3006 #define mmHUBP3_HUBPREQ_DEBUG 0x088b 3007 #define mmHUBP3_HUBPREQ_DEBUG_BASE_IDX 2 3008 #define mmHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x088f 3009 #define mmHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2 3010 #define mmHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x0890 3011 #define mmHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2 3012 3013 3014 // addressBlock: dce_dc_dcbubp3_dispdec_hubpreq_dispdec 3015 // base address: 0xa50 3016 #define mmHUBPREQ3_DCSURF_SURFACE_PITCH 0x089b 3017 #define mmHUBPREQ3_DCSURF_SURFACE_PITCH_BASE_IDX 2 3018 #define mmHUBPREQ3_DCSURF_SURFACE_PITCH_C 0x089c 3019 #define mmHUBPREQ3_DCSURF_SURFACE_PITCH_C_BASE_IDX 2 3020 #define mmHUBPREQ3_VMID_SETTINGS_0 0x089d 3021 #define mmHUBPREQ3_VMID_SETTINGS_0_BASE_IDX 2 3022 #define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS 0x089e 3023 #define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2 3024 #define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x089f 3025 #define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 3026 #define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x08a0 3027 #define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2 3028 #define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x08a1 3029 #define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 3030 #define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS 0x08a2 3031 #define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2 3032 #define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x08a3 3033 #define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 3034 #define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x08a4 3035 #define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2 3036 #define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x08a5 3037 #define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 3038 #define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x08a6 3039 #define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2 3040 #define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x08a7 3041 #define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 3042 #define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x08a8 3043 #define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 3044 #define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x08a9 3045 #define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 3046 #define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x08aa 3047 #define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2 3048 #define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x08ab 3049 #define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 3050 #define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x08ac 3051 #define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 3052 #define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x08ad 3053 #define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 3054 #define mmHUBPREQ3_DCSURF_SURFACE_CONTROL 0x08ae 3055 #define mmHUBPREQ3_DCSURF_SURFACE_CONTROL_BASE_IDX 2 3056 #define mmHUBPREQ3_DCSURF_FLIP_CONTROL 0x08af 3057 #define mmHUBPREQ3_DCSURF_FLIP_CONTROL_BASE_IDX 2 3058 #define mmHUBPREQ3_DCSURF_FLIP_CONTROL2 0x08b0 3059 #define mmHUBPREQ3_DCSURF_FLIP_CONTROL2_BASE_IDX 2 3060 #define mmHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT 0x08b4 3061 #define mmHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2 3062 #define mmHUBPREQ3_DCSURF_SURFACE_INUSE 0x08b5 3063 #define mmHUBPREQ3_DCSURF_SURFACE_INUSE_BASE_IDX 2 3064 #define mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH 0x08b6 3065 #define mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2 3066 #define mmHUBPREQ3_DCSURF_SURFACE_INUSE_C 0x08b7 3067 #define mmHUBPREQ3_DCSURF_SURFACE_INUSE_C_BASE_IDX 2 3068 #define mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C 0x08b8 3069 #define mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2 3070 #define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE 0x08b9 3071 #define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2 3072 #define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x08ba 3073 #define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2 3074 #define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C 0x08bb 3075 #define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2 3076 #define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x08bc 3077 #define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2 3078 #define mmHUBPREQ3_DCN_EXPANSION_MODE 0x08bd 3079 #define mmHUBPREQ3_DCN_EXPANSION_MODE_BASE_IDX 2 3080 #define mmHUBPREQ3_DCN_TTU_QOS_WM 0x08be 3081 #define mmHUBPREQ3_DCN_TTU_QOS_WM_BASE_IDX 2 3082 #define mmHUBPREQ3_DCN_GLOBAL_TTU_CNTL 0x08bf 3083 #define mmHUBPREQ3_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2 3084 #define mmHUBPREQ3_DCN_SURF0_TTU_CNTL0 0x08c0 3085 #define mmHUBPREQ3_DCN_SURF0_TTU_CNTL0_BASE_IDX 2 3086 #define mmHUBPREQ3_DCN_SURF0_TTU_CNTL1 0x08c1 3087 #define mmHUBPREQ3_DCN_SURF0_TTU_CNTL1_BASE_IDX 2 3088 #define mmHUBPREQ3_DCN_SURF1_TTU_CNTL0 0x08c2 3089 #define mmHUBPREQ3_DCN_SURF1_TTU_CNTL0_BASE_IDX 2 3090 #define mmHUBPREQ3_DCN_SURF1_TTU_CNTL1 0x08c3 3091 #define mmHUBPREQ3_DCN_SURF1_TTU_CNTL1_BASE_IDX 2 3092 #define mmHUBPREQ3_DCN_CUR0_TTU_CNTL0 0x08c4 3093 #define mmHUBPREQ3_DCN_CUR0_TTU_CNTL0_BASE_IDX 2 3094 #define mmHUBPREQ3_DCN_CUR0_TTU_CNTL1 0x08c5 3095 #define mmHUBPREQ3_DCN_CUR0_TTU_CNTL1_BASE_IDX 2 3096 #define mmHUBPREQ3_DCN_CUR1_TTU_CNTL0 0x08c6 3097 #define mmHUBPREQ3_DCN_CUR1_TTU_CNTL0_BASE_IDX 2 3098 #define mmHUBPREQ3_DCN_CUR1_TTU_CNTL1 0x08c7 3099 #define mmHUBPREQ3_DCN_CUR1_TTU_CNTL1_BASE_IDX 2 3100 #define mmHUBPREQ3_DCN_DMDATA_VM_CNTL 0x08c8 3101 #define mmHUBPREQ3_DCN_DMDATA_VM_CNTL_BASE_IDX 2 3102 #define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x08c9 3103 #define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2 3104 #define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x08ca 3105 #define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2 3106 #define mmHUBPREQ3_DCN_VM_MX_L1_TLB_CNTL 0x08d7 3107 #define mmHUBPREQ3_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2 3108 #define mmHUBPREQ3_BLANK_OFFSET_0 0x08d8 3109 #define mmHUBPREQ3_BLANK_OFFSET_0_BASE_IDX 2 3110 #define mmHUBPREQ3_BLANK_OFFSET_1 0x08d9 3111 #define mmHUBPREQ3_BLANK_OFFSET_1_BASE_IDX 2 3112 #define mmHUBPREQ3_DST_DIMENSIONS 0x08da 3113 #define mmHUBPREQ3_DST_DIMENSIONS_BASE_IDX 2 3114 #define mmHUBPREQ3_DST_AFTER_SCALER 0x08db 3115 #define mmHUBPREQ3_DST_AFTER_SCALER_BASE_IDX 2 3116 #define mmHUBPREQ3_PREFETCH_SETTINGS 0x08dc 3117 #define mmHUBPREQ3_PREFETCH_SETTINGS_BASE_IDX 2 3118 #define mmHUBPREQ3_PREFETCH_SETTINGS_C 0x08dd 3119 #define mmHUBPREQ3_PREFETCH_SETTINGS_C_BASE_IDX 2 3120 #define mmHUBPREQ3_VBLANK_PARAMETERS_0 0x08de 3121 #define mmHUBPREQ3_VBLANK_PARAMETERS_0_BASE_IDX 2 3122 #define mmHUBPREQ3_VBLANK_PARAMETERS_1 0x08df 3123 #define mmHUBPREQ3_VBLANK_PARAMETERS_1_BASE_IDX 2 3124 #define mmHUBPREQ3_VBLANK_PARAMETERS_2 0x08e0 3125 #define mmHUBPREQ3_VBLANK_PARAMETERS_2_BASE_IDX 2 3126 #define mmHUBPREQ3_VBLANK_PARAMETERS_3 0x08e1 3127 #define mmHUBPREQ3_VBLANK_PARAMETERS_3_BASE_IDX 2 3128 #define mmHUBPREQ3_VBLANK_PARAMETERS_4 0x08e2 3129 #define mmHUBPREQ3_VBLANK_PARAMETERS_4_BASE_IDX 2 3130 #define mmHUBPREQ3_FLIP_PARAMETERS_0 0x08e3 3131 #define mmHUBPREQ3_FLIP_PARAMETERS_0_BASE_IDX 2 3132 #define mmHUBPREQ3_FLIP_PARAMETERS_1 0x08e4 3133 #define mmHUBPREQ3_FLIP_PARAMETERS_1_BASE_IDX 2 3134 #define mmHUBPREQ3_FLIP_PARAMETERS_2 0x08e5 3135 #define mmHUBPREQ3_FLIP_PARAMETERS_2_BASE_IDX 2 3136 #define mmHUBPREQ3_NOM_PARAMETERS_0 0x08e6 3137 #define mmHUBPREQ3_NOM_PARAMETERS_0_BASE_IDX 2 3138 #define mmHUBPREQ3_NOM_PARAMETERS_1 0x08e7 3139 #define mmHUBPREQ3_NOM_PARAMETERS_1_BASE_IDX 2 3140 #define mmHUBPREQ3_NOM_PARAMETERS_2 0x08e8 3141 #define mmHUBPREQ3_NOM_PARAMETERS_2_BASE_IDX 2 3142 #define mmHUBPREQ3_NOM_PARAMETERS_3 0x08e9 3143 #define mmHUBPREQ3_NOM_PARAMETERS_3_BASE_IDX 2 3144 #define mmHUBPREQ3_NOM_PARAMETERS_4 0x08ea 3145 #define mmHUBPREQ3_NOM_PARAMETERS_4_BASE_IDX 2 3146 #define mmHUBPREQ3_NOM_PARAMETERS_5 0x08eb 3147 #define mmHUBPREQ3_NOM_PARAMETERS_5_BASE_IDX 2 3148 #define mmHUBPREQ3_NOM_PARAMETERS_6 0x08ec 3149 #define mmHUBPREQ3_NOM_PARAMETERS_6_BASE_IDX 2 3150 #define mmHUBPREQ3_NOM_PARAMETERS_7 0x08ed 3151 #define mmHUBPREQ3_NOM_PARAMETERS_7_BASE_IDX 2 3152 #define mmHUBPREQ3_PER_LINE_DELIVERY_PRE 0x08ee 3153 #define mmHUBPREQ3_PER_LINE_DELIVERY_PRE_BASE_IDX 2 3154 #define mmHUBPREQ3_PER_LINE_DELIVERY 0x08ef 3155 #define mmHUBPREQ3_PER_LINE_DELIVERY_BASE_IDX 2 3156 #define mmHUBPREQ3_CURSOR_SETTINGS 0x08f0 3157 #define mmHUBPREQ3_CURSOR_SETTINGS_BASE_IDX 2 3158 #define mmHUBPREQ3_REF_FREQ_TO_PIX_FREQ 0x08f1 3159 #define mmHUBPREQ3_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2 3160 #define mmHUBPREQ3_DST_Y_DELTA_DRQ_LIMIT 0x08f2 3161 #define mmHUBPREQ3_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2 3162 #define mmHUBPREQ3_HUBPREQ_MEM_PWR_CTRL 0x08f3 3163 #define mmHUBPREQ3_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2 3164 #define mmHUBPREQ3_HUBPREQ_MEM_PWR_STATUS 0x08f4 3165 #define mmHUBPREQ3_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2 3166 #define mmHUBPREQ3_VBLANK_PARAMETERS_5 0x08f7 3167 #define mmHUBPREQ3_VBLANK_PARAMETERS_5_BASE_IDX 2 3168 #define mmHUBPREQ3_VBLANK_PARAMETERS_6 0x08f8 3169 #define mmHUBPREQ3_VBLANK_PARAMETERS_6_BASE_IDX 2 3170 #define mmHUBPREQ3_FLIP_PARAMETERS_3 0x08f9 3171 #define mmHUBPREQ3_FLIP_PARAMETERS_3_BASE_IDX 2 3172 #define mmHUBPREQ3_FLIP_PARAMETERS_4 0x08fa 3173 #define mmHUBPREQ3_FLIP_PARAMETERS_4_BASE_IDX 2 3174 #define mmHUBPREQ3_FLIP_PARAMETERS_5 0x08fb 3175 #define mmHUBPREQ3_FLIP_PARAMETERS_5_BASE_IDX 2 3176 #define mmHUBPREQ3_FLIP_PARAMETERS_6 0x08fc 3177 #define mmHUBPREQ3_FLIP_PARAMETERS_6_BASE_IDX 2 3178 3179 3180 // addressBlock: dce_dc_dcbubp3_dispdec_hubpret_dispdec 3181 // base address: 0xa50 3182 #define mmHUBPRET3_HUBPRET_CONTROL 0x0900 3183 #define mmHUBPRET3_HUBPRET_CONTROL_BASE_IDX 2 3184 #define mmHUBPRET3_HUBPRET_MEM_PWR_CTRL 0x0901 3185 #define mmHUBPRET3_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2 3186 #define mmHUBPRET3_HUBPRET_MEM_PWR_STATUS 0x0902 3187 #define mmHUBPRET3_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2 3188 #define mmHUBPRET3_HUBPRET_READ_LINE_CTRL0 0x0903 3189 #define mmHUBPRET3_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2 3190 #define mmHUBPRET3_HUBPRET_READ_LINE_CTRL1 0x0904 3191 #define mmHUBPRET3_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2 3192 #define mmHUBPRET3_HUBPRET_READ_LINE0 0x0905 3193 #define mmHUBPRET3_HUBPRET_READ_LINE0_BASE_IDX 2 3194 #define mmHUBPRET3_HUBPRET_READ_LINE1 0x0906 3195 #define mmHUBPRET3_HUBPRET_READ_LINE1_BASE_IDX 2 3196 #define mmHUBPRET3_HUBPRET_INTERRUPT 0x0907 3197 #define mmHUBPRET3_HUBPRET_INTERRUPT_BASE_IDX 2 3198 #define mmHUBPRET3_HUBPRET_READ_LINE_VALUE 0x0908 3199 #define mmHUBPRET3_HUBPRET_READ_LINE_VALUE_BASE_IDX 2 3200 #define mmHUBPRET3_HUBPRET_READ_LINE_STATUS 0x0909 3201 #define mmHUBPRET3_HUBPRET_READ_LINE_STATUS_BASE_IDX 2 3202 3203 3204 // addressBlock: dce_dc_dcbubp3_dispdec_cursor0_dispdec 3205 // base address: 0xa50 3206 #define mmCURSOR0_3_CURSOR_CONTROL 0x090c 3207 #define mmCURSOR0_3_CURSOR_CONTROL_BASE_IDX 2 3208 #define mmCURSOR0_3_CURSOR_SURFACE_ADDRESS 0x090d 3209 #define mmCURSOR0_3_CURSOR_SURFACE_ADDRESS_BASE_IDX 2 3210 #define mmCURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH 0x090e 3211 #define mmCURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2 3212 #define mmCURSOR0_3_CURSOR_SIZE 0x090f 3213 #define mmCURSOR0_3_CURSOR_SIZE_BASE_IDX 2 3214 #define mmCURSOR0_3_CURSOR_POSITION 0x0910 3215 #define mmCURSOR0_3_CURSOR_POSITION_BASE_IDX 2 3216 #define mmCURSOR0_3_CURSOR_HOT_SPOT 0x0911 3217 #define mmCURSOR0_3_CURSOR_HOT_SPOT_BASE_IDX 2 3218 #define mmCURSOR0_3_CURSOR_STEREO_CONTROL 0x0912 3219 #define mmCURSOR0_3_CURSOR_STEREO_CONTROL_BASE_IDX 2 3220 #define mmCURSOR0_3_CURSOR_DST_OFFSET 0x0913 3221 #define mmCURSOR0_3_CURSOR_DST_OFFSET_BASE_IDX 2 3222 #define mmCURSOR0_3_CURSOR_MEM_PWR_CTRL 0x0914 3223 #define mmCURSOR0_3_CURSOR_MEM_PWR_CTRL_BASE_IDX 2 3224 #define mmCURSOR0_3_CURSOR_MEM_PWR_STATUS 0x0915 3225 #define mmCURSOR0_3_CURSOR_MEM_PWR_STATUS_BASE_IDX 2 3226 #define mmCURSOR0_3_DMDATA_ADDRESS_HIGH 0x0916 3227 #define mmCURSOR0_3_DMDATA_ADDRESS_HIGH_BASE_IDX 2 3228 #define mmCURSOR0_3_DMDATA_ADDRESS_LOW 0x0917 3229 #define mmCURSOR0_3_DMDATA_ADDRESS_LOW_BASE_IDX 2 3230 #define mmCURSOR0_3_DMDATA_CNTL 0x0918 3231 #define mmCURSOR0_3_DMDATA_CNTL_BASE_IDX 2 3232 #define mmCURSOR0_3_DMDATA_QOS_CNTL 0x0919 3233 #define mmCURSOR0_3_DMDATA_QOS_CNTL_BASE_IDX 2 3234 #define mmCURSOR0_3_DMDATA_STATUS 0x091a 3235 #define mmCURSOR0_3_DMDATA_STATUS_BASE_IDX 2 3236 #define mmCURSOR0_3_DMDATA_SW_CNTL 0x091b 3237 #define mmCURSOR0_3_DMDATA_SW_CNTL_BASE_IDX 2 3238 #define mmCURSOR0_3_DMDATA_SW_DATA 0x091c 3239 #define mmCURSOR0_3_DMDATA_SW_DATA_BASE_IDX 2 3240 3241 3242 // addressBlock: dce_dc_dcbubp3_dispdec_hubp_dcperfmon_dc_perfmon_dispdec 3243 // base address: 0x24c4 3244 #define mmDC_PERFMON9_PERFCOUNTER_CNTL 0x0931 3245 #define mmDC_PERFMON9_PERFCOUNTER_CNTL_BASE_IDX 2 3246 #define mmDC_PERFMON9_PERFCOUNTER_CNTL2 0x0932 3247 #define mmDC_PERFMON9_PERFCOUNTER_CNTL2_BASE_IDX 2 3248 #define mmDC_PERFMON9_PERFCOUNTER_STATE 0x0933 3249 #define mmDC_PERFMON9_PERFCOUNTER_STATE_BASE_IDX 2 3250 #define mmDC_PERFMON9_PERFMON_CNTL 0x0934 3251 #define mmDC_PERFMON9_PERFMON_CNTL_BASE_IDX 2 3252 #define mmDC_PERFMON9_PERFMON_CNTL2 0x0935 3253 #define mmDC_PERFMON9_PERFMON_CNTL2_BASE_IDX 2 3254 #define mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC 0x0936 3255 #define mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 3256 #define mmDC_PERFMON9_PERFMON_CVALUE_LOW 0x0937 3257 #define mmDC_PERFMON9_PERFMON_CVALUE_LOW_BASE_IDX 2 3258 #define mmDC_PERFMON9_PERFMON_HI 0x0938 3259 #define mmDC_PERFMON9_PERFMON_HI_BASE_IDX 2 3260 #define mmDC_PERFMON9_PERFMON_LOW 0x0939 3261 #define mmDC_PERFMON9_PERFMON_LOW_BASE_IDX 2 3262 3263 3264 // addressBlock: dce_dc_dcbubp4_dispdec_hubp_dispdec 3265 // base address: 0xdc0 3266 #define mmHUBP4_DCSURF_SURFACE_CONFIG 0x0955 3267 #define mmHUBP4_DCSURF_SURFACE_CONFIG_BASE_IDX 2 3268 #define mmHUBP4_DCSURF_ADDR_CONFIG 0x0956 3269 #define mmHUBP4_DCSURF_ADDR_CONFIG_BASE_IDX 2 3270 #define mmHUBP4_DCSURF_TILING_CONFIG 0x0957 3271 #define mmHUBP4_DCSURF_TILING_CONFIG_BASE_IDX 2 3272 #define mmHUBP4_DCSURF_PRI_VIEWPORT_START 0x0959 3273 #define mmHUBP4_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2 3274 #define mmHUBP4_DCSURF_PRI_VIEWPORT_DIMENSION 0x095a 3275 #define mmHUBP4_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 3276 #define mmHUBP4_DCSURF_PRI_VIEWPORT_START_C 0x095b 3277 #define mmHUBP4_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2 3278 #define mmHUBP4_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x095c 3279 #define mmHUBP4_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2 3280 #define mmHUBP4_DCSURF_SEC_VIEWPORT_START 0x095d 3281 #define mmHUBP4_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2 3282 #define mmHUBP4_DCSURF_SEC_VIEWPORT_DIMENSION 0x095e 3283 #define mmHUBP4_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2 3284 #define mmHUBP4_DCSURF_SEC_VIEWPORT_START_C 0x095f 3285 #define mmHUBP4_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2 3286 #define mmHUBP4_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x0960 3287 #define mmHUBP4_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2 3288 #define mmHUBP4_DCHUBP_REQ_SIZE_CONFIG 0x0961 3289 #define mmHUBP4_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2 3290 #define mmHUBP4_DCHUBP_REQ_SIZE_CONFIG_C 0x0962 3291 #define mmHUBP4_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2 3292 #define mmHUBP4_DCHUBP_CNTL 0x0963 3293 #define mmHUBP4_DCHUBP_CNTL_BASE_IDX 2 3294 #define mmHUBP4_HUBP_CLK_CNTL 0x0964 3295 #define mmHUBP4_HUBP_CLK_CNTL_BASE_IDX 2 3296 #define mmHUBP4_DCHUBP_VMPG_CONFIG 0x0965 3297 #define mmHUBP4_DCHUBP_VMPG_CONFIG_BASE_IDX 2 3298 #define mmHUBP4_HUBPREQ_DEBUG_DB 0x0966 3299 #define mmHUBP4_HUBPREQ_DEBUG_DB_BASE_IDX 2 3300 #define mmHUBP4_HUBPREQ_DEBUG 0x0967 3301 #define mmHUBP4_HUBPREQ_DEBUG_BASE_IDX 2 3302 #define mmHUBP4_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x096b 3303 #define mmHUBP4_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2 3304 #define mmHUBP4_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x096c 3305 #define mmHUBP4_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2 3306 3307 3308 // addressBlock: dce_dc_dcbubp4_dispdec_hubpreq_dispdec 3309 // base address: 0xdc0 3310 #define mmHUBPREQ4_DCSURF_SURFACE_PITCH 0x0977 3311 #define mmHUBPREQ4_DCSURF_SURFACE_PITCH_BASE_IDX 2 3312 #define mmHUBPREQ4_DCSURF_SURFACE_PITCH_C 0x0978 3313 #define mmHUBPREQ4_DCSURF_SURFACE_PITCH_C_BASE_IDX 2 3314 #define mmHUBPREQ4_VMID_SETTINGS_0 0x0979 3315 #define mmHUBPREQ4_VMID_SETTINGS_0_BASE_IDX 2 3316 #define mmHUBPREQ4_DCSURF_PRIMARY_SURFACE_ADDRESS 0x097a 3317 #define mmHUBPREQ4_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2 3318 #define mmHUBPREQ4_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x097b 3319 #define mmHUBPREQ4_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 3320 #define mmHUBPREQ4_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x097c 3321 #define mmHUBPREQ4_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2 3322 #define mmHUBPREQ4_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x097d 3323 #define mmHUBPREQ4_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 3324 #define mmHUBPREQ4_DCSURF_SECONDARY_SURFACE_ADDRESS 0x097e 3325 #define mmHUBPREQ4_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2 3326 #define mmHUBPREQ4_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x097f 3327 #define mmHUBPREQ4_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 3328 #define mmHUBPREQ4_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x0980 3329 #define mmHUBPREQ4_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2 3330 #define mmHUBPREQ4_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x0981 3331 #define mmHUBPREQ4_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 3332 #define mmHUBPREQ4_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x0982 3333 #define mmHUBPREQ4_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2 3334 #define mmHUBPREQ4_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x0983 3335 #define mmHUBPREQ4_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 3336 #define mmHUBPREQ4_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x0984 3337 #define mmHUBPREQ4_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 3338 #define mmHUBPREQ4_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x0985 3339 #define mmHUBPREQ4_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 3340 #define mmHUBPREQ4_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x0986 3341 #define mmHUBPREQ4_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2 3342 #define mmHUBPREQ4_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x0987 3343 #define mmHUBPREQ4_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 3344 #define mmHUBPREQ4_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x0988 3345 #define mmHUBPREQ4_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 3346 #define mmHUBPREQ4_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x0989 3347 #define mmHUBPREQ4_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 3348 #define mmHUBPREQ4_DCSURF_SURFACE_CONTROL 0x098a 3349 #define mmHUBPREQ4_DCSURF_SURFACE_CONTROL_BASE_IDX 2 3350 #define mmHUBPREQ4_DCSURF_FLIP_CONTROL 0x098b 3351 #define mmHUBPREQ4_DCSURF_FLIP_CONTROL_BASE_IDX 2 3352 #define mmHUBPREQ4_DCSURF_FLIP_CONTROL2 0x098c 3353 #define mmHUBPREQ4_DCSURF_FLIP_CONTROL2_BASE_IDX 2 3354 #define mmHUBPREQ4_DCSURF_SURFACE_FLIP_INTERRUPT 0x0990 3355 #define mmHUBPREQ4_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2 3356 #define mmHUBPREQ4_DCSURF_SURFACE_INUSE 0x0991 3357 #define mmHUBPREQ4_DCSURF_SURFACE_INUSE_BASE_IDX 2 3358 #define mmHUBPREQ4_DCSURF_SURFACE_INUSE_HIGH 0x0992 3359 #define mmHUBPREQ4_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2 3360 #define mmHUBPREQ4_DCSURF_SURFACE_INUSE_C 0x0993 3361 #define mmHUBPREQ4_DCSURF_SURFACE_INUSE_C_BASE_IDX 2 3362 #define mmHUBPREQ4_DCSURF_SURFACE_INUSE_HIGH_C 0x0994 3363 #define mmHUBPREQ4_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2 3364 #define mmHUBPREQ4_DCSURF_SURFACE_EARLIEST_INUSE 0x0995 3365 #define mmHUBPREQ4_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2 3366 #define mmHUBPREQ4_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x0996 3367 #define mmHUBPREQ4_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2 3368 #define mmHUBPREQ4_DCSURF_SURFACE_EARLIEST_INUSE_C 0x0997 3369 #define mmHUBPREQ4_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2 3370 #define mmHUBPREQ4_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x0998 3371 #define mmHUBPREQ4_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2 3372 #define mmHUBPREQ4_DCN_EXPANSION_MODE 0x0999 3373 #define mmHUBPREQ4_DCN_EXPANSION_MODE_BASE_IDX 2 3374 #define mmHUBPREQ4_DCN_TTU_QOS_WM 0x099a 3375 #define mmHUBPREQ4_DCN_TTU_QOS_WM_BASE_IDX 2 3376 #define mmHUBPREQ4_DCN_GLOBAL_TTU_CNTL 0x099b 3377 #define mmHUBPREQ4_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2 3378 #define mmHUBPREQ4_DCN_SURF0_TTU_CNTL0 0x099c 3379 #define mmHUBPREQ4_DCN_SURF0_TTU_CNTL0_BASE_IDX 2 3380 #define mmHUBPREQ4_DCN_SURF0_TTU_CNTL1 0x099d 3381 #define mmHUBPREQ4_DCN_SURF0_TTU_CNTL1_BASE_IDX 2 3382 #define mmHUBPREQ4_DCN_SURF1_TTU_CNTL0 0x099e 3383 #define mmHUBPREQ4_DCN_SURF1_TTU_CNTL0_BASE_IDX 2 3384 #define mmHUBPREQ4_DCN_SURF1_TTU_CNTL1 0x099f 3385 #define mmHUBPREQ4_DCN_SURF1_TTU_CNTL1_BASE_IDX 2 3386 #define mmHUBPREQ4_DCN_CUR0_TTU_CNTL0 0x09a0 3387 #define mmHUBPREQ4_DCN_CUR0_TTU_CNTL0_BASE_IDX 2 3388 #define mmHUBPREQ4_DCN_CUR0_TTU_CNTL1 0x09a1 3389 #define mmHUBPREQ4_DCN_CUR0_TTU_CNTL1_BASE_IDX 2 3390 #define mmHUBPREQ4_DCN_CUR1_TTU_CNTL0 0x09a2 3391 #define mmHUBPREQ4_DCN_CUR1_TTU_CNTL0_BASE_IDX 2 3392 #define mmHUBPREQ4_DCN_CUR1_TTU_CNTL1 0x09a3 3393 #define mmHUBPREQ4_DCN_CUR1_TTU_CNTL1_BASE_IDX 2 3394 #define mmHUBPREQ4_DCN_DMDATA_VM_CNTL 0x09a4 3395 #define mmHUBPREQ4_DCN_DMDATA_VM_CNTL_BASE_IDX 2 3396 #define mmHUBPREQ4_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x09a5 3397 #define mmHUBPREQ4_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2 3398 #define mmHUBPREQ4_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x09a6 3399 #define mmHUBPREQ4_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2 3400 #define mmHUBPREQ4_DCN_VM_MX_L1_TLB_CNTL 0x09b3 3401 #define mmHUBPREQ4_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2 3402 #define mmHUBPREQ4_BLANK_OFFSET_0 0x09b4 3403 #define mmHUBPREQ4_BLANK_OFFSET_0_BASE_IDX 2 3404 #define mmHUBPREQ4_BLANK_OFFSET_1 0x09b5 3405 #define mmHUBPREQ4_BLANK_OFFSET_1_BASE_IDX 2 3406 #define mmHUBPREQ4_DST_DIMENSIONS 0x09b6 3407 #define mmHUBPREQ4_DST_DIMENSIONS_BASE_IDX 2 3408 #define mmHUBPREQ4_DST_AFTER_SCALER 0x09b7 3409 #define mmHUBPREQ4_DST_AFTER_SCALER_BASE_IDX 2 3410 #define mmHUBPREQ4_PREFETCH_SETTINGS 0x09b8 3411 #define mmHUBPREQ4_PREFETCH_SETTINGS_BASE_IDX 2 3412 #define mmHUBPREQ4_PREFETCH_SETTINGS_C 0x09b9 3413 #define mmHUBPREQ4_PREFETCH_SETTINGS_C_BASE_IDX 2 3414 #define mmHUBPREQ4_VBLANK_PARAMETERS_0 0x09ba 3415 #define mmHUBPREQ4_VBLANK_PARAMETERS_0_BASE_IDX 2 3416 #define mmHUBPREQ4_VBLANK_PARAMETERS_1 0x09bb 3417 #define mmHUBPREQ4_VBLANK_PARAMETERS_1_BASE_IDX 2 3418 #define mmHUBPREQ4_VBLANK_PARAMETERS_2 0x09bc 3419 #define mmHUBPREQ4_VBLANK_PARAMETERS_2_BASE_IDX 2 3420 #define mmHUBPREQ4_VBLANK_PARAMETERS_3 0x09bd 3421 #define mmHUBPREQ4_VBLANK_PARAMETERS_3_BASE_IDX 2 3422 #define mmHUBPREQ4_VBLANK_PARAMETERS_4 0x09be 3423 #define mmHUBPREQ4_VBLANK_PARAMETERS_4_BASE_IDX 2 3424 #define mmHUBPREQ4_FLIP_PARAMETERS_0 0x09bf 3425 #define mmHUBPREQ4_FLIP_PARAMETERS_0_BASE_IDX 2 3426 #define mmHUBPREQ4_FLIP_PARAMETERS_1 0x09c0 3427 #define mmHUBPREQ4_FLIP_PARAMETERS_1_BASE_IDX 2 3428 #define mmHUBPREQ4_FLIP_PARAMETERS_2 0x09c1 3429 #define mmHUBPREQ4_FLIP_PARAMETERS_2_BASE_IDX 2 3430 #define mmHUBPREQ4_NOM_PARAMETERS_0 0x09c2 3431 #define mmHUBPREQ4_NOM_PARAMETERS_0_BASE_IDX 2 3432 #define mmHUBPREQ4_NOM_PARAMETERS_1 0x09c3 3433 #define mmHUBPREQ4_NOM_PARAMETERS_1_BASE_IDX 2 3434 #define mmHUBPREQ4_NOM_PARAMETERS_2 0x09c4 3435 #define mmHUBPREQ4_NOM_PARAMETERS_2_BASE_IDX 2 3436 #define mmHUBPREQ4_NOM_PARAMETERS_3 0x09c5 3437 #define mmHUBPREQ4_NOM_PARAMETERS_3_BASE_IDX 2 3438 #define mmHUBPREQ4_NOM_PARAMETERS_4 0x09c6 3439 #define mmHUBPREQ4_NOM_PARAMETERS_4_BASE_IDX 2 3440 #define mmHUBPREQ4_NOM_PARAMETERS_5 0x09c7 3441 #define mmHUBPREQ4_NOM_PARAMETERS_5_BASE_IDX 2 3442 #define mmHUBPREQ4_NOM_PARAMETERS_6 0x09c8 3443 #define mmHUBPREQ4_NOM_PARAMETERS_6_BASE_IDX 2 3444 #define mmHUBPREQ4_NOM_PARAMETERS_7 0x09c9 3445 #define mmHUBPREQ4_NOM_PARAMETERS_7_BASE_IDX 2 3446 #define mmHUBPREQ4_PER_LINE_DELIVERY_PRE 0x09ca 3447 #define mmHUBPREQ4_PER_LINE_DELIVERY_PRE_BASE_IDX 2 3448 #define mmHUBPREQ4_PER_LINE_DELIVERY 0x09cb 3449 #define mmHUBPREQ4_PER_LINE_DELIVERY_BASE_IDX 2 3450 #define mmHUBPREQ4_CURSOR_SETTINGS 0x09cc 3451 #define mmHUBPREQ4_CURSOR_SETTINGS_BASE_IDX 2 3452 #define mmHUBPREQ4_REF_FREQ_TO_PIX_FREQ 0x09cd 3453 #define mmHUBPREQ4_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2 3454 #define mmHUBPREQ4_DST_Y_DELTA_DRQ_LIMIT 0x09ce 3455 #define mmHUBPREQ4_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2 3456 #define mmHUBPREQ4_HUBPREQ_MEM_PWR_CTRL 0x09cf 3457 #define mmHUBPREQ4_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2 3458 #define mmHUBPREQ4_HUBPREQ_MEM_PWR_STATUS 0x09d0 3459 #define mmHUBPREQ4_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2 3460 #define mmHUBPREQ4_VBLANK_PARAMETERS_5 0x09d3 3461 #define mmHUBPREQ4_VBLANK_PARAMETERS_5_BASE_IDX 2 3462 #define mmHUBPREQ4_VBLANK_PARAMETERS_6 0x09d4 3463 #define mmHUBPREQ4_VBLANK_PARAMETERS_6_BASE_IDX 2 3464 #define mmHUBPREQ4_FLIP_PARAMETERS_3 0x09d5 3465 #define mmHUBPREQ4_FLIP_PARAMETERS_3_BASE_IDX 2 3466 #define mmHUBPREQ4_FLIP_PARAMETERS_4 0x09d6 3467 #define mmHUBPREQ4_FLIP_PARAMETERS_4_BASE_IDX 2 3468 #define mmHUBPREQ4_FLIP_PARAMETERS_5 0x09d7 3469 #define mmHUBPREQ4_FLIP_PARAMETERS_5_BASE_IDX 2 3470 #define mmHUBPREQ4_FLIP_PARAMETERS_6 0x09d8 3471 #define mmHUBPREQ4_FLIP_PARAMETERS_6_BASE_IDX 2 3472 3473 3474 // addressBlock: dce_dc_dcbubp4_dispdec_hubpret_dispdec 3475 // base address: 0xdc0 3476 #define mmHUBPRET4_HUBPRET_CONTROL 0x09dc 3477 #define mmHUBPRET4_HUBPRET_CONTROL_BASE_IDX 2 3478 #define mmHUBPRET4_HUBPRET_MEM_PWR_CTRL 0x09dd 3479 #define mmHUBPRET4_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2 3480 #define mmHUBPRET4_HUBPRET_MEM_PWR_STATUS 0x09de 3481 #define mmHUBPRET4_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2 3482 #define mmHUBPRET4_HUBPRET_READ_LINE_CTRL0 0x09df 3483 #define mmHUBPRET4_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2 3484 #define mmHUBPRET4_HUBPRET_READ_LINE_CTRL1 0x09e0 3485 #define mmHUBPRET4_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2 3486 #define mmHUBPRET4_HUBPRET_READ_LINE0 0x09e1 3487 #define mmHUBPRET4_HUBPRET_READ_LINE0_BASE_IDX 2 3488 #define mmHUBPRET4_HUBPRET_READ_LINE1 0x09e2 3489 #define mmHUBPRET4_HUBPRET_READ_LINE1_BASE_IDX 2 3490 #define mmHUBPRET4_HUBPRET_INTERRUPT 0x09e3 3491 #define mmHUBPRET4_HUBPRET_INTERRUPT_BASE_IDX 2 3492 #define mmHUBPRET4_HUBPRET_READ_LINE_VALUE 0x09e4 3493 #define mmHUBPRET4_HUBPRET_READ_LINE_VALUE_BASE_IDX 2 3494 #define mmHUBPRET4_HUBPRET_READ_LINE_STATUS 0x09e5 3495 #define mmHUBPRET4_HUBPRET_READ_LINE_STATUS_BASE_IDX 2 3496 3497 3498 // addressBlock: dce_dc_dcbubp4_dispdec_cursor0_dispdec 3499 // base address: 0xdc0 3500 #define mmCURSOR0_4_CURSOR_CONTROL 0x09e8 3501 #define mmCURSOR0_4_CURSOR_CONTROL_BASE_IDX 2 3502 #define mmCURSOR0_4_CURSOR_SURFACE_ADDRESS 0x09e9 3503 #define mmCURSOR0_4_CURSOR_SURFACE_ADDRESS_BASE_IDX 2 3504 #define mmCURSOR0_4_CURSOR_SURFACE_ADDRESS_HIGH 0x09ea 3505 #define mmCURSOR0_4_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2 3506 #define mmCURSOR0_4_CURSOR_SIZE 0x09eb 3507 #define mmCURSOR0_4_CURSOR_SIZE_BASE_IDX 2 3508 #define mmCURSOR0_4_CURSOR_POSITION 0x09ec 3509 #define mmCURSOR0_4_CURSOR_POSITION_BASE_IDX 2 3510 #define mmCURSOR0_4_CURSOR_HOT_SPOT 0x09ed 3511 #define mmCURSOR0_4_CURSOR_HOT_SPOT_BASE_IDX 2 3512 #define mmCURSOR0_4_CURSOR_STEREO_CONTROL 0x09ee 3513 #define mmCURSOR0_4_CURSOR_STEREO_CONTROL_BASE_IDX 2 3514 #define mmCURSOR0_4_CURSOR_DST_OFFSET 0x09ef 3515 #define mmCURSOR0_4_CURSOR_DST_OFFSET_BASE_IDX 2 3516 #define mmCURSOR0_4_CURSOR_MEM_PWR_CTRL 0x09f0 3517 #define mmCURSOR0_4_CURSOR_MEM_PWR_CTRL_BASE_IDX 2 3518 #define mmCURSOR0_4_CURSOR_MEM_PWR_STATUS 0x09f1 3519 #define mmCURSOR0_4_CURSOR_MEM_PWR_STATUS_BASE_IDX 2 3520 #define mmCURSOR0_4_DMDATA_ADDRESS_HIGH 0x09f2 3521 #define mmCURSOR0_4_DMDATA_ADDRESS_HIGH_BASE_IDX 2 3522 #define mmCURSOR0_4_DMDATA_ADDRESS_LOW 0x09f3 3523 #define mmCURSOR0_4_DMDATA_ADDRESS_LOW_BASE_IDX 2 3524 #define mmCURSOR0_4_DMDATA_CNTL 0x09f4 3525 #define mmCURSOR0_4_DMDATA_CNTL_BASE_IDX 2 3526 #define mmCURSOR0_4_DMDATA_QOS_CNTL 0x09f5 3527 #define mmCURSOR0_4_DMDATA_QOS_CNTL_BASE_IDX 2 3528 #define mmCURSOR0_4_DMDATA_STATUS 0x09f6 3529 #define mmCURSOR0_4_DMDATA_STATUS_BASE_IDX 2 3530 #define mmCURSOR0_4_DMDATA_SW_CNTL 0x09f7 3531 #define mmCURSOR0_4_DMDATA_SW_CNTL_BASE_IDX 2 3532 #define mmCURSOR0_4_DMDATA_SW_DATA 0x09f8 3533 #define mmCURSOR0_4_DMDATA_SW_DATA_BASE_IDX 2 3534 3535 3536 // addressBlock: dce_dc_dcbubp4_dispdec_hubp_dcperfmon_dc_perfmon_dispdec 3537 // base address: 0x2834 3538 #define mmDC_PERFMON10_PERFCOUNTER_CNTL 0x0a0d 3539 #define mmDC_PERFMON10_PERFCOUNTER_CNTL_BASE_IDX 2 3540 #define mmDC_PERFMON10_PERFCOUNTER_CNTL2 0x0a0e 3541 #define mmDC_PERFMON10_PERFCOUNTER_CNTL2_BASE_IDX 2 3542 #define mmDC_PERFMON10_PERFCOUNTER_STATE 0x0a0f 3543 #define mmDC_PERFMON10_PERFCOUNTER_STATE_BASE_IDX 2 3544 #define mmDC_PERFMON10_PERFMON_CNTL 0x0a10 3545 #define mmDC_PERFMON10_PERFMON_CNTL_BASE_IDX 2 3546 #define mmDC_PERFMON10_PERFMON_CNTL2 0x0a11 3547 #define mmDC_PERFMON10_PERFMON_CNTL2_BASE_IDX 2 3548 #define mmDC_PERFMON10_PERFMON_CVALUE_INT_MISC 0x0a12 3549 #define mmDC_PERFMON10_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 3550 #define mmDC_PERFMON10_PERFMON_CVALUE_LOW 0x0a13 3551 #define mmDC_PERFMON10_PERFMON_CVALUE_LOW_BASE_IDX 2 3552 #define mmDC_PERFMON10_PERFMON_HI 0x0a14 3553 #define mmDC_PERFMON10_PERFMON_HI_BASE_IDX 2 3554 #define mmDC_PERFMON10_PERFMON_LOW 0x0a15 3555 #define mmDC_PERFMON10_PERFMON_LOW_BASE_IDX 2 3556 3557 3558 // addressBlock: dce_dc_dcbubp5_dispdec_hubp_dispdec 3559 // base address: 0x1130 3560 #define mmHUBP5_DCSURF_SURFACE_CONFIG 0x0a31 3561 #define mmHUBP5_DCSURF_SURFACE_CONFIG_BASE_IDX 2 3562 #define mmHUBP5_DCSURF_ADDR_CONFIG 0x0a32 3563 #define mmHUBP5_DCSURF_ADDR_CONFIG_BASE_IDX 2 3564 #define mmHUBP5_DCSURF_TILING_CONFIG 0x0a33 3565 #define mmHUBP5_DCSURF_TILING_CONFIG_BASE_IDX 2 3566 #define mmHUBP5_DCSURF_PRI_VIEWPORT_START 0x0a35 3567 #define mmHUBP5_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2 3568 #define mmHUBP5_DCSURF_PRI_VIEWPORT_DIMENSION 0x0a36 3569 #define mmHUBP5_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 3570 #define mmHUBP5_DCSURF_PRI_VIEWPORT_START_C 0x0a37 3571 #define mmHUBP5_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2 3572 #define mmHUBP5_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x0a38 3573 #define mmHUBP5_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2 3574 #define mmHUBP5_DCSURF_SEC_VIEWPORT_START 0x0a39 3575 #define mmHUBP5_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2 3576 #define mmHUBP5_DCSURF_SEC_VIEWPORT_DIMENSION 0x0a3a 3577 #define mmHUBP5_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2 3578 #define mmHUBP5_DCSURF_SEC_VIEWPORT_START_C 0x0a3b 3579 #define mmHUBP5_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2 3580 #define mmHUBP5_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x0a3c 3581 #define mmHUBP5_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2 3582 #define mmHUBP5_DCHUBP_REQ_SIZE_CONFIG 0x0a3d 3583 #define mmHUBP5_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2 3584 #define mmHUBP5_DCHUBP_REQ_SIZE_CONFIG_C 0x0a3e 3585 #define mmHUBP5_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2 3586 #define mmHUBP5_DCHUBP_CNTL 0x0a3f 3587 #define mmHUBP5_DCHUBP_CNTL_BASE_IDX 2 3588 #define mmHUBP5_HUBP_CLK_CNTL 0x0a40 3589 #define mmHUBP5_HUBP_CLK_CNTL_BASE_IDX 2 3590 #define mmHUBP5_DCHUBP_VMPG_CONFIG 0x0a41 3591 #define mmHUBP5_DCHUBP_VMPG_CONFIG_BASE_IDX 2 3592 #define mmHUBP5_HUBPREQ_DEBUG_DB 0x0a42 3593 #define mmHUBP5_HUBPREQ_DEBUG_DB_BASE_IDX 2 3594 #define mmHUBP5_HUBPREQ_DEBUG 0x0a43 3595 #define mmHUBP5_HUBPREQ_DEBUG_BASE_IDX 2 3596 #define mmHUBP5_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x0a47 3597 #define mmHUBP5_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2 3598 #define mmHUBP5_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x0a48 3599 #define mmHUBP5_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2 3600 3601 3602 // addressBlock: dce_dc_dcbubp5_dispdec_hubpreq_dispdec 3603 // base address: 0x1130 3604 #define mmHUBPREQ5_DCSURF_SURFACE_PITCH 0x0a53 3605 #define mmHUBPREQ5_DCSURF_SURFACE_PITCH_BASE_IDX 2 3606 #define mmHUBPREQ5_DCSURF_SURFACE_PITCH_C 0x0a54 3607 #define mmHUBPREQ5_DCSURF_SURFACE_PITCH_C_BASE_IDX 2 3608 #define mmHUBPREQ5_VMID_SETTINGS_0 0x0a55 3609 #define mmHUBPREQ5_VMID_SETTINGS_0_BASE_IDX 2 3610 #define mmHUBPREQ5_DCSURF_PRIMARY_SURFACE_ADDRESS 0x0a56 3611 #define mmHUBPREQ5_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2 3612 #define mmHUBPREQ5_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x0a57 3613 #define mmHUBPREQ5_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 3614 #define mmHUBPREQ5_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x0a58 3615 #define mmHUBPREQ5_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2 3616 #define mmHUBPREQ5_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x0a59 3617 #define mmHUBPREQ5_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 3618 #define mmHUBPREQ5_DCSURF_SECONDARY_SURFACE_ADDRESS 0x0a5a 3619 #define mmHUBPREQ5_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2 3620 #define mmHUBPREQ5_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x0a5b 3621 #define mmHUBPREQ5_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 3622 #define mmHUBPREQ5_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x0a5c 3623 #define mmHUBPREQ5_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2 3624 #define mmHUBPREQ5_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x0a5d 3625 #define mmHUBPREQ5_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 3626 #define mmHUBPREQ5_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x0a5e 3627 #define mmHUBPREQ5_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2 3628 #define mmHUBPREQ5_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x0a5f 3629 #define mmHUBPREQ5_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 3630 #define mmHUBPREQ5_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x0a60 3631 #define mmHUBPREQ5_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 3632 #define mmHUBPREQ5_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x0a61 3633 #define mmHUBPREQ5_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 3634 #define mmHUBPREQ5_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x0a62 3635 #define mmHUBPREQ5_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2 3636 #define mmHUBPREQ5_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x0a63 3637 #define mmHUBPREQ5_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 3638 #define mmHUBPREQ5_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x0a64 3639 #define mmHUBPREQ5_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 3640 #define mmHUBPREQ5_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x0a65 3641 #define mmHUBPREQ5_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 3642 #define mmHUBPREQ5_DCSURF_SURFACE_CONTROL 0x0a66 3643 #define mmHUBPREQ5_DCSURF_SURFACE_CONTROL_BASE_IDX 2 3644 #define mmHUBPREQ5_DCSURF_FLIP_CONTROL 0x0a67 3645 #define mmHUBPREQ5_DCSURF_FLIP_CONTROL_BASE_IDX 2 3646 #define mmHUBPREQ5_DCSURF_FLIP_CONTROL2 0x0a68 3647 #define mmHUBPREQ5_DCSURF_FLIP_CONTROL2_BASE_IDX 2 3648 #define mmHUBPREQ5_DCSURF_SURFACE_FLIP_INTERRUPT 0x0a6c 3649 #define mmHUBPREQ5_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2 3650 #define mmHUBPREQ5_DCSURF_SURFACE_INUSE 0x0a6d 3651 #define mmHUBPREQ5_DCSURF_SURFACE_INUSE_BASE_IDX 2 3652 #define mmHUBPREQ5_DCSURF_SURFACE_INUSE_HIGH 0x0a6e 3653 #define mmHUBPREQ5_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2 3654 #define mmHUBPREQ5_DCSURF_SURFACE_INUSE_C 0x0a6f 3655 #define mmHUBPREQ5_DCSURF_SURFACE_INUSE_C_BASE_IDX 2 3656 #define mmHUBPREQ5_DCSURF_SURFACE_INUSE_HIGH_C 0x0a70 3657 #define mmHUBPREQ5_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2 3658 #define mmHUBPREQ5_DCSURF_SURFACE_EARLIEST_INUSE 0x0a71 3659 #define mmHUBPREQ5_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2 3660 #define mmHUBPREQ5_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x0a72 3661 #define mmHUBPREQ5_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2 3662 #define mmHUBPREQ5_DCSURF_SURFACE_EARLIEST_INUSE_C 0x0a73 3663 #define mmHUBPREQ5_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2 3664 #define mmHUBPREQ5_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x0a74 3665 #define mmHUBPREQ5_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2 3666 #define mmHUBPREQ5_DCN_EXPANSION_MODE 0x0a75 3667 #define mmHUBPREQ5_DCN_EXPANSION_MODE_BASE_IDX 2 3668 #define mmHUBPREQ5_DCN_TTU_QOS_WM 0x0a76 3669 #define mmHUBPREQ5_DCN_TTU_QOS_WM_BASE_IDX 2 3670 #define mmHUBPREQ5_DCN_GLOBAL_TTU_CNTL 0x0a77 3671 #define mmHUBPREQ5_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2 3672 #define mmHUBPREQ5_DCN_SURF0_TTU_CNTL0 0x0a78 3673 #define mmHUBPREQ5_DCN_SURF0_TTU_CNTL0_BASE_IDX 2 3674 #define mmHUBPREQ5_DCN_SURF0_TTU_CNTL1 0x0a79 3675 #define mmHUBPREQ5_DCN_SURF0_TTU_CNTL1_BASE_IDX 2 3676 #define mmHUBPREQ5_DCN_SURF1_TTU_CNTL0 0x0a7a 3677 #define mmHUBPREQ5_DCN_SURF1_TTU_CNTL0_BASE_IDX 2 3678 #define mmHUBPREQ5_DCN_SURF1_TTU_CNTL1 0x0a7b 3679 #define mmHUBPREQ5_DCN_SURF1_TTU_CNTL1_BASE_IDX 2 3680 #define mmHUBPREQ5_DCN_CUR0_TTU_CNTL0 0x0a7c 3681 #define mmHUBPREQ5_DCN_CUR0_TTU_CNTL0_BASE_IDX 2 3682 #define mmHUBPREQ5_DCN_CUR0_TTU_CNTL1 0x0a7d 3683 #define mmHUBPREQ5_DCN_CUR0_TTU_CNTL1_BASE_IDX 2 3684 #define mmHUBPREQ5_DCN_CUR1_TTU_CNTL0 0x0a7e 3685 #define mmHUBPREQ5_DCN_CUR1_TTU_CNTL0_BASE_IDX 2 3686 #define mmHUBPREQ5_DCN_CUR1_TTU_CNTL1 0x0a7f 3687 #define mmHUBPREQ5_DCN_CUR1_TTU_CNTL1_BASE_IDX 2 3688 #define mmHUBPREQ5_DCN_DMDATA_VM_CNTL 0x0a80 3689 #define mmHUBPREQ5_DCN_DMDATA_VM_CNTL_BASE_IDX 2 3690 #define mmHUBPREQ5_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x0a81 3691 #define mmHUBPREQ5_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2 3692 #define mmHUBPREQ5_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x0a82 3693 #define mmHUBPREQ5_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2 3694 #define mmHUBPREQ5_DCN_VM_MX_L1_TLB_CNTL 0x0a8f 3695 #define mmHUBPREQ5_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2 3696 #define mmHUBPREQ5_BLANK_OFFSET_0 0x0a90 3697 #define mmHUBPREQ5_BLANK_OFFSET_0_BASE_IDX 2 3698 #define mmHUBPREQ5_BLANK_OFFSET_1 0x0a91 3699 #define mmHUBPREQ5_BLANK_OFFSET_1_BASE_IDX 2 3700 #define mmHUBPREQ5_DST_DIMENSIONS 0x0a92 3701 #define mmHUBPREQ5_DST_DIMENSIONS_BASE_IDX 2 3702 #define mmHUBPREQ5_DST_AFTER_SCALER 0x0a93 3703 #define mmHUBPREQ5_DST_AFTER_SCALER_BASE_IDX 2 3704 #define mmHUBPREQ5_PREFETCH_SETTINGS 0x0a94 3705 #define mmHUBPREQ5_PREFETCH_SETTINGS_BASE_IDX 2 3706 #define mmHUBPREQ5_PREFETCH_SETTINGS_C 0x0a95 3707 #define mmHUBPREQ5_PREFETCH_SETTINGS_C_BASE_IDX 2 3708 #define mmHUBPREQ5_VBLANK_PARAMETERS_0 0x0a96 3709 #define mmHUBPREQ5_VBLANK_PARAMETERS_0_BASE_IDX 2 3710 #define mmHUBPREQ5_VBLANK_PARAMETERS_1 0x0a97 3711 #define mmHUBPREQ5_VBLANK_PARAMETERS_1_BASE_IDX 2 3712 #define mmHUBPREQ5_VBLANK_PARAMETERS_2 0x0a98 3713 #define mmHUBPREQ5_VBLANK_PARAMETERS_2_BASE_IDX 2 3714 #define mmHUBPREQ5_VBLANK_PARAMETERS_3 0x0a99 3715 #define mmHUBPREQ5_VBLANK_PARAMETERS_3_BASE_IDX 2 3716 #define mmHUBPREQ5_VBLANK_PARAMETERS_4 0x0a9a 3717 #define mmHUBPREQ5_VBLANK_PARAMETERS_4_BASE_IDX 2 3718 #define mmHUBPREQ5_FLIP_PARAMETERS_0 0x0a9b 3719 #define mmHUBPREQ5_FLIP_PARAMETERS_0_BASE_IDX 2 3720 #define mmHUBPREQ5_FLIP_PARAMETERS_1 0x0a9c 3721 #define mmHUBPREQ5_FLIP_PARAMETERS_1_BASE_IDX 2 3722 #define mmHUBPREQ5_FLIP_PARAMETERS_2 0x0a9d 3723 #define mmHUBPREQ5_FLIP_PARAMETERS_2_BASE_IDX 2 3724 #define mmHUBPREQ5_NOM_PARAMETERS_0 0x0a9e 3725 #define mmHUBPREQ5_NOM_PARAMETERS_0_BASE_IDX 2 3726 #define mmHUBPREQ5_NOM_PARAMETERS_1 0x0a9f 3727 #define mmHUBPREQ5_NOM_PARAMETERS_1_BASE_IDX 2 3728 #define mmHUBPREQ5_NOM_PARAMETERS_2 0x0aa0 3729 #define mmHUBPREQ5_NOM_PARAMETERS_2_BASE_IDX 2 3730 #define mmHUBPREQ5_NOM_PARAMETERS_3 0x0aa1 3731 #define mmHUBPREQ5_NOM_PARAMETERS_3_BASE_IDX 2 3732 #define mmHUBPREQ5_NOM_PARAMETERS_4 0x0aa2 3733 #define mmHUBPREQ5_NOM_PARAMETERS_4_BASE_IDX 2 3734 #define mmHUBPREQ5_NOM_PARAMETERS_5 0x0aa3 3735 #define mmHUBPREQ5_NOM_PARAMETERS_5_BASE_IDX 2 3736 #define mmHUBPREQ5_NOM_PARAMETERS_6 0x0aa4 3737 #define mmHUBPREQ5_NOM_PARAMETERS_6_BASE_IDX 2 3738 #define mmHUBPREQ5_NOM_PARAMETERS_7 0x0aa5 3739 #define mmHUBPREQ5_NOM_PARAMETERS_7_BASE_IDX 2 3740 #define mmHUBPREQ5_PER_LINE_DELIVERY_PRE 0x0aa6 3741 #define mmHUBPREQ5_PER_LINE_DELIVERY_PRE_BASE_IDX 2 3742 #define mmHUBPREQ5_PER_LINE_DELIVERY 0x0aa7 3743 #define mmHUBPREQ5_PER_LINE_DELIVERY_BASE_IDX 2 3744 #define mmHUBPREQ5_CURSOR_SETTINGS 0x0aa8 3745 #define mmHUBPREQ5_CURSOR_SETTINGS_BASE_IDX 2 3746 #define mmHUBPREQ5_REF_FREQ_TO_PIX_FREQ 0x0aa9 3747 #define mmHUBPREQ5_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2 3748 #define mmHUBPREQ5_DST_Y_DELTA_DRQ_LIMIT 0x0aaa 3749 #define mmHUBPREQ5_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2 3750 #define mmHUBPREQ5_HUBPREQ_MEM_PWR_CTRL 0x0aab 3751 #define mmHUBPREQ5_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2 3752 #define mmHUBPREQ5_HUBPREQ_MEM_PWR_STATUS 0x0aac 3753 #define mmHUBPREQ5_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2 3754 #define mmHUBPREQ5_VBLANK_PARAMETERS_5 0x0aaf 3755 #define mmHUBPREQ5_VBLANK_PARAMETERS_5_BASE_IDX 2 3756 #define mmHUBPREQ5_VBLANK_PARAMETERS_6 0x0ab0 3757 #define mmHUBPREQ5_VBLANK_PARAMETERS_6_BASE_IDX 2 3758 #define mmHUBPREQ5_FLIP_PARAMETERS_3 0x0ab1 3759 #define mmHUBPREQ5_FLIP_PARAMETERS_3_BASE_IDX 2 3760 #define mmHUBPREQ5_FLIP_PARAMETERS_4 0x0ab2 3761 #define mmHUBPREQ5_FLIP_PARAMETERS_4_BASE_IDX 2 3762 #define mmHUBPREQ5_FLIP_PARAMETERS_5 0x0ab3 3763 #define mmHUBPREQ5_FLIP_PARAMETERS_5_BASE_IDX 2 3764 #define mmHUBPREQ5_FLIP_PARAMETERS_6 0x0ab4 3765 #define mmHUBPREQ5_FLIP_PARAMETERS_6_BASE_IDX 2 3766 3767 3768 // addressBlock: dce_dc_dcbubp5_dispdec_hubpret_dispdec 3769 // base address: 0x1130 3770 #define mmHUBPRET5_HUBPRET_CONTROL 0x0ab8 3771 #define mmHUBPRET5_HUBPRET_CONTROL_BASE_IDX 2 3772 #define mmHUBPRET5_HUBPRET_MEM_PWR_CTRL 0x0ab9 3773 #define mmHUBPRET5_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2 3774 #define mmHUBPRET5_HUBPRET_MEM_PWR_STATUS 0x0aba 3775 #define mmHUBPRET5_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2 3776 #define mmHUBPRET5_HUBPRET_READ_LINE_CTRL0 0x0abb 3777 #define mmHUBPRET5_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2 3778 #define mmHUBPRET5_HUBPRET_READ_LINE_CTRL1 0x0abc 3779 #define mmHUBPRET5_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2 3780 #define mmHUBPRET5_HUBPRET_READ_LINE0 0x0abd 3781 #define mmHUBPRET5_HUBPRET_READ_LINE0_BASE_IDX 2 3782 #define mmHUBPRET5_HUBPRET_READ_LINE1 0x0abe 3783 #define mmHUBPRET5_HUBPRET_READ_LINE1_BASE_IDX 2 3784 #define mmHUBPRET5_HUBPRET_INTERRUPT 0x0abf 3785 #define mmHUBPRET5_HUBPRET_INTERRUPT_BASE_IDX 2 3786 #define mmHUBPRET5_HUBPRET_READ_LINE_VALUE 0x0ac0 3787 #define mmHUBPRET5_HUBPRET_READ_LINE_VALUE_BASE_IDX 2 3788 #define mmHUBPRET5_HUBPRET_READ_LINE_STATUS 0x0ac1 3789 #define mmHUBPRET5_HUBPRET_READ_LINE_STATUS_BASE_IDX 2 3790 3791 3792 // addressBlock: dce_dc_dcbubp5_dispdec_cursor0_dispdec 3793 // base address: 0x1130 3794 #define mmCURSOR0_5_CURSOR_CONTROL 0x0ac4 3795 #define mmCURSOR0_5_CURSOR_CONTROL_BASE_IDX 2 3796 #define mmCURSOR0_5_CURSOR_SURFACE_ADDRESS 0x0ac5 3797 #define mmCURSOR0_5_CURSOR_SURFACE_ADDRESS_BASE_IDX 2 3798 #define mmCURSOR0_5_CURSOR_SURFACE_ADDRESS_HIGH 0x0ac6 3799 #define mmCURSOR0_5_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2 3800 #define mmCURSOR0_5_CURSOR_SIZE 0x0ac7 3801 #define mmCURSOR0_5_CURSOR_SIZE_BASE_IDX 2 3802 #define mmCURSOR0_5_CURSOR_POSITION 0x0ac8 3803 #define mmCURSOR0_5_CURSOR_POSITION_BASE_IDX 2 3804 #define mmCURSOR0_5_CURSOR_HOT_SPOT 0x0ac9 3805 #define mmCURSOR0_5_CURSOR_HOT_SPOT_BASE_IDX 2 3806 #define mmCURSOR0_5_CURSOR_STEREO_CONTROL 0x0aca 3807 #define mmCURSOR0_5_CURSOR_STEREO_CONTROL_BASE_IDX 2 3808 #define mmCURSOR0_5_CURSOR_DST_OFFSET 0x0acb 3809 #define mmCURSOR0_5_CURSOR_DST_OFFSET_BASE_IDX 2 3810 #define mmCURSOR0_5_CURSOR_MEM_PWR_CTRL 0x0acc 3811 #define mmCURSOR0_5_CURSOR_MEM_PWR_CTRL_BASE_IDX 2 3812 #define mmCURSOR0_5_CURSOR_MEM_PWR_STATUS 0x0acd 3813 #define mmCURSOR0_5_CURSOR_MEM_PWR_STATUS_BASE_IDX 2 3814 #define mmCURSOR0_5_DMDATA_ADDRESS_HIGH 0x0ace 3815 #define mmCURSOR0_5_DMDATA_ADDRESS_HIGH_BASE_IDX 2 3816 #define mmCURSOR0_5_DMDATA_ADDRESS_LOW 0x0acf 3817 #define mmCURSOR0_5_DMDATA_ADDRESS_LOW_BASE_IDX 2 3818 #define mmCURSOR0_5_DMDATA_CNTL 0x0ad0 3819 #define mmCURSOR0_5_DMDATA_CNTL_BASE_IDX 2 3820 #define mmCURSOR0_5_DMDATA_QOS_CNTL 0x0ad1 3821 #define mmCURSOR0_5_DMDATA_QOS_CNTL_BASE_IDX 2 3822 #define mmCURSOR0_5_DMDATA_STATUS 0x0ad2 3823 #define mmCURSOR0_5_DMDATA_STATUS_BASE_IDX 2 3824 #define mmCURSOR0_5_DMDATA_SW_CNTL 0x0ad3 3825 #define mmCURSOR0_5_DMDATA_SW_CNTL_BASE_IDX 2 3826 #define mmCURSOR0_5_DMDATA_SW_DATA 0x0ad4 3827 #define mmCURSOR0_5_DMDATA_SW_DATA_BASE_IDX 2 3828 3829 3830 // addressBlock: dce_dc_dcbubp5_dispdec_hubp_dcperfmon_dc_perfmon_dispdec 3831 // base address: 0x2ba4 3832 #define mmDC_PERFMON11_PERFCOUNTER_CNTL 0x0ae9 3833 #define mmDC_PERFMON11_PERFCOUNTER_CNTL_BASE_IDX 2 3834 #define mmDC_PERFMON11_PERFCOUNTER_CNTL2 0x0aea 3835 #define mmDC_PERFMON11_PERFCOUNTER_CNTL2_BASE_IDX 2 3836 #define mmDC_PERFMON11_PERFCOUNTER_STATE 0x0aeb 3837 #define mmDC_PERFMON11_PERFCOUNTER_STATE_BASE_IDX 2 3838 #define mmDC_PERFMON11_PERFMON_CNTL 0x0aec 3839 #define mmDC_PERFMON11_PERFMON_CNTL_BASE_IDX 2 3840 #define mmDC_PERFMON11_PERFMON_CNTL2 0x0aed 3841 #define mmDC_PERFMON11_PERFMON_CNTL2_BASE_IDX 2 3842 #define mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC 0x0aee 3843 #define mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 3844 #define mmDC_PERFMON11_PERFMON_CVALUE_LOW 0x0aef 3845 #define mmDC_PERFMON11_PERFMON_CVALUE_LOW_BASE_IDX 2 3846 #define mmDC_PERFMON11_PERFMON_HI 0x0af0 3847 #define mmDC_PERFMON11_PERFMON_HI_BASE_IDX 2 3848 #define mmDC_PERFMON11_PERFMON_LOW 0x0af1 3849 #define mmDC_PERFMON11_PERFMON_LOW_BASE_IDX 2 3850 3851 3852 // addressBlock: dce_dc_dpp0_dispdec_dpp_top_dispdec 3853 // base address: 0x0 3854 #define mmDPP_TOP0_DPP_CONTROL 0x0cc5 3855 #define mmDPP_TOP0_DPP_CONTROL_BASE_IDX 2 3856 #define mmDPP_TOP0_DPP_SOFT_RESET 0x0cc6 3857 #define mmDPP_TOP0_DPP_SOFT_RESET_BASE_IDX 2 3858 #define mmDPP_TOP0_DPP_CRC_VAL_R_G 0x0cc7 3859 #define mmDPP_TOP0_DPP_CRC_VAL_R_G_BASE_IDX 2 3860 #define mmDPP_TOP0_DPP_CRC_VAL_B_A 0x0cc8 3861 #define mmDPP_TOP0_DPP_CRC_VAL_B_A_BASE_IDX 2 3862 #define mmDPP_TOP0_DPP_CRC_CTRL 0x0cc9 3863 #define mmDPP_TOP0_DPP_CRC_CTRL_BASE_IDX 2 3864 #define mmDPP_TOP0_HOST_READ_CONTROL 0x0cca 3865 #define mmDPP_TOP0_HOST_READ_CONTROL_BASE_IDX 2 3866 3867 3868 // addressBlock: dce_dc_dpp0_dispdec_cnvc_cfg_dispdec 3869 // base address: 0x0 3870 #define mmCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT 0x0ccf 3871 #define mmCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2 3872 #define mmCNVC_CFG0_FORMAT_CONTROL 0x0cd0 3873 #define mmCNVC_CFG0_FORMAT_CONTROL_BASE_IDX 2 3874 #define mmCNVC_CFG0_FCNV_FP_BIAS_R 0x0cd1 3875 #define mmCNVC_CFG0_FCNV_FP_BIAS_R_BASE_IDX 2 3876 #define mmCNVC_CFG0_FCNV_FP_BIAS_G 0x0cd2 3877 #define mmCNVC_CFG0_FCNV_FP_BIAS_G_BASE_IDX 2 3878 #define mmCNVC_CFG0_FCNV_FP_BIAS_B 0x0cd3 3879 #define mmCNVC_CFG0_FCNV_FP_BIAS_B_BASE_IDX 2 3880 #define mmCNVC_CFG0_FCNV_FP_SCALE_R 0x0cd4 3881 #define mmCNVC_CFG0_FCNV_FP_SCALE_R_BASE_IDX 2 3882 #define mmCNVC_CFG0_FCNV_FP_SCALE_G 0x0cd5 3883 #define mmCNVC_CFG0_FCNV_FP_SCALE_G_BASE_IDX 2 3884 #define mmCNVC_CFG0_FCNV_FP_SCALE_B 0x0cd6 3885 #define mmCNVC_CFG0_FCNV_FP_SCALE_B_BASE_IDX 2 3886 #define mmCNVC_CFG0_COLOR_KEYER_CONTROL 0x0cd7 3887 #define mmCNVC_CFG0_COLOR_KEYER_CONTROL_BASE_IDX 2 3888 #define mmCNVC_CFG0_COLOR_KEYER_ALPHA 0x0cd8 3889 #define mmCNVC_CFG0_COLOR_KEYER_ALPHA_BASE_IDX 2 3890 #define mmCNVC_CFG0_COLOR_KEYER_RED 0x0cd9 3891 #define mmCNVC_CFG0_COLOR_KEYER_RED_BASE_IDX 2 3892 #define mmCNVC_CFG0_COLOR_KEYER_GREEN 0x0cda 3893 #define mmCNVC_CFG0_COLOR_KEYER_GREEN_BASE_IDX 2 3894 #define mmCNVC_CFG0_COLOR_KEYER_BLUE 0x0cdb 3895 #define mmCNVC_CFG0_COLOR_KEYER_BLUE_BASE_IDX 2 3896 #define mmCNVC_CFG0_ALPHA_2BIT_LUT 0x0cdd 3897 #define mmCNVC_CFG0_ALPHA_2BIT_LUT_BASE_IDX 2 3898 #define mmCNVC_CFG0_PRE_DEALPHA 0x0cde 3899 #define mmCNVC_CFG0_PRE_DEALPHA_BASE_IDX 2 3900 #define mmCNVC_CFG0_PRE_CSC_MODE 0x0cdf 3901 #define mmCNVC_CFG0_PRE_CSC_MODE_BASE_IDX 2 3902 #define mmCNVC_CFG0_PRE_CSC_C11_C12 0x0ce0 3903 #define mmCNVC_CFG0_PRE_CSC_C11_C12_BASE_IDX 2 3904 #define mmCNVC_CFG0_PRE_CSC_C13_C14 0x0ce1 3905 #define mmCNVC_CFG0_PRE_CSC_C13_C14_BASE_IDX 2 3906 #define mmCNVC_CFG0_PRE_CSC_C21_C22 0x0ce2 3907 #define mmCNVC_CFG0_PRE_CSC_C21_C22_BASE_IDX 2 3908 #define mmCNVC_CFG0_PRE_CSC_C23_C24 0x0ce3 3909 #define mmCNVC_CFG0_PRE_CSC_C23_C24_BASE_IDX 2 3910 #define mmCNVC_CFG0_PRE_CSC_C31_C32 0x0ce4 3911 #define mmCNVC_CFG0_PRE_CSC_C31_C32_BASE_IDX 2 3912 #define mmCNVC_CFG0_PRE_CSC_C33_C34 0x0ce5 3913 #define mmCNVC_CFG0_PRE_CSC_C33_C34_BASE_IDX 2 3914 #define mmCNVC_CFG0_PRE_CSC_B_C11_C12 0x0ce6 3915 #define mmCNVC_CFG0_PRE_CSC_B_C11_C12_BASE_IDX 2 3916 #define mmCNVC_CFG0_PRE_CSC_B_C13_C14 0x0ce7 3917 #define mmCNVC_CFG0_PRE_CSC_B_C13_C14_BASE_IDX 2 3918 #define mmCNVC_CFG0_PRE_CSC_B_C21_C22 0x0ce8 3919 #define mmCNVC_CFG0_PRE_CSC_B_C21_C22_BASE_IDX 2 3920 #define mmCNVC_CFG0_PRE_CSC_B_C23_C24 0x0ce9 3921 #define mmCNVC_CFG0_PRE_CSC_B_C23_C24_BASE_IDX 2 3922 #define mmCNVC_CFG0_PRE_CSC_B_C31_C32 0x0cea 3923 #define mmCNVC_CFG0_PRE_CSC_B_C31_C32_BASE_IDX 2 3924 #define mmCNVC_CFG0_PRE_CSC_B_C33_C34 0x0ceb 3925 #define mmCNVC_CFG0_PRE_CSC_B_C33_C34_BASE_IDX 2 3926 #define mmCNVC_CFG0_CNVC_COEF_FORMAT 0x0cec 3927 #define mmCNVC_CFG0_CNVC_COEF_FORMAT_BASE_IDX 2 3928 #define mmCNVC_CFG0_PRE_DEGAM 0x0ced 3929 #define mmCNVC_CFG0_PRE_DEGAM_BASE_IDX 2 3930 #define mmCNVC_CFG0_PRE_REALPHA 0x0cee 3931 #define mmCNVC_CFG0_PRE_REALPHA_BASE_IDX 2 3932 3933 3934 // addressBlock: dce_dc_dpp0_dispdec_cnvc_cur_dispdec 3935 // base address: 0x0 3936 #define mmCNVC_CUR0_CURSOR0_CONTROL 0x0cf1 3937 #define mmCNVC_CUR0_CURSOR0_CONTROL_BASE_IDX 2 3938 #define mmCNVC_CUR0_CURSOR0_COLOR0 0x0cf2 3939 #define mmCNVC_CUR0_CURSOR0_COLOR0_BASE_IDX 2 3940 #define mmCNVC_CUR0_CURSOR0_COLOR1 0x0cf3 3941 #define mmCNVC_CUR0_CURSOR0_COLOR1_BASE_IDX 2 3942 #define mmCNVC_CUR0_CURSOR0_FP_SCALE_BIAS 0x0cf4 3943 #define mmCNVC_CUR0_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2 3944 3945 3946 // addressBlock: dce_dc_dpp0_dispdec_dscl_dispdec 3947 // base address: 0x0 3948 #define mmDSCL0_SCL_COEF_RAM_TAP_SELECT 0x0cf9 3949 #define mmDSCL0_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2 3950 #define mmDSCL0_SCL_COEF_RAM_TAP_DATA 0x0cfa 3951 #define mmDSCL0_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2 3952 #define mmDSCL0_SCL_MODE 0x0cfb 3953 #define mmDSCL0_SCL_MODE_BASE_IDX 2 3954 #define mmDSCL0_SCL_TAP_CONTROL 0x0cfc 3955 #define mmDSCL0_SCL_TAP_CONTROL_BASE_IDX 2 3956 #define mmDSCL0_DSCL_CONTROL 0x0cfd 3957 #define mmDSCL0_DSCL_CONTROL_BASE_IDX 2 3958 #define mmDSCL0_DSCL_2TAP_CONTROL 0x0cfe 3959 #define mmDSCL0_DSCL_2TAP_CONTROL_BASE_IDX 2 3960 #define mmDSCL0_SCL_MANUAL_REPLICATE_CONTROL 0x0cff 3961 #define mmDSCL0_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 3962 #define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO 0x0d00 3963 #define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 3964 #define mmDSCL0_SCL_HORZ_FILTER_INIT 0x0d01 3965 #define mmDSCL0_SCL_HORZ_FILTER_INIT_BASE_IDX 2 3966 #define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C 0x0d02 3967 #define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2 3968 #define mmDSCL0_SCL_HORZ_FILTER_INIT_C 0x0d03 3969 #define mmDSCL0_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2 3970 #define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO 0x0d04 3971 #define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 3972 #define mmDSCL0_SCL_VERT_FILTER_INIT 0x0d05 3973 #define mmDSCL0_SCL_VERT_FILTER_INIT_BASE_IDX 2 3974 #define mmDSCL0_SCL_VERT_FILTER_INIT_BOT 0x0d06 3975 #define mmDSCL0_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2 3976 #define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C 0x0d07 3977 #define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2 3978 #define mmDSCL0_SCL_VERT_FILTER_INIT_C 0x0d08 3979 #define mmDSCL0_SCL_VERT_FILTER_INIT_C_BASE_IDX 2 3980 #define mmDSCL0_SCL_VERT_FILTER_INIT_BOT_C 0x0d09 3981 #define mmDSCL0_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2 3982 #define mmDSCL0_SCL_BLACK_COLOR 0x0d0a 3983 #define mmDSCL0_SCL_BLACK_COLOR_BASE_IDX 2 3984 #define mmDSCL0_DSCL_UPDATE 0x0d0b 3985 #define mmDSCL0_DSCL_UPDATE_BASE_IDX 2 3986 #define mmDSCL0_DSCL_AUTOCAL 0x0d0c 3987 #define mmDSCL0_DSCL_AUTOCAL_BASE_IDX 2 3988 #define mmDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x0d0d 3989 #define mmDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 3990 #define mmDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x0d0e 3991 #define mmDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 3992 #define mmDSCL0_OTG_H_BLANK 0x0d0f 3993 #define mmDSCL0_OTG_H_BLANK_BASE_IDX 2 3994 #define mmDSCL0_OTG_V_BLANK 0x0d10 3995 #define mmDSCL0_OTG_V_BLANK_BASE_IDX 2 3996 #define mmDSCL0_RECOUT_START 0x0d11 3997 #define mmDSCL0_RECOUT_START_BASE_IDX 2 3998 #define mmDSCL0_RECOUT_SIZE 0x0d12 3999 #define mmDSCL0_RECOUT_SIZE_BASE_IDX 2 4000 #define mmDSCL0_MPC_SIZE 0x0d13 4001 #define mmDSCL0_MPC_SIZE_BASE_IDX 2 4002 #define mmDSCL0_LB_DATA_FORMAT 0x0d14 4003 #define mmDSCL0_LB_DATA_FORMAT_BASE_IDX 2 4004 #define mmDSCL0_LB_MEMORY_CTRL 0x0d15 4005 #define mmDSCL0_LB_MEMORY_CTRL_BASE_IDX 2 4006 #define mmDSCL0_LB_V_COUNTER 0x0d16 4007 #define mmDSCL0_LB_V_COUNTER_BASE_IDX 2 4008 #define mmDSCL0_DSCL_MEM_PWR_CTRL 0x0d17 4009 #define mmDSCL0_DSCL_MEM_PWR_CTRL_BASE_IDX 2 4010 #define mmDSCL0_DSCL_MEM_PWR_STATUS 0x0d18 4011 #define mmDSCL0_DSCL_MEM_PWR_STATUS_BASE_IDX 2 4012 #define mmDSCL0_OBUF_CONTROL 0x0d19 4013 #define mmDSCL0_OBUF_CONTROL_BASE_IDX 2 4014 #define mmDSCL0_OBUF_MEM_PWR_CTRL 0x0d1a 4015 #define mmDSCL0_OBUF_MEM_PWR_CTRL_BASE_IDX 2 4016 4017 4018 // addressBlock: dce_dc_dpp0_dispdec_cm_dispdec 4019 // base address: 0x0 4020 #define mmCM0_CM_CONTROL 0x0d20 4021 #define mmCM0_CM_CONTROL_BASE_IDX 2 4022 #define mmCM0_CM_POST_CSC_CONTROL 0x0d21 4023 #define mmCM0_CM_POST_CSC_CONTROL_BASE_IDX 2 4024 #define mmCM0_CM_POST_CSC_C11_C12 0x0d22 4025 #define mmCM0_CM_POST_CSC_C11_C12_BASE_IDX 2 4026 #define mmCM0_CM_POST_CSC_C13_C14 0x0d23 4027 #define mmCM0_CM_POST_CSC_C13_C14_BASE_IDX 2 4028 #define mmCM0_CM_POST_CSC_C21_C22 0x0d24 4029 #define mmCM0_CM_POST_CSC_C21_C22_BASE_IDX 2 4030 #define mmCM0_CM_POST_CSC_C23_C24 0x0d25 4031 #define mmCM0_CM_POST_CSC_C23_C24_BASE_IDX 2 4032 #define mmCM0_CM_POST_CSC_C31_C32 0x0d26 4033 #define mmCM0_CM_POST_CSC_C31_C32_BASE_IDX 2 4034 #define mmCM0_CM_POST_CSC_C33_C34 0x0d27 4035 #define mmCM0_CM_POST_CSC_C33_C34_BASE_IDX 2 4036 #define mmCM0_CM_POST_CSC_B_C11_C12 0x0d28 4037 #define mmCM0_CM_POST_CSC_B_C11_C12_BASE_IDX 2 4038 #define mmCM0_CM_POST_CSC_B_C13_C14 0x0d29 4039 #define mmCM0_CM_POST_CSC_B_C13_C14_BASE_IDX 2 4040 #define mmCM0_CM_POST_CSC_B_C21_C22 0x0d2a 4041 #define mmCM0_CM_POST_CSC_B_C21_C22_BASE_IDX 2 4042 #define mmCM0_CM_POST_CSC_B_C23_C24 0x0d2b 4043 #define mmCM0_CM_POST_CSC_B_C23_C24_BASE_IDX 2 4044 #define mmCM0_CM_POST_CSC_B_C31_C32 0x0d2c 4045 #define mmCM0_CM_POST_CSC_B_C31_C32_BASE_IDX 2 4046 #define mmCM0_CM_POST_CSC_B_C33_C34 0x0d2d 4047 #define mmCM0_CM_POST_CSC_B_C33_C34_BASE_IDX 2 4048 #define mmCM0_CM_GAMUT_REMAP_CONTROL 0x0d2e 4049 #define mmCM0_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2 4050 #define mmCM0_CM_GAMUT_REMAP_C11_C12 0x0d2f 4051 #define mmCM0_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2 4052 #define mmCM0_CM_GAMUT_REMAP_C13_C14 0x0d30 4053 #define mmCM0_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2 4054 #define mmCM0_CM_GAMUT_REMAP_C21_C22 0x0d31 4055 #define mmCM0_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2 4056 #define mmCM0_CM_GAMUT_REMAP_C23_C24 0x0d32 4057 #define mmCM0_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2 4058 #define mmCM0_CM_GAMUT_REMAP_C31_C32 0x0d33 4059 #define mmCM0_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2 4060 #define mmCM0_CM_GAMUT_REMAP_C33_C34 0x0d34 4061 #define mmCM0_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2 4062 #define mmCM0_CM_GAMUT_REMAP_B_C11_C12 0x0d35 4063 #define mmCM0_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX 2 4064 #define mmCM0_CM_GAMUT_REMAP_B_C13_C14 0x0d36 4065 #define mmCM0_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX 2 4066 #define mmCM0_CM_GAMUT_REMAP_B_C21_C22 0x0d37 4067 #define mmCM0_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX 2 4068 #define mmCM0_CM_GAMUT_REMAP_B_C23_C24 0x0d38 4069 #define mmCM0_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX 2 4070 #define mmCM0_CM_GAMUT_REMAP_B_C31_C32 0x0d39 4071 #define mmCM0_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX 2 4072 #define mmCM0_CM_GAMUT_REMAP_B_C33_C34 0x0d3a 4073 #define mmCM0_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX 2 4074 #define mmCM0_CM_BIAS_CR_R 0x0d3b 4075 #define mmCM0_CM_BIAS_CR_R_BASE_IDX 2 4076 #define mmCM0_CM_BIAS_Y_G_CB_B 0x0d3c 4077 #define mmCM0_CM_BIAS_Y_G_CB_B_BASE_IDX 2 4078 #define mmCM0_CM_GAMCOR_CONTROL 0x0d3d 4079 #define mmCM0_CM_GAMCOR_CONTROL_BASE_IDX 2 4080 #define mmCM0_CM_GAMCOR_LUT_INDEX 0x0d3e 4081 #define mmCM0_CM_GAMCOR_LUT_INDEX_BASE_IDX 2 4082 #define mmCM0_CM_GAMCOR_LUT_DATA 0x0d3f 4083 #define mmCM0_CM_GAMCOR_LUT_DATA_BASE_IDX 2 4084 #define mmCM0_CM_GAMCOR_LUT_CONTROL 0x0d40 4085 #define mmCM0_CM_GAMCOR_LUT_CONTROL_BASE_IDX 2 4086 #define mmCM0_CM_GAMCOR_RAMA_START_CNTL_B 0x0d41 4087 #define mmCM0_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX 2 4088 #define mmCM0_CM_GAMCOR_RAMA_START_CNTL_G 0x0d42 4089 #define mmCM0_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX 2 4090 #define mmCM0_CM_GAMCOR_RAMA_START_CNTL_R 0x0d43 4091 #define mmCM0_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX 2 4092 #define mmCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B 0x0d44 4093 #define mmCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 4094 #define mmCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G 0x0d45 4095 #define mmCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 4096 #define mmCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R 0x0d46 4097 #define mmCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 4098 #define mmCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B 0x0d47 4099 #define mmCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX 2 4100 #define mmCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G 0x0d48 4101 #define mmCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX 2 4102 #define mmCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R 0x0d49 4103 #define mmCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX 2 4104 #define mmCM0_CM_GAMCOR_RAMA_END_CNTL1_B 0x0d4a 4105 #define mmCM0_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX 2 4106 #define mmCM0_CM_GAMCOR_RAMA_END_CNTL2_B 0x0d4b 4107 #define mmCM0_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX 2 4108 #define mmCM0_CM_GAMCOR_RAMA_END_CNTL1_G 0x0d4c 4109 #define mmCM0_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX 2 4110 #define mmCM0_CM_GAMCOR_RAMA_END_CNTL2_G 0x0d4d 4111 #define mmCM0_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX 2 4112 #define mmCM0_CM_GAMCOR_RAMA_END_CNTL1_R 0x0d4e 4113 #define mmCM0_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX 2 4114 #define mmCM0_CM_GAMCOR_RAMA_END_CNTL2_R 0x0d4f 4115 #define mmCM0_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX 2 4116 #define mmCM0_CM_GAMCOR_RAMA_OFFSET_B 0x0d50 4117 #define mmCM0_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX 2 4118 #define mmCM0_CM_GAMCOR_RAMA_OFFSET_G 0x0d51 4119 #define mmCM0_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX 2 4120 #define mmCM0_CM_GAMCOR_RAMA_OFFSET_R 0x0d52 4121 #define mmCM0_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX 2 4122 #define mmCM0_CM_GAMCOR_RAMA_REGION_0_1 0x0d53 4123 #define mmCM0_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX 2 4124 #define mmCM0_CM_GAMCOR_RAMA_REGION_2_3 0x0d54 4125 #define mmCM0_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX 2 4126 #define mmCM0_CM_GAMCOR_RAMA_REGION_4_5 0x0d55 4127 #define mmCM0_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX 2 4128 #define mmCM0_CM_GAMCOR_RAMA_REGION_6_7 0x0d56 4129 #define mmCM0_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX 2 4130 #define mmCM0_CM_GAMCOR_RAMA_REGION_8_9 0x0d57 4131 #define mmCM0_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX 2 4132 #define mmCM0_CM_GAMCOR_RAMA_REGION_10_11 0x0d58 4133 #define mmCM0_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX 2 4134 #define mmCM0_CM_GAMCOR_RAMA_REGION_12_13 0x0d59 4135 #define mmCM0_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX 2 4136 #define mmCM0_CM_GAMCOR_RAMA_REGION_14_15 0x0d5a 4137 #define mmCM0_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX 2 4138 #define mmCM0_CM_GAMCOR_RAMA_REGION_16_17 0x0d5b 4139 #define mmCM0_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX 2 4140 #define mmCM0_CM_GAMCOR_RAMA_REGION_18_19 0x0d5c 4141 #define mmCM0_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX 2 4142 #define mmCM0_CM_GAMCOR_RAMA_REGION_20_21 0x0d5d 4143 #define mmCM0_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX 2 4144 #define mmCM0_CM_GAMCOR_RAMA_REGION_22_23 0x0d5e 4145 #define mmCM0_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX 2 4146 #define mmCM0_CM_GAMCOR_RAMA_REGION_24_25 0x0d5f 4147 #define mmCM0_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX 2 4148 #define mmCM0_CM_GAMCOR_RAMA_REGION_26_27 0x0d60 4149 #define mmCM0_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX 2 4150 #define mmCM0_CM_GAMCOR_RAMA_REGION_28_29 0x0d61 4151 #define mmCM0_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX 2 4152 #define mmCM0_CM_GAMCOR_RAMA_REGION_30_31 0x0d62 4153 #define mmCM0_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX 2 4154 #define mmCM0_CM_GAMCOR_RAMA_REGION_32_33 0x0d63 4155 #define mmCM0_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX 2 4156 #define mmCM0_CM_GAMCOR_RAMB_START_CNTL_B 0x0d64 4157 #define mmCM0_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX 2 4158 #define mmCM0_CM_GAMCOR_RAMB_START_CNTL_G 0x0d65 4159 #define mmCM0_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX 2 4160 #define mmCM0_CM_GAMCOR_RAMB_START_CNTL_R 0x0d66 4161 #define mmCM0_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX 2 4162 #define mmCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B 0x0d67 4163 #define mmCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 4164 #define mmCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G 0x0d68 4165 #define mmCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 4166 #define mmCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R 0x0d69 4167 #define mmCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 4168 #define mmCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B 0x0d6a 4169 #define mmCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX 2 4170 #define mmCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G 0x0d6b 4171 #define mmCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX 2 4172 #define mmCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R 0x0d6c 4173 #define mmCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX 2 4174 #define mmCM0_CM_GAMCOR_RAMB_END_CNTL1_B 0x0d6d 4175 #define mmCM0_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX 2 4176 #define mmCM0_CM_GAMCOR_RAMB_END_CNTL2_B 0x0d6e 4177 #define mmCM0_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX 2 4178 #define mmCM0_CM_GAMCOR_RAMB_END_CNTL1_G 0x0d6f 4179 #define mmCM0_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX 2 4180 #define mmCM0_CM_GAMCOR_RAMB_END_CNTL2_G 0x0d70 4181 #define mmCM0_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX 2 4182 #define mmCM0_CM_GAMCOR_RAMB_END_CNTL1_R 0x0d71 4183 #define mmCM0_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX 2 4184 #define mmCM0_CM_GAMCOR_RAMB_END_CNTL2_R 0x0d72 4185 #define mmCM0_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX 2 4186 #define mmCM0_CM_GAMCOR_RAMB_OFFSET_B 0x0d73 4187 #define mmCM0_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX 2 4188 #define mmCM0_CM_GAMCOR_RAMB_OFFSET_G 0x0d74 4189 #define mmCM0_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX 2 4190 #define mmCM0_CM_GAMCOR_RAMB_OFFSET_R 0x0d75 4191 #define mmCM0_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX 2 4192 #define mmCM0_CM_GAMCOR_RAMB_REGION_0_1 0x0d76 4193 #define mmCM0_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX 2 4194 #define mmCM0_CM_GAMCOR_RAMB_REGION_2_3 0x0d77 4195 #define mmCM0_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX 2 4196 #define mmCM0_CM_GAMCOR_RAMB_REGION_4_5 0x0d78 4197 #define mmCM0_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX 2 4198 #define mmCM0_CM_GAMCOR_RAMB_REGION_6_7 0x0d79 4199 #define mmCM0_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX 2 4200 #define mmCM0_CM_GAMCOR_RAMB_REGION_8_9 0x0d7a 4201 #define mmCM0_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX 2 4202 #define mmCM0_CM_GAMCOR_RAMB_REGION_10_11 0x0d7b 4203 #define mmCM0_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX 2 4204 #define mmCM0_CM_GAMCOR_RAMB_REGION_12_13 0x0d7c 4205 #define mmCM0_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX 2 4206 #define mmCM0_CM_GAMCOR_RAMB_REGION_14_15 0x0d7d 4207 #define mmCM0_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX 2 4208 #define mmCM0_CM_GAMCOR_RAMB_REGION_16_17 0x0d7e 4209 #define mmCM0_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX 2 4210 #define mmCM0_CM_GAMCOR_RAMB_REGION_18_19 0x0d7f 4211 #define mmCM0_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX 2 4212 #define mmCM0_CM_GAMCOR_RAMB_REGION_20_21 0x0d80 4213 #define mmCM0_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX 2 4214 #define mmCM0_CM_GAMCOR_RAMB_REGION_22_23 0x0d81 4215 #define mmCM0_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX 2 4216 #define mmCM0_CM_GAMCOR_RAMB_REGION_24_25 0x0d82 4217 #define mmCM0_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX 2 4218 #define mmCM0_CM_GAMCOR_RAMB_REGION_26_27 0x0d83 4219 #define mmCM0_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX 2 4220 #define mmCM0_CM_GAMCOR_RAMB_REGION_28_29 0x0d84 4221 #define mmCM0_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX 2 4222 #define mmCM0_CM_GAMCOR_RAMB_REGION_30_31 0x0d85 4223 #define mmCM0_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX 2 4224 #define mmCM0_CM_GAMCOR_RAMB_REGION_32_33 0x0d86 4225 #define mmCM0_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX 2 4226 #define mmCM0_CM_BLNDGAM_CONTROL 0x0d87 4227 #define mmCM0_CM_BLNDGAM_CONTROL_BASE_IDX 2 4228 #define mmCM0_CM_BLNDGAM_LUT_INDEX 0x0d88 4229 #define mmCM0_CM_BLNDGAM_LUT_INDEX_BASE_IDX 2 4230 #define mmCM0_CM_BLNDGAM_LUT_DATA 0x0d89 4231 #define mmCM0_CM_BLNDGAM_LUT_DATA_BASE_IDX 2 4232 #define mmCM0_CM_BLNDGAM_LUT_CONTROL 0x0d8a 4233 #define mmCM0_CM_BLNDGAM_LUT_CONTROL_BASE_IDX 2 4234 #define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_B 0x0d8b 4235 #define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX 2 4236 #define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_G 0x0d8c 4237 #define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX 2 4238 #define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_R 0x0d8d 4239 #define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX 2 4240 #define mmCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B 0x0d8e 4241 #define mmCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 4242 #define mmCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G 0x0d8f 4243 #define mmCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 4244 #define mmCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R 0x0d90 4245 #define mmCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 4246 #define mmCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_B 0x0d91 4247 #define mmCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 2 4248 #define mmCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_G 0x0d92 4249 #define mmCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 2 4250 #define mmCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_R 0x0d93 4251 #define mmCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 2 4252 #define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_B 0x0d94 4253 #define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX 2 4254 #define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_B 0x0d95 4255 #define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX 2 4256 #define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_G 0x0d96 4257 #define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX 2 4258 #define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_G 0x0d97 4259 #define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX 2 4260 #define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_R 0x0d98 4261 #define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX 2 4262 #define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_R 0x0d99 4263 #define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX 2 4264 #define mmCM0_CM_BLNDGAM_RAMA_OFFSET_B 0x0d9a 4265 #define mmCM0_CM_BLNDGAM_RAMA_OFFSET_B_BASE_IDX 2 4266 #define mmCM0_CM_BLNDGAM_RAMA_OFFSET_G 0x0d9b 4267 #define mmCM0_CM_BLNDGAM_RAMA_OFFSET_G_BASE_IDX 2 4268 #define mmCM0_CM_BLNDGAM_RAMA_OFFSET_R 0x0d9c 4269 #define mmCM0_CM_BLNDGAM_RAMA_OFFSET_R_BASE_IDX 2 4270 #define mmCM0_CM_BLNDGAM_RAMA_REGION_0_1 0x0d9d 4271 #define mmCM0_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX 2 4272 #define mmCM0_CM_BLNDGAM_RAMA_REGION_2_3 0x0d9e 4273 #define mmCM0_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX 2 4274 #define mmCM0_CM_BLNDGAM_RAMA_REGION_4_5 0x0d9f 4275 #define mmCM0_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX 2 4276 #define mmCM0_CM_BLNDGAM_RAMA_REGION_6_7 0x0da0 4277 #define mmCM0_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX 2 4278 #define mmCM0_CM_BLNDGAM_RAMA_REGION_8_9 0x0da1 4279 #define mmCM0_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX 2 4280 #define mmCM0_CM_BLNDGAM_RAMA_REGION_10_11 0x0da2 4281 #define mmCM0_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX 2 4282 #define mmCM0_CM_BLNDGAM_RAMA_REGION_12_13 0x0da3 4283 #define mmCM0_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX 2 4284 #define mmCM0_CM_BLNDGAM_RAMA_REGION_14_15 0x0da4 4285 #define mmCM0_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX 2 4286 #define mmCM0_CM_BLNDGAM_RAMA_REGION_16_17 0x0da5 4287 #define mmCM0_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX 2 4288 #define mmCM0_CM_BLNDGAM_RAMA_REGION_18_19 0x0da6 4289 #define mmCM0_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX 2 4290 #define mmCM0_CM_BLNDGAM_RAMA_REGION_20_21 0x0da7 4291 #define mmCM0_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX 2 4292 #define mmCM0_CM_BLNDGAM_RAMA_REGION_22_23 0x0da8 4293 #define mmCM0_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX 2 4294 #define mmCM0_CM_BLNDGAM_RAMA_REGION_24_25 0x0da9 4295 #define mmCM0_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX 2 4296 #define mmCM0_CM_BLNDGAM_RAMA_REGION_26_27 0x0daa 4297 #define mmCM0_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX 2 4298 #define mmCM0_CM_BLNDGAM_RAMA_REGION_28_29 0x0dab 4299 #define mmCM0_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX 2 4300 #define mmCM0_CM_BLNDGAM_RAMA_REGION_30_31 0x0dac 4301 #define mmCM0_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX 2 4302 #define mmCM0_CM_BLNDGAM_RAMA_REGION_32_33 0x0dad 4303 #define mmCM0_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX 2 4304 #define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_B 0x0dae 4305 #define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX 2 4306 #define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_G 0x0daf 4307 #define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX 2 4308 #define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_R 0x0db0 4309 #define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX 2 4310 #define mmCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B 0x0db1 4311 #define mmCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 4312 #define mmCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G 0x0db2 4313 #define mmCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 4314 #define mmCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R 0x0db3 4315 #define mmCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 4316 #define mmCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_B 0x0db4 4317 #define mmCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 2 4318 #define mmCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_G 0x0db5 4319 #define mmCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 2 4320 #define mmCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_R 0x0db6 4321 #define mmCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 2 4322 #define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_B 0x0db7 4323 #define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX 2 4324 #define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_B 0x0db8 4325 #define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX 2 4326 #define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_G 0x0db9 4327 #define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX 2 4328 #define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_G 0x0dba 4329 #define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX 2 4330 #define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_R 0x0dbb 4331 #define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX 2 4332 #define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_R 0x0dbc 4333 #define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX 2 4334 #define mmCM0_CM_BLNDGAM_RAMB_OFFSET_B 0x0dbd 4335 #define mmCM0_CM_BLNDGAM_RAMB_OFFSET_B_BASE_IDX 2 4336 #define mmCM0_CM_BLNDGAM_RAMB_OFFSET_G 0x0dbe 4337 #define mmCM0_CM_BLNDGAM_RAMB_OFFSET_G_BASE_IDX 2 4338 #define mmCM0_CM_BLNDGAM_RAMB_OFFSET_R 0x0dbf 4339 #define mmCM0_CM_BLNDGAM_RAMB_OFFSET_R_BASE_IDX 2 4340 #define mmCM0_CM_BLNDGAM_RAMB_REGION_0_1 0x0dc0 4341 #define mmCM0_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX 2 4342 #define mmCM0_CM_BLNDGAM_RAMB_REGION_2_3 0x0dc1 4343 #define mmCM0_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX 2 4344 #define mmCM0_CM_BLNDGAM_RAMB_REGION_4_5 0x0dc2 4345 #define mmCM0_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX 2 4346 #define mmCM0_CM_BLNDGAM_RAMB_REGION_6_7 0x0dc3 4347 #define mmCM0_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX 2 4348 #define mmCM0_CM_BLNDGAM_RAMB_REGION_8_9 0x0dc4 4349 #define mmCM0_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX 2 4350 #define mmCM0_CM_BLNDGAM_RAMB_REGION_10_11 0x0dc5 4351 #define mmCM0_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX 2 4352 #define mmCM0_CM_BLNDGAM_RAMB_REGION_12_13 0x0dc6 4353 #define mmCM0_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX 2 4354 #define mmCM0_CM_BLNDGAM_RAMB_REGION_14_15 0x0dc7 4355 #define mmCM0_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX 2 4356 #define mmCM0_CM_BLNDGAM_RAMB_REGION_16_17 0x0dc8 4357 #define mmCM0_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX 2 4358 #define mmCM0_CM_BLNDGAM_RAMB_REGION_18_19 0x0dc9 4359 #define mmCM0_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX 2 4360 #define mmCM0_CM_BLNDGAM_RAMB_REGION_20_21 0x0dca 4361 #define mmCM0_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX 2 4362 #define mmCM0_CM_BLNDGAM_RAMB_REGION_22_23 0x0dcb 4363 #define mmCM0_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX 2 4364 #define mmCM0_CM_BLNDGAM_RAMB_REGION_24_25 0x0dcc 4365 #define mmCM0_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX 2 4366 #define mmCM0_CM_BLNDGAM_RAMB_REGION_26_27 0x0dcd 4367 #define mmCM0_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX 2 4368 #define mmCM0_CM_BLNDGAM_RAMB_REGION_28_29 0x0dce 4369 #define mmCM0_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX 2 4370 #define mmCM0_CM_BLNDGAM_RAMB_REGION_30_31 0x0dcf 4371 #define mmCM0_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX 2 4372 #define mmCM0_CM_BLNDGAM_RAMB_REGION_32_33 0x0dd0 4373 #define mmCM0_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX 2 4374 #define mmCM0_CM_HDR_MULT_COEF 0x0dd1 4375 #define mmCM0_CM_HDR_MULT_COEF_BASE_IDX 2 4376 #define mmCM0_CM_MEM_PWR_CTRL 0x0dd2 4377 #define mmCM0_CM_MEM_PWR_CTRL_BASE_IDX 2 4378 #define mmCM0_CM_MEM_PWR_STATUS 0x0dd3 4379 #define mmCM0_CM_MEM_PWR_STATUS_BASE_IDX 2 4380 #define mmCM0_CM_DEALPHA 0x0dd5 4381 #define mmCM0_CM_DEALPHA_BASE_IDX 2 4382 #define mmCM0_CM_COEF_FORMAT 0x0dd6 4383 #define mmCM0_CM_COEF_FORMAT_BASE_IDX 2 4384 #define mmCM0_CM_SHAPER_CONTROL 0x0dd7 4385 #define mmCM0_CM_SHAPER_CONTROL_BASE_IDX 2 4386 #define mmCM0_CM_SHAPER_OFFSET_R 0x0dd8 4387 #define mmCM0_CM_SHAPER_OFFSET_R_BASE_IDX 2 4388 #define mmCM0_CM_SHAPER_OFFSET_G 0x0dd9 4389 #define mmCM0_CM_SHAPER_OFFSET_G_BASE_IDX 2 4390 #define mmCM0_CM_SHAPER_OFFSET_B 0x0dda 4391 #define mmCM0_CM_SHAPER_OFFSET_B_BASE_IDX 2 4392 #define mmCM0_CM_SHAPER_SCALE_R 0x0ddb 4393 #define mmCM0_CM_SHAPER_SCALE_R_BASE_IDX 2 4394 #define mmCM0_CM_SHAPER_SCALE_G_B 0x0ddc 4395 #define mmCM0_CM_SHAPER_SCALE_G_B_BASE_IDX 2 4396 #define mmCM0_CM_SHAPER_LUT_INDEX 0x0ddd 4397 #define mmCM0_CM_SHAPER_LUT_INDEX_BASE_IDX 2 4398 #define mmCM0_CM_SHAPER_LUT_DATA 0x0dde 4399 #define mmCM0_CM_SHAPER_LUT_DATA_BASE_IDX 2 4400 #define mmCM0_CM_SHAPER_LUT_WRITE_EN_MASK 0x0ddf 4401 #define mmCM0_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 2 4402 #define mmCM0_CM_SHAPER_RAMA_START_CNTL_B 0x0de0 4403 #define mmCM0_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 2 4404 #define mmCM0_CM_SHAPER_RAMA_START_CNTL_G 0x0de1 4405 #define mmCM0_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 2 4406 #define mmCM0_CM_SHAPER_RAMA_START_CNTL_R 0x0de2 4407 #define mmCM0_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 2 4408 #define mmCM0_CM_SHAPER_RAMA_END_CNTL_B 0x0de3 4409 #define mmCM0_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 2 4410 #define mmCM0_CM_SHAPER_RAMA_END_CNTL_G 0x0de4 4411 #define mmCM0_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 2 4412 #define mmCM0_CM_SHAPER_RAMA_END_CNTL_R 0x0de5 4413 #define mmCM0_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 2 4414 #define mmCM0_CM_SHAPER_RAMA_REGION_0_1 0x0de6 4415 #define mmCM0_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX 2 4416 #define mmCM0_CM_SHAPER_RAMA_REGION_2_3 0x0de7 4417 #define mmCM0_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX 2 4418 #define mmCM0_CM_SHAPER_RAMA_REGION_4_5 0x0de8 4419 #define mmCM0_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX 2 4420 #define mmCM0_CM_SHAPER_RAMA_REGION_6_7 0x0de9 4421 #define mmCM0_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX 2 4422 #define mmCM0_CM_SHAPER_RAMA_REGION_8_9 0x0dea 4423 #define mmCM0_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX 2 4424 #define mmCM0_CM_SHAPER_RAMA_REGION_10_11 0x0deb 4425 #define mmCM0_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX 2 4426 #define mmCM0_CM_SHAPER_RAMA_REGION_12_13 0x0dec 4427 #define mmCM0_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX 2 4428 #define mmCM0_CM_SHAPER_RAMA_REGION_14_15 0x0ded 4429 #define mmCM0_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX 2 4430 #define mmCM0_CM_SHAPER_RAMA_REGION_16_17 0x0dee 4431 #define mmCM0_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX 2 4432 #define mmCM0_CM_SHAPER_RAMA_REGION_18_19 0x0def 4433 #define mmCM0_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX 2 4434 #define mmCM0_CM_SHAPER_RAMA_REGION_20_21 0x0df0 4435 #define mmCM0_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX 2 4436 #define mmCM0_CM_SHAPER_RAMA_REGION_22_23 0x0df1 4437 #define mmCM0_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX 2 4438 #define mmCM0_CM_SHAPER_RAMA_REGION_24_25 0x0df2 4439 #define mmCM0_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX 2 4440 #define mmCM0_CM_SHAPER_RAMA_REGION_26_27 0x0df3 4441 #define mmCM0_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX 2 4442 #define mmCM0_CM_SHAPER_RAMA_REGION_28_29 0x0df4 4443 #define mmCM0_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX 2 4444 #define mmCM0_CM_SHAPER_RAMA_REGION_30_31 0x0df5 4445 #define mmCM0_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX 2 4446 #define mmCM0_CM_SHAPER_RAMA_REGION_32_33 0x0df6 4447 #define mmCM0_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX 2 4448 #define mmCM0_CM_SHAPER_RAMB_START_CNTL_B 0x0df7 4449 #define mmCM0_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 2 4450 #define mmCM0_CM_SHAPER_RAMB_START_CNTL_G 0x0df8 4451 #define mmCM0_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 2 4452 #define mmCM0_CM_SHAPER_RAMB_START_CNTL_R 0x0df9 4453 #define mmCM0_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 2 4454 #define mmCM0_CM_SHAPER_RAMB_END_CNTL_B 0x0dfa 4455 #define mmCM0_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 2 4456 #define mmCM0_CM_SHAPER_RAMB_END_CNTL_G 0x0dfb 4457 #define mmCM0_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 2 4458 #define mmCM0_CM_SHAPER_RAMB_END_CNTL_R 0x0dfc 4459 #define mmCM0_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 2 4460 #define mmCM0_CM_SHAPER_RAMB_REGION_0_1 0x0dfd 4461 #define mmCM0_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX 2 4462 #define mmCM0_CM_SHAPER_RAMB_REGION_2_3 0x0dfe 4463 #define mmCM0_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX 2 4464 #define mmCM0_CM_SHAPER_RAMB_REGION_4_5 0x0dff 4465 #define mmCM0_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX 2 4466 #define mmCM0_CM_SHAPER_RAMB_REGION_6_7 0x0e00 4467 #define mmCM0_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX 2 4468 #define mmCM0_CM_SHAPER_RAMB_REGION_8_9 0x0e01 4469 #define mmCM0_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX 2 4470 #define mmCM0_CM_SHAPER_RAMB_REGION_10_11 0x0e02 4471 #define mmCM0_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX 2 4472 #define mmCM0_CM_SHAPER_RAMB_REGION_12_13 0x0e03 4473 #define mmCM0_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX 2 4474 #define mmCM0_CM_SHAPER_RAMB_REGION_14_15 0x0e04 4475 #define mmCM0_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX 2 4476 #define mmCM0_CM_SHAPER_RAMB_REGION_16_17 0x0e05 4477 #define mmCM0_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX 2 4478 #define mmCM0_CM_SHAPER_RAMB_REGION_18_19 0x0e06 4479 #define mmCM0_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX 2 4480 #define mmCM0_CM_SHAPER_RAMB_REGION_20_21 0x0e07 4481 #define mmCM0_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX 2 4482 #define mmCM0_CM_SHAPER_RAMB_REGION_22_23 0x0e08 4483 #define mmCM0_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX 2 4484 #define mmCM0_CM_SHAPER_RAMB_REGION_24_25 0x0e09 4485 #define mmCM0_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX 2 4486 #define mmCM0_CM_SHAPER_RAMB_REGION_26_27 0x0e0a 4487 #define mmCM0_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX 2 4488 #define mmCM0_CM_SHAPER_RAMB_REGION_28_29 0x0e0b 4489 #define mmCM0_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX 2 4490 #define mmCM0_CM_SHAPER_RAMB_REGION_30_31 0x0e0c 4491 #define mmCM0_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX 2 4492 #define mmCM0_CM_SHAPER_RAMB_REGION_32_33 0x0e0d 4493 #define mmCM0_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX 2 4494 #define mmCM0_CM_MEM_PWR_CTRL2 0x0e0e 4495 #define mmCM0_CM_MEM_PWR_CTRL2_BASE_IDX 2 4496 #define mmCM0_CM_MEM_PWR_STATUS2 0x0e0f 4497 #define mmCM0_CM_MEM_PWR_STATUS2_BASE_IDX 2 4498 #define mmCM0_CM_3DLUT_MODE 0x0e10 4499 #define mmCM0_CM_3DLUT_MODE_BASE_IDX 2 4500 #define mmCM0_CM_3DLUT_INDEX 0x0e11 4501 #define mmCM0_CM_3DLUT_INDEX_BASE_IDX 2 4502 #define mmCM0_CM_3DLUT_DATA 0x0e12 4503 #define mmCM0_CM_3DLUT_DATA_BASE_IDX 2 4504 #define mmCM0_CM_3DLUT_DATA_30BIT 0x0e13 4505 #define mmCM0_CM_3DLUT_DATA_30BIT_BASE_IDX 2 4506 #define mmCM0_CM_3DLUT_READ_WRITE_CONTROL 0x0e14 4507 #define mmCM0_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 2 4508 #define mmCM0_CM_3DLUT_OUT_NORM_FACTOR 0x0e15 4509 #define mmCM0_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 2 4510 #define mmCM0_CM_3DLUT_OUT_OFFSET_R 0x0e16 4511 #define mmCM0_CM_3DLUT_OUT_OFFSET_R_BASE_IDX 2 4512 #define mmCM0_CM_3DLUT_OUT_OFFSET_G 0x0e17 4513 #define mmCM0_CM_3DLUT_OUT_OFFSET_G_BASE_IDX 2 4514 #define mmCM0_CM_3DLUT_OUT_OFFSET_B 0x0e18 4515 #define mmCM0_CM_3DLUT_OUT_OFFSET_B_BASE_IDX 2 4516 4517 4518 // addressBlock: dce_dc_dpp0_dispdec_dpp_dcperfmon_dc_perfmon_dispdec 4519 // base address: 0x3890 4520 #define mmDC_PERFMON12_PERFCOUNTER_CNTL 0x0e24 4521 #define mmDC_PERFMON12_PERFCOUNTER_CNTL_BASE_IDX 2 4522 #define mmDC_PERFMON12_PERFCOUNTER_CNTL2 0x0e25 4523 #define mmDC_PERFMON12_PERFCOUNTER_CNTL2_BASE_IDX 2 4524 #define mmDC_PERFMON12_PERFCOUNTER_STATE 0x0e26 4525 #define mmDC_PERFMON12_PERFCOUNTER_STATE_BASE_IDX 2 4526 #define mmDC_PERFMON12_PERFMON_CNTL 0x0e27 4527 #define mmDC_PERFMON12_PERFMON_CNTL_BASE_IDX 2 4528 #define mmDC_PERFMON12_PERFMON_CNTL2 0x0e28 4529 #define mmDC_PERFMON12_PERFMON_CNTL2_BASE_IDX 2 4530 #define mmDC_PERFMON12_PERFMON_CVALUE_INT_MISC 0x0e29 4531 #define mmDC_PERFMON12_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 4532 #define mmDC_PERFMON12_PERFMON_CVALUE_LOW 0x0e2a 4533 #define mmDC_PERFMON12_PERFMON_CVALUE_LOW_BASE_IDX 2 4534 #define mmDC_PERFMON12_PERFMON_HI 0x0e2b 4535 #define mmDC_PERFMON12_PERFMON_HI_BASE_IDX 2 4536 #define mmDC_PERFMON12_PERFMON_LOW 0x0e2c 4537 #define mmDC_PERFMON12_PERFMON_LOW_BASE_IDX 2 4538 4539 4540 // addressBlock: dce_dc_dpp1_dispdec_dpp_top_dispdec 4541 // base address: 0x5ac 4542 #define mmDPP_TOP1_DPP_CONTROL 0x0e30 4543 #define mmDPP_TOP1_DPP_CONTROL_BASE_IDX 2 4544 #define mmDPP_TOP1_DPP_SOFT_RESET 0x0e31 4545 #define mmDPP_TOP1_DPP_SOFT_RESET_BASE_IDX 2 4546 #define mmDPP_TOP1_DPP_CRC_VAL_R_G 0x0e32 4547 #define mmDPP_TOP1_DPP_CRC_VAL_R_G_BASE_IDX 2 4548 #define mmDPP_TOP1_DPP_CRC_VAL_B_A 0x0e33 4549 #define mmDPP_TOP1_DPP_CRC_VAL_B_A_BASE_IDX 2 4550 #define mmDPP_TOP1_DPP_CRC_CTRL 0x0e34 4551 #define mmDPP_TOP1_DPP_CRC_CTRL_BASE_IDX 2 4552 #define mmDPP_TOP1_HOST_READ_CONTROL 0x0e35 4553 #define mmDPP_TOP1_HOST_READ_CONTROL_BASE_IDX 2 4554 4555 4556 // addressBlock: dce_dc_dpp1_dispdec_cnvc_cfg_dispdec 4557 // base address: 0x5ac 4558 #define mmCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT 0x0e3a 4559 #define mmCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2 4560 #define mmCNVC_CFG1_FORMAT_CONTROL 0x0e3b 4561 #define mmCNVC_CFG1_FORMAT_CONTROL_BASE_IDX 2 4562 #define mmCNVC_CFG1_FCNV_FP_BIAS_R 0x0e3c 4563 #define mmCNVC_CFG1_FCNV_FP_BIAS_R_BASE_IDX 2 4564 #define mmCNVC_CFG1_FCNV_FP_BIAS_G 0x0e3d 4565 #define mmCNVC_CFG1_FCNV_FP_BIAS_G_BASE_IDX 2 4566 #define mmCNVC_CFG1_FCNV_FP_BIAS_B 0x0e3e 4567 #define mmCNVC_CFG1_FCNV_FP_BIAS_B_BASE_IDX 2 4568 #define mmCNVC_CFG1_FCNV_FP_SCALE_R 0x0e3f 4569 #define mmCNVC_CFG1_FCNV_FP_SCALE_R_BASE_IDX 2 4570 #define mmCNVC_CFG1_FCNV_FP_SCALE_G 0x0e40 4571 #define mmCNVC_CFG1_FCNV_FP_SCALE_G_BASE_IDX 2 4572 #define mmCNVC_CFG1_FCNV_FP_SCALE_B 0x0e41 4573 #define mmCNVC_CFG1_FCNV_FP_SCALE_B_BASE_IDX 2 4574 #define mmCNVC_CFG1_COLOR_KEYER_CONTROL 0x0e42 4575 #define mmCNVC_CFG1_COLOR_KEYER_CONTROL_BASE_IDX 2 4576 #define mmCNVC_CFG1_COLOR_KEYER_ALPHA 0x0e43 4577 #define mmCNVC_CFG1_COLOR_KEYER_ALPHA_BASE_IDX 2 4578 #define mmCNVC_CFG1_COLOR_KEYER_RED 0x0e44 4579 #define mmCNVC_CFG1_COLOR_KEYER_RED_BASE_IDX 2 4580 #define mmCNVC_CFG1_COLOR_KEYER_GREEN 0x0e45 4581 #define mmCNVC_CFG1_COLOR_KEYER_GREEN_BASE_IDX 2 4582 #define mmCNVC_CFG1_COLOR_KEYER_BLUE 0x0e46 4583 #define mmCNVC_CFG1_COLOR_KEYER_BLUE_BASE_IDX 2 4584 #define mmCNVC_CFG1_ALPHA_2BIT_LUT 0x0e48 4585 #define mmCNVC_CFG1_ALPHA_2BIT_LUT_BASE_IDX 2 4586 #define mmCNVC_CFG1_PRE_DEALPHA 0x0e49 4587 #define mmCNVC_CFG1_PRE_DEALPHA_BASE_IDX 2 4588 #define mmCNVC_CFG1_PRE_CSC_MODE 0x0e4a 4589 #define mmCNVC_CFG1_PRE_CSC_MODE_BASE_IDX 2 4590 #define mmCNVC_CFG1_PRE_CSC_C11_C12 0x0e4b 4591 #define mmCNVC_CFG1_PRE_CSC_C11_C12_BASE_IDX 2 4592 #define mmCNVC_CFG1_PRE_CSC_C13_C14 0x0e4c 4593 #define mmCNVC_CFG1_PRE_CSC_C13_C14_BASE_IDX 2 4594 #define mmCNVC_CFG1_PRE_CSC_C21_C22 0x0e4d 4595 #define mmCNVC_CFG1_PRE_CSC_C21_C22_BASE_IDX 2 4596 #define mmCNVC_CFG1_PRE_CSC_C23_C24 0x0e4e 4597 #define mmCNVC_CFG1_PRE_CSC_C23_C24_BASE_IDX 2 4598 #define mmCNVC_CFG1_PRE_CSC_C31_C32 0x0e4f 4599 #define mmCNVC_CFG1_PRE_CSC_C31_C32_BASE_IDX 2 4600 #define mmCNVC_CFG1_PRE_CSC_C33_C34 0x0e50 4601 #define mmCNVC_CFG1_PRE_CSC_C33_C34_BASE_IDX 2 4602 #define mmCNVC_CFG1_PRE_CSC_B_C11_C12 0x0e51 4603 #define mmCNVC_CFG1_PRE_CSC_B_C11_C12_BASE_IDX 2 4604 #define mmCNVC_CFG1_PRE_CSC_B_C13_C14 0x0e52 4605 #define mmCNVC_CFG1_PRE_CSC_B_C13_C14_BASE_IDX 2 4606 #define mmCNVC_CFG1_PRE_CSC_B_C21_C22 0x0e53 4607 #define mmCNVC_CFG1_PRE_CSC_B_C21_C22_BASE_IDX 2 4608 #define mmCNVC_CFG1_PRE_CSC_B_C23_C24 0x0e54 4609 #define mmCNVC_CFG1_PRE_CSC_B_C23_C24_BASE_IDX 2 4610 #define mmCNVC_CFG1_PRE_CSC_B_C31_C32 0x0e55 4611 #define mmCNVC_CFG1_PRE_CSC_B_C31_C32_BASE_IDX 2 4612 #define mmCNVC_CFG1_PRE_CSC_B_C33_C34 0x0e56 4613 #define mmCNVC_CFG1_PRE_CSC_B_C33_C34_BASE_IDX 2 4614 #define mmCNVC_CFG1_CNVC_COEF_FORMAT 0x0e57 4615 #define mmCNVC_CFG1_CNVC_COEF_FORMAT_BASE_IDX 2 4616 #define mmCNVC_CFG1_PRE_DEGAM 0x0e58 4617 #define mmCNVC_CFG1_PRE_DEGAM_BASE_IDX 2 4618 #define mmCNVC_CFG1_PRE_REALPHA 0x0e59 4619 #define mmCNVC_CFG1_PRE_REALPHA_BASE_IDX 2 4620 4621 4622 // addressBlock: dce_dc_dpp1_dispdec_cnvc_cur_dispdec 4623 // base address: 0x5ac 4624 #define mmCNVC_CUR1_CURSOR0_CONTROL 0x0e5c 4625 #define mmCNVC_CUR1_CURSOR0_CONTROL_BASE_IDX 2 4626 #define mmCNVC_CUR1_CURSOR0_COLOR0 0x0e5d 4627 #define mmCNVC_CUR1_CURSOR0_COLOR0_BASE_IDX 2 4628 #define mmCNVC_CUR1_CURSOR0_COLOR1 0x0e5e 4629 #define mmCNVC_CUR1_CURSOR0_COLOR1_BASE_IDX 2 4630 #define mmCNVC_CUR1_CURSOR0_FP_SCALE_BIAS 0x0e5f 4631 #define mmCNVC_CUR1_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2 4632 4633 4634 // addressBlock: dce_dc_dpp1_dispdec_dscl_dispdec 4635 // base address: 0x5ac 4636 #define mmDSCL1_SCL_COEF_RAM_TAP_SELECT 0x0e64 4637 #define mmDSCL1_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2 4638 #define mmDSCL1_SCL_COEF_RAM_TAP_DATA 0x0e65 4639 #define mmDSCL1_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2 4640 #define mmDSCL1_SCL_MODE 0x0e66 4641 #define mmDSCL1_SCL_MODE_BASE_IDX 2 4642 #define mmDSCL1_SCL_TAP_CONTROL 0x0e67 4643 #define mmDSCL1_SCL_TAP_CONTROL_BASE_IDX 2 4644 #define mmDSCL1_DSCL_CONTROL 0x0e68 4645 #define mmDSCL1_DSCL_CONTROL_BASE_IDX 2 4646 #define mmDSCL1_DSCL_2TAP_CONTROL 0x0e69 4647 #define mmDSCL1_DSCL_2TAP_CONTROL_BASE_IDX 2 4648 #define mmDSCL1_SCL_MANUAL_REPLICATE_CONTROL 0x0e6a 4649 #define mmDSCL1_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 4650 #define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO 0x0e6b 4651 #define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 4652 #define mmDSCL1_SCL_HORZ_FILTER_INIT 0x0e6c 4653 #define mmDSCL1_SCL_HORZ_FILTER_INIT_BASE_IDX 2 4654 #define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C 0x0e6d 4655 #define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2 4656 #define mmDSCL1_SCL_HORZ_FILTER_INIT_C 0x0e6e 4657 #define mmDSCL1_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2 4658 #define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO 0x0e6f 4659 #define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 4660 #define mmDSCL1_SCL_VERT_FILTER_INIT 0x0e70 4661 #define mmDSCL1_SCL_VERT_FILTER_INIT_BASE_IDX 2 4662 #define mmDSCL1_SCL_VERT_FILTER_INIT_BOT 0x0e71 4663 #define mmDSCL1_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2 4664 #define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C 0x0e72 4665 #define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2 4666 #define mmDSCL1_SCL_VERT_FILTER_INIT_C 0x0e73 4667 #define mmDSCL1_SCL_VERT_FILTER_INIT_C_BASE_IDX 2 4668 #define mmDSCL1_SCL_VERT_FILTER_INIT_BOT_C 0x0e74 4669 #define mmDSCL1_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2 4670 #define mmDSCL1_SCL_BLACK_COLOR 0x0e75 4671 #define mmDSCL1_SCL_BLACK_COLOR_BASE_IDX 2 4672 #define mmDSCL1_DSCL_UPDATE 0x0e76 4673 #define mmDSCL1_DSCL_UPDATE_BASE_IDX 2 4674 #define mmDSCL1_DSCL_AUTOCAL 0x0e77 4675 #define mmDSCL1_DSCL_AUTOCAL_BASE_IDX 2 4676 #define mmDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x0e78 4677 #define mmDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 4678 #define mmDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x0e79 4679 #define mmDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 4680 #define mmDSCL1_OTG_H_BLANK 0x0e7a 4681 #define mmDSCL1_OTG_H_BLANK_BASE_IDX 2 4682 #define mmDSCL1_OTG_V_BLANK 0x0e7b 4683 #define mmDSCL1_OTG_V_BLANK_BASE_IDX 2 4684 #define mmDSCL1_RECOUT_START 0x0e7c 4685 #define mmDSCL1_RECOUT_START_BASE_IDX 2 4686 #define mmDSCL1_RECOUT_SIZE 0x0e7d 4687 #define mmDSCL1_RECOUT_SIZE_BASE_IDX 2 4688 #define mmDSCL1_MPC_SIZE 0x0e7e 4689 #define mmDSCL1_MPC_SIZE_BASE_IDX 2 4690 #define mmDSCL1_LB_DATA_FORMAT 0x0e7f 4691 #define mmDSCL1_LB_DATA_FORMAT_BASE_IDX 2 4692 #define mmDSCL1_LB_MEMORY_CTRL 0x0e80 4693 #define mmDSCL1_LB_MEMORY_CTRL_BASE_IDX 2 4694 #define mmDSCL1_LB_V_COUNTER 0x0e81 4695 #define mmDSCL1_LB_V_COUNTER_BASE_IDX 2 4696 #define mmDSCL1_DSCL_MEM_PWR_CTRL 0x0e82 4697 #define mmDSCL1_DSCL_MEM_PWR_CTRL_BASE_IDX 2 4698 #define mmDSCL1_DSCL_MEM_PWR_STATUS 0x0e83 4699 #define mmDSCL1_DSCL_MEM_PWR_STATUS_BASE_IDX 2 4700 #define mmDSCL1_OBUF_CONTROL 0x0e84 4701 #define mmDSCL1_OBUF_CONTROL_BASE_IDX 2 4702 #define mmDSCL1_OBUF_MEM_PWR_CTRL 0x0e85 4703 #define mmDSCL1_OBUF_MEM_PWR_CTRL_BASE_IDX 2 4704 4705 4706 // addressBlock: dce_dc_dpp1_dispdec_cm_dispdec 4707 // base address: 0x5ac 4708 #define mmCM1_CM_CONTROL 0x0e8b 4709 #define mmCM1_CM_CONTROL_BASE_IDX 2 4710 #define mmCM1_CM_POST_CSC_CONTROL 0x0e8c 4711 #define mmCM1_CM_POST_CSC_CONTROL_BASE_IDX 2 4712 #define mmCM1_CM_POST_CSC_C11_C12 0x0e8d 4713 #define mmCM1_CM_POST_CSC_C11_C12_BASE_IDX 2 4714 #define mmCM1_CM_POST_CSC_C13_C14 0x0e8e 4715 #define mmCM1_CM_POST_CSC_C13_C14_BASE_IDX 2 4716 #define mmCM1_CM_POST_CSC_C21_C22 0x0e8f 4717 #define mmCM1_CM_POST_CSC_C21_C22_BASE_IDX 2 4718 #define mmCM1_CM_POST_CSC_C23_C24 0x0e90 4719 #define mmCM1_CM_POST_CSC_C23_C24_BASE_IDX 2 4720 #define mmCM1_CM_POST_CSC_C31_C32 0x0e91 4721 #define mmCM1_CM_POST_CSC_C31_C32_BASE_IDX 2 4722 #define mmCM1_CM_POST_CSC_C33_C34 0x0e92 4723 #define mmCM1_CM_POST_CSC_C33_C34_BASE_IDX 2 4724 #define mmCM1_CM_POST_CSC_B_C11_C12 0x0e93 4725 #define mmCM1_CM_POST_CSC_B_C11_C12_BASE_IDX 2 4726 #define mmCM1_CM_POST_CSC_B_C13_C14 0x0e94 4727 #define mmCM1_CM_POST_CSC_B_C13_C14_BASE_IDX 2 4728 #define mmCM1_CM_POST_CSC_B_C21_C22 0x0e95 4729 #define mmCM1_CM_POST_CSC_B_C21_C22_BASE_IDX 2 4730 #define mmCM1_CM_POST_CSC_B_C23_C24 0x0e96 4731 #define mmCM1_CM_POST_CSC_B_C23_C24_BASE_IDX 2 4732 #define mmCM1_CM_POST_CSC_B_C31_C32 0x0e97 4733 #define mmCM1_CM_POST_CSC_B_C31_C32_BASE_IDX 2 4734 #define mmCM1_CM_POST_CSC_B_C33_C34 0x0e98 4735 #define mmCM1_CM_POST_CSC_B_C33_C34_BASE_IDX 2 4736 #define mmCM1_CM_GAMUT_REMAP_CONTROL 0x0e99 4737 #define mmCM1_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2 4738 #define mmCM1_CM_GAMUT_REMAP_C11_C12 0x0e9a 4739 #define mmCM1_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2 4740 #define mmCM1_CM_GAMUT_REMAP_C13_C14 0x0e9b 4741 #define mmCM1_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2 4742 #define mmCM1_CM_GAMUT_REMAP_C21_C22 0x0e9c 4743 #define mmCM1_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2 4744 #define mmCM1_CM_GAMUT_REMAP_C23_C24 0x0e9d 4745 #define mmCM1_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2 4746 #define mmCM1_CM_GAMUT_REMAP_C31_C32 0x0e9e 4747 #define mmCM1_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2 4748 #define mmCM1_CM_GAMUT_REMAP_C33_C34 0x0e9f 4749 #define mmCM1_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2 4750 #define mmCM1_CM_GAMUT_REMAP_B_C11_C12 0x0ea0 4751 #define mmCM1_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX 2 4752 #define mmCM1_CM_GAMUT_REMAP_B_C13_C14 0x0ea1 4753 #define mmCM1_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX 2 4754 #define mmCM1_CM_GAMUT_REMAP_B_C21_C22 0x0ea2 4755 #define mmCM1_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX 2 4756 #define mmCM1_CM_GAMUT_REMAP_B_C23_C24 0x0ea3 4757 #define mmCM1_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX 2 4758 #define mmCM1_CM_GAMUT_REMAP_B_C31_C32 0x0ea4 4759 #define mmCM1_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX 2 4760 #define mmCM1_CM_GAMUT_REMAP_B_C33_C34 0x0ea5 4761 #define mmCM1_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX 2 4762 #define mmCM1_CM_BIAS_CR_R 0x0ea6 4763 #define mmCM1_CM_BIAS_CR_R_BASE_IDX 2 4764 #define mmCM1_CM_BIAS_Y_G_CB_B 0x0ea7 4765 #define mmCM1_CM_BIAS_Y_G_CB_B_BASE_IDX 2 4766 #define mmCM1_CM_GAMCOR_CONTROL 0x0ea8 4767 #define mmCM1_CM_GAMCOR_CONTROL_BASE_IDX 2 4768 #define mmCM1_CM_GAMCOR_LUT_INDEX 0x0ea9 4769 #define mmCM1_CM_GAMCOR_LUT_INDEX_BASE_IDX 2 4770 #define mmCM1_CM_GAMCOR_LUT_DATA 0x0eaa 4771 #define mmCM1_CM_GAMCOR_LUT_DATA_BASE_IDX 2 4772 #define mmCM1_CM_GAMCOR_LUT_CONTROL 0x0eab 4773 #define mmCM1_CM_GAMCOR_LUT_CONTROL_BASE_IDX 2 4774 #define mmCM1_CM_GAMCOR_RAMA_START_CNTL_B 0x0eac 4775 #define mmCM1_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX 2 4776 #define mmCM1_CM_GAMCOR_RAMA_START_CNTL_G 0x0ead 4777 #define mmCM1_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX 2 4778 #define mmCM1_CM_GAMCOR_RAMA_START_CNTL_R 0x0eae 4779 #define mmCM1_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX 2 4780 #define mmCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B 0x0eaf 4781 #define mmCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 4782 #define mmCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G 0x0eb0 4783 #define mmCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 4784 #define mmCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R 0x0eb1 4785 #define mmCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 4786 #define mmCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B 0x0eb2 4787 #define mmCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX 2 4788 #define mmCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G 0x0eb3 4789 #define mmCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX 2 4790 #define mmCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R 0x0eb4 4791 #define mmCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX 2 4792 #define mmCM1_CM_GAMCOR_RAMA_END_CNTL1_B 0x0eb5 4793 #define mmCM1_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX 2 4794 #define mmCM1_CM_GAMCOR_RAMA_END_CNTL2_B 0x0eb6 4795 #define mmCM1_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX 2 4796 #define mmCM1_CM_GAMCOR_RAMA_END_CNTL1_G 0x0eb7 4797 #define mmCM1_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX 2 4798 #define mmCM1_CM_GAMCOR_RAMA_END_CNTL2_G 0x0eb8 4799 #define mmCM1_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX 2 4800 #define mmCM1_CM_GAMCOR_RAMA_END_CNTL1_R 0x0eb9 4801 #define mmCM1_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX 2 4802 #define mmCM1_CM_GAMCOR_RAMA_END_CNTL2_R 0x0eba 4803 #define mmCM1_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX 2 4804 #define mmCM1_CM_GAMCOR_RAMA_OFFSET_B 0x0ebb 4805 #define mmCM1_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX 2 4806 #define mmCM1_CM_GAMCOR_RAMA_OFFSET_G 0x0ebc 4807 #define mmCM1_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX 2 4808 #define mmCM1_CM_GAMCOR_RAMA_OFFSET_R 0x0ebd 4809 #define mmCM1_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX 2 4810 #define mmCM1_CM_GAMCOR_RAMA_REGION_0_1 0x0ebe 4811 #define mmCM1_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX 2 4812 #define mmCM1_CM_GAMCOR_RAMA_REGION_2_3 0x0ebf 4813 #define mmCM1_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX 2 4814 #define mmCM1_CM_GAMCOR_RAMA_REGION_4_5 0x0ec0 4815 #define mmCM1_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX 2 4816 #define mmCM1_CM_GAMCOR_RAMA_REGION_6_7 0x0ec1 4817 #define mmCM1_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX 2 4818 #define mmCM1_CM_GAMCOR_RAMA_REGION_8_9 0x0ec2 4819 #define mmCM1_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX 2 4820 #define mmCM1_CM_GAMCOR_RAMA_REGION_10_11 0x0ec3 4821 #define mmCM1_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX 2 4822 #define mmCM1_CM_GAMCOR_RAMA_REGION_12_13 0x0ec4 4823 #define mmCM1_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX 2 4824 #define mmCM1_CM_GAMCOR_RAMA_REGION_14_15 0x0ec5 4825 #define mmCM1_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX 2 4826 #define mmCM1_CM_GAMCOR_RAMA_REGION_16_17 0x0ec6 4827 #define mmCM1_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX 2 4828 #define mmCM1_CM_GAMCOR_RAMA_REGION_18_19 0x0ec7 4829 #define mmCM1_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX 2 4830 #define mmCM1_CM_GAMCOR_RAMA_REGION_20_21 0x0ec8 4831 #define mmCM1_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX 2 4832 #define mmCM1_CM_GAMCOR_RAMA_REGION_22_23 0x0ec9 4833 #define mmCM1_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX 2 4834 #define mmCM1_CM_GAMCOR_RAMA_REGION_24_25 0x0eca 4835 #define mmCM1_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX 2 4836 #define mmCM1_CM_GAMCOR_RAMA_REGION_26_27 0x0ecb 4837 #define mmCM1_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX 2 4838 #define mmCM1_CM_GAMCOR_RAMA_REGION_28_29 0x0ecc 4839 #define mmCM1_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX 2 4840 #define mmCM1_CM_GAMCOR_RAMA_REGION_30_31 0x0ecd 4841 #define mmCM1_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX 2 4842 #define mmCM1_CM_GAMCOR_RAMA_REGION_32_33 0x0ece 4843 #define mmCM1_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX 2 4844 #define mmCM1_CM_GAMCOR_RAMB_START_CNTL_B 0x0ecf 4845 #define mmCM1_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX 2 4846 #define mmCM1_CM_GAMCOR_RAMB_START_CNTL_G 0x0ed0 4847 #define mmCM1_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX 2 4848 #define mmCM1_CM_GAMCOR_RAMB_START_CNTL_R 0x0ed1 4849 #define mmCM1_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX 2 4850 #define mmCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B 0x0ed2 4851 #define mmCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 4852 #define mmCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G 0x0ed3 4853 #define mmCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 4854 #define mmCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R 0x0ed4 4855 #define mmCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 4856 #define mmCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B 0x0ed5 4857 #define mmCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX 2 4858 #define mmCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G 0x0ed6 4859 #define mmCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX 2 4860 #define mmCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R 0x0ed7 4861 #define mmCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX 2 4862 #define mmCM1_CM_GAMCOR_RAMB_END_CNTL1_B 0x0ed8 4863 #define mmCM1_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX 2 4864 #define mmCM1_CM_GAMCOR_RAMB_END_CNTL2_B 0x0ed9 4865 #define mmCM1_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX 2 4866 #define mmCM1_CM_GAMCOR_RAMB_END_CNTL1_G 0x0eda 4867 #define mmCM1_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX 2 4868 #define mmCM1_CM_GAMCOR_RAMB_END_CNTL2_G 0x0edb 4869 #define mmCM1_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX 2 4870 #define mmCM1_CM_GAMCOR_RAMB_END_CNTL1_R 0x0edc 4871 #define mmCM1_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX 2 4872 #define mmCM1_CM_GAMCOR_RAMB_END_CNTL2_R 0x0edd 4873 #define mmCM1_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX 2 4874 #define mmCM1_CM_GAMCOR_RAMB_OFFSET_B 0x0ede 4875 #define mmCM1_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX 2 4876 #define mmCM1_CM_GAMCOR_RAMB_OFFSET_G 0x0edf 4877 #define mmCM1_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX 2 4878 #define mmCM1_CM_GAMCOR_RAMB_OFFSET_R 0x0ee0 4879 #define mmCM1_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX 2 4880 #define mmCM1_CM_GAMCOR_RAMB_REGION_0_1 0x0ee1 4881 #define mmCM1_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX 2 4882 #define mmCM1_CM_GAMCOR_RAMB_REGION_2_3 0x0ee2 4883 #define mmCM1_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX 2 4884 #define mmCM1_CM_GAMCOR_RAMB_REGION_4_5 0x0ee3 4885 #define mmCM1_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX 2 4886 #define mmCM1_CM_GAMCOR_RAMB_REGION_6_7 0x0ee4 4887 #define mmCM1_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX 2 4888 #define mmCM1_CM_GAMCOR_RAMB_REGION_8_9 0x0ee5 4889 #define mmCM1_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX 2 4890 #define mmCM1_CM_GAMCOR_RAMB_REGION_10_11 0x0ee6 4891 #define mmCM1_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX 2 4892 #define mmCM1_CM_GAMCOR_RAMB_REGION_12_13 0x0ee7 4893 #define mmCM1_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX 2 4894 #define mmCM1_CM_GAMCOR_RAMB_REGION_14_15 0x0ee8 4895 #define mmCM1_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX 2 4896 #define mmCM1_CM_GAMCOR_RAMB_REGION_16_17 0x0ee9 4897 #define mmCM1_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX 2 4898 #define mmCM1_CM_GAMCOR_RAMB_REGION_18_19 0x0eea 4899 #define mmCM1_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX 2 4900 #define mmCM1_CM_GAMCOR_RAMB_REGION_20_21 0x0eeb 4901 #define mmCM1_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX 2 4902 #define mmCM1_CM_GAMCOR_RAMB_REGION_22_23 0x0eec 4903 #define mmCM1_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX 2 4904 #define mmCM1_CM_GAMCOR_RAMB_REGION_24_25 0x0eed 4905 #define mmCM1_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX 2 4906 #define mmCM1_CM_GAMCOR_RAMB_REGION_26_27 0x0eee 4907 #define mmCM1_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX 2 4908 #define mmCM1_CM_GAMCOR_RAMB_REGION_28_29 0x0eef 4909 #define mmCM1_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX 2 4910 #define mmCM1_CM_GAMCOR_RAMB_REGION_30_31 0x0ef0 4911 #define mmCM1_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX 2 4912 #define mmCM1_CM_GAMCOR_RAMB_REGION_32_33 0x0ef1 4913 #define mmCM1_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX 2 4914 #define mmCM1_CM_BLNDGAM_CONTROL 0x0ef2 4915 #define mmCM1_CM_BLNDGAM_CONTROL_BASE_IDX 2 4916 #define mmCM1_CM_BLNDGAM_LUT_INDEX 0x0ef3 4917 #define mmCM1_CM_BLNDGAM_LUT_INDEX_BASE_IDX 2 4918 #define mmCM1_CM_BLNDGAM_LUT_DATA 0x0ef4 4919 #define mmCM1_CM_BLNDGAM_LUT_DATA_BASE_IDX 2 4920 #define mmCM1_CM_BLNDGAM_LUT_CONTROL 0x0ef5 4921 #define mmCM1_CM_BLNDGAM_LUT_CONTROL_BASE_IDX 2 4922 #define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_B 0x0ef6 4923 #define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX 2 4924 #define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_G 0x0ef7 4925 #define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX 2 4926 #define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_R 0x0ef8 4927 #define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX 2 4928 #define mmCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B 0x0ef9 4929 #define mmCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 4930 #define mmCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G 0x0efa 4931 #define mmCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 4932 #define mmCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R 0x0efb 4933 #define mmCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 4934 #define mmCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_B 0x0efc 4935 #define mmCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 2 4936 #define mmCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_G 0x0efd 4937 #define mmCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 2 4938 #define mmCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_R 0x0efe 4939 #define mmCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 2 4940 #define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_B 0x0eff 4941 #define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX 2 4942 #define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_B 0x0f00 4943 #define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX 2 4944 #define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_G 0x0f01 4945 #define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX 2 4946 #define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_G 0x0f02 4947 #define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX 2 4948 #define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_R 0x0f03 4949 #define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX 2 4950 #define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_R 0x0f04 4951 #define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX 2 4952 #define mmCM1_CM_BLNDGAM_RAMA_OFFSET_B 0x0f05 4953 #define mmCM1_CM_BLNDGAM_RAMA_OFFSET_B_BASE_IDX 2 4954 #define mmCM1_CM_BLNDGAM_RAMA_OFFSET_G 0x0f06 4955 #define mmCM1_CM_BLNDGAM_RAMA_OFFSET_G_BASE_IDX 2 4956 #define mmCM1_CM_BLNDGAM_RAMA_OFFSET_R 0x0f07 4957 #define mmCM1_CM_BLNDGAM_RAMA_OFFSET_R_BASE_IDX 2 4958 #define mmCM1_CM_BLNDGAM_RAMA_REGION_0_1 0x0f08 4959 #define mmCM1_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX 2 4960 #define mmCM1_CM_BLNDGAM_RAMA_REGION_2_3 0x0f09 4961 #define mmCM1_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX 2 4962 #define mmCM1_CM_BLNDGAM_RAMA_REGION_4_5 0x0f0a 4963 #define mmCM1_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX 2 4964 #define mmCM1_CM_BLNDGAM_RAMA_REGION_6_7 0x0f0b 4965 #define mmCM1_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX 2 4966 #define mmCM1_CM_BLNDGAM_RAMA_REGION_8_9 0x0f0c 4967 #define mmCM1_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX 2 4968 #define mmCM1_CM_BLNDGAM_RAMA_REGION_10_11 0x0f0d 4969 #define mmCM1_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX 2 4970 #define mmCM1_CM_BLNDGAM_RAMA_REGION_12_13 0x0f0e 4971 #define mmCM1_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX 2 4972 #define mmCM1_CM_BLNDGAM_RAMA_REGION_14_15 0x0f0f 4973 #define mmCM1_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX 2 4974 #define mmCM1_CM_BLNDGAM_RAMA_REGION_16_17 0x0f10 4975 #define mmCM1_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX 2 4976 #define mmCM1_CM_BLNDGAM_RAMA_REGION_18_19 0x0f11 4977 #define mmCM1_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX 2 4978 #define mmCM1_CM_BLNDGAM_RAMA_REGION_20_21 0x0f12 4979 #define mmCM1_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX 2 4980 #define mmCM1_CM_BLNDGAM_RAMA_REGION_22_23 0x0f13 4981 #define mmCM1_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX 2 4982 #define mmCM1_CM_BLNDGAM_RAMA_REGION_24_25 0x0f14 4983 #define mmCM1_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX 2 4984 #define mmCM1_CM_BLNDGAM_RAMA_REGION_26_27 0x0f15 4985 #define mmCM1_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX 2 4986 #define mmCM1_CM_BLNDGAM_RAMA_REGION_28_29 0x0f16 4987 #define mmCM1_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX 2 4988 #define mmCM1_CM_BLNDGAM_RAMA_REGION_30_31 0x0f17 4989 #define mmCM1_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX 2 4990 #define mmCM1_CM_BLNDGAM_RAMA_REGION_32_33 0x0f18 4991 #define mmCM1_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX 2 4992 #define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_B 0x0f19 4993 #define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX 2 4994 #define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_G 0x0f1a 4995 #define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX 2 4996 #define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_R 0x0f1b 4997 #define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX 2 4998 #define mmCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B 0x0f1c 4999 #define mmCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 5000 #define mmCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G 0x0f1d 5001 #define mmCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 5002 #define mmCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R 0x0f1e 5003 #define mmCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 5004 #define mmCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_B 0x0f1f 5005 #define mmCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 2 5006 #define mmCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_G 0x0f20 5007 #define mmCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 2 5008 #define mmCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_R 0x0f21 5009 #define mmCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 2 5010 #define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_B 0x0f22 5011 #define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX 2 5012 #define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_B 0x0f23 5013 #define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX 2 5014 #define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_G 0x0f24 5015 #define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX 2 5016 #define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_G 0x0f25 5017 #define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX 2 5018 #define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_R 0x0f26 5019 #define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX 2 5020 #define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_R 0x0f27 5021 #define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX 2 5022 #define mmCM1_CM_BLNDGAM_RAMB_OFFSET_B 0x0f28 5023 #define mmCM1_CM_BLNDGAM_RAMB_OFFSET_B_BASE_IDX 2 5024 #define mmCM1_CM_BLNDGAM_RAMB_OFFSET_G 0x0f29 5025 #define mmCM1_CM_BLNDGAM_RAMB_OFFSET_G_BASE_IDX 2 5026 #define mmCM1_CM_BLNDGAM_RAMB_OFFSET_R 0x0f2a 5027 #define mmCM1_CM_BLNDGAM_RAMB_OFFSET_R_BASE_IDX 2 5028 #define mmCM1_CM_BLNDGAM_RAMB_REGION_0_1 0x0f2b 5029 #define mmCM1_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX 2 5030 #define mmCM1_CM_BLNDGAM_RAMB_REGION_2_3 0x0f2c 5031 #define mmCM1_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX 2 5032 #define mmCM1_CM_BLNDGAM_RAMB_REGION_4_5 0x0f2d 5033 #define mmCM1_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX 2 5034 #define mmCM1_CM_BLNDGAM_RAMB_REGION_6_7 0x0f2e 5035 #define mmCM1_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX 2 5036 #define mmCM1_CM_BLNDGAM_RAMB_REGION_8_9 0x0f2f 5037 #define mmCM1_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX 2 5038 #define mmCM1_CM_BLNDGAM_RAMB_REGION_10_11 0x0f30 5039 #define mmCM1_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX 2 5040 #define mmCM1_CM_BLNDGAM_RAMB_REGION_12_13 0x0f31 5041 #define mmCM1_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX 2 5042 #define mmCM1_CM_BLNDGAM_RAMB_REGION_14_15 0x0f32 5043 #define mmCM1_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX 2 5044 #define mmCM1_CM_BLNDGAM_RAMB_REGION_16_17 0x0f33 5045 #define mmCM1_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX 2 5046 #define mmCM1_CM_BLNDGAM_RAMB_REGION_18_19 0x0f34 5047 #define mmCM1_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX 2 5048 #define mmCM1_CM_BLNDGAM_RAMB_REGION_20_21 0x0f35 5049 #define mmCM1_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX 2 5050 #define mmCM1_CM_BLNDGAM_RAMB_REGION_22_23 0x0f36 5051 #define mmCM1_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX 2 5052 #define mmCM1_CM_BLNDGAM_RAMB_REGION_24_25 0x0f37 5053 #define mmCM1_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX 2 5054 #define mmCM1_CM_BLNDGAM_RAMB_REGION_26_27 0x0f38 5055 #define mmCM1_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX 2 5056 #define mmCM1_CM_BLNDGAM_RAMB_REGION_28_29 0x0f39 5057 #define mmCM1_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX 2 5058 #define mmCM1_CM_BLNDGAM_RAMB_REGION_30_31 0x0f3a 5059 #define mmCM1_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX 2 5060 #define mmCM1_CM_BLNDGAM_RAMB_REGION_32_33 0x0f3b 5061 #define mmCM1_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX 2 5062 #define mmCM1_CM_HDR_MULT_COEF 0x0f3c 5063 #define mmCM1_CM_HDR_MULT_COEF_BASE_IDX 2 5064 #define mmCM1_CM_MEM_PWR_CTRL 0x0f3d 5065 #define mmCM1_CM_MEM_PWR_CTRL_BASE_IDX 2 5066 #define mmCM1_CM_MEM_PWR_STATUS 0x0f3e 5067 #define mmCM1_CM_MEM_PWR_STATUS_BASE_IDX 2 5068 #define mmCM1_CM_DEALPHA 0x0f40 5069 #define mmCM1_CM_DEALPHA_BASE_IDX 2 5070 #define mmCM1_CM_COEF_FORMAT 0x0f41 5071 #define mmCM1_CM_COEF_FORMAT_BASE_IDX 2 5072 #define mmCM1_CM_SHAPER_CONTROL 0x0f42 5073 #define mmCM1_CM_SHAPER_CONTROL_BASE_IDX 2 5074 #define mmCM1_CM_SHAPER_OFFSET_R 0x0f43 5075 #define mmCM1_CM_SHAPER_OFFSET_R_BASE_IDX 2 5076 #define mmCM1_CM_SHAPER_OFFSET_G 0x0f44 5077 #define mmCM1_CM_SHAPER_OFFSET_G_BASE_IDX 2 5078 #define mmCM1_CM_SHAPER_OFFSET_B 0x0f45 5079 #define mmCM1_CM_SHAPER_OFFSET_B_BASE_IDX 2 5080 #define mmCM1_CM_SHAPER_SCALE_R 0x0f46 5081 #define mmCM1_CM_SHAPER_SCALE_R_BASE_IDX 2 5082 #define mmCM1_CM_SHAPER_SCALE_G_B 0x0f47 5083 #define mmCM1_CM_SHAPER_SCALE_G_B_BASE_IDX 2 5084 #define mmCM1_CM_SHAPER_LUT_INDEX 0x0f48 5085 #define mmCM1_CM_SHAPER_LUT_INDEX_BASE_IDX 2 5086 #define mmCM1_CM_SHAPER_LUT_DATA 0x0f49 5087 #define mmCM1_CM_SHAPER_LUT_DATA_BASE_IDX 2 5088 #define mmCM1_CM_SHAPER_LUT_WRITE_EN_MASK 0x0f4a 5089 #define mmCM1_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 2 5090 #define mmCM1_CM_SHAPER_RAMA_START_CNTL_B 0x0f4b 5091 #define mmCM1_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 2 5092 #define mmCM1_CM_SHAPER_RAMA_START_CNTL_G 0x0f4c 5093 #define mmCM1_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 2 5094 #define mmCM1_CM_SHAPER_RAMA_START_CNTL_R 0x0f4d 5095 #define mmCM1_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 2 5096 #define mmCM1_CM_SHAPER_RAMA_END_CNTL_B 0x0f4e 5097 #define mmCM1_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 2 5098 #define mmCM1_CM_SHAPER_RAMA_END_CNTL_G 0x0f4f 5099 #define mmCM1_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 2 5100 #define mmCM1_CM_SHAPER_RAMA_END_CNTL_R 0x0f50 5101 #define mmCM1_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 2 5102 #define mmCM1_CM_SHAPER_RAMA_REGION_0_1 0x0f51 5103 #define mmCM1_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX 2 5104 #define mmCM1_CM_SHAPER_RAMA_REGION_2_3 0x0f52 5105 #define mmCM1_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX 2 5106 #define mmCM1_CM_SHAPER_RAMA_REGION_4_5 0x0f53 5107 #define mmCM1_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX 2 5108 #define mmCM1_CM_SHAPER_RAMA_REGION_6_7 0x0f54 5109 #define mmCM1_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX 2 5110 #define mmCM1_CM_SHAPER_RAMA_REGION_8_9 0x0f55 5111 #define mmCM1_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX 2 5112 #define mmCM1_CM_SHAPER_RAMA_REGION_10_11 0x0f56 5113 #define mmCM1_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX 2 5114 #define mmCM1_CM_SHAPER_RAMA_REGION_12_13 0x0f57 5115 #define mmCM1_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX 2 5116 #define mmCM1_CM_SHAPER_RAMA_REGION_14_15 0x0f58 5117 #define mmCM1_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX 2 5118 #define mmCM1_CM_SHAPER_RAMA_REGION_16_17 0x0f59 5119 #define mmCM1_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX 2 5120 #define mmCM1_CM_SHAPER_RAMA_REGION_18_19 0x0f5a 5121 #define mmCM1_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX 2 5122 #define mmCM1_CM_SHAPER_RAMA_REGION_20_21 0x0f5b 5123 #define mmCM1_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX 2 5124 #define mmCM1_CM_SHAPER_RAMA_REGION_22_23 0x0f5c 5125 #define mmCM1_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX 2 5126 #define mmCM1_CM_SHAPER_RAMA_REGION_24_25 0x0f5d 5127 #define mmCM1_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX 2 5128 #define mmCM1_CM_SHAPER_RAMA_REGION_26_27 0x0f5e 5129 #define mmCM1_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX 2 5130 #define mmCM1_CM_SHAPER_RAMA_REGION_28_29 0x0f5f 5131 #define mmCM1_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX 2 5132 #define mmCM1_CM_SHAPER_RAMA_REGION_30_31 0x0f60 5133 #define mmCM1_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX 2 5134 #define mmCM1_CM_SHAPER_RAMA_REGION_32_33 0x0f61 5135 #define mmCM1_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX 2 5136 #define mmCM1_CM_SHAPER_RAMB_START_CNTL_B 0x0f62 5137 #define mmCM1_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 2 5138 #define mmCM1_CM_SHAPER_RAMB_START_CNTL_G 0x0f63 5139 #define mmCM1_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 2 5140 #define mmCM1_CM_SHAPER_RAMB_START_CNTL_R 0x0f64 5141 #define mmCM1_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 2 5142 #define mmCM1_CM_SHAPER_RAMB_END_CNTL_B 0x0f65 5143 #define mmCM1_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 2 5144 #define mmCM1_CM_SHAPER_RAMB_END_CNTL_G 0x0f66 5145 #define mmCM1_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 2 5146 #define mmCM1_CM_SHAPER_RAMB_END_CNTL_R 0x0f67 5147 #define mmCM1_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 2 5148 #define mmCM1_CM_SHAPER_RAMB_REGION_0_1 0x0f68 5149 #define mmCM1_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX 2 5150 #define mmCM1_CM_SHAPER_RAMB_REGION_2_3 0x0f69 5151 #define mmCM1_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX 2 5152 #define mmCM1_CM_SHAPER_RAMB_REGION_4_5 0x0f6a 5153 #define mmCM1_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX 2 5154 #define mmCM1_CM_SHAPER_RAMB_REGION_6_7 0x0f6b 5155 #define mmCM1_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX 2 5156 #define mmCM1_CM_SHAPER_RAMB_REGION_8_9 0x0f6c 5157 #define mmCM1_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX 2 5158 #define mmCM1_CM_SHAPER_RAMB_REGION_10_11 0x0f6d 5159 #define mmCM1_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX 2 5160 #define mmCM1_CM_SHAPER_RAMB_REGION_12_13 0x0f6e 5161 #define mmCM1_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX 2 5162 #define mmCM1_CM_SHAPER_RAMB_REGION_14_15 0x0f6f 5163 #define mmCM1_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX 2 5164 #define mmCM1_CM_SHAPER_RAMB_REGION_16_17 0x0f70 5165 #define mmCM1_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX 2 5166 #define mmCM1_CM_SHAPER_RAMB_REGION_18_19 0x0f71 5167 #define mmCM1_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX 2 5168 #define mmCM1_CM_SHAPER_RAMB_REGION_20_21 0x0f72 5169 #define mmCM1_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX 2 5170 #define mmCM1_CM_SHAPER_RAMB_REGION_22_23 0x0f73 5171 #define mmCM1_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX 2 5172 #define mmCM1_CM_SHAPER_RAMB_REGION_24_25 0x0f74 5173 #define mmCM1_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX 2 5174 #define mmCM1_CM_SHAPER_RAMB_REGION_26_27 0x0f75 5175 #define mmCM1_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX 2 5176 #define mmCM1_CM_SHAPER_RAMB_REGION_28_29 0x0f76 5177 #define mmCM1_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX 2 5178 #define mmCM1_CM_SHAPER_RAMB_REGION_30_31 0x0f77 5179 #define mmCM1_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX 2 5180 #define mmCM1_CM_SHAPER_RAMB_REGION_32_33 0x0f78 5181 #define mmCM1_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX 2 5182 #define mmCM1_CM_MEM_PWR_CTRL2 0x0f79 5183 #define mmCM1_CM_MEM_PWR_CTRL2_BASE_IDX 2 5184 #define mmCM1_CM_MEM_PWR_STATUS2 0x0f7a 5185 #define mmCM1_CM_MEM_PWR_STATUS2_BASE_IDX 2 5186 #define mmCM1_CM_3DLUT_MODE 0x0f7b 5187 #define mmCM1_CM_3DLUT_MODE_BASE_IDX 2 5188 #define mmCM1_CM_3DLUT_INDEX 0x0f7c 5189 #define mmCM1_CM_3DLUT_INDEX_BASE_IDX 2 5190 #define mmCM1_CM_3DLUT_DATA 0x0f7d 5191 #define mmCM1_CM_3DLUT_DATA_BASE_IDX 2 5192 #define mmCM1_CM_3DLUT_DATA_30BIT 0x0f7e 5193 #define mmCM1_CM_3DLUT_DATA_30BIT_BASE_IDX 2 5194 #define mmCM1_CM_3DLUT_READ_WRITE_CONTROL 0x0f7f 5195 #define mmCM1_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 2 5196 #define mmCM1_CM_3DLUT_OUT_NORM_FACTOR 0x0f80 5197 #define mmCM1_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 2 5198 #define mmCM1_CM_3DLUT_OUT_OFFSET_R 0x0f81 5199 #define mmCM1_CM_3DLUT_OUT_OFFSET_R_BASE_IDX 2 5200 #define mmCM1_CM_3DLUT_OUT_OFFSET_G 0x0f82 5201 #define mmCM1_CM_3DLUT_OUT_OFFSET_G_BASE_IDX 2 5202 #define mmCM1_CM_3DLUT_OUT_OFFSET_B 0x0f83 5203 #define mmCM1_CM_3DLUT_OUT_OFFSET_B_BASE_IDX 2 5204 5205 5206 // addressBlock: dce_dc_dpp1_dispdec_dpp_dcperfmon_dc_perfmon_dispdec 5207 // base address: 0x3e3c 5208 #define mmDC_PERFMON13_PERFCOUNTER_CNTL 0x0f8f 5209 #define mmDC_PERFMON13_PERFCOUNTER_CNTL_BASE_IDX 2 5210 #define mmDC_PERFMON13_PERFCOUNTER_CNTL2 0x0f90 5211 #define mmDC_PERFMON13_PERFCOUNTER_CNTL2_BASE_IDX 2 5212 #define mmDC_PERFMON13_PERFCOUNTER_STATE 0x0f91 5213 #define mmDC_PERFMON13_PERFCOUNTER_STATE_BASE_IDX 2 5214 #define mmDC_PERFMON13_PERFMON_CNTL 0x0f92 5215 #define mmDC_PERFMON13_PERFMON_CNTL_BASE_IDX 2 5216 #define mmDC_PERFMON13_PERFMON_CNTL2 0x0f93 5217 #define mmDC_PERFMON13_PERFMON_CNTL2_BASE_IDX 2 5218 #define mmDC_PERFMON13_PERFMON_CVALUE_INT_MISC 0x0f94 5219 #define mmDC_PERFMON13_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 5220 #define mmDC_PERFMON13_PERFMON_CVALUE_LOW 0x0f95 5221 #define mmDC_PERFMON13_PERFMON_CVALUE_LOW_BASE_IDX 2 5222 #define mmDC_PERFMON13_PERFMON_HI 0x0f96 5223 #define mmDC_PERFMON13_PERFMON_HI_BASE_IDX 2 5224 #define mmDC_PERFMON13_PERFMON_LOW 0x0f97 5225 #define mmDC_PERFMON13_PERFMON_LOW_BASE_IDX 2 5226 5227 5228 // addressBlock: dce_dc_dpp2_dispdec_dpp_top_dispdec 5229 // base address: 0xb58 5230 #define mmDPP_TOP2_DPP_CONTROL 0x0f9b 5231 #define mmDPP_TOP2_DPP_CONTROL_BASE_IDX 2 5232 #define mmDPP_TOP2_DPP_SOFT_RESET 0x0f9c 5233 #define mmDPP_TOP2_DPP_SOFT_RESET_BASE_IDX 2 5234 #define mmDPP_TOP2_DPP_CRC_VAL_R_G 0x0f9d 5235 #define mmDPP_TOP2_DPP_CRC_VAL_R_G_BASE_IDX 2 5236 #define mmDPP_TOP2_DPP_CRC_VAL_B_A 0x0f9e 5237 #define mmDPP_TOP2_DPP_CRC_VAL_B_A_BASE_IDX 2 5238 #define mmDPP_TOP2_DPP_CRC_CTRL 0x0f9f 5239 #define mmDPP_TOP2_DPP_CRC_CTRL_BASE_IDX 2 5240 #define mmDPP_TOP2_HOST_READ_CONTROL 0x0fa0 5241 #define mmDPP_TOP2_HOST_READ_CONTROL_BASE_IDX 2 5242 5243 5244 // addressBlock: dce_dc_dpp2_dispdec_cnvc_cfg_dispdec 5245 // base address: 0xb58 5246 #define mmCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT 0x0fa5 5247 #define mmCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2 5248 #define mmCNVC_CFG2_FORMAT_CONTROL 0x0fa6 5249 #define mmCNVC_CFG2_FORMAT_CONTROL_BASE_IDX 2 5250 #define mmCNVC_CFG2_FCNV_FP_BIAS_R 0x0fa7 5251 #define mmCNVC_CFG2_FCNV_FP_BIAS_R_BASE_IDX 2 5252 #define mmCNVC_CFG2_FCNV_FP_BIAS_G 0x0fa8 5253 #define mmCNVC_CFG2_FCNV_FP_BIAS_G_BASE_IDX 2 5254 #define mmCNVC_CFG2_FCNV_FP_BIAS_B 0x0fa9 5255 #define mmCNVC_CFG2_FCNV_FP_BIAS_B_BASE_IDX 2 5256 #define mmCNVC_CFG2_FCNV_FP_SCALE_R 0x0faa 5257 #define mmCNVC_CFG2_FCNV_FP_SCALE_R_BASE_IDX 2 5258 #define mmCNVC_CFG2_FCNV_FP_SCALE_G 0x0fab 5259 #define mmCNVC_CFG2_FCNV_FP_SCALE_G_BASE_IDX 2 5260 #define mmCNVC_CFG2_FCNV_FP_SCALE_B 0x0fac 5261 #define mmCNVC_CFG2_FCNV_FP_SCALE_B_BASE_IDX 2 5262 #define mmCNVC_CFG2_COLOR_KEYER_CONTROL 0x0fad 5263 #define mmCNVC_CFG2_COLOR_KEYER_CONTROL_BASE_IDX 2 5264 #define mmCNVC_CFG2_COLOR_KEYER_ALPHA 0x0fae 5265 #define mmCNVC_CFG2_COLOR_KEYER_ALPHA_BASE_IDX 2 5266 #define mmCNVC_CFG2_COLOR_KEYER_RED 0x0faf 5267 #define mmCNVC_CFG2_COLOR_KEYER_RED_BASE_IDX 2 5268 #define mmCNVC_CFG2_COLOR_KEYER_GREEN 0x0fb0 5269 #define mmCNVC_CFG2_COLOR_KEYER_GREEN_BASE_IDX 2 5270 #define mmCNVC_CFG2_COLOR_KEYER_BLUE 0x0fb1 5271 #define mmCNVC_CFG2_COLOR_KEYER_BLUE_BASE_IDX 2 5272 #define mmCNVC_CFG2_ALPHA_2BIT_LUT 0x0fb3 5273 #define mmCNVC_CFG2_ALPHA_2BIT_LUT_BASE_IDX 2 5274 #define mmCNVC_CFG2_PRE_DEALPHA 0x0fb4 5275 #define mmCNVC_CFG2_PRE_DEALPHA_BASE_IDX 2 5276 #define mmCNVC_CFG2_PRE_CSC_MODE 0x0fb5 5277 #define mmCNVC_CFG2_PRE_CSC_MODE_BASE_IDX 2 5278 #define mmCNVC_CFG2_PRE_CSC_C11_C12 0x0fb6 5279 #define mmCNVC_CFG2_PRE_CSC_C11_C12_BASE_IDX 2 5280 #define mmCNVC_CFG2_PRE_CSC_C13_C14 0x0fb7 5281 #define mmCNVC_CFG2_PRE_CSC_C13_C14_BASE_IDX 2 5282 #define mmCNVC_CFG2_PRE_CSC_C21_C22 0x0fb8 5283 #define mmCNVC_CFG2_PRE_CSC_C21_C22_BASE_IDX 2 5284 #define mmCNVC_CFG2_PRE_CSC_C23_C24 0x0fb9 5285 #define mmCNVC_CFG2_PRE_CSC_C23_C24_BASE_IDX 2 5286 #define mmCNVC_CFG2_PRE_CSC_C31_C32 0x0fba 5287 #define mmCNVC_CFG2_PRE_CSC_C31_C32_BASE_IDX 2 5288 #define mmCNVC_CFG2_PRE_CSC_C33_C34 0x0fbb 5289 #define mmCNVC_CFG2_PRE_CSC_C33_C34_BASE_IDX 2 5290 #define mmCNVC_CFG2_PRE_CSC_B_C11_C12 0x0fbc 5291 #define mmCNVC_CFG2_PRE_CSC_B_C11_C12_BASE_IDX 2 5292 #define mmCNVC_CFG2_PRE_CSC_B_C13_C14 0x0fbd 5293 #define mmCNVC_CFG2_PRE_CSC_B_C13_C14_BASE_IDX 2 5294 #define mmCNVC_CFG2_PRE_CSC_B_C21_C22 0x0fbe 5295 #define mmCNVC_CFG2_PRE_CSC_B_C21_C22_BASE_IDX 2 5296 #define mmCNVC_CFG2_PRE_CSC_B_C23_C24 0x0fbf 5297 #define mmCNVC_CFG2_PRE_CSC_B_C23_C24_BASE_IDX 2 5298 #define mmCNVC_CFG2_PRE_CSC_B_C31_C32 0x0fc0 5299 #define mmCNVC_CFG2_PRE_CSC_B_C31_C32_BASE_IDX 2 5300 #define mmCNVC_CFG2_PRE_CSC_B_C33_C34 0x0fc1 5301 #define mmCNVC_CFG2_PRE_CSC_B_C33_C34_BASE_IDX 2 5302 #define mmCNVC_CFG2_CNVC_COEF_FORMAT 0x0fc2 5303 #define mmCNVC_CFG2_CNVC_COEF_FORMAT_BASE_IDX 2 5304 #define mmCNVC_CFG2_PRE_DEGAM 0x0fc3 5305 #define mmCNVC_CFG2_PRE_DEGAM_BASE_IDX 2 5306 #define mmCNVC_CFG2_PRE_REALPHA 0x0fc4 5307 #define mmCNVC_CFG2_PRE_REALPHA_BASE_IDX 2 5308 5309 5310 // addressBlock: dce_dc_dpp2_dispdec_cnvc_cur_dispdec 5311 // base address: 0xb58 5312 #define mmCNVC_CUR2_CURSOR0_CONTROL 0x0fc7 5313 #define mmCNVC_CUR2_CURSOR0_CONTROL_BASE_IDX 2 5314 #define mmCNVC_CUR2_CURSOR0_COLOR0 0x0fc8 5315 #define mmCNVC_CUR2_CURSOR0_COLOR0_BASE_IDX 2 5316 #define mmCNVC_CUR2_CURSOR0_COLOR1 0x0fc9 5317 #define mmCNVC_CUR2_CURSOR0_COLOR1_BASE_IDX 2 5318 #define mmCNVC_CUR2_CURSOR0_FP_SCALE_BIAS 0x0fca 5319 #define mmCNVC_CUR2_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2 5320 5321 // addressBlock: dce_dc_dpp2_dispdec_dscl_dispdec 5322 // base address: 0xb58 5323 #define mmDSCL2_SCL_COEF_RAM_TAP_SELECT 0x0fcf 5324 #define mmDSCL2_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2 5325 #define mmDSCL2_SCL_COEF_RAM_TAP_DATA 0x0fd0 5326 #define mmDSCL2_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2 5327 #define mmDSCL2_SCL_MODE 0x0fd1 5328 #define mmDSCL2_SCL_MODE_BASE_IDX 2 5329 #define mmDSCL2_SCL_TAP_CONTROL 0x0fd2 5330 #define mmDSCL2_SCL_TAP_CONTROL_BASE_IDX 2 5331 #define mmDSCL2_DSCL_CONTROL 0x0fd3 5332 #define mmDSCL2_DSCL_CONTROL_BASE_IDX 2 5333 #define mmDSCL2_DSCL_2TAP_CONTROL 0x0fd4 5334 #define mmDSCL2_DSCL_2TAP_CONTROL_BASE_IDX 2 5335 #define mmDSCL2_SCL_MANUAL_REPLICATE_CONTROL 0x0fd5 5336 #define mmDSCL2_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 5337 #define mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO 0x0fd6 5338 #define mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 5339 #define mmDSCL2_SCL_HORZ_FILTER_INIT 0x0fd7 5340 #define mmDSCL2_SCL_HORZ_FILTER_INIT_BASE_IDX 2 5341 #define mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C 0x0fd8 5342 #define mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2 5343 #define mmDSCL2_SCL_HORZ_FILTER_INIT_C 0x0fd9 5344 #define mmDSCL2_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2 5345 #define mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO 0x0fda 5346 #define mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 5347 #define mmDSCL2_SCL_VERT_FILTER_INIT 0x0fdb 5348 #define mmDSCL2_SCL_VERT_FILTER_INIT_BASE_IDX 2 5349 #define mmDSCL2_SCL_VERT_FILTER_INIT_BOT 0x0fdc 5350 #define mmDSCL2_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2 5351 #define mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C 0x0fdd 5352 #define mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2 5353 #define mmDSCL2_SCL_VERT_FILTER_INIT_C 0x0fde 5354 #define mmDSCL2_SCL_VERT_FILTER_INIT_C_BASE_IDX 2 5355 #define mmDSCL2_SCL_VERT_FILTER_INIT_BOT_C 0x0fdf 5356 #define mmDSCL2_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2 5357 #define mmDSCL2_SCL_BLACK_COLOR 0x0fe0 5358 #define mmDSCL2_SCL_BLACK_COLOR_BASE_IDX 2 5359 #define mmDSCL2_DSCL_UPDATE 0x0fe1 5360 #define mmDSCL2_DSCL_UPDATE_BASE_IDX 2 5361 #define mmDSCL2_DSCL_AUTOCAL 0x0fe2 5362 #define mmDSCL2_DSCL_AUTOCAL_BASE_IDX 2 5363 #define mmDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x0fe3 5364 #define mmDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 5365 #define mmDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x0fe4 5366 #define mmDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 5367 #define mmDSCL2_OTG_H_BLANK 0x0fe5 5368 #define mmDSCL2_OTG_H_BLANK_BASE_IDX 2 5369 #define mmDSCL2_OTG_V_BLANK 0x0fe6 5370 #define mmDSCL2_OTG_V_BLANK_BASE_IDX 2 5371 #define mmDSCL2_RECOUT_START 0x0fe7 5372 #define mmDSCL2_RECOUT_START_BASE_IDX 2 5373 #define mmDSCL2_RECOUT_SIZE 0x0fe8 5374 #define mmDSCL2_RECOUT_SIZE_BASE_IDX 2 5375 #define mmDSCL2_MPC_SIZE 0x0fe9 5376 #define mmDSCL2_MPC_SIZE_BASE_IDX 2 5377 #define mmDSCL2_LB_DATA_FORMAT 0x0fea 5378 #define mmDSCL2_LB_DATA_FORMAT_BASE_IDX 2 5379 #define mmDSCL2_LB_MEMORY_CTRL 0x0feb 5380 #define mmDSCL2_LB_MEMORY_CTRL_BASE_IDX 2 5381 #define mmDSCL2_LB_V_COUNTER 0x0fec 5382 #define mmDSCL2_LB_V_COUNTER_BASE_IDX 2 5383 #define mmDSCL2_DSCL_MEM_PWR_CTRL 0x0fed 5384 #define mmDSCL2_DSCL_MEM_PWR_CTRL_BASE_IDX 2 5385 #define mmDSCL2_DSCL_MEM_PWR_STATUS 0x0fee 5386 #define mmDSCL2_DSCL_MEM_PWR_STATUS_BASE_IDX 2 5387 #define mmDSCL2_OBUF_CONTROL 0x0fef 5388 #define mmDSCL2_OBUF_CONTROL_BASE_IDX 2 5389 #define mmDSCL2_OBUF_MEM_PWR_CTRL 0x0ff0 5390 #define mmDSCL2_OBUF_MEM_PWR_CTRL_BASE_IDX 2 5391 5392 5393 // addressBlock: dce_dc_dpp2_dispdec_cm_dispdec 5394 // base address: 0xb58 5395 #define mmCM2_CM_CONTROL 0x0ff6 5396 #define mmCM2_CM_CONTROL_BASE_IDX 2 5397 #define mmCM2_CM_POST_CSC_CONTROL 0x0ff7 5398 #define mmCM2_CM_POST_CSC_CONTROL_BASE_IDX 2 5399 #define mmCM2_CM_POST_CSC_C11_C12 0x0ff8 5400 #define mmCM2_CM_POST_CSC_C11_C12_BASE_IDX 2 5401 #define mmCM2_CM_POST_CSC_C13_C14 0x0ff9 5402 #define mmCM2_CM_POST_CSC_C13_C14_BASE_IDX 2 5403 #define mmCM2_CM_POST_CSC_C21_C22 0x0ffa 5404 #define mmCM2_CM_POST_CSC_C21_C22_BASE_IDX 2 5405 #define mmCM2_CM_POST_CSC_C23_C24 0x0ffb 5406 #define mmCM2_CM_POST_CSC_C23_C24_BASE_IDX 2 5407 #define mmCM2_CM_POST_CSC_C31_C32 0x0ffc 5408 #define mmCM2_CM_POST_CSC_C31_C32_BASE_IDX 2 5409 #define mmCM2_CM_POST_CSC_C33_C34 0x0ffd 5410 #define mmCM2_CM_POST_CSC_C33_C34_BASE_IDX 2 5411 #define mmCM2_CM_POST_CSC_B_C11_C12 0x0ffe 5412 #define mmCM2_CM_POST_CSC_B_C11_C12_BASE_IDX 2 5413 #define mmCM2_CM_POST_CSC_B_C13_C14 0x0fff 5414 #define mmCM2_CM_POST_CSC_B_C13_C14_BASE_IDX 2 5415 #define mmCM2_CM_POST_CSC_B_C21_C22 0x1000 5416 #define mmCM2_CM_POST_CSC_B_C21_C22_BASE_IDX 2 5417 #define mmCM2_CM_POST_CSC_B_C23_C24 0x1001 5418 #define mmCM2_CM_POST_CSC_B_C23_C24_BASE_IDX 2 5419 #define mmCM2_CM_POST_CSC_B_C31_C32 0x1002 5420 #define mmCM2_CM_POST_CSC_B_C31_C32_BASE_IDX 2 5421 #define mmCM2_CM_POST_CSC_B_C33_C34 0x1003 5422 #define mmCM2_CM_POST_CSC_B_C33_C34_BASE_IDX 2 5423 #define mmCM2_CM_GAMUT_REMAP_CONTROL 0x1004 5424 #define mmCM2_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2 5425 #define mmCM2_CM_GAMUT_REMAP_C11_C12 0x1005 5426 #define mmCM2_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2 5427 #define mmCM2_CM_GAMUT_REMAP_C13_C14 0x1006 5428 #define mmCM2_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2 5429 #define mmCM2_CM_GAMUT_REMAP_C21_C22 0x1007 5430 #define mmCM2_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2 5431 #define mmCM2_CM_GAMUT_REMAP_C23_C24 0x1008 5432 #define mmCM2_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2 5433 #define mmCM2_CM_GAMUT_REMAP_C31_C32 0x1009 5434 #define mmCM2_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2 5435 #define mmCM2_CM_GAMUT_REMAP_C33_C34 0x100a 5436 #define mmCM2_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2 5437 #define mmCM2_CM_GAMUT_REMAP_B_C11_C12 0x100b 5438 #define mmCM2_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX 2 5439 #define mmCM2_CM_GAMUT_REMAP_B_C13_C14 0x100c 5440 #define mmCM2_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX 2 5441 #define mmCM2_CM_GAMUT_REMAP_B_C21_C22 0x100d 5442 #define mmCM2_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX 2 5443 #define mmCM2_CM_GAMUT_REMAP_B_C23_C24 0x100e 5444 #define mmCM2_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX 2 5445 #define mmCM2_CM_GAMUT_REMAP_B_C31_C32 0x100f 5446 #define mmCM2_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX 2 5447 #define mmCM2_CM_GAMUT_REMAP_B_C33_C34 0x1010 5448 #define mmCM2_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX 2 5449 #define mmCM2_CM_BIAS_CR_R 0x1011 5450 #define mmCM2_CM_BIAS_CR_R_BASE_IDX 2 5451 #define mmCM2_CM_BIAS_Y_G_CB_B 0x1012 5452 #define mmCM2_CM_BIAS_Y_G_CB_B_BASE_IDX 2 5453 #define mmCM2_CM_GAMCOR_CONTROL 0x1013 5454 #define mmCM2_CM_GAMCOR_CONTROL_BASE_IDX 2 5455 #define mmCM2_CM_GAMCOR_LUT_INDEX 0x1014 5456 #define mmCM2_CM_GAMCOR_LUT_INDEX_BASE_IDX 2 5457 #define mmCM2_CM_GAMCOR_LUT_DATA 0x1015 5458 #define mmCM2_CM_GAMCOR_LUT_DATA_BASE_IDX 2 5459 #define mmCM2_CM_GAMCOR_LUT_CONTROL 0x1016 5460 #define mmCM2_CM_GAMCOR_LUT_CONTROL_BASE_IDX 2 5461 #define mmCM2_CM_GAMCOR_RAMA_START_CNTL_B 0x1017 5462 #define mmCM2_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX 2 5463 #define mmCM2_CM_GAMCOR_RAMA_START_CNTL_G 0x1018 5464 #define mmCM2_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX 2 5465 #define mmCM2_CM_GAMCOR_RAMA_START_CNTL_R 0x1019 5466 #define mmCM2_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX 2 5467 #define mmCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B 0x101a 5468 #define mmCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 5469 #define mmCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G 0x101b 5470 #define mmCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 5471 #define mmCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R 0x101c 5472 #define mmCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 5473 #define mmCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_B 0x101d 5474 #define mmCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX 2 5475 #define mmCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_G 0x101e 5476 #define mmCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX 2 5477 #define mmCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_R 0x101f 5478 #define mmCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX 2 5479 #define mmCM2_CM_GAMCOR_RAMA_END_CNTL1_B 0x1020 5480 #define mmCM2_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX 2 5481 #define mmCM2_CM_GAMCOR_RAMA_END_CNTL2_B 0x1021 5482 #define mmCM2_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX 2 5483 #define mmCM2_CM_GAMCOR_RAMA_END_CNTL1_G 0x1022 5484 #define mmCM2_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX 2 5485 #define mmCM2_CM_GAMCOR_RAMA_END_CNTL2_G 0x1023 5486 #define mmCM2_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX 2 5487 #define mmCM2_CM_GAMCOR_RAMA_END_CNTL1_R 0x1024 5488 #define mmCM2_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX 2 5489 #define mmCM2_CM_GAMCOR_RAMA_END_CNTL2_R 0x1025 5490 #define mmCM2_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX 2 5491 #define mmCM2_CM_GAMCOR_RAMA_OFFSET_B 0x1026 5492 #define mmCM2_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX 2 5493 #define mmCM2_CM_GAMCOR_RAMA_OFFSET_G 0x1027 5494 #define mmCM2_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX 2 5495 #define mmCM2_CM_GAMCOR_RAMA_OFFSET_R 0x1028 5496 #define mmCM2_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX 2 5497 #define mmCM2_CM_GAMCOR_RAMA_REGION_0_1 0x1029 5498 #define mmCM2_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX 2 5499 #define mmCM2_CM_GAMCOR_RAMA_REGION_2_3 0x102a 5500 #define mmCM2_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX 2 5501 #define mmCM2_CM_GAMCOR_RAMA_REGION_4_5 0x102b 5502 #define mmCM2_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX 2 5503 #define mmCM2_CM_GAMCOR_RAMA_REGION_6_7 0x102c 5504 #define mmCM2_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX 2 5505 #define mmCM2_CM_GAMCOR_RAMA_REGION_8_9 0x102d 5506 #define mmCM2_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX 2 5507 #define mmCM2_CM_GAMCOR_RAMA_REGION_10_11 0x102e 5508 #define mmCM2_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX 2 5509 #define mmCM2_CM_GAMCOR_RAMA_REGION_12_13 0x102f 5510 #define mmCM2_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX 2 5511 #define mmCM2_CM_GAMCOR_RAMA_REGION_14_15 0x1030 5512 #define mmCM2_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX 2 5513 #define mmCM2_CM_GAMCOR_RAMA_REGION_16_17 0x1031 5514 #define mmCM2_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX 2 5515 #define mmCM2_CM_GAMCOR_RAMA_REGION_18_19 0x1032 5516 #define mmCM2_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX 2 5517 #define mmCM2_CM_GAMCOR_RAMA_REGION_20_21 0x1033 5518 #define mmCM2_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX 2 5519 #define mmCM2_CM_GAMCOR_RAMA_REGION_22_23 0x1034 5520 #define mmCM2_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX 2 5521 #define mmCM2_CM_GAMCOR_RAMA_REGION_24_25 0x1035 5522 #define mmCM2_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX 2 5523 #define mmCM2_CM_GAMCOR_RAMA_REGION_26_27 0x1036 5524 #define mmCM2_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX 2 5525 #define mmCM2_CM_GAMCOR_RAMA_REGION_28_29 0x1037 5526 #define mmCM2_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX 2 5527 #define mmCM2_CM_GAMCOR_RAMA_REGION_30_31 0x1038 5528 #define mmCM2_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX 2 5529 #define mmCM2_CM_GAMCOR_RAMA_REGION_32_33 0x1039 5530 #define mmCM2_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX 2 5531 #define mmCM2_CM_GAMCOR_RAMB_START_CNTL_B 0x103a 5532 #define mmCM2_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX 2 5533 #define mmCM2_CM_GAMCOR_RAMB_START_CNTL_G 0x103b 5534 #define mmCM2_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX 2 5535 #define mmCM2_CM_GAMCOR_RAMB_START_CNTL_R 0x103c 5536 #define mmCM2_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX 2 5537 #define mmCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B 0x103d 5538 #define mmCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 5539 #define mmCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G 0x103e 5540 #define mmCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 5541 #define mmCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R 0x103f 5542 #define mmCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 5543 #define mmCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_B 0x1040 5544 #define mmCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX 2 5545 #define mmCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_G 0x1041 5546 #define mmCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX 2 5547 #define mmCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_R 0x1042 5548 #define mmCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX 2 5549 #define mmCM2_CM_GAMCOR_RAMB_END_CNTL1_B 0x1043 5550 #define mmCM2_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX 2 5551 #define mmCM2_CM_GAMCOR_RAMB_END_CNTL2_B 0x1044 5552 #define mmCM2_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX 2 5553 #define mmCM2_CM_GAMCOR_RAMB_END_CNTL1_G 0x1045 5554 #define mmCM2_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX 2 5555 #define mmCM2_CM_GAMCOR_RAMB_END_CNTL2_G 0x1046 5556 #define mmCM2_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX 2 5557 #define mmCM2_CM_GAMCOR_RAMB_END_CNTL1_R 0x1047 5558 #define mmCM2_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX 2 5559 #define mmCM2_CM_GAMCOR_RAMB_END_CNTL2_R 0x1048 5560 #define mmCM2_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX 2 5561 #define mmCM2_CM_GAMCOR_RAMB_OFFSET_B 0x1049 5562 #define mmCM2_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX 2 5563 #define mmCM2_CM_GAMCOR_RAMB_OFFSET_G 0x104a 5564 #define mmCM2_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX 2 5565 #define mmCM2_CM_GAMCOR_RAMB_OFFSET_R 0x104b 5566 #define mmCM2_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX 2 5567 #define mmCM2_CM_GAMCOR_RAMB_REGION_0_1 0x104c 5568 #define mmCM2_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX 2 5569 #define mmCM2_CM_GAMCOR_RAMB_REGION_2_3 0x104d 5570 #define mmCM2_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX 2 5571 #define mmCM2_CM_GAMCOR_RAMB_REGION_4_5 0x104e 5572 #define mmCM2_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX 2 5573 #define mmCM2_CM_GAMCOR_RAMB_REGION_6_7 0x104f 5574 #define mmCM2_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX 2 5575 #define mmCM2_CM_GAMCOR_RAMB_REGION_8_9 0x1050 5576 #define mmCM2_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX 2 5577 #define mmCM2_CM_GAMCOR_RAMB_REGION_10_11 0x1051 5578 #define mmCM2_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX 2 5579 #define mmCM2_CM_GAMCOR_RAMB_REGION_12_13 0x1052 5580 #define mmCM2_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX 2 5581 #define mmCM2_CM_GAMCOR_RAMB_REGION_14_15 0x1053 5582 #define mmCM2_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX 2 5583 #define mmCM2_CM_GAMCOR_RAMB_REGION_16_17 0x1054 5584 #define mmCM2_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX 2 5585 #define mmCM2_CM_GAMCOR_RAMB_REGION_18_19 0x1055 5586 #define mmCM2_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX 2 5587 #define mmCM2_CM_GAMCOR_RAMB_REGION_20_21 0x1056 5588 #define mmCM2_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX 2 5589 #define mmCM2_CM_GAMCOR_RAMB_REGION_22_23 0x1057 5590 #define mmCM2_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX 2 5591 #define mmCM2_CM_GAMCOR_RAMB_REGION_24_25 0x1058 5592 #define mmCM2_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX 2 5593 #define mmCM2_CM_GAMCOR_RAMB_REGION_26_27 0x1059 5594 #define mmCM2_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX 2 5595 #define mmCM2_CM_GAMCOR_RAMB_REGION_28_29 0x105a 5596 #define mmCM2_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX 2 5597 #define mmCM2_CM_GAMCOR_RAMB_REGION_30_31 0x105b 5598 #define mmCM2_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX 2 5599 #define mmCM2_CM_GAMCOR_RAMB_REGION_32_33 0x105c 5600 #define mmCM2_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX 2 5601 #define mmCM2_CM_BLNDGAM_CONTROL 0x105d 5602 #define mmCM2_CM_BLNDGAM_CONTROL_BASE_IDX 2 5603 #define mmCM2_CM_BLNDGAM_LUT_INDEX 0x105e 5604 #define mmCM2_CM_BLNDGAM_LUT_INDEX_BASE_IDX 2 5605 #define mmCM2_CM_BLNDGAM_LUT_DATA 0x105f 5606 #define mmCM2_CM_BLNDGAM_LUT_DATA_BASE_IDX 2 5607 #define mmCM2_CM_BLNDGAM_LUT_CONTROL 0x1060 5608 #define mmCM2_CM_BLNDGAM_LUT_CONTROL_BASE_IDX 2 5609 #define mmCM2_CM_BLNDGAM_RAMA_START_CNTL_B 0x1061 5610 #define mmCM2_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX 2 5611 #define mmCM2_CM_BLNDGAM_RAMA_START_CNTL_G 0x1062 5612 #define mmCM2_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX 2 5613 #define mmCM2_CM_BLNDGAM_RAMA_START_CNTL_R 0x1063 5614 #define mmCM2_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX 2 5615 #define mmCM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B 0x1064 5616 #define mmCM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 5617 #define mmCM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G 0x1065 5618 #define mmCM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 5619 #define mmCM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R 0x1066 5620 #define mmCM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 5621 #define mmCM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_B 0x1067 5622 #define mmCM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 2 5623 #define mmCM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_G 0x1068 5624 #define mmCM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 2 5625 #define mmCM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_R 0x1069 5626 #define mmCM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 2 5627 #define mmCM2_CM_BLNDGAM_RAMA_END_CNTL1_B 0x106a 5628 #define mmCM2_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX 2 5629 #define mmCM2_CM_BLNDGAM_RAMA_END_CNTL2_B 0x106b 5630 #define mmCM2_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX 2 5631 #define mmCM2_CM_BLNDGAM_RAMA_END_CNTL1_G 0x106c 5632 #define mmCM2_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX 2 5633 #define mmCM2_CM_BLNDGAM_RAMA_END_CNTL2_G 0x106d 5634 #define mmCM2_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX 2 5635 #define mmCM2_CM_BLNDGAM_RAMA_END_CNTL1_R 0x106e 5636 #define mmCM2_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX 2 5637 #define mmCM2_CM_BLNDGAM_RAMA_END_CNTL2_R 0x106f 5638 #define mmCM2_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX 2 5639 #define mmCM2_CM_BLNDGAM_RAMA_OFFSET_B 0x1070 5640 #define mmCM2_CM_BLNDGAM_RAMA_OFFSET_B_BASE_IDX 2 5641 #define mmCM2_CM_BLNDGAM_RAMA_OFFSET_G 0x1071 5642 #define mmCM2_CM_BLNDGAM_RAMA_OFFSET_G_BASE_IDX 2 5643 #define mmCM2_CM_BLNDGAM_RAMA_OFFSET_R 0x1072 5644 #define mmCM2_CM_BLNDGAM_RAMA_OFFSET_R_BASE_IDX 2 5645 #define mmCM2_CM_BLNDGAM_RAMA_REGION_0_1 0x1073 5646 #define mmCM2_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX 2 5647 #define mmCM2_CM_BLNDGAM_RAMA_REGION_2_3 0x1074 5648 #define mmCM2_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX 2 5649 #define mmCM2_CM_BLNDGAM_RAMA_REGION_4_5 0x1075 5650 #define mmCM2_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX 2 5651 #define mmCM2_CM_BLNDGAM_RAMA_REGION_6_7 0x1076 5652 #define mmCM2_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX 2 5653 #define mmCM2_CM_BLNDGAM_RAMA_REGION_8_9 0x1077 5654 #define mmCM2_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX 2 5655 #define mmCM2_CM_BLNDGAM_RAMA_REGION_10_11 0x1078 5656 #define mmCM2_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX 2 5657 #define mmCM2_CM_BLNDGAM_RAMA_REGION_12_13 0x1079 5658 #define mmCM2_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX 2 5659 #define mmCM2_CM_BLNDGAM_RAMA_REGION_14_15 0x107a 5660 #define mmCM2_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX 2 5661 #define mmCM2_CM_BLNDGAM_RAMA_REGION_16_17 0x107b 5662 #define mmCM2_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX 2 5663 #define mmCM2_CM_BLNDGAM_RAMA_REGION_18_19 0x107c 5664 #define mmCM2_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX 2 5665 #define mmCM2_CM_BLNDGAM_RAMA_REGION_20_21 0x107d 5666 #define mmCM2_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX 2 5667 #define mmCM2_CM_BLNDGAM_RAMA_REGION_22_23 0x107e 5668 #define mmCM2_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX 2 5669 #define mmCM2_CM_BLNDGAM_RAMA_REGION_24_25 0x107f 5670 #define mmCM2_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX 2 5671 #define mmCM2_CM_BLNDGAM_RAMA_REGION_26_27 0x1080 5672 #define mmCM2_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX 2 5673 #define mmCM2_CM_BLNDGAM_RAMA_REGION_28_29 0x1081 5674 #define mmCM2_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX 2 5675 #define mmCM2_CM_BLNDGAM_RAMA_REGION_30_31 0x1082 5676 #define mmCM2_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX 2 5677 #define mmCM2_CM_BLNDGAM_RAMA_REGION_32_33 0x1083 5678 #define mmCM2_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX 2 5679 #define mmCM2_CM_BLNDGAM_RAMB_START_CNTL_B 0x1084 5680 #define mmCM2_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX 2 5681 #define mmCM2_CM_BLNDGAM_RAMB_START_CNTL_G 0x1085 5682 #define mmCM2_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX 2 5683 #define mmCM2_CM_BLNDGAM_RAMB_START_CNTL_R 0x1086 5684 #define mmCM2_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX 2 5685 #define mmCM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B 0x1087 5686 #define mmCM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 5687 #define mmCM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G 0x1088 5688 #define mmCM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 5689 #define mmCM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R 0x1089 5690 #define mmCM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 5691 #define mmCM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_B 0x108a 5692 #define mmCM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 2 5693 #define mmCM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_G 0x108b 5694 #define mmCM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 2 5695 #define mmCM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_R 0x108c 5696 #define mmCM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 2 5697 #define mmCM2_CM_BLNDGAM_RAMB_END_CNTL1_B 0x108d 5698 #define mmCM2_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX 2 5699 #define mmCM2_CM_BLNDGAM_RAMB_END_CNTL2_B 0x108e 5700 #define mmCM2_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX 2 5701 #define mmCM2_CM_BLNDGAM_RAMB_END_CNTL1_G 0x108f 5702 #define mmCM2_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX 2 5703 #define mmCM2_CM_BLNDGAM_RAMB_END_CNTL2_G 0x1090 5704 #define mmCM2_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX 2 5705 #define mmCM2_CM_BLNDGAM_RAMB_END_CNTL1_R 0x1091 5706 #define mmCM2_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX 2 5707 #define mmCM2_CM_BLNDGAM_RAMB_END_CNTL2_R 0x1092 5708 #define mmCM2_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX 2 5709 #define mmCM2_CM_BLNDGAM_RAMB_OFFSET_B 0x1093 5710 #define mmCM2_CM_BLNDGAM_RAMB_OFFSET_B_BASE_IDX 2 5711 #define mmCM2_CM_BLNDGAM_RAMB_OFFSET_G 0x1094 5712 #define mmCM2_CM_BLNDGAM_RAMB_OFFSET_G_BASE_IDX 2 5713 #define mmCM2_CM_BLNDGAM_RAMB_OFFSET_R 0x1095 5714 #define mmCM2_CM_BLNDGAM_RAMB_OFFSET_R_BASE_IDX 2 5715 #define mmCM2_CM_BLNDGAM_RAMB_REGION_0_1 0x1096 5716 #define mmCM2_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX 2 5717 #define mmCM2_CM_BLNDGAM_RAMB_REGION_2_3 0x1097 5718 #define mmCM2_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX 2 5719 #define mmCM2_CM_BLNDGAM_RAMB_REGION_4_5 0x1098 5720 #define mmCM2_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX 2 5721 #define mmCM2_CM_BLNDGAM_RAMB_REGION_6_7 0x1099 5722 #define mmCM2_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX 2 5723 #define mmCM2_CM_BLNDGAM_RAMB_REGION_8_9 0x109a 5724 #define mmCM2_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX 2 5725 #define mmCM2_CM_BLNDGAM_RAMB_REGION_10_11 0x109b 5726 #define mmCM2_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX 2 5727 #define mmCM2_CM_BLNDGAM_RAMB_REGION_12_13 0x109c 5728 #define mmCM2_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX 2 5729 #define mmCM2_CM_BLNDGAM_RAMB_REGION_14_15 0x109d 5730 #define mmCM2_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX 2 5731 #define mmCM2_CM_BLNDGAM_RAMB_REGION_16_17 0x109e 5732 #define mmCM2_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX 2 5733 #define mmCM2_CM_BLNDGAM_RAMB_REGION_18_19 0x109f 5734 #define mmCM2_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX 2 5735 #define mmCM2_CM_BLNDGAM_RAMB_REGION_20_21 0x10a0 5736 #define mmCM2_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX 2 5737 #define mmCM2_CM_BLNDGAM_RAMB_REGION_22_23 0x10a1 5738 #define mmCM2_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX 2 5739 #define mmCM2_CM_BLNDGAM_RAMB_REGION_24_25 0x10a2 5740 #define mmCM2_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX 2 5741 #define mmCM2_CM_BLNDGAM_RAMB_REGION_26_27 0x10a3 5742 #define mmCM2_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX 2 5743 #define mmCM2_CM_BLNDGAM_RAMB_REGION_28_29 0x10a4 5744 #define mmCM2_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX 2 5745 #define mmCM2_CM_BLNDGAM_RAMB_REGION_30_31 0x10a5 5746 #define mmCM2_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX 2 5747 #define mmCM2_CM_BLNDGAM_RAMB_REGION_32_33 0x10a6 5748 #define mmCM2_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX 2 5749 #define mmCM2_CM_HDR_MULT_COEF 0x10a7 5750 #define mmCM2_CM_HDR_MULT_COEF_BASE_IDX 2 5751 #define mmCM2_CM_MEM_PWR_CTRL 0x10a8 5752 #define mmCM2_CM_MEM_PWR_CTRL_BASE_IDX 2 5753 #define mmCM2_CM_MEM_PWR_STATUS 0x10a9 5754 #define mmCM2_CM_MEM_PWR_STATUS_BASE_IDX 2 5755 #define mmCM2_CM_DEALPHA 0x10ab 5756 #define mmCM2_CM_DEALPHA_BASE_IDX 2 5757 #define mmCM2_CM_COEF_FORMAT 0x10ac 5758 #define mmCM2_CM_COEF_FORMAT_BASE_IDX 2 5759 #define mmCM2_CM_SHAPER_CONTROL 0x10ad 5760 #define mmCM2_CM_SHAPER_CONTROL_BASE_IDX 2 5761 #define mmCM2_CM_SHAPER_OFFSET_R 0x10ae 5762 #define mmCM2_CM_SHAPER_OFFSET_R_BASE_IDX 2 5763 #define mmCM2_CM_SHAPER_OFFSET_G 0x10af 5764 #define mmCM2_CM_SHAPER_OFFSET_G_BASE_IDX 2 5765 #define mmCM2_CM_SHAPER_OFFSET_B 0x10b0 5766 #define mmCM2_CM_SHAPER_OFFSET_B_BASE_IDX 2 5767 #define mmCM2_CM_SHAPER_SCALE_R 0x10b1 5768 #define mmCM2_CM_SHAPER_SCALE_R_BASE_IDX 2 5769 #define mmCM2_CM_SHAPER_SCALE_G_B 0x10b2 5770 #define mmCM2_CM_SHAPER_SCALE_G_B_BASE_IDX 2 5771 #define mmCM2_CM_SHAPER_LUT_INDEX 0x10b3 5772 #define mmCM2_CM_SHAPER_LUT_INDEX_BASE_IDX 2 5773 #define mmCM2_CM_SHAPER_LUT_DATA 0x10b4 5774 #define mmCM2_CM_SHAPER_LUT_DATA_BASE_IDX 2 5775 #define mmCM2_CM_SHAPER_LUT_WRITE_EN_MASK 0x10b5 5776 #define mmCM2_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 2 5777 #define mmCM2_CM_SHAPER_RAMA_START_CNTL_B 0x10b6 5778 #define mmCM2_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 2 5779 #define mmCM2_CM_SHAPER_RAMA_START_CNTL_G 0x10b7 5780 #define mmCM2_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 2 5781 #define mmCM2_CM_SHAPER_RAMA_START_CNTL_R 0x10b8 5782 #define mmCM2_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 2 5783 #define mmCM2_CM_SHAPER_RAMA_END_CNTL_B 0x10b9 5784 #define mmCM2_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 2 5785 #define mmCM2_CM_SHAPER_RAMA_END_CNTL_G 0x10ba 5786 #define mmCM2_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 2 5787 #define mmCM2_CM_SHAPER_RAMA_END_CNTL_R 0x10bb 5788 #define mmCM2_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 2 5789 #define mmCM2_CM_SHAPER_RAMA_REGION_0_1 0x10bc 5790 #define mmCM2_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX 2 5791 #define mmCM2_CM_SHAPER_RAMA_REGION_2_3 0x10bd 5792 #define mmCM2_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX 2 5793 #define mmCM2_CM_SHAPER_RAMA_REGION_4_5 0x10be 5794 #define mmCM2_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX 2 5795 #define mmCM2_CM_SHAPER_RAMA_REGION_6_7 0x10bf 5796 #define mmCM2_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX 2 5797 #define mmCM2_CM_SHAPER_RAMA_REGION_8_9 0x10c0 5798 #define mmCM2_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX 2 5799 #define mmCM2_CM_SHAPER_RAMA_REGION_10_11 0x10c1 5800 #define mmCM2_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX 2 5801 #define mmCM2_CM_SHAPER_RAMA_REGION_12_13 0x10c2 5802 #define mmCM2_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX 2 5803 #define mmCM2_CM_SHAPER_RAMA_REGION_14_15 0x10c3 5804 #define mmCM2_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX 2 5805 #define mmCM2_CM_SHAPER_RAMA_REGION_16_17 0x10c4 5806 #define mmCM2_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX 2 5807 #define mmCM2_CM_SHAPER_RAMA_REGION_18_19 0x10c5 5808 #define mmCM2_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX 2 5809 #define mmCM2_CM_SHAPER_RAMA_REGION_20_21 0x10c6 5810 #define mmCM2_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX 2 5811 #define mmCM2_CM_SHAPER_RAMA_REGION_22_23 0x10c7 5812 #define mmCM2_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX 2 5813 #define mmCM2_CM_SHAPER_RAMA_REGION_24_25 0x10c8 5814 #define mmCM2_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX 2 5815 #define mmCM2_CM_SHAPER_RAMA_REGION_26_27 0x10c9 5816 #define mmCM2_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX 2 5817 #define mmCM2_CM_SHAPER_RAMA_REGION_28_29 0x10ca 5818 #define mmCM2_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX 2 5819 #define mmCM2_CM_SHAPER_RAMA_REGION_30_31 0x10cb 5820 #define mmCM2_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX 2 5821 #define mmCM2_CM_SHAPER_RAMA_REGION_32_33 0x10cc 5822 #define mmCM2_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX 2 5823 #define mmCM2_CM_SHAPER_RAMB_START_CNTL_B 0x10cd 5824 #define mmCM2_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 2 5825 #define mmCM2_CM_SHAPER_RAMB_START_CNTL_G 0x10ce 5826 #define mmCM2_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 2 5827 #define mmCM2_CM_SHAPER_RAMB_START_CNTL_R 0x10cf 5828 #define mmCM2_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 2 5829 #define mmCM2_CM_SHAPER_RAMB_END_CNTL_B 0x10d0 5830 #define mmCM2_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 2 5831 #define mmCM2_CM_SHAPER_RAMB_END_CNTL_G 0x10d1 5832 #define mmCM2_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 2 5833 #define mmCM2_CM_SHAPER_RAMB_END_CNTL_R 0x10d2 5834 #define mmCM2_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 2 5835 #define mmCM2_CM_SHAPER_RAMB_REGION_0_1 0x10d3 5836 #define mmCM2_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX 2 5837 #define mmCM2_CM_SHAPER_RAMB_REGION_2_3 0x10d4 5838 #define mmCM2_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX 2 5839 #define mmCM2_CM_SHAPER_RAMB_REGION_4_5 0x10d5 5840 #define mmCM2_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX 2 5841 #define mmCM2_CM_SHAPER_RAMB_REGION_6_7 0x10d6 5842 #define mmCM2_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX 2 5843 #define mmCM2_CM_SHAPER_RAMB_REGION_8_9 0x10d7 5844 #define mmCM2_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX 2 5845 #define mmCM2_CM_SHAPER_RAMB_REGION_10_11 0x10d8 5846 #define mmCM2_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX 2 5847 #define mmCM2_CM_SHAPER_RAMB_REGION_12_13 0x10d9 5848 #define mmCM2_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX 2 5849 #define mmCM2_CM_SHAPER_RAMB_REGION_14_15 0x10da 5850 #define mmCM2_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX 2 5851 #define mmCM2_CM_SHAPER_RAMB_REGION_16_17 0x10db 5852 #define mmCM2_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX 2 5853 #define mmCM2_CM_SHAPER_RAMB_REGION_18_19 0x10dc 5854 #define mmCM2_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX 2 5855 #define mmCM2_CM_SHAPER_RAMB_REGION_20_21 0x10dd 5856 #define mmCM2_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX 2 5857 #define mmCM2_CM_SHAPER_RAMB_REGION_22_23 0x10de 5858 #define mmCM2_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX 2 5859 #define mmCM2_CM_SHAPER_RAMB_REGION_24_25 0x10df 5860 #define mmCM2_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX 2 5861 #define mmCM2_CM_SHAPER_RAMB_REGION_26_27 0x10e0 5862 #define mmCM2_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX 2 5863 #define mmCM2_CM_SHAPER_RAMB_REGION_28_29 0x10e1 5864 #define mmCM2_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX 2 5865 #define mmCM2_CM_SHAPER_RAMB_REGION_30_31 0x10e2 5866 #define mmCM2_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX 2 5867 #define mmCM2_CM_SHAPER_RAMB_REGION_32_33 0x10e3 5868 #define mmCM2_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX 2 5869 #define mmCM2_CM_MEM_PWR_CTRL2 0x10e4 5870 #define mmCM2_CM_MEM_PWR_CTRL2_BASE_IDX 2 5871 #define mmCM2_CM_MEM_PWR_STATUS2 0x10e5 5872 #define mmCM2_CM_MEM_PWR_STATUS2_BASE_IDX 2 5873 #define mmCM2_CM_3DLUT_MODE 0x10e6 5874 #define mmCM2_CM_3DLUT_MODE_BASE_IDX 2 5875 #define mmCM2_CM_3DLUT_INDEX 0x10e7 5876 #define mmCM2_CM_3DLUT_INDEX_BASE_IDX 2 5877 #define mmCM2_CM_3DLUT_DATA 0x10e8 5878 #define mmCM2_CM_3DLUT_DATA_BASE_IDX 2 5879 #define mmCM2_CM_3DLUT_DATA_30BIT 0x10e9 5880 #define mmCM2_CM_3DLUT_DATA_30BIT_BASE_IDX 2 5881 #define mmCM2_CM_3DLUT_READ_WRITE_CONTROL 0x10ea 5882 #define mmCM2_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 2 5883 #define mmCM2_CM_3DLUT_OUT_NORM_FACTOR 0x10eb 5884 #define mmCM2_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 2 5885 #define mmCM2_CM_3DLUT_OUT_OFFSET_R 0x10ec 5886 #define mmCM2_CM_3DLUT_OUT_OFFSET_R_BASE_IDX 2 5887 #define mmCM2_CM_3DLUT_OUT_OFFSET_G 0x10ed 5888 #define mmCM2_CM_3DLUT_OUT_OFFSET_G_BASE_IDX 2 5889 #define mmCM2_CM_3DLUT_OUT_OFFSET_B 0x10ee 5890 #define mmCM2_CM_3DLUT_OUT_OFFSET_B_BASE_IDX 2 5891 5892 5893 // addressBlock: dce_dc_dpp2_dispdec_dpp_dcperfmon_dc_perfmon_dispdec 5894 // base address: 0x43e8 5895 #define mmDC_PERFMON14_PERFCOUNTER_CNTL 0x10fa 5896 #define mmDC_PERFMON14_PERFCOUNTER_CNTL_BASE_IDX 2 5897 #define mmDC_PERFMON14_PERFCOUNTER_CNTL2 0x10fb 5898 #define mmDC_PERFMON14_PERFCOUNTER_CNTL2_BASE_IDX 2 5899 #define mmDC_PERFMON14_PERFCOUNTER_STATE 0x10fc 5900 #define mmDC_PERFMON14_PERFCOUNTER_STATE_BASE_IDX 2 5901 #define mmDC_PERFMON14_PERFMON_CNTL 0x10fd 5902 #define mmDC_PERFMON14_PERFMON_CNTL_BASE_IDX 2 5903 #define mmDC_PERFMON14_PERFMON_CNTL2 0x10fe 5904 #define mmDC_PERFMON14_PERFMON_CNTL2_BASE_IDX 2 5905 #define mmDC_PERFMON14_PERFMON_CVALUE_INT_MISC 0x10ff 5906 #define mmDC_PERFMON14_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 5907 #define mmDC_PERFMON14_PERFMON_CVALUE_LOW 0x1100 5908 #define mmDC_PERFMON14_PERFMON_CVALUE_LOW_BASE_IDX 2 5909 #define mmDC_PERFMON14_PERFMON_HI 0x1101 5910 #define mmDC_PERFMON14_PERFMON_HI_BASE_IDX 2 5911 #define mmDC_PERFMON14_PERFMON_LOW 0x1102 5912 #define mmDC_PERFMON14_PERFMON_LOW_BASE_IDX 2 5913 5914 5915 // addressBlock: dce_dc_dpp3_dispdec_dpp_top_dispdec 5916 // base address: 0x1104 5917 #define mmDPP_TOP3_DPP_CONTROL 0x1106 5918 #define mmDPP_TOP3_DPP_CONTROL_BASE_IDX 2 5919 #define mmDPP_TOP3_DPP_SOFT_RESET 0x1107 5920 #define mmDPP_TOP3_DPP_SOFT_RESET_BASE_IDX 2 5921 #define mmDPP_TOP3_DPP_CRC_VAL_R_G 0x1108 5922 #define mmDPP_TOP3_DPP_CRC_VAL_R_G_BASE_IDX 2 5923 #define mmDPP_TOP3_DPP_CRC_VAL_B_A 0x1109 5924 #define mmDPP_TOP3_DPP_CRC_VAL_B_A_BASE_IDX 2 5925 #define mmDPP_TOP3_DPP_CRC_CTRL 0x110a 5926 #define mmDPP_TOP3_DPP_CRC_CTRL_BASE_IDX 2 5927 #define mmDPP_TOP3_HOST_READ_CONTROL 0x110b 5928 #define mmDPP_TOP3_HOST_READ_CONTROL_BASE_IDX 2 5929 5930 5931 // addressBlock: dce_dc_dpp3_dispdec_cnvc_cfg_dispdec 5932 // base address: 0x1104 5933 #define mmCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT 0x1110 5934 #define mmCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2 5935 #define mmCNVC_CFG3_FORMAT_CONTROL 0x1111 5936 #define mmCNVC_CFG3_FORMAT_CONTROL_BASE_IDX 2 5937 #define mmCNVC_CFG3_FCNV_FP_BIAS_R 0x1112 5938 #define mmCNVC_CFG3_FCNV_FP_BIAS_R_BASE_IDX 2 5939 #define mmCNVC_CFG3_FCNV_FP_BIAS_G 0x1113 5940 #define mmCNVC_CFG3_FCNV_FP_BIAS_G_BASE_IDX 2 5941 #define mmCNVC_CFG3_FCNV_FP_BIAS_B 0x1114 5942 #define mmCNVC_CFG3_FCNV_FP_BIAS_B_BASE_IDX 2 5943 #define mmCNVC_CFG3_FCNV_FP_SCALE_R 0x1115 5944 #define mmCNVC_CFG3_FCNV_FP_SCALE_R_BASE_IDX 2 5945 #define mmCNVC_CFG3_FCNV_FP_SCALE_G 0x1116 5946 #define mmCNVC_CFG3_FCNV_FP_SCALE_G_BASE_IDX 2 5947 #define mmCNVC_CFG3_FCNV_FP_SCALE_B 0x1117 5948 #define mmCNVC_CFG3_FCNV_FP_SCALE_B_BASE_IDX 2 5949 #define mmCNVC_CFG3_COLOR_KEYER_CONTROL 0x1118 5950 #define mmCNVC_CFG3_COLOR_KEYER_CONTROL_BASE_IDX 2 5951 #define mmCNVC_CFG3_COLOR_KEYER_ALPHA 0x1119 5952 #define mmCNVC_CFG3_COLOR_KEYER_ALPHA_BASE_IDX 2 5953 #define mmCNVC_CFG3_COLOR_KEYER_RED 0x111a 5954 #define mmCNVC_CFG3_COLOR_KEYER_RED_BASE_IDX 2 5955 #define mmCNVC_CFG3_COLOR_KEYER_GREEN 0x111b 5956 #define mmCNVC_CFG3_COLOR_KEYER_GREEN_BASE_IDX 2 5957 #define mmCNVC_CFG3_COLOR_KEYER_BLUE 0x111c 5958 #define mmCNVC_CFG3_COLOR_KEYER_BLUE_BASE_IDX 2 5959 #define mmCNVC_CFG3_ALPHA_2BIT_LUT 0x111e 5960 #define mmCNVC_CFG3_ALPHA_2BIT_LUT_BASE_IDX 2 5961 #define mmCNVC_CFG3_PRE_DEALPHA 0x111f 5962 #define mmCNVC_CFG3_PRE_DEALPHA_BASE_IDX 2 5963 #define mmCNVC_CFG3_PRE_CSC_MODE 0x1120 5964 #define mmCNVC_CFG3_PRE_CSC_MODE_BASE_IDX 2 5965 #define mmCNVC_CFG3_PRE_CSC_C11_C12 0x1121 5966 #define mmCNVC_CFG3_PRE_CSC_C11_C12_BASE_IDX 2 5967 #define mmCNVC_CFG3_PRE_CSC_C13_C14 0x1122 5968 #define mmCNVC_CFG3_PRE_CSC_C13_C14_BASE_IDX 2 5969 #define mmCNVC_CFG3_PRE_CSC_C21_C22 0x1123 5970 #define mmCNVC_CFG3_PRE_CSC_C21_C22_BASE_IDX 2 5971 #define mmCNVC_CFG3_PRE_CSC_C23_C24 0x1124 5972 #define mmCNVC_CFG3_PRE_CSC_C23_C24_BASE_IDX 2 5973 #define mmCNVC_CFG3_PRE_CSC_C31_C32 0x1125 5974 #define mmCNVC_CFG3_PRE_CSC_C31_C32_BASE_IDX 2 5975 #define mmCNVC_CFG3_PRE_CSC_C33_C34 0x1126 5976 #define mmCNVC_CFG3_PRE_CSC_C33_C34_BASE_IDX 2 5977 #define mmCNVC_CFG3_PRE_CSC_B_C11_C12 0x1127 5978 #define mmCNVC_CFG3_PRE_CSC_B_C11_C12_BASE_IDX 2 5979 #define mmCNVC_CFG3_PRE_CSC_B_C13_C14 0x1128 5980 #define mmCNVC_CFG3_PRE_CSC_B_C13_C14_BASE_IDX 2 5981 #define mmCNVC_CFG3_PRE_CSC_B_C21_C22 0x1129 5982 #define mmCNVC_CFG3_PRE_CSC_B_C21_C22_BASE_IDX 2 5983 #define mmCNVC_CFG3_PRE_CSC_B_C23_C24 0x112a 5984 #define mmCNVC_CFG3_PRE_CSC_B_C23_C24_BASE_IDX 2 5985 #define mmCNVC_CFG3_PRE_CSC_B_C31_C32 0x112b 5986 #define mmCNVC_CFG3_PRE_CSC_B_C31_C32_BASE_IDX 2 5987 #define mmCNVC_CFG3_PRE_CSC_B_C33_C34 0x112c 5988 #define mmCNVC_CFG3_PRE_CSC_B_C33_C34_BASE_IDX 2 5989 #define mmCNVC_CFG3_CNVC_COEF_FORMAT 0x112d 5990 #define mmCNVC_CFG3_CNVC_COEF_FORMAT_BASE_IDX 2 5991 #define mmCNVC_CFG3_PRE_DEGAM 0x112e 5992 #define mmCNVC_CFG3_PRE_DEGAM_BASE_IDX 2 5993 #define mmCNVC_CFG3_PRE_REALPHA 0x112f 5994 #define mmCNVC_CFG3_PRE_REALPHA_BASE_IDX 2 5995 5996 5997 // addressBlock: dce_dc_dpp3_dispdec_cnvc_cur_dispdec 5998 // base address: 0x1104 5999 #define mmCNVC_CUR3_CURSOR0_CONTROL 0x1132 6000 #define mmCNVC_CUR3_CURSOR0_CONTROL_BASE_IDX 2 6001 #define mmCNVC_CUR3_CURSOR0_COLOR0 0x1133 6002 #define mmCNVC_CUR3_CURSOR0_COLOR0_BASE_IDX 2 6003 #define mmCNVC_CUR3_CURSOR0_COLOR1 0x1134 6004 #define mmCNVC_CUR3_CURSOR0_COLOR1_BASE_IDX 2 6005 #define mmCNVC_CUR3_CURSOR0_FP_SCALE_BIAS 0x1135 6006 #define mmCNVC_CUR3_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2 6007 6008 6009 // addressBlock: dce_dc_dpp3_dispdec_dscl_dispdec 6010 // base address: 0x1104 6011 #define mmDSCL3_SCL_COEF_RAM_TAP_SELECT 0x113a 6012 #define mmDSCL3_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2 6013 #define mmDSCL3_SCL_COEF_RAM_TAP_DATA 0x113b 6014 #define mmDSCL3_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2 6015 #define mmDSCL3_SCL_MODE 0x113c 6016 #define mmDSCL3_SCL_MODE_BASE_IDX 2 6017 #define mmDSCL3_SCL_TAP_CONTROL 0x113d 6018 #define mmDSCL3_SCL_TAP_CONTROL_BASE_IDX 2 6019 #define mmDSCL3_DSCL_CONTROL 0x113e 6020 #define mmDSCL3_DSCL_CONTROL_BASE_IDX 2 6021 #define mmDSCL3_DSCL_2TAP_CONTROL 0x113f 6022 #define mmDSCL3_DSCL_2TAP_CONTROL_BASE_IDX 2 6023 #define mmDSCL3_SCL_MANUAL_REPLICATE_CONTROL 0x1140 6024 #define mmDSCL3_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 6025 #define mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO 0x1141 6026 #define mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 6027 #define mmDSCL3_SCL_HORZ_FILTER_INIT 0x1142 6028 #define mmDSCL3_SCL_HORZ_FILTER_INIT_BASE_IDX 2 6029 #define mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C 0x1143 6030 #define mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2 6031 #define mmDSCL3_SCL_HORZ_FILTER_INIT_C 0x1144 6032 #define mmDSCL3_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2 6033 #define mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO 0x1145 6034 #define mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 6035 #define mmDSCL3_SCL_VERT_FILTER_INIT 0x1146 6036 #define mmDSCL3_SCL_VERT_FILTER_INIT_BASE_IDX 2 6037 #define mmDSCL3_SCL_VERT_FILTER_INIT_BOT 0x1147 6038 #define mmDSCL3_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2 6039 #define mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C 0x1148 6040 #define mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2 6041 #define mmDSCL3_SCL_VERT_FILTER_INIT_C 0x1149 6042 #define mmDSCL3_SCL_VERT_FILTER_INIT_C_BASE_IDX 2 6043 #define mmDSCL3_SCL_VERT_FILTER_INIT_BOT_C 0x114a 6044 #define mmDSCL3_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2 6045 #define mmDSCL3_SCL_BLACK_COLOR 0x114b 6046 #define mmDSCL3_SCL_BLACK_COLOR_BASE_IDX 2 6047 #define mmDSCL3_DSCL_UPDATE 0x114c 6048 #define mmDSCL3_DSCL_UPDATE_BASE_IDX 2 6049 #define mmDSCL3_DSCL_AUTOCAL 0x114d 6050 #define mmDSCL3_DSCL_AUTOCAL_BASE_IDX 2 6051 #define mmDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x114e 6052 #define mmDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 6053 #define mmDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x114f 6054 #define mmDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 6055 #define mmDSCL3_OTG_H_BLANK 0x1150 6056 #define mmDSCL3_OTG_H_BLANK_BASE_IDX 2 6057 #define mmDSCL3_OTG_V_BLANK 0x1151 6058 #define mmDSCL3_OTG_V_BLANK_BASE_IDX 2 6059 #define mmDSCL3_RECOUT_START 0x1152 6060 #define mmDSCL3_RECOUT_START_BASE_IDX 2 6061 #define mmDSCL3_RECOUT_SIZE 0x1153 6062 #define mmDSCL3_RECOUT_SIZE_BASE_IDX 2 6063 #define mmDSCL3_MPC_SIZE 0x1154 6064 #define mmDSCL3_MPC_SIZE_BASE_IDX 2 6065 #define mmDSCL3_LB_DATA_FORMAT 0x1155 6066 #define mmDSCL3_LB_DATA_FORMAT_BASE_IDX 2 6067 #define mmDSCL3_LB_MEMORY_CTRL 0x1156 6068 #define mmDSCL3_LB_MEMORY_CTRL_BASE_IDX 2 6069 #define mmDSCL3_LB_V_COUNTER 0x1157 6070 #define mmDSCL3_LB_V_COUNTER_BASE_IDX 2 6071 #define mmDSCL3_DSCL_MEM_PWR_CTRL 0x1158 6072 #define mmDSCL3_DSCL_MEM_PWR_CTRL_BASE_IDX 2 6073 #define mmDSCL3_DSCL_MEM_PWR_STATUS 0x1159 6074 #define mmDSCL3_DSCL_MEM_PWR_STATUS_BASE_IDX 2 6075 #define mmDSCL3_OBUF_CONTROL 0x115a 6076 #define mmDSCL3_OBUF_CONTROL_BASE_IDX 2 6077 #define mmDSCL3_OBUF_MEM_PWR_CTRL 0x115b 6078 #define mmDSCL3_OBUF_MEM_PWR_CTRL_BASE_IDX 2 6079 6080 6081 // addressBlock: dce_dc_dpp3_dispdec_cm_dispdec 6082 // base address: 0x1104 6083 #define mmCM3_CM_CONTROL 0x1161 6084 #define mmCM3_CM_CONTROL_BASE_IDX 2 6085 #define mmCM3_CM_POST_CSC_CONTROL 0x1162 6086 #define mmCM3_CM_POST_CSC_CONTROL_BASE_IDX 2 6087 #define mmCM3_CM_POST_CSC_C11_C12 0x1163 6088 #define mmCM3_CM_POST_CSC_C11_C12_BASE_IDX 2 6089 #define mmCM3_CM_POST_CSC_C13_C14 0x1164 6090 #define mmCM3_CM_POST_CSC_C13_C14_BASE_IDX 2 6091 #define mmCM3_CM_POST_CSC_C21_C22 0x1165 6092 #define mmCM3_CM_POST_CSC_C21_C22_BASE_IDX 2 6093 #define mmCM3_CM_POST_CSC_C23_C24 0x1166 6094 #define mmCM3_CM_POST_CSC_C23_C24_BASE_IDX 2 6095 #define mmCM3_CM_POST_CSC_C31_C32 0x1167 6096 #define mmCM3_CM_POST_CSC_C31_C32_BASE_IDX 2 6097 #define mmCM3_CM_POST_CSC_C33_C34 0x1168 6098 #define mmCM3_CM_POST_CSC_C33_C34_BASE_IDX 2 6099 #define mmCM3_CM_POST_CSC_B_C11_C12 0x1169 6100 #define mmCM3_CM_POST_CSC_B_C11_C12_BASE_IDX 2 6101 #define mmCM3_CM_POST_CSC_B_C13_C14 0x116a 6102 #define mmCM3_CM_POST_CSC_B_C13_C14_BASE_IDX 2 6103 #define mmCM3_CM_POST_CSC_B_C21_C22 0x116b 6104 #define mmCM3_CM_POST_CSC_B_C21_C22_BASE_IDX 2 6105 #define mmCM3_CM_POST_CSC_B_C23_C24 0x116c 6106 #define mmCM3_CM_POST_CSC_B_C23_C24_BASE_IDX 2 6107 #define mmCM3_CM_POST_CSC_B_C31_C32 0x116d 6108 #define mmCM3_CM_POST_CSC_B_C31_C32_BASE_IDX 2 6109 #define mmCM3_CM_POST_CSC_B_C33_C34 0x116e 6110 #define mmCM3_CM_POST_CSC_B_C33_C34_BASE_IDX 2 6111 #define mmCM3_CM_GAMUT_REMAP_CONTROL 0x116f 6112 #define mmCM3_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2 6113 #define mmCM3_CM_GAMUT_REMAP_C11_C12 0x1170 6114 #define mmCM3_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2 6115 #define mmCM3_CM_GAMUT_REMAP_C13_C14 0x1171 6116 #define mmCM3_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2 6117 #define mmCM3_CM_GAMUT_REMAP_C21_C22 0x1172 6118 #define mmCM3_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2 6119 #define mmCM3_CM_GAMUT_REMAP_C23_C24 0x1173 6120 #define mmCM3_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2 6121 #define mmCM3_CM_GAMUT_REMAP_C31_C32 0x1174 6122 #define mmCM3_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2 6123 #define mmCM3_CM_GAMUT_REMAP_C33_C34 0x1175 6124 #define mmCM3_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2 6125 #define mmCM3_CM_GAMUT_REMAP_B_C11_C12 0x1176 6126 #define mmCM3_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX 2 6127 #define mmCM3_CM_GAMUT_REMAP_B_C13_C14 0x1177 6128 #define mmCM3_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX 2 6129 #define mmCM3_CM_GAMUT_REMAP_B_C21_C22 0x1178 6130 #define mmCM3_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX 2 6131 #define mmCM3_CM_GAMUT_REMAP_B_C23_C24 0x1179 6132 #define mmCM3_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX 2 6133 #define mmCM3_CM_GAMUT_REMAP_B_C31_C32 0x117a 6134 #define mmCM3_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX 2 6135 #define mmCM3_CM_GAMUT_REMAP_B_C33_C34 0x117b 6136 #define mmCM3_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX 2 6137 #define mmCM3_CM_BIAS_CR_R 0x117c 6138 #define mmCM3_CM_BIAS_CR_R_BASE_IDX 2 6139 #define mmCM3_CM_BIAS_Y_G_CB_B 0x117d 6140 #define mmCM3_CM_BIAS_Y_G_CB_B_BASE_IDX 2 6141 #define mmCM3_CM_GAMCOR_CONTROL 0x117e 6142 #define mmCM3_CM_GAMCOR_CONTROL_BASE_IDX 2 6143 #define mmCM3_CM_GAMCOR_LUT_INDEX 0x117f 6144 #define mmCM3_CM_GAMCOR_LUT_INDEX_BASE_IDX 2 6145 #define mmCM3_CM_GAMCOR_LUT_DATA 0x1180 6146 #define mmCM3_CM_GAMCOR_LUT_DATA_BASE_IDX 2 6147 #define mmCM3_CM_GAMCOR_LUT_CONTROL 0x1181 6148 #define mmCM3_CM_GAMCOR_LUT_CONTROL_BASE_IDX 2 6149 #define mmCM3_CM_GAMCOR_RAMA_START_CNTL_B 0x1182 6150 #define mmCM3_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX 2 6151 #define mmCM3_CM_GAMCOR_RAMA_START_CNTL_G 0x1183 6152 #define mmCM3_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX 2 6153 #define mmCM3_CM_GAMCOR_RAMA_START_CNTL_R 0x1184 6154 #define mmCM3_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX 2 6155 #define mmCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B 0x1185 6156 #define mmCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 6157 #define mmCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G 0x1186 6158 #define mmCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 6159 #define mmCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R 0x1187 6160 #define mmCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 6161 #define mmCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_B 0x1188 6162 #define mmCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX 2 6163 #define mmCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_G 0x1189 6164 #define mmCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX 2 6165 #define mmCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_R 0x118a 6166 #define mmCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX 2 6167 #define mmCM3_CM_GAMCOR_RAMA_END_CNTL1_B 0x118b 6168 #define mmCM3_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX 2 6169 #define mmCM3_CM_GAMCOR_RAMA_END_CNTL2_B 0x118c 6170 #define mmCM3_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX 2 6171 #define mmCM3_CM_GAMCOR_RAMA_END_CNTL1_G 0x118d 6172 #define mmCM3_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX 2 6173 #define mmCM3_CM_GAMCOR_RAMA_END_CNTL2_G 0x118e 6174 #define mmCM3_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX 2 6175 #define mmCM3_CM_GAMCOR_RAMA_END_CNTL1_R 0x118f 6176 #define mmCM3_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX 2 6177 #define mmCM3_CM_GAMCOR_RAMA_END_CNTL2_R 0x1190 6178 #define mmCM3_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX 2 6179 #define mmCM3_CM_GAMCOR_RAMA_OFFSET_B 0x1191 6180 #define mmCM3_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX 2 6181 #define mmCM3_CM_GAMCOR_RAMA_OFFSET_G 0x1192 6182 #define mmCM3_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX 2 6183 #define mmCM3_CM_GAMCOR_RAMA_OFFSET_R 0x1193 6184 #define mmCM3_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX 2 6185 #define mmCM3_CM_GAMCOR_RAMA_REGION_0_1 0x1194 6186 #define mmCM3_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX 2 6187 #define mmCM3_CM_GAMCOR_RAMA_REGION_2_3 0x1195 6188 #define mmCM3_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX 2 6189 #define mmCM3_CM_GAMCOR_RAMA_REGION_4_5 0x1196 6190 #define mmCM3_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX 2 6191 #define mmCM3_CM_GAMCOR_RAMA_REGION_6_7 0x1197 6192 #define mmCM3_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX 2 6193 #define mmCM3_CM_GAMCOR_RAMA_REGION_8_9 0x1198 6194 #define mmCM3_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX 2 6195 #define mmCM3_CM_GAMCOR_RAMA_REGION_10_11 0x1199 6196 #define mmCM3_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX 2 6197 #define mmCM3_CM_GAMCOR_RAMA_REGION_12_13 0x119a 6198 #define mmCM3_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX 2 6199 #define mmCM3_CM_GAMCOR_RAMA_REGION_14_15 0x119b 6200 #define mmCM3_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX 2 6201 #define mmCM3_CM_GAMCOR_RAMA_REGION_16_17 0x119c 6202 #define mmCM3_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX 2 6203 #define mmCM3_CM_GAMCOR_RAMA_REGION_18_19 0x119d 6204 #define mmCM3_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX 2 6205 #define mmCM3_CM_GAMCOR_RAMA_REGION_20_21 0x119e 6206 #define mmCM3_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX 2 6207 #define mmCM3_CM_GAMCOR_RAMA_REGION_22_23 0x119f 6208 #define mmCM3_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX 2 6209 #define mmCM3_CM_GAMCOR_RAMA_REGION_24_25 0x11a0 6210 #define mmCM3_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX 2 6211 #define mmCM3_CM_GAMCOR_RAMA_REGION_26_27 0x11a1 6212 #define mmCM3_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX 2 6213 #define mmCM3_CM_GAMCOR_RAMA_REGION_28_29 0x11a2 6214 #define mmCM3_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX 2 6215 #define mmCM3_CM_GAMCOR_RAMA_REGION_30_31 0x11a3 6216 #define mmCM3_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX 2 6217 #define mmCM3_CM_GAMCOR_RAMA_REGION_32_33 0x11a4 6218 #define mmCM3_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX 2 6219 #define mmCM3_CM_GAMCOR_RAMB_START_CNTL_B 0x11a5 6220 #define mmCM3_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX 2 6221 #define mmCM3_CM_GAMCOR_RAMB_START_CNTL_G 0x11a6 6222 #define mmCM3_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX 2 6223 #define mmCM3_CM_GAMCOR_RAMB_START_CNTL_R 0x11a7 6224 #define mmCM3_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX 2 6225 #define mmCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B 0x11a8 6226 #define mmCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 6227 #define mmCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G 0x11a9 6228 #define mmCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 6229 #define mmCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R 0x11aa 6230 #define mmCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 6231 #define mmCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_B 0x11ab 6232 #define mmCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX 2 6233 #define mmCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_G 0x11ac 6234 #define mmCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX 2 6235 #define mmCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_R 0x11ad 6236 #define mmCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX 2 6237 #define mmCM3_CM_GAMCOR_RAMB_END_CNTL1_B 0x11ae 6238 #define mmCM3_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX 2 6239 #define mmCM3_CM_GAMCOR_RAMB_END_CNTL2_B 0x11af 6240 #define mmCM3_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX 2 6241 #define mmCM3_CM_GAMCOR_RAMB_END_CNTL1_G 0x11b0 6242 #define mmCM3_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX 2 6243 #define mmCM3_CM_GAMCOR_RAMB_END_CNTL2_G 0x11b1 6244 #define mmCM3_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX 2 6245 #define mmCM3_CM_GAMCOR_RAMB_END_CNTL1_R 0x11b2 6246 #define mmCM3_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX 2 6247 #define mmCM3_CM_GAMCOR_RAMB_END_CNTL2_R 0x11b3 6248 #define mmCM3_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX 2 6249 #define mmCM3_CM_GAMCOR_RAMB_OFFSET_B 0x11b4 6250 #define mmCM3_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX 2 6251 #define mmCM3_CM_GAMCOR_RAMB_OFFSET_G 0x11b5 6252 #define mmCM3_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX 2 6253 #define mmCM3_CM_GAMCOR_RAMB_OFFSET_R 0x11b6 6254 #define mmCM3_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX 2 6255 #define mmCM3_CM_GAMCOR_RAMB_REGION_0_1 0x11b7 6256 #define mmCM3_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX 2 6257 #define mmCM3_CM_GAMCOR_RAMB_REGION_2_3 0x11b8 6258 #define mmCM3_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX 2 6259 #define mmCM3_CM_GAMCOR_RAMB_REGION_4_5 0x11b9 6260 #define mmCM3_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX 2 6261 #define mmCM3_CM_GAMCOR_RAMB_REGION_6_7 0x11ba 6262 #define mmCM3_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX 2 6263 #define mmCM3_CM_GAMCOR_RAMB_REGION_8_9 0x11bb 6264 #define mmCM3_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX 2 6265 #define mmCM3_CM_GAMCOR_RAMB_REGION_10_11 0x11bc 6266 #define mmCM3_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX 2 6267 #define mmCM3_CM_GAMCOR_RAMB_REGION_12_13 0x11bd 6268 #define mmCM3_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX 2 6269 #define mmCM3_CM_GAMCOR_RAMB_REGION_14_15 0x11be 6270 #define mmCM3_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX 2 6271 #define mmCM3_CM_GAMCOR_RAMB_REGION_16_17 0x11bf 6272 #define mmCM3_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX 2 6273 #define mmCM3_CM_GAMCOR_RAMB_REGION_18_19 0x11c0 6274 #define mmCM3_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX 2 6275 #define mmCM3_CM_GAMCOR_RAMB_REGION_20_21 0x11c1 6276 #define mmCM3_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX 2 6277 #define mmCM3_CM_GAMCOR_RAMB_REGION_22_23 0x11c2 6278 #define mmCM3_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX 2 6279 #define mmCM3_CM_GAMCOR_RAMB_REGION_24_25 0x11c3 6280 #define mmCM3_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX 2 6281 #define mmCM3_CM_GAMCOR_RAMB_REGION_26_27 0x11c4 6282 #define mmCM3_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX 2 6283 #define mmCM3_CM_GAMCOR_RAMB_REGION_28_29 0x11c5 6284 #define mmCM3_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX 2 6285 #define mmCM3_CM_GAMCOR_RAMB_REGION_30_31 0x11c6 6286 #define mmCM3_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX 2 6287 #define mmCM3_CM_GAMCOR_RAMB_REGION_32_33 0x11c7 6288 #define mmCM3_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX 2 6289 #define mmCM3_CM_BLNDGAM_CONTROL 0x11c8 6290 #define mmCM3_CM_BLNDGAM_CONTROL_BASE_IDX 2 6291 #define mmCM3_CM_BLNDGAM_LUT_INDEX 0x11c9 6292 #define mmCM3_CM_BLNDGAM_LUT_INDEX_BASE_IDX 2 6293 #define mmCM3_CM_BLNDGAM_LUT_DATA 0x11ca 6294 #define mmCM3_CM_BLNDGAM_LUT_DATA_BASE_IDX 2 6295 #define mmCM3_CM_BLNDGAM_LUT_CONTROL 0x11cb 6296 #define mmCM3_CM_BLNDGAM_LUT_CONTROL_BASE_IDX 2 6297 #define mmCM3_CM_BLNDGAM_RAMA_START_CNTL_B 0x11cc 6298 #define mmCM3_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX 2 6299 #define mmCM3_CM_BLNDGAM_RAMA_START_CNTL_G 0x11cd 6300 #define mmCM3_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX 2 6301 #define mmCM3_CM_BLNDGAM_RAMA_START_CNTL_R 0x11ce 6302 #define mmCM3_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX 2 6303 #define mmCM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B 0x11cf 6304 #define mmCM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 6305 #define mmCM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G 0x11d0 6306 #define mmCM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 6307 #define mmCM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R 0x11d1 6308 #define mmCM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 6309 #define mmCM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_B 0x11d2 6310 #define mmCM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 2 6311 #define mmCM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_G 0x11d3 6312 #define mmCM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 2 6313 #define mmCM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_R 0x11d4 6314 #define mmCM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 2 6315 #define mmCM3_CM_BLNDGAM_RAMA_END_CNTL1_B 0x11d5 6316 #define mmCM3_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX 2 6317 #define mmCM3_CM_BLNDGAM_RAMA_END_CNTL2_B 0x11d6 6318 #define mmCM3_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX 2 6319 #define mmCM3_CM_BLNDGAM_RAMA_END_CNTL1_G 0x11d7 6320 #define mmCM3_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX 2 6321 #define mmCM3_CM_BLNDGAM_RAMA_END_CNTL2_G 0x11d8 6322 #define mmCM3_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX 2 6323 #define mmCM3_CM_BLNDGAM_RAMA_END_CNTL1_R 0x11d9 6324 #define mmCM3_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX 2 6325 #define mmCM3_CM_BLNDGAM_RAMA_END_CNTL2_R 0x11da 6326 #define mmCM3_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX 2 6327 #define mmCM3_CM_BLNDGAM_RAMA_OFFSET_B 0x11db 6328 #define mmCM3_CM_BLNDGAM_RAMA_OFFSET_B_BASE_IDX 2 6329 #define mmCM3_CM_BLNDGAM_RAMA_OFFSET_G 0x11dc 6330 #define mmCM3_CM_BLNDGAM_RAMA_OFFSET_G_BASE_IDX 2 6331 #define mmCM3_CM_BLNDGAM_RAMA_OFFSET_R 0x11dd 6332 #define mmCM3_CM_BLNDGAM_RAMA_OFFSET_R_BASE_IDX 2 6333 #define mmCM3_CM_BLNDGAM_RAMA_REGION_0_1 0x11de 6334 #define mmCM3_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX 2 6335 #define mmCM3_CM_BLNDGAM_RAMA_REGION_2_3 0x11df 6336 #define mmCM3_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX 2 6337 #define mmCM3_CM_BLNDGAM_RAMA_REGION_4_5 0x11e0 6338 #define mmCM3_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX 2 6339 #define mmCM3_CM_BLNDGAM_RAMA_REGION_6_7 0x11e1 6340 #define mmCM3_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX 2 6341 #define mmCM3_CM_BLNDGAM_RAMA_REGION_8_9 0x11e2 6342 #define mmCM3_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX 2 6343 #define mmCM3_CM_BLNDGAM_RAMA_REGION_10_11 0x11e3 6344 #define mmCM3_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX 2 6345 #define mmCM3_CM_BLNDGAM_RAMA_REGION_12_13 0x11e4 6346 #define mmCM3_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX 2 6347 #define mmCM3_CM_BLNDGAM_RAMA_REGION_14_15 0x11e5 6348 #define mmCM3_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX 2 6349 #define mmCM3_CM_BLNDGAM_RAMA_REGION_16_17 0x11e6 6350 #define mmCM3_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX 2 6351 #define mmCM3_CM_BLNDGAM_RAMA_REGION_18_19 0x11e7 6352 #define mmCM3_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX 2 6353 #define mmCM3_CM_BLNDGAM_RAMA_REGION_20_21 0x11e8 6354 #define mmCM3_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX 2 6355 #define mmCM3_CM_BLNDGAM_RAMA_REGION_22_23 0x11e9 6356 #define mmCM3_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX 2 6357 #define mmCM3_CM_BLNDGAM_RAMA_REGION_24_25 0x11ea 6358 #define mmCM3_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX 2 6359 #define mmCM3_CM_BLNDGAM_RAMA_REGION_26_27 0x11eb 6360 #define mmCM3_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX 2 6361 #define mmCM3_CM_BLNDGAM_RAMA_REGION_28_29 0x11ec 6362 #define mmCM3_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX 2 6363 #define mmCM3_CM_BLNDGAM_RAMA_REGION_30_31 0x11ed 6364 #define mmCM3_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX 2 6365 #define mmCM3_CM_BLNDGAM_RAMA_REGION_32_33 0x11ee 6366 #define mmCM3_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX 2 6367 #define mmCM3_CM_BLNDGAM_RAMB_START_CNTL_B 0x11ef 6368 #define mmCM3_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX 2 6369 #define mmCM3_CM_BLNDGAM_RAMB_START_CNTL_G 0x11f0 6370 #define mmCM3_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX 2 6371 #define mmCM3_CM_BLNDGAM_RAMB_START_CNTL_R 0x11f1 6372 #define mmCM3_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX 2 6373 #define mmCM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B 0x11f2 6374 #define mmCM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 6375 #define mmCM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G 0x11f3 6376 #define mmCM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 6377 #define mmCM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R 0x11f4 6378 #define mmCM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 6379 #define mmCM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_B 0x11f5 6380 #define mmCM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 2 6381 #define mmCM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_G 0x11f6 6382 #define mmCM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 2 6383 #define mmCM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_R 0x11f7 6384 #define mmCM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 2 6385 #define mmCM3_CM_BLNDGAM_RAMB_END_CNTL1_B 0x11f8 6386 #define mmCM3_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX 2 6387 #define mmCM3_CM_BLNDGAM_RAMB_END_CNTL2_B 0x11f9 6388 #define mmCM3_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX 2 6389 #define mmCM3_CM_BLNDGAM_RAMB_END_CNTL1_G 0x11fa 6390 #define mmCM3_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX 2 6391 #define mmCM3_CM_BLNDGAM_RAMB_END_CNTL2_G 0x11fb 6392 #define mmCM3_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX 2 6393 #define mmCM3_CM_BLNDGAM_RAMB_END_CNTL1_R 0x11fc 6394 #define mmCM3_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX 2 6395 #define mmCM3_CM_BLNDGAM_RAMB_END_CNTL2_R 0x11fd 6396 #define mmCM3_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX 2 6397 #define mmCM3_CM_BLNDGAM_RAMB_OFFSET_B 0x11fe 6398 #define mmCM3_CM_BLNDGAM_RAMB_OFFSET_B_BASE_IDX 2 6399 #define mmCM3_CM_BLNDGAM_RAMB_OFFSET_G 0x11ff 6400 #define mmCM3_CM_BLNDGAM_RAMB_OFFSET_G_BASE_IDX 2 6401 #define mmCM3_CM_BLNDGAM_RAMB_OFFSET_R 0x1200 6402 #define mmCM3_CM_BLNDGAM_RAMB_OFFSET_R_BASE_IDX 2 6403 #define mmCM3_CM_BLNDGAM_RAMB_REGION_0_1 0x1201 6404 #define mmCM3_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX 2 6405 #define mmCM3_CM_BLNDGAM_RAMB_REGION_2_3 0x1202 6406 #define mmCM3_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX 2 6407 #define mmCM3_CM_BLNDGAM_RAMB_REGION_4_5 0x1203 6408 #define mmCM3_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX 2 6409 #define mmCM3_CM_BLNDGAM_RAMB_REGION_6_7 0x1204 6410 #define mmCM3_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX 2 6411 #define mmCM3_CM_BLNDGAM_RAMB_REGION_8_9 0x1205 6412 #define mmCM3_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX 2 6413 #define mmCM3_CM_BLNDGAM_RAMB_REGION_10_11 0x1206 6414 #define mmCM3_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX 2 6415 #define mmCM3_CM_BLNDGAM_RAMB_REGION_12_13 0x1207 6416 #define mmCM3_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX 2 6417 #define mmCM3_CM_BLNDGAM_RAMB_REGION_14_15 0x1208 6418 #define mmCM3_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX 2 6419 #define mmCM3_CM_BLNDGAM_RAMB_REGION_16_17 0x1209 6420 #define mmCM3_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX 2 6421 #define mmCM3_CM_BLNDGAM_RAMB_REGION_18_19 0x120a 6422 #define mmCM3_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX 2 6423 #define mmCM3_CM_BLNDGAM_RAMB_REGION_20_21 0x120b 6424 #define mmCM3_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX 2 6425 #define mmCM3_CM_BLNDGAM_RAMB_REGION_22_23 0x120c 6426 #define mmCM3_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX 2 6427 #define mmCM3_CM_BLNDGAM_RAMB_REGION_24_25 0x120d 6428 #define mmCM3_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX 2 6429 #define mmCM3_CM_BLNDGAM_RAMB_REGION_26_27 0x120e 6430 #define mmCM3_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX 2 6431 #define mmCM3_CM_BLNDGAM_RAMB_REGION_28_29 0x120f 6432 #define mmCM3_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX 2 6433 #define mmCM3_CM_BLNDGAM_RAMB_REGION_30_31 0x1210 6434 #define mmCM3_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX 2 6435 #define mmCM3_CM_BLNDGAM_RAMB_REGION_32_33 0x1211 6436 #define mmCM3_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX 2 6437 #define mmCM3_CM_HDR_MULT_COEF 0x1212 6438 #define mmCM3_CM_HDR_MULT_COEF_BASE_IDX 2 6439 #define mmCM3_CM_MEM_PWR_CTRL 0x1213 6440 #define mmCM3_CM_MEM_PWR_CTRL_BASE_IDX 2 6441 #define mmCM3_CM_MEM_PWR_STATUS 0x1214 6442 #define mmCM3_CM_MEM_PWR_STATUS_BASE_IDX 2 6443 #define mmCM3_CM_DEALPHA 0x1216 6444 #define mmCM3_CM_DEALPHA_BASE_IDX 2 6445 #define mmCM3_CM_COEF_FORMAT 0x1217 6446 #define mmCM3_CM_COEF_FORMAT_BASE_IDX 2 6447 #define mmCM3_CM_SHAPER_CONTROL 0x1218 6448 #define mmCM3_CM_SHAPER_CONTROL_BASE_IDX 2 6449 #define mmCM3_CM_SHAPER_OFFSET_R 0x1219 6450 #define mmCM3_CM_SHAPER_OFFSET_R_BASE_IDX 2 6451 #define mmCM3_CM_SHAPER_OFFSET_G 0x121a 6452 #define mmCM3_CM_SHAPER_OFFSET_G_BASE_IDX 2 6453 #define mmCM3_CM_SHAPER_OFFSET_B 0x121b 6454 #define mmCM3_CM_SHAPER_OFFSET_B_BASE_IDX 2 6455 #define mmCM3_CM_SHAPER_SCALE_R 0x121c 6456 #define mmCM3_CM_SHAPER_SCALE_R_BASE_IDX 2 6457 #define mmCM3_CM_SHAPER_SCALE_G_B 0x121d 6458 #define mmCM3_CM_SHAPER_SCALE_G_B_BASE_IDX 2 6459 #define mmCM3_CM_SHAPER_LUT_INDEX 0x121e 6460 #define mmCM3_CM_SHAPER_LUT_INDEX_BASE_IDX 2 6461 #define mmCM3_CM_SHAPER_LUT_DATA 0x121f 6462 #define mmCM3_CM_SHAPER_LUT_DATA_BASE_IDX 2 6463 #define mmCM3_CM_SHAPER_LUT_WRITE_EN_MASK 0x1220 6464 #define mmCM3_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 2 6465 #define mmCM3_CM_SHAPER_RAMA_START_CNTL_B 0x1221 6466 #define mmCM3_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 2 6467 #define mmCM3_CM_SHAPER_RAMA_START_CNTL_G 0x1222 6468 #define mmCM3_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 2 6469 #define mmCM3_CM_SHAPER_RAMA_START_CNTL_R 0x1223 6470 #define mmCM3_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 2 6471 #define mmCM3_CM_SHAPER_RAMA_END_CNTL_B 0x1224 6472 #define mmCM3_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 2 6473 #define mmCM3_CM_SHAPER_RAMA_END_CNTL_G 0x1225 6474 #define mmCM3_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 2 6475 #define mmCM3_CM_SHAPER_RAMA_END_CNTL_R 0x1226 6476 #define mmCM3_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 2 6477 #define mmCM3_CM_SHAPER_RAMA_REGION_0_1 0x1227 6478 #define mmCM3_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX 2 6479 #define mmCM3_CM_SHAPER_RAMA_REGION_2_3 0x1228 6480 #define mmCM3_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX 2 6481 #define mmCM3_CM_SHAPER_RAMA_REGION_4_5 0x1229 6482 #define mmCM3_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX 2 6483 #define mmCM3_CM_SHAPER_RAMA_REGION_6_7 0x122a 6484 #define mmCM3_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX 2 6485 #define mmCM3_CM_SHAPER_RAMA_REGION_8_9 0x122b 6486 #define mmCM3_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX 2 6487 #define mmCM3_CM_SHAPER_RAMA_REGION_10_11 0x122c 6488 #define mmCM3_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX 2 6489 #define mmCM3_CM_SHAPER_RAMA_REGION_12_13 0x122d 6490 #define mmCM3_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX 2 6491 #define mmCM3_CM_SHAPER_RAMA_REGION_14_15 0x122e 6492 #define mmCM3_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX 2 6493 #define mmCM3_CM_SHAPER_RAMA_REGION_16_17 0x122f 6494 #define mmCM3_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX 2 6495 #define mmCM3_CM_SHAPER_RAMA_REGION_18_19 0x1230 6496 #define mmCM3_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX 2 6497 #define mmCM3_CM_SHAPER_RAMA_REGION_20_21 0x1231 6498 #define mmCM3_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX 2 6499 #define mmCM3_CM_SHAPER_RAMA_REGION_22_23 0x1232 6500 #define mmCM3_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX 2 6501 #define mmCM3_CM_SHAPER_RAMA_REGION_24_25 0x1233 6502 #define mmCM3_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX 2 6503 #define mmCM3_CM_SHAPER_RAMA_REGION_26_27 0x1234 6504 #define mmCM3_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX 2 6505 #define mmCM3_CM_SHAPER_RAMA_REGION_28_29 0x1235 6506 #define mmCM3_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX 2 6507 #define mmCM3_CM_SHAPER_RAMA_REGION_30_31 0x1236 6508 #define mmCM3_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX 2 6509 #define mmCM3_CM_SHAPER_RAMA_REGION_32_33 0x1237 6510 #define mmCM3_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX 2 6511 #define mmCM3_CM_SHAPER_RAMB_START_CNTL_B 0x1238 6512 #define mmCM3_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 2 6513 #define mmCM3_CM_SHAPER_RAMB_START_CNTL_G 0x1239 6514 #define mmCM3_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 2 6515 #define mmCM3_CM_SHAPER_RAMB_START_CNTL_R 0x123a 6516 #define mmCM3_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 2 6517 #define mmCM3_CM_SHAPER_RAMB_END_CNTL_B 0x123b 6518 #define mmCM3_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 2 6519 #define mmCM3_CM_SHAPER_RAMB_END_CNTL_G 0x123c 6520 #define mmCM3_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 2 6521 #define mmCM3_CM_SHAPER_RAMB_END_CNTL_R 0x123d 6522 #define mmCM3_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 2 6523 #define mmCM3_CM_SHAPER_RAMB_REGION_0_1 0x123e 6524 #define mmCM3_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX 2 6525 #define mmCM3_CM_SHAPER_RAMB_REGION_2_3 0x123f 6526 #define mmCM3_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX 2 6527 #define mmCM3_CM_SHAPER_RAMB_REGION_4_5 0x1240 6528 #define mmCM3_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX 2 6529 #define mmCM3_CM_SHAPER_RAMB_REGION_6_7 0x1241 6530 #define mmCM3_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX 2 6531 #define mmCM3_CM_SHAPER_RAMB_REGION_8_9 0x1242 6532 #define mmCM3_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX 2 6533 #define mmCM3_CM_SHAPER_RAMB_REGION_10_11 0x1243 6534 #define mmCM3_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX 2 6535 #define mmCM3_CM_SHAPER_RAMB_REGION_12_13 0x1244 6536 #define mmCM3_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX 2 6537 #define mmCM3_CM_SHAPER_RAMB_REGION_14_15 0x1245 6538 #define mmCM3_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX 2 6539 #define mmCM3_CM_SHAPER_RAMB_REGION_16_17 0x1246 6540 #define mmCM3_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX 2 6541 #define mmCM3_CM_SHAPER_RAMB_REGION_18_19 0x1247 6542 #define mmCM3_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX 2 6543 #define mmCM3_CM_SHAPER_RAMB_REGION_20_21 0x1248 6544 #define mmCM3_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX 2 6545 #define mmCM3_CM_SHAPER_RAMB_REGION_22_23 0x1249 6546 #define mmCM3_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX 2 6547 #define mmCM3_CM_SHAPER_RAMB_REGION_24_25 0x124a 6548 #define mmCM3_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX 2 6549 #define mmCM3_CM_SHAPER_RAMB_REGION_26_27 0x124b 6550 #define mmCM3_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX 2 6551 #define mmCM3_CM_SHAPER_RAMB_REGION_28_29 0x124c 6552 #define mmCM3_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX 2 6553 #define mmCM3_CM_SHAPER_RAMB_REGION_30_31 0x124d 6554 #define mmCM3_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX 2 6555 #define mmCM3_CM_SHAPER_RAMB_REGION_32_33 0x124e 6556 #define mmCM3_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX 2 6557 #define mmCM3_CM_MEM_PWR_CTRL2 0x124f 6558 #define mmCM3_CM_MEM_PWR_CTRL2_BASE_IDX 2 6559 #define mmCM3_CM_MEM_PWR_STATUS2 0x1250 6560 #define mmCM3_CM_MEM_PWR_STATUS2_BASE_IDX 2 6561 #define mmCM3_CM_3DLUT_MODE 0x1251 6562 #define mmCM3_CM_3DLUT_MODE_BASE_IDX 2 6563 #define mmCM3_CM_3DLUT_INDEX 0x1252 6564 #define mmCM3_CM_3DLUT_INDEX_BASE_IDX 2 6565 #define mmCM3_CM_3DLUT_DATA 0x1253 6566 #define mmCM3_CM_3DLUT_DATA_BASE_IDX 2 6567 #define mmCM3_CM_3DLUT_DATA_30BIT 0x1254 6568 #define mmCM3_CM_3DLUT_DATA_30BIT_BASE_IDX 2 6569 #define mmCM3_CM_3DLUT_READ_WRITE_CONTROL 0x1255 6570 #define mmCM3_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 2 6571 #define mmCM3_CM_3DLUT_OUT_NORM_FACTOR 0x1256 6572 #define mmCM3_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 2 6573 #define mmCM3_CM_3DLUT_OUT_OFFSET_R 0x1257 6574 #define mmCM3_CM_3DLUT_OUT_OFFSET_R_BASE_IDX 2 6575 #define mmCM3_CM_3DLUT_OUT_OFFSET_G 0x1258 6576 #define mmCM3_CM_3DLUT_OUT_OFFSET_G_BASE_IDX 2 6577 #define mmCM3_CM_3DLUT_OUT_OFFSET_B 0x1259 6578 #define mmCM3_CM_3DLUT_OUT_OFFSET_B_BASE_IDX 2 6579 6580 6581 // addressBlock: dce_dc_dpp3_dispdec_dpp_dcperfmon_dc_perfmon_dispdec 6582 // base address: 0x4994 6583 #define mmDC_PERFMON15_PERFCOUNTER_CNTL 0x1265 6584 #define mmDC_PERFMON15_PERFCOUNTER_CNTL_BASE_IDX 2 6585 #define mmDC_PERFMON15_PERFCOUNTER_CNTL2 0x1266 6586 #define mmDC_PERFMON15_PERFCOUNTER_CNTL2_BASE_IDX 2 6587 #define mmDC_PERFMON15_PERFCOUNTER_STATE 0x1267 6588 #define mmDC_PERFMON15_PERFCOUNTER_STATE_BASE_IDX 2 6589 #define mmDC_PERFMON15_PERFMON_CNTL 0x1268 6590 #define mmDC_PERFMON15_PERFMON_CNTL_BASE_IDX 2 6591 #define mmDC_PERFMON15_PERFMON_CNTL2 0x1269 6592 #define mmDC_PERFMON15_PERFMON_CNTL2_BASE_IDX 2 6593 #define mmDC_PERFMON15_PERFMON_CVALUE_INT_MISC 0x126a 6594 #define mmDC_PERFMON15_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 6595 #define mmDC_PERFMON15_PERFMON_CVALUE_LOW 0x126b 6596 #define mmDC_PERFMON15_PERFMON_CVALUE_LOW_BASE_IDX 2 6597 #define mmDC_PERFMON15_PERFMON_HI 0x126c 6598 #define mmDC_PERFMON15_PERFMON_HI_BASE_IDX 2 6599 #define mmDC_PERFMON15_PERFMON_LOW 0x126d 6600 #define mmDC_PERFMON15_PERFMON_LOW_BASE_IDX 2 6601 6602 6603 // addressBlock: dce_dc_dpp4_dispdec_dpp_top_dispdec 6604 // base address: 0x16b0 6605 #define mmDPP_TOP4_DPP_CONTROL 0x1271 6606 #define mmDPP_TOP4_DPP_CONTROL_BASE_IDX 2 6607 #define mmDPP_TOP4_DPP_SOFT_RESET 0x1272 6608 #define mmDPP_TOP4_DPP_SOFT_RESET_BASE_IDX 2 6609 #define mmDPP_TOP4_DPP_CRC_VAL_R_G 0x1273 6610 #define mmDPP_TOP4_DPP_CRC_VAL_R_G_BASE_IDX 2 6611 #define mmDPP_TOP4_DPP_CRC_VAL_B_A 0x1274 6612 #define mmDPP_TOP4_DPP_CRC_VAL_B_A_BASE_IDX 2 6613 #define mmDPP_TOP4_DPP_CRC_CTRL 0x1275 6614 #define mmDPP_TOP4_DPP_CRC_CTRL_BASE_IDX 2 6615 #define mmDPP_TOP4_HOST_READ_CONTROL 0x1276 6616 #define mmDPP_TOP4_HOST_READ_CONTROL_BASE_IDX 2 6617 6618 6619 // addressBlock: dce_dc_dpp4_dispdec_cnvc_cfg_dispdec 6620 // base address: 0x16b0 6621 #define mmCNVC_CFG4_CNVC_SURFACE_PIXEL_FORMAT 0x127b 6622 #define mmCNVC_CFG4_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2 6623 #define mmCNVC_CFG4_FORMAT_CONTROL 0x127c 6624 #define mmCNVC_CFG4_FORMAT_CONTROL_BASE_IDX 2 6625 #define mmCNVC_CFG4_FCNV_FP_BIAS_R 0x127d 6626 #define mmCNVC_CFG4_FCNV_FP_BIAS_R_BASE_IDX 2 6627 #define mmCNVC_CFG4_FCNV_FP_BIAS_G 0x127e 6628 #define mmCNVC_CFG4_FCNV_FP_BIAS_G_BASE_IDX 2 6629 #define mmCNVC_CFG4_FCNV_FP_BIAS_B 0x127f 6630 #define mmCNVC_CFG4_FCNV_FP_BIAS_B_BASE_IDX 2 6631 #define mmCNVC_CFG4_FCNV_FP_SCALE_R 0x1280 6632 #define mmCNVC_CFG4_FCNV_FP_SCALE_R_BASE_IDX 2 6633 #define mmCNVC_CFG4_FCNV_FP_SCALE_G 0x1281 6634 #define mmCNVC_CFG4_FCNV_FP_SCALE_G_BASE_IDX 2 6635 #define mmCNVC_CFG4_FCNV_FP_SCALE_B 0x1282 6636 #define mmCNVC_CFG4_FCNV_FP_SCALE_B_BASE_IDX 2 6637 #define mmCNVC_CFG4_COLOR_KEYER_CONTROL 0x1283 6638 #define mmCNVC_CFG4_COLOR_KEYER_CONTROL_BASE_IDX 2 6639 #define mmCNVC_CFG4_COLOR_KEYER_ALPHA 0x1284 6640 #define mmCNVC_CFG4_COLOR_KEYER_ALPHA_BASE_IDX 2 6641 #define mmCNVC_CFG4_COLOR_KEYER_RED 0x1285 6642 #define mmCNVC_CFG4_COLOR_KEYER_RED_BASE_IDX 2 6643 #define mmCNVC_CFG4_COLOR_KEYER_GREEN 0x1286 6644 #define mmCNVC_CFG4_COLOR_KEYER_GREEN_BASE_IDX 2 6645 #define mmCNVC_CFG4_COLOR_KEYER_BLUE 0x1287 6646 #define mmCNVC_CFG4_COLOR_KEYER_BLUE_BASE_IDX 2 6647 #define mmCNVC_CFG4_ALPHA_2BIT_LUT 0x1289 6648 #define mmCNVC_CFG4_ALPHA_2BIT_LUT_BASE_IDX 2 6649 #define mmCNVC_CFG4_PRE_DEALPHA 0x128a 6650 #define mmCNVC_CFG4_PRE_DEALPHA_BASE_IDX 2 6651 #define mmCNVC_CFG4_PRE_CSC_MODE 0x128b 6652 #define mmCNVC_CFG4_PRE_CSC_MODE_BASE_IDX 2 6653 #define mmCNVC_CFG4_PRE_CSC_C11_C12 0x128c 6654 #define mmCNVC_CFG4_PRE_CSC_C11_C12_BASE_IDX 2 6655 #define mmCNVC_CFG4_PRE_CSC_C13_C14 0x128d 6656 #define mmCNVC_CFG4_PRE_CSC_C13_C14_BASE_IDX 2 6657 #define mmCNVC_CFG4_PRE_CSC_C21_C22 0x128e 6658 #define mmCNVC_CFG4_PRE_CSC_C21_C22_BASE_IDX 2 6659 #define mmCNVC_CFG4_PRE_CSC_C23_C24 0x128f 6660 #define mmCNVC_CFG4_PRE_CSC_C23_C24_BASE_IDX 2 6661 #define mmCNVC_CFG4_PRE_CSC_C31_C32 0x1290 6662 #define mmCNVC_CFG4_PRE_CSC_C31_C32_BASE_IDX 2 6663 #define mmCNVC_CFG4_PRE_CSC_C33_C34 0x1291 6664 #define mmCNVC_CFG4_PRE_CSC_C33_C34_BASE_IDX 2 6665 #define mmCNVC_CFG4_PRE_CSC_B_C11_C12 0x1292 6666 #define mmCNVC_CFG4_PRE_CSC_B_C11_C12_BASE_IDX 2 6667 #define mmCNVC_CFG4_PRE_CSC_B_C13_C14 0x1293 6668 #define mmCNVC_CFG4_PRE_CSC_B_C13_C14_BASE_IDX 2 6669 #define mmCNVC_CFG4_PRE_CSC_B_C21_C22 0x1294 6670 #define mmCNVC_CFG4_PRE_CSC_B_C21_C22_BASE_IDX 2 6671 #define mmCNVC_CFG4_PRE_CSC_B_C23_C24 0x1295 6672 #define mmCNVC_CFG4_PRE_CSC_B_C23_C24_BASE_IDX 2 6673 #define mmCNVC_CFG4_PRE_CSC_B_C31_C32 0x1296 6674 #define mmCNVC_CFG4_PRE_CSC_B_C31_C32_BASE_IDX 2 6675 #define mmCNVC_CFG4_PRE_CSC_B_C33_C34 0x1297 6676 #define mmCNVC_CFG4_PRE_CSC_B_C33_C34_BASE_IDX 2 6677 #define mmCNVC_CFG4_CNVC_COEF_FORMAT 0x1298 6678 #define mmCNVC_CFG4_CNVC_COEF_FORMAT_BASE_IDX 2 6679 #define mmCNVC_CFG4_PRE_DEGAM 0x1299 6680 #define mmCNVC_CFG4_PRE_DEGAM_BASE_IDX 2 6681 #define mmCNVC_CFG4_PRE_REALPHA 0x129a 6682 #define mmCNVC_CFG4_PRE_REALPHA_BASE_IDX 2 6683 6684 6685 // addressBlock: dce_dc_dpp4_dispdec_cnvc_cur_dispdec 6686 // base address: 0x16b0 6687 #define mmCNVC_CUR4_CURSOR0_CONTROL 0x129d 6688 #define mmCNVC_CUR4_CURSOR0_CONTROL_BASE_IDX 2 6689 #define mmCNVC_CUR4_CURSOR0_COLOR0 0x129e 6690 #define mmCNVC_CUR4_CURSOR0_COLOR0_BASE_IDX 2 6691 #define mmCNVC_CUR4_CURSOR0_COLOR1 0x129f 6692 #define mmCNVC_CUR4_CURSOR0_COLOR1_BASE_IDX 2 6693 #define mmCNVC_CUR4_CURSOR0_FP_SCALE_BIAS 0x12a0 6694 #define mmCNVC_CUR4_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2 6695 6696 6697 // addressBlock: dce_dc_dpp4_dispdec_dscl_dispdec 6698 // base address: 0x16b0 6699 #define mmDSCL4_SCL_COEF_RAM_TAP_SELECT 0x12a5 6700 #define mmDSCL4_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2 6701 #define mmDSCL4_SCL_COEF_RAM_TAP_DATA 0x12a6 6702 #define mmDSCL4_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2 6703 #define mmDSCL4_SCL_MODE 0x12a7 6704 #define mmDSCL4_SCL_MODE_BASE_IDX 2 6705 #define mmDSCL4_SCL_TAP_CONTROL 0x12a8 6706 #define mmDSCL4_SCL_TAP_CONTROL_BASE_IDX 2 6707 #define mmDSCL4_DSCL_CONTROL 0x12a9 6708 #define mmDSCL4_DSCL_CONTROL_BASE_IDX 2 6709 #define mmDSCL4_DSCL_2TAP_CONTROL 0x12aa 6710 #define mmDSCL4_DSCL_2TAP_CONTROL_BASE_IDX 2 6711 #define mmDSCL4_SCL_MANUAL_REPLICATE_CONTROL 0x12ab 6712 #define mmDSCL4_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 6713 #define mmDSCL4_SCL_HORZ_FILTER_SCALE_RATIO 0x12ac 6714 #define mmDSCL4_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 6715 #define mmDSCL4_SCL_HORZ_FILTER_INIT 0x12ad 6716 #define mmDSCL4_SCL_HORZ_FILTER_INIT_BASE_IDX 2 6717 #define mmDSCL4_SCL_HORZ_FILTER_SCALE_RATIO_C 0x12ae 6718 #define mmDSCL4_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2 6719 #define mmDSCL4_SCL_HORZ_FILTER_INIT_C 0x12af 6720 #define mmDSCL4_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2 6721 #define mmDSCL4_SCL_VERT_FILTER_SCALE_RATIO 0x12b0 6722 #define mmDSCL4_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 6723 #define mmDSCL4_SCL_VERT_FILTER_INIT 0x12b1 6724 #define mmDSCL4_SCL_VERT_FILTER_INIT_BASE_IDX 2 6725 #define mmDSCL4_SCL_VERT_FILTER_INIT_BOT 0x12b2 6726 #define mmDSCL4_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2 6727 #define mmDSCL4_SCL_VERT_FILTER_SCALE_RATIO_C 0x12b3 6728 #define mmDSCL4_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2 6729 #define mmDSCL4_SCL_VERT_FILTER_INIT_C 0x12b4 6730 #define mmDSCL4_SCL_VERT_FILTER_INIT_C_BASE_IDX 2 6731 #define mmDSCL4_SCL_VERT_FILTER_INIT_BOT_C 0x12b5 6732 #define mmDSCL4_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2 6733 #define mmDSCL4_SCL_BLACK_COLOR 0x12b6 6734 #define mmDSCL4_SCL_BLACK_COLOR_BASE_IDX 2 6735 #define mmDSCL4_DSCL_UPDATE 0x12b7 6736 #define mmDSCL4_DSCL_UPDATE_BASE_IDX 2 6737 #define mmDSCL4_DSCL_AUTOCAL 0x12b8 6738 #define mmDSCL4_DSCL_AUTOCAL_BASE_IDX 2 6739 #define mmDSCL4_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x12b9 6740 #define mmDSCL4_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 6741 #define mmDSCL4_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x12ba 6742 #define mmDSCL4_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 6743 #define mmDSCL4_OTG_H_BLANK 0x12bb 6744 #define mmDSCL4_OTG_H_BLANK_BASE_IDX 2 6745 #define mmDSCL4_OTG_V_BLANK 0x12bc 6746 #define mmDSCL4_OTG_V_BLANK_BASE_IDX 2 6747 #define mmDSCL4_RECOUT_START 0x12bd 6748 #define mmDSCL4_RECOUT_START_BASE_IDX 2 6749 #define mmDSCL4_RECOUT_SIZE 0x12be 6750 #define mmDSCL4_RECOUT_SIZE_BASE_IDX 2 6751 #define mmDSCL4_MPC_SIZE 0x12bf 6752 #define mmDSCL4_MPC_SIZE_BASE_IDX 2 6753 #define mmDSCL4_LB_DATA_FORMAT 0x12c0 6754 #define mmDSCL4_LB_DATA_FORMAT_BASE_IDX 2 6755 #define mmDSCL4_LB_MEMORY_CTRL 0x12c1 6756 #define mmDSCL4_LB_MEMORY_CTRL_BASE_IDX 2 6757 #define mmDSCL4_LB_V_COUNTER 0x12c2 6758 #define mmDSCL4_LB_V_COUNTER_BASE_IDX 2 6759 #define mmDSCL4_DSCL_MEM_PWR_CTRL 0x12c3 6760 #define mmDSCL4_DSCL_MEM_PWR_CTRL_BASE_IDX 2 6761 #define mmDSCL4_DSCL_MEM_PWR_STATUS 0x12c4 6762 #define mmDSCL4_DSCL_MEM_PWR_STATUS_BASE_IDX 2 6763 #define mmDSCL4_OBUF_CONTROL 0x12c5 6764 #define mmDSCL4_OBUF_CONTROL_BASE_IDX 2 6765 #define mmDSCL4_OBUF_MEM_PWR_CTRL 0x12c6 6766 #define mmDSCL4_OBUF_MEM_PWR_CTRL_BASE_IDX 2 6767 6768 6769 // addressBlock: dce_dc_dpp4_dispdec_cm_dispdec 6770 // base address: 0x16b0 6771 #define mmCM4_CM_CONTROL 0x12cc 6772 #define mmCM4_CM_CONTROL_BASE_IDX 2 6773 #define mmCM4_CM_POST_CSC_CONTROL 0x12cd 6774 #define mmCM4_CM_POST_CSC_CONTROL_BASE_IDX 2 6775 #define mmCM4_CM_POST_CSC_C11_C12 0x12ce 6776 #define mmCM4_CM_POST_CSC_C11_C12_BASE_IDX 2 6777 #define mmCM4_CM_POST_CSC_C13_C14 0x12cf 6778 #define mmCM4_CM_POST_CSC_C13_C14_BASE_IDX 2 6779 #define mmCM4_CM_POST_CSC_C21_C22 0x12d0 6780 #define mmCM4_CM_POST_CSC_C21_C22_BASE_IDX 2 6781 #define mmCM4_CM_POST_CSC_C23_C24 0x12d1 6782 #define mmCM4_CM_POST_CSC_C23_C24_BASE_IDX 2 6783 #define mmCM4_CM_POST_CSC_C31_C32 0x12d2 6784 #define mmCM4_CM_POST_CSC_C31_C32_BASE_IDX 2 6785 #define mmCM4_CM_POST_CSC_C33_C34 0x12d3 6786 #define mmCM4_CM_POST_CSC_C33_C34_BASE_IDX 2 6787 #define mmCM4_CM_POST_CSC_B_C11_C12 0x12d4 6788 #define mmCM4_CM_POST_CSC_B_C11_C12_BASE_IDX 2 6789 #define mmCM4_CM_POST_CSC_B_C13_C14 0x12d5 6790 #define mmCM4_CM_POST_CSC_B_C13_C14_BASE_IDX 2 6791 #define mmCM4_CM_POST_CSC_B_C21_C22 0x12d6 6792 #define mmCM4_CM_POST_CSC_B_C21_C22_BASE_IDX 2 6793 #define mmCM4_CM_POST_CSC_B_C23_C24 0x12d7 6794 #define mmCM4_CM_POST_CSC_B_C23_C24_BASE_IDX 2 6795 #define mmCM4_CM_POST_CSC_B_C31_C32 0x12d8 6796 #define mmCM4_CM_POST_CSC_B_C31_C32_BASE_IDX 2 6797 #define mmCM4_CM_POST_CSC_B_C33_C34 0x12d9 6798 #define mmCM4_CM_POST_CSC_B_C33_C34_BASE_IDX 2 6799 #define mmCM4_CM_GAMUT_REMAP_CONTROL 0x12da 6800 #define mmCM4_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2 6801 #define mmCM4_CM_GAMUT_REMAP_C11_C12 0x12db 6802 #define mmCM4_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2 6803 #define mmCM4_CM_GAMUT_REMAP_C13_C14 0x12dc 6804 #define mmCM4_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2 6805 #define mmCM4_CM_GAMUT_REMAP_C21_C22 0x12dd 6806 #define mmCM4_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2 6807 #define mmCM4_CM_GAMUT_REMAP_C23_C24 0x12de 6808 #define mmCM4_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2 6809 #define mmCM4_CM_GAMUT_REMAP_C31_C32 0x12df 6810 #define mmCM4_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2 6811 #define mmCM4_CM_GAMUT_REMAP_C33_C34 0x12e0 6812 #define mmCM4_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2 6813 #define mmCM4_CM_GAMUT_REMAP_B_C11_C12 0x12e1 6814 #define mmCM4_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX 2 6815 #define mmCM4_CM_GAMUT_REMAP_B_C13_C14 0x12e2 6816 #define mmCM4_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX 2 6817 #define mmCM4_CM_GAMUT_REMAP_B_C21_C22 0x12e3 6818 #define mmCM4_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX 2 6819 #define mmCM4_CM_GAMUT_REMAP_B_C23_C24 0x12e4 6820 #define mmCM4_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX 2 6821 #define mmCM4_CM_GAMUT_REMAP_B_C31_C32 0x12e5 6822 #define mmCM4_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX 2 6823 #define mmCM4_CM_GAMUT_REMAP_B_C33_C34 0x12e6 6824 #define mmCM4_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX 2 6825 #define mmCM4_CM_BIAS_CR_R 0x12e7 6826 #define mmCM4_CM_BIAS_CR_R_BASE_IDX 2 6827 #define mmCM4_CM_BIAS_Y_G_CB_B 0x12e8 6828 #define mmCM4_CM_BIAS_Y_G_CB_B_BASE_IDX 2 6829 #define mmCM4_CM_GAMCOR_CONTROL 0x12e9 6830 #define mmCM4_CM_GAMCOR_CONTROL_BASE_IDX 2 6831 #define mmCM4_CM_GAMCOR_LUT_INDEX 0x12ea 6832 #define mmCM4_CM_GAMCOR_LUT_INDEX_BASE_IDX 2 6833 #define mmCM4_CM_GAMCOR_LUT_DATA 0x12eb 6834 #define mmCM4_CM_GAMCOR_LUT_DATA_BASE_IDX 2 6835 #define mmCM4_CM_GAMCOR_LUT_CONTROL 0x12ec 6836 #define mmCM4_CM_GAMCOR_LUT_CONTROL_BASE_IDX 2 6837 #define mmCM4_CM_GAMCOR_RAMA_START_CNTL_B 0x12ed 6838 #define mmCM4_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX 2 6839 #define mmCM4_CM_GAMCOR_RAMA_START_CNTL_G 0x12ee 6840 #define mmCM4_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX 2 6841 #define mmCM4_CM_GAMCOR_RAMA_START_CNTL_R 0x12ef 6842 #define mmCM4_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX 2 6843 #define mmCM4_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B 0x12f0 6844 #define mmCM4_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 6845 #define mmCM4_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G 0x12f1 6846 #define mmCM4_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 6847 #define mmCM4_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R 0x12f2 6848 #define mmCM4_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 6849 #define mmCM4_CM_GAMCOR_RAMA_START_BASE_CNTL_B 0x12f3 6850 #define mmCM4_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX 2 6851 #define mmCM4_CM_GAMCOR_RAMA_START_BASE_CNTL_G 0x12f4 6852 #define mmCM4_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX 2 6853 #define mmCM4_CM_GAMCOR_RAMA_START_BASE_CNTL_R 0x12f5 6854 #define mmCM4_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX 2 6855 #define mmCM4_CM_GAMCOR_RAMA_END_CNTL1_B 0x12f6 6856 #define mmCM4_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX 2 6857 #define mmCM4_CM_GAMCOR_RAMA_END_CNTL2_B 0x12f7 6858 #define mmCM4_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX 2 6859 #define mmCM4_CM_GAMCOR_RAMA_END_CNTL1_G 0x12f8 6860 #define mmCM4_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX 2 6861 #define mmCM4_CM_GAMCOR_RAMA_END_CNTL2_G 0x12f9 6862 #define mmCM4_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX 2 6863 #define mmCM4_CM_GAMCOR_RAMA_END_CNTL1_R 0x12fa 6864 #define mmCM4_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX 2 6865 #define mmCM4_CM_GAMCOR_RAMA_END_CNTL2_R 0x12fb 6866 #define mmCM4_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX 2 6867 #define mmCM4_CM_GAMCOR_RAMA_OFFSET_B 0x12fc 6868 #define mmCM4_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX 2 6869 #define mmCM4_CM_GAMCOR_RAMA_OFFSET_G 0x12fd 6870 #define mmCM4_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX 2 6871 #define mmCM4_CM_GAMCOR_RAMA_OFFSET_R 0x12fe 6872 #define mmCM4_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX 2 6873 #define mmCM4_CM_GAMCOR_RAMA_REGION_0_1 0x12ff 6874 #define mmCM4_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX 2 6875 #define mmCM4_CM_GAMCOR_RAMA_REGION_2_3 0x1300 6876 #define mmCM4_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX 2 6877 #define mmCM4_CM_GAMCOR_RAMA_REGION_4_5 0x1301 6878 #define mmCM4_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX 2 6879 #define mmCM4_CM_GAMCOR_RAMA_REGION_6_7 0x1302 6880 #define mmCM4_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX 2 6881 #define mmCM4_CM_GAMCOR_RAMA_REGION_8_9 0x1303 6882 #define mmCM4_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX 2 6883 #define mmCM4_CM_GAMCOR_RAMA_REGION_10_11 0x1304 6884 #define mmCM4_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX 2 6885 #define mmCM4_CM_GAMCOR_RAMA_REGION_12_13 0x1305 6886 #define mmCM4_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX 2 6887 #define mmCM4_CM_GAMCOR_RAMA_REGION_14_15 0x1306 6888 #define mmCM4_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX 2 6889 #define mmCM4_CM_GAMCOR_RAMA_REGION_16_17 0x1307 6890 #define mmCM4_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX 2 6891 #define mmCM4_CM_GAMCOR_RAMA_REGION_18_19 0x1308 6892 #define mmCM4_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX 2 6893 #define mmCM4_CM_GAMCOR_RAMA_REGION_20_21 0x1309 6894 #define mmCM4_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX 2 6895 #define mmCM4_CM_GAMCOR_RAMA_REGION_22_23 0x130a 6896 #define mmCM4_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX 2 6897 #define mmCM4_CM_GAMCOR_RAMA_REGION_24_25 0x130b 6898 #define mmCM4_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX 2 6899 #define mmCM4_CM_GAMCOR_RAMA_REGION_26_27 0x130c 6900 #define mmCM4_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX 2 6901 #define mmCM4_CM_GAMCOR_RAMA_REGION_28_29 0x130d 6902 #define mmCM4_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX 2 6903 #define mmCM4_CM_GAMCOR_RAMA_REGION_30_31 0x130e 6904 #define mmCM4_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX 2 6905 #define mmCM4_CM_GAMCOR_RAMA_REGION_32_33 0x130f 6906 #define mmCM4_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX 2 6907 #define mmCM4_CM_GAMCOR_RAMB_START_CNTL_B 0x1310 6908 #define mmCM4_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX 2 6909 #define mmCM4_CM_GAMCOR_RAMB_START_CNTL_G 0x1311 6910 #define mmCM4_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX 2 6911 #define mmCM4_CM_GAMCOR_RAMB_START_CNTL_R 0x1312 6912 #define mmCM4_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX 2 6913 #define mmCM4_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B 0x1313 6914 #define mmCM4_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 6915 #define mmCM4_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G 0x1314 6916 #define mmCM4_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 6917 #define mmCM4_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R 0x1315 6918 #define mmCM4_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 6919 #define mmCM4_CM_GAMCOR_RAMB_START_BASE_CNTL_B 0x1316 6920 #define mmCM4_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX 2 6921 #define mmCM4_CM_GAMCOR_RAMB_START_BASE_CNTL_G 0x1317 6922 #define mmCM4_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX 2 6923 #define mmCM4_CM_GAMCOR_RAMB_START_BASE_CNTL_R 0x1318 6924 #define mmCM4_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX 2 6925 #define mmCM4_CM_GAMCOR_RAMB_END_CNTL1_B 0x1319 6926 #define mmCM4_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX 2 6927 #define mmCM4_CM_GAMCOR_RAMB_END_CNTL2_B 0x131a 6928 #define mmCM4_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX 2 6929 #define mmCM4_CM_GAMCOR_RAMB_END_CNTL1_G 0x131b 6930 #define mmCM4_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX 2 6931 #define mmCM4_CM_GAMCOR_RAMB_END_CNTL2_G 0x131c 6932 #define mmCM4_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX 2 6933 #define mmCM4_CM_GAMCOR_RAMB_END_CNTL1_R 0x131d 6934 #define mmCM4_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX 2 6935 #define mmCM4_CM_GAMCOR_RAMB_END_CNTL2_R 0x131e 6936 #define mmCM4_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX 2 6937 #define mmCM4_CM_GAMCOR_RAMB_OFFSET_B 0x131f 6938 #define mmCM4_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX 2 6939 #define mmCM4_CM_GAMCOR_RAMB_OFFSET_G 0x1320 6940 #define mmCM4_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX 2 6941 #define mmCM4_CM_GAMCOR_RAMB_OFFSET_R 0x1321 6942 #define mmCM4_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX 2 6943 #define mmCM4_CM_GAMCOR_RAMB_REGION_0_1 0x1322 6944 #define mmCM4_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX 2 6945 #define mmCM4_CM_GAMCOR_RAMB_REGION_2_3 0x1323 6946 #define mmCM4_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX 2 6947 #define mmCM4_CM_GAMCOR_RAMB_REGION_4_5 0x1324 6948 #define mmCM4_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX 2 6949 #define mmCM4_CM_GAMCOR_RAMB_REGION_6_7 0x1325 6950 #define mmCM4_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX 2 6951 #define mmCM4_CM_GAMCOR_RAMB_REGION_8_9 0x1326 6952 #define mmCM4_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX 2 6953 #define mmCM4_CM_GAMCOR_RAMB_REGION_10_11 0x1327 6954 #define mmCM4_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX 2 6955 #define mmCM4_CM_GAMCOR_RAMB_REGION_12_13 0x1328 6956 #define mmCM4_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX 2 6957 #define mmCM4_CM_GAMCOR_RAMB_REGION_14_15 0x1329 6958 #define mmCM4_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX 2 6959 #define mmCM4_CM_GAMCOR_RAMB_REGION_16_17 0x132a 6960 #define mmCM4_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX 2 6961 #define mmCM4_CM_GAMCOR_RAMB_REGION_18_19 0x132b 6962 #define mmCM4_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX 2 6963 #define mmCM4_CM_GAMCOR_RAMB_REGION_20_21 0x132c 6964 #define mmCM4_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX 2 6965 #define mmCM4_CM_GAMCOR_RAMB_REGION_22_23 0x132d 6966 #define mmCM4_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX 2 6967 #define mmCM4_CM_GAMCOR_RAMB_REGION_24_25 0x132e 6968 #define mmCM4_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX 2 6969 #define mmCM4_CM_GAMCOR_RAMB_REGION_26_27 0x132f 6970 #define mmCM4_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX 2 6971 #define mmCM4_CM_GAMCOR_RAMB_REGION_28_29 0x1330 6972 #define mmCM4_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX 2 6973 #define mmCM4_CM_GAMCOR_RAMB_REGION_30_31 0x1331 6974 #define mmCM4_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX 2 6975 #define mmCM4_CM_GAMCOR_RAMB_REGION_32_33 0x1332 6976 #define mmCM4_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX 2 6977 #define mmCM4_CM_BLNDGAM_CONTROL 0x1333 6978 #define mmCM4_CM_BLNDGAM_CONTROL_BASE_IDX 2 6979 #define mmCM4_CM_BLNDGAM_LUT_INDEX 0x1334 6980 #define mmCM4_CM_BLNDGAM_LUT_INDEX_BASE_IDX 2 6981 #define mmCM4_CM_BLNDGAM_LUT_DATA 0x1335 6982 #define mmCM4_CM_BLNDGAM_LUT_DATA_BASE_IDX 2 6983 #define mmCM4_CM_BLNDGAM_LUT_CONTROL 0x1336 6984 #define mmCM4_CM_BLNDGAM_LUT_CONTROL_BASE_IDX 2 6985 #define mmCM4_CM_BLNDGAM_RAMA_START_CNTL_B 0x1337 6986 #define mmCM4_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX 2 6987 #define mmCM4_CM_BLNDGAM_RAMA_START_CNTL_G 0x1338 6988 #define mmCM4_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX 2 6989 #define mmCM4_CM_BLNDGAM_RAMA_START_CNTL_R 0x1339 6990 #define mmCM4_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX 2 6991 #define mmCM4_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B 0x133a 6992 #define mmCM4_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 6993 #define mmCM4_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G 0x133b 6994 #define mmCM4_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 6995 #define mmCM4_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R 0x133c 6996 #define mmCM4_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 6997 #define mmCM4_CM_BLNDGAM_RAMA_START_BASE_CNTL_B 0x133d 6998 #define mmCM4_CM_BLNDGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 2 6999 #define mmCM4_CM_BLNDGAM_RAMA_START_BASE_CNTL_G 0x133e 7000 #define mmCM4_CM_BLNDGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 2 7001 #define mmCM4_CM_BLNDGAM_RAMA_START_BASE_CNTL_R 0x133f 7002 #define mmCM4_CM_BLNDGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 2 7003 #define mmCM4_CM_BLNDGAM_RAMA_END_CNTL1_B 0x1340 7004 #define mmCM4_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX 2 7005 #define mmCM4_CM_BLNDGAM_RAMA_END_CNTL2_B 0x1341 7006 #define mmCM4_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX 2 7007 #define mmCM4_CM_BLNDGAM_RAMA_END_CNTL1_G 0x1342 7008 #define mmCM4_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX 2 7009 #define mmCM4_CM_BLNDGAM_RAMA_END_CNTL2_G 0x1343 7010 #define mmCM4_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX 2 7011 #define mmCM4_CM_BLNDGAM_RAMA_END_CNTL1_R 0x1344 7012 #define mmCM4_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX 2 7013 #define mmCM4_CM_BLNDGAM_RAMA_END_CNTL2_R 0x1345 7014 #define mmCM4_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX 2 7015 #define mmCM4_CM_BLNDGAM_RAMA_OFFSET_B 0x1346 7016 #define mmCM4_CM_BLNDGAM_RAMA_OFFSET_B_BASE_IDX 2 7017 #define mmCM4_CM_BLNDGAM_RAMA_OFFSET_G 0x1347 7018 #define mmCM4_CM_BLNDGAM_RAMA_OFFSET_G_BASE_IDX 2 7019 #define mmCM4_CM_BLNDGAM_RAMA_OFFSET_R 0x1348 7020 #define mmCM4_CM_BLNDGAM_RAMA_OFFSET_R_BASE_IDX 2 7021 #define mmCM4_CM_BLNDGAM_RAMA_REGION_0_1 0x1349 7022 #define mmCM4_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX 2 7023 #define mmCM4_CM_BLNDGAM_RAMA_REGION_2_3 0x134a 7024 #define mmCM4_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX 2 7025 #define mmCM4_CM_BLNDGAM_RAMA_REGION_4_5 0x134b 7026 #define mmCM4_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX 2 7027 #define mmCM4_CM_BLNDGAM_RAMA_REGION_6_7 0x134c 7028 #define mmCM4_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX 2 7029 #define mmCM4_CM_BLNDGAM_RAMA_REGION_8_9 0x134d 7030 #define mmCM4_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX 2 7031 #define mmCM4_CM_BLNDGAM_RAMA_REGION_10_11 0x134e 7032 #define mmCM4_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX 2 7033 #define mmCM4_CM_BLNDGAM_RAMA_REGION_12_13 0x134f 7034 #define mmCM4_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX 2 7035 #define mmCM4_CM_BLNDGAM_RAMA_REGION_14_15 0x1350 7036 #define mmCM4_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX 2 7037 #define mmCM4_CM_BLNDGAM_RAMA_REGION_16_17 0x1351 7038 #define mmCM4_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX 2 7039 #define mmCM4_CM_BLNDGAM_RAMA_REGION_18_19 0x1352 7040 #define mmCM4_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX 2 7041 #define mmCM4_CM_BLNDGAM_RAMA_REGION_20_21 0x1353 7042 #define mmCM4_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX 2 7043 #define mmCM4_CM_BLNDGAM_RAMA_REGION_22_23 0x1354 7044 #define mmCM4_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX 2 7045 #define mmCM4_CM_BLNDGAM_RAMA_REGION_24_25 0x1355 7046 #define mmCM4_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX 2 7047 #define mmCM4_CM_BLNDGAM_RAMA_REGION_26_27 0x1356 7048 #define mmCM4_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX 2 7049 #define mmCM4_CM_BLNDGAM_RAMA_REGION_28_29 0x1357 7050 #define mmCM4_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX 2 7051 #define mmCM4_CM_BLNDGAM_RAMA_REGION_30_31 0x1358 7052 #define mmCM4_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX 2 7053 #define mmCM4_CM_BLNDGAM_RAMA_REGION_32_33 0x1359 7054 #define mmCM4_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX 2 7055 #define mmCM4_CM_BLNDGAM_RAMB_START_CNTL_B 0x135a 7056 #define mmCM4_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX 2 7057 #define mmCM4_CM_BLNDGAM_RAMB_START_CNTL_G 0x135b 7058 #define mmCM4_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX 2 7059 #define mmCM4_CM_BLNDGAM_RAMB_START_CNTL_R 0x135c 7060 #define mmCM4_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX 2 7061 #define mmCM4_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B 0x135d 7062 #define mmCM4_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 7063 #define mmCM4_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G 0x135e 7064 #define mmCM4_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 7065 #define mmCM4_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R 0x135f 7066 #define mmCM4_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 7067 #define mmCM4_CM_BLNDGAM_RAMB_START_BASE_CNTL_B 0x1360 7068 #define mmCM4_CM_BLNDGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 2 7069 #define mmCM4_CM_BLNDGAM_RAMB_START_BASE_CNTL_G 0x1361 7070 #define mmCM4_CM_BLNDGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 2 7071 #define mmCM4_CM_BLNDGAM_RAMB_START_BASE_CNTL_R 0x1362 7072 #define mmCM4_CM_BLNDGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 2 7073 #define mmCM4_CM_BLNDGAM_RAMB_END_CNTL1_B 0x1363 7074 #define mmCM4_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX 2 7075 #define mmCM4_CM_BLNDGAM_RAMB_END_CNTL2_B 0x1364 7076 #define mmCM4_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX 2 7077 #define mmCM4_CM_BLNDGAM_RAMB_END_CNTL1_G 0x1365 7078 #define mmCM4_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX 2 7079 #define mmCM4_CM_BLNDGAM_RAMB_END_CNTL2_G 0x1366 7080 #define mmCM4_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX 2 7081 #define mmCM4_CM_BLNDGAM_RAMB_END_CNTL1_R 0x1367 7082 #define mmCM4_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX 2 7083 #define mmCM4_CM_BLNDGAM_RAMB_END_CNTL2_R 0x1368 7084 #define mmCM4_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX 2 7085 #define mmCM4_CM_BLNDGAM_RAMB_OFFSET_B 0x1369 7086 #define mmCM4_CM_BLNDGAM_RAMB_OFFSET_B_BASE_IDX 2 7087 #define mmCM4_CM_BLNDGAM_RAMB_OFFSET_G 0x136a 7088 #define mmCM4_CM_BLNDGAM_RAMB_OFFSET_G_BASE_IDX 2 7089 #define mmCM4_CM_BLNDGAM_RAMB_OFFSET_R 0x136b 7090 #define mmCM4_CM_BLNDGAM_RAMB_OFFSET_R_BASE_IDX 2 7091 #define mmCM4_CM_BLNDGAM_RAMB_REGION_0_1 0x136c 7092 #define mmCM4_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX 2 7093 #define mmCM4_CM_BLNDGAM_RAMB_REGION_2_3 0x136d 7094 #define mmCM4_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX 2 7095 #define mmCM4_CM_BLNDGAM_RAMB_REGION_4_5 0x136e 7096 #define mmCM4_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX 2 7097 #define mmCM4_CM_BLNDGAM_RAMB_REGION_6_7 0x136f 7098 #define mmCM4_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX 2 7099 #define mmCM4_CM_BLNDGAM_RAMB_REGION_8_9 0x1370 7100 #define mmCM4_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX 2 7101 #define mmCM4_CM_BLNDGAM_RAMB_REGION_10_11 0x1371 7102 #define mmCM4_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX 2 7103 #define mmCM4_CM_BLNDGAM_RAMB_REGION_12_13 0x1372 7104 #define mmCM4_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX 2 7105 #define mmCM4_CM_BLNDGAM_RAMB_REGION_14_15 0x1373 7106 #define mmCM4_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX 2 7107 #define mmCM4_CM_BLNDGAM_RAMB_REGION_16_17 0x1374 7108 #define mmCM4_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX 2 7109 #define mmCM4_CM_BLNDGAM_RAMB_REGION_18_19 0x1375 7110 #define mmCM4_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX 2 7111 #define mmCM4_CM_BLNDGAM_RAMB_REGION_20_21 0x1376 7112 #define mmCM4_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX 2 7113 #define mmCM4_CM_BLNDGAM_RAMB_REGION_22_23 0x1377 7114 #define mmCM4_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX 2 7115 #define mmCM4_CM_BLNDGAM_RAMB_REGION_24_25 0x1378 7116 #define mmCM4_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX 2 7117 #define mmCM4_CM_BLNDGAM_RAMB_REGION_26_27 0x1379 7118 #define mmCM4_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX 2 7119 #define mmCM4_CM_BLNDGAM_RAMB_REGION_28_29 0x137a 7120 #define mmCM4_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX 2 7121 #define mmCM4_CM_BLNDGAM_RAMB_REGION_30_31 0x137b 7122 #define mmCM4_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX 2 7123 #define mmCM4_CM_BLNDGAM_RAMB_REGION_32_33 0x137c 7124 #define mmCM4_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX 2 7125 #define mmCM4_CM_HDR_MULT_COEF 0x137d 7126 #define mmCM4_CM_HDR_MULT_COEF_BASE_IDX 2 7127 #define mmCM4_CM_MEM_PWR_CTRL 0x137e 7128 #define mmCM4_CM_MEM_PWR_CTRL_BASE_IDX 2 7129 #define mmCM4_CM_MEM_PWR_STATUS 0x137f 7130 #define mmCM4_CM_MEM_PWR_STATUS_BASE_IDX 2 7131 #define mmCM4_CM_DEALPHA 0x1381 7132 #define mmCM4_CM_DEALPHA_BASE_IDX 2 7133 #define mmCM4_CM_COEF_FORMAT 0x1382 7134 #define mmCM4_CM_COEF_FORMAT_BASE_IDX 2 7135 #define mmCM4_CM_SHAPER_CONTROL 0x1383 7136 #define mmCM4_CM_SHAPER_CONTROL_BASE_IDX 2 7137 #define mmCM4_CM_SHAPER_OFFSET_R 0x1384 7138 #define mmCM4_CM_SHAPER_OFFSET_R_BASE_IDX 2 7139 #define mmCM4_CM_SHAPER_OFFSET_G 0x1385 7140 #define mmCM4_CM_SHAPER_OFFSET_G_BASE_IDX 2 7141 #define mmCM4_CM_SHAPER_OFFSET_B 0x1386 7142 #define mmCM4_CM_SHAPER_OFFSET_B_BASE_IDX 2 7143 #define mmCM4_CM_SHAPER_SCALE_R 0x1387 7144 #define mmCM4_CM_SHAPER_SCALE_R_BASE_IDX 2 7145 #define mmCM4_CM_SHAPER_SCALE_G_B 0x1388 7146 #define mmCM4_CM_SHAPER_SCALE_G_B_BASE_IDX 2 7147 #define mmCM4_CM_SHAPER_LUT_INDEX 0x1389 7148 #define mmCM4_CM_SHAPER_LUT_INDEX_BASE_IDX 2 7149 #define mmCM4_CM_SHAPER_LUT_DATA 0x138a 7150 #define mmCM4_CM_SHAPER_LUT_DATA_BASE_IDX 2 7151 #define mmCM4_CM_SHAPER_LUT_WRITE_EN_MASK 0x138b 7152 #define mmCM4_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 2 7153 #define mmCM4_CM_SHAPER_RAMA_START_CNTL_B 0x138c 7154 #define mmCM4_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 2 7155 #define mmCM4_CM_SHAPER_RAMA_START_CNTL_G 0x138d 7156 #define mmCM4_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 2 7157 #define mmCM4_CM_SHAPER_RAMA_START_CNTL_R 0x138e 7158 #define mmCM4_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 2 7159 #define mmCM4_CM_SHAPER_RAMA_END_CNTL_B 0x138f 7160 #define mmCM4_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 2 7161 #define mmCM4_CM_SHAPER_RAMA_END_CNTL_G 0x1390 7162 #define mmCM4_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 2 7163 #define mmCM4_CM_SHAPER_RAMA_END_CNTL_R 0x1391 7164 #define mmCM4_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 2 7165 #define mmCM4_CM_SHAPER_RAMA_REGION_0_1 0x1392 7166 #define mmCM4_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX 2 7167 #define mmCM4_CM_SHAPER_RAMA_REGION_2_3 0x1393 7168 #define mmCM4_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX 2 7169 #define mmCM4_CM_SHAPER_RAMA_REGION_4_5 0x1394 7170 #define mmCM4_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX 2 7171 #define mmCM4_CM_SHAPER_RAMA_REGION_6_7 0x1395 7172 #define mmCM4_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX 2 7173 #define mmCM4_CM_SHAPER_RAMA_REGION_8_9 0x1396 7174 #define mmCM4_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX 2 7175 #define mmCM4_CM_SHAPER_RAMA_REGION_10_11 0x1397 7176 #define mmCM4_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX 2 7177 #define mmCM4_CM_SHAPER_RAMA_REGION_12_13 0x1398 7178 #define mmCM4_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX 2 7179 #define mmCM4_CM_SHAPER_RAMA_REGION_14_15 0x1399 7180 #define mmCM4_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX 2 7181 #define mmCM4_CM_SHAPER_RAMA_REGION_16_17 0x139a 7182 #define mmCM4_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX 2 7183 #define mmCM4_CM_SHAPER_RAMA_REGION_18_19 0x139b 7184 #define mmCM4_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX 2 7185 #define mmCM4_CM_SHAPER_RAMA_REGION_20_21 0x139c 7186 #define mmCM4_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX 2 7187 #define mmCM4_CM_SHAPER_RAMA_REGION_22_23 0x139d 7188 #define mmCM4_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX 2 7189 #define mmCM4_CM_SHAPER_RAMA_REGION_24_25 0x139e 7190 #define mmCM4_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX 2 7191 #define mmCM4_CM_SHAPER_RAMA_REGION_26_27 0x139f 7192 #define mmCM4_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX 2 7193 #define mmCM4_CM_SHAPER_RAMA_REGION_28_29 0x13a0 7194 #define mmCM4_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX 2 7195 #define mmCM4_CM_SHAPER_RAMA_REGION_30_31 0x13a1 7196 #define mmCM4_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX 2 7197 #define mmCM4_CM_SHAPER_RAMA_REGION_32_33 0x13a2 7198 #define mmCM4_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX 2 7199 #define mmCM4_CM_SHAPER_RAMB_START_CNTL_B 0x13a3 7200 #define mmCM4_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 2 7201 #define mmCM4_CM_SHAPER_RAMB_START_CNTL_G 0x13a4 7202 #define mmCM4_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 2 7203 #define mmCM4_CM_SHAPER_RAMB_START_CNTL_R 0x13a5 7204 #define mmCM4_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 2 7205 #define mmCM4_CM_SHAPER_RAMB_END_CNTL_B 0x13a6 7206 #define mmCM4_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 2 7207 #define mmCM4_CM_SHAPER_RAMB_END_CNTL_G 0x13a7 7208 #define mmCM4_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 2 7209 #define mmCM4_CM_SHAPER_RAMB_END_CNTL_R 0x13a8 7210 #define mmCM4_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 2 7211 #define mmCM4_CM_SHAPER_RAMB_REGION_0_1 0x13a9 7212 #define mmCM4_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX 2 7213 #define mmCM4_CM_SHAPER_RAMB_REGION_2_3 0x13aa 7214 #define mmCM4_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX 2 7215 #define mmCM4_CM_SHAPER_RAMB_REGION_4_5 0x13ab 7216 #define mmCM4_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX 2 7217 #define mmCM4_CM_SHAPER_RAMB_REGION_6_7 0x13ac 7218 #define mmCM4_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX 2 7219 #define mmCM4_CM_SHAPER_RAMB_REGION_8_9 0x13ad 7220 #define mmCM4_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX 2 7221 #define mmCM4_CM_SHAPER_RAMB_REGION_10_11 0x13ae 7222 #define mmCM4_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX 2 7223 #define mmCM4_CM_SHAPER_RAMB_REGION_12_13 0x13af 7224 #define mmCM4_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX 2 7225 #define mmCM4_CM_SHAPER_RAMB_REGION_14_15 0x13b0 7226 #define mmCM4_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX 2 7227 #define mmCM4_CM_SHAPER_RAMB_REGION_16_17 0x13b1 7228 #define mmCM4_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX 2 7229 #define mmCM4_CM_SHAPER_RAMB_REGION_18_19 0x13b2 7230 #define mmCM4_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX 2 7231 #define mmCM4_CM_SHAPER_RAMB_REGION_20_21 0x13b3 7232 #define mmCM4_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX 2 7233 #define mmCM4_CM_SHAPER_RAMB_REGION_22_23 0x13b4 7234 #define mmCM4_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX 2 7235 #define mmCM4_CM_SHAPER_RAMB_REGION_24_25 0x13b5 7236 #define mmCM4_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX 2 7237 #define mmCM4_CM_SHAPER_RAMB_REGION_26_27 0x13b6 7238 #define mmCM4_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX 2 7239 #define mmCM4_CM_SHAPER_RAMB_REGION_28_29 0x13b7 7240 #define mmCM4_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX 2 7241 #define mmCM4_CM_SHAPER_RAMB_REGION_30_31 0x13b8 7242 #define mmCM4_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX 2 7243 #define mmCM4_CM_SHAPER_RAMB_REGION_32_33 0x13b9 7244 #define mmCM4_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX 2 7245 #define mmCM4_CM_MEM_PWR_CTRL2 0x13ba 7246 #define mmCM4_CM_MEM_PWR_CTRL2_BASE_IDX 2 7247 #define mmCM4_CM_MEM_PWR_STATUS2 0x13bb 7248 #define mmCM4_CM_MEM_PWR_STATUS2_BASE_IDX 2 7249 #define mmCM4_CM_3DLUT_MODE 0x13bc 7250 #define mmCM4_CM_3DLUT_MODE_BASE_IDX 2 7251 #define mmCM4_CM_3DLUT_INDEX 0x13bd 7252 #define mmCM4_CM_3DLUT_INDEX_BASE_IDX 2 7253 #define mmCM4_CM_3DLUT_DATA 0x13be 7254 #define mmCM4_CM_3DLUT_DATA_BASE_IDX 2 7255 #define mmCM4_CM_3DLUT_DATA_30BIT 0x13bf 7256 #define mmCM4_CM_3DLUT_DATA_30BIT_BASE_IDX 2 7257 #define mmCM4_CM_3DLUT_READ_WRITE_CONTROL 0x13c0 7258 #define mmCM4_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 2 7259 #define mmCM4_CM_3DLUT_OUT_NORM_FACTOR 0x13c1 7260 #define mmCM4_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 2 7261 #define mmCM4_CM_3DLUT_OUT_OFFSET_R 0x13c2 7262 #define mmCM4_CM_3DLUT_OUT_OFFSET_R_BASE_IDX 2 7263 #define mmCM4_CM_3DLUT_OUT_OFFSET_G 0x13c3 7264 #define mmCM4_CM_3DLUT_OUT_OFFSET_G_BASE_IDX 2 7265 #define mmCM4_CM_3DLUT_OUT_OFFSET_B 0x13c4 7266 #define mmCM4_CM_3DLUT_OUT_OFFSET_B_BASE_IDX 2 7267 7268 7269 // addressBlock: dce_dc_dpp4_dispdec_dpp_dcperfmon_dc_perfmon_dispdec 7270 // base address: 0x4f40 7271 #define mmDC_PERFMON16_PERFCOUNTER_CNTL 0x13d0 7272 #define mmDC_PERFMON16_PERFCOUNTER_CNTL_BASE_IDX 2 7273 #define mmDC_PERFMON16_PERFCOUNTER_CNTL2 0x13d1 7274 #define mmDC_PERFMON16_PERFCOUNTER_CNTL2_BASE_IDX 2 7275 #define mmDC_PERFMON16_PERFCOUNTER_STATE 0x13d2 7276 #define mmDC_PERFMON16_PERFCOUNTER_STATE_BASE_IDX 2 7277 #define mmDC_PERFMON16_PERFMON_CNTL 0x13d3 7278 #define mmDC_PERFMON16_PERFMON_CNTL_BASE_IDX 2 7279 #define mmDC_PERFMON16_PERFMON_CNTL2 0x13d4 7280 #define mmDC_PERFMON16_PERFMON_CNTL2_BASE_IDX 2 7281 #define mmDC_PERFMON16_PERFMON_CVALUE_INT_MISC 0x13d5 7282 #define mmDC_PERFMON16_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 7283 #define mmDC_PERFMON16_PERFMON_CVALUE_LOW 0x13d6 7284 #define mmDC_PERFMON16_PERFMON_CVALUE_LOW_BASE_IDX 2 7285 #define mmDC_PERFMON16_PERFMON_HI 0x13d7 7286 #define mmDC_PERFMON16_PERFMON_HI_BASE_IDX 2 7287 #define mmDC_PERFMON16_PERFMON_LOW 0x13d8 7288 #define mmDC_PERFMON16_PERFMON_LOW_BASE_IDX 2 7289 7290 7291 // addressBlock: dce_dc_dpp5_dispdec_dpp_top_dispdec 7292 // base address: 0x1c5c 7293 #define mmDPP_TOP5_DPP_CONTROL 0x13dc 7294 #define mmDPP_TOP5_DPP_CONTROL_BASE_IDX 2 7295 #define mmDPP_TOP5_DPP_SOFT_RESET 0x13dd 7296 #define mmDPP_TOP5_DPP_SOFT_RESET_BASE_IDX 2 7297 #define mmDPP_TOP5_DPP_CRC_VAL_R_G 0x13de 7298 #define mmDPP_TOP5_DPP_CRC_VAL_R_G_BASE_IDX 2 7299 #define mmDPP_TOP5_DPP_CRC_VAL_B_A 0x13df 7300 #define mmDPP_TOP5_DPP_CRC_VAL_B_A_BASE_IDX 2 7301 #define mmDPP_TOP5_DPP_CRC_CTRL 0x13e0 7302 #define mmDPP_TOP5_DPP_CRC_CTRL_BASE_IDX 2 7303 #define mmDPP_TOP5_HOST_READ_CONTROL 0x13e1 7304 #define mmDPP_TOP5_HOST_READ_CONTROL_BASE_IDX 2 7305 7306 7307 // addressBlock: dce_dc_dpp5_dispdec_cnvc_cfg_dispdec 7308 // base address: 0x1c5c 7309 #define mmCNVC_CFG5_CNVC_SURFACE_PIXEL_FORMAT 0x13e6 7310 #define mmCNVC_CFG5_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2 7311 #define mmCNVC_CFG5_FORMAT_CONTROL 0x13e7 7312 #define mmCNVC_CFG5_FORMAT_CONTROL_BASE_IDX 2 7313 #define mmCNVC_CFG5_FCNV_FP_BIAS_R 0x13e8 7314 #define mmCNVC_CFG5_FCNV_FP_BIAS_R_BASE_IDX 2 7315 #define mmCNVC_CFG5_FCNV_FP_BIAS_G 0x13e9 7316 #define mmCNVC_CFG5_FCNV_FP_BIAS_G_BASE_IDX 2 7317 #define mmCNVC_CFG5_FCNV_FP_BIAS_B 0x13ea 7318 #define mmCNVC_CFG5_FCNV_FP_BIAS_B_BASE_IDX 2 7319 #define mmCNVC_CFG5_FCNV_FP_SCALE_R 0x13eb 7320 #define mmCNVC_CFG5_FCNV_FP_SCALE_R_BASE_IDX 2 7321 #define mmCNVC_CFG5_FCNV_FP_SCALE_G 0x13ec 7322 #define mmCNVC_CFG5_FCNV_FP_SCALE_G_BASE_IDX 2 7323 #define mmCNVC_CFG5_FCNV_FP_SCALE_B 0x13ed 7324 #define mmCNVC_CFG5_FCNV_FP_SCALE_B_BASE_IDX 2 7325 #define mmCNVC_CFG5_COLOR_KEYER_CONTROL 0x13ee 7326 #define mmCNVC_CFG5_COLOR_KEYER_CONTROL_BASE_IDX 2 7327 #define mmCNVC_CFG5_COLOR_KEYER_ALPHA 0x13ef 7328 #define mmCNVC_CFG5_COLOR_KEYER_ALPHA_BASE_IDX 2 7329 #define mmCNVC_CFG5_COLOR_KEYER_RED 0x13f0 7330 #define mmCNVC_CFG5_COLOR_KEYER_RED_BASE_IDX 2 7331 #define mmCNVC_CFG5_COLOR_KEYER_GREEN 0x13f1 7332 #define mmCNVC_CFG5_COLOR_KEYER_GREEN_BASE_IDX 2 7333 #define mmCNVC_CFG5_COLOR_KEYER_BLUE 0x13f2 7334 #define mmCNVC_CFG5_COLOR_KEYER_BLUE_BASE_IDX 2 7335 #define mmCNVC_CFG5_ALPHA_2BIT_LUT 0x13f4 7336 #define mmCNVC_CFG5_ALPHA_2BIT_LUT_BASE_IDX 2 7337 #define mmCNVC_CFG5_PRE_DEALPHA 0x13f5 7338 #define mmCNVC_CFG5_PRE_DEALPHA_BASE_IDX 2 7339 #define mmCNVC_CFG5_PRE_CSC_MODE 0x13f6 7340 #define mmCNVC_CFG5_PRE_CSC_MODE_BASE_IDX 2 7341 #define mmCNVC_CFG5_PRE_CSC_C11_C12 0x13f7 7342 #define mmCNVC_CFG5_PRE_CSC_C11_C12_BASE_IDX 2 7343 #define mmCNVC_CFG5_PRE_CSC_C13_C14 0x13f8 7344 #define mmCNVC_CFG5_PRE_CSC_C13_C14_BASE_IDX 2 7345 #define mmCNVC_CFG5_PRE_CSC_C21_C22 0x13f9 7346 #define mmCNVC_CFG5_PRE_CSC_C21_C22_BASE_IDX 2 7347 #define mmCNVC_CFG5_PRE_CSC_C23_C24 0x13fa 7348 #define mmCNVC_CFG5_PRE_CSC_C23_C24_BASE_IDX 2 7349 #define mmCNVC_CFG5_PRE_CSC_C31_C32 0x13fb 7350 #define mmCNVC_CFG5_PRE_CSC_C31_C32_BASE_IDX 2 7351 #define mmCNVC_CFG5_PRE_CSC_C33_C34 0x13fc 7352 #define mmCNVC_CFG5_PRE_CSC_C33_C34_BASE_IDX 2 7353 #define mmCNVC_CFG5_PRE_CSC_B_C11_C12 0x13fd 7354 #define mmCNVC_CFG5_PRE_CSC_B_C11_C12_BASE_IDX 2 7355 #define mmCNVC_CFG5_PRE_CSC_B_C13_C14 0x13fe 7356 #define mmCNVC_CFG5_PRE_CSC_B_C13_C14_BASE_IDX 2 7357 #define mmCNVC_CFG5_PRE_CSC_B_C21_C22 0x13ff 7358 #define mmCNVC_CFG5_PRE_CSC_B_C21_C22_BASE_IDX 2 7359 #define mmCNVC_CFG5_PRE_CSC_B_C23_C24 0x1400 7360 #define mmCNVC_CFG5_PRE_CSC_B_C23_C24_BASE_IDX 2 7361 #define mmCNVC_CFG5_PRE_CSC_B_C31_C32 0x1401 7362 #define mmCNVC_CFG5_PRE_CSC_B_C31_C32_BASE_IDX 2 7363 #define mmCNVC_CFG5_PRE_CSC_B_C33_C34 0x1402 7364 #define mmCNVC_CFG5_PRE_CSC_B_C33_C34_BASE_IDX 2 7365 #define mmCNVC_CFG5_CNVC_COEF_FORMAT 0x1403 7366 #define mmCNVC_CFG5_CNVC_COEF_FORMAT_BASE_IDX 2 7367 #define mmCNVC_CFG5_PRE_DEGAM 0x1404 7368 #define mmCNVC_CFG5_PRE_DEGAM_BASE_IDX 2 7369 #define mmCNVC_CFG5_PRE_REALPHA 0x1405 7370 #define mmCNVC_CFG5_PRE_REALPHA_BASE_IDX 2 7371 7372 7373 // addressBlock: dce_dc_dpp5_dispdec_cnvc_cur_dispdec 7374 // base address: 0x1c5c 7375 #define mmCNVC_CUR5_CURSOR0_CONTROL 0x1408 7376 #define mmCNVC_CUR5_CURSOR0_CONTROL_BASE_IDX 2 7377 #define mmCNVC_CUR5_CURSOR0_COLOR0 0x1409 7378 #define mmCNVC_CUR5_CURSOR0_COLOR0_BASE_IDX 2 7379 #define mmCNVC_CUR5_CURSOR0_COLOR1 0x140a 7380 #define mmCNVC_CUR5_CURSOR0_COLOR1_BASE_IDX 2 7381 #define mmCNVC_CUR5_CURSOR0_FP_SCALE_BIAS 0x140b 7382 #define mmCNVC_CUR5_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2 7383 7384 7385 // addressBlock: dce_dc_dpp5_dispdec_dscl_dispdec 7386 // base address: 0x1c5c 7387 #define mmDSCL5_SCL_COEF_RAM_TAP_SELECT 0x1410 7388 #define mmDSCL5_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2 7389 #define mmDSCL5_SCL_COEF_RAM_TAP_DATA 0x1411 7390 #define mmDSCL5_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2 7391 #define mmDSCL5_SCL_MODE 0x1412 7392 #define mmDSCL5_SCL_MODE_BASE_IDX 2 7393 #define mmDSCL5_SCL_TAP_CONTROL 0x1413 7394 #define mmDSCL5_SCL_TAP_CONTROL_BASE_IDX 2 7395 #define mmDSCL5_DSCL_CONTROL 0x1414 7396 #define mmDSCL5_DSCL_CONTROL_BASE_IDX 2 7397 #define mmDSCL5_DSCL_2TAP_CONTROL 0x1415 7398 #define mmDSCL5_DSCL_2TAP_CONTROL_BASE_IDX 2 7399 #define mmDSCL5_SCL_MANUAL_REPLICATE_CONTROL 0x1416 7400 #define mmDSCL5_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 7401 #define mmDSCL5_SCL_HORZ_FILTER_SCALE_RATIO 0x1417 7402 #define mmDSCL5_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 7403 #define mmDSCL5_SCL_HORZ_FILTER_INIT 0x1418 7404 #define mmDSCL5_SCL_HORZ_FILTER_INIT_BASE_IDX 2 7405 #define mmDSCL5_SCL_HORZ_FILTER_SCALE_RATIO_C 0x1419 7406 #define mmDSCL5_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2 7407 #define mmDSCL5_SCL_HORZ_FILTER_INIT_C 0x141a 7408 #define mmDSCL5_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2 7409 #define mmDSCL5_SCL_VERT_FILTER_SCALE_RATIO 0x141b 7410 #define mmDSCL5_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 7411 #define mmDSCL5_SCL_VERT_FILTER_INIT 0x141c 7412 #define mmDSCL5_SCL_VERT_FILTER_INIT_BASE_IDX 2 7413 #define mmDSCL5_SCL_VERT_FILTER_INIT_BOT 0x141d 7414 #define mmDSCL5_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2 7415 #define mmDSCL5_SCL_VERT_FILTER_SCALE_RATIO_C 0x141e 7416 #define mmDSCL5_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2 7417 #define mmDSCL5_SCL_VERT_FILTER_INIT_C 0x141f 7418 #define mmDSCL5_SCL_VERT_FILTER_INIT_C_BASE_IDX 2 7419 #define mmDSCL5_SCL_VERT_FILTER_INIT_BOT_C 0x1420 7420 #define mmDSCL5_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2 7421 #define mmDSCL5_SCL_BLACK_COLOR 0x1421 7422 #define mmDSCL5_SCL_BLACK_COLOR_BASE_IDX 2 7423 #define mmDSCL5_DSCL_UPDATE 0x1422 7424 #define mmDSCL5_DSCL_UPDATE_BASE_IDX 2 7425 #define mmDSCL5_DSCL_AUTOCAL 0x1423 7426 #define mmDSCL5_DSCL_AUTOCAL_BASE_IDX 2 7427 #define mmDSCL5_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x1424 7428 #define mmDSCL5_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 7429 #define mmDSCL5_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x1425 7430 #define mmDSCL5_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 7431 #define mmDSCL5_OTG_H_BLANK 0x1426 7432 #define mmDSCL5_OTG_H_BLANK_BASE_IDX 2 7433 #define mmDSCL5_OTG_V_BLANK 0x1427 7434 #define mmDSCL5_OTG_V_BLANK_BASE_IDX 2 7435 #define mmDSCL5_RECOUT_START 0x1428 7436 #define mmDSCL5_RECOUT_START_BASE_IDX 2 7437 #define mmDSCL5_RECOUT_SIZE 0x1429 7438 #define mmDSCL5_RECOUT_SIZE_BASE_IDX 2 7439 #define mmDSCL5_MPC_SIZE 0x142a 7440 #define mmDSCL5_MPC_SIZE_BASE_IDX 2 7441 #define mmDSCL5_LB_DATA_FORMAT 0x142b 7442 #define mmDSCL5_LB_DATA_FORMAT_BASE_IDX 2 7443 #define mmDSCL5_LB_MEMORY_CTRL 0x142c 7444 #define mmDSCL5_LB_MEMORY_CTRL_BASE_IDX 2 7445 #define mmDSCL5_LB_V_COUNTER 0x142d 7446 #define mmDSCL5_LB_V_COUNTER_BASE_IDX 2 7447 #define mmDSCL5_DSCL_MEM_PWR_CTRL 0x142e 7448 #define mmDSCL5_DSCL_MEM_PWR_CTRL_BASE_IDX 2 7449 #define mmDSCL5_DSCL_MEM_PWR_STATUS 0x142f 7450 #define mmDSCL5_DSCL_MEM_PWR_STATUS_BASE_IDX 2 7451 #define mmDSCL5_OBUF_CONTROL 0x1430 7452 #define mmDSCL5_OBUF_CONTROL_BASE_IDX 2 7453 #define mmDSCL5_OBUF_MEM_PWR_CTRL 0x1431 7454 #define mmDSCL5_OBUF_MEM_PWR_CTRL_BASE_IDX 2 7455 7456 7457 // addressBlock: dce_dc_dpp5_dispdec_cm_dispdec 7458 // base address: 0x1c5c 7459 #define mmCM5_CM_CONTROL 0x1437 7460 #define mmCM5_CM_CONTROL_BASE_IDX 2 7461 #define mmCM5_CM_POST_CSC_CONTROL 0x1438 7462 #define mmCM5_CM_POST_CSC_CONTROL_BASE_IDX 2 7463 #define mmCM5_CM_POST_CSC_C11_C12 0x1439 7464 #define mmCM5_CM_POST_CSC_C11_C12_BASE_IDX 2 7465 #define mmCM5_CM_POST_CSC_C13_C14 0x143a 7466 #define mmCM5_CM_POST_CSC_C13_C14_BASE_IDX 2 7467 #define mmCM5_CM_POST_CSC_C21_C22 0x143b 7468 #define mmCM5_CM_POST_CSC_C21_C22_BASE_IDX 2 7469 #define mmCM5_CM_POST_CSC_C23_C24 0x143c 7470 #define mmCM5_CM_POST_CSC_C23_C24_BASE_IDX 2 7471 #define mmCM5_CM_POST_CSC_C31_C32 0x143d 7472 #define mmCM5_CM_POST_CSC_C31_C32_BASE_IDX 2 7473 #define mmCM5_CM_POST_CSC_C33_C34 0x143e 7474 #define mmCM5_CM_POST_CSC_C33_C34_BASE_IDX 2 7475 #define mmCM5_CM_POST_CSC_B_C11_C12 0x143f 7476 #define mmCM5_CM_POST_CSC_B_C11_C12_BASE_IDX 2 7477 #define mmCM5_CM_POST_CSC_B_C13_C14 0x1440 7478 #define mmCM5_CM_POST_CSC_B_C13_C14_BASE_IDX 2 7479 #define mmCM5_CM_POST_CSC_B_C21_C22 0x1441 7480 #define mmCM5_CM_POST_CSC_B_C21_C22_BASE_IDX 2 7481 #define mmCM5_CM_POST_CSC_B_C23_C24 0x1442 7482 #define mmCM5_CM_POST_CSC_B_C23_C24_BASE_IDX 2 7483 #define mmCM5_CM_POST_CSC_B_C31_C32 0x1443 7484 #define mmCM5_CM_POST_CSC_B_C31_C32_BASE_IDX 2 7485 #define mmCM5_CM_POST_CSC_B_C33_C34 0x1444 7486 #define mmCM5_CM_POST_CSC_B_C33_C34_BASE_IDX 2 7487 #define mmCM5_CM_GAMUT_REMAP_CONTROL 0x1445 7488 #define mmCM5_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2 7489 #define mmCM5_CM_GAMUT_REMAP_C11_C12 0x1446 7490 #define mmCM5_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2 7491 #define mmCM5_CM_GAMUT_REMAP_C13_C14 0x1447 7492 #define mmCM5_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2 7493 #define mmCM5_CM_GAMUT_REMAP_C21_C22 0x1448 7494 #define mmCM5_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2 7495 #define mmCM5_CM_GAMUT_REMAP_C23_C24 0x1449 7496 #define mmCM5_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2 7497 #define mmCM5_CM_GAMUT_REMAP_C31_C32 0x144a 7498 #define mmCM5_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2 7499 #define mmCM5_CM_GAMUT_REMAP_C33_C34 0x144b 7500 #define mmCM5_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2 7501 #define mmCM5_CM_GAMUT_REMAP_B_C11_C12 0x144c 7502 #define mmCM5_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX 2 7503 #define mmCM5_CM_GAMUT_REMAP_B_C13_C14 0x144d 7504 #define mmCM5_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX 2 7505 #define mmCM5_CM_GAMUT_REMAP_B_C21_C22 0x144e 7506 #define mmCM5_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX 2 7507 #define mmCM5_CM_GAMUT_REMAP_B_C23_C24 0x144f 7508 #define mmCM5_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX 2 7509 #define mmCM5_CM_GAMUT_REMAP_B_C31_C32 0x1450 7510 #define mmCM5_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX 2 7511 #define mmCM5_CM_GAMUT_REMAP_B_C33_C34 0x1451 7512 #define mmCM5_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX 2 7513 #define mmCM5_CM_BIAS_CR_R 0x1452 7514 #define mmCM5_CM_BIAS_CR_R_BASE_IDX 2 7515 #define mmCM5_CM_BIAS_Y_G_CB_B 0x1453 7516 #define mmCM5_CM_BIAS_Y_G_CB_B_BASE_IDX 2 7517 #define mmCM5_CM_GAMCOR_CONTROL 0x1454 7518 #define mmCM5_CM_GAMCOR_CONTROL_BASE_IDX 2 7519 #define mmCM5_CM_GAMCOR_LUT_INDEX 0x1455 7520 #define mmCM5_CM_GAMCOR_LUT_INDEX_BASE_IDX 2 7521 #define mmCM5_CM_GAMCOR_LUT_DATA 0x1456 7522 #define mmCM5_CM_GAMCOR_LUT_DATA_BASE_IDX 2 7523 #define mmCM5_CM_GAMCOR_LUT_CONTROL 0x1457 7524 #define mmCM5_CM_GAMCOR_LUT_CONTROL_BASE_IDX 2 7525 #define mmCM5_CM_GAMCOR_RAMA_START_CNTL_B 0x1458 7526 #define mmCM5_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX 2 7527 #define mmCM5_CM_GAMCOR_RAMA_START_CNTL_G 0x1459 7528 #define mmCM5_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX 2 7529 #define mmCM5_CM_GAMCOR_RAMA_START_CNTL_R 0x145a 7530 #define mmCM5_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX 2 7531 #define mmCM5_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B 0x145b 7532 #define mmCM5_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 7533 #define mmCM5_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G 0x145c 7534 #define mmCM5_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 7535 #define mmCM5_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R 0x145d 7536 #define mmCM5_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 7537 #define mmCM5_CM_GAMCOR_RAMA_START_BASE_CNTL_B 0x145e 7538 #define mmCM5_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX 2 7539 #define mmCM5_CM_GAMCOR_RAMA_START_BASE_CNTL_G 0x145f 7540 #define mmCM5_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX 2 7541 #define mmCM5_CM_GAMCOR_RAMA_START_BASE_CNTL_R 0x1460 7542 #define mmCM5_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX 2 7543 #define mmCM5_CM_GAMCOR_RAMA_END_CNTL1_B 0x1461 7544 #define mmCM5_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX 2 7545 #define mmCM5_CM_GAMCOR_RAMA_END_CNTL2_B 0x1462 7546 #define mmCM5_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX 2 7547 #define mmCM5_CM_GAMCOR_RAMA_END_CNTL1_G 0x1463 7548 #define mmCM5_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX 2 7549 #define mmCM5_CM_GAMCOR_RAMA_END_CNTL2_G 0x1464 7550 #define mmCM5_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX 2 7551 #define mmCM5_CM_GAMCOR_RAMA_END_CNTL1_R 0x1465 7552 #define mmCM5_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX 2 7553 #define mmCM5_CM_GAMCOR_RAMA_END_CNTL2_R 0x1466 7554 #define mmCM5_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX 2 7555 #define mmCM5_CM_GAMCOR_RAMA_OFFSET_B 0x1467 7556 #define mmCM5_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX 2 7557 #define mmCM5_CM_GAMCOR_RAMA_OFFSET_G 0x1468 7558 #define mmCM5_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX 2 7559 #define mmCM5_CM_GAMCOR_RAMA_OFFSET_R 0x1469 7560 #define mmCM5_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX 2 7561 #define mmCM5_CM_GAMCOR_RAMA_REGION_0_1 0x146a 7562 #define mmCM5_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX 2 7563 #define mmCM5_CM_GAMCOR_RAMA_REGION_2_3 0x146b 7564 #define mmCM5_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX 2 7565 #define mmCM5_CM_GAMCOR_RAMA_REGION_4_5 0x146c 7566 #define mmCM5_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX 2 7567 #define mmCM5_CM_GAMCOR_RAMA_REGION_6_7 0x146d 7568 #define mmCM5_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX 2 7569 #define mmCM5_CM_GAMCOR_RAMA_REGION_8_9 0x146e 7570 #define mmCM5_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX 2 7571 #define mmCM5_CM_GAMCOR_RAMA_REGION_10_11 0x146f 7572 #define mmCM5_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX 2 7573 #define mmCM5_CM_GAMCOR_RAMA_REGION_12_13 0x1470 7574 #define mmCM5_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX 2 7575 #define mmCM5_CM_GAMCOR_RAMA_REGION_14_15 0x1471 7576 #define mmCM5_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX 2 7577 #define mmCM5_CM_GAMCOR_RAMA_REGION_16_17 0x1472 7578 #define mmCM5_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX 2 7579 #define mmCM5_CM_GAMCOR_RAMA_REGION_18_19 0x1473 7580 #define mmCM5_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX 2 7581 #define mmCM5_CM_GAMCOR_RAMA_REGION_20_21 0x1474 7582 #define mmCM5_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX 2 7583 #define mmCM5_CM_GAMCOR_RAMA_REGION_22_23 0x1475 7584 #define mmCM5_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX 2 7585 #define mmCM5_CM_GAMCOR_RAMA_REGION_24_25 0x1476 7586 #define mmCM5_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX 2 7587 #define mmCM5_CM_GAMCOR_RAMA_REGION_26_27 0x1477 7588 #define mmCM5_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX 2 7589 #define mmCM5_CM_GAMCOR_RAMA_REGION_28_29 0x1478 7590 #define mmCM5_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX 2 7591 #define mmCM5_CM_GAMCOR_RAMA_REGION_30_31 0x1479 7592 #define mmCM5_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX 2 7593 #define mmCM5_CM_GAMCOR_RAMA_REGION_32_33 0x147a 7594 #define mmCM5_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX 2 7595 #define mmCM5_CM_GAMCOR_RAMB_START_CNTL_B 0x147b 7596 #define mmCM5_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX 2 7597 #define mmCM5_CM_GAMCOR_RAMB_START_CNTL_G 0x147c 7598 #define mmCM5_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX 2 7599 #define mmCM5_CM_GAMCOR_RAMB_START_CNTL_R 0x147d 7600 #define mmCM5_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX 2 7601 #define mmCM5_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B 0x147e 7602 #define mmCM5_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 7603 #define mmCM5_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G 0x147f 7604 #define mmCM5_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 7605 #define mmCM5_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R 0x1480 7606 #define mmCM5_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 7607 #define mmCM5_CM_GAMCOR_RAMB_START_BASE_CNTL_B 0x1481 7608 #define mmCM5_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX 2 7609 #define mmCM5_CM_GAMCOR_RAMB_START_BASE_CNTL_G 0x1482 7610 #define mmCM5_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX 2 7611 #define mmCM5_CM_GAMCOR_RAMB_START_BASE_CNTL_R 0x1483 7612 #define mmCM5_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX 2 7613 #define mmCM5_CM_GAMCOR_RAMB_END_CNTL1_B 0x1484 7614 #define mmCM5_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX 2 7615 #define mmCM5_CM_GAMCOR_RAMB_END_CNTL2_B 0x1485 7616 #define mmCM5_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX 2 7617 #define mmCM5_CM_GAMCOR_RAMB_END_CNTL1_G 0x1486 7618 #define mmCM5_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX 2 7619 #define mmCM5_CM_GAMCOR_RAMB_END_CNTL2_G 0x1487 7620 #define mmCM5_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX 2 7621 #define mmCM5_CM_GAMCOR_RAMB_END_CNTL1_R 0x1488 7622 #define mmCM5_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX 2 7623 #define mmCM5_CM_GAMCOR_RAMB_END_CNTL2_R 0x1489 7624 #define mmCM5_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX 2 7625 #define mmCM5_CM_GAMCOR_RAMB_OFFSET_B 0x148a 7626 #define mmCM5_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX 2 7627 #define mmCM5_CM_GAMCOR_RAMB_OFFSET_G 0x148b 7628 #define mmCM5_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX 2 7629 #define mmCM5_CM_GAMCOR_RAMB_OFFSET_R 0x148c 7630 #define mmCM5_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX 2 7631 #define mmCM5_CM_GAMCOR_RAMB_REGION_0_1 0x148d 7632 #define mmCM5_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX 2 7633 #define mmCM5_CM_GAMCOR_RAMB_REGION_2_3 0x148e 7634 #define mmCM5_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX 2 7635 #define mmCM5_CM_GAMCOR_RAMB_REGION_4_5 0x148f 7636 #define mmCM5_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX 2 7637 #define mmCM5_CM_GAMCOR_RAMB_REGION_6_7 0x1490 7638 #define mmCM5_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX 2 7639 #define mmCM5_CM_GAMCOR_RAMB_REGION_8_9 0x1491 7640 #define mmCM5_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX 2 7641 #define mmCM5_CM_GAMCOR_RAMB_REGION_10_11 0x1492 7642 #define mmCM5_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX 2 7643 #define mmCM5_CM_GAMCOR_RAMB_REGION_12_13 0x1493 7644 #define mmCM5_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX 2 7645 #define mmCM5_CM_GAMCOR_RAMB_REGION_14_15 0x1494 7646 #define mmCM5_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX 2 7647 #define mmCM5_CM_GAMCOR_RAMB_REGION_16_17 0x1495 7648 #define mmCM5_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX 2 7649 #define mmCM5_CM_GAMCOR_RAMB_REGION_18_19 0x1496 7650 #define mmCM5_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX 2 7651 #define mmCM5_CM_GAMCOR_RAMB_REGION_20_21 0x1497 7652 #define mmCM5_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX 2 7653 #define mmCM5_CM_GAMCOR_RAMB_REGION_22_23 0x1498 7654 #define mmCM5_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX 2 7655 #define mmCM5_CM_GAMCOR_RAMB_REGION_24_25 0x1499 7656 #define mmCM5_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX 2 7657 #define mmCM5_CM_GAMCOR_RAMB_REGION_26_27 0x149a 7658 #define mmCM5_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX 2 7659 #define mmCM5_CM_GAMCOR_RAMB_REGION_28_29 0x149b 7660 #define mmCM5_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX 2 7661 #define mmCM5_CM_GAMCOR_RAMB_REGION_30_31 0x149c 7662 #define mmCM5_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX 2 7663 #define mmCM5_CM_GAMCOR_RAMB_REGION_32_33 0x149d 7664 #define mmCM5_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX 2 7665 #define mmCM5_CM_BLNDGAM_CONTROL 0x149e 7666 #define mmCM5_CM_BLNDGAM_CONTROL_BASE_IDX 2 7667 #define mmCM5_CM_BLNDGAM_LUT_INDEX 0x149f 7668 #define mmCM5_CM_BLNDGAM_LUT_INDEX_BASE_IDX 2 7669 #define mmCM5_CM_BLNDGAM_LUT_DATA 0x14a0 7670 #define mmCM5_CM_BLNDGAM_LUT_DATA_BASE_IDX 2 7671 #define mmCM5_CM_BLNDGAM_LUT_CONTROL 0x14a1 7672 #define mmCM5_CM_BLNDGAM_LUT_CONTROL_BASE_IDX 2 7673 #define mmCM5_CM_BLNDGAM_RAMA_START_CNTL_B 0x14a2 7674 #define mmCM5_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX 2 7675 #define mmCM5_CM_BLNDGAM_RAMA_START_CNTL_G 0x14a3 7676 #define mmCM5_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX 2 7677 #define mmCM5_CM_BLNDGAM_RAMA_START_CNTL_R 0x14a4 7678 #define mmCM5_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX 2 7679 #define mmCM5_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B 0x14a5 7680 #define mmCM5_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 7681 #define mmCM5_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G 0x14a6 7682 #define mmCM5_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 7683 #define mmCM5_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R 0x14a7 7684 #define mmCM5_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 7685 #define mmCM5_CM_BLNDGAM_RAMA_START_BASE_CNTL_B 0x14a8 7686 #define mmCM5_CM_BLNDGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 2 7687 #define mmCM5_CM_BLNDGAM_RAMA_START_BASE_CNTL_G 0x14a9 7688 #define mmCM5_CM_BLNDGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 2 7689 #define mmCM5_CM_BLNDGAM_RAMA_START_BASE_CNTL_R 0x14aa 7690 #define mmCM5_CM_BLNDGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 2 7691 #define mmCM5_CM_BLNDGAM_RAMA_END_CNTL1_B 0x14ab 7692 #define mmCM5_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX 2 7693 #define mmCM5_CM_BLNDGAM_RAMA_END_CNTL2_B 0x14ac 7694 #define mmCM5_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX 2 7695 #define mmCM5_CM_BLNDGAM_RAMA_END_CNTL1_G 0x14ad 7696 #define mmCM5_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX 2 7697 #define mmCM5_CM_BLNDGAM_RAMA_END_CNTL2_G 0x14ae 7698 #define mmCM5_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX 2 7699 #define mmCM5_CM_BLNDGAM_RAMA_END_CNTL1_R 0x14af 7700 #define mmCM5_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX 2 7701 #define mmCM5_CM_BLNDGAM_RAMA_END_CNTL2_R 0x14b0 7702 #define mmCM5_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX 2 7703 #define mmCM5_CM_BLNDGAM_RAMA_OFFSET_B 0x14b1 7704 #define mmCM5_CM_BLNDGAM_RAMA_OFFSET_B_BASE_IDX 2 7705 #define mmCM5_CM_BLNDGAM_RAMA_OFFSET_G 0x14b2 7706 #define mmCM5_CM_BLNDGAM_RAMA_OFFSET_G_BASE_IDX 2 7707 #define mmCM5_CM_BLNDGAM_RAMA_OFFSET_R 0x14b3 7708 #define mmCM5_CM_BLNDGAM_RAMA_OFFSET_R_BASE_IDX 2 7709 #define mmCM5_CM_BLNDGAM_RAMA_REGION_0_1 0x14b4 7710 #define mmCM5_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX 2 7711 #define mmCM5_CM_BLNDGAM_RAMA_REGION_2_3 0x14b5 7712 #define mmCM5_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX 2 7713 #define mmCM5_CM_BLNDGAM_RAMA_REGION_4_5 0x14b6 7714 #define mmCM5_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX 2 7715 #define mmCM5_CM_BLNDGAM_RAMA_REGION_6_7 0x14b7 7716 #define mmCM5_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX 2 7717 #define mmCM5_CM_BLNDGAM_RAMA_REGION_8_9 0x14b8 7718 #define mmCM5_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX 2 7719 #define mmCM5_CM_BLNDGAM_RAMA_REGION_10_11 0x14b9 7720 #define mmCM5_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX 2 7721 #define mmCM5_CM_BLNDGAM_RAMA_REGION_12_13 0x14ba 7722 #define mmCM5_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX 2 7723 #define mmCM5_CM_BLNDGAM_RAMA_REGION_14_15 0x14bb 7724 #define mmCM5_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX 2 7725 #define mmCM5_CM_BLNDGAM_RAMA_REGION_16_17 0x14bc 7726 #define mmCM5_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX 2 7727 #define mmCM5_CM_BLNDGAM_RAMA_REGION_18_19 0x14bd 7728 #define mmCM5_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX 2 7729 #define mmCM5_CM_BLNDGAM_RAMA_REGION_20_21 0x14be 7730 #define mmCM5_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX 2 7731 #define mmCM5_CM_BLNDGAM_RAMA_REGION_22_23 0x14bf 7732 #define mmCM5_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX 2 7733 #define mmCM5_CM_BLNDGAM_RAMA_REGION_24_25 0x14c0 7734 #define mmCM5_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX 2 7735 #define mmCM5_CM_BLNDGAM_RAMA_REGION_26_27 0x14c1 7736 #define mmCM5_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX 2 7737 #define mmCM5_CM_BLNDGAM_RAMA_REGION_28_29 0x14c2 7738 #define mmCM5_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX 2 7739 #define mmCM5_CM_BLNDGAM_RAMA_REGION_30_31 0x14c3 7740 #define mmCM5_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX 2 7741 #define mmCM5_CM_BLNDGAM_RAMA_REGION_32_33 0x14c4 7742 #define mmCM5_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX 2 7743 #define mmCM5_CM_BLNDGAM_RAMB_START_CNTL_B 0x14c5 7744 #define mmCM5_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX 2 7745 #define mmCM5_CM_BLNDGAM_RAMB_START_CNTL_G 0x14c6 7746 #define mmCM5_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX 2 7747 #define mmCM5_CM_BLNDGAM_RAMB_START_CNTL_R 0x14c7 7748 #define mmCM5_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX 2 7749 #define mmCM5_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B 0x14c8 7750 #define mmCM5_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 7751 #define mmCM5_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G 0x14c9 7752 #define mmCM5_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 7753 #define mmCM5_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R 0x14ca 7754 #define mmCM5_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 7755 #define mmCM5_CM_BLNDGAM_RAMB_START_BASE_CNTL_B 0x14cb 7756 #define mmCM5_CM_BLNDGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 2 7757 #define mmCM5_CM_BLNDGAM_RAMB_START_BASE_CNTL_G 0x14cc 7758 #define mmCM5_CM_BLNDGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 2 7759 #define mmCM5_CM_BLNDGAM_RAMB_START_BASE_CNTL_R 0x14cd 7760 #define mmCM5_CM_BLNDGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 2 7761 #define mmCM5_CM_BLNDGAM_RAMB_END_CNTL1_B 0x14ce 7762 #define mmCM5_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX 2 7763 #define mmCM5_CM_BLNDGAM_RAMB_END_CNTL2_B 0x14cf 7764 #define mmCM5_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX 2 7765 #define mmCM5_CM_BLNDGAM_RAMB_END_CNTL1_G 0x14d0 7766 #define mmCM5_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX 2 7767 #define mmCM5_CM_BLNDGAM_RAMB_END_CNTL2_G 0x14d1 7768 #define mmCM5_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX 2 7769 #define mmCM5_CM_BLNDGAM_RAMB_END_CNTL1_R 0x14d2 7770 #define mmCM5_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX 2 7771 #define mmCM5_CM_BLNDGAM_RAMB_END_CNTL2_R 0x14d3 7772 #define mmCM5_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX 2 7773 #define mmCM5_CM_BLNDGAM_RAMB_OFFSET_B 0x14d4 7774 #define mmCM5_CM_BLNDGAM_RAMB_OFFSET_B_BASE_IDX 2 7775 #define mmCM5_CM_BLNDGAM_RAMB_OFFSET_G 0x14d5 7776 #define mmCM5_CM_BLNDGAM_RAMB_OFFSET_G_BASE_IDX 2 7777 #define mmCM5_CM_BLNDGAM_RAMB_OFFSET_R 0x14d6 7778 #define mmCM5_CM_BLNDGAM_RAMB_OFFSET_R_BASE_IDX 2 7779 #define mmCM5_CM_BLNDGAM_RAMB_REGION_0_1 0x14d7 7780 #define mmCM5_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX 2 7781 #define mmCM5_CM_BLNDGAM_RAMB_REGION_2_3 0x14d8 7782 #define mmCM5_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX 2 7783 #define mmCM5_CM_BLNDGAM_RAMB_REGION_4_5 0x14d9 7784 #define mmCM5_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX 2 7785 #define mmCM5_CM_BLNDGAM_RAMB_REGION_6_7 0x14da 7786 #define mmCM5_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX 2 7787 #define mmCM5_CM_BLNDGAM_RAMB_REGION_8_9 0x14db 7788 #define mmCM5_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX 2 7789 #define mmCM5_CM_BLNDGAM_RAMB_REGION_10_11 0x14dc 7790 #define mmCM5_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX 2 7791 #define mmCM5_CM_BLNDGAM_RAMB_REGION_12_13 0x14dd 7792 #define mmCM5_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX 2 7793 #define mmCM5_CM_BLNDGAM_RAMB_REGION_14_15 0x14de 7794 #define mmCM5_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX 2 7795 #define mmCM5_CM_BLNDGAM_RAMB_REGION_16_17 0x14df 7796 #define mmCM5_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX 2 7797 #define mmCM5_CM_BLNDGAM_RAMB_REGION_18_19 0x14e0 7798 #define mmCM5_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX 2 7799 #define mmCM5_CM_BLNDGAM_RAMB_REGION_20_21 0x14e1 7800 #define mmCM5_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX 2 7801 #define mmCM5_CM_BLNDGAM_RAMB_REGION_22_23 0x14e2 7802 #define mmCM5_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX 2 7803 #define mmCM5_CM_BLNDGAM_RAMB_REGION_24_25 0x14e3 7804 #define mmCM5_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX 2 7805 #define mmCM5_CM_BLNDGAM_RAMB_REGION_26_27 0x14e4 7806 #define mmCM5_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX 2 7807 #define mmCM5_CM_BLNDGAM_RAMB_REGION_28_29 0x14e5 7808 #define mmCM5_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX 2 7809 #define mmCM5_CM_BLNDGAM_RAMB_REGION_30_31 0x14e6 7810 #define mmCM5_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX 2 7811 #define mmCM5_CM_BLNDGAM_RAMB_REGION_32_33 0x14e7 7812 #define mmCM5_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX 2 7813 #define mmCM5_CM_HDR_MULT_COEF 0x14e8 7814 #define mmCM5_CM_HDR_MULT_COEF_BASE_IDX 2 7815 #define mmCM5_CM_MEM_PWR_CTRL 0x14e9 7816 #define mmCM5_CM_MEM_PWR_CTRL_BASE_IDX 2 7817 #define mmCM5_CM_MEM_PWR_STATUS 0x14ea 7818 #define mmCM5_CM_MEM_PWR_STATUS_BASE_IDX 2 7819 #define mmCM5_CM_DEALPHA 0x14ec 7820 #define mmCM5_CM_DEALPHA_BASE_IDX 2 7821 #define mmCM5_CM_COEF_FORMAT 0x14ed 7822 #define mmCM5_CM_COEF_FORMAT_BASE_IDX 2 7823 #define mmCM5_CM_SHAPER_CONTROL 0x14ee 7824 #define mmCM5_CM_SHAPER_CONTROL_BASE_IDX 2 7825 #define mmCM5_CM_SHAPER_OFFSET_R 0x14ef 7826 #define mmCM5_CM_SHAPER_OFFSET_R_BASE_IDX 2 7827 #define mmCM5_CM_SHAPER_OFFSET_G 0x14f0 7828 #define mmCM5_CM_SHAPER_OFFSET_G_BASE_IDX 2 7829 #define mmCM5_CM_SHAPER_OFFSET_B 0x14f1 7830 #define mmCM5_CM_SHAPER_OFFSET_B_BASE_IDX 2 7831 #define mmCM5_CM_SHAPER_SCALE_R 0x14f2 7832 #define mmCM5_CM_SHAPER_SCALE_R_BASE_IDX 2 7833 #define mmCM5_CM_SHAPER_SCALE_G_B 0x14f3 7834 #define mmCM5_CM_SHAPER_SCALE_G_B_BASE_IDX 2 7835 #define mmCM5_CM_SHAPER_LUT_INDEX 0x14f4 7836 #define mmCM5_CM_SHAPER_LUT_INDEX_BASE_IDX 2 7837 #define mmCM5_CM_SHAPER_LUT_DATA 0x14f5 7838 #define mmCM5_CM_SHAPER_LUT_DATA_BASE_IDX 2 7839 #define mmCM5_CM_SHAPER_LUT_WRITE_EN_MASK 0x14f6 7840 #define mmCM5_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 2 7841 #define mmCM5_CM_SHAPER_RAMA_START_CNTL_B 0x14f7 7842 #define mmCM5_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 2 7843 #define mmCM5_CM_SHAPER_RAMA_START_CNTL_G 0x14f8 7844 #define mmCM5_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 2 7845 #define mmCM5_CM_SHAPER_RAMA_START_CNTL_R 0x14f9 7846 #define mmCM5_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 2 7847 #define mmCM5_CM_SHAPER_RAMA_END_CNTL_B 0x14fa 7848 #define mmCM5_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 2 7849 #define mmCM5_CM_SHAPER_RAMA_END_CNTL_G 0x14fb 7850 #define mmCM5_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 2 7851 #define mmCM5_CM_SHAPER_RAMA_END_CNTL_R 0x14fc 7852 #define mmCM5_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 2 7853 #define mmCM5_CM_SHAPER_RAMA_REGION_0_1 0x14fd 7854 #define mmCM5_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX 2 7855 #define mmCM5_CM_SHAPER_RAMA_REGION_2_3 0x14fe 7856 #define mmCM5_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX 2 7857 #define mmCM5_CM_SHAPER_RAMA_REGION_4_5 0x14ff 7858 #define mmCM5_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX 2 7859 #define mmCM5_CM_SHAPER_RAMA_REGION_6_7 0x1500 7860 #define mmCM5_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX 2 7861 #define mmCM5_CM_SHAPER_RAMA_REGION_8_9 0x1501 7862 #define mmCM5_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX 2 7863 #define mmCM5_CM_SHAPER_RAMA_REGION_10_11 0x1502 7864 #define mmCM5_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX 2 7865 #define mmCM5_CM_SHAPER_RAMA_REGION_12_13 0x1503 7866 #define mmCM5_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX 2 7867 #define mmCM5_CM_SHAPER_RAMA_REGION_14_15 0x1504 7868 #define mmCM5_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX 2 7869 #define mmCM5_CM_SHAPER_RAMA_REGION_16_17 0x1505 7870 #define mmCM5_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX 2 7871 #define mmCM5_CM_SHAPER_RAMA_REGION_18_19 0x1506 7872 #define mmCM5_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX 2 7873 #define mmCM5_CM_SHAPER_RAMA_REGION_20_21 0x1507 7874 #define mmCM5_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX 2 7875 #define mmCM5_CM_SHAPER_RAMA_REGION_22_23 0x1508 7876 #define mmCM5_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX 2 7877 #define mmCM5_CM_SHAPER_RAMA_REGION_24_25 0x1509 7878 #define mmCM5_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX 2 7879 #define mmCM5_CM_SHAPER_RAMA_REGION_26_27 0x150a 7880 #define mmCM5_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX 2 7881 #define mmCM5_CM_SHAPER_RAMA_REGION_28_29 0x150b 7882 #define mmCM5_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX 2 7883 #define mmCM5_CM_SHAPER_RAMA_REGION_30_31 0x150c 7884 #define mmCM5_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX 2 7885 #define mmCM5_CM_SHAPER_RAMA_REGION_32_33 0x150d 7886 #define mmCM5_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX 2 7887 #define mmCM5_CM_SHAPER_RAMB_START_CNTL_B 0x150e 7888 #define mmCM5_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 2 7889 #define mmCM5_CM_SHAPER_RAMB_START_CNTL_G 0x150f 7890 #define mmCM5_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 2 7891 #define mmCM5_CM_SHAPER_RAMB_START_CNTL_R 0x1510 7892 #define mmCM5_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 2 7893 #define mmCM5_CM_SHAPER_RAMB_END_CNTL_B 0x1511 7894 #define mmCM5_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 2 7895 #define mmCM5_CM_SHAPER_RAMB_END_CNTL_G 0x1512 7896 #define mmCM5_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 2 7897 #define mmCM5_CM_SHAPER_RAMB_END_CNTL_R 0x1513 7898 #define mmCM5_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 2 7899 #define mmCM5_CM_SHAPER_RAMB_REGION_0_1 0x1514 7900 #define mmCM5_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX 2 7901 #define mmCM5_CM_SHAPER_RAMB_REGION_2_3 0x1515 7902 #define mmCM5_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX 2 7903 #define mmCM5_CM_SHAPER_RAMB_REGION_4_5 0x1516 7904 #define mmCM5_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX 2 7905 #define mmCM5_CM_SHAPER_RAMB_REGION_6_7 0x1517 7906 #define mmCM5_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX 2 7907 #define mmCM5_CM_SHAPER_RAMB_REGION_8_9 0x1518 7908 #define mmCM5_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX 2 7909 #define mmCM5_CM_SHAPER_RAMB_REGION_10_11 0x1519 7910 #define mmCM5_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX 2 7911 #define mmCM5_CM_SHAPER_RAMB_REGION_12_13 0x151a 7912 #define mmCM5_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX 2 7913 #define mmCM5_CM_SHAPER_RAMB_REGION_14_15 0x151b 7914 #define mmCM5_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX 2 7915 #define mmCM5_CM_SHAPER_RAMB_REGION_16_17 0x151c 7916 #define mmCM5_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX 2 7917 #define mmCM5_CM_SHAPER_RAMB_REGION_18_19 0x151d 7918 #define mmCM5_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX 2 7919 #define mmCM5_CM_SHAPER_RAMB_REGION_20_21 0x151e 7920 #define mmCM5_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX 2 7921 #define mmCM5_CM_SHAPER_RAMB_REGION_22_23 0x151f 7922 #define mmCM5_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX 2 7923 #define mmCM5_CM_SHAPER_RAMB_REGION_24_25 0x1520 7924 #define mmCM5_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX 2 7925 #define mmCM5_CM_SHAPER_RAMB_REGION_26_27 0x1521 7926 #define mmCM5_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX 2 7927 #define mmCM5_CM_SHAPER_RAMB_REGION_28_29 0x1522 7928 #define mmCM5_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX 2 7929 #define mmCM5_CM_SHAPER_RAMB_REGION_30_31 0x1523 7930 #define mmCM5_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX 2 7931 #define mmCM5_CM_SHAPER_RAMB_REGION_32_33 0x1524 7932 #define mmCM5_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX 2 7933 #define mmCM5_CM_MEM_PWR_CTRL2 0x1525 7934 #define mmCM5_CM_MEM_PWR_CTRL2_BASE_IDX 2 7935 #define mmCM5_CM_MEM_PWR_STATUS2 0x1526 7936 #define mmCM5_CM_MEM_PWR_STATUS2_BASE_IDX 2 7937 #define mmCM5_CM_3DLUT_MODE 0x1527 7938 #define mmCM5_CM_3DLUT_MODE_BASE_IDX 2 7939 #define mmCM5_CM_3DLUT_INDEX 0x1528 7940 #define mmCM5_CM_3DLUT_INDEX_BASE_IDX 2 7941 #define mmCM5_CM_3DLUT_DATA 0x1529 7942 #define mmCM5_CM_3DLUT_DATA_BASE_IDX 2 7943 #define mmCM5_CM_3DLUT_DATA_30BIT 0x152a 7944 #define mmCM5_CM_3DLUT_DATA_30BIT_BASE_IDX 2 7945 #define mmCM5_CM_3DLUT_READ_WRITE_CONTROL 0x152b 7946 #define mmCM5_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 2 7947 #define mmCM5_CM_3DLUT_OUT_NORM_FACTOR 0x152c 7948 #define mmCM5_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 2 7949 #define mmCM5_CM_3DLUT_OUT_OFFSET_R 0x152d 7950 #define mmCM5_CM_3DLUT_OUT_OFFSET_R_BASE_IDX 2 7951 #define mmCM5_CM_3DLUT_OUT_OFFSET_G 0x152e 7952 #define mmCM5_CM_3DLUT_OUT_OFFSET_G_BASE_IDX 2 7953 #define mmCM5_CM_3DLUT_OUT_OFFSET_B 0x152f 7954 #define mmCM5_CM_3DLUT_OUT_OFFSET_B_BASE_IDX 2 7955 7956 7957 // addressBlock: dce_dc_dpp5_dispdec_dpp_dcperfmon_dc_perfmon_dispdec 7958 // base address: 0x54ec 7959 #define mmDC_PERFMON17_PERFCOUNTER_CNTL 0x153b 7960 #define mmDC_PERFMON17_PERFCOUNTER_CNTL_BASE_IDX 2 7961 #define mmDC_PERFMON17_PERFCOUNTER_CNTL2 0x153c 7962 #define mmDC_PERFMON17_PERFCOUNTER_CNTL2_BASE_IDX 2 7963 #define mmDC_PERFMON17_PERFCOUNTER_STATE 0x153d 7964 #define mmDC_PERFMON17_PERFCOUNTER_STATE_BASE_IDX 2 7965 #define mmDC_PERFMON17_PERFMON_CNTL 0x153e 7966 #define mmDC_PERFMON17_PERFMON_CNTL_BASE_IDX 2 7967 #define mmDC_PERFMON17_PERFMON_CNTL2 0x153f 7968 #define mmDC_PERFMON17_PERFMON_CNTL2_BASE_IDX 2 7969 #define mmDC_PERFMON17_PERFMON_CVALUE_INT_MISC 0x1540 7970 #define mmDC_PERFMON17_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 7971 #define mmDC_PERFMON17_PERFMON_CVALUE_LOW 0x1541 7972 #define mmDC_PERFMON17_PERFMON_CVALUE_LOW_BASE_IDX 2 7973 #define mmDC_PERFMON17_PERFMON_HI 0x1542 7974 #define mmDC_PERFMON17_PERFMON_HI_BASE_IDX 2 7975 #define mmDC_PERFMON17_PERFMON_LOW 0x1543 7976 #define mmDC_PERFMON17_PERFMON_LOW_BASE_IDX 2 7977 7978 7979 // addressBlock: dce_dc_opp_fmt0_dispdec 7980 // base address: 0x0 7981 #define mmFMT0_FMT_CLAMP_COMPONENT_R 0x183c 7982 #define mmFMT0_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 7983 #define mmFMT0_FMT_CLAMP_COMPONENT_G 0x183d 7984 #define mmFMT0_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 7985 #define mmFMT0_FMT_CLAMP_COMPONENT_B 0x183e 7986 #define mmFMT0_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 7987 #define mmFMT0_FMT_DYNAMIC_EXP_CNTL 0x183f 7988 #define mmFMT0_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 7989 #define mmFMT0_FMT_CONTROL 0x1840 7990 #define mmFMT0_FMT_CONTROL_BASE_IDX 2 7991 #define mmFMT0_FMT_BIT_DEPTH_CONTROL 0x1841 7992 #define mmFMT0_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 7993 #define mmFMT0_FMT_DITHER_RAND_R_SEED 0x1842 7994 #define mmFMT0_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 7995 #define mmFMT0_FMT_DITHER_RAND_G_SEED 0x1843 7996 #define mmFMT0_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 7997 #define mmFMT0_FMT_DITHER_RAND_B_SEED 0x1844 7998 #define mmFMT0_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 7999 #define mmFMT0_FMT_CLAMP_CNTL 0x1845 8000 #define mmFMT0_FMT_CLAMP_CNTL_BASE_IDX 2 8001 #define mmFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x1846 8002 #define mmFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 8003 #define mmFMT0_FMT_MAP420_MEMORY_CONTROL 0x1847 8004 #define mmFMT0_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2 8005 #define mmFMT0_FMT_422_CONTROL 0x1849 8006 #define mmFMT0_FMT_422_CONTROL_BASE_IDX 2 8007 8008 8009 // addressBlock: dce_dc_opp_dpg0_dispdec 8010 // base address: 0x0 8011 #define mmDPG0_DPG_CONTROL 0x1854 8012 #define mmDPG0_DPG_CONTROL_BASE_IDX 2 8013 #define mmDPG0_DPG_RAMP_CONTROL 0x1855 8014 #define mmDPG0_DPG_RAMP_CONTROL_BASE_IDX 2 8015 #define mmDPG0_DPG_DIMENSIONS 0x1856 8016 #define mmDPG0_DPG_DIMENSIONS_BASE_IDX 2 8017 #define mmDPG0_DPG_COLOUR_R_CR 0x1857 8018 #define mmDPG0_DPG_COLOUR_R_CR_BASE_IDX 2 8019 #define mmDPG0_DPG_COLOUR_G_Y 0x1858 8020 #define mmDPG0_DPG_COLOUR_G_Y_BASE_IDX 2 8021 #define mmDPG0_DPG_COLOUR_B_CB 0x1859 8022 #define mmDPG0_DPG_COLOUR_B_CB_BASE_IDX 2 8023 #define mmDPG0_DPG_OFFSET_SEGMENT 0x185a 8024 #define mmDPG0_DPG_OFFSET_SEGMENT_BASE_IDX 2 8025 #define mmDPG0_DPG_STATUS 0x185b 8026 #define mmDPG0_DPG_STATUS_BASE_IDX 2 8027 8028 8029 // addressBlock: dce_dc_opp_oppbuf0_dispdec 8030 // base address: 0x0 8031 #define mmOPPBUF0_OPPBUF_CONTROL 0x1884 8032 #define mmOPPBUF0_OPPBUF_CONTROL_BASE_IDX 2 8033 #define mmOPPBUF0_OPPBUF_3D_PARAMETERS_0 0x1885 8034 #define mmOPPBUF0_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2 8035 #define mmOPPBUF0_OPPBUF_3D_PARAMETERS_1 0x1886 8036 #define mmOPPBUF0_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2 8037 #define mmOPPBUF0_OPPBUF_CONTROL1 0x1889 8038 #define mmOPPBUF0_OPPBUF_CONTROL1_BASE_IDX 2 8039 8040 8041 // addressBlock: dce_dc_opp_opp_pipe0_dispdec 8042 // base address: 0x0 8043 #define mmOPP_PIPE0_OPP_PIPE_CONTROL 0x188c 8044 #define mmOPP_PIPE0_OPP_PIPE_CONTROL_BASE_IDX 2 8045 8046 8047 // addressBlock: dce_dc_opp_opp_pipe_crc0_dispdec 8048 // base address: 0x0 8049 #define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL 0x1891 8050 #define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL_BASE_IDX 2 8051 #define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK 0x1892 8052 #define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK_BASE_IDX 2 8053 #define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0 0x1893 8054 #define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0_BASE_IDX 2 8055 #define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1 0x1894 8056 #define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1_BASE_IDX 2 8057 #define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2 0x1895 8058 #define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2_BASE_IDX 2 8059 8060 8061 // addressBlock: dce_dc_opp_fmt1_dispdec 8062 // base address: 0x168 8063 #define mmFMT1_FMT_CLAMP_COMPONENT_R 0x1896 8064 #define mmFMT1_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 8065 #define mmFMT1_FMT_CLAMP_COMPONENT_G 0x1897 8066 #define mmFMT1_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 8067 #define mmFMT1_FMT_CLAMP_COMPONENT_B 0x1898 8068 #define mmFMT1_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 8069 #define mmFMT1_FMT_DYNAMIC_EXP_CNTL 0x1899 8070 #define mmFMT1_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 8071 #define mmFMT1_FMT_CONTROL 0x189a 8072 #define mmFMT1_FMT_CONTROL_BASE_IDX 2 8073 #define mmFMT1_FMT_BIT_DEPTH_CONTROL 0x189b 8074 #define mmFMT1_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 8075 #define mmFMT1_FMT_DITHER_RAND_R_SEED 0x189c 8076 #define mmFMT1_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 8077 #define mmFMT1_FMT_DITHER_RAND_G_SEED 0x189d 8078 #define mmFMT1_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 8079 #define mmFMT1_FMT_DITHER_RAND_B_SEED 0x189e 8080 #define mmFMT1_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 8081 #define mmFMT1_FMT_CLAMP_CNTL 0x189f 8082 #define mmFMT1_FMT_CLAMP_CNTL_BASE_IDX 2 8083 #define mmFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x18a0 8084 #define mmFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 8085 #define mmFMT1_FMT_MAP420_MEMORY_CONTROL 0x18a1 8086 #define mmFMT1_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2 8087 #define mmFMT1_FMT_422_CONTROL 0x18a3 8088 #define mmFMT1_FMT_422_CONTROL_BASE_IDX 2 8089 8090 8091 // addressBlock: dce_dc_opp_dpg1_dispdec 8092 // base address: 0x168 8093 #define mmDPG1_DPG_CONTROL 0x18ae 8094 #define mmDPG1_DPG_CONTROL_BASE_IDX 2 8095 #define mmDPG1_DPG_RAMP_CONTROL 0x18af 8096 #define mmDPG1_DPG_RAMP_CONTROL_BASE_IDX 2 8097 #define mmDPG1_DPG_DIMENSIONS 0x18b0 8098 #define mmDPG1_DPG_DIMENSIONS_BASE_IDX 2 8099 #define mmDPG1_DPG_COLOUR_R_CR 0x18b1 8100 #define mmDPG1_DPG_COLOUR_R_CR_BASE_IDX 2 8101 #define mmDPG1_DPG_COLOUR_G_Y 0x18b2 8102 #define mmDPG1_DPG_COLOUR_G_Y_BASE_IDX 2 8103 #define mmDPG1_DPG_COLOUR_B_CB 0x18b3 8104 #define mmDPG1_DPG_COLOUR_B_CB_BASE_IDX 2 8105 #define mmDPG1_DPG_OFFSET_SEGMENT 0x18b4 8106 #define mmDPG1_DPG_OFFSET_SEGMENT_BASE_IDX 2 8107 #define mmDPG1_DPG_STATUS 0x18b5 8108 #define mmDPG1_DPG_STATUS_BASE_IDX 2 8109 8110 8111 // addressBlock: dce_dc_opp_oppbuf1_dispdec 8112 // base address: 0x168 8113 #define mmOPPBUF1_OPPBUF_CONTROL 0x18de 8114 #define mmOPPBUF1_OPPBUF_CONTROL_BASE_IDX 2 8115 #define mmOPPBUF1_OPPBUF_3D_PARAMETERS_0 0x18df 8116 #define mmOPPBUF1_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2 8117 #define mmOPPBUF1_OPPBUF_3D_PARAMETERS_1 0x18e0 8118 #define mmOPPBUF1_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2 8119 #define mmOPPBUF1_OPPBUF_CONTROL1 0x18e3 8120 #define mmOPPBUF1_OPPBUF_CONTROL1_BASE_IDX 2 8121 8122 8123 // addressBlock: dce_dc_opp_opp_pipe1_dispdec 8124 // base address: 0x168 8125 #define mmOPP_PIPE1_OPP_PIPE_CONTROL 0x18e6 8126 #define mmOPP_PIPE1_OPP_PIPE_CONTROL_BASE_IDX 2 8127 8128 8129 // addressBlock: dce_dc_opp_opp_pipe_crc1_dispdec 8130 // base address: 0x168 8131 #define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL 0x18eb 8132 #define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL_BASE_IDX 2 8133 #define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK 0x18ec 8134 #define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK_BASE_IDX 2 8135 #define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0 0x18ed 8136 #define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0_BASE_IDX 2 8137 #define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1 0x18ee 8138 #define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1_BASE_IDX 2 8139 #define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2 0x18ef 8140 #define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2_BASE_IDX 2 8141 8142 8143 // addressBlock: dce_dc_opp_fmt2_dispdec 8144 // base address: 0x2d0 8145 #define mmFMT2_FMT_CLAMP_COMPONENT_R 0x18f0 8146 #define mmFMT2_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 8147 #define mmFMT2_FMT_CLAMP_COMPONENT_G 0x18f1 8148 #define mmFMT2_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 8149 #define mmFMT2_FMT_CLAMP_COMPONENT_B 0x18f2 8150 #define mmFMT2_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 8151 #define mmFMT2_FMT_DYNAMIC_EXP_CNTL 0x18f3 8152 #define mmFMT2_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 8153 #define mmFMT2_FMT_CONTROL 0x18f4 8154 #define mmFMT2_FMT_CONTROL_BASE_IDX 2 8155 #define mmFMT2_FMT_BIT_DEPTH_CONTROL 0x18f5 8156 #define mmFMT2_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 8157 #define mmFMT2_FMT_DITHER_RAND_R_SEED 0x18f6 8158 #define mmFMT2_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 8159 #define mmFMT2_FMT_DITHER_RAND_G_SEED 0x18f7 8160 #define mmFMT2_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 8161 #define mmFMT2_FMT_DITHER_RAND_B_SEED 0x18f8 8162 #define mmFMT2_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 8163 #define mmFMT2_FMT_CLAMP_CNTL 0x18f9 8164 #define mmFMT2_FMT_CLAMP_CNTL_BASE_IDX 2 8165 #define mmFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x18fa 8166 #define mmFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 8167 #define mmFMT2_FMT_MAP420_MEMORY_CONTROL 0x18fb 8168 #define mmFMT2_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2 8169 #define mmFMT2_FMT_422_CONTROL 0x18fd 8170 #define mmFMT2_FMT_422_CONTROL_BASE_IDX 2 8171 8172 8173 8174 // addressBlock: dce_dc_opp_dpg2_dispdec 8175 // base address: 0x2d0 8176 #define mmDPG2_DPG_CONTROL 0x1908 8177 #define mmDPG2_DPG_CONTROL_BASE_IDX 2 8178 #define mmDPG2_DPG_RAMP_CONTROL 0x1909 8179 #define mmDPG2_DPG_RAMP_CONTROL_BASE_IDX 2 8180 #define mmDPG2_DPG_DIMENSIONS 0x190a 8181 #define mmDPG2_DPG_DIMENSIONS_BASE_IDX 2 8182 #define mmDPG2_DPG_COLOUR_R_CR 0x190b 8183 #define mmDPG2_DPG_COLOUR_R_CR_BASE_IDX 2 8184 #define mmDPG2_DPG_COLOUR_G_Y 0x190c 8185 #define mmDPG2_DPG_COLOUR_G_Y_BASE_IDX 2 8186 #define mmDPG2_DPG_COLOUR_B_CB 0x190d 8187 #define mmDPG2_DPG_COLOUR_B_CB_BASE_IDX 2 8188 #define mmDPG2_DPG_OFFSET_SEGMENT 0x190e 8189 #define mmDPG2_DPG_OFFSET_SEGMENT_BASE_IDX 2 8190 #define mmDPG2_DPG_STATUS 0x190f 8191 #define mmDPG2_DPG_STATUS_BASE_IDX 2 8192 8193 8194 // addressBlock: dce_dc_opp_oppbuf2_dispdec 8195 // base address: 0x2d0 8196 #define mmOPPBUF2_OPPBUF_CONTROL 0x1938 8197 #define mmOPPBUF2_OPPBUF_CONTROL_BASE_IDX 2 8198 #define mmOPPBUF2_OPPBUF_3D_PARAMETERS_0 0x1939 8199 #define mmOPPBUF2_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2 8200 #define mmOPPBUF2_OPPBUF_3D_PARAMETERS_1 0x193a 8201 #define mmOPPBUF2_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2 8202 #define mmOPPBUF2_OPPBUF_CONTROL1 0x193d 8203 #define mmOPPBUF2_OPPBUF_CONTROL1_BASE_IDX 2 8204 8205 8206 // addressBlock: dce_dc_opp_opp_pipe2_dispdec 8207 // base address: 0x2d0 8208 #define mmOPP_PIPE2_OPP_PIPE_CONTROL 0x1940 8209 #define mmOPP_PIPE2_OPP_PIPE_CONTROL_BASE_IDX 2 8210 8211 8212 // addressBlock: dce_dc_opp_opp_pipe_crc2_dispdec 8213 // base address: 0x2d0 8214 #define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL 0x1945 8215 #define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL_BASE_IDX 2 8216 #define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_MASK 0x1946 8217 #define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_MASK_BASE_IDX 2 8218 #define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0 0x1947 8219 #define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0_BASE_IDX 2 8220 #define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1 0x1948 8221 #define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1_BASE_IDX 2 8222 #define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2 0x1949 8223 #define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2_BASE_IDX 2 8224 8225 8226 // addressBlock: dce_dc_opp_fmt3_dispdec 8227 // base address: 0x438 8228 #define mmFMT3_FMT_CLAMP_COMPONENT_R 0x194a 8229 #define mmFMT3_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 8230 #define mmFMT3_FMT_CLAMP_COMPONENT_G 0x194b 8231 #define mmFMT3_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 8232 #define mmFMT3_FMT_CLAMP_COMPONENT_B 0x194c 8233 #define mmFMT3_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 8234 #define mmFMT3_FMT_DYNAMIC_EXP_CNTL 0x194d 8235 #define mmFMT3_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 8236 #define mmFMT3_FMT_CONTROL 0x194e 8237 #define mmFMT3_FMT_CONTROL_BASE_IDX 2 8238 #define mmFMT3_FMT_BIT_DEPTH_CONTROL 0x194f 8239 #define mmFMT3_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 8240 #define mmFMT3_FMT_DITHER_RAND_R_SEED 0x1950 8241 #define mmFMT3_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 8242 #define mmFMT3_FMT_DITHER_RAND_G_SEED 0x1951 8243 #define mmFMT3_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 8244 #define mmFMT3_FMT_DITHER_RAND_B_SEED 0x1952 8245 #define mmFMT3_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 8246 #define mmFMT3_FMT_CLAMP_CNTL 0x1953 8247 #define mmFMT3_FMT_CLAMP_CNTL_BASE_IDX 2 8248 #define mmFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x1954 8249 #define mmFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 8250 #define mmFMT3_FMT_MAP420_MEMORY_CONTROL 0x1955 8251 #define mmFMT3_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2 8252 #define mmFMT3_FMT_422_CONTROL 0x1957 8253 #define mmFMT3_FMT_422_CONTROL_BASE_IDX 2 8254 8255 8256 // addressBlock: dce_dc_opp_dpg3_dispdec 8257 // base address: 0x438 8258 #define mmDPG3_DPG_CONTROL 0x1962 8259 #define mmDPG3_DPG_CONTROL_BASE_IDX 2 8260 #define mmDPG3_DPG_RAMP_CONTROL 0x1963 8261 #define mmDPG3_DPG_RAMP_CONTROL_BASE_IDX 2 8262 #define mmDPG3_DPG_DIMENSIONS 0x1964 8263 #define mmDPG3_DPG_DIMENSIONS_BASE_IDX 2 8264 #define mmDPG3_DPG_COLOUR_R_CR 0x1965 8265 #define mmDPG3_DPG_COLOUR_R_CR_BASE_IDX 2 8266 #define mmDPG3_DPG_COLOUR_G_Y 0x1966 8267 #define mmDPG3_DPG_COLOUR_G_Y_BASE_IDX 2 8268 #define mmDPG3_DPG_COLOUR_B_CB 0x1967 8269 #define mmDPG3_DPG_COLOUR_B_CB_BASE_IDX 2 8270 #define mmDPG3_DPG_OFFSET_SEGMENT 0x1968 8271 #define mmDPG3_DPG_OFFSET_SEGMENT_BASE_IDX 2 8272 #define mmDPG3_DPG_STATUS 0x1969 8273 #define mmDPG3_DPG_STATUS_BASE_IDX 2 8274 8275 8276 // addressBlock: dce_dc_opp_oppbuf3_dispdec 8277 // base address: 0x438 8278 #define mmOPPBUF3_OPPBUF_CONTROL 0x1992 8279 #define mmOPPBUF3_OPPBUF_CONTROL_BASE_IDX 2 8280 #define mmOPPBUF3_OPPBUF_3D_PARAMETERS_0 0x1993 8281 #define mmOPPBUF3_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2 8282 #define mmOPPBUF3_OPPBUF_3D_PARAMETERS_1 0x1994 8283 #define mmOPPBUF3_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2 8284 #define mmOPPBUF3_OPPBUF_CONTROL1 0x1997 8285 #define mmOPPBUF3_OPPBUF_CONTROL1_BASE_IDX 2 8286 8287 8288 // addressBlock: dce_dc_opp_opp_pipe3_dispdec 8289 // base address: 0x438 8290 #define mmOPP_PIPE3_OPP_PIPE_CONTROL 0x199a 8291 #define mmOPP_PIPE3_OPP_PIPE_CONTROL_BASE_IDX 2 8292 8293 // addressBlock: dce_dc_opp_opp_pipe_crc3_dispdec 8294 // base address: 0x438 8295 #define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL 0x199f 8296 #define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL_BASE_IDX 2 8297 #define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_MASK 0x19a0 8298 #define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_MASK_BASE_IDX 2 8299 #define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0 0x19a1 8300 #define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0_BASE_IDX 2 8301 #define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1 0x19a2 8302 #define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1_BASE_IDX 2 8303 #define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2 0x19a3 8304 #define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2_BASE_IDX 2 8305 8306 8307 // addressBlock: dce_dc_opp_fmt4_dispdec 8308 // base address: 0x5a0 8309 #define mmFMT4_FMT_CLAMP_COMPONENT_R 0x19a4 8310 #define mmFMT4_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 8311 #define mmFMT4_FMT_CLAMP_COMPONENT_G 0x19a5 8312 #define mmFMT4_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 8313 #define mmFMT4_FMT_CLAMP_COMPONENT_B 0x19a6 8314 #define mmFMT4_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 8315 #define mmFMT4_FMT_DYNAMIC_EXP_CNTL 0x19a7 8316 #define mmFMT4_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 8317 #define mmFMT4_FMT_CONTROL 0x19a8 8318 #define mmFMT4_FMT_CONTROL_BASE_IDX 2 8319 #define mmFMT4_FMT_BIT_DEPTH_CONTROL 0x19a9 8320 #define mmFMT4_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 8321 #define mmFMT4_FMT_DITHER_RAND_R_SEED 0x19aa 8322 #define mmFMT4_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 8323 #define mmFMT4_FMT_DITHER_RAND_G_SEED 0x19ab 8324 #define mmFMT4_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 8325 #define mmFMT4_FMT_DITHER_RAND_B_SEED 0x19ac 8326 #define mmFMT4_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 8327 #define mmFMT4_FMT_CLAMP_CNTL 0x19ad 8328 #define mmFMT4_FMT_CLAMP_CNTL_BASE_IDX 2 8329 #define mmFMT4_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x19ae 8330 #define mmFMT4_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 8331 #define mmFMT4_FMT_MAP420_MEMORY_CONTROL 0x19af 8332 #define mmFMT4_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2 8333 #define mmFMT4_FMT_422_CONTROL 0x19b1 8334 #define mmFMT4_FMT_422_CONTROL_BASE_IDX 2 8335 8336 8337 8338 // addressBlock: dce_dc_opp_dpg4_dispdec 8339 // base address: 0x5a0 8340 #define mmDPG4_DPG_CONTROL 0x19bc 8341 #define mmDPG4_DPG_CONTROL_BASE_IDX 2 8342 #define mmDPG4_DPG_RAMP_CONTROL 0x19bd 8343 #define mmDPG4_DPG_RAMP_CONTROL_BASE_IDX 2 8344 #define mmDPG4_DPG_DIMENSIONS 0x19be 8345 #define mmDPG4_DPG_DIMENSIONS_BASE_IDX 2 8346 #define mmDPG4_DPG_COLOUR_R_CR 0x19bf 8347 #define mmDPG4_DPG_COLOUR_R_CR_BASE_IDX 2 8348 #define mmDPG4_DPG_COLOUR_G_Y 0x19c0 8349 #define mmDPG4_DPG_COLOUR_G_Y_BASE_IDX 2 8350 #define mmDPG4_DPG_COLOUR_B_CB 0x19c1 8351 #define mmDPG4_DPG_COLOUR_B_CB_BASE_IDX 2 8352 #define mmDPG4_DPG_OFFSET_SEGMENT 0x19c2 8353 #define mmDPG4_DPG_OFFSET_SEGMENT_BASE_IDX 2 8354 #define mmDPG4_DPG_STATUS 0x19c3 8355 #define mmDPG4_DPG_STATUS_BASE_IDX 2 8356 8357 8358 // addressBlock: dce_dc_opp_oppbuf4_dispdec 8359 // base address: 0x5a0 8360 #define mmOPPBUF4_OPPBUF_CONTROL 0x19ec 8361 #define mmOPPBUF4_OPPBUF_CONTROL_BASE_IDX 2 8362 #define mmOPPBUF4_OPPBUF_3D_PARAMETERS_0 0x19ed 8363 #define mmOPPBUF4_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2 8364 #define mmOPPBUF4_OPPBUF_3D_PARAMETERS_1 0x19ee 8365 #define mmOPPBUF4_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2 8366 #define mmOPPBUF4_OPPBUF_CONTROL1 0x19f1 8367 #define mmOPPBUF4_OPPBUF_CONTROL1_BASE_IDX 2 8368 8369 8370 // addressBlock: dce_dc_opp_opp_pipe4_dispdec 8371 // base address: 0x5a0 8372 #define mmOPP_PIPE4_OPP_PIPE_CONTROL 0x19f4 8373 #define mmOPP_PIPE4_OPP_PIPE_CONTROL_BASE_IDX 2 8374 8375 // addressBlock: dce_dc_opp_opp_pipe_crc4_dispdec 8376 // base address: 0x5a0 8377 #define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL 0x19f9 8378 #define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL_BASE_IDX 2 8379 #define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_MASK 0x19fa 8380 #define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_MASK_BASE_IDX 2 8381 #define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT0 0x19fb 8382 #define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT0_BASE_IDX 2 8383 #define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT1 0x19fc 8384 #define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT1_BASE_IDX 2 8385 #define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT2 0x19fd 8386 #define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT2_BASE_IDX 2 8387 8388 8389 // addressBlock: dce_dc_opp_fmt5_dispdec 8390 // base address: 0x708 8391 #define mmFMT5_FMT_CLAMP_COMPONENT_R 0x19fe 8392 #define mmFMT5_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 8393 #define mmFMT5_FMT_CLAMP_COMPONENT_G 0x19ff 8394 #define mmFMT5_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 8395 #define mmFMT5_FMT_CLAMP_COMPONENT_B 0x1a00 8396 #define mmFMT5_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 8397 #define mmFMT5_FMT_DYNAMIC_EXP_CNTL 0x1a01 8398 #define mmFMT5_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 8399 #define mmFMT5_FMT_CONTROL 0x1a02 8400 #define mmFMT5_FMT_CONTROL_BASE_IDX 2 8401 #define mmFMT5_FMT_BIT_DEPTH_CONTROL 0x1a03 8402 #define mmFMT5_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 8403 #define mmFMT5_FMT_DITHER_RAND_R_SEED 0x1a04 8404 #define mmFMT5_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 8405 #define mmFMT5_FMT_DITHER_RAND_G_SEED 0x1a05 8406 #define mmFMT5_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 8407 #define mmFMT5_FMT_DITHER_RAND_B_SEED 0x1a06 8408 #define mmFMT5_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 8409 #define mmFMT5_FMT_CLAMP_CNTL 0x1a07 8410 #define mmFMT5_FMT_CLAMP_CNTL_BASE_IDX 2 8411 #define mmFMT5_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x1a08 8412 #define mmFMT5_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 8413 #define mmFMT5_FMT_MAP420_MEMORY_CONTROL 0x1a09 8414 #define mmFMT5_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2 8415 #define mmFMT5_FMT_422_CONTROL 0x1a0b 8416 #define mmFMT5_FMT_422_CONTROL_BASE_IDX 2 8417 8418 8419 // addressBlock: dce_dc_opp_dpg5_dispdec 8420 // base address: 0x708 8421 #define mmDPG5_DPG_CONTROL 0x1a16 8422 #define mmDPG5_DPG_CONTROL_BASE_IDX 2 8423 #define mmDPG5_DPG_RAMP_CONTROL 0x1a17 8424 #define mmDPG5_DPG_RAMP_CONTROL_BASE_IDX 2 8425 #define mmDPG5_DPG_DIMENSIONS 0x1a18 8426 #define mmDPG5_DPG_DIMENSIONS_BASE_IDX 2 8427 #define mmDPG5_DPG_COLOUR_R_CR 0x1a19 8428 #define mmDPG5_DPG_COLOUR_R_CR_BASE_IDX 2 8429 #define mmDPG5_DPG_COLOUR_G_Y 0x1a1a 8430 #define mmDPG5_DPG_COLOUR_G_Y_BASE_IDX 2 8431 #define mmDPG5_DPG_COLOUR_B_CB 0x1a1b 8432 #define mmDPG5_DPG_COLOUR_B_CB_BASE_IDX 2 8433 #define mmDPG5_DPG_OFFSET_SEGMENT 0x1a1c 8434 #define mmDPG5_DPG_OFFSET_SEGMENT_BASE_IDX 2 8435 #define mmDPG5_DPG_STATUS 0x1a1d 8436 #define mmDPG5_DPG_STATUS_BASE_IDX 2 8437 8438 8439 // addressBlock: dce_dc_opp_oppbuf5_dispdec 8440 // base address: 0x708 8441 #define mmOPPBUF5_OPPBUF_CONTROL 0x1a46 8442 #define mmOPPBUF5_OPPBUF_CONTROL_BASE_IDX 2 8443 #define mmOPPBUF5_OPPBUF_3D_PARAMETERS_0 0x1a47 8444 #define mmOPPBUF5_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2 8445 #define mmOPPBUF5_OPPBUF_3D_PARAMETERS_1 0x1a48 8446 #define mmOPPBUF5_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2 8447 #define mmOPPBUF5_OPPBUF_CONTROL1 0x1a4b 8448 #define mmOPPBUF5_OPPBUF_CONTROL1_BASE_IDX 2 8449 8450 8451 // addressBlock: dce_dc_opp_opp_pipe5_dispdec 8452 // base address: 0x708 8453 #define mmOPP_PIPE5_OPP_PIPE_CONTROL 0x1a4e 8454 #define mmOPP_PIPE5_OPP_PIPE_CONTROL_BASE_IDX 2 8455 8456 8457 // addressBlock: dce_dc_opp_opp_pipe_crc5_dispdec 8458 // base address: 0x708 8459 #define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL 0x1a53 8460 #define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL_BASE_IDX 2 8461 #define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_MASK 0x1a54 8462 #define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_MASK_BASE_IDX 2 8463 #define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT0 0x1a55 8464 #define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT0_BASE_IDX 2 8465 #define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT1 0x1a56 8466 #define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT1_BASE_IDX 2 8467 #define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT2 0x1a57 8468 #define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT2_BASE_IDX 2 8469 8470 8471 // addressBlock: dce_dc_opp_opp_top_dispdec 8472 // base address: 0x0 8473 #define mmOPP_TOP_CLK_CONTROL 0x1a5e 8474 #define mmOPP_TOP_CLK_CONTROL_BASE_IDX 2 8475 #define mmOPP_ABM_CONTROL 0x1a60 8476 #define mmOPP_ABM_CONTROL_BASE_IDX 2 8477 8478 8479 // addressBlock: dce_dc_opp_dscrm0_dispdec 8480 // base address: 0x0 8481 #define mmDSCRM0_DSCRM_DSC_FORWARD_CONFIG 0x1a64 8482 #define mmDSCRM0_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2 8483 8484 8485 // addressBlock: dce_dc_opp_dscrm1_dispdec 8486 // base address: 0x4 8487 #define mmDSCRM1_DSCRM_DSC_FORWARD_CONFIG 0x1a65 8488 #define mmDSCRM1_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2 8489 8490 8491 // addressBlock: dce_dc_opp_dscrm2_dispdec 8492 // base address: 0x8 8493 #define mmDSCRM2_DSCRM_DSC_FORWARD_CONFIG 0x1a66 8494 #define mmDSCRM2_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2 8495 8496 8497 // addressBlock: dce_dc_opp_dscrm3_dispdec 8498 // base address: 0xc 8499 #define mmDSCRM3_DSCRM_DSC_FORWARD_CONFIG 0x1a67 8500 #define mmDSCRM3_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2 8501 8502 8503 // addressBlock: dce_dc_opp_dscrm4_dispdec 8504 // base address: 0x10 8505 #define mmDSCRM4_DSCRM_DSC_FORWARD_CONFIG 0x1a68 8506 #define mmDSCRM4_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2 8507 8508 8509 // addressBlock: dce_dc_opp_dscrm5_dispdec 8510 // base address: 0x14 8511 #define mmDSCRM5_DSCRM_DSC_FORWARD_CONFIG 0x1a69 8512 #define mmDSCRM5_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2 8513 8514 8515 // addressBlock: dce_dc_opp_opp_dcperfmon_dc_perfmon_dispdec 8516 // base address: 0x6af8 8517 #define mmDC_PERFMON18_PERFCOUNTER_CNTL 0x1abe 8518 #define mmDC_PERFMON18_PERFCOUNTER_CNTL_BASE_IDX 2 8519 #define mmDC_PERFMON18_PERFCOUNTER_CNTL2 0x1abf 8520 #define mmDC_PERFMON18_PERFCOUNTER_CNTL2_BASE_IDX 2 8521 #define mmDC_PERFMON18_PERFCOUNTER_STATE 0x1ac0 8522 #define mmDC_PERFMON18_PERFCOUNTER_STATE_BASE_IDX 2 8523 #define mmDC_PERFMON18_PERFMON_CNTL 0x1ac1 8524 #define mmDC_PERFMON18_PERFMON_CNTL_BASE_IDX 2 8525 #define mmDC_PERFMON18_PERFMON_CNTL2 0x1ac2 8526 #define mmDC_PERFMON18_PERFMON_CNTL2_BASE_IDX 2 8527 #define mmDC_PERFMON18_PERFMON_CVALUE_INT_MISC 0x1ac3 8528 #define mmDC_PERFMON18_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 8529 #define mmDC_PERFMON18_PERFMON_CVALUE_LOW 0x1ac4 8530 #define mmDC_PERFMON18_PERFMON_CVALUE_LOW_BASE_IDX 2 8531 #define mmDC_PERFMON18_PERFMON_HI 0x1ac5 8532 #define mmDC_PERFMON18_PERFMON_HI_BASE_IDX 2 8533 #define mmDC_PERFMON18_PERFMON_LOW 0x1ac6 8534 #define mmDC_PERFMON18_PERFMON_LOW_BASE_IDX 2 8535 8536 8537 // addressBlock: dce_dc_optc_odm0_dispdec 8538 // base address: 0x0 8539 #define mmODM0_OPTC_INPUT_GLOBAL_CONTROL 0x1aca 8540 #define mmODM0_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2 8541 #define mmODM0_OPTC_DATA_SOURCE_SELECT 0x1acb 8542 #define mmODM0_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2 8543 #define mmODM0_OPTC_DATA_FORMAT_CONTROL 0x1acc 8544 #define mmODM0_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2 8545 #define mmODM0_OPTC_BYTES_PER_PIXEL 0x1acd 8546 #define mmODM0_OPTC_BYTES_PER_PIXEL_BASE_IDX 2 8547 #define mmODM0_OPTC_WIDTH_CONTROL 0x1ace 8548 #define mmODM0_OPTC_WIDTH_CONTROL_BASE_IDX 2 8549 #define mmODM0_OPTC_INPUT_CLOCK_CONTROL 0x1acf 8550 #define mmODM0_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2 8551 #define mmODM0_OPTC_MEMORY_CONFIG 0x1ad0 8552 #define mmODM0_OPTC_MEMORY_CONFIG_BASE_IDX 2 8553 #define mmODM0_OPTC_INPUT_SPARE_REGISTER 0x1ad1 8554 #define mmODM0_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2 8555 8556 8557 // addressBlock: dce_dc_optc_odm1_dispdec 8558 // base address: 0x40 8559 #define mmODM1_OPTC_INPUT_GLOBAL_CONTROL 0x1ada 8560 #define mmODM1_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2 8561 #define mmODM1_OPTC_DATA_SOURCE_SELECT 0x1adb 8562 #define mmODM1_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2 8563 #define mmODM1_OPTC_DATA_FORMAT_CONTROL 0x1adc 8564 #define mmODM1_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2 8565 #define mmODM1_OPTC_BYTES_PER_PIXEL 0x1add 8566 #define mmODM1_OPTC_BYTES_PER_PIXEL_BASE_IDX 2 8567 #define mmODM1_OPTC_WIDTH_CONTROL 0x1ade 8568 #define mmODM1_OPTC_WIDTH_CONTROL_BASE_IDX 2 8569 #define mmODM1_OPTC_INPUT_CLOCK_CONTROL 0x1adf 8570 #define mmODM1_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2 8571 #define mmODM1_OPTC_MEMORY_CONFIG 0x1ae0 8572 #define mmODM1_OPTC_MEMORY_CONFIG_BASE_IDX 2 8573 #define mmODM1_OPTC_INPUT_SPARE_REGISTER 0x1ae1 8574 #define mmODM1_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2 8575 8576 8577 // addressBlock: dce_dc_optc_odm2_dispdec 8578 // base address: 0x80 8579 #define mmODM2_OPTC_INPUT_GLOBAL_CONTROL 0x1aea 8580 #define mmODM2_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2 8581 #define mmODM2_OPTC_DATA_SOURCE_SELECT 0x1aeb 8582 #define mmODM2_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2 8583 #define mmODM2_OPTC_DATA_FORMAT_CONTROL 0x1aec 8584 #define mmODM2_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2 8585 #define mmODM2_OPTC_BYTES_PER_PIXEL 0x1aed 8586 #define mmODM2_OPTC_BYTES_PER_PIXEL_BASE_IDX 2 8587 #define mmODM2_OPTC_WIDTH_CONTROL 0x1aee 8588 #define mmODM2_OPTC_WIDTH_CONTROL_BASE_IDX 2 8589 #define mmODM2_OPTC_INPUT_CLOCK_CONTROL 0x1aef 8590 #define mmODM2_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2 8591 #define mmODM2_OPTC_MEMORY_CONFIG 0x1af0 8592 #define mmODM2_OPTC_MEMORY_CONFIG_BASE_IDX 2 8593 #define mmODM2_OPTC_INPUT_SPARE_REGISTER 0x1af1 8594 #define mmODM2_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2 8595 8596 8597 // addressBlock: dce_dc_optc_odm3_dispdec 8598 // base address: 0xc0 8599 #define mmODM3_OPTC_INPUT_GLOBAL_CONTROL 0x1afa 8600 #define mmODM3_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2 8601 #define mmODM3_OPTC_DATA_SOURCE_SELECT 0x1afb 8602 #define mmODM3_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2 8603 #define mmODM3_OPTC_DATA_FORMAT_CONTROL 0x1afc 8604 #define mmODM3_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2 8605 #define mmODM3_OPTC_BYTES_PER_PIXEL 0x1afd 8606 #define mmODM3_OPTC_BYTES_PER_PIXEL_BASE_IDX 2 8607 #define mmODM3_OPTC_WIDTH_CONTROL 0x1afe 8608 #define mmODM3_OPTC_WIDTH_CONTROL_BASE_IDX 2 8609 #define mmODM3_OPTC_INPUT_CLOCK_CONTROL 0x1aff 8610 #define mmODM3_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2 8611 #define mmODM3_OPTC_MEMORY_CONFIG 0x1b00 8612 #define mmODM3_OPTC_MEMORY_CONFIG_BASE_IDX 2 8613 #define mmODM3_OPTC_INPUT_SPARE_REGISTER 0x1b01 8614 #define mmODM3_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2 8615 8616 8617 // addressBlock: dce_dc_optc_odm4_dispdec 8618 // base address: 0x100 8619 #define mmODM4_OPTC_INPUT_GLOBAL_CONTROL 0x1b0a 8620 #define mmODM4_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2 8621 #define mmODM4_OPTC_DATA_SOURCE_SELECT 0x1b0b 8622 #define mmODM4_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2 8623 #define mmODM4_OPTC_DATA_FORMAT_CONTROL 0x1b0c 8624 #define mmODM4_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2 8625 #define mmODM4_OPTC_BYTES_PER_PIXEL 0x1b0d 8626 #define mmODM4_OPTC_BYTES_PER_PIXEL_BASE_IDX 2 8627 #define mmODM4_OPTC_WIDTH_CONTROL 0x1b0e 8628 #define mmODM4_OPTC_WIDTH_CONTROL_BASE_IDX 2 8629 #define mmODM4_OPTC_INPUT_CLOCK_CONTROL 0x1b0f 8630 #define mmODM4_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2 8631 #define mmODM4_OPTC_MEMORY_CONFIG 0x1b10 8632 #define mmODM4_OPTC_MEMORY_CONFIG_BASE_IDX 2 8633 #define mmODM4_OPTC_INPUT_SPARE_REGISTER 0x1b11 8634 #define mmODM4_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2 8635 8636 8637 // addressBlock: dce_dc_optc_odm5_dispdec 8638 // base address: 0x140 8639 #define mmODM5_OPTC_INPUT_GLOBAL_CONTROL 0x1b1a 8640 #define mmODM5_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2 8641 #define mmODM5_OPTC_DATA_SOURCE_SELECT 0x1b1b 8642 #define mmODM5_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2 8643 #define mmODM5_OPTC_DATA_FORMAT_CONTROL 0x1b1c 8644 #define mmODM5_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2 8645 #define mmODM5_OPTC_BYTES_PER_PIXEL 0x1b1d 8646 #define mmODM5_OPTC_BYTES_PER_PIXEL_BASE_IDX 2 8647 #define mmODM5_OPTC_WIDTH_CONTROL 0x1b1e 8648 #define mmODM5_OPTC_WIDTH_CONTROL_BASE_IDX 2 8649 #define mmODM5_OPTC_INPUT_CLOCK_CONTROL 0x1b1f 8650 #define mmODM5_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2 8651 #define mmODM5_OPTC_MEMORY_CONFIG 0x1b20 8652 #define mmODM5_OPTC_MEMORY_CONFIG_BASE_IDX 2 8653 #define mmODM5_OPTC_INPUT_SPARE_REGISTER 0x1b21 8654 #define mmODM5_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2 8655 8656 8657 // addressBlock: dce_dc_optc_otg0_dispdec 8658 // base address: 0x0 8659 #define mmOTG0_OTG_H_TOTAL 0x1b2a 8660 #define mmOTG0_OTG_H_TOTAL_BASE_IDX 2 8661 #define mmOTG0_OTG_H_BLANK_START_END 0x1b2b 8662 #define mmOTG0_OTG_H_BLANK_START_END_BASE_IDX 2 8663 #define mmOTG0_OTG_H_SYNC_A 0x1b2c 8664 #define mmOTG0_OTG_H_SYNC_A_BASE_IDX 2 8665 #define mmOTG0_OTG_H_SYNC_A_CNTL 0x1b2d 8666 #define mmOTG0_OTG_H_SYNC_A_CNTL_BASE_IDX 2 8667 #define mmOTG0_OTG_H_TIMING_CNTL 0x1b2e 8668 #define mmOTG0_OTG_H_TIMING_CNTL_BASE_IDX 2 8669 #define mmOTG0_OTG_V_TOTAL 0x1b2f 8670 #define mmOTG0_OTG_V_TOTAL_BASE_IDX 2 8671 #define mmOTG0_OTG_V_TOTAL_MIN 0x1b30 8672 #define mmOTG0_OTG_V_TOTAL_MIN_BASE_IDX 2 8673 #define mmOTG0_OTG_V_TOTAL_MAX 0x1b31 8674 #define mmOTG0_OTG_V_TOTAL_MAX_BASE_IDX 2 8675 #define mmOTG0_OTG_V_TOTAL_MID 0x1b32 8676 #define mmOTG0_OTG_V_TOTAL_MID_BASE_IDX 2 8677 #define mmOTG0_OTG_V_TOTAL_CONTROL 0x1b33 8678 #define mmOTG0_OTG_V_TOTAL_CONTROL_BASE_IDX 2 8679 #define mmOTG0_OTG_V_TOTAL_INT_STATUS 0x1b34 8680 #define mmOTG0_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2 8681 #define mmOTG0_OTG_VSYNC_NOM_INT_STATUS 0x1b35 8682 #define mmOTG0_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2 8683 #define mmOTG0_OTG_V_BLANK_START_END 0x1b36 8684 #define mmOTG0_OTG_V_BLANK_START_END_BASE_IDX 2 8685 #define mmOTG0_OTG_V_SYNC_A 0x1b37 8686 #define mmOTG0_OTG_V_SYNC_A_BASE_IDX 2 8687 #define mmOTG0_OTG_V_SYNC_A_CNTL 0x1b38 8688 #define mmOTG0_OTG_V_SYNC_A_CNTL_BASE_IDX 2 8689 #define mmOTG0_OTG_TRIGA_CNTL 0x1b39 8690 #define mmOTG0_OTG_TRIGA_CNTL_BASE_IDX 2 8691 #define mmOTG0_OTG_TRIGA_MANUAL_TRIG 0x1b3a 8692 #define mmOTG0_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2 8693 #define mmOTG0_OTG_TRIGB_CNTL 0x1b3b 8694 #define mmOTG0_OTG_TRIGB_CNTL_BASE_IDX 2 8695 #define mmOTG0_OTG_TRIGB_MANUAL_TRIG 0x1b3c 8696 #define mmOTG0_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2 8697 #define mmOTG0_OTG_FORCE_COUNT_NOW_CNTL 0x1b3d 8698 #define mmOTG0_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 8699 #define mmOTG0_OTG_FLOW_CONTROL 0x1b3e 8700 #define mmOTG0_OTG_FLOW_CONTROL_BASE_IDX 2 8701 #define mmOTG0_OTG_STEREO_FORCE_NEXT_EYE 0x1b3f 8702 #define mmOTG0_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 8703 #define mmOTG0_OTG_CONTROL 0x1b41 8704 #define mmOTG0_OTG_CONTROL_BASE_IDX 2 8705 #define mmOTG0_OTG_BLANK_CONTROL 0x1b42 8706 #define mmOTG0_OTG_BLANK_CONTROL_BASE_IDX 2 8707 #define mmOTG0_OTG_INTERLACE_CONTROL 0x1b44 8708 #define mmOTG0_OTG_INTERLACE_CONTROL_BASE_IDX 2 8709 #define mmOTG0_OTG_INTERLACE_STATUS 0x1b45 8710 #define mmOTG0_OTG_INTERLACE_STATUS_BASE_IDX 2 8711 #define mmOTG0_OTG_PIXEL_DATA_READBACK0 0x1b47 8712 #define mmOTG0_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2 8713 #define mmOTG0_OTG_PIXEL_DATA_READBACK1 0x1b48 8714 #define mmOTG0_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2 8715 #define mmOTG0_OTG_STATUS 0x1b49 8716 #define mmOTG0_OTG_STATUS_BASE_IDX 2 8717 #define mmOTG0_OTG_STATUS_POSITION 0x1b4a 8718 #define mmOTG0_OTG_STATUS_POSITION_BASE_IDX 2 8719 #define mmOTG0_OTG_NOM_VERT_POSITION 0x1b4b 8720 #define mmOTG0_OTG_NOM_VERT_POSITION_BASE_IDX 2 8721 #define mmOTG0_OTG_STATUS_FRAME_COUNT 0x1b4c 8722 #define mmOTG0_OTG_STATUS_FRAME_COUNT_BASE_IDX 2 8723 #define mmOTG0_OTG_STATUS_VF_COUNT 0x1b4d 8724 #define mmOTG0_OTG_STATUS_VF_COUNT_BASE_IDX 2 8725 #define mmOTG0_OTG_STATUS_HV_COUNT 0x1b4e 8726 #define mmOTG0_OTG_STATUS_HV_COUNT_BASE_IDX 2 8727 #define mmOTG0_OTG_COUNT_CONTROL 0x1b4f 8728 #define mmOTG0_OTG_COUNT_CONTROL_BASE_IDX 2 8729 #define mmOTG0_OTG_COUNT_RESET 0x1b50 8730 #define mmOTG0_OTG_COUNT_RESET_BASE_IDX 2 8731 #define mmOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1b51 8732 #define mmOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 8733 #define mmOTG0_OTG_VERT_SYNC_CONTROL 0x1b52 8734 #define mmOTG0_OTG_VERT_SYNC_CONTROL_BASE_IDX 2 8735 #define mmOTG0_OTG_STEREO_STATUS 0x1b53 8736 #define mmOTG0_OTG_STEREO_STATUS_BASE_IDX 2 8737 #define mmOTG0_OTG_STEREO_CONTROL 0x1b54 8738 #define mmOTG0_OTG_STEREO_CONTROL_BASE_IDX 2 8739 #define mmOTG0_OTG_SNAPSHOT_STATUS 0x1b55 8740 #define mmOTG0_OTG_SNAPSHOT_STATUS_BASE_IDX 2 8741 #define mmOTG0_OTG_SNAPSHOT_CONTROL 0x1b56 8742 #define mmOTG0_OTG_SNAPSHOT_CONTROL_BASE_IDX 2 8743 #define mmOTG0_OTG_SNAPSHOT_POSITION 0x1b57 8744 #define mmOTG0_OTG_SNAPSHOT_POSITION_BASE_IDX 2 8745 #define mmOTG0_OTG_SNAPSHOT_FRAME 0x1b58 8746 #define mmOTG0_OTG_SNAPSHOT_FRAME_BASE_IDX 2 8747 #define mmOTG0_OTG_INTERRUPT_CONTROL 0x1b59 8748 #define mmOTG0_OTG_INTERRUPT_CONTROL_BASE_IDX 2 8749 #define mmOTG0_OTG_UPDATE_LOCK 0x1b5a 8750 #define mmOTG0_OTG_UPDATE_LOCK_BASE_IDX 2 8751 #define mmOTG0_OTG_DOUBLE_BUFFER_CONTROL 0x1b5b 8752 #define mmOTG0_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 8753 #define mmOTG0_OTG_MASTER_EN 0x1b5c 8754 #define mmOTG0_OTG_MASTER_EN_BASE_IDX 2 8755 #define mmOTG0_OTG_BLANK_DATA_COLOR 0x1b5e 8756 #define mmOTG0_OTG_BLANK_DATA_COLOR_BASE_IDX 2 8757 #define mmOTG0_OTG_BLANK_DATA_COLOR_EXT 0x1b5f 8758 #define mmOTG0_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX 2 8759 #define mmOTG0_OTG_VERTICAL_INTERRUPT0_POSITION 0x1b62 8760 #define mmOTG0_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 8761 #define mmOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1b63 8762 #define mmOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 8763 #define mmOTG0_OTG_VERTICAL_INTERRUPT1_POSITION 0x1b64 8764 #define mmOTG0_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 8765 #define mmOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1b65 8766 #define mmOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 8767 #define mmOTG0_OTG_VERTICAL_INTERRUPT2_POSITION 0x1b66 8768 #define mmOTG0_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 8769 #define mmOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1b67 8770 #define mmOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 8771 #define mmOTG0_OTG_CRC_CNTL 0x1b68 8772 #define mmOTG0_OTG_CRC_CNTL_BASE_IDX 2 8773 #define mmOTG0_OTG_CRC_CNTL2 0x1b69 8774 #define mmOTG0_OTG_CRC_CNTL2_BASE_IDX 2 8775 #define mmOTG0_OTG_CRC0_WINDOWA_X_CONTROL 0x1b6a 8776 #define mmOTG0_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 8777 #define mmOTG0_OTG_CRC0_WINDOWA_Y_CONTROL 0x1b6b 8778 #define mmOTG0_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 8779 #define mmOTG0_OTG_CRC0_WINDOWB_X_CONTROL 0x1b6c 8780 #define mmOTG0_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 8781 #define mmOTG0_OTG_CRC0_WINDOWB_Y_CONTROL 0x1b6d 8782 #define mmOTG0_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 8783 #define mmOTG0_OTG_CRC0_DATA_RG 0x1b6e 8784 #define mmOTG0_OTG_CRC0_DATA_RG_BASE_IDX 2 8785 #define mmOTG0_OTG_CRC0_DATA_B 0x1b6f 8786 #define mmOTG0_OTG_CRC0_DATA_B_BASE_IDX 2 8787 #define mmOTG0_OTG_CRC1_WINDOWA_X_CONTROL 0x1b70 8788 #define mmOTG0_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 8789 #define mmOTG0_OTG_CRC1_WINDOWA_Y_CONTROL 0x1b71 8790 #define mmOTG0_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 8791 #define mmOTG0_OTG_CRC1_WINDOWB_X_CONTROL 0x1b72 8792 #define mmOTG0_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 8793 #define mmOTG0_OTG_CRC1_WINDOWB_Y_CONTROL 0x1b73 8794 #define mmOTG0_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 8795 #define mmOTG0_OTG_CRC1_DATA_RG 0x1b74 8796 #define mmOTG0_OTG_CRC1_DATA_RG_BASE_IDX 2 8797 #define mmOTG0_OTG_CRC1_DATA_B 0x1b75 8798 #define mmOTG0_OTG_CRC1_DATA_B_BASE_IDX 2 8799 #define mmOTG0_OTG_CRC2_DATA_RG 0x1b76 8800 #define mmOTG0_OTG_CRC2_DATA_RG_BASE_IDX 2 8801 #define mmOTG0_OTG_CRC2_DATA_B 0x1b77 8802 #define mmOTG0_OTG_CRC2_DATA_B_BASE_IDX 2 8803 #define mmOTG0_OTG_CRC3_DATA_RG 0x1b78 8804 #define mmOTG0_OTG_CRC3_DATA_RG_BASE_IDX 2 8805 #define mmOTG0_OTG_CRC3_DATA_B 0x1b79 8806 #define mmOTG0_OTG_CRC3_DATA_B_BASE_IDX 2 8807 #define mmOTG0_OTG_CRC_SIG_RED_GREEN_MASK 0x1b7a 8808 #define mmOTG0_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 8809 #define mmOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1b7b 8810 #define mmOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 8811 #define mmOTG0_OTG_STATIC_SCREEN_CONTROL 0x1b82 8812 #define mmOTG0_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2 8813 #define mmOTG0_OTG_3D_STRUCTURE_CONTROL 0x1b83 8814 #define mmOTG0_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2 8815 #define mmOTG0_OTG_GSL_VSYNC_GAP 0x1b84 8816 #define mmOTG0_OTG_GSL_VSYNC_GAP_BASE_IDX 2 8817 #define mmOTG0_OTG_MASTER_UPDATE_MODE 0x1b85 8818 #define mmOTG0_OTG_MASTER_UPDATE_MODE_BASE_IDX 2 8819 #define mmOTG0_OTG_CLOCK_CONTROL 0x1b86 8820 #define mmOTG0_OTG_CLOCK_CONTROL_BASE_IDX 2 8821 #define mmOTG0_OTG_VSTARTUP_PARAM 0x1b87 8822 #define mmOTG0_OTG_VSTARTUP_PARAM_BASE_IDX 2 8823 #define mmOTG0_OTG_VUPDATE_PARAM 0x1b88 8824 #define mmOTG0_OTG_VUPDATE_PARAM_BASE_IDX 2 8825 #define mmOTG0_OTG_VREADY_PARAM 0x1b89 8826 #define mmOTG0_OTG_VREADY_PARAM_BASE_IDX 2 8827 #define mmOTG0_OTG_GLOBAL_SYNC_STATUS 0x1b8a 8828 #define mmOTG0_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2 8829 #define mmOTG0_OTG_MASTER_UPDATE_LOCK 0x1b8b 8830 #define mmOTG0_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2 8831 #define mmOTG0_OTG_GSL_CONTROL 0x1b8c 8832 #define mmOTG0_OTG_GSL_CONTROL_BASE_IDX 2 8833 #define mmOTG0_OTG_GSL_WINDOW_X 0x1b8d 8834 #define mmOTG0_OTG_GSL_WINDOW_X_BASE_IDX 2 8835 #define mmOTG0_OTG_GSL_WINDOW_Y 0x1b8e 8836 #define mmOTG0_OTG_GSL_WINDOW_Y_BASE_IDX 2 8837 #define mmOTG0_OTG_VUPDATE_KEEPOUT 0x1b8f 8838 #define mmOTG0_OTG_VUPDATE_KEEPOUT_BASE_IDX 2 8839 #define mmOTG0_OTG_GLOBAL_CONTROL0 0x1b90 8840 #define mmOTG0_OTG_GLOBAL_CONTROL0_BASE_IDX 2 8841 #define mmOTG0_OTG_GLOBAL_CONTROL1 0x1b91 8842 #define mmOTG0_OTG_GLOBAL_CONTROL1_BASE_IDX 2 8843 #define mmOTG0_OTG_GLOBAL_CONTROL2 0x1b92 8844 #define mmOTG0_OTG_GLOBAL_CONTROL2_BASE_IDX 2 8845 #define mmOTG0_OTG_GLOBAL_CONTROL3 0x1b93 8846 #define mmOTG0_OTG_GLOBAL_CONTROL3_BASE_IDX 2 8847 #define mmOTG0_OTG_GLOBAL_CONTROL4 0x1b94 8848 #define mmOTG0_OTG_GLOBAL_CONTROL4_BASE_IDX 2 8849 #define mmOTG0_OTG_TRIG_MANUAL_CONTROL 0x1b95 8850 #define mmOTG0_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2 8851 #define mmOTG0_OTG_MANUAL_FLOW_CONTROL 0x1b96 8852 #define mmOTG0_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2 8853 #define mmOTG0_OTG_DRR_TIMING_INT_STATUS 0x1b97 8854 #define mmOTG0_OTG_DRR_TIMING_INT_STATUS_BASE_IDX 2 8855 #define mmOTG0_OTG_DRR_V_TOTAL_REACH_RANGE 0x1b98 8856 #define mmOTG0_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX 2 8857 #define mmOTG0_OTG_DRR_V_TOTAL_CHANGE 0x1b99 8858 #define mmOTG0_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX 2 8859 #define mmOTG0_OTG_DRR_TRIGGER_WINDOW 0x1b9a 8860 #define mmOTG0_OTG_DRR_TRIGGER_WINDOW_BASE_IDX 2 8861 #define mmOTG0_OTG_DRR_CONTROL 0x1b9b 8862 #define mmOTG0_OTG_DRR_CONTROL_BASE_IDX 2 8863 #define mmOTG0_OTG_M_CONST_DTO0 0x1b9c 8864 #define mmOTG0_OTG_M_CONST_DTO0_BASE_IDX 2 8865 #define mmOTG0_OTG_M_CONST_DTO1 0x1b9d 8866 #define mmOTG0_OTG_M_CONST_DTO1_BASE_IDX 2 8867 #define mmOTG0_OTG_REQUEST_CONTROL 0x1b9e 8868 #define mmOTG0_OTG_REQUEST_CONTROL_BASE_IDX 2 8869 #define mmOTG0_OTG_DSC_START_POSITION 0x1b9f 8870 #define mmOTG0_OTG_DSC_START_POSITION_BASE_IDX 2 8871 #define mmOTG0_OTG_PIPE_UPDATE_STATUS 0x1ba0 8872 #define mmOTG0_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2 8873 #define mmOTG0_OTG_SPARE_REGISTER 0x1ba2 8874 #define mmOTG0_OTG_SPARE_REGISTER_BASE_IDX 2 8875 8876 8877 // addressBlock: dce_dc_optc_otg1_dispdec 8878 // base address: 0x200 8879 #define mmOTG1_OTG_H_TOTAL 0x1baa 8880 #define mmOTG1_OTG_H_TOTAL_BASE_IDX 2 8881 #define mmOTG1_OTG_H_BLANK_START_END 0x1bab 8882 #define mmOTG1_OTG_H_BLANK_START_END_BASE_IDX 2 8883 #define mmOTG1_OTG_H_SYNC_A 0x1bac 8884 #define mmOTG1_OTG_H_SYNC_A_BASE_IDX 2 8885 #define mmOTG1_OTG_H_SYNC_A_CNTL 0x1bad 8886 #define mmOTG1_OTG_H_SYNC_A_CNTL_BASE_IDX 2 8887 #define mmOTG1_OTG_H_TIMING_CNTL 0x1bae 8888 #define mmOTG1_OTG_H_TIMING_CNTL_BASE_IDX 2 8889 #define mmOTG1_OTG_V_TOTAL 0x1baf 8890 #define mmOTG1_OTG_V_TOTAL_BASE_IDX 2 8891 #define mmOTG1_OTG_V_TOTAL_MIN 0x1bb0 8892 #define mmOTG1_OTG_V_TOTAL_MIN_BASE_IDX 2 8893 #define mmOTG1_OTG_V_TOTAL_MAX 0x1bb1 8894 #define mmOTG1_OTG_V_TOTAL_MAX_BASE_IDX 2 8895 #define mmOTG1_OTG_V_TOTAL_MID 0x1bb2 8896 #define mmOTG1_OTG_V_TOTAL_MID_BASE_IDX 2 8897 #define mmOTG1_OTG_V_TOTAL_CONTROL 0x1bb3 8898 #define mmOTG1_OTG_V_TOTAL_CONTROL_BASE_IDX 2 8899 #define mmOTG1_OTG_V_TOTAL_INT_STATUS 0x1bb4 8900 #define mmOTG1_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2 8901 #define mmOTG1_OTG_VSYNC_NOM_INT_STATUS 0x1bb5 8902 #define mmOTG1_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2 8903 #define mmOTG1_OTG_V_BLANK_START_END 0x1bb6 8904 #define mmOTG1_OTG_V_BLANK_START_END_BASE_IDX 2 8905 #define mmOTG1_OTG_V_SYNC_A 0x1bb7 8906 #define mmOTG1_OTG_V_SYNC_A_BASE_IDX 2 8907 #define mmOTG1_OTG_V_SYNC_A_CNTL 0x1bb8 8908 #define mmOTG1_OTG_V_SYNC_A_CNTL_BASE_IDX 2 8909 #define mmOTG1_OTG_TRIGA_CNTL 0x1bb9 8910 #define mmOTG1_OTG_TRIGA_CNTL_BASE_IDX 2 8911 #define mmOTG1_OTG_TRIGA_MANUAL_TRIG 0x1bba 8912 #define mmOTG1_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2 8913 #define mmOTG1_OTG_TRIGB_CNTL 0x1bbb 8914 #define mmOTG1_OTG_TRIGB_CNTL_BASE_IDX 2 8915 #define mmOTG1_OTG_TRIGB_MANUAL_TRIG 0x1bbc 8916 #define mmOTG1_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2 8917 #define mmOTG1_OTG_FORCE_COUNT_NOW_CNTL 0x1bbd 8918 #define mmOTG1_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 8919 #define mmOTG1_OTG_FLOW_CONTROL 0x1bbe 8920 #define mmOTG1_OTG_FLOW_CONTROL_BASE_IDX 2 8921 #define mmOTG1_OTG_STEREO_FORCE_NEXT_EYE 0x1bbf 8922 #define mmOTG1_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 8923 #define mmOTG1_OTG_CONTROL 0x1bc1 8924 #define mmOTG1_OTG_CONTROL_BASE_IDX 2 8925 #define mmOTG1_OTG_BLANK_CONTROL 0x1bc2 8926 #define mmOTG1_OTG_BLANK_CONTROL_BASE_IDX 2 8927 #define mmOTG1_OTG_INTERLACE_CONTROL 0x1bc4 8928 #define mmOTG1_OTG_INTERLACE_CONTROL_BASE_IDX 2 8929 #define mmOTG1_OTG_INTERLACE_STATUS 0x1bc5 8930 #define mmOTG1_OTG_INTERLACE_STATUS_BASE_IDX 2 8931 #define mmOTG1_OTG_PIXEL_DATA_READBACK0 0x1bc7 8932 #define mmOTG1_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2 8933 #define mmOTG1_OTG_PIXEL_DATA_READBACK1 0x1bc8 8934 #define mmOTG1_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2 8935 #define mmOTG1_OTG_STATUS 0x1bc9 8936 #define mmOTG1_OTG_STATUS_BASE_IDX 2 8937 #define mmOTG1_OTG_STATUS_POSITION 0x1bca 8938 #define mmOTG1_OTG_STATUS_POSITION_BASE_IDX 2 8939 #define mmOTG1_OTG_NOM_VERT_POSITION 0x1bcb 8940 #define mmOTG1_OTG_NOM_VERT_POSITION_BASE_IDX 2 8941 #define mmOTG1_OTG_STATUS_FRAME_COUNT 0x1bcc 8942 #define mmOTG1_OTG_STATUS_FRAME_COUNT_BASE_IDX 2 8943 #define mmOTG1_OTG_STATUS_VF_COUNT 0x1bcd 8944 #define mmOTG1_OTG_STATUS_VF_COUNT_BASE_IDX 2 8945 #define mmOTG1_OTG_STATUS_HV_COUNT 0x1bce 8946 #define mmOTG1_OTG_STATUS_HV_COUNT_BASE_IDX 2 8947 #define mmOTG1_OTG_COUNT_CONTROL 0x1bcf 8948 #define mmOTG1_OTG_COUNT_CONTROL_BASE_IDX 2 8949 #define mmOTG1_OTG_COUNT_RESET 0x1bd0 8950 #define mmOTG1_OTG_COUNT_RESET_BASE_IDX 2 8951 #define mmOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1bd1 8952 #define mmOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 8953 #define mmOTG1_OTG_VERT_SYNC_CONTROL 0x1bd2 8954 #define mmOTG1_OTG_VERT_SYNC_CONTROL_BASE_IDX 2 8955 #define mmOTG1_OTG_STEREO_STATUS 0x1bd3 8956 #define mmOTG1_OTG_STEREO_STATUS_BASE_IDX 2 8957 #define mmOTG1_OTG_STEREO_CONTROL 0x1bd4 8958 #define mmOTG1_OTG_STEREO_CONTROL_BASE_IDX 2 8959 #define mmOTG1_OTG_SNAPSHOT_STATUS 0x1bd5 8960 #define mmOTG1_OTG_SNAPSHOT_STATUS_BASE_IDX 2 8961 #define mmOTG1_OTG_SNAPSHOT_CONTROL 0x1bd6 8962 #define mmOTG1_OTG_SNAPSHOT_CONTROL_BASE_IDX 2 8963 #define mmOTG1_OTG_SNAPSHOT_POSITION 0x1bd7 8964 #define mmOTG1_OTG_SNAPSHOT_POSITION_BASE_IDX 2 8965 #define mmOTG1_OTG_SNAPSHOT_FRAME 0x1bd8 8966 #define mmOTG1_OTG_SNAPSHOT_FRAME_BASE_IDX 2 8967 #define mmOTG1_OTG_INTERRUPT_CONTROL 0x1bd9 8968 #define mmOTG1_OTG_INTERRUPT_CONTROL_BASE_IDX 2 8969 #define mmOTG1_OTG_UPDATE_LOCK 0x1bda 8970 #define mmOTG1_OTG_UPDATE_LOCK_BASE_IDX 2 8971 #define mmOTG1_OTG_DOUBLE_BUFFER_CONTROL 0x1bdb 8972 #define mmOTG1_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 8973 #define mmOTG1_OTG_MASTER_EN 0x1bdc 8974 #define mmOTG1_OTG_MASTER_EN_BASE_IDX 2 8975 #define mmOTG1_OTG_BLANK_DATA_COLOR 0x1bde 8976 #define mmOTG1_OTG_BLANK_DATA_COLOR_BASE_IDX 2 8977 #define mmOTG1_OTG_BLANK_DATA_COLOR_EXT 0x1bdf 8978 #define mmOTG1_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX 2 8979 #define mmOTG1_OTG_VERTICAL_INTERRUPT0_POSITION 0x1be2 8980 #define mmOTG1_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 8981 #define mmOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1be3 8982 #define mmOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 8983 #define mmOTG1_OTG_VERTICAL_INTERRUPT1_POSITION 0x1be4 8984 #define mmOTG1_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 8985 #define mmOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1be5 8986 #define mmOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 8987 #define mmOTG1_OTG_VERTICAL_INTERRUPT2_POSITION 0x1be6 8988 #define mmOTG1_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 8989 #define mmOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1be7 8990 #define mmOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 8991 #define mmOTG1_OTG_CRC_CNTL 0x1be8 8992 #define mmOTG1_OTG_CRC_CNTL_BASE_IDX 2 8993 #define mmOTG1_OTG_CRC_CNTL2 0x1be9 8994 #define mmOTG1_OTG_CRC_CNTL2_BASE_IDX 2 8995 #define mmOTG1_OTG_CRC0_WINDOWA_X_CONTROL 0x1bea 8996 #define mmOTG1_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 8997 #define mmOTG1_OTG_CRC0_WINDOWA_Y_CONTROL 0x1beb 8998 #define mmOTG1_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 8999 #define mmOTG1_OTG_CRC0_WINDOWB_X_CONTROL 0x1bec 9000 #define mmOTG1_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 9001 #define mmOTG1_OTG_CRC0_WINDOWB_Y_CONTROL 0x1bed 9002 #define mmOTG1_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 9003 #define mmOTG1_OTG_CRC0_DATA_RG 0x1bee 9004 #define mmOTG1_OTG_CRC0_DATA_RG_BASE_IDX 2 9005 #define mmOTG1_OTG_CRC0_DATA_B 0x1bef 9006 #define mmOTG1_OTG_CRC0_DATA_B_BASE_IDX 2 9007 #define mmOTG1_OTG_CRC1_WINDOWA_X_CONTROL 0x1bf0 9008 #define mmOTG1_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 9009 #define mmOTG1_OTG_CRC1_WINDOWA_Y_CONTROL 0x1bf1 9010 #define mmOTG1_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 9011 #define mmOTG1_OTG_CRC1_WINDOWB_X_CONTROL 0x1bf2 9012 #define mmOTG1_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 9013 #define mmOTG1_OTG_CRC1_WINDOWB_Y_CONTROL 0x1bf3 9014 #define mmOTG1_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 9015 #define mmOTG1_OTG_CRC1_DATA_RG 0x1bf4 9016 #define mmOTG1_OTG_CRC1_DATA_RG_BASE_IDX 2 9017 #define mmOTG1_OTG_CRC1_DATA_B 0x1bf5 9018 #define mmOTG1_OTG_CRC1_DATA_B_BASE_IDX 2 9019 #define mmOTG1_OTG_CRC2_DATA_RG 0x1bf6 9020 #define mmOTG1_OTG_CRC2_DATA_RG_BASE_IDX 2 9021 #define mmOTG1_OTG_CRC2_DATA_B 0x1bf7 9022 #define mmOTG1_OTG_CRC2_DATA_B_BASE_IDX 2 9023 #define mmOTG1_OTG_CRC3_DATA_RG 0x1bf8 9024 #define mmOTG1_OTG_CRC3_DATA_RG_BASE_IDX 2 9025 #define mmOTG1_OTG_CRC3_DATA_B 0x1bf9 9026 #define mmOTG1_OTG_CRC3_DATA_B_BASE_IDX 2 9027 #define mmOTG1_OTG_CRC_SIG_RED_GREEN_MASK 0x1bfa 9028 #define mmOTG1_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 9029 #define mmOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1bfb 9030 #define mmOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 9031 #define mmOTG1_OTG_STATIC_SCREEN_CONTROL 0x1c02 9032 #define mmOTG1_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2 9033 #define mmOTG1_OTG_3D_STRUCTURE_CONTROL 0x1c03 9034 #define mmOTG1_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2 9035 #define mmOTG1_OTG_GSL_VSYNC_GAP 0x1c04 9036 #define mmOTG1_OTG_GSL_VSYNC_GAP_BASE_IDX 2 9037 #define mmOTG1_OTG_MASTER_UPDATE_MODE 0x1c05 9038 #define mmOTG1_OTG_MASTER_UPDATE_MODE_BASE_IDX 2 9039 #define mmOTG1_OTG_CLOCK_CONTROL 0x1c06 9040 #define mmOTG1_OTG_CLOCK_CONTROL_BASE_IDX 2 9041 #define mmOTG1_OTG_VSTARTUP_PARAM 0x1c07 9042 #define mmOTG1_OTG_VSTARTUP_PARAM_BASE_IDX 2 9043 #define mmOTG1_OTG_VUPDATE_PARAM 0x1c08 9044 #define mmOTG1_OTG_VUPDATE_PARAM_BASE_IDX 2 9045 #define mmOTG1_OTG_VREADY_PARAM 0x1c09 9046 #define mmOTG1_OTG_VREADY_PARAM_BASE_IDX 2 9047 #define mmOTG1_OTG_GLOBAL_SYNC_STATUS 0x1c0a 9048 #define mmOTG1_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2 9049 #define mmOTG1_OTG_MASTER_UPDATE_LOCK 0x1c0b 9050 #define mmOTG1_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2 9051 #define mmOTG1_OTG_GSL_CONTROL 0x1c0c 9052 #define mmOTG1_OTG_GSL_CONTROL_BASE_IDX 2 9053 #define mmOTG1_OTG_GSL_WINDOW_X 0x1c0d 9054 #define mmOTG1_OTG_GSL_WINDOW_X_BASE_IDX 2 9055 #define mmOTG1_OTG_GSL_WINDOW_Y 0x1c0e 9056 #define mmOTG1_OTG_GSL_WINDOW_Y_BASE_IDX 2 9057 #define mmOTG1_OTG_VUPDATE_KEEPOUT 0x1c0f 9058 #define mmOTG1_OTG_VUPDATE_KEEPOUT_BASE_IDX 2 9059 #define mmOTG1_OTG_GLOBAL_CONTROL0 0x1c10 9060 #define mmOTG1_OTG_GLOBAL_CONTROL0_BASE_IDX 2 9061 #define mmOTG1_OTG_GLOBAL_CONTROL1 0x1c11 9062 #define mmOTG1_OTG_GLOBAL_CONTROL1_BASE_IDX 2 9063 #define mmOTG1_OTG_GLOBAL_CONTROL2 0x1c12 9064 #define mmOTG1_OTG_GLOBAL_CONTROL2_BASE_IDX 2 9065 #define mmOTG1_OTG_GLOBAL_CONTROL3 0x1c13 9066 #define mmOTG1_OTG_GLOBAL_CONTROL3_BASE_IDX 2 9067 #define mmOTG1_OTG_GLOBAL_CONTROL4 0x1c14 9068 #define mmOTG1_OTG_GLOBAL_CONTROL4_BASE_IDX 2 9069 #define mmOTG1_OTG_TRIG_MANUAL_CONTROL 0x1c15 9070 #define mmOTG1_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2 9071 #define mmOTG1_OTG_MANUAL_FLOW_CONTROL 0x1c16 9072 #define mmOTG1_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2 9073 #define mmOTG1_OTG_DRR_TIMING_INT_STATUS 0x1c17 9074 #define mmOTG1_OTG_DRR_TIMING_INT_STATUS_BASE_IDX 2 9075 #define mmOTG1_OTG_DRR_V_TOTAL_REACH_RANGE 0x1c18 9076 #define mmOTG1_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX 2 9077 #define mmOTG1_OTG_DRR_V_TOTAL_CHANGE 0x1c19 9078 #define mmOTG1_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX 2 9079 #define mmOTG1_OTG_DRR_TRIGGER_WINDOW 0x1c1a 9080 #define mmOTG1_OTG_DRR_TRIGGER_WINDOW_BASE_IDX 2 9081 #define mmOTG1_OTG_DRR_CONTROL 0x1c1b 9082 #define mmOTG1_OTG_DRR_CONTROL_BASE_IDX 2 9083 #define mmOTG1_OTG_M_CONST_DTO0 0x1c1c 9084 #define mmOTG1_OTG_M_CONST_DTO0_BASE_IDX 2 9085 #define mmOTG1_OTG_M_CONST_DTO1 0x1c1d 9086 #define mmOTG1_OTG_M_CONST_DTO1_BASE_IDX 2 9087 #define mmOTG1_OTG_REQUEST_CONTROL 0x1c1e 9088 #define mmOTG1_OTG_REQUEST_CONTROL_BASE_IDX 2 9089 #define mmOTG1_OTG_DSC_START_POSITION 0x1c1f 9090 #define mmOTG1_OTG_DSC_START_POSITION_BASE_IDX 2 9091 #define mmOTG1_OTG_PIPE_UPDATE_STATUS 0x1c20 9092 #define mmOTG1_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2 9093 #define mmOTG1_OTG_SPARE_REGISTER 0x1c22 9094 #define mmOTG1_OTG_SPARE_REGISTER_BASE_IDX 2 9095 9096 9097 // addressBlock: dce_dc_optc_otg2_dispdec 9098 // base address: 0x400 9099 #define mmOTG2_OTG_H_TOTAL 0x1c2a 9100 #define mmOTG2_OTG_H_TOTAL_BASE_IDX 2 9101 #define mmOTG2_OTG_H_BLANK_START_END 0x1c2b 9102 #define mmOTG2_OTG_H_BLANK_START_END_BASE_IDX 2 9103 #define mmOTG2_OTG_H_SYNC_A 0x1c2c 9104 #define mmOTG2_OTG_H_SYNC_A_BASE_IDX 2 9105 #define mmOTG2_OTG_H_SYNC_A_CNTL 0x1c2d 9106 #define mmOTG2_OTG_H_SYNC_A_CNTL_BASE_IDX 2 9107 #define mmOTG2_OTG_H_TIMING_CNTL 0x1c2e 9108 #define mmOTG2_OTG_H_TIMING_CNTL_BASE_IDX 2 9109 #define mmOTG2_OTG_V_TOTAL 0x1c2f 9110 #define mmOTG2_OTG_V_TOTAL_BASE_IDX 2 9111 #define mmOTG2_OTG_V_TOTAL_MIN 0x1c30 9112 #define mmOTG2_OTG_V_TOTAL_MIN_BASE_IDX 2 9113 #define mmOTG2_OTG_V_TOTAL_MAX 0x1c31 9114 #define mmOTG2_OTG_V_TOTAL_MAX_BASE_IDX 2 9115 #define mmOTG2_OTG_V_TOTAL_MID 0x1c32 9116 #define mmOTG2_OTG_V_TOTAL_MID_BASE_IDX 2 9117 #define mmOTG2_OTG_V_TOTAL_CONTROL 0x1c33 9118 #define mmOTG2_OTG_V_TOTAL_CONTROL_BASE_IDX 2 9119 #define mmOTG2_OTG_V_TOTAL_INT_STATUS 0x1c34 9120 #define mmOTG2_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2 9121 #define mmOTG2_OTG_VSYNC_NOM_INT_STATUS 0x1c35 9122 #define mmOTG2_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2 9123 #define mmOTG2_OTG_V_BLANK_START_END 0x1c36 9124 #define mmOTG2_OTG_V_BLANK_START_END_BASE_IDX 2 9125 #define mmOTG2_OTG_V_SYNC_A 0x1c37 9126 #define mmOTG2_OTG_V_SYNC_A_BASE_IDX 2 9127 #define mmOTG2_OTG_V_SYNC_A_CNTL 0x1c38 9128 #define mmOTG2_OTG_V_SYNC_A_CNTL_BASE_IDX 2 9129 #define mmOTG2_OTG_TRIGA_CNTL 0x1c39 9130 #define mmOTG2_OTG_TRIGA_CNTL_BASE_IDX 2 9131 #define mmOTG2_OTG_TRIGA_MANUAL_TRIG 0x1c3a 9132 #define mmOTG2_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2 9133 #define mmOTG2_OTG_TRIGB_CNTL 0x1c3b 9134 #define mmOTG2_OTG_TRIGB_CNTL_BASE_IDX 2 9135 #define mmOTG2_OTG_TRIGB_MANUAL_TRIG 0x1c3c 9136 #define mmOTG2_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2 9137 #define mmOTG2_OTG_FORCE_COUNT_NOW_CNTL 0x1c3d 9138 #define mmOTG2_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 9139 #define mmOTG2_OTG_FLOW_CONTROL 0x1c3e 9140 #define mmOTG2_OTG_FLOW_CONTROL_BASE_IDX 2 9141 #define mmOTG2_OTG_STEREO_FORCE_NEXT_EYE 0x1c3f 9142 #define mmOTG2_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 9143 #define mmOTG2_OTG_CONTROL 0x1c41 9144 #define mmOTG2_OTG_CONTROL_BASE_IDX 2 9145 #define mmOTG2_OTG_BLANK_CONTROL 0x1c42 9146 #define mmOTG2_OTG_BLANK_CONTROL_BASE_IDX 2 9147 #define mmOTG2_OTG_INTERLACE_CONTROL 0x1c44 9148 #define mmOTG2_OTG_INTERLACE_CONTROL_BASE_IDX 2 9149 #define mmOTG2_OTG_INTERLACE_STATUS 0x1c45 9150 #define mmOTG2_OTG_INTERLACE_STATUS_BASE_IDX 2 9151 #define mmOTG2_OTG_PIXEL_DATA_READBACK0 0x1c47 9152 #define mmOTG2_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2 9153 #define mmOTG2_OTG_PIXEL_DATA_READBACK1 0x1c48 9154 #define mmOTG2_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2 9155 #define mmOTG2_OTG_STATUS 0x1c49 9156 #define mmOTG2_OTG_STATUS_BASE_IDX 2 9157 #define mmOTG2_OTG_STATUS_POSITION 0x1c4a 9158 #define mmOTG2_OTG_STATUS_POSITION_BASE_IDX 2 9159 #define mmOTG2_OTG_NOM_VERT_POSITION 0x1c4b 9160 #define mmOTG2_OTG_NOM_VERT_POSITION_BASE_IDX 2 9161 #define mmOTG2_OTG_STATUS_FRAME_COUNT 0x1c4c 9162 #define mmOTG2_OTG_STATUS_FRAME_COUNT_BASE_IDX 2 9163 #define mmOTG2_OTG_STATUS_VF_COUNT 0x1c4d 9164 #define mmOTG2_OTG_STATUS_VF_COUNT_BASE_IDX 2 9165 #define mmOTG2_OTG_STATUS_HV_COUNT 0x1c4e 9166 #define mmOTG2_OTG_STATUS_HV_COUNT_BASE_IDX 2 9167 #define mmOTG2_OTG_COUNT_CONTROL 0x1c4f 9168 #define mmOTG2_OTG_COUNT_CONTROL_BASE_IDX 2 9169 #define mmOTG2_OTG_COUNT_RESET 0x1c50 9170 #define mmOTG2_OTG_COUNT_RESET_BASE_IDX 2 9171 #define mmOTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1c51 9172 #define mmOTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 9173 #define mmOTG2_OTG_VERT_SYNC_CONTROL 0x1c52 9174 #define mmOTG2_OTG_VERT_SYNC_CONTROL_BASE_IDX 2 9175 #define mmOTG2_OTG_STEREO_STATUS 0x1c53 9176 #define mmOTG2_OTG_STEREO_STATUS_BASE_IDX 2 9177 #define mmOTG2_OTG_STEREO_CONTROL 0x1c54 9178 #define mmOTG2_OTG_STEREO_CONTROL_BASE_IDX 2 9179 #define mmOTG2_OTG_SNAPSHOT_STATUS 0x1c55 9180 #define mmOTG2_OTG_SNAPSHOT_STATUS_BASE_IDX 2 9181 #define mmOTG2_OTG_SNAPSHOT_CONTROL 0x1c56 9182 #define mmOTG2_OTG_SNAPSHOT_CONTROL_BASE_IDX 2 9183 #define mmOTG2_OTG_SNAPSHOT_POSITION 0x1c57 9184 #define mmOTG2_OTG_SNAPSHOT_POSITION_BASE_IDX 2 9185 #define mmOTG2_OTG_SNAPSHOT_FRAME 0x1c58 9186 #define mmOTG2_OTG_SNAPSHOT_FRAME_BASE_IDX 2 9187 #define mmOTG2_OTG_INTERRUPT_CONTROL 0x1c59 9188 #define mmOTG2_OTG_INTERRUPT_CONTROL_BASE_IDX 2 9189 #define mmOTG2_OTG_UPDATE_LOCK 0x1c5a 9190 #define mmOTG2_OTG_UPDATE_LOCK_BASE_IDX 2 9191 #define mmOTG2_OTG_DOUBLE_BUFFER_CONTROL 0x1c5b 9192 #define mmOTG2_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 9193 #define mmOTG2_OTG_MASTER_EN 0x1c5c 9194 #define mmOTG2_OTG_MASTER_EN_BASE_IDX 2 9195 #define mmOTG2_OTG_BLANK_DATA_COLOR 0x1c5e 9196 #define mmOTG2_OTG_BLANK_DATA_COLOR_BASE_IDX 2 9197 #define mmOTG2_OTG_BLANK_DATA_COLOR_EXT 0x1c5f 9198 #define mmOTG2_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX 2 9199 #define mmOTG2_OTG_VERTICAL_INTERRUPT0_POSITION 0x1c62 9200 #define mmOTG2_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 9201 #define mmOTG2_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1c63 9202 #define mmOTG2_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 9203 #define mmOTG2_OTG_VERTICAL_INTERRUPT1_POSITION 0x1c64 9204 #define mmOTG2_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 9205 #define mmOTG2_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1c65 9206 #define mmOTG2_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 9207 #define mmOTG2_OTG_VERTICAL_INTERRUPT2_POSITION 0x1c66 9208 #define mmOTG2_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 9209 #define mmOTG2_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1c67 9210 #define mmOTG2_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 9211 #define mmOTG2_OTG_CRC_CNTL 0x1c68 9212 #define mmOTG2_OTG_CRC_CNTL_BASE_IDX 2 9213 #define mmOTG2_OTG_CRC_CNTL2 0x1c69 9214 #define mmOTG2_OTG_CRC_CNTL2_BASE_IDX 2 9215 #define mmOTG2_OTG_CRC0_WINDOWA_X_CONTROL 0x1c6a 9216 #define mmOTG2_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 9217 #define mmOTG2_OTG_CRC0_WINDOWA_Y_CONTROL 0x1c6b 9218 #define mmOTG2_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 9219 #define mmOTG2_OTG_CRC0_WINDOWB_X_CONTROL 0x1c6c 9220 #define mmOTG2_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 9221 #define mmOTG2_OTG_CRC0_WINDOWB_Y_CONTROL 0x1c6d 9222 #define mmOTG2_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 9223 #define mmOTG2_OTG_CRC0_DATA_RG 0x1c6e 9224 #define mmOTG2_OTG_CRC0_DATA_RG_BASE_IDX 2 9225 #define mmOTG2_OTG_CRC0_DATA_B 0x1c6f 9226 #define mmOTG2_OTG_CRC0_DATA_B_BASE_IDX 2 9227 #define mmOTG2_OTG_CRC1_WINDOWA_X_CONTROL 0x1c70 9228 #define mmOTG2_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 9229 #define mmOTG2_OTG_CRC1_WINDOWA_Y_CONTROL 0x1c71 9230 #define mmOTG2_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 9231 #define mmOTG2_OTG_CRC1_WINDOWB_X_CONTROL 0x1c72 9232 #define mmOTG2_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 9233 #define mmOTG2_OTG_CRC1_WINDOWB_Y_CONTROL 0x1c73 9234 #define mmOTG2_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 9235 #define mmOTG2_OTG_CRC1_DATA_RG 0x1c74 9236 #define mmOTG2_OTG_CRC1_DATA_RG_BASE_IDX 2 9237 #define mmOTG2_OTG_CRC1_DATA_B 0x1c75 9238 #define mmOTG2_OTG_CRC1_DATA_B_BASE_IDX 2 9239 #define mmOTG2_OTG_CRC2_DATA_RG 0x1c76 9240 #define mmOTG2_OTG_CRC2_DATA_RG_BASE_IDX 2 9241 #define mmOTG2_OTG_CRC2_DATA_B 0x1c77 9242 #define mmOTG2_OTG_CRC2_DATA_B_BASE_IDX 2 9243 #define mmOTG2_OTG_CRC3_DATA_RG 0x1c78 9244 #define mmOTG2_OTG_CRC3_DATA_RG_BASE_IDX 2 9245 #define mmOTG2_OTG_CRC3_DATA_B 0x1c79 9246 #define mmOTG2_OTG_CRC3_DATA_B_BASE_IDX 2 9247 #define mmOTG2_OTG_CRC_SIG_RED_GREEN_MASK 0x1c7a 9248 #define mmOTG2_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 9249 #define mmOTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1c7b 9250 #define mmOTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 9251 #define mmOTG2_OTG_STATIC_SCREEN_CONTROL 0x1c82 9252 #define mmOTG2_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2 9253 #define mmOTG2_OTG_3D_STRUCTURE_CONTROL 0x1c83 9254 #define mmOTG2_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2 9255 #define mmOTG2_OTG_GSL_VSYNC_GAP 0x1c84 9256 #define mmOTG2_OTG_GSL_VSYNC_GAP_BASE_IDX 2 9257 #define mmOTG2_OTG_MASTER_UPDATE_MODE 0x1c85 9258 #define mmOTG2_OTG_MASTER_UPDATE_MODE_BASE_IDX 2 9259 #define mmOTG2_OTG_CLOCK_CONTROL 0x1c86 9260 #define mmOTG2_OTG_CLOCK_CONTROL_BASE_IDX 2 9261 #define mmOTG2_OTG_VSTARTUP_PARAM 0x1c87 9262 #define mmOTG2_OTG_VSTARTUP_PARAM_BASE_IDX 2 9263 #define mmOTG2_OTG_VUPDATE_PARAM 0x1c88 9264 #define mmOTG2_OTG_VUPDATE_PARAM_BASE_IDX 2 9265 #define mmOTG2_OTG_VREADY_PARAM 0x1c89 9266 #define mmOTG2_OTG_VREADY_PARAM_BASE_IDX 2 9267 #define mmOTG2_OTG_GLOBAL_SYNC_STATUS 0x1c8a 9268 #define mmOTG2_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2 9269 #define mmOTG2_OTG_MASTER_UPDATE_LOCK 0x1c8b 9270 #define mmOTG2_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2 9271 #define mmOTG2_OTG_GSL_CONTROL 0x1c8c 9272 #define mmOTG2_OTG_GSL_CONTROL_BASE_IDX 2 9273 #define mmOTG2_OTG_GSL_WINDOW_X 0x1c8d 9274 #define mmOTG2_OTG_GSL_WINDOW_X_BASE_IDX 2 9275 #define mmOTG2_OTG_GSL_WINDOW_Y 0x1c8e 9276 #define mmOTG2_OTG_GSL_WINDOW_Y_BASE_IDX 2 9277 #define mmOTG2_OTG_VUPDATE_KEEPOUT 0x1c8f 9278 #define mmOTG2_OTG_VUPDATE_KEEPOUT_BASE_IDX 2 9279 #define mmOTG2_OTG_GLOBAL_CONTROL0 0x1c90 9280 #define mmOTG2_OTG_GLOBAL_CONTROL0_BASE_IDX 2 9281 #define mmOTG2_OTG_GLOBAL_CONTROL1 0x1c91 9282 #define mmOTG2_OTG_GLOBAL_CONTROL1_BASE_IDX 2 9283 #define mmOTG2_OTG_GLOBAL_CONTROL2 0x1c92 9284 #define mmOTG2_OTG_GLOBAL_CONTROL2_BASE_IDX 2 9285 #define mmOTG2_OTG_GLOBAL_CONTROL3 0x1c93 9286 #define mmOTG2_OTG_GLOBAL_CONTROL3_BASE_IDX 2 9287 #define mmOTG2_OTG_GLOBAL_CONTROL4 0x1c94 9288 #define mmOTG2_OTG_GLOBAL_CONTROL4_BASE_IDX 2 9289 #define mmOTG2_OTG_TRIG_MANUAL_CONTROL 0x1c95 9290 #define mmOTG2_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2 9291 #define mmOTG2_OTG_MANUAL_FLOW_CONTROL 0x1c96 9292 #define mmOTG2_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2 9293 #define mmOTG2_OTG_DRR_TIMING_INT_STATUS 0x1c97 9294 #define mmOTG2_OTG_DRR_TIMING_INT_STATUS_BASE_IDX 2 9295 #define mmOTG2_OTG_DRR_V_TOTAL_REACH_RANGE 0x1c98 9296 #define mmOTG2_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX 2 9297 #define mmOTG2_OTG_DRR_V_TOTAL_CHANGE 0x1c99 9298 #define mmOTG2_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX 2 9299 #define mmOTG2_OTG_DRR_TRIGGER_WINDOW 0x1c9a 9300 #define mmOTG2_OTG_DRR_TRIGGER_WINDOW_BASE_IDX 2 9301 #define mmOTG2_OTG_DRR_CONTROL 0x1c9b 9302 #define mmOTG2_OTG_DRR_CONTROL_BASE_IDX 2 9303 #define mmOTG2_OTG_M_CONST_DTO0 0x1c9c 9304 #define mmOTG2_OTG_M_CONST_DTO0_BASE_IDX 2 9305 #define mmOTG2_OTG_M_CONST_DTO1 0x1c9d 9306 #define mmOTG2_OTG_M_CONST_DTO1_BASE_IDX 2 9307 #define mmOTG2_OTG_REQUEST_CONTROL 0x1c9e 9308 #define mmOTG2_OTG_REQUEST_CONTROL_BASE_IDX 2 9309 #define mmOTG2_OTG_DSC_START_POSITION 0x1c9f 9310 #define mmOTG2_OTG_DSC_START_POSITION_BASE_IDX 2 9311 #define mmOTG2_OTG_PIPE_UPDATE_STATUS 0x1ca0 9312 #define mmOTG2_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2 9313 #define mmOTG2_OTG_SPARE_REGISTER 0x1ca2 9314 #define mmOTG2_OTG_SPARE_REGISTER_BASE_IDX 2 9315 9316 9317 // addressBlock: dce_dc_optc_otg3_dispdec 9318 // base address: 0x600 9319 #define mmOTG3_OTG_H_TOTAL 0x1caa 9320 #define mmOTG3_OTG_H_TOTAL_BASE_IDX 2 9321 #define mmOTG3_OTG_H_BLANK_START_END 0x1cab 9322 #define mmOTG3_OTG_H_BLANK_START_END_BASE_IDX 2 9323 #define mmOTG3_OTG_H_SYNC_A 0x1cac 9324 #define mmOTG3_OTG_H_SYNC_A_BASE_IDX 2 9325 #define mmOTG3_OTG_H_SYNC_A_CNTL 0x1cad 9326 #define mmOTG3_OTG_H_SYNC_A_CNTL_BASE_IDX 2 9327 #define mmOTG3_OTG_H_TIMING_CNTL 0x1cae 9328 #define mmOTG3_OTG_H_TIMING_CNTL_BASE_IDX 2 9329 #define mmOTG3_OTG_V_TOTAL 0x1caf 9330 #define mmOTG3_OTG_V_TOTAL_BASE_IDX 2 9331 #define mmOTG3_OTG_V_TOTAL_MIN 0x1cb0 9332 #define mmOTG3_OTG_V_TOTAL_MIN_BASE_IDX 2 9333 #define mmOTG3_OTG_V_TOTAL_MAX 0x1cb1 9334 #define mmOTG3_OTG_V_TOTAL_MAX_BASE_IDX 2 9335 #define mmOTG3_OTG_V_TOTAL_MID 0x1cb2 9336 #define mmOTG3_OTG_V_TOTAL_MID_BASE_IDX 2 9337 #define mmOTG3_OTG_V_TOTAL_CONTROL 0x1cb3 9338 #define mmOTG3_OTG_V_TOTAL_CONTROL_BASE_IDX 2 9339 #define mmOTG3_OTG_V_TOTAL_INT_STATUS 0x1cb4 9340 #define mmOTG3_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2 9341 #define mmOTG3_OTG_VSYNC_NOM_INT_STATUS 0x1cb5 9342 #define mmOTG3_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2 9343 #define mmOTG3_OTG_V_BLANK_START_END 0x1cb6 9344 #define mmOTG3_OTG_V_BLANK_START_END_BASE_IDX 2 9345 #define mmOTG3_OTG_V_SYNC_A 0x1cb7 9346 #define mmOTG3_OTG_V_SYNC_A_BASE_IDX 2 9347 #define mmOTG3_OTG_V_SYNC_A_CNTL 0x1cb8 9348 #define mmOTG3_OTG_V_SYNC_A_CNTL_BASE_IDX 2 9349 #define mmOTG3_OTG_TRIGA_CNTL 0x1cb9 9350 #define mmOTG3_OTG_TRIGA_CNTL_BASE_IDX 2 9351 #define mmOTG3_OTG_TRIGA_MANUAL_TRIG 0x1cba 9352 #define mmOTG3_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2 9353 #define mmOTG3_OTG_TRIGB_CNTL 0x1cbb 9354 #define mmOTG3_OTG_TRIGB_CNTL_BASE_IDX 2 9355 #define mmOTG3_OTG_TRIGB_MANUAL_TRIG 0x1cbc 9356 #define mmOTG3_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2 9357 #define mmOTG3_OTG_FORCE_COUNT_NOW_CNTL 0x1cbd 9358 #define mmOTG3_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 9359 #define mmOTG3_OTG_FLOW_CONTROL 0x1cbe 9360 #define mmOTG3_OTG_FLOW_CONTROL_BASE_IDX 2 9361 #define mmOTG3_OTG_STEREO_FORCE_NEXT_EYE 0x1cbf 9362 #define mmOTG3_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 9363 #define mmOTG3_OTG_CONTROL 0x1cc1 9364 #define mmOTG3_OTG_CONTROL_BASE_IDX 2 9365 #define mmOTG3_OTG_BLANK_CONTROL 0x1cc2 9366 #define mmOTG3_OTG_BLANK_CONTROL_BASE_IDX 2 9367 #define mmOTG3_OTG_INTERLACE_CONTROL 0x1cc4 9368 #define mmOTG3_OTG_INTERLACE_CONTROL_BASE_IDX 2 9369 #define mmOTG3_OTG_INTERLACE_STATUS 0x1cc5 9370 #define mmOTG3_OTG_INTERLACE_STATUS_BASE_IDX 2 9371 #define mmOTG3_OTG_PIXEL_DATA_READBACK0 0x1cc7 9372 #define mmOTG3_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2 9373 #define mmOTG3_OTG_PIXEL_DATA_READBACK1 0x1cc8 9374 #define mmOTG3_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2 9375 #define mmOTG3_OTG_STATUS 0x1cc9 9376 #define mmOTG3_OTG_STATUS_BASE_IDX 2 9377 #define mmOTG3_OTG_STATUS_POSITION 0x1cca 9378 #define mmOTG3_OTG_STATUS_POSITION_BASE_IDX 2 9379 #define mmOTG3_OTG_NOM_VERT_POSITION 0x1ccb 9380 #define mmOTG3_OTG_NOM_VERT_POSITION_BASE_IDX 2 9381 #define mmOTG3_OTG_STATUS_FRAME_COUNT 0x1ccc 9382 #define mmOTG3_OTG_STATUS_FRAME_COUNT_BASE_IDX 2 9383 #define mmOTG3_OTG_STATUS_VF_COUNT 0x1ccd 9384 #define mmOTG3_OTG_STATUS_VF_COUNT_BASE_IDX 2 9385 #define mmOTG3_OTG_STATUS_HV_COUNT 0x1cce 9386 #define mmOTG3_OTG_STATUS_HV_COUNT_BASE_IDX 2 9387 #define mmOTG3_OTG_COUNT_CONTROL 0x1ccf 9388 #define mmOTG3_OTG_COUNT_CONTROL_BASE_IDX 2 9389 #define mmOTG3_OTG_COUNT_RESET 0x1cd0 9390 #define mmOTG3_OTG_COUNT_RESET_BASE_IDX 2 9391 #define mmOTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1cd1 9392 #define mmOTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 9393 #define mmOTG3_OTG_VERT_SYNC_CONTROL 0x1cd2 9394 #define mmOTG3_OTG_VERT_SYNC_CONTROL_BASE_IDX 2 9395 #define mmOTG3_OTG_STEREO_STATUS 0x1cd3 9396 #define mmOTG3_OTG_STEREO_STATUS_BASE_IDX 2 9397 #define mmOTG3_OTG_STEREO_CONTROL 0x1cd4 9398 #define mmOTG3_OTG_STEREO_CONTROL_BASE_IDX 2 9399 #define mmOTG3_OTG_SNAPSHOT_STATUS 0x1cd5 9400 #define mmOTG3_OTG_SNAPSHOT_STATUS_BASE_IDX 2 9401 #define mmOTG3_OTG_SNAPSHOT_CONTROL 0x1cd6 9402 #define mmOTG3_OTG_SNAPSHOT_CONTROL_BASE_IDX 2 9403 #define mmOTG3_OTG_SNAPSHOT_POSITION 0x1cd7 9404 #define mmOTG3_OTG_SNAPSHOT_POSITION_BASE_IDX 2 9405 #define mmOTG3_OTG_SNAPSHOT_FRAME 0x1cd8 9406 #define mmOTG3_OTG_SNAPSHOT_FRAME_BASE_IDX 2 9407 #define mmOTG3_OTG_INTERRUPT_CONTROL 0x1cd9 9408 #define mmOTG3_OTG_INTERRUPT_CONTROL_BASE_IDX 2 9409 #define mmOTG3_OTG_UPDATE_LOCK 0x1cda 9410 #define mmOTG3_OTG_UPDATE_LOCK_BASE_IDX 2 9411 #define mmOTG3_OTG_DOUBLE_BUFFER_CONTROL 0x1cdb 9412 #define mmOTG3_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 9413 #define mmOTG3_OTG_MASTER_EN 0x1cdc 9414 #define mmOTG3_OTG_MASTER_EN_BASE_IDX 2 9415 #define mmOTG3_OTG_BLANK_DATA_COLOR 0x1cde 9416 #define mmOTG3_OTG_BLANK_DATA_COLOR_BASE_IDX 2 9417 #define mmOTG3_OTG_BLANK_DATA_COLOR_EXT 0x1cdf 9418 #define mmOTG3_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX 2 9419 #define mmOTG3_OTG_VERTICAL_INTERRUPT0_POSITION 0x1ce2 9420 #define mmOTG3_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 9421 #define mmOTG3_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1ce3 9422 #define mmOTG3_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 9423 #define mmOTG3_OTG_VERTICAL_INTERRUPT1_POSITION 0x1ce4 9424 #define mmOTG3_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 9425 #define mmOTG3_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1ce5 9426 #define mmOTG3_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 9427 #define mmOTG3_OTG_VERTICAL_INTERRUPT2_POSITION 0x1ce6 9428 #define mmOTG3_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 9429 #define mmOTG3_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1ce7 9430 #define mmOTG3_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 9431 #define mmOTG3_OTG_CRC_CNTL 0x1ce8 9432 #define mmOTG3_OTG_CRC_CNTL_BASE_IDX 2 9433 #define mmOTG3_OTG_CRC_CNTL2 0x1ce9 9434 #define mmOTG3_OTG_CRC_CNTL2_BASE_IDX 2 9435 #define mmOTG3_OTG_CRC0_WINDOWA_X_CONTROL 0x1cea 9436 #define mmOTG3_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 9437 #define mmOTG3_OTG_CRC0_WINDOWA_Y_CONTROL 0x1ceb 9438 #define mmOTG3_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 9439 #define mmOTG3_OTG_CRC0_WINDOWB_X_CONTROL 0x1cec 9440 #define mmOTG3_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 9441 #define mmOTG3_OTG_CRC0_WINDOWB_Y_CONTROL 0x1ced 9442 #define mmOTG3_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 9443 #define mmOTG3_OTG_CRC0_DATA_RG 0x1cee 9444 #define mmOTG3_OTG_CRC0_DATA_RG_BASE_IDX 2 9445 #define mmOTG3_OTG_CRC0_DATA_B 0x1cef 9446 #define mmOTG3_OTG_CRC0_DATA_B_BASE_IDX 2 9447 #define mmOTG3_OTG_CRC1_WINDOWA_X_CONTROL 0x1cf0 9448 #define mmOTG3_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 9449 #define mmOTG3_OTG_CRC1_WINDOWA_Y_CONTROL 0x1cf1 9450 #define mmOTG3_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 9451 #define mmOTG3_OTG_CRC1_WINDOWB_X_CONTROL 0x1cf2 9452 #define mmOTG3_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 9453 #define mmOTG3_OTG_CRC1_WINDOWB_Y_CONTROL 0x1cf3 9454 #define mmOTG3_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 9455 #define mmOTG3_OTG_CRC1_DATA_RG 0x1cf4 9456 #define mmOTG3_OTG_CRC1_DATA_RG_BASE_IDX 2 9457 #define mmOTG3_OTG_CRC1_DATA_B 0x1cf5 9458 #define mmOTG3_OTG_CRC1_DATA_B_BASE_IDX 2 9459 #define mmOTG3_OTG_CRC2_DATA_RG 0x1cf6 9460 #define mmOTG3_OTG_CRC2_DATA_RG_BASE_IDX 2 9461 #define mmOTG3_OTG_CRC2_DATA_B 0x1cf7 9462 #define mmOTG3_OTG_CRC2_DATA_B_BASE_IDX 2 9463 #define mmOTG3_OTG_CRC3_DATA_RG 0x1cf8 9464 #define mmOTG3_OTG_CRC3_DATA_RG_BASE_IDX 2 9465 #define mmOTG3_OTG_CRC3_DATA_B 0x1cf9 9466 #define mmOTG3_OTG_CRC3_DATA_B_BASE_IDX 2 9467 #define mmOTG3_OTG_CRC_SIG_RED_GREEN_MASK 0x1cfa 9468 #define mmOTG3_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 9469 #define mmOTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1cfb 9470 #define mmOTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 9471 #define mmOTG3_OTG_STATIC_SCREEN_CONTROL 0x1d02 9472 #define mmOTG3_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2 9473 #define mmOTG3_OTG_3D_STRUCTURE_CONTROL 0x1d03 9474 #define mmOTG3_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2 9475 #define mmOTG3_OTG_GSL_VSYNC_GAP 0x1d04 9476 #define mmOTG3_OTG_GSL_VSYNC_GAP_BASE_IDX 2 9477 #define mmOTG3_OTG_MASTER_UPDATE_MODE 0x1d05 9478 #define mmOTG3_OTG_MASTER_UPDATE_MODE_BASE_IDX 2 9479 #define mmOTG3_OTG_CLOCK_CONTROL 0x1d06 9480 #define mmOTG3_OTG_CLOCK_CONTROL_BASE_IDX 2 9481 #define mmOTG3_OTG_VSTARTUP_PARAM 0x1d07 9482 #define mmOTG3_OTG_VSTARTUP_PARAM_BASE_IDX 2 9483 #define mmOTG3_OTG_VUPDATE_PARAM 0x1d08 9484 #define mmOTG3_OTG_VUPDATE_PARAM_BASE_IDX 2 9485 #define mmOTG3_OTG_VREADY_PARAM 0x1d09 9486 #define mmOTG3_OTG_VREADY_PARAM_BASE_IDX 2 9487 #define mmOTG3_OTG_GLOBAL_SYNC_STATUS 0x1d0a 9488 #define mmOTG3_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2 9489 #define mmOTG3_OTG_MASTER_UPDATE_LOCK 0x1d0b 9490 #define mmOTG3_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2 9491 #define mmOTG3_OTG_GSL_CONTROL 0x1d0c 9492 #define mmOTG3_OTG_GSL_CONTROL_BASE_IDX 2 9493 #define mmOTG3_OTG_GSL_WINDOW_X 0x1d0d 9494 #define mmOTG3_OTG_GSL_WINDOW_X_BASE_IDX 2 9495 #define mmOTG3_OTG_GSL_WINDOW_Y 0x1d0e 9496 #define mmOTG3_OTG_GSL_WINDOW_Y_BASE_IDX 2 9497 #define mmOTG3_OTG_VUPDATE_KEEPOUT 0x1d0f 9498 #define mmOTG3_OTG_VUPDATE_KEEPOUT_BASE_IDX 2 9499 #define mmOTG3_OTG_GLOBAL_CONTROL0 0x1d10 9500 #define mmOTG3_OTG_GLOBAL_CONTROL0_BASE_IDX 2 9501 #define mmOTG3_OTG_GLOBAL_CONTROL1 0x1d11 9502 #define mmOTG3_OTG_GLOBAL_CONTROL1_BASE_IDX 2 9503 #define mmOTG3_OTG_GLOBAL_CONTROL2 0x1d12 9504 #define mmOTG3_OTG_GLOBAL_CONTROL2_BASE_IDX 2 9505 #define mmOTG3_OTG_GLOBAL_CONTROL3 0x1d13 9506 #define mmOTG3_OTG_GLOBAL_CONTROL3_BASE_IDX 2 9507 #define mmOTG3_OTG_GLOBAL_CONTROL4 0x1d14 9508 #define mmOTG3_OTG_GLOBAL_CONTROL4_BASE_IDX 2 9509 #define mmOTG3_OTG_TRIG_MANUAL_CONTROL 0x1d15 9510 #define mmOTG3_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2 9511 #define mmOTG3_OTG_MANUAL_FLOW_CONTROL 0x1d16 9512 #define mmOTG3_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2 9513 #define mmOTG3_OTG_DRR_TIMING_INT_STATUS 0x1d17 9514 #define mmOTG3_OTG_DRR_TIMING_INT_STATUS_BASE_IDX 2 9515 #define mmOTG3_OTG_DRR_V_TOTAL_REACH_RANGE 0x1d18 9516 #define mmOTG3_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX 2 9517 #define mmOTG3_OTG_DRR_V_TOTAL_CHANGE 0x1d19 9518 #define mmOTG3_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX 2 9519 #define mmOTG3_OTG_DRR_TRIGGER_WINDOW 0x1d1a 9520 #define mmOTG3_OTG_DRR_TRIGGER_WINDOW_BASE_IDX 2 9521 #define mmOTG3_OTG_DRR_CONTROL 0x1d1b 9522 #define mmOTG3_OTG_DRR_CONTROL_BASE_IDX 2 9523 #define mmOTG3_OTG_M_CONST_DTO0 0x1d1c 9524 #define mmOTG3_OTG_M_CONST_DTO0_BASE_IDX 2 9525 #define mmOTG3_OTG_M_CONST_DTO1 0x1d1d 9526 #define mmOTG3_OTG_M_CONST_DTO1_BASE_IDX 2 9527 #define mmOTG3_OTG_REQUEST_CONTROL 0x1d1e 9528 #define mmOTG3_OTG_REQUEST_CONTROL_BASE_IDX 2 9529 #define mmOTG3_OTG_DSC_START_POSITION 0x1d1f 9530 #define mmOTG3_OTG_DSC_START_POSITION_BASE_IDX 2 9531 #define mmOTG3_OTG_PIPE_UPDATE_STATUS 0x1d20 9532 #define mmOTG3_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2 9533 #define mmOTG3_OTG_SPARE_REGISTER 0x1d22 9534 #define mmOTG3_OTG_SPARE_REGISTER_BASE_IDX 2 9535 9536 9537 // addressBlock: dce_dc_optc_otg4_dispdec 9538 // base address: 0x800 9539 #define mmOTG4_OTG_H_TOTAL 0x1d2a 9540 #define mmOTG4_OTG_H_TOTAL_BASE_IDX 2 9541 #define mmOTG4_OTG_H_BLANK_START_END 0x1d2b 9542 #define mmOTG4_OTG_H_BLANK_START_END_BASE_IDX 2 9543 #define mmOTG4_OTG_H_SYNC_A 0x1d2c 9544 #define mmOTG4_OTG_H_SYNC_A_BASE_IDX 2 9545 #define mmOTG4_OTG_H_SYNC_A_CNTL 0x1d2d 9546 #define mmOTG4_OTG_H_SYNC_A_CNTL_BASE_IDX 2 9547 #define mmOTG4_OTG_H_TIMING_CNTL 0x1d2e 9548 #define mmOTG4_OTG_H_TIMING_CNTL_BASE_IDX 2 9549 #define mmOTG4_OTG_V_TOTAL 0x1d2f 9550 #define mmOTG4_OTG_V_TOTAL_BASE_IDX 2 9551 #define mmOTG4_OTG_V_TOTAL_MIN 0x1d30 9552 #define mmOTG4_OTG_V_TOTAL_MIN_BASE_IDX 2 9553 #define mmOTG4_OTG_V_TOTAL_MAX 0x1d31 9554 #define mmOTG4_OTG_V_TOTAL_MAX_BASE_IDX 2 9555 #define mmOTG4_OTG_V_TOTAL_MID 0x1d32 9556 #define mmOTG4_OTG_V_TOTAL_MID_BASE_IDX 2 9557 #define mmOTG4_OTG_V_TOTAL_CONTROL 0x1d33 9558 #define mmOTG4_OTG_V_TOTAL_CONTROL_BASE_IDX 2 9559 #define mmOTG4_OTG_V_TOTAL_INT_STATUS 0x1d34 9560 #define mmOTG4_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2 9561 #define mmOTG4_OTG_VSYNC_NOM_INT_STATUS 0x1d35 9562 #define mmOTG4_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2 9563 #define mmOTG4_OTG_V_BLANK_START_END 0x1d36 9564 #define mmOTG4_OTG_V_BLANK_START_END_BASE_IDX 2 9565 #define mmOTG4_OTG_V_SYNC_A 0x1d37 9566 #define mmOTG4_OTG_V_SYNC_A_BASE_IDX 2 9567 #define mmOTG4_OTG_V_SYNC_A_CNTL 0x1d38 9568 #define mmOTG4_OTG_V_SYNC_A_CNTL_BASE_IDX 2 9569 #define mmOTG4_OTG_TRIGA_CNTL 0x1d39 9570 #define mmOTG4_OTG_TRIGA_CNTL_BASE_IDX 2 9571 #define mmOTG4_OTG_TRIGA_MANUAL_TRIG 0x1d3a 9572 #define mmOTG4_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2 9573 #define mmOTG4_OTG_TRIGB_CNTL 0x1d3b 9574 #define mmOTG4_OTG_TRIGB_CNTL_BASE_IDX 2 9575 #define mmOTG4_OTG_TRIGB_MANUAL_TRIG 0x1d3c 9576 #define mmOTG4_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2 9577 #define mmOTG4_OTG_FORCE_COUNT_NOW_CNTL 0x1d3d 9578 #define mmOTG4_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 9579 #define mmOTG4_OTG_FLOW_CONTROL 0x1d3e 9580 #define mmOTG4_OTG_FLOW_CONTROL_BASE_IDX 2 9581 #define mmOTG4_OTG_STEREO_FORCE_NEXT_EYE 0x1d3f 9582 #define mmOTG4_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 9583 #define mmOTG4_OTG_CONTROL 0x1d41 9584 #define mmOTG4_OTG_CONTROL_BASE_IDX 2 9585 #define mmOTG4_OTG_BLANK_CONTROL 0x1d42 9586 #define mmOTG4_OTG_BLANK_CONTROL_BASE_IDX 2 9587 #define mmOTG4_OTG_INTERLACE_CONTROL 0x1d44 9588 #define mmOTG4_OTG_INTERLACE_CONTROL_BASE_IDX 2 9589 #define mmOTG4_OTG_INTERLACE_STATUS 0x1d45 9590 #define mmOTG4_OTG_INTERLACE_STATUS_BASE_IDX 2 9591 #define mmOTG4_OTG_PIXEL_DATA_READBACK0 0x1d47 9592 #define mmOTG4_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2 9593 #define mmOTG4_OTG_PIXEL_DATA_READBACK1 0x1d48 9594 #define mmOTG4_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2 9595 #define mmOTG4_OTG_STATUS 0x1d49 9596 #define mmOTG4_OTG_STATUS_BASE_IDX 2 9597 #define mmOTG4_OTG_STATUS_POSITION 0x1d4a 9598 #define mmOTG4_OTG_STATUS_POSITION_BASE_IDX 2 9599 #define mmOTG4_OTG_NOM_VERT_POSITION 0x1d4b 9600 #define mmOTG4_OTG_NOM_VERT_POSITION_BASE_IDX 2 9601 #define mmOTG4_OTG_STATUS_FRAME_COUNT 0x1d4c 9602 #define mmOTG4_OTG_STATUS_FRAME_COUNT_BASE_IDX 2 9603 #define mmOTG4_OTG_STATUS_VF_COUNT 0x1d4d 9604 #define mmOTG4_OTG_STATUS_VF_COUNT_BASE_IDX 2 9605 #define mmOTG4_OTG_STATUS_HV_COUNT 0x1d4e 9606 #define mmOTG4_OTG_STATUS_HV_COUNT_BASE_IDX 2 9607 #define mmOTG4_OTG_COUNT_CONTROL 0x1d4f 9608 #define mmOTG4_OTG_COUNT_CONTROL_BASE_IDX 2 9609 #define mmOTG4_OTG_COUNT_RESET 0x1d50 9610 #define mmOTG4_OTG_COUNT_RESET_BASE_IDX 2 9611 #define mmOTG4_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1d51 9612 #define mmOTG4_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 9613 #define mmOTG4_OTG_VERT_SYNC_CONTROL 0x1d52 9614 #define mmOTG4_OTG_VERT_SYNC_CONTROL_BASE_IDX 2 9615 #define mmOTG4_OTG_STEREO_STATUS 0x1d53 9616 #define mmOTG4_OTG_STEREO_STATUS_BASE_IDX 2 9617 #define mmOTG4_OTG_STEREO_CONTROL 0x1d54 9618 #define mmOTG4_OTG_STEREO_CONTROL_BASE_IDX 2 9619 #define mmOTG4_OTG_SNAPSHOT_STATUS 0x1d55 9620 #define mmOTG4_OTG_SNAPSHOT_STATUS_BASE_IDX 2 9621 #define mmOTG4_OTG_SNAPSHOT_CONTROL 0x1d56 9622 #define mmOTG4_OTG_SNAPSHOT_CONTROL_BASE_IDX 2 9623 #define mmOTG4_OTG_SNAPSHOT_POSITION 0x1d57 9624 #define mmOTG4_OTG_SNAPSHOT_POSITION_BASE_IDX 2 9625 #define mmOTG4_OTG_SNAPSHOT_FRAME 0x1d58 9626 #define mmOTG4_OTG_SNAPSHOT_FRAME_BASE_IDX 2 9627 #define mmOTG4_OTG_INTERRUPT_CONTROL 0x1d59 9628 #define mmOTG4_OTG_INTERRUPT_CONTROL_BASE_IDX 2 9629 #define mmOTG4_OTG_UPDATE_LOCK 0x1d5a 9630 #define mmOTG4_OTG_UPDATE_LOCK_BASE_IDX 2 9631 #define mmOTG4_OTG_DOUBLE_BUFFER_CONTROL 0x1d5b 9632 #define mmOTG4_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 9633 #define mmOTG4_OTG_MASTER_EN 0x1d5c 9634 #define mmOTG4_OTG_MASTER_EN_BASE_IDX 2 9635 #define mmOTG4_OTG_BLANK_DATA_COLOR 0x1d5e 9636 #define mmOTG4_OTG_BLANK_DATA_COLOR_BASE_IDX 2 9637 #define mmOTG4_OTG_BLANK_DATA_COLOR_EXT 0x1d5f 9638 #define mmOTG4_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX 2 9639 #define mmOTG4_OTG_VERTICAL_INTERRUPT0_POSITION 0x1d62 9640 #define mmOTG4_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 9641 #define mmOTG4_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1d63 9642 #define mmOTG4_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 9643 #define mmOTG4_OTG_VERTICAL_INTERRUPT1_POSITION 0x1d64 9644 #define mmOTG4_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 9645 #define mmOTG4_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1d65 9646 #define mmOTG4_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 9647 #define mmOTG4_OTG_VERTICAL_INTERRUPT2_POSITION 0x1d66 9648 #define mmOTG4_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 9649 #define mmOTG4_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1d67 9650 #define mmOTG4_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 9651 #define mmOTG4_OTG_CRC_CNTL 0x1d68 9652 #define mmOTG4_OTG_CRC_CNTL_BASE_IDX 2 9653 #define mmOTG4_OTG_CRC_CNTL2 0x1d69 9654 #define mmOTG4_OTG_CRC_CNTL2_BASE_IDX 2 9655 #define mmOTG4_OTG_CRC0_WINDOWA_X_CONTROL 0x1d6a 9656 #define mmOTG4_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 9657 #define mmOTG4_OTG_CRC0_WINDOWA_Y_CONTROL 0x1d6b 9658 #define mmOTG4_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 9659 #define mmOTG4_OTG_CRC0_WINDOWB_X_CONTROL 0x1d6c 9660 #define mmOTG4_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 9661 #define mmOTG4_OTG_CRC0_WINDOWB_Y_CONTROL 0x1d6d 9662 #define mmOTG4_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 9663 #define mmOTG4_OTG_CRC0_DATA_RG 0x1d6e 9664 #define mmOTG4_OTG_CRC0_DATA_RG_BASE_IDX 2 9665 #define mmOTG4_OTG_CRC0_DATA_B 0x1d6f 9666 #define mmOTG4_OTG_CRC0_DATA_B_BASE_IDX 2 9667 #define mmOTG4_OTG_CRC1_WINDOWA_X_CONTROL 0x1d70 9668 #define mmOTG4_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 9669 #define mmOTG4_OTG_CRC1_WINDOWA_Y_CONTROL 0x1d71 9670 #define mmOTG4_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 9671 #define mmOTG4_OTG_CRC1_WINDOWB_X_CONTROL 0x1d72 9672 #define mmOTG4_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 9673 #define mmOTG4_OTG_CRC1_WINDOWB_Y_CONTROL 0x1d73 9674 #define mmOTG4_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 9675 #define mmOTG4_OTG_CRC1_DATA_RG 0x1d74 9676 #define mmOTG4_OTG_CRC1_DATA_RG_BASE_IDX 2 9677 #define mmOTG4_OTG_CRC1_DATA_B 0x1d75 9678 #define mmOTG4_OTG_CRC1_DATA_B_BASE_IDX 2 9679 #define mmOTG4_OTG_CRC2_DATA_RG 0x1d76 9680 #define mmOTG4_OTG_CRC2_DATA_RG_BASE_IDX 2 9681 #define mmOTG4_OTG_CRC2_DATA_B 0x1d77 9682 #define mmOTG4_OTG_CRC2_DATA_B_BASE_IDX 2 9683 #define mmOTG4_OTG_CRC3_DATA_RG 0x1d78 9684 #define mmOTG4_OTG_CRC3_DATA_RG_BASE_IDX 2 9685 #define mmOTG4_OTG_CRC3_DATA_B 0x1d79 9686 #define mmOTG4_OTG_CRC3_DATA_B_BASE_IDX 2 9687 #define mmOTG4_OTG_CRC_SIG_RED_GREEN_MASK 0x1d7a 9688 #define mmOTG4_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 9689 #define mmOTG4_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1d7b 9690 #define mmOTG4_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 9691 #define mmOTG4_OTG_STATIC_SCREEN_CONTROL 0x1d82 9692 #define mmOTG4_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2 9693 #define mmOTG4_OTG_3D_STRUCTURE_CONTROL 0x1d83 9694 #define mmOTG4_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2 9695 #define mmOTG4_OTG_GSL_VSYNC_GAP 0x1d84 9696 #define mmOTG4_OTG_GSL_VSYNC_GAP_BASE_IDX 2 9697 #define mmOTG4_OTG_MASTER_UPDATE_MODE 0x1d85 9698 #define mmOTG4_OTG_MASTER_UPDATE_MODE_BASE_IDX 2 9699 #define mmOTG4_OTG_CLOCK_CONTROL 0x1d86 9700 #define mmOTG4_OTG_CLOCK_CONTROL_BASE_IDX 2 9701 #define mmOTG4_OTG_VSTARTUP_PARAM 0x1d87 9702 #define mmOTG4_OTG_VSTARTUP_PARAM_BASE_IDX 2 9703 #define mmOTG4_OTG_VUPDATE_PARAM 0x1d88 9704 #define mmOTG4_OTG_VUPDATE_PARAM_BASE_IDX 2 9705 #define mmOTG4_OTG_VREADY_PARAM 0x1d89 9706 #define mmOTG4_OTG_VREADY_PARAM_BASE_IDX 2 9707 #define mmOTG4_OTG_GLOBAL_SYNC_STATUS 0x1d8a 9708 #define mmOTG4_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2 9709 #define mmOTG4_OTG_MASTER_UPDATE_LOCK 0x1d8b 9710 #define mmOTG4_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2 9711 #define mmOTG4_OTG_GSL_CONTROL 0x1d8c 9712 #define mmOTG4_OTG_GSL_CONTROL_BASE_IDX 2 9713 #define mmOTG4_OTG_GSL_WINDOW_X 0x1d8d 9714 #define mmOTG4_OTG_GSL_WINDOW_X_BASE_IDX 2 9715 #define mmOTG4_OTG_GSL_WINDOW_Y 0x1d8e 9716 #define mmOTG4_OTG_GSL_WINDOW_Y_BASE_IDX 2 9717 #define mmOTG4_OTG_VUPDATE_KEEPOUT 0x1d8f 9718 #define mmOTG4_OTG_VUPDATE_KEEPOUT_BASE_IDX 2 9719 #define mmOTG4_OTG_GLOBAL_CONTROL0 0x1d90 9720 #define mmOTG4_OTG_GLOBAL_CONTROL0_BASE_IDX 2 9721 #define mmOTG4_OTG_GLOBAL_CONTROL1 0x1d91 9722 #define mmOTG4_OTG_GLOBAL_CONTROL1_BASE_IDX 2 9723 #define mmOTG4_OTG_GLOBAL_CONTROL2 0x1d92 9724 #define mmOTG4_OTG_GLOBAL_CONTROL2_BASE_IDX 2 9725 #define mmOTG4_OTG_GLOBAL_CONTROL3 0x1d93 9726 #define mmOTG4_OTG_GLOBAL_CONTROL3_BASE_IDX 2 9727 #define mmOTG4_OTG_GLOBAL_CONTROL4 0x1d94 9728 #define mmOTG4_OTG_GLOBAL_CONTROL4_BASE_IDX 2 9729 #define mmOTG4_OTG_TRIG_MANUAL_CONTROL 0x1d95 9730 #define mmOTG4_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2 9731 #define mmOTG4_OTG_MANUAL_FLOW_CONTROL 0x1d96 9732 #define mmOTG4_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2 9733 #define mmOTG4_OTG_DRR_TIMING_INT_STATUS 0x1d97 9734 #define mmOTG4_OTG_DRR_TIMING_INT_STATUS_BASE_IDX 2 9735 #define mmOTG4_OTG_DRR_V_TOTAL_REACH_RANGE 0x1d98 9736 #define mmOTG4_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX 2 9737 #define mmOTG4_OTG_DRR_V_TOTAL_CHANGE 0x1d99 9738 #define mmOTG4_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX 2 9739 #define mmOTG4_OTG_DRR_TRIGGER_WINDOW 0x1d9a 9740 #define mmOTG4_OTG_DRR_TRIGGER_WINDOW_BASE_IDX 2 9741 #define mmOTG4_OTG_DRR_CONTROL 0x1d9b 9742 #define mmOTG4_OTG_DRR_CONTROL_BASE_IDX 2 9743 #define mmOTG4_OTG_M_CONST_DTO0 0x1d9c 9744 #define mmOTG4_OTG_M_CONST_DTO0_BASE_IDX 2 9745 #define mmOTG4_OTG_M_CONST_DTO1 0x1d9d 9746 #define mmOTG4_OTG_M_CONST_DTO1_BASE_IDX 2 9747 #define mmOTG4_OTG_REQUEST_CONTROL 0x1d9e 9748 #define mmOTG4_OTG_REQUEST_CONTROL_BASE_IDX 2 9749 #define mmOTG4_OTG_DSC_START_POSITION 0x1d9f 9750 #define mmOTG4_OTG_DSC_START_POSITION_BASE_IDX 2 9751 #define mmOTG4_OTG_PIPE_UPDATE_STATUS 0x1da0 9752 #define mmOTG4_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2 9753 #define mmOTG4_OTG_SPARE_REGISTER 0x1da2 9754 #define mmOTG4_OTG_SPARE_REGISTER_BASE_IDX 2 9755 9756 9757 // addressBlock: dce_dc_optc_otg5_dispdec 9758 // base address: 0xa00 9759 #define mmOTG5_OTG_H_TOTAL 0x1daa 9760 #define mmOTG5_OTG_H_TOTAL_BASE_IDX 2 9761 #define mmOTG5_OTG_H_BLANK_START_END 0x1dab 9762 #define mmOTG5_OTG_H_BLANK_START_END_BASE_IDX 2 9763 #define mmOTG5_OTG_H_SYNC_A 0x1dac 9764 #define mmOTG5_OTG_H_SYNC_A_BASE_IDX 2 9765 #define mmOTG5_OTG_H_SYNC_A_CNTL 0x1dad 9766 #define mmOTG5_OTG_H_SYNC_A_CNTL_BASE_IDX 2 9767 #define mmOTG5_OTG_H_TIMING_CNTL 0x1dae 9768 #define mmOTG5_OTG_H_TIMING_CNTL_BASE_IDX 2 9769 #define mmOTG5_OTG_V_TOTAL 0x1daf 9770 #define mmOTG5_OTG_V_TOTAL_BASE_IDX 2 9771 #define mmOTG5_OTG_V_TOTAL_MIN 0x1db0 9772 #define mmOTG5_OTG_V_TOTAL_MIN_BASE_IDX 2 9773 #define mmOTG5_OTG_V_TOTAL_MAX 0x1db1 9774 #define mmOTG5_OTG_V_TOTAL_MAX_BASE_IDX 2 9775 #define mmOTG5_OTG_V_TOTAL_MID 0x1db2 9776 #define mmOTG5_OTG_V_TOTAL_MID_BASE_IDX 2 9777 #define mmOTG5_OTG_V_TOTAL_CONTROL 0x1db3 9778 #define mmOTG5_OTG_V_TOTAL_CONTROL_BASE_IDX 2 9779 #define mmOTG5_OTG_V_TOTAL_INT_STATUS 0x1db4 9780 #define mmOTG5_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2 9781 #define mmOTG5_OTG_VSYNC_NOM_INT_STATUS 0x1db5 9782 #define mmOTG5_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2 9783 #define mmOTG5_OTG_V_BLANK_START_END 0x1db6 9784 #define mmOTG5_OTG_V_BLANK_START_END_BASE_IDX 2 9785 #define mmOTG5_OTG_V_SYNC_A 0x1db7 9786 #define mmOTG5_OTG_V_SYNC_A_BASE_IDX 2 9787 #define mmOTG5_OTG_V_SYNC_A_CNTL 0x1db8 9788 #define mmOTG5_OTG_V_SYNC_A_CNTL_BASE_IDX 2 9789 #define mmOTG5_OTG_TRIGA_CNTL 0x1db9 9790 #define mmOTG5_OTG_TRIGA_CNTL_BASE_IDX 2 9791 #define mmOTG5_OTG_TRIGA_MANUAL_TRIG 0x1dba 9792 #define mmOTG5_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2 9793 #define mmOTG5_OTG_TRIGB_CNTL 0x1dbb 9794 #define mmOTG5_OTG_TRIGB_CNTL_BASE_IDX 2 9795 #define mmOTG5_OTG_TRIGB_MANUAL_TRIG 0x1dbc 9796 #define mmOTG5_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2 9797 #define mmOTG5_OTG_FORCE_COUNT_NOW_CNTL 0x1dbd 9798 #define mmOTG5_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 9799 #define mmOTG5_OTG_FLOW_CONTROL 0x1dbe 9800 #define mmOTG5_OTG_FLOW_CONTROL_BASE_IDX 2 9801 #define mmOTG5_OTG_STEREO_FORCE_NEXT_EYE 0x1dbf 9802 #define mmOTG5_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 9803 #define mmOTG5_OTG_CONTROL 0x1dc1 9804 #define mmOTG5_OTG_CONTROL_BASE_IDX 2 9805 #define mmOTG5_OTG_BLANK_CONTROL 0x1dc2 9806 #define mmOTG5_OTG_BLANK_CONTROL_BASE_IDX 2 9807 #define mmOTG5_OTG_INTERLACE_CONTROL 0x1dc4 9808 #define mmOTG5_OTG_INTERLACE_CONTROL_BASE_IDX 2 9809 #define mmOTG5_OTG_INTERLACE_STATUS 0x1dc5 9810 #define mmOTG5_OTG_INTERLACE_STATUS_BASE_IDX 2 9811 #define mmOTG5_OTG_PIXEL_DATA_READBACK0 0x1dc7 9812 #define mmOTG5_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2 9813 #define mmOTG5_OTG_PIXEL_DATA_READBACK1 0x1dc8 9814 #define mmOTG5_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2 9815 #define mmOTG5_OTG_STATUS 0x1dc9 9816 #define mmOTG5_OTG_STATUS_BASE_IDX 2 9817 #define mmOTG5_OTG_STATUS_POSITION 0x1dca 9818 #define mmOTG5_OTG_STATUS_POSITION_BASE_IDX 2 9819 #define mmOTG5_OTG_NOM_VERT_POSITION 0x1dcb 9820 #define mmOTG5_OTG_NOM_VERT_POSITION_BASE_IDX 2 9821 #define mmOTG5_OTG_STATUS_FRAME_COUNT 0x1dcc 9822 #define mmOTG5_OTG_STATUS_FRAME_COUNT_BASE_IDX 2 9823 #define mmOTG5_OTG_STATUS_VF_COUNT 0x1dcd 9824 #define mmOTG5_OTG_STATUS_VF_COUNT_BASE_IDX 2 9825 #define mmOTG5_OTG_STATUS_HV_COUNT 0x1dce 9826 #define mmOTG5_OTG_STATUS_HV_COUNT_BASE_IDX 2 9827 #define mmOTG5_OTG_COUNT_CONTROL 0x1dcf 9828 #define mmOTG5_OTG_COUNT_CONTROL_BASE_IDX 2 9829 #define mmOTG5_OTG_COUNT_RESET 0x1dd0 9830 #define mmOTG5_OTG_COUNT_RESET_BASE_IDX 2 9831 #define mmOTG5_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1dd1 9832 #define mmOTG5_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 9833 #define mmOTG5_OTG_VERT_SYNC_CONTROL 0x1dd2 9834 #define mmOTG5_OTG_VERT_SYNC_CONTROL_BASE_IDX 2 9835 #define mmOTG5_OTG_STEREO_STATUS 0x1dd3 9836 #define mmOTG5_OTG_STEREO_STATUS_BASE_IDX 2 9837 #define mmOTG5_OTG_STEREO_CONTROL 0x1dd4 9838 #define mmOTG5_OTG_STEREO_CONTROL_BASE_IDX 2 9839 #define mmOTG5_OTG_SNAPSHOT_STATUS 0x1dd5 9840 #define mmOTG5_OTG_SNAPSHOT_STATUS_BASE_IDX 2 9841 #define mmOTG5_OTG_SNAPSHOT_CONTROL 0x1dd6 9842 #define mmOTG5_OTG_SNAPSHOT_CONTROL_BASE_IDX 2 9843 #define mmOTG5_OTG_SNAPSHOT_POSITION 0x1dd7 9844 #define mmOTG5_OTG_SNAPSHOT_POSITION_BASE_IDX 2 9845 #define mmOTG5_OTG_SNAPSHOT_FRAME 0x1dd8 9846 #define mmOTG5_OTG_SNAPSHOT_FRAME_BASE_IDX 2 9847 #define mmOTG5_OTG_INTERRUPT_CONTROL 0x1dd9 9848 #define mmOTG5_OTG_INTERRUPT_CONTROL_BASE_IDX 2 9849 #define mmOTG5_OTG_UPDATE_LOCK 0x1dda 9850 #define mmOTG5_OTG_UPDATE_LOCK_BASE_IDX 2 9851 #define mmOTG5_OTG_DOUBLE_BUFFER_CONTROL 0x1ddb 9852 #define mmOTG5_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 9853 #define mmOTG5_OTG_MASTER_EN 0x1ddc 9854 #define mmOTG5_OTG_MASTER_EN_BASE_IDX 2 9855 #define mmOTG5_OTG_BLANK_DATA_COLOR 0x1dde 9856 #define mmOTG5_OTG_BLANK_DATA_COLOR_BASE_IDX 2 9857 #define mmOTG5_OTG_BLANK_DATA_COLOR_EXT 0x1ddf 9858 #define mmOTG5_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX 2 9859 #define mmOTG5_OTG_VERTICAL_INTERRUPT0_POSITION 0x1de2 9860 #define mmOTG5_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 9861 #define mmOTG5_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1de3 9862 #define mmOTG5_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 9863 #define mmOTG5_OTG_VERTICAL_INTERRUPT1_POSITION 0x1de4 9864 #define mmOTG5_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 9865 #define mmOTG5_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1de5 9866 #define mmOTG5_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 9867 #define mmOTG5_OTG_VERTICAL_INTERRUPT2_POSITION 0x1de6 9868 #define mmOTG5_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 9869 #define mmOTG5_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1de7 9870 #define mmOTG5_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 9871 #define mmOTG5_OTG_CRC_CNTL 0x1de8 9872 #define mmOTG5_OTG_CRC_CNTL_BASE_IDX 2 9873 #define mmOTG5_OTG_CRC_CNTL2 0x1de9 9874 #define mmOTG5_OTG_CRC_CNTL2_BASE_IDX 2 9875 #define mmOTG5_OTG_CRC0_WINDOWA_X_CONTROL 0x1dea 9876 #define mmOTG5_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 9877 #define mmOTG5_OTG_CRC0_WINDOWA_Y_CONTROL 0x1deb 9878 #define mmOTG5_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 9879 #define mmOTG5_OTG_CRC0_WINDOWB_X_CONTROL 0x1dec 9880 #define mmOTG5_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 9881 #define mmOTG5_OTG_CRC0_WINDOWB_Y_CONTROL 0x1ded 9882 #define mmOTG5_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 9883 #define mmOTG5_OTG_CRC0_DATA_RG 0x1dee 9884 #define mmOTG5_OTG_CRC0_DATA_RG_BASE_IDX 2 9885 #define mmOTG5_OTG_CRC0_DATA_B 0x1def 9886 #define mmOTG5_OTG_CRC0_DATA_B_BASE_IDX 2 9887 #define mmOTG5_OTG_CRC1_WINDOWA_X_CONTROL 0x1df0 9888 #define mmOTG5_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 9889 #define mmOTG5_OTG_CRC1_WINDOWA_Y_CONTROL 0x1df1 9890 #define mmOTG5_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 9891 #define mmOTG5_OTG_CRC1_WINDOWB_X_CONTROL 0x1df2 9892 #define mmOTG5_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 9893 #define mmOTG5_OTG_CRC1_WINDOWB_Y_CONTROL 0x1df3 9894 #define mmOTG5_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 9895 #define mmOTG5_OTG_CRC1_DATA_RG 0x1df4 9896 #define mmOTG5_OTG_CRC1_DATA_RG_BASE_IDX 2 9897 #define mmOTG5_OTG_CRC1_DATA_B 0x1df5 9898 #define mmOTG5_OTG_CRC1_DATA_B_BASE_IDX 2 9899 #define mmOTG5_OTG_CRC2_DATA_RG 0x1df6 9900 #define mmOTG5_OTG_CRC2_DATA_RG_BASE_IDX 2 9901 #define mmOTG5_OTG_CRC2_DATA_B 0x1df7 9902 #define mmOTG5_OTG_CRC2_DATA_B_BASE_IDX 2 9903 #define mmOTG5_OTG_CRC3_DATA_RG 0x1df8 9904 #define mmOTG5_OTG_CRC3_DATA_RG_BASE_IDX 2 9905 #define mmOTG5_OTG_CRC3_DATA_B 0x1df9 9906 #define mmOTG5_OTG_CRC3_DATA_B_BASE_IDX 2 9907 #define mmOTG5_OTG_CRC_SIG_RED_GREEN_MASK 0x1dfa 9908 #define mmOTG5_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 9909 #define mmOTG5_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1dfb 9910 #define mmOTG5_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 9911 #define mmOTG5_OTG_STATIC_SCREEN_CONTROL 0x1e02 9912 #define mmOTG5_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2 9913 #define mmOTG5_OTG_3D_STRUCTURE_CONTROL 0x1e03 9914 #define mmOTG5_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2 9915 #define mmOTG5_OTG_GSL_VSYNC_GAP 0x1e04 9916 #define mmOTG5_OTG_GSL_VSYNC_GAP_BASE_IDX 2 9917 #define mmOTG5_OTG_MASTER_UPDATE_MODE 0x1e05 9918 #define mmOTG5_OTG_MASTER_UPDATE_MODE_BASE_IDX 2 9919 #define mmOTG5_OTG_CLOCK_CONTROL 0x1e06 9920 #define mmOTG5_OTG_CLOCK_CONTROL_BASE_IDX 2 9921 #define mmOTG5_OTG_VSTARTUP_PARAM 0x1e07 9922 #define mmOTG5_OTG_VSTARTUP_PARAM_BASE_IDX 2 9923 #define mmOTG5_OTG_VUPDATE_PARAM 0x1e08 9924 #define mmOTG5_OTG_VUPDATE_PARAM_BASE_IDX 2 9925 #define mmOTG5_OTG_VREADY_PARAM 0x1e09 9926 #define mmOTG5_OTG_VREADY_PARAM_BASE_IDX 2 9927 #define mmOTG5_OTG_GLOBAL_SYNC_STATUS 0x1e0a 9928 #define mmOTG5_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2 9929 #define mmOTG5_OTG_MASTER_UPDATE_LOCK 0x1e0b 9930 #define mmOTG5_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2 9931 #define mmOTG5_OTG_GSL_CONTROL 0x1e0c 9932 #define mmOTG5_OTG_GSL_CONTROL_BASE_IDX 2 9933 #define mmOTG5_OTG_GSL_WINDOW_X 0x1e0d 9934 #define mmOTG5_OTG_GSL_WINDOW_X_BASE_IDX 2 9935 #define mmOTG5_OTG_GSL_WINDOW_Y 0x1e0e 9936 #define mmOTG5_OTG_GSL_WINDOW_Y_BASE_IDX 2 9937 #define mmOTG5_OTG_VUPDATE_KEEPOUT 0x1e0f 9938 #define mmOTG5_OTG_VUPDATE_KEEPOUT_BASE_IDX 2 9939 #define mmOTG5_OTG_GLOBAL_CONTROL0 0x1e10 9940 #define mmOTG5_OTG_GLOBAL_CONTROL0_BASE_IDX 2 9941 #define mmOTG5_OTG_GLOBAL_CONTROL1 0x1e11 9942 #define mmOTG5_OTG_GLOBAL_CONTROL1_BASE_IDX 2 9943 #define mmOTG5_OTG_GLOBAL_CONTROL2 0x1e12 9944 #define mmOTG5_OTG_GLOBAL_CONTROL2_BASE_IDX 2 9945 #define mmOTG5_OTG_GLOBAL_CONTROL3 0x1e13 9946 #define mmOTG5_OTG_GLOBAL_CONTROL3_BASE_IDX 2 9947 #define mmOTG5_OTG_GLOBAL_CONTROL4 0x1e14 9948 #define mmOTG5_OTG_GLOBAL_CONTROL4_BASE_IDX 2 9949 #define mmOTG5_OTG_TRIG_MANUAL_CONTROL 0x1e15 9950 #define mmOTG5_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2 9951 #define mmOTG5_OTG_MANUAL_FLOW_CONTROL 0x1e16 9952 #define mmOTG5_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2 9953 #define mmOTG5_OTG_DRR_TIMING_INT_STATUS 0x1e17 9954 #define mmOTG5_OTG_DRR_TIMING_INT_STATUS_BASE_IDX 2 9955 #define mmOTG5_OTG_DRR_V_TOTAL_REACH_RANGE 0x1e18 9956 #define mmOTG5_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX 2 9957 #define mmOTG5_OTG_DRR_V_TOTAL_CHANGE 0x1e19 9958 #define mmOTG5_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX 2 9959 #define mmOTG5_OTG_DRR_TRIGGER_WINDOW 0x1e1a 9960 #define mmOTG5_OTG_DRR_TRIGGER_WINDOW_BASE_IDX 2 9961 #define mmOTG5_OTG_DRR_CONTROL 0x1e1b 9962 #define mmOTG5_OTG_DRR_CONTROL_BASE_IDX 2 9963 #define mmOTG5_OTG_M_CONST_DTO0 0x1e1c 9964 #define mmOTG5_OTG_M_CONST_DTO0_BASE_IDX 2 9965 #define mmOTG5_OTG_M_CONST_DTO1 0x1e1d 9966 #define mmOTG5_OTG_M_CONST_DTO1_BASE_IDX 2 9967 #define mmOTG5_OTG_REQUEST_CONTROL 0x1e1e 9968 #define mmOTG5_OTG_REQUEST_CONTROL_BASE_IDX 2 9969 #define mmOTG5_OTG_DSC_START_POSITION 0x1e1f 9970 #define mmOTG5_OTG_DSC_START_POSITION_BASE_IDX 2 9971 #define mmOTG5_OTG_PIPE_UPDATE_STATUS 0x1e20 9972 #define mmOTG5_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2 9973 #define mmOTG5_OTG_SPARE_REGISTER 0x1e22 9974 #define mmOTG5_OTG_SPARE_REGISTER_BASE_IDX 2 9975 9976 9977 // addressBlock: dce_dc_optc_optc_misc_dispdec 9978 // base address: 0x0 9979 #define mmDWB_SOURCE_SELECT 0x1e2a 9980 #define mmDWB_SOURCE_SELECT_BASE_IDX 2 9981 #define mmGSL_SOURCE_SELECT 0x1e2b 9982 #define mmGSL_SOURCE_SELECT_BASE_IDX 2 9983 #define mmOPTC_CLOCK_CONTROL 0x1e2c 9984 #define mmOPTC_CLOCK_CONTROL_BASE_IDX 2 9985 #define mmODM_MEM_PWR_CTRL 0x1e2d 9986 #define mmODM_MEM_PWR_CTRL_BASE_IDX 2 9987 #define mmODM_MEM_PWR_CTRL2 0x1e2e 9988 #define mmODM_MEM_PWR_CTRL2_BASE_IDX 2 9989 #define mmODM_MEM_PWR_CTRL3 0x1e2f 9990 #define mmODM_MEM_PWR_CTRL3_BASE_IDX 2 9991 #define mmODM_MEM_PWR_STATUS 0x1e30 9992 #define mmODM_MEM_PWR_STATUS_BASE_IDX 2 9993 #define mmOPTC_MISC_SPARE_REGISTER 0x1e31 9994 #define mmOPTC_MISC_SPARE_REGISTER_BASE_IDX 2 9995 9996 9997 // addressBlock: dce_dc_optc_optc_dcperfmon_dc_perfmon_dispdec 9998 // base address: 0x79a8 9999 #define mmDC_PERFMON19_PERFCOUNTER_CNTL 0x1e6a 10000 #define mmDC_PERFMON19_PERFCOUNTER_CNTL_BASE_IDX 2 10001 #define mmDC_PERFMON19_PERFCOUNTER_CNTL2 0x1e6b 10002 #define mmDC_PERFMON19_PERFCOUNTER_CNTL2_BASE_IDX 2 10003 #define mmDC_PERFMON19_PERFCOUNTER_STATE 0x1e6c 10004 #define mmDC_PERFMON19_PERFCOUNTER_STATE_BASE_IDX 2 10005 #define mmDC_PERFMON19_PERFMON_CNTL 0x1e6d 10006 #define mmDC_PERFMON19_PERFMON_CNTL_BASE_IDX 2 10007 #define mmDC_PERFMON19_PERFMON_CNTL2 0x1e6e 10008 #define mmDC_PERFMON19_PERFMON_CNTL2_BASE_IDX 2 10009 #define mmDC_PERFMON19_PERFMON_CVALUE_INT_MISC 0x1e6f 10010 #define mmDC_PERFMON19_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 10011 #define mmDC_PERFMON19_PERFMON_CVALUE_LOW 0x1e70 10012 #define mmDC_PERFMON19_PERFMON_CVALUE_LOW_BASE_IDX 2 10013 #define mmDC_PERFMON19_PERFMON_HI 0x1e71 10014 #define mmDC_PERFMON19_PERFMON_HI_BASE_IDX 2 10015 #define mmDC_PERFMON19_PERFMON_LOW 0x1e72 10016 #define mmDC_PERFMON19_PERFMON_LOW_BASE_IDX 2 10017 10018 10019 // addressBlock: dce_dc_dio_dout_i2c_dispdec 10020 // base address: 0x0 10021 #define mmDC_I2C_CONTROL 0x1e98 10022 #define mmDC_I2C_CONTROL_BASE_IDX 2 10023 #define mmDC_I2C_ARBITRATION 0x1e99 10024 #define mmDC_I2C_ARBITRATION_BASE_IDX 2 10025 #define mmDC_I2C_INTERRUPT_CONTROL 0x1e9a 10026 #define mmDC_I2C_INTERRUPT_CONTROL_BASE_IDX 2 10027 #define mmDC_I2C_SW_STATUS 0x1e9b 10028 #define mmDC_I2C_SW_STATUS_BASE_IDX 2 10029 #define mmDC_I2C_DDC1_HW_STATUS 0x1e9c 10030 #define mmDC_I2C_DDC1_HW_STATUS_BASE_IDX 2 10031 #define mmDC_I2C_DDC2_HW_STATUS 0x1e9d 10032 #define mmDC_I2C_DDC2_HW_STATUS_BASE_IDX 2 10033 #define mmDC_I2C_DDC3_HW_STATUS 0x1e9e 10034 #define mmDC_I2C_DDC3_HW_STATUS_BASE_IDX 2 10035 #define mmDC_I2C_DDC4_HW_STATUS 0x1e9f 10036 #define mmDC_I2C_DDC4_HW_STATUS_BASE_IDX 2 10037 #define mmDC_I2C_DDC5_HW_STATUS 0x1ea0 10038 #define mmDC_I2C_DDC5_HW_STATUS_BASE_IDX 2 10039 #define mmDC_I2C_DDC6_HW_STATUS 0x1ea1 10040 #define mmDC_I2C_DDC6_HW_STATUS_BASE_IDX 2 10041 #define mmDC_I2C_DDC1_SPEED 0x1ea2 10042 #define mmDC_I2C_DDC1_SPEED_BASE_IDX 2 10043 #define mmDC_I2C_DDC1_SETUP 0x1ea3 10044 #define mmDC_I2C_DDC1_SETUP_BASE_IDX 2 10045 #define mmDC_I2C_DDC2_SPEED 0x1ea4 10046 #define mmDC_I2C_DDC2_SPEED_BASE_IDX 2 10047 #define mmDC_I2C_DDC2_SETUP 0x1ea5 10048 #define mmDC_I2C_DDC2_SETUP_BASE_IDX 2 10049 #define mmDC_I2C_DDC3_SPEED 0x1ea6 10050 #define mmDC_I2C_DDC3_SPEED_BASE_IDX 2 10051 #define mmDC_I2C_DDC3_SETUP 0x1ea7 10052 #define mmDC_I2C_DDC3_SETUP_BASE_IDX 2 10053 #define mmDC_I2C_DDC4_SPEED 0x1ea8 10054 #define mmDC_I2C_DDC4_SPEED_BASE_IDX 2 10055 #define mmDC_I2C_DDC4_SETUP 0x1ea9 10056 #define mmDC_I2C_DDC4_SETUP_BASE_IDX 2 10057 #define mmDC_I2C_DDC5_SPEED 0x1eaa 10058 #define mmDC_I2C_DDC5_SPEED_BASE_IDX 2 10059 #define mmDC_I2C_DDC5_SETUP 0x1eab 10060 #define mmDC_I2C_DDC5_SETUP_BASE_IDX 2 10061 #define mmDC_I2C_DDC6_SPEED 0x1eac 10062 #define mmDC_I2C_DDC6_SPEED_BASE_IDX 2 10063 #define mmDC_I2C_DDC6_SETUP 0x1ead 10064 #define mmDC_I2C_DDC6_SETUP_BASE_IDX 2 10065 #define mmDC_I2C_TRANSACTION0 0x1eae 10066 #define mmDC_I2C_TRANSACTION0_BASE_IDX 2 10067 #define mmDC_I2C_TRANSACTION1 0x1eaf 10068 #define mmDC_I2C_TRANSACTION1_BASE_IDX 2 10069 #define mmDC_I2C_TRANSACTION2 0x1eb0 10070 #define mmDC_I2C_TRANSACTION2_BASE_IDX 2 10071 #define mmDC_I2C_TRANSACTION3 0x1eb1 10072 #define mmDC_I2C_TRANSACTION3_BASE_IDX 2 10073 #define mmDC_I2C_DATA 0x1eb2 10074 #define mmDC_I2C_DATA_BASE_IDX 2 10075 #define mmDC_I2C_EDID_DETECT_CTRL 0x1eb6 10076 #define mmDC_I2C_EDID_DETECT_CTRL_BASE_IDX 2 10077 #define mmDC_I2C_READ_REQUEST_INTERRUPT 0x1eb7 10078 #define mmDC_I2C_READ_REQUEST_INTERRUPT_BASE_IDX 2 10079 10080 10081 // addressBlock: dce_dc_dio_dio_misc_dispdec 10082 // base address: 0x0 10083 #define mmDIO_SCRATCH0 0x1eca 10084 #define mmDIO_SCRATCH0_BASE_IDX 2 10085 #define mmDIO_SCRATCH1 0x1ecb 10086 #define mmDIO_SCRATCH1_BASE_IDX 2 10087 #define mmDIO_SCRATCH2 0x1ecc 10088 #define mmDIO_SCRATCH2_BASE_IDX 2 10089 #define mmDIO_SCRATCH3 0x1ecd 10090 #define mmDIO_SCRATCH3_BASE_IDX 2 10091 #define mmDIO_SCRATCH4 0x1ece 10092 #define mmDIO_SCRATCH4_BASE_IDX 2 10093 #define mmDIO_SCRATCH5 0x1ecf 10094 #define mmDIO_SCRATCH5_BASE_IDX 2 10095 #define mmDIO_SCRATCH6 0x1ed0 10096 #define mmDIO_SCRATCH6_BASE_IDX 2 10097 #define mmDIO_SCRATCH7 0x1ed1 10098 #define mmDIO_SCRATCH7_BASE_IDX 2 10099 #define mmDIO_MEM_PWR_STATUS 0x1edd 10100 #define mmDIO_MEM_PWR_STATUS_BASE_IDX 2 10101 #define mmDIO_MEM_PWR_CTRL 0x1ede 10102 #define mmDIO_MEM_PWR_CTRL_BASE_IDX 2 10103 #define mmDIO_MEM_PWR_CTRL2 0x1edf 10104 #define mmDIO_MEM_PWR_CTRL2_BASE_IDX 2 10105 #define mmDIO_CLK_CNTL 0x1ee0 10106 #define mmDIO_CLK_CNTL_BASE_IDX 2 10107 #define mmDIO_POWER_MANAGEMENT_CNTL 0x1ee4 10108 #define mmDIO_POWER_MANAGEMENT_CNTL_BASE_IDX 2 10109 #define mmDIG_SOFT_RESET 0x1eee 10110 #define mmDIG_SOFT_RESET_BASE_IDX 2 10111 #define mmDIO_CLK_CNTL2 0x1ef2 10112 #define mmDIO_CLK_CNTL2_BASE_IDX 2 10113 #define mmDIO_CLK_CNTL3 0x1ef3 10114 #define mmDIO_CLK_CNTL3_BASE_IDX 2 10115 #define mmDIO_HDMI_RXSTATUS_TIMER_CONTROL 0x1eff 10116 #define mmDIO_HDMI_RXSTATUS_TIMER_CONTROL_BASE_IDX 2 10117 #define mmDIO_GENERIC_INTERRUPT_MESSAGE 0x1f02 10118 #define mmDIO_GENERIC_INTERRUPT_MESSAGE_BASE_IDX 2 10119 #define mmDIO_GENERIC_INTERRUPT_CLEAR 0x1f03 10120 #define mmDIO_GENERIC_INTERRUPT_CLEAR_BASE_IDX 2 10121 10122 10123 // addressBlock: dce_dc_dio_hpd0_dispdec 10124 // base address: 0x0 10125 #define mmHPD0_DC_HPD_INT_STATUS 0x1f14 10126 #define mmHPD0_DC_HPD_INT_STATUS_BASE_IDX 2 10127 #define mmHPD0_DC_HPD_INT_CONTROL 0x1f15 10128 #define mmHPD0_DC_HPD_INT_CONTROL_BASE_IDX 2 10129 #define mmHPD0_DC_HPD_CONTROL 0x1f16 10130 #define mmHPD0_DC_HPD_CONTROL_BASE_IDX 2 10131 #define mmHPD0_DC_HPD_FAST_TRAIN_CNTL 0x1f17 10132 #define mmHPD0_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 10133 #define mmHPD0_DC_HPD_TOGGLE_FILT_CNTL 0x1f18 10134 #define mmHPD0_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 10135 10136 10137 // addressBlock: dce_dc_dio_hpd1_dispdec 10138 // base address: 0x20 10139 #define mmHPD1_DC_HPD_INT_STATUS 0x1f1c 10140 #define mmHPD1_DC_HPD_INT_STATUS_BASE_IDX 2 10141 #define mmHPD1_DC_HPD_INT_CONTROL 0x1f1d 10142 #define mmHPD1_DC_HPD_INT_CONTROL_BASE_IDX 2 10143 #define mmHPD1_DC_HPD_CONTROL 0x1f1e 10144 #define mmHPD1_DC_HPD_CONTROL_BASE_IDX 2 10145 #define mmHPD1_DC_HPD_FAST_TRAIN_CNTL 0x1f1f 10146 #define mmHPD1_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 10147 #define mmHPD1_DC_HPD_TOGGLE_FILT_CNTL 0x1f20 10148 #define mmHPD1_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 10149 10150 10151 // addressBlock: dce_dc_dio_hpd2_dispdec 10152 // base address: 0x40 10153 #define mmHPD2_DC_HPD_INT_STATUS 0x1f24 10154 #define mmHPD2_DC_HPD_INT_STATUS_BASE_IDX 2 10155 #define mmHPD2_DC_HPD_INT_CONTROL 0x1f25 10156 #define mmHPD2_DC_HPD_INT_CONTROL_BASE_IDX 2 10157 #define mmHPD2_DC_HPD_CONTROL 0x1f26 10158 #define mmHPD2_DC_HPD_CONTROL_BASE_IDX 2 10159 #define mmHPD2_DC_HPD_FAST_TRAIN_CNTL 0x1f27 10160 #define mmHPD2_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 10161 #define mmHPD2_DC_HPD_TOGGLE_FILT_CNTL 0x1f28 10162 #define mmHPD2_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 10163 10164 10165 // addressBlock: dce_dc_dio_hpd3_dispdec 10166 // base address: 0x60 10167 #define mmHPD3_DC_HPD_INT_STATUS 0x1f2c 10168 #define mmHPD3_DC_HPD_INT_STATUS_BASE_IDX 2 10169 #define mmHPD3_DC_HPD_INT_CONTROL 0x1f2d 10170 #define mmHPD3_DC_HPD_INT_CONTROL_BASE_IDX 2 10171 #define mmHPD3_DC_HPD_CONTROL 0x1f2e 10172 #define mmHPD3_DC_HPD_CONTROL_BASE_IDX 2 10173 #define mmHPD3_DC_HPD_FAST_TRAIN_CNTL 0x1f2f 10174 #define mmHPD3_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 10175 #define mmHPD3_DC_HPD_TOGGLE_FILT_CNTL 0x1f30 10176 #define mmHPD3_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 10177 10178 10179 // addressBlock: dce_dc_dio_hpd4_dispdec 10180 // base address: 0x80 10181 #define mmHPD4_DC_HPD_INT_STATUS 0x1f34 10182 #define mmHPD4_DC_HPD_INT_STATUS_BASE_IDX 2 10183 #define mmHPD4_DC_HPD_INT_CONTROL 0x1f35 10184 #define mmHPD4_DC_HPD_INT_CONTROL_BASE_IDX 2 10185 #define mmHPD4_DC_HPD_CONTROL 0x1f36 10186 #define mmHPD4_DC_HPD_CONTROL_BASE_IDX 2 10187 #define mmHPD4_DC_HPD_FAST_TRAIN_CNTL 0x1f37 10188 #define mmHPD4_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 10189 #define mmHPD4_DC_HPD_TOGGLE_FILT_CNTL 0x1f38 10190 #define mmHPD4_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 10191 10192 10193 // addressBlock: dce_dc_dio_hpd5_dispdec 10194 // base address: 0xa0 10195 #define mmHPD5_DC_HPD_INT_STATUS 0x1f3c 10196 #define mmHPD5_DC_HPD_INT_STATUS_BASE_IDX 2 10197 #define mmHPD5_DC_HPD_INT_CONTROL 0x1f3d 10198 #define mmHPD5_DC_HPD_INT_CONTROL_BASE_IDX 2 10199 #define mmHPD5_DC_HPD_CONTROL 0x1f3e 10200 #define mmHPD5_DC_HPD_CONTROL_BASE_IDX 2 10201 #define mmHPD5_DC_HPD_FAST_TRAIN_CNTL 0x1f3f 10202 #define mmHPD5_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 10203 #define mmHPD5_DC_HPD_TOGGLE_FILT_CNTL 0x1f40 10204 #define mmHPD5_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 10205 10206 10207 // addressBlock: dce_dc_dio_dio_dcperfmon_dc_perfmon_dispdec 10208 // base address: 0x7d10 10209 #define mmDC_PERFMON20_PERFCOUNTER_CNTL 0x1f44 10210 #define mmDC_PERFMON20_PERFCOUNTER_CNTL_BASE_IDX 2 10211 #define mmDC_PERFMON20_PERFCOUNTER_CNTL2 0x1f45 10212 #define mmDC_PERFMON20_PERFCOUNTER_CNTL2_BASE_IDX 2 10213 #define mmDC_PERFMON20_PERFCOUNTER_STATE 0x1f46 10214 #define mmDC_PERFMON20_PERFCOUNTER_STATE_BASE_IDX 2 10215 #define mmDC_PERFMON20_PERFMON_CNTL 0x1f47 10216 #define mmDC_PERFMON20_PERFMON_CNTL_BASE_IDX 2 10217 #define mmDC_PERFMON20_PERFMON_CNTL2 0x1f48 10218 #define mmDC_PERFMON20_PERFMON_CNTL2_BASE_IDX 2 10219 #define mmDC_PERFMON20_PERFMON_CVALUE_INT_MISC 0x1f49 10220 #define mmDC_PERFMON20_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 10221 #define mmDC_PERFMON20_PERFMON_CVALUE_LOW 0x1f4a 10222 #define mmDC_PERFMON20_PERFMON_CVALUE_LOW_BASE_IDX 2 10223 #define mmDC_PERFMON20_PERFMON_HI 0x1f4b 10224 #define mmDC_PERFMON20_PERFMON_HI_BASE_IDX 2 10225 #define mmDC_PERFMON20_PERFMON_LOW 0x1f4c 10226 #define mmDC_PERFMON20_PERFMON_LOW_BASE_IDX 2 10227 10228 10229 // addressBlock: dce_dc_dio_dp_aux0_dispdec 10230 // base address: 0x0 10231 #define mmDP_AUX0_AUX_CONTROL 0x1f50 10232 #define mmDP_AUX0_AUX_CONTROL_BASE_IDX 2 10233 #define mmDP_AUX0_AUX_SW_CONTROL 0x1f51 10234 #define mmDP_AUX0_AUX_SW_CONTROL_BASE_IDX 2 10235 #define mmDP_AUX0_AUX_ARB_CONTROL 0x1f52 10236 #define mmDP_AUX0_AUX_ARB_CONTROL_BASE_IDX 2 10237 #define mmDP_AUX0_AUX_INTERRUPT_CONTROL 0x1f53 10238 #define mmDP_AUX0_AUX_INTERRUPT_CONTROL_BASE_IDX 2 10239 #define mmDP_AUX0_AUX_SW_STATUS 0x1f54 10240 #define mmDP_AUX0_AUX_SW_STATUS_BASE_IDX 2 10241 #define mmDP_AUX0_AUX_LS_STATUS 0x1f55 10242 #define mmDP_AUX0_AUX_LS_STATUS_BASE_IDX 2 10243 #define mmDP_AUX0_AUX_SW_DATA 0x1f56 10244 #define mmDP_AUX0_AUX_SW_DATA_BASE_IDX 2 10245 #define mmDP_AUX0_AUX_LS_DATA 0x1f57 10246 #define mmDP_AUX0_AUX_LS_DATA_BASE_IDX 2 10247 #define mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL 0x1f58 10248 #define mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 10249 #define mmDP_AUX0_AUX_DPHY_TX_CONTROL 0x1f59 10250 #define mmDP_AUX0_AUX_DPHY_TX_CONTROL_BASE_IDX 2 10251 #define mmDP_AUX0_AUX_DPHY_RX_CONTROL0 0x1f5a 10252 #define mmDP_AUX0_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 10253 #define mmDP_AUX0_AUX_DPHY_RX_CONTROL1 0x1f5b 10254 #define mmDP_AUX0_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 10255 #define mmDP_AUX0_AUX_DPHY_TX_STATUS 0x1f5c 10256 #define mmDP_AUX0_AUX_DPHY_TX_STATUS_BASE_IDX 2 10257 #define mmDP_AUX0_AUX_DPHY_RX_STATUS 0x1f5d 10258 #define mmDP_AUX0_AUX_DPHY_RX_STATUS_BASE_IDX 2 10259 #define mmDP_AUX0_AUX_GTC_SYNC_CONTROL 0x1f5e 10260 #define mmDP_AUX0_AUX_GTC_SYNC_CONTROL_BASE_IDX 2 10261 #define mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL 0x1f5f 10262 #define mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 10263 #define mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1f60 10264 #define mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 10265 #define mmDP_AUX0_AUX_GTC_SYNC_STATUS 0x1f61 10266 #define mmDP_AUX0_AUX_GTC_SYNC_STATUS_BASE_IDX 2 10267 #define mmDP_AUX0_AUX_PHY_WAKE_CNTL 0x1f66 10268 #define mmDP_AUX0_AUX_PHY_WAKE_CNTL_BASE_IDX 2 10269 10270 10271 // addressBlock: dce_dc_dio_dp_aux1_dispdec 10272 // base address: 0x70 10273 #define mmDP_AUX1_AUX_CONTROL 0x1f6c 10274 #define mmDP_AUX1_AUX_CONTROL_BASE_IDX 2 10275 #define mmDP_AUX1_AUX_SW_CONTROL 0x1f6d 10276 #define mmDP_AUX1_AUX_SW_CONTROL_BASE_IDX 2 10277 #define mmDP_AUX1_AUX_ARB_CONTROL 0x1f6e 10278 #define mmDP_AUX1_AUX_ARB_CONTROL_BASE_IDX 2 10279 #define mmDP_AUX1_AUX_INTERRUPT_CONTROL 0x1f6f 10280 #define mmDP_AUX1_AUX_INTERRUPT_CONTROL_BASE_IDX 2 10281 #define mmDP_AUX1_AUX_SW_STATUS 0x1f70 10282 #define mmDP_AUX1_AUX_SW_STATUS_BASE_IDX 2 10283 #define mmDP_AUX1_AUX_LS_STATUS 0x1f71 10284 #define mmDP_AUX1_AUX_LS_STATUS_BASE_IDX 2 10285 #define mmDP_AUX1_AUX_SW_DATA 0x1f72 10286 #define mmDP_AUX1_AUX_SW_DATA_BASE_IDX 2 10287 #define mmDP_AUX1_AUX_LS_DATA 0x1f73 10288 #define mmDP_AUX1_AUX_LS_DATA_BASE_IDX 2 10289 #define mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL 0x1f74 10290 #define mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 10291 #define mmDP_AUX1_AUX_DPHY_TX_CONTROL 0x1f75 10292 #define mmDP_AUX1_AUX_DPHY_TX_CONTROL_BASE_IDX 2 10293 #define mmDP_AUX1_AUX_DPHY_RX_CONTROL0 0x1f76 10294 #define mmDP_AUX1_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 10295 #define mmDP_AUX1_AUX_DPHY_RX_CONTROL1 0x1f77 10296 #define mmDP_AUX1_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 10297 #define mmDP_AUX1_AUX_DPHY_TX_STATUS 0x1f78 10298 #define mmDP_AUX1_AUX_DPHY_TX_STATUS_BASE_IDX 2 10299 #define mmDP_AUX1_AUX_DPHY_RX_STATUS 0x1f79 10300 #define mmDP_AUX1_AUX_DPHY_RX_STATUS_BASE_IDX 2 10301 #define mmDP_AUX1_AUX_GTC_SYNC_CONTROL 0x1f7a 10302 #define mmDP_AUX1_AUX_GTC_SYNC_CONTROL_BASE_IDX 2 10303 #define mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL 0x1f7b 10304 #define mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 10305 #define mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1f7c 10306 #define mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 10307 #define mmDP_AUX1_AUX_GTC_SYNC_STATUS 0x1f7d 10308 #define mmDP_AUX1_AUX_GTC_SYNC_STATUS_BASE_IDX 2 10309 #define mmDP_AUX1_AUX_PHY_WAKE_CNTL 0x1f82 10310 #define mmDP_AUX1_AUX_PHY_WAKE_CNTL_BASE_IDX 2 10311 10312 10313 // addressBlock: dce_dc_dio_dp_aux2_dispdec 10314 // base address: 0xe0 10315 #define mmDP_AUX2_AUX_CONTROL 0x1f88 10316 #define mmDP_AUX2_AUX_CONTROL_BASE_IDX 2 10317 #define mmDP_AUX2_AUX_SW_CONTROL 0x1f89 10318 #define mmDP_AUX2_AUX_SW_CONTROL_BASE_IDX 2 10319 #define mmDP_AUX2_AUX_ARB_CONTROL 0x1f8a 10320 #define mmDP_AUX2_AUX_ARB_CONTROL_BASE_IDX 2 10321 #define mmDP_AUX2_AUX_INTERRUPT_CONTROL 0x1f8b 10322 #define mmDP_AUX2_AUX_INTERRUPT_CONTROL_BASE_IDX 2 10323 #define mmDP_AUX2_AUX_SW_STATUS 0x1f8c 10324 #define mmDP_AUX2_AUX_SW_STATUS_BASE_IDX 2 10325 #define mmDP_AUX2_AUX_LS_STATUS 0x1f8d 10326 #define mmDP_AUX2_AUX_LS_STATUS_BASE_IDX 2 10327 #define mmDP_AUX2_AUX_SW_DATA 0x1f8e 10328 #define mmDP_AUX2_AUX_SW_DATA_BASE_IDX 2 10329 #define mmDP_AUX2_AUX_LS_DATA 0x1f8f 10330 #define mmDP_AUX2_AUX_LS_DATA_BASE_IDX 2 10331 #define mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL 0x1f90 10332 #define mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 10333 #define mmDP_AUX2_AUX_DPHY_TX_CONTROL 0x1f91 10334 #define mmDP_AUX2_AUX_DPHY_TX_CONTROL_BASE_IDX 2 10335 #define mmDP_AUX2_AUX_DPHY_RX_CONTROL0 0x1f92 10336 #define mmDP_AUX2_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 10337 #define mmDP_AUX2_AUX_DPHY_RX_CONTROL1 0x1f93 10338 #define mmDP_AUX2_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 10339 #define mmDP_AUX2_AUX_DPHY_TX_STATUS 0x1f94 10340 #define mmDP_AUX2_AUX_DPHY_TX_STATUS_BASE_IDX 2 10341 #define mmDP_AUX2_AUX_DPHY_RX_STATUS 0x1f95 10342 #define mmDP_AUX2_AUX_DPHY_RX_STATUS_BASE_IDX 2 10343 #define mmDP_AUX2_AUX_GTC_SYNC_CONTROL 0x1f96 10344 #define mmDP_AUX2_AUX_GTC_SYNC_CONTROL_BASE_IDX 2 10345 #define mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL 0x1f97 10346 #define mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 10347 #define mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1f98 10348 #define mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 10349 #define mmDP_AUX2_AUX_GTC_SYNC_STATUS 0x1f99 10350 #define mmDP_AUX2_AUX_GTC_SYNC_STATUS_BASE_IDX 2 10351 #define mmDP_AUX2_AUX_PHY_WAKE_CNTL 0x1f9e 10352 #define mmDP_AUX2_AUX_PHY_WAKE_CNTL_BASE_IDX 2 10353 10354 10355 // addressBlock: dce_dc_dio_dp_aux3_dispdec 10356 // base address: 0x150 10357 #define mmDP_AUX3_AUX_CONTROL 0x1fa4 10358 #define mmDP_AUX3_AUX_CONTROL_BASE_IDX 2 10359 #define mmDP_AUX3_AUX_SW_CONTROL 0x1fa5 10360 #define mmDP_AUX3_AUX_SW_CONTROL_BASE_IDX 2 10361 #define mmDP_AUX3_AUX_ARB_CONTROL 0x1fa6 10362 #define mmDP_AUX3_AUX_ARB_CONTROL_BASE_IDX 2 10363 #define mmDP_AUX3_AUX_INTERRUPT_CONTROL 0x1fa7 10364 #define mmDP_AUX3_AUX_INTERRUPT_CONTROL_BASE_IDX 2 10365 #define mmDP_AUX3_AUX_SW_STATUS 0x1fa8 10366 #define mmDP_AUX3_AUX_SW_STATUS_BASE_IDX 2 10367 #define mmDP_AUX3_AUX_LS_STATUS 0x1fa9 10368 #define mmDP_AUX3_AUX_LS_STATUS_BASE_IDX 2 10369 #define mmDP_AUX3_AUX_SW_DATA 0x1faa 10370 #define mmDP_AUX3_AUX_SW_DATA_BASE_IDX 2 10371 #define mmDP_AUX3_AUX_LS_DATA 0x1fab 10372 #define mmDP_AUX3_AUX_LS_DATA_BASE_IDX 2 10373 #define mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL 0x1fac 10374 #define mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 10375 #define mmDP_AUX3_AUX_DPHY_TX_CONTROL 0x1fad 10376 #define mmDP_AUX3_AUX_DPHY_TX_CONTROL_BASE_IDX 2 10377 #define mmDP_AUX3_AUX_DPHY_RX_CONTROL0 0x1fae 10378 #define mmDP_AUX3_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 10379 #define mmDP_AUX3_AUX_DPHY_RX_CONTROL1 0x1faf 10380 #define mmDP_AUX3_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 10381 #define mmDP_AUX3_AUX_DPHY_TX_STATUS 0x1fb0 10382 #define mmDP_AUX3_AUX_DPHY_TX_STATUS_BASE_IDX 2 10383 #define mmDP_AUX3_AUX_DPHY_RX_STATUS 0x1fb1 10384 #define mmDP_AUX3_AUX_DPHY_RX_STATUS_BASE_IDX 2 10385 #define mmDP_AUX3_AUX_GTC_SYNC_CONTROL 0x1fb2 10386 #define mmDP_AUX3_AUX_GTC_SYNC_CONTROL_BASE_IDX 2 10387 #define mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL 0x1fb3 10388 #define mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 10389 #define mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1fb4 10390 #define mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 10391 #define mmDP_AUX3_AUX_GTC_SYNC_STATUS 0x1fb5 10392 #define mmDP_AUX3_AUX_GTC_SYNC_STATUS_BASE_IDX 2 10393 #define mmDP_AUX3_AUX_PHY_WAKE_CNTL 0x1fba 10394 #define mmDP_AUX3_AUX_PHY_WAKE_CNTL_BASE_IDX 2 10395 10396 10397 // addressBlock: dce_dc_dio_dp_aux4_dispdec 10398 // base address: 0x1c0 10399 #define mmDP_AUX4_AUX_CONTROL 0x1fc0 10400 #define mmDP_AUX4_AUX_CONTROL_BASE_IDX 2 10401 #define mmDP_AUX4_AUX_SW_CONTROL 0x1fc1 10402 #define mmDP_AUX4_AUX_SW_CONTROL_BASE_IDX 2 10403 #define mmDP_AUX4_AUX_ARB_CONTROL 0x1fc2 10404 #define mmDP_AUX4_AUX_ARB_CONTROL_BASE_IDX 2 10405 #define mmDP_AUX4_AUX_INTERRUPT_CONTROL 0x1fc3 10406 #define mmDP_AUX4_AUX_INTERRUPT_CONTROL_BASE_IDX 2 10407 #define mmDP_AUX4_AUX_SW_STATUS 0x1fc4 10408 #define mmDP_AUX4_AUX_SW_STATUS_BASE_IDX 2 10409 #define mmDP_AUX4_AUX_LS_STATUS 0x1fc5 10410 #define mmDP_AUX4_AUX_LS_STATUS_BASE_IDX 2 10411 #define mmDP_AUX4_AUX_SW_DATA 0x1fc6 10412 #define mmDP_AUX4_AUX_SW_DATA_BASE_IDX 2 10413 #define mmDP_AUX4_AUX_LS_DATA 0x1fc7 10414 #define mmDP_AUX4_AUX_LS_DATA_BASE_IDX 2 10415 #define mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL 0x1fc8 10416 #define mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 10417 #define mmDP_AUX4_AUX_DPHY_TX_CONTROL 0x1fc9 10418 #define mmDP_AUX4_AUX_DPHY_TX_CONTROL_BASE_IDX 2 10419 #define mmDP_AUX4_AUX_DPHY_RX_CONTROL0 0x1fca 10420 #define mmDP_AUX4_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 10421 #define mmDP_AUX4_AUX_DPHY_RX_CONTROL1 0x1fcb 10422 #define mmDP_AUX4_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 10423 #define mmDP_AUX4_AUX_DPHY_TX_STATUS 0x1fcc 10424 #define mmDP_AUX4_AUX_DPHY_TX_STATUS_BASE_IDX 2 10425 #define mmDP_AUX4_AUX_DPHY_RX_STATUS 0x1fcd 10426 #define mmDP_AUX4_AUX_DPHY_RX_STATUS_BASE_IDX 2 10427 #define mmDP_AUX4_AUX_GTC_SYNC_CONTROL 0x1fce 10428 #define mmDP_AUX4_AUX_GTC_SYNC_CONTROL_BASE_IDX 2 10429 #define mmDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL 0x1fcf 10430 #define mmDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 10431 #define mmDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1fd0 10432 #define mmDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 10433 #define mmDP_AUX4_AUX_GTC_SYNC_STATUS 0x1fd1 10434 #define mmDP_AUX4_AUX_GTC_SYNC_STATUS_BASE_IDX 2 10435 #define mmDP_AUX4_AUX_PHY_WAKE_CNTL 0x1fd6 10436 #define mmDP_AUX4_AUX_PHY_WAKE_CNTL_BASE_IDX 2 10437 10438 10439 // addressBlock: dce_dc_dio_dp_aux5_dispdec 10440 // base address: 0x230 10441 #define mmDP_AUX5_AUX_CONTROL 0x1fdc 10442 #define mmDP_AUX5_AUX_CONTROL_BASE_IDX 2 10443 #define mmDP_AUX5_AUX_SW_CONTROL 0x1fdd 10444 #define mmDP_AUX5_AUX_SW_CONTROL_BASE_IDX 2 10445 #define mmDP_AUX5_AUX_ARB_CONTROL 0x1fde 10446 #define mmDP_AUX5_AUX_ARB_CONTROL_BASE_IDX 2 10447 #define mmDP_AUX5_AUX_INTERRUPT_CONTROL 0x1fdf 10448 #define mmDP_AUX5_AUX_INTERRUPT_CONTROL_BASE_IDX 2 10449 #define mmDP_AUX5_AUX_SW_STATUS 0x1fe0 10450 #define mmDP_AUX5_AUX_SW_STATUS_BASE_IDX 2 10451 #define mmDP_AUX5_AUX_LS_STATUS 0x1fe1 10452 #define mmDP_AUX5_AUX_LS_STATUS_BASE_IDX 2 10453 #define mmDP_AUX5_AUX_SW_DATA 0x1fe2 10454 #define mmDP_AUX5_AUX_SW_DATA_BASE_IDX 2 10455 #define mmDP_AUX5_AUX_LS_DATA 0x1fe3 10456 #define mmDP_AUX5_AUX_LS_DATA_BASE_IDX 2 10457 #define mmDP_AUX5_AUX_DPHY_TX_REF_CONTROL 0x1fe4 10458 #define mmDP_AUX5_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 10459 #define mmDP_AUX5_AUX_DPHY_TX_CONTROL 0x1fe5 10460 #define mmDP_AUX5_AUX_DPHY_TX_CONTROL_BASE_IDX 2 10461 #define mmDP_AUX5_AUX_DPHY_RX_CONTROL0 0x1fe6 10462 #define mmDP_AUX5_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 10463 #define mmDP_AUX5_AUX_DPHY_RX_CONTROL1 0x1fe7 10464 #define mmDP_AUX5_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 10465 #define mmDP_AUX5_AUX_DPHY_TX_STATUS 0x1fe8 10466 #define mmDP_AUX5_AUX_DPHY_TX_STATUS_BASE_IDX 2 10467 #define mmDP_AUX5_AUX_DPHY_RX_STATUS 0x1fe9 10468 #define mmDP_AUX5_AUX_DPHY_RX_STATUS_BASE_IDX 2 10469 #define mmDP_AUX5_AUX_GTC_SYNC_CONTROL 0x1fea 10470 #define mmDP_AUX5_AUX_GTC_SYNC_CONTROL_BASE_IDX 2 10471 #define mmDP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL 0x1feb 10472 #define mmDP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 10473 #define mmDP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1fec 10474 #define mmDP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 10475 #define mmDP_AUX5_AUX_GTC_SYNC_STATUS 0x1fed 10476 #define mmDP_AUX5_AUX_GTC_SYNC_STATUS_BASE_IDX 2 10477 #define mmDP_AUX5_AUX_PHY_WAKE_CNTL 0x1ff2 10478 #define mmDP_AUX5_AUX_PHY_WAKE_CNTL_BASE_IDX 2 10479 10480 10481 // addressBlock: dce_dc_dio_dig0_vpg_vpg_dispdec 10482 // base address: 0x154a0 10483 #define mmVPG0_VPG_GENERIC_PACKET_ACCESS_CTRL 0x2068 10484 #define mmVPG0_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 10485 #define mmVPG0_VPG_GENERIC_PACKET_DATA 0x2069 10486 #define mmVPG0_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 10487 #define mmVPG0_VPG_GSP_FRAME_UPDATE_CTRL 0x206a 10488 #define mmVPG0_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 10489 #define mmVPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x206b 10490 #define mmVPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 10491 #define mmVPG0_VPG_GENERIC_STATUS 0x206c 10492 #define mmVPG0_VPG_GENERIC_STATUS_BASE_IDX 2 10493 #define mmVPG0_VPG_MEM_PWR 0x206d 10494 #define mmVPG0_VPG_MEM_PWR_BASE_IDX 2 10495 #define mmVPG0_VPG_ISRC1_2_ACCESS_CTRL 0x206e 10496 #define mmVPG0_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 10497 #define mmVPG0_VPG_ISRC1_2_DATA 0x206f 10498 #define mmVPG0_VPG_ISRC1_2_DATA_BASE_IDX 2 10499 #define mmVPG0_VPG_MPEG_INFO0 0x2070 10500 #define mmVPG0_VPG_MPEG_INFO0_BASE_IDX 2 10501 #define mmVPG0_VPG_MPEG_INFO1 0x2071 10502 #define mmVPG0_VPG_MPEG_INFO1_BASE_IDX 2 10503 10504 10505 // addressBlock: dce_dc_dio_dig0_afmt_afmt_dispdec 10506 // base address: 0x154cc 10507 #define mmAFMT0_AFMT_VBI_PACKET_CONTROL 0x2074 10508 #define mmAFMT0_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 10509 #define mmAFMT0_AFMT_AUDIO_PACKET_CONTROL2 0x2075 10510 #define mmAFMT0_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 10511 #define mmAFMT0_AFMT_AUDIO_INFO0 0x2076 10512 #define mmAFMT0_AFMT_AUDIO_INFO0_BASE_IDX 2 10513 #define mmAFMT0_AFMT_AUDIO_INFO1 0x2077 10514 #define mmAFMT0_AFMT_AUDIO_INFO1_BASE_IDX 2 10515 #define mmAFMT0_AFMT_60958_0 0x2078 10516 #define mmAFMT0_AFMT_60958_0_BASE_IDX 2 10517 #define mmAFMT0_AFMT_60958_1 0x2079 10518 #define mmAFMT0_AFMT_60958_1_BASE_IDX 2 10519 #define mmAFMT0_AFMT_AUDIO_CRC_CONTROL 0x207a 10520 #define mmAFMT0_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 10521 #define mmAFMT0_AFMT_RAMP_CONTROL0 0x207b 10522 #define mmAFMT0_AFMT_RAMP_CONTROL0_BASE_IDX 2 10523 #define mmAFMT0_AFMT_RAMP_CONTROL1 0x207c 10524 #define mmAFMT0_AFMT_RAMP_CONTROL1_BASE_IDX 2 10525 #define mmAFMT0_AFMT_RAMP_CONTROL2 0x207d 10526 #define mmAFMT0_AFMT_RAMP_CONTROL2_BASE_IDX 2 10527 #define mmAFMT0_AFMT_RAMP_CONTROL3 0x207e 10528 #define mmAFMT0_AFMT_RAMP_CONTROL3_BASE_IDX 2 10529 #define mmAFMT0_AFMT_60958_2 0x207f 10530 #define mmAFMT0_AFMT_60958_2_BASE_IDX 2 10531 #define mmAFMT0_AFMT_AUDIO_CRC_RESULT 0x2080 10532 #define mmAFMT0_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 10533 #define mmAFMT0_AFMT_STATUS 0x2081 10534 #define mmAFMT0_AFMT_STATUS_BASE_IDX 2 10535 #define mmAFMT0_AFMT_AUDIO_PACKET_CONTROL 0x2082 10536 #define mmAFMT0_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 10537 #define mmAFMT0_AFMT_INFOFRAME_CONTROL0 0x2083 10538 #define mmAFMT0_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 10539 #define mmAFMT0_AFMT_INTERRUPT_STATUS 0x2084 10540 #define mmAFMT0_AFMT_INTERRUPT_STATUS_BASE_IDX 2 10541 #define mmAFMT0_AFMT_AUDIO_SRC_CONTROL 0x2085 10542 #define mmAFMT0_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 10543 #define mmAFMT0_AFMT_MEM_PWR 0x2087 10544 #define mmAFMT0_AFMT_MEM_PWR_BASE_IDX 2 10545 10546 10547 // addressBlock: dce_dc_dio_dig0_dme_dme_dispdec 10548 // base address: 0x15524 10549 #define mmDME0_DME_CONTROL 0x2089 10550 #define mmDME0_DME_CONTROL_BASE_IDX 2 10551 #define mmDME0_DME_MEMORY_CONTROL 0x208a 10552 #define mmDME0_DME_MEMORY_CONTROL_BASE_IDX 2 10553 10554 10555 // addressBlock: dce_dc_dio_dig0_dispdec 10556 // base address: 0x0 10557 #define mmDIG0_DIG_FE_CNTL 0x208b 10558 #define mmDIG0_DIG_FE_CNTL_BASE_IDX 2 10559 #define mmDIG0_DIG_OUTPUT_CRC_CNTL 0x208c 10560 #define mmDIG0_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 10561 #define mmDIG0_DIG_OUTPUT_CRC_RESULT 0x208d 10562 #define mmDIG0_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 10563 #define mmDIG0_DIG_CLOCK_PATTERN 0x208e 10564 #define mmDIG0_DIG_CLOCK_PATTERN_BASE_IDX 2 10565 #define mmDIG0_DIG_TEST_PATTERN 0x208f 10566 #define mmDIG0_DIG_TEST_PATTERN_BASE_IDX 2 10567 #define mmDIG0_DIG_RANDOM_PATTERN_SEED 0x2090 10568 #define mmDIG0_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 10569 #define mmDIG0_DIG_FIFO_STATUS 0x2091 10570 #define mmDIG0_DIG_FIFO_STATUS_BASE_IDX 2 10571 #define mmDIG0_HDMI_METADATA_PACKET_CONTROL 0x2092 10572 #define mmDIG0_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2 10573 #define mmDIG0_HDMI_CONTROL 0x2093 10574 #define mmDIG0_HDMI_CONTROL_BASE_IDX 2 10575 #define mmDIG0_HDMI_STATUS 0x2094 10576 #define mmDIG0_HDMI_STATUS_BASE_IDX 2 10577 #define mmDIG0_HDMI_AUDIO_PACKET_CONTROL 0x2095 10578 #define mmDIG0_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 10579 #define mmDIG0_HDMI_ACR_PACKET_CONTROL 0x2096 10580 #define mmDIG0_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 10581 #define mmDIG0_HDMI_VBI_PACKET_CONTROL 0x2097 10582 #define mmDIG0_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 10583 #define mmDIG0_HDMI_INFOFRAME_CONTROL0 0x2098 10584 #define mmDIG0_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 10585 #define mmDIG0_HDMI_INFOFRAME_CONTROL1 0x2099 10586 #define mmDIG0_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 10587 #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL0 0x209a 10588 #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 10589 #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL6 0x209b 10590 #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX 2 10591 #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL5 0x209c 10592 #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2 10593 #define mmDIG0_HDMI_GC 0x209d 10594 #define mmDIG0_HDMI_GC_BASE_IDX 2 10595 #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL1 0x209e 10596 #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 10597 #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL2 0x209f 10598 #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 10599 #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL3 0x20a0 10600 #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 10601 #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL4 0x20a1 10602 #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2 10603 #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL7 0x20a2 10604 #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX 2 10605 #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL8 0x20a3 10606 #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX 2 10607 #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL9 0x20a4 10608 #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX 2 10609 #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL10 0x20a5 10610 #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX 2 10611 #define mmDIG0_HDMI_DB_CONTROL 0x20a6 10612 #define mmDIG0_HDMI_DB_CONTROL_BASE_IDX 2 10613 #define mmDIG0_HDMI_ACR_32_0 0x20a7 10614 #define mmDIG0_HDMI_ACR_32_0_BASE_IDX 2 10615 #define mmDIG0_HDMI_ACR_32_1 0x20a8 10616 #define mmDIG0_HDMI_ACR_32_1_BASE_IDX 2 10617 #define mmDIG0_HDMI_ACR_44_0 0x20a9 10618 #define mmDIG0_HDMI_ACR_44_0_BASE_IDX 2 10619 #define mmDIG0_HDMI_ACR_44_1 0x20aa 10620 #define mmDIG0_HDMI_ACR_44_1_BASE_IDX 2 10621 #define mmDIG0_HDMI_ACR_48_0 0x20ab 10622 #define mmDIG0_HDMI_ACR_48_0_BASE_IDX 2 10623 #define mmDIG0_HDMI_ACR_48_1 0x20ac 10624 #define mmDIG0_HDMI_ACR_48_1_BASE_IDX 2 10625 #define mmDIG0_HDMI_ACR_STATUS_0 0x20ad 10626 #define mmDIG0_HDMI_ACR_STATUS_0_BASE_IDX 2 10627 #define mmDIG0_HDMI_ACR_STATUS_1 0x20ae 10628 #define mmDIG0_HDMI_ACR_STATUS_1_BASE_IDX 2 10629 #define mmDIG0_AFMT_CNTL 0x20af 10630 #define mmDIG0_AFMT_CNTL_BASE_IDX 2 10631 #define mmDIG0_DIG_BE_CNTL 0x20b0 10632 #define mmDIG0_DIG_BE_CNTL_BASE_IDX 2 10633 #define mmDIG0_DIG_BE_EN_CNTL 0x20b1 10634 #define mmDIG0_DIG_BE_EN_CNTL_BASE_IDX 2 10635 #define mmDIG0_TMDS_CNTL 0x20d7 10636 #define mmDIG0_TMDS_CNTL_BASE_IDX 2 10637 #define mmDIG0_TMDS_CONTROL_CHAR 0x20d8 10638 #define mmDIG0_TMDS_CONTROL_CHAR_BASE_IDX 2 10639 #define mmDIG0_TMDS_CONTROL0_FEEDBACK 0x20d9 10640 #define mmDIG0_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 10641 #define mmDIG0_TMDS_STEREOSYNC_CTL_SEL 0x20da 10642 #define mmDIG0_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 10643 #define mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1 0x20db 10644 #define mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 10645 #define mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3 0x20dc 10646 #define mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 10647 #define mmDIG0_TMDS_CTL_BITS 0x20de 10648 #define mmDIG0_TMDS_CTL_BITS_BASE_IDX 2 10649 #define mmDIG0_TMDS_DCBALANCER_CONTROL 0x20df 10650 #define mmDIG0_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 10651 #define mmDIG0_TMDS_SYNC_DCBALANCE_CHAR 0x20e0 10652 #define mmDIG0_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2 10653 #define mmDIG0_TMDS_CTL0_1_GEN_CNTL 0x20e1 10654 #define mmDIG0_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 10655 #define mmDIG0_TMDS_CTL2_3_GEN_CNTL 0x20e2 10656 #define mmDIG0_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 10657 #define mmDIG0_DIG_VERSION 0x20e4 10658 #define mmDIG0_DIG_VERSION_BASE_IDX 2 10659 #define mmDIG0_DIG_LANE_ENABLE 0x20e5 10660 #define mmDIG0_DIG_LANE_ENABLE_BASE_IDX 2 10661 #define mmDIG0_FORCE_DIG_DISABLE 0x20e6 10662 #define mmDIG0_FORCE_DIG_DISABLE_BASE_IDX 2 10663 10664 // addressBlock: dce_dc_dio_dp0_dispdec 10665 // base address: 0x0 10666 #define mmDP0_DP_LINK_CNTL 0x2108 10667 #define mmDP0_DP_LINK_CNTL_BASE_IDX 2 10668 #define mmDP0_DP_PIXEL_FORMAT 0x2109 10669 #define mmDP0_DP_PIXEL_FORMAT_BASE_IDX 2 10670 #define mmDP0_DP_MSA_COLORIMETRY 0x210a 10671 #define mmDP0_DP_MSA_COLORIMETRY_BASE_IDX 2 10672 #define mmDP0_DP_CONFIG 0x210b 10673 #define mmDP0_DP_CONFIG_BASE_IDX 2 10674 #define mmDP0_DP_VID_STREAM_CNTL 0x210c 10675 #define mmDP0_DP_VID_STREAM_CNTL_BASE_IDX 2 10676 #define mmDP0_DP_STEER_FIFO 0x210d 10677 #define mmDP0_DP_STEER_FIFO_BASE_IDX 2 10678 #define mmDP0_DP_MSA_MISC 0x210e 10679 #define mmDP0_DP_MSA_MISC_BASE_IDX 2 10680 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x210f 10681 #define mmDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 10682 #define mmDP0_DP_VID_TIMING 0x2110 10683 #define mmDP0_DP_VID_TIMING_BASE_IDX 2 10684 #define mmDP0_DP_VID_N 0x2111 10685 #define mmDP0_DP_VID_N_BASE_IDX 2 10686 #define mmDP0_DP_VID_M 0x2112 10687 #define mmDP0_DP_VID_M_BASE_IDX 2 10688 #define mmDP0_DP_LINK_FRAMING_CNTL 0x2113 10689 #define mmDP0_DP_LINK_FRAMING_CNTL_BASE_IDX 2 10690 #define mmDP0_DP_HBR2_EYE_PATTERN 0x2114 10691 #define mmDP0_DP_HBR2_EYE_PATTERN_BASE_IDX 2 10692 #define mmDP0_DP_VID_MSA_VBID 0x2115 10693 #define mmDP0_DP_VID_MSA_VBID_BASE_IDX 2 10694 #define mmDP0_DP_VID_INTERRUPT_CNTL 0x2116 10695 #define mmDP0_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 10696 #define mmDP0_DP_DPHY_CNTL 0x2117 10697 #define mmDP0_DP_DPHY_CNTL_BASE_IDX 2 10698 #define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL 0x2118 10699 #define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 10700 #define mmDP0_DP_DPHY_SYM0 0x2119 10701 #define mmDP0_DP_DPHY_SYM0_BASE_IDX 2 10702 #define mmDP0_DP_DPHY_SYM1 0x211a 10703 #define mmDP0_DP_DPHY_SYM1_BASE_IDX 2 10704 #define mmDP0_DP_DPHY_SYM2 0x211b 10705 #define mmDP0_DP_DPHY_SYM2_BASE_IDX 2 10706 #define mmDP0_DP_DPHY_8B10B_CNTL 0x211c 10707 #define mmDP0_DP_DPHY_8B10B_CNTL_BASE_IDX 2 10708 #define mmDP0_DP_DPHY_PRBS_CNTL 0x211d 10709 #define mmDP0_DP_DPHY_PRBS_CNTL_BASE_IDX 2 10710 #define mmDP0_DP_DPHY_SCRAM_CNTL 0x211e 10711 #define mmDP0_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 10712 #define mmDP0_DP_DPHY_CRC_EN 0x211f 10713 #define mmDP0_DP_DPHY_CRC_EN_BASE_IDX 2 10714 #define mmDP0_DP_DPHY_CRC_CNTL 0x2120 10715 #define mmDP0_DP_DPHY_CRC_CNTL_BASE_IDX 2 10716 #define mmDP0_DP_DPHY_CRC_RESULT 0x2121 10717 #define mmDP0_DP_DPHY_CRC_RESULT_BASE_IDX 2 10718 #define mmDP0_DP_DPHY_CRC_MST_CNTL 0x2122 10719 #define mmDP0_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 10720 #define mmDP0_DP_DPHY_CRC_MST_STATUS 0x2123 10721 #define mmDP0_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 10722 #define mmDP0_DP_DPHY_FAST_TRAINING 0x2124 10723 #define mmDP0_DP_DPHY_FAST_TRAINING_BASE_IDX 2 10724 #define mmDP0_DP_DPHY_FAST_TRAINING_STATUS 0x2125 10725 #define mmDP0_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 10726 #define mmDP0_DP_SEC_CNTL 0x212b 10727 #define mmDP0_DP_SEC_CNTL_BASE_IDX 2 10728 #define mmDP0_DP_SEC_CNTL1 0x212c 10729 #define mmDP0_DP_SEC_CNTL1_BASE_IDX 2 10730 #define mmDP0_DP_SEC_FRAMING1 0x212d 10731 #define mmDP0_DP_SEC_FRAMING1_BASE_IDX 2 10732 #define mmDP0_DP_SEC_FRAMING2 0x212e 10733 #define mmDP0_DP_SEC_FRAMING2_BASE_IDX 2 10734 #define mmDP0_DP_SEC_FRAMING3 0x212f 10735 #define mmDP0_DP_SEC_FRAMING3_BASE_IDX 2 10736 #define mmDP0_DP_SEC_FRAMING4 0x2130 10737 #define mmDP0_DP_SEC_FRAMING4_BASE_IDX 2 10738 #define mmDP0_DP_SEC_AUD_N 0x2131 10739 #define mmDP0_DP_SEC_AUD_N_BASE_IDX 2 10740 #define mmDP0_DP_SEC_AUD_N_READBACK 0x2132 10741 #define mmDP0_DP_SEC_AUD_N_READBACK_BASE_IDX 2 10742 #define mmDP0_DP_SEC_AUD_M 0x2133 10743 #define mmDP0_DP_SEC_AUD_M_BASE_IDX 2 10744 #define mmDP0_DP_SEC_AUD_M_READBACK 0x2134 10745 #define mmDP0_DP_SEC_AUD_M_READBACK_BASE_IDX 2 10746 #define mmDP0_DP_SEC_TIMESTAMP 0x2135 10747 #define mmDP0_DP_SEC_TIMESTAMP_BASE_IDX 2 10748 #define mmDP0_DP_SEC_PACKET_CNTL 0x2136 10749 #define mmDP0_DP_SEC_PACKET_CNTL_BASE_IDX 2 10750 #define mmDP0_DP_MSE_RATE_CNTL 0x2137 10751 #define mmDP0_DP_MSE_RATE_CNTL_BASE_IDX 2 10752 #define mmDP0_DP_MSE_RATE_UPDATE 0x2139 10753 #define mmDP0_DP_MSE_RATE_UPDATE_BASE_IDX 2 10754 #define mmDP0_DP_MSE_SAT0 0x213a 10755 #define mmDP0_DP_MSE_SAT0_BASE_IDX 2 10756 #define mmDP0_DP_MSE_SAT1 0x213b 10757 #define mmDP0_DP_MSE_SAT1_BASE_IDX 2 10758 #define mmDP0_DP_MSE_SAT2 0x213c 10759 #define mmDP0_DP_MSE_SAT2_BASE_IDX 2 10760 #define mmDP0_DP_MSE_SAT_UPDATE 0x213d 10761 #define mmDP0_DP_MSE_SAT_UPDATE_BASE_IDX 2 10762 #define mmDP0_DP_MSE_LINK_TIMING 0x213e 10763 #define mmDP0_DP_MSE_LINK_TIMING_BASE_IDX 2 10764 #define mmDP0_DP_MSE_MISC_CNTL 0x213f 10765 #define mmDP0_DP_MSE_MISC_CNTL_BASE_IDX 2 10766 #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x2144 10767 #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 10768 #define mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL 0x2145 10769 #define mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 10770 #define mmDP0_DP_MSE_SAT0_STATUS 0x2147 10771 #define mmDP0_DP_MSE_SAT0_STATUS_BASE_IDX 2 10772 #define mmDP0_DP_MSE_SAT1_STATUS 0x2148 10773 #define mmDP0_DP_MSE_SAT1_STATUS_BASE_IDX 2 10774 #define mmDP0_DP_MSE_SAT2_STATUS 0x2149 10775 #define mmDP0_DP_MSE_SAT2_STATUS_BASE_IDX 2 10776 #define mmDP0_DP_MSA_TIMING_PARAM1 0x214c 10777 #define mmDP0_DP_MSA_TIMING_PARAM1_BASE_IDX 2 10778 #define mmDP0_DP_MSA_TIMING_PARAM2 0x214d 10779 #define mmDP0_DP_MSA_TIMING_PARAM2_BASE_IDX 2 10780 #define mmDP0_DP_MSA_TIMING_PARAM3 0x214e 10781 #define mmDP0_DP_MSA_TIMING_PARAM3_BASE_IDX 2 10782 #define mmDP0_DP_MSA_TIMING_PARAM4 0x214f 10783 #define mmDP0_DP_MSA_TIMING_PARAM4_BASE_IDX 2 10784 #define mmDP0_DP_MSO_CNTL 0x2150 10785 #define mmDP0_DP_MSO_CNTL_BASE_IDX 2 10786 #define mmDP0_DP_MSO_CNTL1 0x2151 10787 #define mmDP0_DP_MSO_CNTL1_BASE_IDX 2 10788 #define mmDP0_DP_DSC_CNTL 0x2152 10789 #define mmDP0_DP_DSC_CNTL_BASE_IDX 2 10790 #define mmDP0_DP_SEC_CNTL2 0x2153 10791 #define mmDP0_DP_SEC_CNTL2_BASE_IDX 2 10792 #define mmDP0_DP_SEC_CNTL3 0x2154 10793 #define mmDP0_DP_SEC_CNTL3_BASE_IDX 2 10794 #define mmDP0_DP_SEC_CNTL4 0x2155 10795 #define mmDP0_DP_SEC_CNTL4_BASE_IDX 2 10796 #define mmDP0_DP_SEC_CNTL5 0x2156 10797 #define mmDP0_DP_SEC_CNTL5_BASE_IDX 2 10798 #define mmDP0_DP_SEC_CNTL6 0x2157 10799 #define mmDP0_DP_SEC_CNTL6_BASE_IDX 2 10800 #define mmDP0_DP_SEC_CNTL7 0x2158 10801 #define mmDP0_DP_SEC_CNTL7_BASE_IDX 2 10802 #define mmDP0_DP_DB_CNTL 0x2159 10803 #define mmDP0_DP_DB_CNTL_BASE_IDX 2 10804 #define mmDP0_DP_MSA_VBID_MISC 0x215a 10805 #define mmDP0_DP_MSA_VBID_MISC_BASE_IDX 2 10806 #define mmDP0_DP_SEC_METADATA_TRANSMISSION 0x215b 10807 #define mmDP0_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2 10808 #define mmDP0_DP_DSC_BYTES_PER_PIXEL 0x215c 10809 #define mmDP0_DP_DSC_BYTES_PER_PIXEL_BASE_IDX 2 10810 #define mmDP0_DP_ALPM_CNTL 0x215d 10811 #define mmDP0_DP_ALPM_CNTL_BASE_IDX 2 10812 #define mmDP0_DP_GSP8_CNTL 0x215e 10813 #define mmDP0_DP_GSP8_CNTL_BASE_IDX 2 10814 #define mmDP0_DP_GSP9_CNTL 0x215f 10815 #define mmDP0_DP_GSP9_CNTL_BASE_IDX 2 10816 #define mmDP0_DP_GSP10_CNTL 0x2160 10817 #define mmDP0_DP_GSP10_CNTL_BASE_IDX 2 10818 #define mmDP0_DP_GSP11_CNTL 0x2161 10819 #define mmDP0_DP_GSP11_CNTL_BASE_IDX 2 10820 #define mmDP0_DP_GSP_EN_DB_STATUS 0x2162 10821 #define mmDP0_DP_GSP_EN_DB_STATUS_BASE_IDX 2 10822 10823 10824 // addressBlock: dce_dc_dio_dig1_vpg_vpg_dispdec 10825 // base address: 0x158a0 10826 #define mmVPG1_VPG_GENERIC_PACKET_ACCESS_CTRL 0x2168 10827 #define mmVPG1_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 10828 #define mmVPG1_VPG_GENERIC_PACKET_DATA 0x2169 10829 #define mmVPG1_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 10830 #define mmVPG1_VPG_GSP_FRAME_UPDATE_CTRL 0x216a 10831 #define mmVPG1_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 10832 #define mmVPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x216b 10833 #define mmVPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 10834 #define mmVPG1_VPG_GENERIC_STATUS 0x216c 10835 #define mmVPG1_VPG_GENERIC_STATUS_BASE_IDX 2 10836 #define mmVPG1_VPG_MEM_PWR 0x216d 10837 #define mmVPG1_VPG_MEM_PWR_BASE_IDX 2 10838 #define mmVPG1_VPG_ISRC1_2_ACCESS_CTRL 0x216e 10839 #define mmVPG1_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 10840 #define mmVPG1_VPG_ISRC1_2_DATA 0x216f 10841 #define mmVPG1_VPG_ISRC1_2_DATA_BASE_IDX 2 10842 #define mmVPG1_VPG_MPEG_INFO0 0x2170 10843 #define mmVPG1_VPG_MPEG_INFO0_BASE_IDX 2 10844 #define mmVPG1_VPG_MPEG_INFO1 0x2171 10845 #define mmVPG1_VPG_MPEG_INFO1_BASE_IDX 2 10846 10847 10848 // addressBlock: dce_dc_dio_dig1_afmt_afmt_dispdec 10849 // base address: 0x158cc 10850 #define mmAFMT1_AFMT_VBI_PACKET_CONTROL 0x2174 10851 #define mmAFMT1_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 10852 #define mmAFMT1_AFMT_AUDIO_PACKET_CONTROL2 0x2175 10853 #define mmAFMT1_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 10854 #define mmAFMT1_AFMT_AUDIO_INFO0 0x2176 10855 #define mmAFMT1_AFMT_AUDIO_INFO0_BASE_IDX 2 10856 #define mmAFMT1_AFMT_AUDIO_INFO1 0x2177 10857 #define mmAFMT1_AFMT_AUDIO_INFO1_BASE_IDX 2 10858 #define mmAFMT1_AFMT_60958_0 0x2178 10859 #define mmAFMT1_AFMT_60958_0_BASE_IDX 2 10860 #define mmAFMT1_AFMT_60958_1 0x2179 10861 #define mmAFMT1_AFMT_60958_1_BASE_IDX 2 10862 #define mmAFMT1_AFMT_AUDIO_CRC_CONTROL 0x217a 10863 #define mmAFMT1_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 10864 #define mmAFMT1_AFMT_RAMP_CONTROL0 0x217b 10865 #define mmAFMT1_AFMT_RAMP_CONTROL0_BASE_IDX 2 10866 #define mmAFMT1_AFMT_RAMP_CONTROL1 0x217c 10867 #define mmAFMT1_AFMT_RAMP_CONTROL1_BASE_IDX 2 10868 #define mmAFMT1_AFMT_RAMP_CONTROL2 0x217d 10869 #define mmAFMT1_AFMT_RAMP_CONTROL2_BASE_IDX 2 10870 #define mmAFMT1_AFMT_RAMP_CONTROL3 0x217e 10871 #define mmAFMT1_AFMT_RAMP_CONTROL3_BASE_IDX 2 10872 #define mmAFMT1_AFMT_60958_2 0x217f 10873 #define mmAFMT1_AFMT_60958_2_BASE_IDX 2 10874 #define mmAFMT1_AFMT_AUDIO_CRC_RESULT 0x2180 10875 #define mmAFMT1_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 10876 #define mmAFMT1_AFMT_STATUS 0x2181 10877 #define mmAFMT1_AFMT_STATUS_BASE_IDX 2 10878 #define mmAFMT1_AFMT_AUDIO_PACKET_CONTROL 0x2182 10879 #define mmAFMT1_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 10880 #define mmAFMT1_AFMT_INFOFRAME_CONTROL0 0x2183 10881 #define mmAFMT1_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 10882 #define mmAFMT1_AFMT_INTERRUPT_STATUS 0x2184 10883 #define mmAFMT1_AFMT_INTERRUPT_STATUS_BASE_IDX 2 10884 #define mmAFMT1_AFMT_AUDIO_SRC_CONTROL 0x2185 10885 #define mmAFMT1_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 10886 #define mmAFMT1_AFMT_MEM_PWR 0x2187 10887 #define mmAFMT1_AFMT_MEM_PWR_BASE_IDX 2 10888 10889 10890 // addressBlock: dce_dc_dio_dig1_dme_dme_dispdec 10891 // base address: 0x15924 10892 #define mmDME1_DME_CONTROL 0x2189 10893 #define mmDME1_DME_CONTROL_BASE_IDX 2 10894 #define mmDME1_DME_MEMORY_CONTROL 0x218a 10895 #define mmDME1_DME_MEMORY_CONTROL_BASE_IDX 2 10896 10897 10898 // addressBlock: dce_dc_dio_dig1_dispdec 10899 // base address: 0x400 10900 #define mmDIG1_DIG_FE_CNTL 0x218b 10901 #define mmDIG1_DIG_FE_CNTL_BASE_IDX 2 10902 #define mmDIG1_DIG_OUTPUT_CRC_CNTL 0x218c 10903 #define mmDIG1_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 10904 #define mmDIG1_DIG_OUTPUT_CRC_RESULT 0x218d 10905 #define mmDIG1_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 10906 #define mmDIG1_DIG_CLOCK_PATTERN 0x218e 10907 #define mmDIG1_DIG_CLOCK_PATTERN_BASE_IDX 2 10908 #define mmDIG1_DIG_TEST_PATTERN 0x218f 10909 #define mmDIG1_DIG_TEST_PATTERN_BASE_IDX 2 10910 #define mmDIG1_DIG_RANDOM_PATTERN_SEED 0x2190 10911 #define mmDIG1_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 10912 #define mmDIG1_DIG_FIFO_STATUS 0x2191 10913 #define mmDIG1_DIG_FIFO_STATUS_BASE_IDX 2 10914 #define mmDIG1_HDMI_METADATA_PACKET_CONTROL 0x2192 10915 #define mmDIG1_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2 10916 #define mmDIG1_HDMI_CONTROL 0x2193 10917 #define mmDIG1_HDMI_CONTROL_BASE_IDX 2 10918 #define mmDIG1_HDMI_STATUS 0x2194 10919 #define mmDIG1_HDMI_STATUS_BASE_IDX 2 10920 #define mmDIG1_HDMI_AUDIO_PACKET_CONTROL 0x2195 10921 #define mmDIG1_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 10922 #define mmDIG1_HDMI_ACR_PACKET_CONTROL 0x2196 10923 #define mmDIG1_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 10924 #define mmDIG1_HDMI_VBI_PACKET_CONTROL 0x2197 10925 #define mmDIG1_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 10926 #define mmDIG1_HDMI_INFOFRAME_CONTROL0 0x2198 10927 #define mmDIG1_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 10928 #define mmDIG1_HDMI_INFOFRAME_CONTROL1 0x2199 10929 #define mmDIG1_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 10930 #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL0 0x219a 10931 #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 10932 #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL6 0x219b 10933 #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX 2 10934 #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL5 0x219c 10935 #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2 10936 #define mmDIG1_HDMI_GC 0x219d 10937 #define mmDIG1_HDMI_GC_BASE_IDX 2 10938 #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL1 0x219e 10939 #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 10940 #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL2 0x219f 10941 #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 10942 #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL3 0x21a0 10943 #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 10944 #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL4 0x21a1 10945 #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2 10946 #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL7 0x21a2 10947 #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX 2 10948 #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL8 0x21a3 10949 #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX 2 10950 #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL9 0x21a4 10951 #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX 2 10952 #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL10 0x21a5 10953 #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX 2 10954 #define mmDIG1_HDMI_DB_CONTROL 0x21a6 10955 #define mmDIG1_HDMI_DB_CONTROL_BASE_IDX 2 10956 #define mmDIG1_HDMI_ACR_32_0 0x21a7 10957 #define mmDIG1_HDMI_ACR_32_0_BASE_IDX 2 10958 #define mmDIG1_HDMI_ACR_32_1 0x21a8 10959 #define mmDIG1_HDMI_ACR_32_1_BASE_IDX 2 10960 #define mmDIG1_HDMI_ACR_44_0 0x21a9 10961 #define mmDIG1_HDMI_ACR_44_0_BASE_IDX 2 10962 #define mmDIG1_HDMI_ACR_44_1 0x21aa 10963 #define mmDIG1_HDMI_ACR_44_1_BASE_IDX 2 10964 #define mmDIG1_HDMI_ACR_48_0 0x21ab 10965 #define mmDIG1_HDMI_ACR_48_0_BASE_IDX 2 10966 #define mmDIG1_HDMI_ACR_48_1 0x21ac 10967 #define mmDIG1_HDMI_ACR_48_1_BASE_IDX 2 10968 #define mmDIG1_HDMI_ACR_STATUS_0 0x21ad 10969 #define mmDIG1_HDMI_ACR_STATUS_0_BASE_IDX 2 10970 #define mmDIG1_HDMI_ACR_STATUS_1 0x21ae 10971 #define mmDIG1_HDMI_ACR_STATUS_1_BASE_IDX 2 10972 #define mmDIG1_AFMT_CNTL 0x21af 10973 #define mmDIG1_AFMT_CNTL_BASE_IDX 2 10974 #define mmDIG1_DIG_BE_CNTL 0x21b0 10975 #define mmDIG1_DIG_BE_CNTL_BASE_IDX 2 10976 #define mmDIG1_DIG_BE_EN_CNTL 0x21b1 10977 #define mmDIG1_DIG_BE_EN_CNTL_BASE_IDX 2 10978 #define mmDIG1_TMDS_CNTL 0x21d7 10979 #define mmDIG1_TMDS_CNTL_BASE_IDX 2 10980 #define mmDIG1_TMDS_CONTROL_CHAR 0x21d8 10981 #define mmDIG1_TMDS_CONTROL_CHAR_BASE_IDX 2 10982 #define mmDIG1_TMDS_CONTROL0_FEEDBACK 0x21d9 10983 #define mmDIG1_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 10984 #define mmDIG1_TMDS_STEREOSYNC_CTL_SEL 0x21da 10985 #define mmDIG1_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 10986 #define mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1 0x21db 10987 #define mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 10988 #define mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3 0x21dc 10989 #define mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 10990 #define mmDIG1_TMDS_CTL_BITS 0x21de 10991 #define mmDIG1_TMDS_CTL_BITS_BASE_IDX 2 10992 #define mmDIG1_TMDS_DCBALANCER_CONTROL 0x21df 10993 #define mmDIG1_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 10994 #define mmDIG1_TMDS_SYNC_DCBALANCE_CHAR 0x21e0 10995 #define mmDIG1_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2 10996 #define mmDIG1_TMDS_CTL0_1_GEN_CNTL 0x21e1 10997 #define mmDIG1_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 10998 #define mmDIG1_TMDS_CTL2_3_GEN_CNTL 0x21e2 10999 #define mmDIG1_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 11000 #define mmDIG1_DIG_VERSION 0x21e4 11001 #define mmDIG1_DIG_VERSION_BASE_IDX 2 11002 #define mmDIG1_DIG_LANE_ENABLE 0x21e5 11003 #define mmDIG1_DIG_LANE_ENABLE_BASE_IDX 2 11004 #define mmDIG1_FORCE_DIG_DISABLE 0x21e6 11005 #define mmDIG1_FORCE_DIG_DISABLE_BASE_IDX 2 11006 11007 // addressBlock: dce_dc_dio_dp1_dispdec 11008 // base address: 0x400 11009 #define mmDP1_DP_LINK_CNTL 0x2208 11010 #define mmDP1_DP_LINK_CNTL_BASE_IDX 2 11011 #define mmDP1_DP_PIXEL_FORMAT 0x2209 11012 #define mmDP1_DP_PIXEL_FORMAT_BASE_IDX 2 11013 #define mmDP1_DP_MSA_COLORIMETRY 0x220a 11014 #define mmDP1_DP_MSA_COLORIMETRY_BASE_IDX 2 11015 #define mmDP1_DP_CONFIG 0x220b 11016 #define mmDP1_DP_CONFIG_BASE_IDX 2 11017 #define mmDP1_DP_VID_STREAM_CNTL 0x220c 11018 #define mmDP1_DP_VID_STREAM_CNTL_BASE_IDX 2 11019 #define mmDP1_DP_STEER_FIFO 0x220d 11020 #define mmDP1_DP_STEER_FIFO_BASE_IDX 2 11021 #define mmDP1_DP_MSA_MISC 0x220e 11022 #define mmDP1_DP_MSA_MISC_BASE_IDX 2 11023 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x220f 11024 #define mmDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 11025 #define mmDP1_DP_VID_TIMING 0x2210 11026 #define mmDP1_DP_VID_TIMING_BASE_IDX 2 11027 #define mmDP1_DP_VID_N 0x2211 11028 #define mmDP1_DP_VID_N_BASE_IDX 2 11029 #define mmDP1_DP_VID_M 0x2212 11030 #define mmDP1_DP_VID_M_BASE_IDX 2 11031 #define mmDP1_DP_LINK_FRAMING_CNTL 0x2213 11032 #define mmDP1_DP_LINK_FRAMING_CNTL_BASE_IDX 2 11033 #define mmDP1_DP_HBR2_EYE_PATTERN 0x2214 11034 #define mmDP1_DP_HBR2_EYE_PATTERN_BASE_IDX 2 11035 #define mmDP1_DP_VID_MSA_VBID 0x2215 11036 #define mmDP1_DP_VID_MSA_VBID_BASE_IDX 2 11037 #define mmDP1_DP_VID_INTERRUPT_CNTL 0x2216 11038 #define mmDP1_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 11039 #define mmDP1_DP_DPHY_CNTL 0x2217 11040 #define mmDP1_DP_DPHY_CNTL_BASE_IDX 2 11041 #define mmDP1_DP_DPHY_TRAINING_PATTERN_SEL 0x2218 11042 #define mmDP1_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 11043 #define mmDP1_DP_DPHY_SYM0 0x2219 11044 #define mmDP1_DP_DPHY_SYM0_BASE_IDX 2 11045 #define mmDP1_DP_DPHY_SYM1 0x221a 11046 #define mmDP1_DP_DPHY_SYM1_BASE_IDX 2 11047 #define mmDP1_DP_DPHY_SYM2 0x221b 11048 #define mmDP1_DP_DPHY_SYM2_BASE_IDX 2 11049 #define mmDP1_DP_DPHY_8B10B_CNTL 0x221c 11050 #define mmDP1_DP_DPHY_8B10B_CNTL_BASE_IDX 2 11051 #define mmDP1_DP_DPHY_PRBS_CNTL 0x221d 11052 #define mmDP1_DP_DPHY_PRBS_CNTL_BASE_IDX 2 11053 #define mmDP1_DP_DPHY_SCRAM_CNTL 0x221e 11054 #define mmDP1_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 11055 #define mmDP1_DP_DPHY_CRC_EN 0x221f 11056 #define mmDP1_DP_DPHY_CRC_EN_BASE_IDX 2 11057 #define mmDP1_DP_DPHY_CRC_CNTL 0x2220 11058 #define mmDP1_DP_DPHY_CRC_CNTL_BASE_IDX 2 11059 #define mmDP1_DP_DPHY_CRC_RESULT 0x2221 11060 #define mmDP1_DP_DPHY_CRC_RESULT_BASE_IDX 2 11061 #define mmDP1_DP_DPHY_CRC_MST_CNTL 0x2222 11062 #define mmDP1_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 11063 #define mmDP1_DP_DPHY_CRC_MST_STATUS 0x2223 11064 #define mmDP1_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 11065 #define mmDP1_DP_DPHY_FAST_TRAINING 0x2224 11066 #define mmDP1_DP_DPHY_FAST_TRAINING_BASE_IDX 2 11067 #define mmDP1_DP_DPHY_FAST_TRAINING_STATUS 0x2225 11068 #define mmDP1_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 11069 #define mmDP1_DP_SEC_CNTL 0x222b 11070 #define mmDP1_DP_SEC_CNTL_BASE_IDX 2 11071 #define mmDP1_DP_SEC_CNTL1 0x222c 11072 #define mmDP1_DP_SEC_CNTL1_BASE_IDX 2 11073 #define mmDP1_DP_SEC_FRAMING1 0x222d 11074 #define mmDP1_DP_SEC_FRAMING1_BASE_IDX 2 11075 #define mmDP1_DP_SEC_FRAMING2 0x222e 11076 #define mmDP1_DP_SEC_FRAMING2_BASE_IDX 2 11077 #define mmDP1_DP_SEC_FRAMING3 0x222f 11078 #define mmDP1_DP_SEC_FRAMING3_BASE_IDX 2 11079 #define mmDP1_DP_SEC_FRAMING4 0x2230 11080 #define mmDP1_DP_SEC_FRAMING4_BASE_IDX 2 11081 #define mmDP1_DP_SEC_AUD_N 0x2231 11082 #define mmDP1_DP_SEC_AUD_N_BASE_IDX 2 11083 #define mmDP1_DP_SEC_AUD_N_READBACK 0x2232 11084 #define mmDP1_DP_SEC_AUD_N_READBACK_BASE_IDX 2 11085 #define mmDP1_DP_SEC_AUD_M 0x2233 11086 #define mmDP1_DP_SEC_AUD_M_BASE_IDX 2 11087 #define mmDP1_DP_SEC_AUD_M_READBACK 0x2234 11088 #define mmDP1_DP_SEC_AUD_M_READBACK_BASE_IDX 2 11089 #define mmDP1_DP_SEC_TIMESTAMP 0x2235 11090 #define mmDP1_DP_SEC_TIMESTAMP_BASE_IDX 2 11091 #define mmDP1_DP_SEC_PACKET_CNTL 0x2236 11092 #define mmDP1_DP_SEC_PACKET_CNTL_BASE_IDX 2 11093 #define mmDP1_DP_MSE_RATE_CNTL 0x2237 11094 #define mmDP1_DP_MSE_RATE_CNTL_BASE_IDX 2 11095 #define mmDP1_DP_MSE_RATE_UPDATE 0x2239 11096 #define mmDP1_DP_MSE_RATE_UPDATE_BASE_IDX 2 11097 #define mmDP1_DP_MSE_SAT0 0x223a 11098 #define mmDP1_DP_MSE_SAT0_BASE_IDX 2 11099 #define mmDP1_DP_MSE_SAT1 0x223b 11100 #define mmDP1_DP_MSE_SAT1_BASE_IDX 2 11101 #define mmDP1_DP_MSE_SAT2 0x223c 11102 #define mmDP1_DP_MSE_SAT2_BASE_IDX 2 11103 #define mmDP1_DP_MSE_SAT_UPDATE 0x223d 11104 #define mmDP1_DP_MSE_SAT_UPDATE_BASE_IDX 2 11105 #define mmDP1_DP_MSE_LINK_TIMING 0x223e 11106 #define mmDP1_DP_MSE_LINK_TIMING_BASE_IDX 2 11107 #define mmDP1_DP_MSE_MISC_CNTL 0x223f 11108 #define mmDP1_DP_MSE_MISC_CNTL_BASE_IDX 2 11109 #define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x2244 11110 #define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 11111 #define mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL 0x2245 11112 #define mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 11113 #define mmDP1_DP_MSE_SAT0_STATUS 0x2247 11114 #define mmDP1_DP_MSE_SAT0_STATUS_BASE_IDX 2 11115 #define mmDP1_DP_MSE_SAT1_STATUS 0x2248 11116 #define mmDP1_DP_MSE_SAT1_STATUS_BASE_IDX 2 11117 #define mmDP1_DP_MSE_SAT2_STATUS 0x2249 11118 #define mmDP1_DP_MSE_SAT2_STATUS_BASE_IDX 2 11119 #define mmDP1_DP_MSA_TIMING_PARAM1 0x224c 11120 #define mmDP1_DP_MSA_TIMING_PARAM1_BASE_IDX 2 11121 #define mmDP1_DP_MSA_TIMING_PARAM2 0x224d 11122 #define mmDP1_DP_MSA_TIMING_PARAM2_BASE_IDX 2 11123 #define mmDP1_DP_MSA_TIMING_PARAM3 0x224e 11124 #define mmDP1_DP_MSA_TIMING_PARAM3_BASE_IDX 2 11125 #define mmDP1_DP_MSA_TIMING_PARAM4 0x224f 11126 #define mmDP1_DP_MSA_TIMING_PARAM4_BASE_IDX 2 11127 #define mmDP1_DP_MSO_CNTL 0x2250 11128 #define mmDP1_DP_MSO_CNTL_BASE_IDX 2 11129 #define mmDP1_DP_MSO_CNTL1 0x2251 11130 #define mmDP1_DP_MSO_CNTL1_BASE_IDX 2 11131 #define mmDP1_DP_DSC_CNTL 0x2252 11132 #define mmDP1_DP_DSC_CNTL_BASE_IDX 2 11133 #define mmDP1_DP_SEC_CNTL2 0x2253 11134 #define mmDP1_DP_SEC_CNTL2_BASE_IDX 2 11135 #define mmDP1_DP_SEC_CNTL3 0x2254 11136 #define mmDP1_DP_SEC_CNTL3_BASE_IDX 2 11137 #define mmDP1_DP_SEC_CNTL4 0x2255 11138 #define mmDP1_DP_SEC_CNTL4_BASE_IDX 2 11139 #define mmDP1_DP_SEC_CNTL5 0x2256 11140 #define mmDP1_DP_SEC_CNTL5_BASE_IDX 2 11141 #define mmDP1_DP_SEC_CNTL6 0x2257 11142 #define mmDP1_DP_SEC_CNTL6_BASE_IDX 2 11143 #define mmDP1_DP_SEC_CNTL7 0x2258 11144 #define mmDP1_DP_SEC_CNTL7_BASE_IDX 2 11145 #define mmDP1_DP_DB_CNTL 0x2259 11146 #define mmDP1_DP_DB_CNTL_BASE_IDX 2 11147 #define mmDP1_DP_MSA_VBID_MISC 0x225a 11148 #define mmDP1_DP_MSA_VBID_MISC_BASE_IDX 2 11149 #define mmDP1_DP_SEC_METADATA_TRANSMISSION 0x225b 11150 #define mmDP1_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2 11151 #define mmDP1_DP_DSC_BYTES_PER_PIXEL 0x225c 11152 #define mmDP1_DP_DSC_BYTES_PER_PIXEL_BASE_IDX 2 11153 #define mmDP1_DP_ALPM_CNTL 0x225d 11154 #define mmDP1_DP_ALPM_CNTL_BASE_IDX 2 11155 #define mmDP1_DP_GSP8_CNTL 0x225e 11156 #define mmDP1_DP_GSP8_CNTL_BASE_IDX 2 11157 #define mmDP1_DP_GSP9_CNTL 0x225f 11158 #define mmDP1_DP_GSP9_CNTL_BASE_IDX 2 11159 #define mmDP1_DP_GSP10_CNTL 0x2260 11160 #define mmDP1_DP_GSP10_CNTL_BASE_IDX 2 11161 #define mmDP1_DP_GSP11_CNTL 0x2261 11162 #define mmDP1_DP_GSP11_CNTL_BASE_IDX 2 11163 #define mmDP1_DP_GSP_EN_DB_STATUS 0x2262 11164 #define mmDP1_DP_GSP_EN_DB_STATUS_BASE_IDX 2 11165 11166 11167 // addressBlock: dce_dc_dio_dig2_vpg_vpg_dispdec 11168 // base address: 0x15ca0 11169 #define mmVPG2_VPG_GENERIC_PACKET_ACCESS_CTRL 0x2268 11170 #define mmVPG2_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 11171 #define mmVPG2_VPG_GENERIC_PACKET_DATA 0x2269 11172 #define mmVPG2_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 11173 #define mmVPG2_VPG_GSP_FRAME_UPDATE_CTRL 0x226a 11174 #define mmVPG2_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 11175 #define mmVPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x226b 11176 #define mmVPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 11177 #define mmVPG2_VPG_GENERIC_STATUS 0x226c 11178 #define mmVPG2_VPG_GENERIC_STATUS_BASE_IDX 2 11179 #define mmVPG2_VPG_MEM_PWR 0x226d 11180 #define mmVPG2_VPG_MEM_PWR_BASE_IDX 2 11181 #define mmVPG2_VPG_ISRC1_2_ACCESS_CTRL 0x226e 11182 #define mmVPG2_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 11183 #define mmVPG2_VPG_ISRC1_2_DATA 0x226f 11184 #define mmVPG2_VPG_ISRC1_2_DATA_BASE_IDX 2 11185 #define mmVPG2_VPG_MPEG_INFO0 0x2270 11186 #define mmVPG2_VPG_MPEG_INFO0_BASE_IDX 2 11187 #define mmVPG2_VPG_MPEG_INFO1 0x2271 11188 #define mmVPG2_VPG_MPEG_INFO1_BASE_IDX 2 11189 11190 11191 // addressBlock: dce_dc_dio_dig2_afmt_afmt_dispdec 11192 // base address: 0x15ccc 11193 #define mmAFMT2_AFMT_VBI_PACKET_CONTROL 0x2274 11194 #define mmAFMT2_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 11195 #define mmAFMT2_AFMT_AUDIO_PACKET_CONTROL2 0x2275 11196 #define mmAFMT2_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 11197 #define mmAFMT2_AFMT_AUDIO_INFO0 0x2276 11198 #define mmAFMT2_AFMT_AUDIO_INFO0_BASE_IDX 2 11199 #define mmAFMT2_AFMT_AUDIO_INFO1 0x2277 11200 #define mmAFMT2_AFMT_AUDIO_INFO1_BASE_IDX 2 11201 #define mmAFMT2_AFMT_60958_0 0x2278 11202 #define mmAFMT2_AFMT_60958_0_BASE_IDX 2 11203 #define mmAFMT2_AFMT_60958_1 0x2279 11204 #define mmAFMT2_AFMT_60958_1_BASE_IDX 2 11205 #define mmAFMT2_AFMT_AUDIO_CRC_CONTROL 0x227a 11206 #define mmAFMT2_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 11207 #define mmAFMT2_AFMT_RAMP_CONTROL0 0x227b 11208 #define mmAFMT2_AFMT_RAMP_CONTROL0_BASE_IDX 2 11209 #define mmAFMT2_AFMT_RAMP_CONTROL1 0x227c 11210 #define mmAFMT2_AFMT_RAMP_CONTROL1_BASE_IDX 2 11211 #define mmAFMT2_AFMT_RAMP_CONTROL2 0x227d 11212 #define mmAFMT2_AFMT_RAMP_CONTROL2_BASE_IDX 2 11213 #define mmAFMT2_AFMT_RAMP_CONTROL3 0x227e 11214 #define mmAFMT2_AFMT_RAMP_CONTROL3_BASE_IDX 2 11215 #define mmAFMT2_AFMT_60958_2 0x227f 11216 #define mmAFMT2_AFMT_60958_2_BASE_IDX 2 11217 #define mmAFMT2_AFMT_AUDIO_CRC_RESULT 0x2280 11218 #define mmAFMT2_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 11219 #define mmAFMT2_AFMT_STATUS 0x2281 11220 #define mmAFMT2_AFMT_STATUS_BASE_IDX 2 11221 #define mmAFMT2_AFMT_AUDIO_PACKET_CONTROL 0x2282 11222 #define mmAFMT2_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 11223 #define mmAFMT2_AFMT_INFOFRAME_CONTROL0 0x2283 11224 #define mmAFMT2_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 11225 #define mmAFMT2_AFMT_INTERRUPT_STATUS 0x2284 11226 #define mmAFMT2_AFMT_INTERRUPT_STATUS_BASE_IDX 2 11227 #define mmAFMT2_AFMT_AUDIO_SRC_CONTROL 0x2285 11228 #define mmAFMT2_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 11229 #define mmAFMT2_AFMT_MEM_PWR 0x2287 11230 #define mmAFMT2_AFMT_MEM_PWR_BASE_IDX 2 11231 11232 11233 // addressBlock: dce_dc_dio_dig2_dme_dme_dispdec 11234 // base address: 0x15d24 11235 #define mmDME2_DME_CONTROL 0x2289 11236 #define mmDME2_DME_CONTROL_BASE_IDX 2 11237 #define mmDME2_DME_MEMORY_CONTROL 0x228a 11238 #define mmDME2_DME_MEMORY_CONTROL_BASE_IDX 2 11239 11240 11241 // addressBlock: dce_dc_dio_dig2_dispdec 11242 // base address: 0x800 11243 #define mmDIG2_DIG_FE_CNTL 0x228b 11244 #define mmDIG2_DIG_FE_CNTL_BASE_IDX 2 11245 #define mmDIG2_DIG_OUTPUT_CRC_CNTL 0x228c 11246 #define mmDIG2_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 11247 #define mmDIG2_DIG_OUTPUT_CRC_RESULT 0x228d 11248 #define mmDIG2_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 11249 #define mmDIG2_DIG_CLOCK_PATTERN 0x228e 11250 #define mmDIG2_DIG_CLOCK_PATTERN_BASE_IDX 2 11251 #define mmDIG2_DIG_TEST_PATTERN 0x228f 11252 #define mmDIG2_DIG_TEST_PATTERN_BASE_IDX 2 11253 #define mmDIG2_DIG_RANDOM_PATTERN_SEED 0x2290 11254 #define mmDIG2_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 11255 #define mmDIG2_DIG_FIFO_STATUS 0x2291 11256 #define mmDIG2_DIG_FIFO_STATUS_BASE_IDX 2 11257 #define mmDIG2_HDMI_METADATA_PACKET_CONTROL 0x2292 11258 #define mmDIG2_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2 11259 #define mmDIG2_HDMI_CONTROL 0x2293 11260 #define mmDIG2_HDMI_CONTROL_BASE_IDX 2 11261 #define mmDIG2_HDMI_STATUS 0x2294 11262 #define mmDIG2_HDMI_STATUS_BASE_IDX 2 11263 #define mmDIG2_HDMI_AUDIO_PACKET_CONTROL 0x2295 11264 #define mmDIG2_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 11265 #define mmDIG2_HDMI_ACR_PACKET_CONTROL 0x2296 11266 #define mmDIG2_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 11267 #define mmDIG2_HDMI_VBI_PACKET_CONTROL 0x2297 11268 #define mmDIG2_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 11269 #define mmDIG2_HDMI_INFOFRAME_CONTROL0 0x2298 11270 #define mmDIG2_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 11271 #define mmDIG2_HDMI_INFOFRAME_CONTROL1 0x2299 11272 #define mmDIG2_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 11273 #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL0 0x229a 11274 #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 11275 #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL6 0x229b 11276 #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX 2 11277 #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL5 0x229c 11278 #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2 11279 #define mmDIG2_HDMI_GC 0x229d 11280 #define mmDIG2_HDMI_GC_BASE_IDX 2 11281 #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL1 0x229e 11282 #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 11283 #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL2 0x229f 11284 #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 11285 #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL3 0x22a0 11286 #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 11287 #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL4 0x22a1 11288 #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2 11289 #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL7 0x22a2 11290 #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX 2 11291 #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL8 0x22a3 11292 #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX 2 11293 #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL9 0x22a4 11294 #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX 2 11295 #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL10 0x22a5 11296 #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX 2 11297 #define mmDIG2_HDMI_DB_CONTROL 0x22a6 11298 #define mmDIG2_HDMI_DB_CONTROL_BASE_IDX 2 11299 #define mmDIG2_HDMI_ACR_32_0 0x22a7 11300 #define mmDIG2_HDMI_ACR_32_0_BASE_IDX 2 11301 #define mmDIG2_HDMI_ACR_32_1 0x22a8 11302 #define mmDIG2_HDMI_ACR_32_1_BASE_IDX 2 11303 #define mmDIG2_HDMI_ACR_44_0 0x22a9 11304 #define mmDIG2_HDMI_ACR_44_0_BASE_IDX 2 11305 #define mmDIG2_HDMI_ACR_44_1 0x22aa 11306 #define mmDIG2_HDMI_ACR_44_1_BASE_IDX 2 11307 #define mmDIG2_HDMI_ACR_48_0 0x22ab 11308 #define mmDIG2_HDMI_ACR_48_0_BASE_IDX 2 11309 #define mmDIG2_HDMI_ACR_48_1 0x22ac 11310 #define mmDIG2_HDMI_ACR_48_1_BASE_IDX 2 11311 #define mmDIG2_HDMI_ACR_STATUS_0 0x22ad 11312 #define mmDIG2_HDMI_ACR_STATUS_0_BASE_IDX 2 11313 #define mmDIG2_HDMI_ACR_STATUS_1 0x22ae 11314 #define mmDIG2_HDMI_ACR_STATUS_1_BASE_IDX 2 11315 #define mmDIG2_AFMT_CNTL 0x22af 11316 #define mmDIG2_AFMT_CNTL_BASE_IDX 2 11317 #define mmDIG2_DIG_BE_CNTL 0x22b0 11318 #define mmDIG2_DIG_BE_CNTL_BASE_IDX 2 11319 #define mmDIG2_DIG_BE_EN_CNTL 0x22b1 11320 #define mmDIG2_DIG_BE_EN_CNTL_BASE_IDX 2 11321 #define mmDIG2_TMDS_CNTL 0x22d7 11322 #define mmDIG2_TMDS_CNTL_BASE_IDX 2 11323 #define mmDIG2_TMDS_CONTROL_CHAR 0x22d8 11324 #define mmDIG2_TMDS_CONTROL_CHAR_BASE_IDX 2 11325 #define mmDIG2_TMDS_CONTROL0_FEEDBACK 0x22d9 11326 #define mmDIG2_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 11327 #define mmDIG2_TMDS_STEREOSYNC_CTL_SEL 0x22da 11328 #define mmDIG2_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 11329 #define mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1 0x22db 11330 #define mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 11331 #define mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3 0x22dc 11332 #define mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 11333 #define mmDIG2_TMDS_CTL_BITS 0x22de 11334 #define mmDIG2_TMDS_CTL_BITS_BASE_IDX 2 11335 #define mmDIG2_TMDS_DCBALANCER_CONTROL 0x22df 11336 #define mmDIG2_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 11337 #define mmDIG2_TMDS_SYNC_DCBALANCE_CHAR 0x22e0 11338 #define mmDIG2_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2 11339 #define mmDIG2_TMDS_CTL0_1_GEN_CNTL 0x22e1 11340 #define mmDIG2_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 11341 #define mmDIG2_TMDS_CTL2_3_GEN_CNTL 0x22e2 11342 #define mmDIG2_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 11343 #define mmDIG2_DIG_VERSION 0x22e4 11344 #define mmDIG2_DIG_VERSION_BASE_IDX 2 11345 #define mmDIG2_DIG_LANE_ENABLE 0x22e5 11346 #define mmDIG2_DIG_LANE_ENABLE_BASE_IDX 2 11347 #define mmDIG2_FORCE_DIG_DISABLE 0x22e6 11348 #define mmDIG2_FORCE_DIG_DISABLE_BASE_IDX 2 11349 11350 // addressBlock: dce_dc_dio_dp2_dispdec 11351 // base address: 0x800 11352 #define mmDP2_DP_LINK_CNTL 0x2308 11353 #define mmDP2_DP_LINK_CNTL_BASE_IDX 2 11354 #define mmDP2_DP_PIXEL_FORMAT 0x2309 11355 #define mmDP2_DP_PIXEL_FORMAT_BASE_IDX 2 11356 #define mmDP2_DP_MSA_COLORIMETRY 0x230a 11357 #define mmDP2_DP_MSA_COLORIMETRY_BASE_IDX 2 11358 #define mmDP2_DP_CONFIG 0x230b 11359 #define mmDP2_DP_CONFIG_BASE_IDX 2 11360 #define mmDP2_DP_VID_STREAM_CNTL 0x230c 11361 #define mmDP2_DP_VID_STREAM_CNTL_BASE_IDX 2 11362 #define mmDP2_DP_STEER_FIFO 0x230d 11363 #define mmDP2_DP_STEER_FIFO_BASE_IDX 2 11364 #define mmDP2_DP_MSA_MISC 0x230e 11365 #define mmDP2_DP_MSA_MISC_BASE_IDX 2 11366 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x230f 11367 #define mmDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 11368 #define mmDP2_DP_VID_TIMING 0x2310 11369 #define mmDP2_DP_VID_TIMING_BASE_IDX 2 11370 #define mmDP2_DP_VID_N 0x2311 11371 #define mmDP2_DP_VID_N_BASE_IDX 2 11372 #define mmDP2_DP_VID_M 0x2312 11373 #define mmDP2_DP_VID_M_BASE_IDX 2 11374 #define mmDP2_DP_LINK_FRAMING_CNTL 0x2313 11375 #define mmDP2_DP_LINK_FRAMING_CNTL_BASE_IDX 2 11376 #define mmDP2_DP_HBR2_EYE_PATTERN 0x2314 11377 #define mmDP2_DP_HBR2_EYE_PATTERN_BASE_IDX 2 11378 #define mmDP2_DP_VID_MSA_VBID 0x2315 11379 #define mmDP2_DP_VID_MSA_VBID_BASE_IDX 2 11380 #define mmDP2_DP_VID_INTERRUPT_CNTL 0x2316 11381 #define mmDP2_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 11382 #define mmDP2_DP_DPHY_CNTL 0x2317 11383 #define mmDP2_DP_DPHY_CNTL_BASE_IDX 2 11384 #define mmDP2_DP_DPHY_TRAINING_PATTERN_SEL 0x2318 11385 #define mmDP2_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 11386 #define mmDP2_DP_DPHY_SYM0 0x2319 11387 #define mmDP2_DP_DPHY_SYM0_BASE_IDX 2 11388 #define mmDP2_DP_DPHY_SYM1 0x231a 11389 #define mmDP2_DP_DPHY_SYM1_BASE_IDX 2 11390 #define mmDP2_DP_DPHY_SYM2 0x231b 11391 #define mmDP2_DP_DPHY_SYM2_BASE_IDX 2 11392 #define mmDP2_DP_DPHY_8B10B_CNTL 0x231c 11393 #define mmDP2_DP_DPHY_8B10B_CNTL_BASE_IDX 2 11394 #define mmDP2_DP_DPHY_PRBS_CNTL 0x231d 11395 #define mmDP2_DP_DPHY_PRBS_CNTL_BASE_IDX 2 11396 #define mmDP2_DP_DPHY_SCRAM_CNTL 0x231e 11397 #define mmDP2_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 11398 #define mmDP2_DP_DPHY_CRC_EN 0x231f 11399 #define mmDP2_DP_DPHY_CRC_EN_BASE_IDX 2 11400 #define mmDP2_DP_DPHY_CRC_CNTL 0x2320 11401 #define mmDP2_DP_DPHY_CRC_CNTL_BASE_IDX 2 11402 #define mmDP2_DP_DPHY_CRC_RESULT 0x2321 11403 #define mmDP2_DP_DPHY_CRC_RESULT_BASE_IDX 2 11404 #define mmDP2_DP_DPHY_CRC_MST_CNTL 0x2322 11405 #define mmDP2_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 11406 #define mmDP2_DP_DPHY_CRC_MST_STATUS 0x2323 11407 #define mmDP2_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 11408 #define mmDP2_DP_DPHY_FAST_TRAINING 0x2324 11409 #define mmDP2_DP_DPHY_FAST_TRAINING_BASE_IDX 2 11410 #define mmDP2_DP_DPHY_FAST_TRAINING_STATUS 0x2325 11411 #define mmDP2_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 11412 #define mmDP2_DP_SEC_CNTL 0x232b 11413 #define mmDP2_DP_SEC_CNTL_BASE_IDX 2 11414 #define mmDP2_DP_SEC_CNTL1 0x232c 11415 #define mmDP2_DP_SEC_CNTL1_BASE_IDX 2 11416 #define mmDP2_DP_SEC_FRAMING1 0x232d 11417 #define mmDP2_DP_SEC_FRAMING1_BASE_IDX 2 11418 #define mmDP2_DP_SEC_FRAMING2 0x232e 11419 #define mmDP2_DP_SEC_FRAMING2_BASE_IDX 2 11420 #define mmDP2_DP_SEC_FRAMING3 0x232f 11421 #define mmDP2_DP_SEC_FRAMING3_BASE_IDX 2 11422 #define mmDP2_DP_SEC_FRAMING4 0x2330 11423 #define mmDP2_DP_SEC_FRAMING4_BASE_IDX 2 11424 #define mmDP2_DP_SEC_AUD_N 0x2331 11425 #define mmDP2_DP_SEC_AUD_N_BASE_IDX 2 11426 #define mmDP2_DP_SEC_AUD_N_READBACK 0x2332 11427 #define mmDP2_DP_SEC_AUD_N_READBACK_BASE_IDX 2 11428 #define mmDP2_DP_SEC_AUD_M 0x2333 11429 #define mmDP2_DP_SEC_AUD_M_BASE_IDX 2 11430 #define mmDP2_DP_SEC_AUD_M_READBACK 0x2334 11431 #define mmDP2_DP_SEC_AUD_M_READBACK_BASE_IDX 2 11432 #define mmDP2_DP_SEC_TIMESTAMP 0x2335 11433 #define mmDP2_DP_SEC_TIMESTAMP_BASE_IDX 2 11434 #define mmDP2_DP_SEC_PACKET_CNTL 0x2336 11435 #define mmDP2_DP_SEC_PACKET_CNTL_BASE_IDX 2 11436 #define mmDP2_DP_MSE_RATE_CNTL 0x2337 11437 #define mmDP2_DP_MSE_RATE_CNTL_BASE_IDX 2 11438 #define mmDP2_DP_MSE_RATE_UPDATE 0x2339 11439 #define mmDP2_DP_MSE_RATE_UPDATE_BASE_IDX 2 11440 #define mmDP2_DP_MSE_SAT0 0x233a 11441 #define mmDP2_DP_MSE_SAT0_BASE_IDX 2 11442 #define mmDP2_DP_MSE_SAT1 0x233b 11443 #define mmDP2_DP_MSE_SAT1_BASE_IDX 2 11444 #define mmDP2_DP_MSE_SAT2 0x233c 11445 #define mmDP2_DP_MSE_SAT2_BASE_IDX 2 11446 #define mmDP2_DP_MSE_SAT_UPDATE 0x233d 11447 #define mmDP2_DP_MSE_SAT_UPDATE_BASE_IDX 2 11448 #define mmDP2_DP_MSE_LINK_TIMING 0x233e 11449 #define mmDP2_DP_MSE_LINK_TIMING_BASE_IDX 2 11450 #define mmDP2_DP_MSE_MISC_CNTL 0x233f 11451 #define mmDP2_DP_MSE_MISC_CNTL_BASE_IDX 2 11452 #define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL 0x2344 11453 #define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 11454 #define mmDP2_DP_DPHY_HBR2_PATTERN_CONTROL 0x2345 11455 #define mmDP2_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 11456 #define mmDP2_DP_MSE_SAT0_STATUS 0x2347 11457 #define mmDP2_DP_MSE_SAT0_STATUS_BASE_IDX 2 11458 #define mmDP2_DP_MSE_SAT1_STATUS 0x2348 11459 #define mmDP2_DP_MSE_SAT1_STATUS_BASE_IDX 2 11460 #define mmDP2_DP_MSE_SAT2_STATUS 0x2349 11461 #define mmDP2_DP_MSE_SAT2_STATUS_BASE_IDX 2 11462 #define mmDP2_DP_MSA_TIMING_PARAM1 0x234c 11463 #define mmDP2_DP_MSA_TIMING_PARAM1_BASE_IDX 2 11464 #define mmDP2_DP_MSA_TIMING_PARAM2 0x234d 11465 #define mmDP2_DP_MSA_TIMING_PARAM2_BASE_IDX 2 11466 #define mmDP2_DP_MSA_TIMING_PARAM3 0x234e 11467 #define mmDP2_DP_MSA_TIMING_PARAM3_BASE_IDX 2 11468 #define mmDP2_DP_MSA_TIMING_PARAM4 0x234f 11469 #define mmDP2_DP_MSA_TIMING_PARAM4_BASE_IDX 2 11470 #define mmDP2_DP_MSO_CNTL 0x2350 11471 #define mmDP2_DP_MSO_CNTL_BASE_IDX 2 11472 #define mmDP2_DP_MSO_CNTL1 0x2351 11473 #define mmDP2_DP_MSO_CNTL1_BASE_IDX 2 11474 #define mmDP2_DP_DSC_CNTL 0x2352 11475 #define mmDP2_DP_DSC_CNTL_BASE_IDX 2 11476 #define mmDP2_DP_SEC_CNTL2 0x2353 11477 #define mmDP2_DP_SEC_CNTL2_BASE_IDX 2 11478 #define mmDP2_DP_SEC_CNTL3 0x2354 11479 #define mmDP2_DP_SEC_CNTL3_BASE_IDX 2 11480 #define mmDP2_DP_SEC_CNTL4 0x2355 11481 #define mmDP2_DP_SEC_CNTL4_BASE_IDX 2 11482 #define mmDP2_DP_SEC_CNTL5 0x2356 11483 #define mmDP2_DP_SEC_CNTL5_BASE_IDX 2 11484 #define mmDP2_DP_SEC_CNTL6 0x2357 11485 #define mmDP2_DP_SEC_CNTL6_BASE_IDX 2 11486 #define mmDP2_DP_SEC_CNTL7 0x2358 11487 #define mmDP2_DP_SEC_CNTL7_BASE_IDX 2 11488 #define mmDP2_DP_DB_CNTL 0x2359 11489 #define mmDP2_DP_DB_CNTL_BASE_IDX 2 11490 #define mmDP2_DP_MSA_VBID_MISC 0x235a 11491 #define mmDP2_DP_MSA_VBID_MISC_BASE_IDX 2 11492 #define mmDP2_DP_SEC_METADATA_TRANSMISSION 0x235b 11493 #define mmDP2_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2 11494 #define mmDP2_DP_DSC_BYTES_PER_PIXEL 0x235c 11495 #define mmDP2_DP_DSC_BYTES_PER_PIXEL_BASE_IDX 2 11496 #define mmDP2_DP_ALPM_CNTL 0x235d 11497 #define mmDP2_DP_ALPM_CNTL_BASE_IDX 2 11498 #define mmDP2_DP_GSP8_CNTL 0x235e 11499 #define mmDP2_DP_GSP8_CNTL_BASE_IDX 2 11500 #define mmDP2_DP_GSP9_CNTL 0x235f 11501 #define mmDP2_DP_GSP9_CNTL_BASE_IDX 2 11502 #define mmDP2_DP_GSP10_CNTL 0x2360 11503 #define mmDP2_DP_GSP10_CNTL_BASE_IDX 2 11504 #define mmDP2_DP_GSP11_CNTL 0x2361 11505 #define mmDP2_DP_GSP11_CNTL_BASE_IDX 2 11506 #define mmDP2_DP_GSP_EN_DB_STATUS 0x2362 11507 #define mmDP2_DP_GSP_EN_DB_STATUS_BASE_IDX 2 11508 11509 11510 // addressBlock: dce_dc_dio_dig3_vpg_vpg_dispdec 11511 // base address: 0x160a0 11512 #define mmVPG3_VPG_GENERIC_PACKET_ACCESS_CTRL 0x2368 11513 #define mmVPG3_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 11514 #define mmVPG3_VPG_GENERIC_PACKET_DATA 0x2369 11515 #define mmVPG3_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 11516 #define mmVPG3_VPG_GSP_FRAME_UPDATE_CTRL 0x236a 11517 #define mmVPG3_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 11518 #define mmVPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x236b 11519 #define mmVPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 11520 #define mmVPG3_VPG_GENERIC_STATUS 0x236c 11521 #define mmVPG3_VPG_GENERIC_STATUS_BASE_IDX 2 11522 #define mmVPG3_VPG_MEM_PWR 0x236d 11523 #define mmVPG3_VPG_MEM_PWR_BASE_IDX 2 11524 #define mmVPG3_VPG_ISRC1_2_ACCESS_CTRL 0x236e 11525 #define mmVPG3_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 11526 #define mmVPG3_VPG_ISRC1_2_DATA 0x236f 11527 #define mmVPG3_VPG_ISRC1_2_DATA_BASE_IDX 2 11528 #define mmVPG3_VPG_MPEG_INFO0 0x2370 11529 #define mmVPG3_VPG_MPEG_INFO0_BASE_IDX 2 11530 #define mmVPG3_VPG_MPEG_INFO1 0x2371 11531 #define mmVPG3_VPG_MPEG_INFO1_BASE_IDX 2 11532 11533 11534 // addressBlock: dce_dc_dio_dig3_afmt_afmt_dispdec 11535 // base address: 0x160cc 11536 #define mmAFMT3_AFMT_VBI_PACKET_CONTROL 0x2374 11537 #define mmAFMT3_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 11538 #define mmAFMT3_AFMT_AUDIO_PACKET_CONTROL2 0x2375 11539 #define mmAFMT3_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 11540 #define mmAFMT3_AFMT_AUDIO_INFO0 0x2376 11541 #define mmAFMT3_AFMT_AUDIO_INFO0_BASE_IDX 2 11542 #define mmAFMT3_AFMT_AUDIO_INFO1 0x2377 11543 #define mmAFMT3_AFMT_AUDIO_INFO1_BASE_IDX 2 11544 #define mmAFMT3_AFMT_60958_0 0x2378 11545 #define mmAFMT3_AFMT_60958_0_BASE_IDX 2 11546 #define mmAFMT3_AFMT_60958_1 0x2379 11547 #define mmAFMT3_AFMT_60958_1_BASE_IDX 2 11548 #define mmAFMT3_AFMT_AUDIO_CRC_CONTROL 0x237a 11549 #define mmAFMT3_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 11550 #define mmAFMT3_AFMT_RAMP_CONTROL0 0x237b 11551 #define mmAFMT3_AFMT_RAMP_CONTROL0_BASE_IDX 2 11552 #define mmAFMT3_AFMT_RAMP_CONTROL1 0x237c 11553 #define mmAFMT3_AFMT_RAMP_CONTROL1_BASE_IDX 2 11554 #define mmAFMT3_AFMT_RAMP_CONTROL2 0x237d 11555 #define mmAFMT3_AFMT_RAMP_CONTROL2_BASE_IDX 2 11556 #define mmAFMT3_AFMT_RAMP_CONTROL3 0x237e 11557 #define mmAFMT3_AFMT_RAMP_CONTROL3_BASE_IDX 2 11558 #define mmAFMT3_AFMT_60958_2 0x237f 11559 #define mmAFMT3_AFMT_60958_2_BASE_IDX 2 11560 #define mmAFMT3_AFMT_AUDIO_CRC_RESULT 0x2380 11561 #define mmAFMT3_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 11562 #define mmAFMT3_AFMT_STATUS 0x2381 11563 #define mmAFMT3_AFMT_STATUS_BASE_IDX 2 11564 #define mmAFMT3_AFMT_AUDIO_PACKET_CONTROL 0x2382 11565 #define mmAFMT3_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 11566 #define mmAFMT3_AFMT_INFOFRAME_CONTROL0 0x2383 11567 #define mmAFMT3_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 11568 #define mmAFMT3_AFMT_INTERRUPT_STATUS 0x2384 11569 #define mmAFMT3_AFMT_INTERRUPT_STATUS_BASE_IDX 2 11570 #define mmAFMT3_AFMT_AUDIO_SRC_CONTROL 0x2385 11571 #define mmAFMT3_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 11572 #define mmAFMT3_AFMT_MEM_PWR 0x2387 11573 #define mmAFMT3_AFMT_MEM_PWR_BASE_IDX 2 11574 11575 11576 // addressBlock: dce_dc_dio_dig3_dme_dme_dispdec 11577 // base address: 0x16124 11578 #define mmDME3_DME_CONTROL 0x2389 11579 #define mmDME3_DME_CONTROL_BASE_IDX 2 11580 #define mmDME3_DME_MEMORY_CONTROL 0x238a 11581 #define mmDME3_DME_MEMORY_CONTROL_BASE_IDX 2 11582 11583 11584 // addressBlock: dce_dc_dio_dig3_dispdec 11585 // base address: 0xc00 11586 #define mmDIG3_DIG_FE_CNTL 0x238b 11587 #define mmDIG3_DIG_FE_CNTL_BASE_IDX 2 11588 #define mmDIG3_DIG_OUTPUT_CRC_CNTL 0x238c 11589 #define mmDIG3_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 11590 #define mmDIG3_DIG_OUTPUT_CRC_RESULT 0x238d 11591 #define mmDIG3_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 11592 #define mmDIG3_DIG_CLOCK_PATTERN 0x238e 11593 #define mmDIG3_DIG_CLOCK_PATTERN_BASE_IDX 2 11594 #define mmDIG3_DIG_TEST_PATTERN 0x238f 11595 #define mmDIG3_DIG_TEST_PATTERN_BASE_IDX 2 11596 #define mmDIG3_DIG_RANDOM_PATTERN_SEED 0x2390 11597 #define mmDIG3_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 11598 #define mmDIG3_DIG_FIFO_STATUS 0x2391 11599 #define mmDIG3_DIG_FIFO_STATUS_BASE_IDX 2 11600 #define mmDIG3_HDMI_METADATA_PACKET_CONTROL 0x2392 11601 #define mmDIG3_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2 11602 #define mmDIG3_HDMI_CONTROL 0x2393 11603 #define mmDIG3_HDMI_CONTROL_BASE_IDX 2 11604 #define mmDIG3_HDMI_STATUS 0x2394 11605 #define mmDIG3_HDMI_STATUS_BASE_IDX 2 11606 #define mmDIG3_HDMI_AUDIO_PACKET_CONTROL 0x2395 11607 #define mmDIG3_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 11608 #define mmDIG3_HDMI_ACR_PACKET_CONTROL 0x2396 11609 #define mmDIG3_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 11610 #define mmDIG3_HDMI_VBI_PACKET_CONTROL 0x2397 11611 #define mmDIG3_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 11612 #define mmDIG3_HDMI_INFOFRAME_CONTROL0 0x2398 11613 #define mmDIG3_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 11614 #define mmDIG3_HDMI_INFOFRAME_CONTROL1 0x2399 11615 #define mmDIG3_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 11616 #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL0 0x239a 11617 #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 11618 #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL6 0x239b 11619 #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX 2 11620 #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL5 0x239c 11621 #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2 11622 #define mmDIG3_HDMI_GC 0x239d 11623 #define mmDIG3_HDMI_GC_BASE_IDX 2 11624 #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL1 0x239e 11625 #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 11626 #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL2 0x239f 11627 #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 11628 #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL3 0x23a0 11629 #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 11630 #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL4 0x23a1 11631 #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2 11632 #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL7 0x23a2 11633 #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX 2 11634 #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL8 0x23a3 11635 #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX 2 11636 #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL9 0x23a4 11637 #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX 2 11638 #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL10 0x23a5 11639 #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX 2 11640 #define mmDIG3_HDMI_DB_CONTROL 0x23a6 11641 #define mmDIG3_HDMI_DB_CONTROL_BASE_IDX 2 11642 #define mmDIG3_HDMI_ACR_32_0 0x23a7 11643 #define mmDIG3_HDMI_ACR_32_0_BASE_IDX 2 11644 #define mmDIG3_HDMI_ACR_32_1 0x23a8 11645 #define mmDIG3_HDMI_ACR_32_1_BASE_IDX 2 11646 #define mmDIG3_HDMI_ACR_44_0 0x23a9 11647 #define mmDIG3_HDMI_ACR_44_0_BASE_IDX 2 11648 #define mmDIG3_HDMI_ACR_44_1 0x23aa 11649 #define mmDIG3_HDMI_ACR_44_1_BASE_IDX 2 11650 #define mmDIG3_HDMI_ACR_48_0 0x23ab 11651 #define mmDIG3_HDMI_ACR_48_0_BASE_IDX 2 11652 #define mmDIG3_HDMI_ACR_48_1 0x23ac 11653 #define mmDIG3_HDMI_ACR_48_1_BASE_IDX 2 11654 #define mmDIG3_HDMI_ACR_STATUS_0 0x23ad 11655 #define mmDIG3_HDMI_ACR_STATUS_0_BASE_IDX 2 11656 #define mmDIG3_HDMI_ACR_STATUS_1 0x23ae 11657 #define mmDIG3_HDMI_ACR_STATUS_1_BASE_IDX 2 11658 #define mmDIG3_AFMT_CNTL 0x23af 11659 #define mmDIG3_AFMT_CNTL_BASE_IDX 2 11660 #define mmDIG3_DIG_BE_CNTL 0x23b0 11661 #define mmDIG3_DIG_BE_CNTL_BASE_IDX 2 11662 #define mmDIG3_DIG_BE_EN_CNTL 0x23b1 11663 #define mmDIG3_DIG_BE_EN_CNTL_BASE_IDX 2 11664 #define mmDIG3_TMDS_CNTL 0x23d7 11665 #define mmDIG3_TMDS_CNTL_BASE_IDX 2 11666 #define mmDIG3_TMDS_CONTROL_CHAR 0x23d8 11667 #define mmDIG3_TMDS_CONTROL_CHAR_BASE_IDX 2 11668 #define mmDIG3_TMDS_CONTROL0_FEEDBACK 0x23d9 11669 #define mmDIG3_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 11670 #define mmDIG3_TMDS_STEREOSYNC_CTL_SEL 0x23da 11671 #define mmDIG3_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 11672 #define mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1 0x23db 11673 #define mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 11674 #define mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3 0x23dc 11675 #define mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 11676 #define mmDIG3_TMDS_CTL_BITS 0x23de 11677 #define mmDIG3_TMDS_CTL_BITS_BASE_IDX 2 11678 #define mmDIG3_TMDS_DCBALANCER_CONTROL 0x23df 11679 #define mmDIG3_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 11680 #define mmDIG3_TMDS_SYNC_DCBALANCE_CHAR 0x23e0 11681 #define mmDIG3_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2 11682 #define mmDIG3_TMDS_CTL0_1_GEN_CNTL 0x23e1 11683 #define mmDIG3_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 11684 #define mmDIG3_TMDS_CTL2_3_GEN_CNTL 0x23e2 11685 #define mmDIG3_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 11686 #define mmDIG3_DIG_VERSION 0x23e4 11687 #define mmDIG3_DIG_VERSION_BASE_IDX 2 11688 #define mmDIG3_DIG_LANE_ENABLE 0x23e5 11689 #define mmDIG3_DIG_LANE_ENABLE_BASE_IDX 2 11690 #define mmDIG3_FORCE_DIG_DISABLE 0x23e6 11691 #define mmDIG3_FORCE_DIG_DISABLE_BASE_IDX 2 11692 11693 11694 // addressBlock: dce_dc_dio_dp3_dispdec 11695 // base address: 0xc00 11696 #define mmDP3_DP_LINK_CNTL 0x2408 11697 #define mmDP3_DP_LINK_CNTL_BASE_IDX 2 11698 #define mmDP3_DP_PIXEL_FORMAT 0x2409 11699 #define mmDP3_DP_PIXEL_FORMAT_BASE_IDX 2 11700 #define mmDP3_DP_MSA_COLORIMETRY 0x240a 11701 #define mmDP3_DP_MSA_COLORIMETRY_BASE_IDX 2 11702 #define mmDP3_DP_CONFIG 0x240b 11703 #define mmDP3_DP_CONFIG_BASE_IDX 2 11704 #define mmDP3_DP_VID_STREAM_CNTL 0x240c 11705 #define mmDP3_DP_VID_STREAM_CNTL_BASE_IDX 2 11706 #define mmDP3_DP_STEER_FIFO 0x240d 11707 #define mmDP3_DP_STEER_FIFO_BASE_IDX 2 11708 #define mmDP3_DP_MSA_MISC 0x240e 11709 #define mmDP3_DP_MSA_MISC_BASE_IDX 2 11710 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x240f 11711 #define mmDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 11712 #define mmDP3_DP_VID_TIMING 0x2410 11713 #define mmDP3_DP_VID_TIMING_BASE_IDX 2 11714 #define mmDP3_DP_VID_N 0x2411 11715 #define mmDP3_DP_VID_N_BASE_IDX 2 11716 #define mmDP3_DP_VID_M 0x2412 11717 #define mmDP3_DP_VID_M_BASE_IDX 2 11718 #define mmDP3_DP_LINK_FRAMING_CNTL 0x2413 11719 #define mmDP3_DP_LINK_FRAMING_CNTL_BASE_IDX 2 11720 #define mmDP3_DP_HBR2_EYE_PATTERN 0x2414 11721 #define mmDP3_DP_HBR2_EYE_PATTERN_BASE_IDX 2 11722 #define mmDP3_DP_VID_MSA_VBID 0x2415 11723 #define mmDP3_DP_VID_MSA_VBID_BASE_IDX 2 11724 #define mmDP3_DP_VID_INTERRUPT_CNTL 0x2416 11725 #define mmDP3_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 11726 #define mmDP3_DP_DPHY_CNTL 0x2417 11727 #define mmDP3_DP_DPHY_CNTL_BASE_IDX 2 11728 #define mmDP3_DP_DPHY_TRAINING_PATTERN_SEL 0x2418 11729 #define mmDP3_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 11730 #define mmDP3_DP_DPHY_SYM0 0x2419 11731 #define mmDP3_DP_DPHY_SYM0_BASE_IDX 2 11732 #define mmDP3_DP_DPHY_SYM1 0x241a 11733 #define mmDP3_DP_DPHY_SYM1_BASE_IDX 2 11734 #define mmDP3_DP_DPHY_SYM2 0x241b 11735 #define mmDP3_DP_DPHY_SYM2_BASE_IDX 2 11736 #define mmDP3_DP_DPHY_8B10B_CNTL 0x241c 11737 #define mmDP3_DP_DPHY_8B10B_CNTL_BASE_IDX 2 11738 #define mmDP3_DP_DPHY_PRBS_CNTL 0x241d 11739 #define mmDP3_DP_DPHY_PRBS_CNTL_BASE_IDX 2 11740 #define mmDP3_DP_DPHY_SCRAM_CNTL 0x241e 11741 #define mmDP3_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 11742 #define mmDP3_DP_DPHY_CRC_EN 0x241f 11743 #define mmDP3_DP_DPHY_CRC_EN_BASE_IDX 2 11744 #define mmDP3_DP_DPHY_CRC_CNTL 0x2420 11745 #define mmDP3_DP_DPHY_CRC_CNTL_BASE_IDX 2 11746 #define mmDP3_DP_DPHY_CRC_RESULT 0x2421 11747 #define mmDP3_DP_DPHY_CRC_RESULT_BASE_IDX 2 11748 #define mmDP3_DP_DPHY_CRC_MST_CNTL 0x2422 11749 #define mmDP3_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 11750 #define mmDP3_DP_DPHY_CRC_MST_STATUS 0x2423 11751 #define mmDP3_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 11752 #define mmDP3_DP_DPHY_FAST_TRAINING 0x2424 11753 #define mmDP3_DP_DPHY_FAST_TRAINING_BASE_IDX 2 11754 #define mmDP3_DP_DPHY_FAST_TRAINING_STATUS 0x2425 11755 #define mmDP3_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 11756 #define mmDP3_DP_SEC_CNTL 0x242b 11757 #define mmDP3_DP_SEC_CNTL_BASE_IDX 2 11758 #define mmDP3_DP_SEC_CNTL1 0x242c 11759 #define mmDP3_DP_SEC_CNTL1_BASE_IDX 2 11760 #define mmDP3_DP_SEC_FRAMING1 0x242d 11761 #define mmDP3_DP_SEC_FRAMING1_BASE_IDX 2 11762 #define mmDP3_DP_SEC_FRAMING2 0x242e 11763 #define mmDP3_DP_SEC_FRAMING2_BASE_IDX 2 11764 #define mmDP3_DP_SEC_FRAMING3 0x242f 11765 #define mmDP3_DP_SEC_FRAMING3_BASE_IDX 2 11766 #define mmDP3_DP_SEC_FRAMING4 0x2430 11767 #define mmDP3_DP_SEC_FRAMING4_BASE_IDX 2 11768 #define mmDP3_DP_SEC_AUD_N 0x2431 11769 #define mmDP3_DP_SEC_AUD_N_BASE_IDX 2 11770 #define mmDP3_DP_SEC_AUD_N_READBACK 0x2432 11771 #define mmDP3_DP_SEC_AUD_N_READBACK_BASE_IDX 2 11772 #define mmDP3_DP_SEC_AUD_M 0x2433 11773 #define mmDP3_DP_SEC_AUD_M_BASE_IDX 2 11774 #define mmDP3_DP_SEC_AUD_M_READBACK 0x2434 11775 #define mmDP3_DP_SEC_AUD_M_READBACK_BASE_IDX 2 11776 #define mmDP3_DP_SEC_TIMESTAMP 0x2435 11777 #define mmDP3_DP_SEC_TIMESTAMP_BASE_IDX 2 11778 #define mmDP3_DP_SEC_PACKET_CNTL 0x2436 11779 #define mmDP3_DP_SEC_PACKET_CNTL_BASE_IDX 2 11780 #define mmDP3_DP_MSE_RATE_CNTL 0x2437 11781 #define mmDP3_DP_MSE_RATE_CNTL_BASE_IDX 2 11782 #define mmDP3_DP_MSE_RATE_UPDATE 0x2439 11783 #define mmDP3_DP_MSE_RATE_UPDATE_BASE_IDX 2 11784 #define mmDP3_DP_MSE_SAT0 0x243a 11785 #define mmDP3_DP_MSE_SAT0_BASE_IDX 2 11786 #define mmDP3_DP_MSE_SAT1 0x243b 11787 #define mmDP3_DP_MSE_SAT1_BASE_IDX 2 11788 #define mmDP3_DP_MSE_SAT2 0x243c 11789 #define mmDP3_DP_MSE_SAT2_BASE_IDX 2 11790 #define mmDP3_DP_MSE_SAT_UPDATE 0x243d 11791 #define mmDP3_DP_MSE_SAT_UPDATE_BASE_IDX 2 11792 #define mmDP3_DP_MSE_LINK_TIMING 0x243e 11793 #define mmDP3_DP_MSE_LINK_TIMING_BASE_IDX 2 11794 #define mmDP3_DP_MSE_MISC_CNTL 0x243f 11795 #define mmDP3_DP_MSE_MISC_CNTL_BASE_IDX 2 11796 #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x2444 11797 #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 11798 #define mmDP3_DP_DPHY_HBR2_PATTERN_CONTROL 0x2445 11799 #define mmDP3_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 11800 #define mmDP3_DP_MSE_SAT0_STATUS 0x2447 11801 #define mmDP3_DP_MSE_SAT0_STATUS_BASE_IDX 2 11802 #define mmDP3_DP_MSE_SAT1_STATUS 0x2448 11803 #define mmDP3_DP_MSE_SAT1_STATUS_BASE_IDX 2 11804 #define mmDP3_DP_MSE_SAT2_STATUS 0x2449 11805 #define mmDP3_DP_MSE_SAT2_STATUS_BASE_IDX 2 11806 #define mmDP3_DP_MSA_TIMING_PARAM1 0x244c 11807 #define mmDP3_DP_MSA_TIMING_PARAM1_BASE_IDX 2 11808 #define mmDP3_DP_MSA_TIMING_PARAM2 0x244d 11809 #define mmDP3_DP_MSA_TIMING_PARAM2_BASE_IDX 2 11810 #define mmDP3_DP_MSA_TIMING_PARAM3 0x244e 11811 #define mmDP3_DP_MSA_TIMING_PARAM3_BASE_IDX 2 11812 #define mmDP3_DP_MSA_TIMING_PARAM4 0x244f 11813 #define mmDP3_DP_MSA_TIMING_PARAM4_BASE_IDX 2 11814 #define mmDP3_DP_MSO_CNTL 0x2450 11815 #define mmDP3_DP_MSO_CNTL_BASE_IDX 2 11816 #define mmDP3_DP_MSO_CNTL1 0x2451 11817 #define mmDP3_DP_MSO_CNTL1_BASE_IDX 2 11818 #define mmDP3_DP_DSC_CNTL 0x2452 11819 #define mmDP3_DP_DSC_CNTL_BASE_IDX 2 11820 #define mmDP3_DP_SEC_CNTL2 0x2453 11821 #define mmDP3_DP_SEC_CNTL2_BASE_IDX 2 11822 #define mmDP3_DP_SEC_CNTL3 0x2454 11823 #define mmDP3_DP_SEC_CNTL3_BASE_IDX 2 11824 #define mmDP3_DP_SEC_CNTL4 0x2455 11825 #define mmDP3_DP_SEC_CNTL4_BASE_IDX 2 11826 #define mmDP3_DP_SEC_CNTL5 0x2456 11827 #define mmDP3_DP_SEC_CNTL5_BASE_IDX 2 11828 #define mmDP3_DP_SEC_CNTL6 0x2457 11829 #define mmDP3_DP_SEC_CNTL6_BASE_IDX 2 11830 #define mmDP3_DP_SEC_CNTL7 0x2458 11831 #define mmDP3_DP_SEC_CNTL7_BASE_IDX 2 11832 #define mmDP3_DP_DB_CNTL 0x2459 11833 #define mmDP3_DP_DB_CNTL_BASE_IDX 2 11834 #define mmDP3_DP_MSA_VBID_MISC 0x245a 11835 #define mmDP3_DP_MSA_VBID_MISC_BASE_IDX 2 11836 #define mmDP3_DP_SEC_METADATA_TRANSMISSION 0x245b 11837 #define mmDP3_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2 11838 #define mmDP3_DP_DSC_BYTES_PER_PIXEL 0x245c 11839 #define mmDP3_DP_DSC_BYTES_PER_PIXEL_BASE_IDX 2 11840 #define mmDP3_DP_ALPM_CNTL 0x245d 11841 #define mmDP3_DP_ALPM_CNTL_BASE_IDX 2 11842 #define mmDP3_DP_GSP8_CNTL 0x245e 11843 #define mmDP3_DP_GSP8_CNTL_BASE_IDX 2 11844 #define mmDP3_DP_GSP9_CNTL 0x245f 11845 #define mmDP3_DP_GSP9_CNTL_BASE_IDX 2 11846 #define mmDP3_DP_GSP10_CNTL 0x2460 11847 #define mmDP3_DP_GSP10_CNTL_BASE_IDX 2 11848 #define mmDP3_DP_GSP11_CNTL 0x2461 11849 #define mmDP3_DP_GSP11_CNTL_BASE_IDX 2 11850 #define mmDP3_DP_GSP_EN_DB_STATUS 0x2462 11851 #define mmDP3_DP_GSP_EN_DB_STATUS_BASE_IDX 2 11852 11853 11854 // addressBlock: dce_dc_dio_dig4_vpg_vpg_dispdec 11855 // base address: 0x164a0 11856 #define mmVPG4_VPG_GENERIC_PACKET_ACCESS_CTRL 0x2468 11857 #define mmVPG4_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 11858 #define mmVPG4_VPG_GENERIC_PACKET_DATA 0x2469 11859 #define mmVPG4_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 11860 #define mmVPG4_VPG_GSP_FRAME_UPDATE_CTRL 0x246a 11861 #define mmVPG4_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 11862 #define mmVPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x246b 11863 #define mmVPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 11864 #define mmVPG4_VPG_GENERIC_STATUS 0x246c 11865 #define mmVPG4_VPG_GENERIC_STATUS_BASE_IDX 2 11866 #define mmVPG4_VPG_MEM_PWR 0x246d 11867 #define mmVPG4_VPG_MEM_PWR_BASE_IDX 2 11868 #define mmVPG4_VPG_ISRC1_2_ACCESS_CTRL 0x246e 11869 #define mmVPG4_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 11870 #define mmVPG4_VPG_ISRC1_2_DATA 0x246f 11871 #define mmVPG4_VPG_ISRC1_2_DATA_BASE_IDX 2 11872 #define mmVPG4_VPG_MPEG_INFO0 0x2470 11873 #define mmVPG4_VPG_MPEG_INFO0_BASE_IDX 2 11874 #define mmVPG4_VPG_MPEG_INFO1 0x2471 11875 #define mmVPG4_VPG_MPEG_INFO1_BASE_IDX 2 11876 11877 11878 // addressBlock: dce_dc_dio_dig4_afmt_afmt_dispdec 11879 #define mmAFMT4_AFMT_VBI_PACKET_CONTROL 0x2474 11880 #define mmAFMT4_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 11881 #define mmAFMT4_AFMT_AUDIO_PACKET_CONTROL2 0x2475 11882 #define mmAFMT4_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 11883 #define mmAFMT4_AFMT_AUDIO_INFO0 0x2476 11884 #define mmAFMT4_AFMT_AUDIO_INFO0_BASE_IDX 2 11885 #define mmAFMT4_AFMT_AUDIO_INFO1 0x2477 11886 #define mmAFMT4_AFMT_AUDIO_INFO1_BASE_IDX 2 11887 #define mmAFMT4_AFMT_60958_0 0x2478 11888 #define mmAFMT4_AFMT_60958_0_BASE_IDX 2 11889 #define mmAFMT4_AFMT_60958_1 0x2479 11890 #define mmAFMT4_AFMT_60958_1_BASE_IDX 2 11891 #define mmAFMT4_AFMT_AUDIO_CRC_CONTROL 0x247a 11892 #define mmAFMT4_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 11893 #define mmAFMT4_AFMT_RAMP_CONTROL0 0x247b 11894 #define mmAFMT4_AFMT_RAMP_CONTROL0_BASE_IDX 2 11895 #define mmAFMT4_AFMT_RAMP_CONTROL1 0x247c 11896 #define mmAFMT4_AFMT_RAMP_CONTROL1_BASE_IDX 2 11897 #define mmAFMT4_AFMT_RAMP_CONTROL2 0x247d 11898 #define mmAFMT4_AFMT_RAMP_CONTROL2_BASE_IDX 2 11899 #define mmAFMT4_AFMT_RAMP_CONTROL3 0x247e 11900 #define mmAFMT4_AFMT_RAMP_CONTROL3_BASE_IDX 2 11901 #define mmAFMT4_AFMT_60958_2 0x247f 11902 #define mmAFMT4_AFMT_60958_2_BASE_IDX 2 11903 #define mmAFMT4_AFMT_AUDIO_CRC_RESULT 0x2480 11904 #define mmAFMT4_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 11905 #define mmAFMT4_AFMT_STATUS 0x2481 11906 #define mmAFMT4_AFMT_STATUS_BASE_IDX 2 11907 #define mmAFMT4_AFMT_AUDIO_PACKET_CONTROL 0x2482 11908 #define mmAFMT4_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 11909 #define mmAFMT4_AFMT_INFOFRAME_CONTROL0 0x2483 11910 #define mmAFMT4_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 11911 #define mmAFMT4_AFMT_INTERRUPT_STATUS 0x2484 11912 #define mmAFMT4_AFMT_INTERRUPT_STATUS_BASE_IDX 2 11913 #define mmAFMT4_AFMT_AUDIO_SRC_CONTROL 0x2485 11914 #define mmAFMT4_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 11915 #define mmAFMT4_AFMT_MEM_PWR 0x2487 11916 #define mmAFMT4_AFMT_MEM_PWR_BASE_IDX 2 11917 11918 11919 // addressBlock: dce_dc_dio_dig4_dme_dme_dispdec 11920 // base address: 0x16524 11921 #define mmDME4_DME_CONTROL 0x2489 11922 #define mmDME4_DME_CONTROL_BASE_IDX 2 11923 #define mmDME4_DME_MEMORY_CONTROL 0x248a 11924 #define mmDME4_DME_MEMORY_CONTROL_BASE_IDX 2 11925 11926 11927 // addressBlock: dce_dc_dio_dig4_dispdec 11928 // base address: 0x1000 11929 #define mmDIG4_DIG_FE_CNTL 0x248b 11930 #define mmDIG4_DIG_FE_CNTL_BASE_IDX 2 11931 #define mmDIG4_DIG_OUTPUT_CRC_CNTL 0x248c 11932 #define mmDIG4_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 11933 #define mmDIG4_DIG_OUTPUT_CRC_RESULT 0x248d 11934 #define mmDIG4_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 11935 #define mmDIG4_DIG_CLOCK_PATTERN 0x248e 11936 #define mmDIG4_DIG_CLOCK_PATTERN_BASE_IDX 2 11937 #define mmDIG4_DIG_TEST_PATTERN 0x248f 11938 #define mmDIG4_DIG_TEST_PATTERN_BASE_IDX 2 11939 #define mmDIG4_DIG_RANDOM_PATTERN_SEED 0x2490 11940 #define mmDIG4_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 11941 #define mmDIG4_DIG_FIFO_STATUS 0x2491 11942 #define mmDIG4_DIG_FIFO_STATUS_BASE_IDX 2 11943 #define mmDIG4_HDMI_METADATA_PACKET_CONTROL 0x2492 11944 #define mmDIG4_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2 11945 #define mmDIG4_HDMI_CONTROL 0x2493 11946 #define mmDIG4_HDMI_CONTROL_BASE_IDX 2 11947 #define mmDIG4_HDMI_STATUS 0x2494 11948 #define mmDIG4_HDMI_STATUS_BASE_IDX 2 11949 #define mmDIG4_HDMI_AUDIO_PACKET_CONTROL 0x2495 11950 #define mmDIG4_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 11951 #define mmDIG4_HDMI_ACR_PACKET_CONTROL 0x2496 11952 #define mmDIG4_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 11953 #define mmDIG4_HDMI_VBI_PACKET_CONTROL 0x2497 11954 #define mmDIG4_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 11955 #define mmDIG4_HDMI_INFOFRAME_CONTROL0 0x2498 11956 #define mmDIG4_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 11957 #define mmDIG4_HDMI_INFOFRAME_CONTROL1 0x2499 11958 #define mmDIG4_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 11959 #define mmDIG4_HDMI_GENERIC_PACKET_CONTROL0 0x249a 11960 #define mmDIG4_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 11961 #define mmDIG4_HDMI_GENERIC_PACKET_CONTROL6 0x249b 11962 #define mmDIG4_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX 2 11963 #define mmDIG4_HDMI_GENERIC_PACKET_CONTROL5 0x249c 11964 #define mmDIG4_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2 11965 #define mmDIG4_HDMI_GC 0x249d 11966 #define mmDIG4_HDMI_GC_BASE_IDX 2 11967 #define mmDIG4_HDMI_GENERIC_PACKET_CONTROL1 0x249e 11968 #define mmDIG4_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 11969 #define mmDIG4_HDMI_GENERIC_PACKET_CONTROL2 0x249f 11970 #define mmDIG4_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 11971 #define mmDIG4_HDMI_GENERIC_PACKET_CONTROL3 0x24a0 11972 #define mmDIG4_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 11973 #define mmDIG4_HDMI_GENERIC_PACKET_CONTROL4 0x24a1 11974 #define mmDIG4_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2 11975 #define mmDIG4_HDMI_GENERIC_PACKET_CONTROL7 0x24a2 11976 #define mmDIG4_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX 2 11977 #define mmDIG4_HDMI_GENERIC_PACKET_CONTROL8 0x24a3 11978 #define mmDIG4_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX 2 11979 #define mmDIG4_HDMI_GENERIC_PACKET_CONTROL9 0x24a4 11980 #define mmDIG4_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX 2 11981 #define mmDIG4_HDMI_GENERIC_PACKET_CONTROL10 0x24a5 11982 #define mmDIG4_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX 2 11983 #define mmDIG4_HDMI_DB_CONTROL 0x24a6 11984 #define mmDIG4_HDMI_DB_CONTROL_BASE_IDX 2 11985 #define mmDIG4_HDMI_ACR_32_0 0x24a7 11986 #define mmDIG4_HDMI_ACR_32_0_BASE_IDX 2 11987 #define mmDIG4_HDMI_ACR_32_1 0x24a8 11988 #define mmDIG4_HDMI_ACR_32_1_BASE_IDX 2 11989 #define mmDIG4_HDMI_ACR_44_0 0x24a9 11990 #define mmDIG4_HDMI_ACR_44_0_BASE_IDX 2 11991 #define mmDIG4_HDMI_ACR_44_1 0x24aa 11992 #define mmDIG4_HDMI_ACR_44_1_BASE_IDX 2 11993 #define mmDIG4_HDMI_ACR_48_0 0x24ab 11994 #define mmDIG4_HDMI_ACR_48_0_BASE_IDX 2 11995 #define mmDIG4_HDMI_ACR_48_1 0x24ac 11996 #define mmDIG4_HDMI_ACR_48_1_BASE_IDX 2 11997 #define mmDIG4_HDMI_ACR_STATUS_0 0x24ad 11998 #define mmDIG4_HDMI_ACR_STATUS_0_BASE_IDX 2 11999 #define mmDIG4_HDMI_ACR_STATUS_1 0x24ae 12000 #define mmDIG4_HDMI_ACR_STATUS_1_BASE_IDX 2 12001 #define mmDIG4_AFMT_CNTL 0x24af 12002 #define mmDIG4_AFMT_CNTL_BASE_IDX 2 12003 #define mmDIG4_DIG_BE_CNTL 0x24b0 12004 #define mmDIG4_DIG_BE_CNTL_BASE_IDX 2 12005 #define mmDIG4_DIG_BE_EN_CNTL 0x24b1 12006 #define mmDIG4_DIG_BE_EN_CNTL_BASE_IDX 2 12007 #define mmDIG4_TMDS_CNTL 0x24d7 12008 #define mmDIG4_TMDS_CNTL_BASE_IDX 2 12009 #define mmDIG4_TMDS_CONTROL_CHAR 0x24d8 12010 #define mmDIG4_TMDS_CONTROL_CHAR_BASE_IDX 2 12011 #define mmDIG4_TMDS_CONTROL0_FEEDBACK 0x24d9 12012 #define mmDIG4_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 12013 #define mmDIG4_TMDS_STEREOSYNC_CTL_SEL 0x24da 12014 #define mmDIG4_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 12015 #define mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1 0x24db 12016 #define mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 12017 #define mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3 0x24dc 12018 #define mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 12019 #define mmDIG4_TMDS_CTL_BITS 0x24de 12020 #define mmDIG4_TMDS_CTL_BITS_BASE_IDX 2 12021 #define mmDIG4_TMDS_DCBALANCER_CONTROL 0x24df 12022 #define mmDIG4_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 12023 #define mmDIG4_TMDS_SYNC_DCBALANCE_CHAR 0x24e0 12024 #define mmDIG4_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2 12025 #define mmDIG4_TMDS_CTL0_1_GEN_CNTL 0x24e1 12026 #define mmDIG4_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 12027 #define mmDIG4_TMDS_CTL2_3_GEN_CNTL 0x24e2 12028 #define mmDIG4_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 12029 #define mmDIG4_DIG_VERSION 0x24e4 12030 #define mmDIG4_DIG_VERSION_BASE_IDX 2 12031 #define mmDIG4_DIG_LANE_ENABLE 0x24e5 12032 #define mmDIG4_DIG_LANE_ENABLE_BASE_IDX 2 12033 #define mmDIG4_FORCE_DIG_DISABLE 0x24e6 12034 #define mmDIG4_FORCE_DIG_DISABLE_BASE_IDX 2 12035 12036 12037 // addressBlock: dce_dc_dio_dp4_dispdec 12038 // base address: 0x1000 12039 #define mmDP4_DP_LINK_CNTL 0x2508 12040 #define mmDP4_DP_LINK_CNTL_BASE_IDX 2 12041 #define mmDP4_DP_PIXEL_FORMAT 0x2509 12042 #define mmDP4_DP_PIXEL_FORMAT_BASE_IDX 2 12043 #define mmDP4_DP_MSA_COLORIMETRY 0x250a 12044 #define mmDP4_DP_MSA_COLORIMETRY_BASE_IDX 2 12045 #define mmDP4_DP_CONFIG 0x250b 12046 #define mmDP4_DP_CONFIG_BASE_IDX 2 12047 #define mmDP4_DP_VID_STREAM_CNTL 0x250c 12048 #define mmDP4_DP_VID_STREAM_CNTL_BASE_IDX 2 12049 #define mmDP4_DP_STEER_FIFO 0x250d 12050 #define mmDP4_DP_STEER_FIFO_BASE_IDX 2 12051 #define mmDP4_DP_MSA_MISC 0x250e 12052 #define mmDP4_DP_MSA_MISC_BASE_IDX 2 12053 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x250f 12054 #define mmDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 12055 #define mmDP4_DP_VID_TIMING 0x2510 12056 #define mmDP4_DP_VID_TIMING_BASE_IDX 2 12057 #define mmDP4_DP_VID_N 0x2511 12058 #define mmDP4_DP_VID_N_BASE_IDX 2 12059 #define mmDP4_DP_VID_M 0x2512 12060 #define mmDP4_DP_VID_M_BASE_IDX 2 12061 #define mmDP4_DP_LINK_FRAMING_CNTL 0x2513 12062 #define mmDP4_DP_LINK_FRAMING_CNTL_BASE_IDX 2 12063 #define mmDP4_DP_HBR2_EYE_PATTERN 0x2514 12064 #define mmDP4_DP_HBR2_EYE_PATTERN_BASE_IDX 2 12065 #define mmDP4_DP_VID_MSA_VBID 0x2515 12066 #define mmDP4_DP_VID_MSA_VBID_BASE_IDX 2 12067 #define mmDP4_DP_VID_INTERRUPT_CNTL 0x2516 12068 #define mmDP4_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 12069 #define mmDP4_DP_DPHY_CNTL 0x2517 12070 #define mmDP4_DP_DPHY_CNTL_BASE_IDX 2 12071 #define mmDP4_DP_DPHY_TRAINING_PATTERN_SEL 0x2518 12072 #define mmDP4_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 12073 #define mmDP4_DP_DPHY_SYM0 0x2519 12074 #define mmDP4_DP_DPHY_SYM0_BASE_IDX 2 12075 #define mmDP4_DP_DPHY_SYM1 0x251a 12076 #define mmDP4_DP_DPHY_SYM1_BASE_IDX 2 12077 #define mmDP4_DP_DPHY_SYM2 0x251b 12078 #define mmDP4_DP_DPHY_SYM2_BASE_IDX 2 12079 #define mmDP4_DP_DPHY_8B10B_CNTL 0x251c 12080 #define mmDP4_DP_DPHY_8B10B_CNTL_BASE_IDX 2 12081 #define mmDP4_DP_DPHY_PRBS_CNTL 0x251d 12082 #define mmDP4_DP_DPHY_PRBS_CNTL_BASE_IDX 2 12083 #define mmDP4_DP_DPHY_SCRAM_CNTL 0x251e 12084 #define mmDP4_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 12085 #define mmDP4_DP_DPHY_CRC_EN 0x251f 12086 #define mmDP4_DP_DPHY_CRC_EN_BASE_IDX 2 12087 #define mmDP4_DP_DPHY_CRC_CNTL 0x2520 12088 #define mmDP4_DP_DPHY_CRC_CNTL_BASE_IDX 2 12089 #define mmDP4_DP_DPHY_CRC_RESULT 0x2521 12090 #define mmDP4_DP_DPHY_CRC_RESULT_BASE_IDX 2 12091 #define mmDP4_DP_DPHY_CRC_MST_CNTL 0x2522 12092 #define mmDP4_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 12093 #define mmDP4_DP_DPHY_CRC_MST_STATUS 0x2523 12094 #define mmDP4_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 12095 #define mmDP4_DP_DPHY_FAST_TRAINING 0x2524 12096 #define mmDP4_DP_DPHY_FAST_TRAINING_BASE_IDX 2 12097 #define mmDP4_DP_DPHY_FAST_TRAINING_STATUS 0x2525 12098 #define mmDP4_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 12099 #define mmDP4_DP_SEC_CNTL 0x252b 12100 #define mmDP4_DP_SEC_CNTL_BASE_IDX 2 12101 #define mmDP4_DP_SEC_CNTL1 0x252c 12102 #define mmDP4_DP_SEC_CNTL1_BASE_IDX 2 12103 #define mmDP4_DP_SEC_FRAMING1 0x252d 12104 #define mmDP4_DP_SEC_FRAMING1_BASE_IDX 2 12105 #define mmDP4_DP_SEC_FRAMING2 0x252e 12106 #define mmDP4_DP_SEC_FRAMING2_BASE_IDX 2 12107 #define mmDP4_DP_SEC_FRAMING3 0x252f 12108 #define mmDP4_DP_SEC_FRAMING3_BASE_IDX 2 12109 #define mmDP4_DP_SEC_FRAMING4 0x2530 12110 #define mmDP4_DP_SEC_FRAMING4_BASE_IDX 2 12111 #define mmDP4_DP_SEC_AUD_N 0x2531 12112 #define mmDP4_DP_SEC_AUD_N_BASE_IDX 2 12113 #define mmDP4_DP_SEC_AUD_N_READBACK 0x2532 12114 #define mmDP4_DP_SEC_AUD_N_READBACK_BASE_IDX 2 12115 #define mmDP4_DP_SEC_AUD_M 0x2533 12116 #define mmDP4_DP_SEC_AUD_M_BASE_IDX 2 12117 #define mmDP4_DP_SEC_AUD_M_READBACK 0x2534 12118 #define mmDP4_DP_SEC_AUD_M_READBACK_BASE_IDX 2 12119 #define mmDP4_DP_SEC_TIMESTAMP 0x2535 12120 #define mmDP4_DP_SEC_TIMESTAMP_BASE_IDX 2 12121 #define mmDP4_DP_SEC_PACKET_CNTL 0x2536 12122 #define mmDP4_DP_SEC_PACKET_CNTL_BASE_IDX 2 12123 #define mmDP4_DP_MSE_RATE_CNTL 0x2537 12124 #define mmDP4_DP_MSE_RATE_CNTL_BASE_IDX 2 12125 #define mmDP4_DP_MSE_RATE_UPDATE 0x2539 12126 #define mmDP4_DP_MSE_RATE_UPDATE_BASE_IDX 2 12127 #define mmDP4_DP_MSE_SAT0 0x253a 12128 #define mmDP4_DP_MSE_SAT0_BASE_IDX 2 12129 #define mmDP4_DP_MSE_SAT1 0x253b 12130 #define mmDP4_DP_MSE_SAT1_BASE_IDX 2 12131 #define mmDP4_DP_MSE_SAT2 0x253c 12132 #define mmDP4_DP_MSE_SAT2_BASE_IDX 2 12133 #define mmDP4_DP_MSE_SAT_UPDATE 0x253d 12134 #define mmDP4_DP_MSE_SAT_UPDATE_BASE_IDX 2 12135 #define mmDP4_DP_MSE_LINK_TIMING 0x253e 12136 #define mmDP4_DP_MSE_LINK_TIMING_BASE_IDX 2 12137 #define mmDP4_DP_MSE_MISC_CNTL 0x253f 12138 #define mmDP4_DP_MSE_MISC_CNTL_BASE_IDX 2 12139 #define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL 0x2544 12140 #define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 12141 #define mmDP4_DP_DPHY_HBR2_PATTERN_CONTROL 0x2545 12142 #define mmDP4_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 12143 #define mmDP4_DP_MSE_SAT0_STATUS 0x2547 12144 #define mmDP4_DP_MSE_SAT0_STATUS_BASE_IDX 2 12145 #define mmDP4_DP_MSE_SAT1_STATUS 0x2548 12146 #define mmDP4_DP_MSE_SAT1_STATUS_BASE_IDX 2 12147 #define mmDP4_DP_MSE_SAT2_STATUS 0x2549 12148 #define mmDP4_DP_MSE_SAT2_STATUS_BASE_IDX 2 12149 #define mmDP4_DP_MSA_TIMING_PARAM1 0x254c 12150 #define mmDP4_DP_MSA_TIMING_PARAM1_BASE_IDX 2 12151 #define mmDP4_DP_MSA_TIMING_PARAM2 0x254d 12152 #define mmDP4_DP_MSA_TIMING_PARAM2_BASE_IDX 2 12153 #define mmDP4_DP_MSA_TIMING_PARAM3 0x254e 12154 #define mmDP4_DP_MSA_TIMING_PARAM3_BASE_IDX 2 12155 #define mmDP4_DP_MSA_TIMING_PARAM4 0x254f 12156 #define mmDP4_DP_MSA_TIMING_PARAM4_BASE_IDX 2 12157 #define mmDP4_DP_MSO_CNTL 0x2550 12158 #define mmDP4_DP_MSO_CNTL_BASE_IDX 2 12159 #define mmDP4_DP_MSO_CNTL1 0x2551 12160 #define mmDP4_DP_MSO_CNTL1_BASE_IDX 2 12161 #define mmDP4_DP_DSC_CNTL 0x2552 12162 #define mmDP4_DP_DSC_CNTL_BASE_IDX 2 12163 #define mmDP4_DP_SEC_CNTL2 0x2553 12164 #define mmDP4_DP_SEC_CNTL2_BASE_IDX 2 12165 #define mmDP4_DP_SEC_CNTL3 0x2554 12166 #define mmDP4_DP_SEC_CNTL3_BASE_IDX 2 12167 #define mmDP4_DP_SEC_CNTL4 0x2555 12168 #define mmDP4_DP_SEC_CNTL4_BASE_IDX 2 12169 #define mmDP4_DP_SEC_CNTL5 0x2556 12170 #define mmDP4_DP_SEC_CNTL5_BASE_IDX 2 12171 #define mmDP4_DP_SEC_CNTL6 0x2557 12172 #define mmDP4_DP_SEC_CNTL6_BASE_IDX 2 12173 #define mmDP4_DP_SEC_CNTL7 0x2558 12174 #define mmDP4_DP_SEC_CNTL7_BASE_IDX 2 12175 #define mmDP4_DP_DB_CNTL 0x2559 12176 #define mmDP4_DP_DB_CNTL_BASE_IDX 2 12177 #define mmDP4_DP_MSA_VBID_MISC 0x255a 12178 #define mmDP4_DP_MSA_VBID_MISC_BASE_IDX 2 12179 #define mmDP4_DP_SEC_METADATA_TRANSMISSION 0x255b 12180 #define mmDP4_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2 12181 #define mmDP4_DP_DSC_BYTES_PER_PIXEL 0x255c 12182 #define mmDP4_DP_DSC_BYTES_PER_PIXEL_BASE_IDX 2 12183 #define mmDP4_DP_ALPM_CNTL 0x255d 12184 #define mmDP4_DP_ALPM_CNTL_BASE_IDX 2 12185 #define mmDP4_DP_GSP8_CNTL 0x255e 12186 #define mmDP4_DP_GSP8_CNTL_BASE_IDX 2 12187 #define mmDP4_DP_GSP9_CNTL 0x255f 12188 #define mmDP4_DP_GSP9_CNTL_BASE_IDX 2 12189 #define mmDP4_DP_GSP10_CNTL 0x2560 12190 #define mmDP4_DP_GSP10_CNTL_BASE_IDX 2 12191 #define mmDP4_DP_GSP11_CNTL 0x2561 12192 #define mmDP4_DP_GSP11_CNTL_BASE_IDX 2 12193 #define mmDP4_DP_GSP_EN_DB_STATUS 0x2562 12194 #define mmDP4_DP_GSP_EN_DB_STATUS_BASE_IDX 2 12195 12196 12197 // addressBlock: dce_dc_dio_dig5_vpg_vpg_dispdec 12198 // base address: 0x168a0 12199 #define mmVPG5_VPG_GENERIC_PACKET_ACCESS_CTRL 0x2568 12200 #define mmVPG5_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 12201 #define mmVPG5_VPG_GENERIC_PACKET_DATA 0x2569 12202 #define mmVPG5_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 12203 #define mmVPG5_VPG_GSP_FRAME_UPDATE_CTRL 0x256a 12204 #define mmVPG5_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 12205 #define mmVPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x256b 12206 #define mmVPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 12207 #define mmVPG5_VPG_GENERIC_STATUS 0x256c 12208 #define mmVPG5_VPG_GENERIC_STATUS_BASE_IDX 2 12209 #define mmVPG5_VPG_MEM_PWR 0x256d 12210 #define mmVPG5_VPG_MEM_PWR_BASE_IDX 2 12211 #define mmVPG5_VPG_ISRC1_2_ACCESS_CTRL 0x256e 12212 #define mmVPG5_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 12213 #define mmVPG5_VPG_ISRC1_2_DATA 0x256f 12214 #define mmVPG5_VPG_ISRC1_2_DATA_BASE_IDX 2 12215 #define mmVPG5_VPG_MPEG_INFO0 0x2570 12216 #define mmVPG5_VPG_MPEG_INFO0_BASE_IDX 2 12217 #define mmVPG5_VPG_MPEG_INFO1 0x2571 12218 #define mmVPG5_VPG_MPEG_INFO1_BASE_IDX 2 12219 12220 12221 // addressBlock: dce_dc_dio_dig5_afmt_afmt_dispdec 12222 // base address: 0x168cc 12223 #define mmAFMT5_AFMT_VBI_PACKET_CONTROL 0x2574 12224 #define mmAFMT5_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 12225 #define mmAFMT5_AFMT_AUDIO_PACKET_CONTROL2 0x2575 12226 #define mmAFMT5_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 12227 #define mmAFMT5_AFMT_AUDIO_INFO0 0x2576 12228 #define mmAFMT5_AFMT_AUDIO_INFO0_BASE_IDX 2 12229 #define mmAFMT5_AFMT_AUDIO_INFO1 0x2577 12230 #define mmAFMT5_AFMT_AUDIO_INFO1_BASE_IDX 2 12231 #define mmAFMT5_AFMT_60958_0 0x2578 12232 #define mmAFMT5_AFMT_60958_0_BASE_IDX 2 12233 #define mmAFMT5_AFMT_60958_1 0x2579 12234 #define mmAFMT5_AFMT_60958_1_BASE_IDX 2 12235 #define mmAFMT5_AFMT_AUDIO_CRC_CONTROL 0x257a 12236 #define mmAFMT5_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 12237 #define mmAFMT5_AFMT_RAMP_CONTROL0 0x257b 12238 #define mmAFMT5_AFMT_RAMP_CONTROL0_BASE_IDX 2 12239 #define mmAFMT5_AFMT_RAMP_CONTROL1 0x257c 12240 #define mmAFMT5_AFMT_RAMP_CONTROL1_BASE_IDX 2 12241 #define mmAFMT5_AFMT_RAMP_CONTROL2 0x257d 12242 #define mmAFMT5_AFMT_RAMP_CONTROL2_BASE_IDX 2 12243 #define mmAFMT5_AFMT_RAMP_CONTROL3 0x257e 12244 #define mmAFMT5_AFMT_RAMP_CONTROL3_BASE_IDX 2 12245 #define mmAFMT5_AFMT_60958_2 0x257f 12246 #define mmAFMT5_AFMT_60958_2_BASE_IDX 2 12247 #define mmAFMT5_AFMT_AUDIO_CRC_RESULT 0x2580 12248 #define mmAFMT5_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 12249 #define mmAFMT5_AFMT_STATUS 0x2581 12250 #define mmAFMT5_AFMT_STATUS_BASE_IDX 2 12251 #define mmAFMT5_AFMT_AUDIO_PACKET_CONTROL 0x2582 12252 #define mmAFMT5_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 12253 #define mmAFMT5_AFMT_INFOFRAME_CONTROL0 0x2583 12254 #define mmAFMT5_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 12255 #define mmAFMT5_AFMT_INTERRUPT_STATUS 0x2584 12256 #define mmAFMT5_AFMT_INTERRUPT_STATUS_BASE_IDX 2 12257 #define mmAFMT5_AFMT_AUDIO_SRC_CONTROL 0x2585 12258 #define mmAFMT5_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 12259 #define mmAFMT5_AFMT_MEM_PWR 0x2587 12260 #define mmAFMT5_AFMT_MEM_PWR_BASE_IDX 2 12261 12262 12263 // addressBlock: dce_dc_dio_dig5_dme_dme_dispdec 12264 // base address: 0x16924 12265 #define mmDME5_DME_CONTROL 0x2589 12266 #define mmDME5_DME_CONTROL_BASE_IDX 2 12267 #define mmDME5_DME_MEMORY_CONTROL 0x258a 12268 #define mmDME5_DME_MEMORY_CONTROL_BASE_IDX 2 12269 12270 12271 // addressBlock: dce_dc_dio_dig5_dispdec 12272 // base address: 0x1400 12273 #define mmDIG5_DIG_FE_CNTL 0x258b 12274 #define mmDIG5_DIG_FE_CNTL_BASE_IDX 2 12275 #define mmDIG5_DIG_OUTPUT_CRC_CNTL 0x258c 12276 #define mmDIG5_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 12277 #define mmDIG5_DIG_OUTPUT_CRC_RESULT 0x258d 12278 #define mmDIG5_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 12279 #define mmDIG5_DIG_CLOCK_PATTERN 0x258e 12280 #define mmDIG5_DIG_CLOCK_PATTERN_BASE_IDX 2 12281 #define mmDIG5_DIG_TEST_PATTERN 0x258f 12282 #define mmDIG5_DIG_TEST_PATTERN_BASE_IDX 2 12283 #define mmDIG5_DIG_RANDOM_PATTERN_SEED 0x2590 12284 #define mmDIG5_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 12285 #define mmDIG5_DIG_FIFO_STATUS 0x2591 12286 #define mmDIG5_DIG_FIFO_STATUS_BASE_IDX 2 12287 #define mmDIG5_HDMI_METADATA_PACKET_CONTROL 0x2592 12288 #define mmDIG5_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2 12289 #define mmDIG5_HDMI_CONTROL 0x2593 12290 #define mmDIG5_HDMI_CONTROL_BASE_IDX 2 12291 #define mmDIG5_HDMI_STATUS 0x2594 12292 #define mmDIG5_HDMI_STATUS_BASE_IDX 2 12293 #define mmDIG5_HDMI_AUDIO_PACKET_CONTROL 0x2595 12294 #define mmDIG5_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 12295 #define mmDIG5_HDMI_ACR_PACKET_CONTROL 0x2596 12296 #define mmDIG5_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 12297 #define mmDIG5_HDMI_VBI_PACKET_CONTROL 0x2597 12298 #define mmDIG5_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 12299 #define mmDIG5_HDMI_INFOFRAME_CONTROL0 0x2598 12300 #define mmDIG5_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 12301 #define mmDIG5_HDMI_INFOFRAME_CONTROL1 0x2599 12302 #define mmDIG5_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 12303 #define mmDIG5_HDMI_GENERIC_PACKET_CONTROL0 0x259a 12304 #define mmDIG5_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 12305 #define mmDIG5_HDMI_GENERIC_PACKET_CONTROL6 0x259b 12306 #define mmDIG5_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX 2 12307 #define mmDIG5_HDMI_GENERIC_PACKET_CONTROL5 0x259c 12308 #define mmDIG5_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2 12309 #define mmDIG5_HDMI_GC 0x259d 12310 #define mmDIG5_HDMI_GC_BASE_IDX 2 12311 #define mmDIG5_HDMI_GENERIC_PACKET_CONTROL1 0x259e 12312 #define mmDIG5_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 12313 #define mmDIG5_HDMI_GENERIC_PACKET_CONTROL2 0x259f 12314 #define mmDIG5_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 12315 #define mmDIG5_HDMI_GENERIC_PACKET_CONTROL3 0x25a0 12316 #define mmDIG5_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 12317 #define mmDIG5_HDMI_GENERIC_PACKET_CONTROL4 0x25a1 12318 #define mmDIG5_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2 12319 #define mmDIG5_HDMI_GENERIC_PACKET_CONTROL7 0x25a2 12320 #define mmDIG5_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX 2 12321 #define mmDIG5_HDMI_GENERIC_PACKET_CONTROL8 0x25a3 12322 #define mmDIG5_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX 2 12323 #define mmDIG5_HDMI_GENERIC_PACKET_CONTROL9 0x25a4 12324 #define mmDIG5_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX 2 12325 #define mmDIG5_HDMI_GENERIC_PACKET_CONTROL10 0x25a5 12326 #define mmDIG5_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX 2 12327 #define mmDIG5_HDMI_DB_CONTROL 0x25a6 12328 #define mmDIG5_HDMI_DB_CONTROL_BASE_IDX 2 12329 #define mmDIG5_HDMI_ACR_32_0 0x25a7 12330 #define mmDIG5_HDMI_ACR_32_0_BASE_IDX 2 12331 #define mmDIG5_HDMI_ACR_32_1 0x25a8 12332 #define mmDIG5_HDMI_ACR_32_1_BASE_IDX 2 12333 #define mmDIG5_HDMI_ACR_44_0 0x25a9 12334 #define mmDIG5_HDMI_ACR_44_0_BASE_IDX 2 12335 #define mmDIG5_HDMI_ACR_44_1 0x25aa 12336 #define mmDIG5_HDMI_ACR_44_1_BASE_IDX 2 12337 #define mmDIG5_HDMI_ACR_48_0 0x25ab 12338 #define mmDIG5_HDMI_ACR_48_0_BASE_IDX 2 12339 #define mmDIG5_HDMI_ACR_48_1 0x25ac 12340 #define mmDIG5_HDMI_ACR_48_1_BASE_IDX 2 12341 #define mmDIG5_HDMI_ACR_STATUS_0 0x25ad 12342 #define mmDIG5_HDMI_ACR_STATUS_0_BASE_IDX 2 12343 #define mmDIG5_HDMI_ACR_STATUS_1 0x25ae 12344 #define mmDIG5_HDMI_ACR_STATUS_1_BASE_IDX 2 12345 #define mmDIG5_AFMT_CNTL 0x25af 12346 #define mmDIG5_AFMT_CNTL_BASE_IDX 2 12347 #define mmDIG5_DIG_BE_CNTL 0x25b0 12348 #define mmDIG5_DIG_BE_CNTL_BASE_IDX 2 12349 #define mmDIG5_DIG_BE_EN_CNTL 0x25b1 12350 #define mmDIG5_DIG_BE_EN_CNTL_BASE_IDX 2 12351 12352 #define mmDIG5_TMDS_CNTL 0x25d7 12353 #define mmDIG5_TMDS_CNTL_BASE_IDX 2 12354 #define mmDIG5_TMDS_CONTROL_CHAR 0x25d8 12355 #define mmDIG5_TMDS_CONTROL_CHAR_BASE_IDX 2 12356 #define mmDIG5_TMDS_CONTROL0_FEEDBACK 0x25d9 12357 #define mmDIG5_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 12358 #define mmDIG5_TMDS_STEREOSYNC_CTL_SEL 0x25da 12359 #define mmDIG5_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 12360 #define mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1 0x25db 12361 #define mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 12362 #define mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3 0x25dc 12363 #define mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 12364 #define mmDIG5_TMDS_CTL_BITS 0x25de 12365 #define mmDIG5_TMDS_CTL_BITS_BASE_IDX 2 12366 #define mmDIG5_TMDS_DCBALANCER_CONTROL 0x25df 12367 #define mmDIG5_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 12368 #define mmDIG5_TMDS_SYNC_DCBALANCE_CHAR 0x25e0 12369 #define mmDIG5_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2 12370 #define mmDIG5_TMDS_CTL0_1_GEN_CNTL 0x25e1 12371 #define mmDIG5_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 12372 #define mmDIG5_TMDS_CTL2_3_GEN_CNTL 0x25e2 12373 #define mmDIG5_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 12374 #define mmDIG5_DIG_VERSION 0x25e4 12375 #define mmDIG5_DIG_VERSION_BASE_IDX 2 12376 #define mmDIG5_DIG_LANE_ENABLE 0x25e5 12377 #define mmDIG5_DIG_LANE_ENABLE_BASE_IDX 2 12378 #define mmDIG5_FORCE_DIG_DISABLE 0x25e6 12379 #define mmDIG5_FORCE_DIG_DISABLE_BASE_IDX 2 12380 12381 // addressBlock: dce_dc_dio_dp5_dispdec 12382 // base address: 0x1400 12383 #define mmDP5_DP_LINK_CNTL 0x2608 12384 #define mmDP5_DP_LINK_CNTL_BASE_IDX 2 12385 #define mmDP5_DP_PIXEL_FORMAT 0x2609 12386 #define mmDP5_DP_PIXEL_FORMAT_BASE_IDX 2 12387 #define mmDP5_DP_MSA_COLORIMETRY 0x260a 12388 #define mmDP5_DP_MSA_COLORIMETRY_BASE_IDX 2 12389 #define mmDP5_DP_CONFIG 0x260b 12390 #define mmDP5_DP_CONFIG_BASE_IDX 2 12391 #define mmDP5_DP_VID_STREAM_CNTL 0x260c 12392 #define mmDP5_DP_VID_STREAM_CNTL_BASE_IDX 2 12393 #define mmDP5_DP_STEER_FIFO 0x260d 12394 #define mmDP5_DP_STEER_FIFO_BASE_IDX 2 12395 #define mmDP5_DP_MSA_MISC 0x260e 12396 #define mmDP5_DP_MSA_MISC_BASE_IDX 2 12397 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x260f 12398 #define mmDP5_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 12399 #define mmDP5_DP_VID_TIMING 0x2610 12400 #define mmDP5_DP_VID_TIMING_BASE_IDX 2 12401 #define mmDP5_DP_VID_N 0x2611 12402 #define mmDP5_DP_VID_N_BASE_IDX 2 12403 #define mmDP5_DP_VID_M 0x2612 12404 #define mmDP5_DP_VID_M_BASE_IDX 2 12405 #define mmDP5_DP_LINK_FRAMING_CNTL 0x2613 12406 #define mmDP5_DP_LINK_FRAMING_CNTL_BASE_IDX 2 12407 #define mmDP5_DP_HBR2_EYE_PATTERN 0x2614 12408 #define mmDP5_DP_HBR2_EYE_PATTERN_BASE_IDX 2 12409 #define mmDP5_DP_VID_MSA_VBID 0x2615 12410 #define mmDP5_DP_VID_MSA_VBID_BASE_IDX 2 12411 #define mmDP5_DP_VID_INTERRUPT_CNTL 0x2616 12412 #define mmDP5_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 12413 #define mmDP5_DP_DPHY_CNTL 0x2617 12414 #define mmDP5_DP_DPHY_CNTL_BASE_IDX 2 12415 #define mmDP5_DP_DPHY_TRAINING_PATTERN_SEL 0x2618 12416 #define mmDP5_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 12417 #define mmDP5_DP_DPHY_SYM0 0x2619 12418 #define mmDP5_DP_DPHY_SYM0_BASE_IDX 2 12419 #define mmDP5_DP_DPHY_SYM1 0x261a 12420 #define mmDP5_DP_DPHY_SYM1_BASE_IDX 2 12421 #define mmDP5_DP_DPHY_SYM2 0x261b 12422 #define mmDP5_DP_DPHY_SYM2_BASE_IDX 2 12423 #define mmDP5_DP_DPHY_8B10B_CNTL 0x261c 12424 #define mmDP5_DP_DPHY_8B10B_CNTL_BASE_IDX 2 12425 #define mmDP5_DP_DPHY_PRBS_CNTL 0x261d 12426 #define mmDP5_DP_DPHY_PRBS_CNTL_BASE_IDX 2 12427 #define mmDP5_DP_DPHY_SCRAM_CNTL 0x261e 12428 #define mmDP5_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 12429 #define mmDP5_DP_DPHY_CRC_EN 0x261f 12430 #define mmDP5_DP_DPHY_CRC_EN_BASE_IDX 2 12431 #define mmDP5_DP_DPHY_CRC_CNTL 0x2620 12432 #define mmDP5_DP_DPHY_CRC_CNTL_BASE_IDX 2 12433 #define mmDP5_DP_DPHY_CRC_RESULT 0x2621 12434 #define mmDP5_DP_DPHY_CRC_RESULT_BASE_IDX 2 12435 #define mmDP5_DP_DPHY_CRC_MST_CNTL 0x2622 12436 #define mmDP5_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 12437 #define mmDP5_DP_DPHY_CRC_MST_STATUS 0x2623 12438 #define mmDP5_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 12439 #define mmDP5_DP_DPHY_FAST_TRAINING 0x2624 12440 #define mmDP5_DP_DPHY_FAST_TRAINING_BASE_IDX 2 12441 #define mmDP5_DP_DPHY_FAST_TRAINING_STATUS 0x2625 12442 #define mmDP5_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 12443 #define mmDP5_DP_SEC_CNTL 0x262b 12444 #define mmDP5_DP_SEC_CNTL_BASE_IDX 2 12445 #define mmDP5_DP_SEC_CNTL1 0x262c 12446 #define mmDP5_DP_SEC_CNTL1_BASE_IDX 2 12447 #define mmDP5_DP_SEC_FRAMING1 0x262d 12448 #define mmDP5_DP_SEC_FRAMING1_BASE_IDX 2 12449 #define mmDP5_DP_SEC_FRAMING2 0x262e 12450 #define mmDP5_DP_SEC_FRAMING2_BASE_IDX 2 12451 #define mmDP5_DP_SEC_FRAMING3 0x262f 12452 #define mmDP5_DP_SEC_FRAMING3_BASE_IDX 2 12453 #define mmDP5_DP_SEC_FRAMING4 0x2630 12454 #define mmDP5_DP_SEC_FRAMING4_BASE_IDX 2 12455 #define mmDP5_DP_SEC_AUD_N 0x2631 12456 #define mmDP5_DP_SEC_AUD_N_BASE_IDX 2 12457 #define mmDP5_DP_SEC_AUD_N_READBACK 0x2632 12458 #define mmDP5_DP_SEC_AUD_N_READBACK_BASE_IDX 2 12459 #define mmDP5_DP_SEC_AUD_M 0x2633 12460 #define mmDP5_DP_SEC_AUD_M_BASE_IDX 2 12461 #define mmDP5_DP_SEC_AUD_M_READBACK 0x2634 12462 #define mmDP5_DP_SEC_AUD_M_READBACK_BASE_IDX 2 12463 #define mmDP5_DP_SEC_TIMESTAMP 0x2635 12464 #define mmDP5_DP_SEC_TIMESTAMP_BASE_IDX 2 12465 #define mmDP5_DP_SEC_PACKET_CNTL 0x2636 12466 #define mmDP5_DP_SEC_PACKET_CNTL_BASE_IDX 2 12467 #define mmDP5_DP_MSE_RATE_CNTL 0x2637 12468 #define mmDP5_DP_MSE_RATE_CNTL_BASE_IDX 2 12469 #define mmDP5_DP_MSE_RATE_UPDATE 0x2639 12470 #define mmDP5_DP_MSE_RATE_UPDATE_BASE_IDX 2 12471 #define mmDP5_DP_MSE_SAT0 0x263a 12472 #define mmDP5_DP_MSE_SAT0_BASE_IDX 2 12473 #define mmDP5_DP_MSE_SAT1 0x263b 12474 #define mmDP5_DP_MSE_SAT1_BASE_IDX 2 12475 #define mmDP5_DP_MSE_SAT2 0x263c 12476 #define mmDP5_DP_MSE_SAT2_BASE_IDX 2 12477 #define mmDP5_DP_MSE_SAT_UPDATE 0x263d 12478 #define mmDP5_DP_MSE_SAT_UPDATE_BASE_IDX 2 12479 #define mmDP5_DP_MSE_LINK_TIMING 0x263e 12480 #define mmDP5_DP_MSE_LINK_TIMING_BASE_IDX 2 12481 #define mmDP5_DP_MSE_MISC_CNTL 0x263f 12482 #define mmDP5_DP_MSE_MISC_CNTL_BASE_IDX 2 12483 #define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL 0x2644 12484 #define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 12485 #define mmDP5_DP_DPHY_HBR2_PATTERN_CONTROL 0x2645 12486 #define mmDP5_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 12487 #define mmDP5_DP_MSE_SAT0_STATUS 0x2647 12488 #define mmDP5_DP_MSE_SAT0_STATUS_BASE_IDX 2 12489 #define mmDP5_DP_MSE_SAT1_STATUS 0x2648 12490 #define mmDP5_DP_MSE_SAT1_STATUS_BASE_IDX 2 12491 #define mmDP5_DP_MSE_SAT2_STATUS 0x2649 12492 #define mmDP5_DP_MSE_SAT2_STATUS_BASE_IDX 2 12493 #define mmDP5_DP_MSA_TIMING_PARAM1 0x264c 12494 #define mmDP5_DP_MSA_TIMING_PARAM1_BASE_IDX 2 12495 #define mmDP5_DP_MSA_TIMING_PARAM2 0x264d 12496 #define mmDP5_DP_MSA_TIMING_PARAM2_BASE_IDX 2 12497 #define mmDP5_DP_MSA_TIMING_PARAM3 0x264e 12498 #define mmDP5_DP_MSA_TIMING_PARAM3_BASE_IDX 2 12499 #define mmDP5_DP_MSA_TIMING_PARAM4 0x264f 12500 #define mmDP5_DP_MSA_TIMING_PARAM4_BASE_IDX 2 12501 #define mmDP5_DP_MSO_CNTL 0x2650 12502 #define mmDP5_DP_MSO_CNTL_BASE_IDX 2 12503 #define mmDP5_DP_MSO_CNTL1 0x2651 12504 #define mmDP5_DP_MSO_CNTL1_BASE_IDX 2 12505 #define mmDP5_DP_DSC_CNTL 0x2652 12506 #define mmDP5_DP_DSC_CNTL_BASE_IDX 2 12507 #define mmDP5_DP_SEC_CNTL2 0x2653 12508 #define mmDP5_DP_SEC_CNTL2_BASE_IDX 2 12509 #define mmDP5_DP_SEC_CNTL3 0x2654 12510 #define mmDP5_DP_SEC_CNTL3_BASE_IDX 2 12511 #define mmDP5_DP_SEC_CNTL4 0x2655 12512 #define mmDP5_DP_SEC_CNTL4_BASE_IDX 2 12513 #define mmDP5_DP_SEC_CNTL5 0x2656 12514 #define mmDP5_DP_SEC_CNTL5_BASE_IDX 2 12515 #define mmDP5_DP_SEC_CNTL6 0x2657 12516 #define mmDP5_DP_SEC_CNTL6_BASE_IDX 2 12517 #define mmDP5_DP_SEC_CNTL7 0x2658 12518 #define mmDP5_DP_SEC_CNTL7_BASE_IDX 2 12519 #define mmDP5_DP_DB_CNTL 0x2659 12520 #define mmDP5_DP_DB_CNTL_BASE_IDX 2 12521 #define mmDP5_DP_MSA_VBID_MISC 0x265a 12522 #define mmDP5_DP_MSA_VBID_MISC_BASE_IDX 2 12523 #define mmDP5_DP_SEC_METADATA_TRANSMISSION 0x265b 12524 #define mmDP5_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2 12525 #define mmDP5_DP_DSC_BYTES_PER_PIXEL 0x265c 12526 #define mmDP5_DP_DSC_BYTES_PER_PIXEL_BASE_IDX 2 12527 #define mmDP5_DP_ALPM_CNTL 0x265d 12528 #define mmDP5_DP_ALPM_CNTL_BASE_IDX 2 12529 #define mmDP5_DP_GSP8_CNTL 0x265e 12530 #define mmDP5_DP_GSP8_CNTL_BASE_IDX 2 12531 #define mmDP5_DP_GSP9_CNTL 0x265f 12532 #define mmDP5_DP_GSP9_CNTL_BASE_IDX 2 12533 #define mmDP5_DP_GSP10_CNTL 0x2660 12534 #define mmDP5_DP_GSP10_CNTL_BASE_IDX 2 12535 #define mmDP5_DP_GSP11_CNTL 0x2661 12536 #define mmDP5_DP_GSP11_CNTL_BASE_IDX 2 12537 #define mmDP5_DP_GSP_EN_DB_STATUS 0x2662 12538 #define mmDP5_DP_GSP_EN_DB_STATUS_BASE_IDX 2 12539 12540 12541 // addressBlock: dce_dc_dcio_dcio_dispdec 12542 // base address: 0x0 12543 #define mmDC_GENERICA 0x2868 12544 #define mmDC_GENERICA_BASE_IDX 2 12545 #define mmDC_GENERICB 0x2869 12546 #define mmDC_GENERICB_BASE_IDX 2 12547 #define mmDCIO_CLOCK_CNTL 0x286a 12548 #define mmDCIO_CLOCK_CNTL_BASE_IDX 2 12549 #define mmDC_REF_CLK_CNTL 0x286b 12550 #define mmDC_REF_CLK_CNTL_BASE_IDX 2 12551 #define mmUNIPHYA_LINK_CNTL 0x286d 12552 #define mmUNIPHYA_LINK_CNTL_BASE_IDX 2 12553 #define mmUNIPHYA_CHANNEL_XBAR_CNTL 0x286e 12554 #define mmUNIPHYA_CHANNEL_XBAR_CNTL_BASE_IDX 2 12555 #define mmUNIPHYB_LINK_CNTL 0x286f 12556 #define mmUNIPHYB_LINK_CNTL_BASE_IDX 2 12557 #define mmUNIPHYB_CHANNEL_XBAR_CNTL 0x2870 12558 #define mmUNIPHYB_CHANNEL_XBAR_CNTL_BASE_IDX 2 12559 #define mmUNIPHYC_LINK_CNTL 0x2871 12560 #define mmUNIPHYC_LINK_CNTL_BASE_IDX 2 12561 #define mmUNIPHYC_CHANNEL_XBAR_CNTL 0x2872 12562 #define mmUNIPHYC_CHANNEL_XBAR_CNTL_BASE_IDX 2 12563 #define mmUNIPHYD_LINK_CNTL 0x2873 12564 #define mmUNIPHYD_LINK_CNTL_BASE_IDX 2 12565 #define mmUNIPHYD_CHANNEL_XBAR_CNTL 0x2874 12566 #define mmUNIPHYD_CHANNEL_XBAR_CNTL_BASE_IDX 2 12567 #define mmUNIPHYE_LINK_CNTL 0x2875 12568 #define mmUNIPHYE_LINK_CNTL_BASE_IDX 2 12569 #define mmUNIPHYE_CHANNEL_XBAR_CNTL 0x2876 12570 #define mmUNIPHYE_CHANNEL_XBAR_CNTL_BASE_IDX 2 12571 #define mmUNIPHYF_LINK_CNTL 0x2877 12572 #define mmUNIPHYF_LINK_CNTL_BASE_IDX 2 12573 #define mmUNIPHYF_CHANNEL_XBAR_CNTL 0x2878 12574 #define mmUNIPHYF_CHANNEL_XBAR_CNTL_BASE_IDX 2 12575 #define mmDCIO_WRCMD_DELAY 0x287e 12576 #define mmDCIO_WRCMD_DELAY_BASE_IDX 2 12577 #define mmDC_PINSTRAPS 0x2880 12578 #define mmDC_PINSTRAPS_BASE_IDX 2 12579 #define mmLVTMA_PWRSEQ_CNTL 0x2883 12580 #define mmLVTMA_PWRSEQ_CNTL_BASE_IDX 2 12581 #define mmLVTMA_PWRSEQ_STATE 0x2884 12582 #define mmLVTMA_PWRSEQ_STATE_BASE_IDX 2 12583 #define mmLVTMA_PWRSEQ_REF_DIV 0x2885 12584 #define mmLVTMA_PWRSEQ_REF_DIV_BASE_IDX 2 12585 #define mmLVTMA_PWRSEQ_DELAY1 0x2886 12586 #define mmLVTMA_PWRSEQ_DELAY1_BASE_IDX 2 12587 #define mmLVTMA_PWRSEQ_DELAY2 0x2887 12588 #define mmLVTMA_PWRSEQ_DELAY2_BASE_IDX 2 12589 #define mmBL_PWM_CNTL 0x2888 12590 #define mmBL_PWM_CNTL_BASE_IDX 2 12591 #define mmBL_PWM_CNTL2 0x2889 12592 #define mmBL_PWM_CNTL2_BASE_IDX 2 12593 #define mmBL_PWM_PERIOD_CNTL 0x288a 12594 #define mmBL_PWM_PERIOD_CNTL_BASE_IDX 2 12595 #define mmBL_PWM_GRP1_REG_LOCK 0x288b 12596 #define mmBL_PWM_GRP1_REG_LOCK_BASE_IDX 2 12597 #define mmDCIO_GSL_GENLK_PAD_CNTL 0x288c 12598 #define mmDCIO_GSL_GENLK_PAD_CNTL_BASE_IDX 2 12599 #define mmDCIO_GSL_SWAPLOCK_PAD_CNTL 0x288d 12600 #define mmDCIO_GSL_SWAPLOCK_PAD_CNTL_BASE_IDX 2 12601 #define mmDCIO_SOFT_RESET 0x289e 12602 #define mmDCIO_SOFT_RESET_BASE_IDX 2 12603 12604 12605 // addressBlock: dce_dc_dcio_dcio_chip_dispdec 12606 // base address: 0x0 12607 #define mmDC_GPIO_GENERIC_MASK 0x28c8 12608 #define mmDC_GPIO_GENERIC_MASK_BASE_IDX 2 12609 #define mmDC_GPIO_GENERIC_A 0x28c9 12610 #define mmDC_GPIO_GENERIC_A_BASE_IDX 2 12611 #define mmDC_GPIO_GENERIC_EN 0x28ca 12612 #define mmDC_GPIO_GENERIC_EN_BASE_IDX 2 12613 #define mmDC_GPIO_GENERIC_Y 0x28cb 12614 #define mmDC_GPIO_GENERIC_Y_BASE_IDX 2 12615 #define mmDC_GPIO_DDC1_MASK 0x28d0 12616 #define mmDC_GPIO_DDC1_MASK_BASE_IDX 2 12617 #define mmDC_GPIO_DDC1_A 0x28d1 12618 #define mmDC_GPIO_DDC1_A_BASE_IDX 2 12619 #define mmDC_GPIO_DDC1_EN 0x28d2 12620 #define mmDC_GPIO_DDC1_EN_BASE_IDX 2 12621 #define mmDC_GPIO_DDC1_Y 0x28d3 12622 #define mmDC_GPIO_DDC1_Y_BASE_IDX 2 12623 #define mmDC_GPIO_DDC2_MASK 0x28d4 12624 #define mmDC_GPIO_DDC2_MASK_BASE_IDX 2 12625 #define mmDC_GPIO_DDC2_A 0x28d5 12626 #define mmDC_GPIO_DDC2_A_BASE_IDX 2 12627 #define mmDC_GPIO_DDC2_EN 0x28d6 12628 #define mmDC_GPIO_DDC2_EN_BASE_IDX 2 12629 #define mmDC_GPIO_DDC2_Y 0x28d7 12630 #define mmDC_GPIO_DDC2_Y_BASE_IDX 2 12631 #define mmDC_GPIO_DDC3_MASK 0x28d8 12632 #define mmDC_GPIO_DDC3_MASK_BASE_IDX 2 12633 #define mmDC_GPIO_DDC3_A 0x28d9 12634 #define mmDC_GPIO_DDC3_A_BASE_IDX 2 12635 #define mmDC_GPIO_DDC3_EN 0x28da 12636 #define mmDC_GPIO_DDC3_EN_BASE_IDX 2 12637 #define mmDC_GPIO_DDC3_Y 0x28db 12638 #define mmDC_GPIO_DDC3_Y_BASE_IDX 2 12639 #define mmDC_GPIO_DDC4_MASK 0x28dc 12640 #define mmDC_GPIO_DDC4_MASK_BASE_IDX 2 12641 #define mmDC_GPIO_DDC4_A 0x28dd 12642 #define mmDC_GPIO_DDC4_A_BASE_IDX 2 12643 #define mmDC_GPIO_DDC4_EN 0x28de 12644 #define mmDC_GPIO_DDC4_EN_BASE_IDX 2 12645 #define mmDC_GPIO_DDC4_Y 0x28df 12646 #define mmDC_GPIO_DDC4_Y_BASE_IDX 2 12647 #define mmDC_GPIO_DDC5_MASK 0x28e0 12648 #define mmDC_GPIO_DDC5_MASK_BASE_IDX 2 12649 #define mmDC_GPIO_DDC5_A 0x28e1 12650 #define mmDC_GPIO_DDC5_A_BASE_IDX 2 12651 #define mmDC_GPIO_DDC5_EN 0x28e2 12652 #define mmDC_GPIO_DDC5_EN_BASE_IDX 2 12653 #define mmDC_GPIO_DDC5_Y 0x28e3 12654 #define mmDC_GPIO_DDC5_Y_BASE_IDX 2 12655 #define mmDC_GPIO_DDC6_MASK 0x28e4 12656 #define mmDC_GPIO_DDC6_MASK_BASE_IDX 2 12657 #define mmDC_GPIO_DDC6_A 0x28e5 12658 #define mmDC_GPIO_DDC6_A_BASE_IDX 2 12659 #define mmDC_GPIO_DDC6_EN 0x28e6 12660 #define mmDC_GPIO_DDC6_EN_BASE_IDX 2 12661 #define mmDC_GPIO_DDC6_Y 0x28e7 12662 #define mmDC_GPIO_DDC6_Y_BASE_IDX 2 12663 #define mmDC_GPIO_DDCVGA_MASK 0x28e8 12664 #define mmDC_GPIO_DDCVGA_MASK_BASE_IDX 2 12665 #define mmDC_GPIO_DDCVGA_A 0x28e9 12666 #define mmDC_GPIO_DDCVGA_A_BASE_IDX 2 12667 #define mmDC_GPIO_DDCVGA_EN 0x28ea 12668 #define mmDC_GPIO_DDCVGA_EN_BASE_IDX 2 12669 #define mmDC_GPIO_DDCVGA_Y 0x28eb 12670 #define mmDC_GPIO_DDCVGA_Y_BASE_IDX 2 12671 #define mmDC_GPIO_GENLK_MASK 0x28f0 12672 #define mmDC_GPIO_GENLK_MASK_BASE_IDX 2 12673 #define mmDC_GPIO_GENLK_A 0x28f1 12674 #define mmDC_GPIO_GENLK_A_BASE_IDX 2 12675 #define mmDC_GPIO_GENLK_EN 0x28f2 12676 #define mmDC_GPIO_GENLK_EN_BASE_IDX 2 12677 #define mmDC_GPIO_GENLK_Y 0x28f3 12678 #define mmDC_GPIO_GENLK_Y_BASE_IDX 2 12679 #define mmDC_GPIO_HPD_MASK 0x28f4 12680 #define mmDC_GPIO_HPD_MASK_BASE_IDX 2 12681 #define mmDC_GPIO_HPD_A 0x28f5 12682 #define mmDC_GPIO_HPD_A_BASE_IDX 2 12683 #define mmDC_GPIO_HPD_EN 0x28f6 12684 #define mmDC_GPIO_HPD_EN_BASE_IDX 2 12685 #define mmDC_GPIO_HPD_Y 0x28f7 12686 #define mmDC_GPIO_HPD_Y_BASE_IDX 2 12687 #define mmDC_GPIO_PWRSEQ_MASK 0x28f8 12688 #define mmDC_GPIO_PWRSEQ_MASK_BASE_IDX 2 12689 #define mmDC_GPIO_PWRSEQ_A 0x28f9 12690 #define mmDC_GPIO_PWRSEQ_A_BASE_IDX 2 12691 #define mmDC_GPIO_PWRSEQ_EN 0x28fa 12692 #define mmDC_GPIO_PWRSEQ_EN_BASE_IDX 2 12693 #define mmDC_GPIO_PWRSEQ_Y 0x28fb 12694 #define mmDC_GPIO_PWRSEQ_Y_BASE_IDX 2 12695 #define mmDC_GPIO_PAD_STRENGTH_1 0x28fc 12696 #define mmDC_GPIO_PAD_STRENGTH_1_BASE_IDX 2 12697 #define mmDC_GPIO_PAD_STRENGTH_2 0x28fd 12698 #define mmDC_GPIO_PAD_STRENGTH_2_BASE_IDX 2 12699 #define mmPHY_AUX_CNTL 0x28ff 12700 #define mmPHY_AUX_CNTL_BASE_IDX 2 12701 #define mmDC_GPIO_TX12_EN 0x2915 12702 #define mmDC_GPIO_TX12_EN_BASE_IDX 2 12703 #define mmDC_GPIO_AUX_CTRL_0 0x2916 12704 #define mmDC_GPIO_AUX_CTRL_0_BASE_IDX 2 12705 #define mmDC_GPIO_AUX_CTRL_1 0x2917 12706 #define mmDC_GPIO_AUX_CTRL_1_BASE_IDX 2 12707 #define mmDC_GPIO_AUX_CTRL_2 0x2918 12708 #define mmDC_GPIO_AUX_CTRL_2_BASE_IDX 2 12709 #define mmDC_GPIO_RXEN 0x2919 12710 #define mmDC_GPIO_RXEN_BASE_IDX 2 12711 #define mmDC_GPIO_PULLUPEN 0x291a 12712 #define mmDC_GPIO_PULLUPEN_BASE_IDX 2 12713 #define mmDC_GPIO_AUX_CTRL_3 0x291b 12714 #define mmDC_GPIO_AUX_CTRL_3_BASE_IDX 2 12715 #define mmDC_GPIO_AUX_CTRL_4 0x291c 12716 #define mmDC_GPIO_AUX_CTRL_4_BASE_IDX 2 12717 #define mmDC_GPIO_AUX_CTRL_5 0x291d 12718 #define mmDC_GPIO_AUX_CTRL_5_BASE_IDX 2 12719 #define mmAUXI2C_PAD_ALL_PWR_OK 0x291e 12720 #define mmAUXI2C_PAD_ALL_PWR_OK_BASE_IDX 2 12721 12722 12723 12724 // addressBlock: dce_dc_dsc0_dispdec_dsc_top_dispdec 12725 // base address: 0x0 12726 #define mmDSC_TOP0_DSC_TOP_CONTROL 0x3000 12727 #define mmDSC_TOP0_DSC_TOP_CONTROL_BASE_IDX 2 12728 #define mmDSC_TOP0_DSC_DEBUG_CONTROL 0x3001 12729 #define mmDSC_TOP0_DSC_DEBUG_CONTROL_BASE_IDX 2 12730 12731 12732 // addressBlock: dce_dc_dsc0_dispdec_dsccif_dispdec 12733 // base address: 0x0 12734 #define mmDSCCIF0_DSCCIF_CONFIG0 0x3005 12735 #define mmDSCCIF0_DSCCIF_CONFIG0_BASE_IDX 2 12736 #define mmDSCCIF0_DSCCIF_CONFIG1 0x3006 12737 #define mmDSCCIF0_DSCCIF_CONFIG1_BASE_IDX 2 12738 12739 12740 // addressBlock: dce_dc_dsc0_dispdec_dscc_dispdec 12741 // base address: 0x0 12742 #define mmDSCC0_DSCC_CONFIG0 0x300a 12743 #define mmDSCC0_DSCC_CONFIG0_BASE_IDX 2 12744 #define mmDSCC0_DSCC_CONFIG1 0x300b 12745 #define mmDSCC0_DSCC_CONFIG1_BASE_IDX 2 12746 #define mmDSCC0_DSCC_STATUS 0x300c 12747 #define mmDSCC0_DSCC_STATUS_BASE_IDX 2 12748 #define mmDSCC0_DSCC_INTERRUPT_CONTROL_STATUS 0x300d 12749 #define mmDSCC0_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX 2 12750 #define mmDSCC0_DSCC_PPS_CONFIG0 0x300e 12751 #define mmDSCC0_DSCC_PPS_CONFIG0_BASE_IDX 2 12752 #define mmDSCC0_DSCC_PPS_CONFIG1 0x300f 12753 #define mmDSCC0_DSCC_PPS_CONFIG1_BASE_IDX 2 12754 #define mmDSCC0_DSCC_PPS_CONFIG2 0x3010 12755 #define mmDSCC0_DSCC_PPS_CONFIG2_BASE_IDX 2 12756 #define mmDSCC0_DSCC_PPS_CONFIG3 0x3011 12757 #define mmDSCC0_DSCC_PPS_CONFIG3_BASE_IDX 2 12758 #define mmDSCC0_DSCC_PPS_CONFIG4 0x3012 12759 #define mmDSCC0_DSCC_PPS_CONFIG4_BASE_IDX 2 12760 #define mmDSCC0_DSCC_PPS_CONFIG5 0x3013 12761 #define mmDSCC0_DSCC_PPS_CONFIG5_BASE_IDX 2 12762 #define mmDSCC0_DSCC_PPS_CONFIG6 0x3014 12763 #define mmDSCC0_DSCC_PPS_CONFIG6_BASE_IDX 2 12764 #define mmDSCC0_DSCC_PPS_CONFIG7 0x3015 12765 #define mmDSCC0_DSCC_PPS_CONFIG7_BASE_IDX 2 12766 #define mmDSCC0_DSCC_PPS_CONFIG8 0x3016 12767 #define mmDSCC0_DSCC_PPS_CONFIG8_BASE_IDX 2 12768 #define mmDSCC0_DSCC_PPS_CONFIG9 0x3017 12769 #define mmDSCC0_DSCC_PPS_CONFIG9_BASE_IDX 2 12770 #define mmDSCC0_DSCC_PPS_CONFIG10 0x3018 12771 #define mmDSCC0_DSCC_PPS_CONFIG10_BASE_IDX 2 12772 #define mmDSCC0_DSCC_PPS_CONFIG11 0x3019 12773 #define mmDSCC0_DSCC_PPS_CONFIG11_BASE_IDX 2 12774 #define mmDSCC0_DSCC_PPS_CONFIG12 0x301a 12775 #define mmDSCC0_DSCC_PPS_CONFIG12_BASE_IDX 2 12776 #define mmDSCC0_DSCC_PPS_CONFIG13 0x301b 12777 #define mmDSCC0_DSCC_PPS_CONFIG13_BASE_IDX 2 12778 #define mmDSCC0_DSCC_PPS_CONFIG14 0x301c 12779 #define mmDSCC0_DSCC_PPS_CONFIG14_BASE_IDX 2 12780 #define mmDSCC0_DSCC_PPS_CONFIG15 0x301d 12781 #define mmDSCC0_DSCC_PPS_CONFIG15_BASE_IDX 2 12782 #define mmDSCC0_DSCC_PPS_CONFIG16 0x301e 12783 #define mmDSCC0_DSCC_PPS_CONFIG16_BASE_IDX 2 12784 #define mmDSCC0_DSCC_PPS_CONFIG17 0x301f 12785 #define mmDSCC0_DSCC_PPS_CONFIG17_BASE_IDX 2 12786 #define mmDSCC0_DSCC_PPS_CONFIG18 0x3020 12787 #define mmDSCC0_DSCC_PPS_CONFIG18_BASE_IDX 2 12788 #define mmDSCC0_DSCC_PPS_CONFIG19 0x3021 12789 #define mmDSCC0_DSCC_PPS_CONFIG19_BASE_IDX 2 12790 #define mmDSCC0_DSCC_PPS_CONFIG20 0x3022 12791 #define mmDSCC0_DSCC_PPS_CONFIG20_BASE_IDX 2 12792 #define mmDSCC0_DSCC_PPS_CONFIG21 0x3023 12793 #define mmDSCC0_DSCC_PPS_CONFIG21_BASE_IDX 2 12794 #define mmDSCC0_DSCC_PPS_CONFIG22 0x3024 12795 #define mmDSCC0_DSCC_PPS_CONFIG22_BASE_IDX 2 12796 #define mmDSCC0_DSCC_MEM_POWER_CONTROL 0x3025 12797 #define mmDSCC0_DSCC_MEM_POWER_CONTROL_BASE_IDX 2 12798 #define mmDSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER 0x3026 12799 #define mmDSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2 12800 #define mmDSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER 0x3027 12801 #define mmDSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2 12802 #define mmDSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER 0x3028 12803 #define mmDSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2 12804 #define mmDSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER 0x3029 12805 #define mmDSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2 12806 #define mmDSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER 0x302a 12807 #define mmDSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2 12808 #define mmDSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER 0x302b 12809 #define mmDSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2 12810 #define mmDSCC0_DSCC_MAX_ABS_ERROR0 0x302c 12811 #define mmDSCC0_DSCC_MAX_ABS_ERROR0_BASE_IDX 2 12812 #define mmDSCC0_DSCC_MAX_ABS_ERROR1 0x302d 12813 #define mmDSCC0_DSCC_MAX_ABS_ERROR1_BASE_IDX 2 12814 #define mmDSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL 0x302e 12815 #define mmDSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 12816 #define mmDSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL 0x302f 12817 #define mmDSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 12818 #define mmDSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL 0x3030 12819 #define mmDSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 12820 #define mmDSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL 0x3031 12821 #define mmDSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 12822 #define mmDSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL 0x3032 12823 #define mmDSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 12824 #define mmDSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL 0x3033 12825 #define mmDSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 12826 #define mmDSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL 0x3034 12827 #define mmDSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 12828 #define mmDSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x3035 12829 #define mmDSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 12830 12831 12832 // addressBlock: dce_dc_dsc0_dispdec_dsc_dcperfmon_dc_perfmon_dispdec 12833 // base address: 0xc140 12834 #define mmDC_PERFMON21_PERFCOUNTER_CNTL 0x3050 12835 #define mmDC_PERFMON21_PERFCOUNTER_CNTL_BASE_IDX 2 12836 #define mmDC_PERFMON21_PERFCOUNTER_CNTL2 0x3051 12837 #define mmDC_PERFMON21_PERFCOUNTER_CNTL2_BASE_IDX 2 12838 #define mmDC_PERFMON21_PERFCOUNTER_STATE 0x3052 12839 #define mmDC_PERFMON21_PERFCOUNTER_STATE_BASE_IDX 2 12840 #define mmDC_PERFMON21_PERFMON_CNTL 0x3053 12841 #define mmDC_PERFMON21_PERFMON_CNTL_BASE_IDX 2 12842 #define mmDC_PERFMON21_PERFMON_CNTL2 0x3054 12843 #define mmDC_PERFMON21_PERFMON_CNTL2_BASE_IDX 2 12844 #define mmDC_PERFMON21_PERFMON_CVALUE_INT_MISC 0x3055 12845 #define mmDC_PERFMON21_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 12846 #define mmDC_PERFMON21_PERFMON_CVALUE_LOW 0x3056 12847 #define mmDC_PERFMON21_PERFMON_CVALUE_LOW_BASE_IDX 2 12848 #define mmDC_PERFMON21_PERFMON_HI 0x3057 12849 #define mmDC_PERFMON21_PERFMON_HI_BASE_IDX 2 12850 #define mmDC_PERFMON21_PERFMON_LOW 0x3058 12851 #define mmDC_PERFMON21_PERFMON_LOW_BASE_IDX 2 12852 12853 12854 // addressBlock: dce_dc_dsc1_dispdec_dsc_top_dispdec 12855 // base address: 0x170 12856 #define mmDSC_TOP1_DSC_TOP_CONTROL 0x305c 12857 #define mmDSC_TOP1_DSC_TOP_CONTROL_BASE_IDX 2 12858 #define mmDSC_TOP1_DSC_DEBUG_CONTROL 0x305d 12859 #define mmDSC_TOP1_DSC_DEBUG_CONTROL_BASE_IDX 2 12860 12861 12862 // addressBlock: dce_dc_dsc1_dispdec_dsccif_dispdec 12863 // base address: 0x170 12864 #define mmDSCCIF1_DSCCIF_CONFIG0 0x3061 12865 #define mmDSCCIF1_DSCCIF_CONFIG0_BASE_IDX 2 12866 #define mmDSCCIF1_DSCCIF_CONFIG1 0x3062 12867 #define mmDSCCIF1_DSCCIF_CONFIG1_BASE_IDX 2 12868 12869 12870 // addressBlock: dce_dc_dsc1_dispdec_dscc_dispdec 12871 // base address: 0x170 12872 #define mmDSCC1_DSCC_CONFIG0 0x3066 12873 #define mmDSCC1_DSCC_CONFIG0_BASE_IDX 2 12874 #define mmDSCC1_DSCC_CONFIG1 0x3067 12875 #define mmDSCC1_DSCC_CONFIG1_BASE_IDX 2 12876 #define mmDSCC1_DSCC_STATUS 0x3068 12877 #define mmDSCC1_DSCC_STATUS_BASE_IDX 2 12878 #define mmDSCC1_DSCC_INTERRUPT_CONTROL_STATUS 0x3069 12879 #define mmDSCC1_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX 2 12880 #define mmDSCC1_DSCC_PPS_CONFIG0 0x306a 12881 #define mmDSCC1_DSCC_PPS_CONFIG0_BASE_IDX 2 12882 #define mmDSCC1_DSCC_PPS_CONFIG1 0x306b 12883 #define mmDSCC1_DSCC_PPS_CONFIG1_BASE_IDX 2 12884 #define mmDSCC1_DSCC_PPS_CONFIG2 0x306c 12885 #define mmDSCC1_DSCC_PPS_CONFIG2_BASE_IDX 2 12886 #define mmDSCC1_DSCC_PPS_CONFIG3 0x306d 12887 #define mmDSCC1_DSCC_PPS_CONFIG3_BASE_IDX 2 12888 #define mmDSCC1_DSCC_PPS_CONFIG4 0x306e 12889 #define mmDSCC1_DSCC_PPS_CONFIG4_BASE_IDX 2 12890 #define mmDSCC1_DSCC_PPS_CONFIG5 0x306f 12891 #define mmDSCC1_DSCC_PPS_CONFIG5_BASE_IDX 2 12892 #define mmDSCC1_DSCC_PPS_CONFIG6 0x3070 12893 #define mmDSCC1_DSCC_PPS_CONFIG6_BASE_IDX 2 12894 #define mmDSCC1_DSCC_PPS_CONFIG7 0x3071 12895 #define mmDSCC1_DSCC_PPS_CONFIG7_BASE_IDX 2 12896 #define mmDSCC1_DSCC_PPS_CONFIG8 0x3072 12897 #define mmDSCC1_DSCC_PPS_CONFIG8_BASE_IDX 2 12898 #define mmDSCC1_DSCC_PPS_CONFIG9 0x3073 12899 #define mmDSCC1_DSCC_PPS_CONFIG9_BASE_IDX 2 12900 #define mmDSCC1_DSCC_PPS_CONFIG10 0x3074 12901 #define mmDSCC1_DSCC_PPS_CONFIG10_BASE_IDX 2 12902 #define mmDSCC1_DSCC_PPS_CONFIG11 0x3075 12903 #define mmDSCC1_DSCC_PPS_CONFIG11_BASE_IDX 2 12904 #define mmDSCC1_DSCC_PPS_CONFIG12 0x3076 12905 #define mmDSCC1_DSCC_PPS_CONFIG12_BASE_IDX 2 12906 #define mmDSCC1_DSCC_PPS_CONFIG13 0x3077 12907 #define mmDSCC1_DSCC_PPS_CONFIG13_BASE_IDX 2 12908 #define mmDSCC1_DSCC_PPS_CONFIG14 0x3078 12909 #define mmDSCC1_DSCC_PPS_CONFIG14_BASE_IDX 2 12910 #define mmDSCC1_DSCC_PPS_CONFIG15 0x3079 12911 #define mmDSCC1_DSCC_PPS_CONFIG15_BASE_IDX 2 12912 #define mmDSCC1_DSCC_PPS_CONFIG16 0x307a 12913 #define mmDSCC1_DSCC_PPS_CONFIG16_BASE_IDX 2 12914 #define mmDSCC1_DSCC_PPS_CONFIG17 0x307b 12915 #define mmDSCC1_DSCC_PPS_CONFIG17_BASE_IDX 2 12916 #define mmDSCC1_DSCC_PPS_CONFIG18 0x307c 12917 #define mmDSCC1_DSCC_PPS_CONFIG18_BASE_IDX 2 12918 #define mmDSCC1_DSCC_PPS_CONFIG19 0x307d 12919 #define mmDSCC1_DSCC_PPS_CONFIG19_BASE_IDX 2 12920 #define mmDSCC1_DSCC_PPS_CONFIG20 0x307e 12921 #define mmDSCC1_DSCC_PPS_CONFIG20_BASE_IDX 2 12922 #define mmDSCC1_DSCC_PPS_CONFIG21 0x307f 12923 #define mmDSCC1_DSCC_PPS_CONFIG21_BASE_IDX 2 12924 #define mmDSCC1_DSCC_PPS_CONFIG22 0x3080 12925 #define mmDSCC1_DSCC_PPS_CONFIG22_BASE_IDX 2 12926 #define mmDSCC1_DSCC_MEM_POWER_CONTROL 0x3081 12927 #define mmDSCC1_DSCC_MEM_POWER_CONTROL_BASE_IDX 2 12928 #define mmDSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER 0x3082 12929 #define mmDSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2 12930 #define mmDSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER 0x3083 12931 #define mmDSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2 12932 #define mmDSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER 0x3084 12933 #define mmDSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2 12934 #define mmDSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER 0x3085 12935 #define mmDSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2 12936 #define mmDSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER 0x3086 12937 #define mmDSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2 12938 #define mmDSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER 0x3087 12939 #define mmDSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2 12940 #define mmDSCC1_DSCC_MAX_ABS_ERROR0 0x3088 12941 #define mmDSCC1_DSCC_MAX_ABS_ERROR0_BASE_IDX 2 12942 #define mmDSCC1_DSCC_MAX_ABS_ERROR1 0x3089 12943 #define mmDSCC1_DSCC_MAX_ABS_ERROR1_BASE_IDX 2 12944 #define mmDSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL 0x308a 12945 #define mmDSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 12946 #define mmDSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL 0x308b 12947 #define mmDSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 12948 #define mmDSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL 0x308c 12949 #define mmDSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 12950 #define mmDSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL 0x308d 12951 #define mmDSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 12952 #define mmDSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL 0x308e 12953 #define mmDSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 12954 #define mmDSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL 0x308f 12955 #define mmDSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 12956 #define mmDSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL 0x3090 12957 #define mmDSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 12958 #define mmDSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x3091 12959 #define mmDSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 12960 12961 12962 // addressBlock: dce_dc_dsc1_dispdec_dsc_dcperfmon_dc_perfmon_dispdec 12963 // base address: 0xc2b0 12964 #define mmDC_PERFMON22_PERFCOUNTER_CNTL 0x30ac 12965 #define mmDC_PERFMON22_PERFCOUNTER_CNTL_BASE_IDX 2 12966 #define mmDC_PERFMON22_PERFCOUNTER_CNTL2 0x30ad 12967 #define mmDC_PERFMON22_PERFCOUNTER_CNTL2_BASE_IDX 2 12968 #define mmDC_PERFMON22_PERFCOUNTER_STATE 0x30ae 12969 #define mmDC_PERFMON22_PERFCOUNTER_STATE_BASE_IDX 2 12970 #define mmDC_PERFMON22_PERFMON_CNTL 0x30af 12971 #define mmDC_PERFMON22_PERFMON_CNTL_BASE_IDX 2 12972 #define mmDC_PERFMON22_PERFMON_CNTL2 0x30b0 12973 #define mmDC_PERFMON22_PERFMON_CNTL2_BASE_IDX 2 12974 #define mmDC_PERFMON22_PERFMON_CVALUE_INT_MISC 0x30b1 12975 #define mmDC_PERFMON22_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 12976 #define mmDC_PERFMON22_PERFMON_CVALUE_LOW 0x30b2 12977 #define mmDC_PERFMON22_PERFMON_CVALUE_LOW_BASE_IDX 2 12978 #define mmDC_PERFMON22_PERFMON_HI 0x30b3 12979 #define mmDC_PERFMON22_PERFMON_HI_BASE_IDX 2 12980 #define mmDC_PERFMON22_PERFMON_LOW 0x30b4 12981 #define mmDC_PERFMON22_PERFMON_LOW_BASE_IDX 2 12982 12983 12984 // addressBlock: dce_dc_dsc2_dispdec_dsc_top_dispdec 12985 // base address: 0x2e0 12986 #define mmDSC_TOP2_DSC_TOP_CONTROL 0x30b8 12987 #define mmDSC_TOP2_DSC_TOP_CONTROL_BASE_IDX 2 12988 #define mmDSC_TOP2_DSC_DEBUG_CONTROL 0x30b9 12989 #define mmDSC_TOP2_DSC_DEBUG_CONTROL_BASE_IDX 2 12990 12991 12992 // addressBlock: dce_dc_dsc2_dispdec_dsccif_dispdec 12993 // base address: 0x2e0 12994 #define mmDSCCIF2_DSCCIF_CONFIG0 0x30bd 12995 #define mmDSCCIF2_DSCCIF_CONFIG0_BASE_IDX 2 12996 #define mmDSCCIF2_DSCCIF_CONFIG1 0x30be 12997 #define mmDSCCIF2_DSCCIF_CONFIG1_BASE_IDX 2 12998 12999 13000 // addressBlock: dce_dc_dsc2_dispdec_dscc_dispdec 13001 // base address: 0x2e0 13002 #define mmDSCC2_DSCC_CONFIG0 0x30c2 13003 #define mmDSCC2_DSCC_CONFIG0_BASE_IDX 2 13004 #define mmDSCC2_DSCC_CONFIG1 0x30c3 13005 #define mmDSCC2_DSCC_CONFIG1_BASE_IDX 2 13006 #define mmDSCC2_DSCC_STATUS 0x30c4 13007 #define mmDSCC2_DSCC_STATUS_BASE_IDX 2 13008 #define mmDSCC2_DSCC_INTERRUPT_CONTROL_STATUS 0x30c5 13009 #define mmDSCC2_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX 2 13010 #define mmDSCC2_DSCC_PPS_CONFIG0 0x30c6 13011 #define mmDSCC2_DSCC_PPS_CONFIG0_BASE_IDX 2 13012 #define mmDSCC2_DSCC_PPS_CONFIG1 0x30c7 13013 #define mmDSCC2_DSCC_PPS_CONFIG1_BASE_IDX 2 13014 #define mmDSCC2_DSCC_PPS_CONFIG2 0x30c8 13015 #define mmDSCC2_DSCC_PPS_CONFIG2_BASE_IDX 2 13016 #define mmDSCC2_DSCC_PPS_CONFIG3 0x30c9 13017 #define mmDSCC2_DSCC_PPS_CONFIG3_BASE_IDX 2 13018 #define mmDSCC2_DSCC_PPS_CONFIG4 0x30ca 13019 #define mmDSCC2_DSCC_PPS_CONFIG4_BASE_IDX 2 13020 #define mmDSCC2_DSCC_PPS_CONFIG5 0x30cb 13021 #define mmDSCC2_DSCC_PPS_CONFIG5_BASE_IDX 2 13022 #define mmDSCC2_DSCC_PPS_CONFIG6 0x30cc 13023 #define mmDSCC2_DSCC_PPS_CONFIG6_BASE_IDX 2 13024 #define mmDSCC2_DSCC_PPS_CONFIG7 0x30cd 13025 #define mmDSCC2_DSCC_PPS_CONFIG7_BASE_IDX 2 13026 #define mmDSCC2_DSCC_PPS_CONFIG8 0x30ce 13027 #define mmDSCC2_DSCC_PPS_CONFIG8_BASE_IDX 2 13028 #define mmDSCC2_DSCC_PPS_CONFIG9 0x30cf 13029 #define mmDSCC2_DSCC_PPS_CONFIG9_BASE_IDX 2 13030 #define mmDSCC2_DSCC_PPS_CONFIG10 0x30d0 13031 #define mmDSCC2_DSCC_PPS_CONFIG10_BASE_IDX 2 13032 #define mmDSCC2_DSCC_PPS_CONFIG11 0x30d1 13033 #define mmDSCC2_DSCC_PPS_CONFIG11_BASE_IDX 2 13034 #define mmDSCC2_DSCC_PPS_CONFIG12 0x30d2 13035 #define mmDSCC2_DSCC_PPS_CONFIG12_BASE_IDX 2 13036 #define mmDSCC2_DSCC_PPS_CONFIG13 0x30d3 13037 #define mmDSCC2_DSCC_PPS_CONFIG13_BASE_IDX 2 13038 #define mmDSCC2_DSCC_PPS_CONFIG14 0x30d4 13039 #define mmDSCC2_DSCC_PPS_CONFIG14_BASE_IDX 2 13040 #define mmDSCC2_DSCC_PPS_CONFIG15 0x30d5 13041 #define mmDSCC2_DSCC_PPS_CONFIG15_BASE_IDX 2 13042 #define mmDSCC2_DSCC_PPS_CONFIG16 0x30d6 13043 #define mmDSCC2_DSCC_PPS_CONFIG16_BASE_IDX 2 13044 #define mmDSCC2_DSCC_PPS_CONFIG17 0x30d7 13045 #define mmDSCC2_DSCC_PPS_CONFIG17_BASE_IDX 2 13046 #define mmDSCC2_DSCC_PPS_CONFIG18 0x30d8 13047 #define mmDSCC2_DSCC_PPS_CONFIG18_BASE_IDX 2 13048 #define mmDSCC2_DSCC_PPS_CONFIG19 0x30d9 13049 #define mmDSCC2_DSCC_PPS_CONFIG19_BASE_IDX 2 13050 #define mmDSCC2_DSCC_PPS_CONFIG20 0x30da 13051 #define mmDSCC2_DSCC_PPS_CONFIG20_BASE_IDX 2 13052 #define mmDSCC2_DSCC_PPS_CONFIG21 0x30db 13053 #define mmDSCC2_DSCC_PPS_CONFIG21_BASE_IDX 2 13054 #define mmDSCC2_DSCC_PPS_CONFIG22 0x30dc 13055 #define mmDSCC2_DSCC_PPS_CONFIG22_BASE_IDX 2 13056 #define mmDSCC2_DSCC_MEM_POWER_CONTROL 0x30dd 13057 #define mmDSCC2_DSCC_MEM_POWER_CONTROL_BASE_IDX 2 13058 #define mmDSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER 0x30de 13059 #define mmDSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2 13060 #define mmDSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER 0x30df 13061 #define mmDSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2 13062 #define mmDSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER 0x30e0 13063 #define mmDSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2 13064 #define mmDSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER 0x30e1 13065 #define mmDSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2 13066 #define mmDSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER 0x30e2 13067 #define mmDSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2 13068 #define mmDSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER 0x30e3 13069 #define mmDSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2 13070 #define mmDSCC2_DSCC_MAX_ABS_ERROR0 0x30e4 13071 #define mmDSCC2_DSCC_MAX_ABS_ERROR0_BASE_IDX 2 13072 #define mmDSCC2_DSCC_MAX_ABS_ERROR1 0x30e5 13073 #define mmDSCC2_DSCC_MAX_ABS_ERROR1_BASE_IDX 2 13074 #define mmDSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL 0x30e6 13075 #define mmDSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 13076 #define mmDSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL 0x30e7 13077 #define mmDSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 13078 #define mmDSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL 0x30e8 13079 #define mmDSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 13080 #define mmDSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL 0x30e9 13081 #define mmDSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 13082 #define mmDSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL 0x30ea 13083 #define mmDSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 13084 #define mmDSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL 0x30eb 13085 #define mmDSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 13086 #define mmDSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL 0x30ec 13087 #define mmDSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 13088 #define mmDSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x30ed 13089 #define mmDSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 13090 13091 13092 // addressBlock: dce_dc_dsc2_dispdec_dsc_dcperfmon_dc_perfmon_dispdec 13093 // base address: 0xc420 13094 #define mmDC_PERFMON23_PERFCOUNTER_CNTL 0x3108 13095 #define mmDC_PERFMON23_PERFCOUNTER_CNTL_BASE_IDX 2 13096 #define mmDC_PERFMON23_PERFCOUNTER_CNTL2 0x3109 13097 #define mmDC_PERFMON23_PERFCOUNTER_CNTL2_BASE_IDX 2 13098 #define mmDC_PERFMON23_PERFCOUNTER_STATE 0x310a 13099 #define mmDC_PERFMON23_PERFCOUNTER_STATE_BASE_IDX 2 13100 #define mmDC_PERFMON23_PERFMON_CNTL 0x310b 13101 #define mmDC_PERFMON23_PERFMON_CNTL_BASE_IDX 2 13102 #define mmDC_PERFMON23_PERFMON_CNTL2 0x310c 13103 #define mmDC_PERFMON23_PERFMON_CNTL2_BASE_IDX 2 13104 #define mmDC_PERFMON23_PERFMON_CVALUE_INT_MISC 0x310d 13105 #define mmDC_PERFMON23_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 13106 #define mmDC_PERFMON23_PERFMON_CVALUE_LOW 0x310e 13107 #define mmDC_PERFMON23_PERFMON_CVALUE_LOW_BASE_IDX 2 13108 #define mmDC_PERFMON23_PERFMON_HI 0x310f 13109 #define mmDC_PERFMON23_PERFMON_HI_BASE_IDX 2 13110 #define mmDC_PERFMON23_PERFMON_LOW 0x3110 13111 #define mmDC_PERFMON23_PERFMON_LOW_BASE_IDX 2 13112 13113 13114 // addressBlock: dce_dc_dsc3_dispdec_dsc_top_dispdec 13115 // base address: 0x450 13116 #define mmDSC_TOP3_DSC_TOP_CONTROL 0x3114 13117 #define mmDSC_TOP3_DSC_TOP_CONTROL_BASE_IDX 2 13118 #define mmDSC_TOP3_DSC_DEBUG_CONTROL 0x3115 13119 #define mmDSC_TOP3_DSC_DEBUG_CONTROL_BASE_IDX 2 13120 13121 13122 // addressBlock: dce_dc_dsc3_dispdec_dsccif_dispdec 13123 // base address: 0x450 13124 #define mmDSCCIF3_DSCCIF_CONFIG0 0x3119 13125 #define mmDSCCIF3_DSCCIF_CONFIG0_BASE_IDX 2 13126 #define mmDSCCIF3_DSCCIF_CONFIG1 0x311a 13127 #define mmDSCCIF3_DSCCIF_CONFIG1_BASE_IDX 2 13128 13129 13130 // addressBlock: dce_dc_dsc3_dispdec_dscc_dispdec 13131 // base address: 0x450 13132 #define mmDSCC3_DSCC_CONFIG0 0x311e 13133 #define mmDSCC3_DSCC_CONFIG0_BASE_IDX 2 13134 #define mmDSCC3_DSCC_CONFIG1 0x311f 13135 #define mmDSCC3_DSCC_CONFIG1_BASE_IDX 2 13136 #define mmDSCC3_DSCC_STATUS 0x3120 13137 #define mmDSCC3_DSCC_STATUS_BASE_IDX 2 13138 #define mmDSCC3_DSCC_INTERRUPT_CONTROL_STATUS 0x3121 13139 #define mmDSCC3_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX 2 13140 #define mmDSCC3_DSCC_PPS_CONFIG0 0x3122 13141 #define mmDSCC3_DSCC_PPS_CONFIG0_BASE_IDX 2 13142 #define mmDSCC3_DSCC_PPS_CONFIG1 0x3123 13143 #define mmDSCC3_DSCC_PPS_CONFIG1_BASE_IDX 2 13144 #define mmDSCC3_DSCC_PPS_CONFIG2 0x3124 13145 #define mmDSCC3_DSCC_PPS_CONFIG2_BASE_IDX 2 13146 #define mmDSCC3_DSCC_PPS_CONFIG3 0x3125 13147 #define mmDSCC3_DSCC_PPS_CONFIG3_BASE_IDX 2 13148 #define mmDSCC3_DSCC_PPS_CONFIG4 0x3126 13149 #define mmDSCC3_DSCC_PPS_CONFIG4_BASE_IDX 2 13150 #define mmDSCC3_DSCC_PPS_CONFIG5 0x3127 13151 #define mmDSCC3_DSCC_PPS_CONFIG5_BASE_IDX 2 13152 #define mmDSCC3_DSCC_PPS_CONFIG6 0x3128 13153 #define mmDSCC3_DSCC_PPS_CONFIG6_BASE_IDX 2 13154 #define mmDSCC3_DSCC_PPS_CONFIG7 0x3129 13155 #define mmDSCC3_DSCC_PPS_CONFIG7_BASE_IDX 2 13156 #define mmDSCC3_DSCC_PPS_CONFIG8 0x312a 13157 #define mmDSCC3_DSCC_PPS_CONFIG8_BASE_IDX 2 13158 #define mmDSCC3_DSCC_PPS_CONFIG9 0x312b 13159 #define mmDSCC3_DSCC_PPS_CONFIG9_BASE_IDX 2 13160 #define mmDSCC3_DSCC_PPS_CONFIG10 0x312c 13161 #define mmDSCC3_DSCC_PPS_CONFIG10_BASE_IDX 2 13162 #define mmDSCC3_DSCC_PPS_CONFIG11 0x312d 13163 #define mmDSCC3_DSCC_PPS_CONFIG11_BASE_IDX 2 13164 #define mmDSCC3_DSCC_PPS_CONFIG12 0x312e 13165 #define mmDSCC3_DSCC_PPS_CONFIG12_BASE_IDX 2 13166 #define mmDSCC3_DSCC_PPS_CONFIG13 0x312f 13167 #define mmDSCC3_DSCC_PPS_CONFIG13_BASE_IDX 2 13168 #define mmDSCC3_DSCC_PPS_CONFIG14 0x3130 13169 #define mmDSCC3_DSCC_PPS_CONFIG14_BASE_IDX 2 13170 #define mmDSCC3_DSCC_PPS_CONFIG15 0x3131 13171 #define mmDSCC3_DSCC_PPS_CONFIG15_BASE_IDX 2 13172 #define mmDSCC3_DSCC_PPS_CONFIG16 0x3132 13173 #define mmDSCC3_DSCC_PPS_CONFIG16_BASE_IDX 2 13174 #define mmDSCC3_DSCC_PPS_CONFIG17 0x3133 13175 #define mmDSCC3_DSCC_PPS_CONFIG17_BASE_IDX 2 13176 #define mmDSCC3_DSCC_PPS_CONFIG18 0x3134 13177 #define mmDSCC3_DSCC_PPS_CONFIG18_BASE_IDX 2 13178 #define mmDSCC3_DSCC_PPS_CONFIG19 0x3135 13179 #define mmDSCC3_DSCC_PPS_CONFIG19_BASE_IDX 2 13180 #define mmDSCC3_DSCC_PPS_CONFIG20 0x3136 13181 #define mmDSCC3_DSCC_PPS_CONFIG20_BASE_IDX 2 13182 #define mmDSCC3_DSCC_PPS_CONFIG21 0x3137 13183 #define mmDSCC3_DSCC_PPS_CONFIG21_BASE_IDX 2 13184 #define mmDSCC3_DSCC_PPS_CONFIG22 0x3138 13185 #define mmDSCC3_DSCC_PPS_CONFIG22_BASE_IDX 2 13186 #define mmDSCC3_DSCC_MEM_POWER_CONTROL 0x3139 13187 #define mmDSCC3_DSCC_MEM_POWER_CONTROL_BASE_IDX 2 13188 #define mmDSCC3_DSCC_R_Y_SQUARED_ERROR_LOWER 0x313a 13189 #define mmDSCC3_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2 13190 #define mmDSCC3_DSCC_R_Y_SQUARED_ERROR_UPPER 0x313b 13191 #define mmDSCC3_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2 13192 #define mmDSCC3_DSCC_G_CB_SQUARED_ERROR_LOWER 0x313c 13193 #define mmDSCC3_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2 13194 #define mmDSCC3_DSCC_G_CB_SQUARED_ERROR_UPPER 0x313d 13195 #define mmDSCC3_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2 13196 #define mmDSCC3_DSCC_B_CR_SQUARED_ERROR_LOWER 0x313e 13197 #define mmDSCC3_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2 13198 #define mmDSCC3_DSCC_B_CR_SQUARED_ERROR_UPPER 0x313f 13199 #define mmDSCC3_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2 13200 #define mmDSCC3_DSCC_MAX_ABS_ERROR0 0x3140 13201 #define mmDSCC3_DSCC_MAX_ABS_ERROR0_BASE_IDX 2 13202 #define mmDSCC3_DSCC_MAX_ABS_ERROR1 0x3141 13203 #define mmDSCC3_DSCC_MAX_ABS_ERROR1_BASE_IDX 2 13204 #define mmDSCC3_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL 0x3142 13205 #define mmDSCC3_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 13206 #define mmDSCC3_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL 0x3143 13207 #define mmDSCC3_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 13208 #define mmDSCC3_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL 0x3144 13209 #define mmDSCC3_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 13210 #define mmDSCC3_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL 0x3145 13211 #define mmDSCC3_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 13212 #define mmDSCC3_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL 0x3146 13213 #define mmDSCC3_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 13214 #define mmDSCC3_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL 0x3147 13215 #define mmDSCC3_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 13216 #define mmDSCC3_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL 0x3148 13217 #define mmDSCC3_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 13218 #define mmDSCC3_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x3149 13219 #define mmDSCC3_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 13220 13221 13222 // addressBlock: dce_dc_dsc3_dispdec_dsc_dcperfmon_dc_perfmon_dispdec 13223 // base address: 0xc590 13224 #define mmDC_PERFMON24_PERFCOUNTER_CNTL 0x3164 13225 #define mmDC_PERFMON24_PERFCOUNTER_CNTL_BASE_IDX 2 13226 #define mmDC_PERFMON24_PERFCOUNTER_CNTL2 0x3165 13227 #define mmDC_PERFMON24_PERFCOUNTER_CNTL2_BASE_IDX 2 13228 #define mmDC_PERFMON24_PERFCOUNTER_STATE 0x3166 13229 #define mmDC_PERFMON24_PERFCOUNTER_STATE_BASE_IDX 2 13230 #define mmDC_PERFMON24_PERFMON_CNTL 0x3167 13231 #define mmDC_PERFMON24_PERFMON_CNTL_BASE_IDX 2 13232 #define mmDC_PERFMON24_PERFMON_CNTL2 0x3168 13233 #define mmDC_PERFMON24_PERFMON_CNTL2_BASE_IDX 2 13234 #define mmDC_PERFMON24_PERFMON_CVALUE_INT_MISC 0x3169 13235 #define mmDC_PERFMON24_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 13236 #define mmDC_PERFMON24_PERFMON_CVALUE_LOW 0x316a 13237 #define mmDC_PERFMON24_PERFMON_CVALUE_LOW_BASE_IDX 2 13238 #define mmDC_PERFMON24_PERFMON_HI 0x316b 13239 #define mmDC_PERFMON24_PERFMON_HI_BASE_IDX 2 13240 #define mmDC_PERFMON24_PERFMON_LOW 0x316c 13241 #define mmDC_PERFMON24_PERFMON_LOW_BASE_IDX 2 13242 13243 13244 // addressBlock: dce_dc_dsc4_dispdec_dsc_top_dispdec 13245 // base address: 0x5c0 13246 #define mmDSC_TOP4_DSC_TOP_CONTROL 0x3170 13247 #define mmDSC_TOP4_DSC_TOP_CONTROL_BASE_IDX 2 13248 #define mmDSC_TOP4_DSC_DEBUG_CONTROL 0x3171 13249 #define mmDSC_TOP4_DSC_DEBUG_CONTROL_BASE_IDX 2 13250 13251 13252 // addressBlock: dce_dc_dsc4_dispdec_dsccif_dispdec 13253 // base address: 0x5c0 13254 #define mmDSCCIF4_DSCCIF_CONFIG0 0x3175 13255 #define mmDSCCIF4_DSCCIF_CONFIG0_BASE_IDX 2 13256 #define mmDSCCIF4_DSCCIF_CONFIG1 0x3176 13257 #define mmDSCCIF4_DSCCIF_CONFIG1_BASE_IDX 2 13258 13259 13260 // addressBlock: dce_dc_dsc4_dispdec_dscc_dispdec 13261 // base address: 0x5c0 13262 #define mmDSCC4_DSCC_CONFIG0 0x317a 13263 #define mmDSCC4_DSCC_CONFIG0_BASE_IDX 2 13264 #define mmDSCC4_DSCC_CONFIG1 0x317b 13265 #define mmDSCC4_DSCC_CONFIG1_BASE_IDX 2 13266 #define mmDSCC4_DSCC_STATUS 0x317c 13267 #define mmDSCC4_DSCC_STATUS_BASE_IDX 2 13268 #define mmDSCC4_DSCC_INTERRUPT_CONTROL_STATUS 0x317d 13269 #define mmDSCC4_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX 2 13270 #define mmDSCC4_DSCC_PPS_CONFIG0 0x317e 13271 #define mmDSCC4_DSCC_PPS_CONFIG0_BASE_IDX 2 13272 #define mmDSCC4_DSCC_PPS_CONFIG1 0x317f 13273 #define mmDSCC4_DSCC_PPS_CONFIG1_BASE_IDX 2 13274 #define mmDSCC4_DSCC_PPS_CONFIG2 0x3180 13275 #define mmDSCC4_DSCC_PPS_CONFIG2_BASE_IDX 2 13276 #define mmDSCC4_DSCC_PPS_CONFIG3 0x3181 13277 #define mmDSCC4_DSCC_PPS_CONFIG3_BASE_IDX 2 13278 #define mmDSCC4_DSCC_PPS_CONFIG4 0x3182 13279 #define mmDSCC4_DSCC_PPS_CONFIG4_BASE_IDX 2 13280 #define mmDSCC4_DSCC_PPS_CONFIG5 0x3183 13281 #define mmDSCC4_DSCC_PPS_CONFIG5_BASE_IDX 2 13282 #define mmDSCC4_DSCC_PPS_CONFIG6 0x3184 13283 #define mmDSCC4_DSCC_PPS_CONFIG6_BASE_IDX 2 13284 #define mmDSCC4_DSCC_PPS_CONFIG7 0x3185 13285 #define mmDSCC4_DSCC_PPS_CONFIG7_BASE_IDX 2 13286 #define mmDSCC4_DSCC_PPS_CONFIG8 0x3186 13287 #define mmDSCC4_DSCC_PPS_CONFIG8_BASE_IDX 2 13288 #define mmDSCC4_DSCC_PPS_CONFIG9 0x3187 13289 #define mmDSCC4_DSCC_PPS_CONFIG9_BASE_IDX 2 13290 #define mmDSCC4_DSCC_PPS_CONFIG10 0x3188 13291 #define mmDSCC4_DSCC_PPS_CONFIG10_BASE_IDX 2 13292 #define mmDSCC4_DSCC_PPS_CONFIG11 0x3189 13293 #define mmDSCC4_DSCC_PPS_CONFIG11_BASE_IDX 2 13294 #define mmDSCC4_DSCC_PPS_CONFIG12 0x318a 13295 #define mmDSCC4_DSCC_PPS_CONFIG12_BASE_IDX 2 13296 #define mmDSCC4_DSCC_PPS_CONFIG13 0x318b 13297 #define mmDSCC4_DSCC_PPS_CONFIG13_BASE_IDX 2 13298 #define mmDSCC4_DSCC_PPS_CONFIG14 0x318c 13299 #define mmDSCC4_DSCC_PPS_CONFIG14_BASE_IDX 2 13300 #define mmDSCC4_DSCC_PPS_CONFIG15 0x318d 13301 #define mmDSCC4_DSCC_PPS_CONFIG15_BASE_IDX 2 13302 #define mmDSCC4_DSCC_PPS_CONFIG16 0x318e 13303 #define mmDSCC4_DSCC_PPS_CONFIG16_BASE_IDX 2 13304 #define mmDSCC4_DSCC_PPS_CONFIG17 0x318f 13305 #define mmDSCC4_DSCC_PPS_CONFIG17_BASE_IDX 2 13306 #define mmDSCC4_DSCC_PPS_CONFIG18 0x3190 13307 #define mmDSCC4_DSCC_PPS_CONFIG18_BASE_IDX 2 13308 #define mmDSCC4_DSCC_PPS_CONFIG19 0x3191 13309 #define mmDSCC4_DSCC_PPS_CONFIG19_BASE_IDX 2 13310 #define mmDSCC4_DSCC_PPS_CONFIG20 0x3192 13311 #define mmDSCC4_DSCC_PPS_CONFIG20_BASE_IDX 2 13312 #define mmDSCC4_DSCC_PPS_CONFIG21 0x3193 13313 #define mmDSCC4_DSCC_PPS_CONFIG21_BASE_IDX 2 13314 #define mmDSCC4_DSCC_PPS_CONFIG22 0x3194 13315 #define mmDSCC4_DSCC_PPS_CONFIG22_BASE_IDX 2 13316 #define mmDSCC4_DSCC_MEM_POWER_CONTROL 0x3195 13317 #define mmDSCC4_DSCC_MEM_POWER_CONTROL_BASE_IDX 2 13318 #define mmDSCC4_DSCC_R_Y_SQUARED_ERROR_LOWER 0x3196 13319 #define mmDSCC4_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2 13320 #define mmDSCC4_DSCC_R_Y_SQUARED_ERROR_UPPER 0x3197 13321 #define mmDSCC4_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2 13322 #define mmDSCC4_DSCC_G_CB_SQUARED_ERROR_LOWER 0x3198 13323 #define mmDSCC4_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2 13324 #define mmDSCC4_DSCC_G_CB_SQUARED_ERROR_UPPER 0x3199 13325 #define mmDSCC4_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2 13326 #define mmDSCC4_DSCC_B_CR_SQUARED_ERROR_LOWER 0x319a 13327 #define mmDSCC4_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2 13328 #define mmDSCC4_DSCC_B_CR_SQUARED_ERROR_UPPER 0x319b 13329 #define mmDSCC4_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2 13330 #define mmDSCC4_DSCC_MAX_ABS_ERROR0 0x319c 13331 #define mmDSCC4_DSCC_MAX_ABS_ERROR0_BASE_IDX 2 13332 #define mmDSCC4_DSCC_MAX_ABS_ERROR1 0x319d 13333 #define mmDSCC4_DSCC_MAX_ABS_ERROR1_BASE_IDX 2 13334 #define mmDSCC4_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL 0x319e 13335 #define mmDSCC4_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 13336 #define mmDSCC4_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL 0x319f 13337 #define mmDSCC4_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 13338 #define mmDSCC4_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL 0x31a0 13339 #define mmDSCC4_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 13340 #define mmDSCC4_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL 0x31a1 13341 #define mmDSCC4_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 13342 #define mmDSCC4_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL 0x31a2 13343 #define mmDSCC4_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 13344 #define mmDSCC4_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL 0x31a3 13345 #define mmDSCC4_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 13346 #define mmDSCC4_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL 0x31a4 13347 #define mmDSCC4_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 13348 #define mmDSCC4_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x31a5 13349 #define mmDSCC4_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 13350 13351 13352 // addressBlock: dce_dc_dsc4_dispdec_dsc_dcperfmon_dc_perfmon_dispdec 13353 // base address: 0xc700 13354 #define mmDC_PERFMON25_PERFCOUNTER_CNTL 0x31c0 13355 #define mmDC_PERFMON25_PERFCOUNTER_CNTL_BASE_IDX 2 13356 #define mmDC_PERFMON25_PERFCOUNTER_CNTL2 0x31c1 13357 #define mmDC_PERFMON25_PERFCOUNTER_CNTL2_BASE_IDX 2 13358 #define mmDC_PERFMON25_PERFCOUNTER_STATE 0x31c2 13359 #define mmDC_PERFMON25_PERFCOUNTER_STATE_BASE_IDX 2 13360 #define mmDC_PERFMON25_PERFMON_CNTL 0x31c3 13361 #define mmDC_PERFMON25_PERFMON_CNTL_BASE_IDX 2 13362 #define mmDC_PERFMON25_PERFMON_CNTL2 0x31c4 13363 #define mmDC_PERFMON25_PERFMON_CNTL2_BASE_IDX 2 13364 #define mmDC_PERFMON25_PERFMON_CVALUE_INT_MISC 0x31c5 13365 #define mmDC_PERFMON25_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 13366 #define mmDC_PERFMON25_PERFMON_CVALUE_LOW 0x31c6 13367 #define mmDC_PERFMON25_PERFMON_CVALUE_LOW_BASE_IDX 2 13368 #define mmDC_PERFMON25_PERFMON_HI 0x31c7 13369 #define mmDC_PERFMON25_PERFMON_HI_BASE_IDX 2 13370 #define mmDC_PERFMON25_PERFMON_LOW 0x31c8 13371 #define mmDC_PERFMON25_PERFMON_LOW_BASE_IDX 2 13372 13373 13374 // addressBlock: dce_dc_dsc5_dispdec_dsc_top_dispdec 13375 // base address: 0x730 13376 #define mmDSC_TOP5_DSC_TOP_CONTROL 0x31cc 13377 #define mmDSC_TOP5_DSC_TOP_CONTROL_BASE_IDX 2 13378 #define mmDSC_TOP5_DSC_DEBUG_CONTROL 0x31cd 13379 #define mmDSC_TOP5_DSC_DEBUG_CONTROL_BASE_IDX 2 13380 13381 // addressBlock: dce_dc_dsc5_dispdec_dsccif_dispdec 13382 // base address: 0x730 13383 #define mmDSCCIF5_DSCCIF_CONFIG0 0x31d1 13384 #define mmDSCCIF5_DSCCIF_CONFIG0_BASE_IDX 2 13385 #define mmDSCCIF5_DSCCIF_CONFIG1 0x31d2 13386 #define mmDSCCIF5_DSCCIF_CONFIG1_BASE_IDX 2 13387 13388 13389 // addressBlock: dce_dc_dsc5_dispdec_dscc_dispdec 13390 // base address: 0x730 13391 #define mmDSCC5_DSCC_CONFIG0 0x31d6 13392 #define mmDSCC5_DSCC_CONFIG0_BASE_IDX 2 13393 #define mmDSCC5_DSCC_CONFIG1 0x31d7 13394 #define mmDSCC5_DSCC_CONFIG1_BASE_IDX 2 13395 #define mmDSCC5_DSCC_STATUS 0x31d8 13396 #define mmDSCC5_DSCC_STATUS_BASE_IDX 2 13397 #define mmDSCC5_DSCC_INTERRUPT_CONTROL_STATUS 0x31d9 13398 #define mmDSCC5_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX 2 13399 #define mmDSCC5_DSCC_PPS_CONFIG0 0x31da 13400 #define mmDSCC5_DSCC_PPS_CONFIG0_BASE_IDX 2 13401 #define mmDSCC5_DSCC_PPS_CONFIG1 0x31db 13402 #define mmDSCC5_DSCC_PPS_CONFIG1_BASE_IDX 2 13403 #define mmDSCC5_DSCC_PPS_CONFIG2 0x31dc 13404 #define mmDSCC5_DSCC_PPS_CONFIG2_BASE_IDX 2 13405 #define mmDSCC5_DSCC_PPS_CONFIG3 0x31dd 13406 #define mmDSCC5_DSCC_PPS_CONFIG3_BASE_IDX 2 13407 #define mmDSCC5_DSCC_PPS_CONFIG4 0x31de 13408 #define mmDSCC5_DSCC_PPS_CONFIG4_BASE_IDX 2 13409 #define mmDSCC5_DSCC_PPS_CONFIG5 0x31df 13410 #define mmDSCC5_DSCC_PPS_CONFIG5_BASE_IDX 2 13411 #define mmDSCC5_DSCC_PPS_CONFIG6 0x31e0 13412 #define mmDSCC5_DSCC_PPS_CONFIG6_BASE_IDX 2 13413 #define mmDSCC5_DSCC_PPS_CONFIG7 0x31e1 13414 #define mmDSCC5_DSCC_PPS_CONFIG7_BASE_IDX 2 13415 #define mmDSCC5_DSCC_PPS_CONFIG8 0x31e2 13416 #define mmDSCC5_DSCC_PPS_CONFIG8_BASE_IDX 2 13417 #define mmDSCC5_DSCC_PPS_CONFIG9 0x31e3 13418 #define mmDSCC5_DSCC_PPS_CONFIG9_BASE_IDX 2 13419 #define mmDSCC5_DSCC_PPS_CONFIG10 0x31e4 13420 #define mmDSCC5_DSCC_PPS_CONFIG10_BASE_IDX 2 13421 #define mmDSCC5_DSCC_PPS_CONFIG11 0x31e5 13422 #define mmDSCC5_DSCC_PPS_CONFIG11_BASE_IDX 2 13423 #define mmDSCC5_DSCC_PPS_CONFIG12 0x31e6 13424 #define mmDSCC5_DSCC_PPS_CONFIG12_BASE_IDX 2 13425 #define mmDSCC5_DSCC_PPS_CONFIG13 0x31e7 13426 #define mmDSCC5_DSCC_PPS_CONFIG13_BASE_IDX 2 13427 #define mmDSCC5_DSCC_PPS_CONFIG14 0x31e8 13428 #define mmDSCC5_DSCC_PPS_CONFIG14_BASE_IDX 2 13429 #define mmDSCC5_DSCC_PPS_CONFIG15 0x31e9 13430 #define mmDSCC5_DSCC_PPS_CONFIG15_BASE_IDX 2 13431 #define mmDSCC5_DSCC_PPS_CONFIG16 0x31ea 13432 #define mmDSCC5_DSCC_PPS_CONFIG16_BASE_IDX 2 13433 #define mmDSCC5_DSCC_PPS_CONFIG17 0x31eb 13434 #define mmDSCC5_DSCC_PPS_CONFIG17_BASE_IDX 2 13435 #define mmDSCC5_DSCC_PPS_CONFIG18 0x31ec 13436 #define mmDSCC5_DSCC_PPS_CONFIG18_BASE_IDX 2 13437 #define mmDSCC5_DSCC_PPS_CONFIG19 0x31ed 13438 #define mmDSCC5_DSCC_PPS_CONFIG19_BASE_IDX 2 13439 #define mmDSCC5_DSCC_PPS_CONFIG20 0x31ee 13440 #define mmDSCC5_DSCC_PPS_CONFIG20_BASE_IDX 2 13441 #define mmDSCC5_DSCC_PPS_CONFIG21 0x31ef 13442 #define mmDSCC5_DSCC_PPS_CONFIG21_BASE_IDX 2 13443 #define mmDSCC5_DSCC_PPS_CONFIG22 0x31f0 13444 #define mmDSCC5_DSCC_PPS_CONFIG22_BASE_IDX 2 13445 #define mmDSCC5_DSCC_MEM_POWER_CONTROL 0x31f1 13446 #define mmDSCC5_DSCC_MEM_POWER_CONTROL_BASE_IDX 2 13447 #define mmDSCC5_DSCC_R_Y_SQUARED_ERROR_LOWER 0x31f2 13448 #define mmDSCC5_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2 13449 #define mmDSCC5_DSCC_R_Y_SQUARED_ERROR_UPPER 0x31f3 13450 #define mmDSCC5_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2 13451 #define mmDSCC5_DSCC_G_CB_SQUARED_ERROR_LOWER 0x31f4 13452 #define mmDSCC5_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2 13453 #define mmDSCC5_DSCC_G_CB_SQUARED_ERROR_UPPER 0x31f5 13454 #define mmDSCC5_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2 13455 #define mmDSCC5_DSCC_B_CR_SQUARED_ERROR_LOWER 0x31f6 13456 #define mmDSCC5_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2 13457 #define mmDSCC5_DSCC_B_CR_SQUARED_ERROR_UPPER 0x31f7 13458 #define mmDSCC5_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2 13459 #define mmDSCC5_DSCC_MAX_ABS_ERROR0 0x31f8 13460 #define mmDSCC5_DSCC_MAX_ABS_ERROR0_BASE_IDX 2 13461 #define mmDSCC5_DSCC_MAX_ABS_ERROR1 0x31f9 13462 #define mmDSCC5_DSCC_MAX_ABS_ERROR1_BASE_IDX 2 13463 #define mmDSCC5_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL 0x31fa 13464 #define mmDSCC5_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 13465 #define mmDSCC5_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL 0x31fb 13466 #define mmDSCC5_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 13467 #define mmDSCC5_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL 0x31fc 13468 #define mmDSCC5_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 13469 #define mmDSCC5_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL 0x31fd 13470 #define mmDSCC5_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 13471 #define mmDSCC5_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL 0x31fe 13472 #define mmDSCC5_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 13473 #define mmDSCC5_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL 0x31ff 13474 #define mmDSCC5_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 13475 #define mmDSCC5_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL 0x3200 13476 #define mmDSCC5_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 13477 #define mmDSCC5_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x3201 13478 #define mmDSCC5_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 13479 13480 13481 // addressBlock: dce_dc_dsc5_dispdec_dsc_dcperfmon_dc_perfmon_dispdec 13482 // base address: 0xc870 13483 #define mmDC_PERFMON26_PERFCOUNTER_CNTL 0x321c 13484 #define mmDC_PERFMON26_PERFCOUNTER_CNTL_BASE_IDX 2 13485 #define mmDC_PERFMON26_PERFCOUNTER_CNTL2 0x321d 13486 #define mmDC_PERFMON26_PERFCOUNTER_CNTL2_BASE_IDX 2 13487 #define mmDC_PERFMON26_PERFCOUNTER_STATE 0x321e 13488 #define mmDC_PERFMON26_PERFCOUNTER_STATE_BASE_IDX 2 13489 #define mmDC_PERFMON26_PERFMON_CNTL 0x321f 13490 #define mmDC_PERFMON26_PERFMON_CNTL_BASE_IDX 2 13491 #define mmDC_PERFMON26_PERFMON_CNTL2 0x3220 13492 #define mmDC_PERFMON26_PERFMON_CNTL2_BASE_IDX 2 13493 #define mmDC_PERFMON26_PERFMON_CVALUE_INT_MISC 0x3221 13494 #define mmDC_PERFMON26_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 13495 #define mmDC_PERFMON26_PERFMON_CVALUE_LOW 0x3222 13496 #define mmDC_PERFMON26_PERFMON_CVALUE_LOW_BASE_IDX 2 13497 #define mmDC_PERFMON26_PERFMON_HI 0x3223 13498 #define mmDC_PERFMON26_PERFMON_HI_BASE_IDX 2 13499 #define mmDC_PERFMON26_PERFMON_LOW 0x3224 13500 #define mmDC_PERFMON26_PERFMON_LOW_BASE_IDX 2 13501 13502 13503 // addressBlock: dce_dc_wb0_dispdec_dwb_top_dispdec 13504 // base address: 0x0 13505 #define mmDWB_ENABLE_CLK_CTRL 0x3228 13506 #define mmDWB_ENABLE_CLK_CTRL_BASE_IDX 2 13507 #define mmDWB_MEM_PWR_CTRL 0x3229 13508 #define mmDWB_MEM_PWR_CTRL_BASE_IDX 2 13509 #define mmFC_MODE_CTRL 0x322a 13510 #define mmFC_MODE_CTRL_BASE_IDX 2 13511 #define mmFC_FLOW_CTRL 0x322b 13512 #define mmFC_FLOW_CTRL_BASE_IDX 2 13513 #define mmFC_WINDOW_START 0x322c 13514 #define mmFC_WINDOW_START_BASE_IDX 2 13515 #define mmFC_WINDOW_SIZE 0x322d 13516 #define mmFC_WINDOW_SIZE_BASE_IDX 2 13517 #define mmFC_SOURCE_SIZE 0x322e 13518 #define mmFC_SOURCE_SIZE_BASE_IDX 2 13519 #define mmDWB_UPDATE_CTRL 0x322f 13520 #define mmDWB_UPDATE_CTRL_BASE_IDX 2 13521 #define mmDWB_CRC_CTRL 0x3230 13522 #define mmDWB_CRC_CTRL_BASE_IDX 2 13523 #define mmDWB_CRC_MASK_R_G 0x3231 13524 #define mmDWB_CRC_MASK_R_G_BASE_IDX 2 13525 #define mmDWB_CRC_MASK_B_A 0x3232 13526 #define mmDWB_CRC_MASK_B_A_BASE_IDX 2 13527 #define mmDWB_CRC_VAL_R_G 0x3233 13528 #define mmDWB_CRC_VAL_R_G_BASE_IDX 2 13529 #define mmDWB_CRC_VAL_B_A 0x3234 13530 #define mmDWB_CRC_VAL_B_A_BASE_IDX 2 13531 #define mmDWB_OUT_CTRL 0x3235 13532 #define mmDWB_OUT_CTRL_BASE_IDX 2 13533 #define mmDWB_MMHUBBUB_BACKPRESSURE_CNT_EN 0x3236 13534 #define mmDWB_MMHUBBUB_BACKPRESSURE_CNT_EN_BASE_IDX 2 13535 #define mmDWB_MMHUBBUB_BACKPRESSURE_CNT 0x3237 13536 #define mmDWB_MMHUBBUB_BACKPRESSURE_CNT_BASE_IDX 2 13537 #define mmDWB_HOST_READ_CONTROL 0x3238 13538 #define mmDWB_HOST_READ_CONTROL_BASE_IDX 2 13539 #define mmDWB_OVERFLOW_STATUS 0x3239 13540 #define mmDWB_OVERFLOW_STATUS_BASE_IDX 2 13541 #define mmDWB_OVERFLOW_COUNTER 0x323a 13542 #define mmDWB_OVERFLOW_COUNTER_BASE_IDX 2 13543 #define mmDWB_SOFT_RESET 0x323b 13544 #define mmDWB_SOFT_RESET_BASE_IDX 2 13545 13546 13547 // addressBlock: dce_dc_wb0_dispdec_wb_dcperfmon_dc_perfmon_dispdec 13548 // base address: 0xca20 13549 #define mmDC_PERFMON27_PERFCOUNTER_CNTL 0x3288 13550 #define mmDC_PERFMON27_PERFCOUNTER_CNTL_BASE_IDX 2 13551 #define mmDC_PERFMON27_PERFCOUNTER_CNTL2 0x3289 13552 #define mmDC_PERFMON27_PERFCOUNTER_CNTL2_BASE_IDX 2 13553 #define mmDC_PERFMON27_PERFCOUNTER_STATE 0x328a 13554 #define mmDC_PERFMON27_PERFCOUNTER_STATE_BASE_IDX 2 13555 #define mmDC_PERFMON27_PERFMON_CNTL 0x328b 13556 #define mmDC_PERFMON27_PERFMON_CNTL_BASE_IDX 2 13557 #define mmDC_PERFMON27_PERFMON_CNTL2 0x328c 13558 #define mmDC_PERFMON27_PERFMON_CNTL2_BASE_IDX 2 13559 #define mmDC_PERFMON27_PERFMON_CVALUE_INT_MISC 0x328d 13560 #define mmDC_PERFMON27_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 13561 #define mmDC_PERFMON27_PERFMON_CVALUE_LOW 0x328e 13562 #define mmDC_PERFMON27_PERFMON_CVALUE_LOW_BASE_IDX 2 13563 #define mmDC_PERFMON27_PERFMON_HI 0x328f 13564 #define mmDC_PERFMON27_PERFMON_HI_BASE_IDX 2 13565 #define mmDC_PERFMON27_PERFMON_LOW 0x3290 13566 #define mmDC_PERFMON27_PERFMON_LOW_BASE_IDX 2 13567 13568 13569 // addressBlock: dce_dc_wb0_dispdec_dwbcp_dispdec 13570 // base address: 0x0 13571 #define mmDWB_HDR_MULT_COEF 0x3294 13572 #define mmDWB_HDR_MULT_COEF_BASE_IDX 2 13573 #define mmDWB_GAMUT_REMAP_MODE 0x3295 13574 #define mmDWB_GAMUT_REMAP_MODE_BASE_IDX 2 13575 #define mmDWB_GAMUT_REMAP_COEF_FORMAT 0x3296 13576 #define mmDWB_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 2 13577 #define mmDWB_GAMUT_REMAPA_C11_C12 0x3297 13578 #define mmDWB_GAMUT_REMAPA_C11_C12_BASE_IDX 2 13579 #define mmDWB_GAMUT_REMAPA_C13_C14 0x3298 13580 #define mmDWB_GAMUT_REMAPA_C13_C14_BASE_IDX 2 13581 #define mmDWB_GAMUT_REMAPA_C21_C22 0x3299 13582 #define mmDWB_GAMUT_REMAPA_C21_C22_BASE_IDX 2 13583 #define mmDWB_GAMUT_REMAPA_C23_C24 0x329a 13584 #define mmDWB_GAMUT_REMAPA_C23_C24_BASE_IDX 2 13585 #define mmDWB_GAMUT_REMAPA_C31_C32 0x329b 13586 #define mmDWB_GAMUT_REMAPA_C31_C32_BASE_IDX 2 13587 #define mmDWB_GAMUT_REMAPA_C33_C34 0x329c 13588 #define mmDWB_GAMUT_REMAPA_C33_C34_BASE_IDX 2 13589 #define mmDWB_GAMUT_REMAPB_C11_C12 0x329d 13590 #define mmDWB_GAMUT_REMAPB_C11_C12_BASE_IDX 2 13591 #define mmDWB_GAMUT_REMAPB_C13_C14 0x329e 13592 #define mmDWB_GAMUT_REMAPB_C13_C14_BASE_IDX 2 13593 #define mmDWB_GAMUT_REMAPB_C21_C22 0x329f 13594 #define mmDWB_GAMUT_REMAPB_C21_C22_BASE_IDX 2 13595 #define mmDWB_GAMUT_REMAPB_C23_C24 0x32a0 13596 #define mmDWB_GAMUT_REMAPB_C23_C24_BASE_IDX 2 13597 #define mmDWB_GAMUT_REMAPB_C31_C32 0x32a1 13598 #define mmDWB_GAMUT_REMAPB_C31_C32_BASE_IDX 2 13599 #define mmDWB_GAMUT_REMAPB_C33_C34 0x32a2 13600 #define mmDWB_GAMUT_REMAPB_C33_C34_BASE_IDX 2 13601 #define mmDWB_OGAM_CONTROL 0x32a3 13602 #define mmDWB_OGAM_CONTROL_BASE_IDX 2 13603 #define mmDWB_OGAM_LUT_INDEX 0x32a4 13604 #define mmDWB_OGAM_LUT_INDEX_BASE_IDX 2 13605 #define mmDWB_OGAM_LUT_DATA 0x32a5 13606 #define mmDWB_OGAM_LUT_DATA_BASE_IDX 2 13607 #define mmDWB_OGAM_LUT_CONTROL 0x32a6 13608 #define mmDWB_OGAM_LUT_CONTROL_BASE_IDX 2 13609 #define mmDWB_OGAM_RAMA_START_CNTL_B 0x32a7 13610 #define mmDWB_OGAM_RAMA_START_CNTL_B_BASE_IDX 2 13611 #define mmDWB_OGAM_RAMA_START_CNTL_G 0x32a8 13612 #define mmDWB_OGAM_RAMA_START_CNTL_G_BASE_IDX 2 13613 #define mmDWB_OGAM_RAMA_START_CNTL_R 0x32a9 13614 #define mmDWB_OGAM_RAMA_START_CNTL_R_BASE_IDX 2 13615 #define mmDWB_OGAM_RAMA_START_BASE_CNTL_B 0x32aa 13616 #define mmDWB_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 2 13617 #define mmDWB_OGAM_RAMA_START_SLOPE_CNTL_B 0x32ab 13618 #define mmDWB_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 13619 #define mmDWB_OGAM_RAMA_START_BASE_CNTL_G 0x32ac 13620 #define mmDWB_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 2 13621 #define mmDWB_OGAM_RAMA_START_SLOPE_CNTL_G 0x32ad 13622 #define mmDWB_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 13623 #define mmDWB_OGAM_RAMA_START_BASE_CNTL_R 0x32ae 13624 #define mmDWB_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 2 13625 #define mmDWB_OGAM_RAMA_START_SLOPE_CNTL_R 0x32af 13626 #define mmDWB_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 13627 #define mmDWB_OGAM_RAMA_END_CNTL1_B 0x32b0 13628 #define mmDWB_OGAM_RAMA_END_CNTL1_B_BASE_IDX 2 13629 #define mmDWB_OGAM_RAMA_END_CNTL2_B 0x32b1 13630 #define mmDWB_OGAM_RAMA_END_CNTL2_B_BASE_IDX 2 13631 #define mmDWB_OGAM_RAMA_END_CNTL1_G 0x32b2 13632 #define mmDWB_OGAM_RAMA_END_CNTL1_G_BASE_IDX 2 13633 #define mmDWB_OGAM_RAMA_END_CNTL2_G 0x32b3 13634 #define mmDWB_OGAM_RAMA_END_CNTL2_G_BASE_IDX 2 13635 #define mmDWB_OGAM_RAMA_END_CNTL1_R 0x32b4 13636 #define mmDWB_OGAM_RAMA_END_CNTL1_R_BASE_IDX 2 13637 #define mmDWB_OGAM_RAMA_END_CNTL2_R 0x32b5 13638 #define mmDWB_OGAM_RAMA_END_CNTL2_R_BASE_IDX 2 13639 #define mmDWB_OGAM_RAMA_OFFSET_B 0x32b6 13640 #define mmDWB_OGAM_RAMA_OFFSET_B_BASE_IDX 2 13641 #define mmDWB_OGAM_RAMA_OFFSET_G 0x32b7 13642 #define mmDWB_OGAM_RAMA_OFFSET_G_BASE_IDX 2 13643 #define mmDWB_OGAM_RAMA_OFFSET_R 0x32b8 13644 #define mmDWB_OGAM_RAMA_OFFSET_R_BASE_IDX 2 13645 #define mmDWB_OGAM_RAMA_REGION_0_1 0x32b9 13646 #define mmDWB_OGAM_RAMA_REGION_0_1_BASE_IDX 2 13647 #define mmDWB_OGAM_RAMA_REGION_2_3 0x32ba 13648 #define mmDWB_OGAM_RAMA_REGION_2_3_BASE_IDX 2 13649 #define mmDWB_OGAM_RAMA_REGION_4_5 0x32bb 13650 #define mmDWB_OGAM_RAMA_REGION_4_5_BASE_IDX 2 13651 #define mmDWB_OGAM_RAMA_REGION_6_7 0x32bc 13652 #define mmDWB_OGAM_RAMA_REGION_6_7_BASE_IDX 2 13653 #define mmDWB_OGAM_RAMA_REGION_8_9 0x32bd 13654 #define mmDWB_OGAM_RAMA_REGION_8_9_BASE_IDX 2 13655 #define mmDWB_OGAM_RAMA_REGION_10_11 0x32be 13656 #define mmDWB_OGAM_RAMA_REGION_10_11_BASE_IDX 2 13657 #define mmDWB_OGAM_RAMA_REGION_12_13 0x32bf 13658 #define mmDWB_OGAM_RAMA_REGION_12_13_BASE_IDX 2 13659 #define mmDWB_OGAM_RAMA_REGION_14_15 0x32c0 13660 #define mmDWB_OGAM_RAMA_REGION_14_15_BASE_IDX 2 13661 #define mmDWB_OGAM_RAMA_REGION_16_17 0x32c1 13662 #define mmDWB_OGAM_RAMA_REGION_16_17_BASE_IDX 2 13663 #define mmDWB_OGAM_RAMA_REGION_18_19 0x32c2 13664 #define mmDWB_OGAM_RAMA_REGION_18_19_BASE_IDX 2 13665 #define mmDWB_OGAM_RAMA_REGION_20_21 0x32c3 13666 #define mmDWB_OGAM_RAMA_REGION_20_21_BASE_IDX 2 13667 #define mmDWB_OGAM_RAMA_REGION_22_23 0x32c4 13668 #define mmDWB_OGAM_RAMA_REGION_22_23_BASE_IDX 2 13669 #define mmDWB_OGAM_RAMA_REGION_24_25 0x32c5 13670 #define mmDWB_OGAM_RAMA_REGION_24_25_BASE_IDX 2 13671 #define mmDWB_OGAM_RAMA_REGION_26_27 0x32c6 13672 #define mmDWB_OGAM_RAMA_REGION_26_27_BASE_IDX 2 13673 #define mmDWB_OGAM_RAMA_REGION_28_29 0x32c7 13674 #define mmDWB_OGAM_RAMA_REGION_28_29_BASE_IDX 2 13675 #define mmDWB_OGAM_RAMA_REGION_30_31 0x32c8 13676 #define mmDWB_OGAM_RAMA_REGION_30_31_BASE_IDX 2 13677 #define mmDWB_OGAM_RAMA_REGION_32_33 0x32c9 13678 #define mmDWB_OGAM_RAMA_REGION_32_33_BASE_IDX 2 13679 #define mmDWB_OGAM_RAMB_START_CNTL_B 0x32ca 13680 #define mmDWB_OGAM_RAMB_START_CNTL_B_BASE_IDX 2 13681 #define mmDWB_OGAM_RAMB_START_CNTL_G 0x32cb 13682 #define mmDWB_OGAM_RAMB_START_CNTL_G_BASE_IDX 2 13683 #define mmDWB_OGAM_RAMB_START_CNTL_R 0x32cc 13684 #define mmDWB_OGAM_RAMB_START_CNTL_R_BASE_IDX 2 13685 #define mmDWB_OGAM_RAMB_START_BASE_CNTL_B 0x32cd 13686 #define mmDWB_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 2 13687 #define mmDWB_OGAM_RAMB_START_SLOPE_CNTL_B 0x32ce 13688 #define mmDWB_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 13689 #define mmDWB_OGAM_RAMB_START_BASE_CNTL_G 0x32cf 13690 #define mmDWB_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 2 13691 #define mmDWB_OGAM_RAMB_START_SLOPE_CNTL_G 0x32d0 13692 #define mmDWB_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 13693 #define mmDWB_OGAM_RAMB_START_BASE_CNTL_R 0x32d1 13694 #define mmDWB_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 2 13695 #define mmDWB_OGAM_RAMB_START_SLOPE_CNTL_R 0x32d2 13696 #define mmDWB_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 13697 #define mmDWB_OGAM_RAMB_END_CNTL1_B 0x32d3 13698 #define mmDWB_OGAM_RAMB_END_CNTL1_B_BASE_IDX 2 13699 #define mmDWB_OGAM_RAMB_END_CNTL2_B 0x32d4 13700 #define mmDWB_OGAM_RAMB_END_CNTL2_B_BASE_IDX 2 13701 #define mmDWB_OGAM_RAMB_END_CNTL1_G 0x32d5 13702 #define mmDWB_OGAM_RAMB_END_CNTL1_G_BASE_IDX 2 13703 #define mmDWB_OGAM_RAMB_END_CNTL2_G 0x32d6 13704 #define mmDWB_OGAM_RAMB_END_CNTL2_G_BASE_IDX 2 13705 #define mmDWB_OGAM_RAMB_END_CNTL1_R 0x32d7 13706 #define mmDWB_OGAM_RAMB_END_CNTL1_R_BASE_IDX 2 13707 #define mmDWB_OGAM_RAMB_END_CNTL2_R 0x32d8 13708 #define mmDWB_OGAM_RAMB_END_CNTL2_R_BASE_IDX 2 13709 #define mmDWB_OGAM_RAMB_OFFSET_B 0x32d9 13710 #define mmDWB_OGAM_RAMB_OFFSET_B_BASE_IDX 2 13711 #define mmDWB_OGAM_RAMB_OFFSET_G 0x32da 13712 #define mmDWB_OGAM_RAMB_OFFSET_G_BASE_IDX 2 13713 #define mmDWB_OGAM_RAMB_OFFSET_R 0x32db 13714 #define mmDWB_OGAM_RAMB_OFFSET_R_BASE_IDX 2 13715 #define mmDWB_OGAM_RAMB_REGION_0_1 0x32dc 13716 #define mmDWB_OGAM_RAMB_REGION_0_1_BASE_IDX 2 13717 #define mmDWB_OGAM_RAMB_REGION_2_3 0x32dd 13718 #define mmDWB_OGAM_RAMB_REGION_2_3_BASE_IDX 2 13719 #define mmDWB_OGAM_RAMB_REGION_4_5 0x32de 13720 #define mmDWB_OGAM_RAMB_REGION_4_5_BASE_IDX 2 13721 #define mmDWB_OGAM_RAMB_REGION_6_7 0x32df 13722 #define mmDWB_OGAM_RAMB_REGION_6_7_BASE_IDX 2 13723 #define mmDWB_OGAM_RAMB_REGION_8_9 0x32e0 13724 #define mmDWB_OGAM_RAMB_REGION_8_9_BASE_IDX 2 13725 #define mmDWB_OGAM_RAMB_REGION_10_11 0x32e1 13726 #define mmDWB_OGAM_RAMB_REGION_10_11_BASE_IDX 2 13727 #define mmDWB_OGAM_RAMB_REGION_12_13 0x32e2 13728 #define mmDWB_OGAM_RAMB_REGION_12_13_BASE_IDX 2 13729 #define mmDWB_OGAM_RAMB_REGION_14_15 0x32e3 13730 #define mmDWB_OGAM_RAMB_REGION_14_15_BASE_IDX 2 13731 #define mmDWB_OGAM_RAMB_REGION_16_17 0x32e4 13732 #define mmDWB_OGAM_RAMB_REGION_16_17_BASE_IDX 2 13733 #define mmDWB_OGAM_RAMB_REGION_18_19 0x32e5 13734 #define mmDWB_OGAM_RAMB_REGION_18_19_BASE_IDX 2 13735 #define mmDWB_OGAM_RAMB_REGION_20_21 0x32e6 13736 #define mmDWB_OGAM_RAMB_REGION_20_21_BASE_IDX 2 13737 #define mmDWB_OGAM_RAMB_REGION_22_23 0x32e7 13738 #define mmDWB_OGAM_RAMB_REGION_22_23_BASE_IDX 2 13739 #define mmDWB_OGAM_RAMB_REGION_24_25 0x32e8 13740 #define mmDWB_OGAM_RAMB_REGION_24_25_BASE_IDX 2 13741 #define mmDWB_OGAM_RAMB_REGION_26_27 0x32e9 13742 #define mmDWB_OGAM_RAMB_REGION_26_27_BASE_IDX 2 13743 #define mmDWB_OGAM_RAMB_REGION_28_29 0x32ea 13744 #define mmDWB_OGAM_RAMB_REGION_28_29_BASE_IDX 2 13745 #define mmDWB_OGAM_RAMB_REGION_30_31 0x32eb 13746 #define mmDWB_OGAM_RAMB_REGION_30_31_BASE_IDX 2 13747 #define mmDWB_OGAM_RAMB_REGION_32_33 0x32ec 13748 #define mmDWB_OGAM_RAMB_REGION_32_33_BASE_IDX 2 13749 13750 13751 // addressBlock: dce_dc_mpc_mpcc0_dispdec 13752 // base address: 0x0 13753 #define mmMPCC0_MPCC_TOP_SEL 0x0000 13754 #define mmMPCC0_MPCC_TOP_SEL_BASE_IDX 3 13755 #define mmMPCC0_MPCC_BOT_SEL 0x0001 13756 #define mmMPCC0_MPCC_BOT_SEL_BASE_IDX 3 13757 #define mmMPCC0_MPCC_OPP_ID 0x0002 13758 #define mmMPCC0_MPCC_OPP_ID_BASE_IDX 3 13759 #define mmMPCC0_MPCC_CONTROL 0x0003 13760 #define mmMPCC0_MPCC_CONTROL_BASE_IDX 3 13761 #define mmMPCC0_MPCC_SM_CONTROL 0x0004 13762 #define mmMPCC0_MPCC_SM_CONTROL_BASE_IDX 3 13763 #define mmMPCC0_MPCC_UPDATE_LOCK_SEL 0x0005 13764 #define mmMPCC0_MPCC_UPDATE_LOCK_SEL_BASE_IDX 3 13765 #define mmMPCC0_MPCC_TOP_GAIN 0x0006 13766 #define mmMPCC0_MPCC_TOP_GAIN_BASE_IDX 3 13767 #define mmMPCC0_MPCC_BOT_GAIN_INSIDE 0x0007 13768 #define mmMPCC0_MPCC_BOT_GAIN_INSIDE_BASE_IDX 3 13769 #define mmMPCC0_MPCC_BOT_GAIN_OUTSIDE 0x0008 13770 #define mmMPCC0_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 3 13771 #define mmMPCC0_MPCC_BG_R_CR 0x0009 13772 #define mmMPCC0_MPCC_BG_R_CR_BASE_IDX 3 13773 #define mmMPCC0_MPCC_BG_G_Y 0x000a 13774 #define mmMPCC0_MPCC_BG_G_Y_BASE_IDX 3 13775 #define mmMPCC0_MPCC_BG_B_CB 0x000b 13776 #define mmMPCC0_MPCC_BG_B_CB_BASE_IDX 3 13777 #define mmMPCC0_MPCC_MEM_PWR_CTRL 0x000c 13778 #define mmMPCC0_MPCC_MEM_PWR_CTRL_BASE_IDX 3 13779 #define mmMPCC0_MPCC_STATUS 0x000d 13780 #define mmMPCC0_MPCC_STATUS_BASE_IDX 3 13781 13782 13783 // addressBlock: dce_dc_mpc_mpcc1_dispdec 13784 // base address: 0x80 13785 #define mmMPCC1_MPCC_TOP_SEL 0x0020 13786 #define mmMPCC1_MPCC_TOP_SEL_BASE_IDX 3 13787 #define mmMPCC1_MPCC_BOT_SEL 0x0021 13788 #define mmMPCC1_MPCC_BOT_SEL_BASE_IDX 3 13789 #define mmMPCC1_MPCC_OPP_ID 0x0022 13790 #define mmMPCC1_MPCC_OPP_ID_BASE_IDX 3 13791 #define mmMPCC1_MPCC_CONTROL 0x0023 13792 #define mmMPCC1_MPCC_CONTROL_BASE_IDX 3 13793 #define mmMPCC1_MPCC_SM_CONTROL 0x0024 13794 #define mmMPCC1_MPCC_SM_CONTROL_BASE_IDX 3 13795 #define mmMPCC1_MPCC_UPDATE_LOCK_SEL 0x0025 13796 #define mmMPCC1_MPCC_UPDATE_LOCK_SEL_BASE_IDX 3 13797 #define mmMPCC1_MPCC_TOP_GAIN 0x0026 13798 #define mmMPCC1_MPCC_TOP_GAIN_BASE_IDX 3 13799 #define mmMPCC1_MPCC_BOT_GAIN_INSIDE 0x0027 13800 #define mmMPCC1_MPCC_BOT_GAIN_INSIDE_BASE_IDX 3 13801 #define mmMPCC1_MPCC_BOT_GAIN_OUTSIDE 0x0028 13802 #define mmMPCC1_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 3 13803 #define mmMPCC1_MPCC_BG_R_CR 0x0029 13804 #define mmMPCC1_MPCC_BG_R_CR_BASE_IDX 3 13805 #define mmMPCC1_MPCC_BG_G_Y 0x002a 13806 #define mmMPCC1_MPCC_BG_G_Y_BASE_IDX 3 13807 #define mmMPCC1_MPCC_BG_B_CB 0x002b 13808 #define mmMPCC1_MPCC_BG_B_CB_BASE_IDX 3 13809 #define mmMPCC1_MPCC_MEM_PWR_CTRL 0x002c 13810 #define mmMPCC1_MPCC_MEM_PWR_CTRL_BASE_IDX 3 13811 #define mmMPCC1_MPCC_STATUS 0x002d 13812 #define mmMPCC1_MPCC_STATUS_BASE_IDX 3 13813 13814 13815 // addressBlock: dce_dc_mpc_mpcc2_dispdec 13816 // base address: 0x100 13817 #define mmMPCC2_MPCC_TOP_SEL 0x0040 13818 #define mmMPCC2_MPCC_TOP_SEL_BASE_IDX 3 13819 #define mmMPCC2_MPCC_BOT_SEL 0x0041 13820 #define mmMPCC2_MPCC_BOT_SEL_BASE_IDX 3 13821 #define mmMPCC2_MPCC_OPP_ID 0x0042 13822 #define mmMPCC2_MPCC_OPP_ID_BASE_IDX 3 13823 #define mmMPCC2_MPCC_CONTROL 0x0043 13824 #define mmMPCC2_MPCC_CONTROL_BASE_IDX 3 13825 #define mmMPCC2_MPCC_SM_CONTROL 0x0044 13826 #define mmMPCC2_MPCC_SM_CONTROL_BASE_IDX 3 13827 #define mmMPCC2_MPCC_UPDATE_LOCK_SEL 0x0045 13828 #define mmMPCC2_MPCC_UPDATE_LOCK_SEL_BASE_IDX 3 13829 #define mmMPCC2_MPCC_TOP_GAIN 0x0046 13830 #define mmMPCC2_MPCC_TOP_GAIN_BASE_IDX 3 13831 #define mmMPCC2_MPCC_BOT_GAIN_INSIDE 0x0047 13832 #define mmMPCC2_MPCC_BOT_GAIN_INSIDE_BASE_IDX 3 13833 #define mmMPCC2_MPCC_BOT_GAIN_OUTSIDE 0x0048 13834 #define mmMPCC2_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 3 13835 #define mmMPCC2_MPCC_BG_R_CR 0x0049 13836 #define mmMPCC2_MPCC_BG_R_CR_BASE_IDX 3 13837 #define mmMPCC2_MPCC_BG_G_Y 0x004a 13838 #define mmMPCC2_MPCC_BG_G_Y_BASE_IDX 3 13839 #define mmMPCC2_MPCC_BG_B_CB 0x004b 13840 #define mmMPCC2_MPCC_BG_B_CB_BASE_IDX 3 13841 #define mmMPCC2_MPCC_MEM_PWR_CTRL 0x004c 13842 #define mmMPCC2_MPCC_MEM_PWR_CTRL_BASE_IDX 3 13843 #define mmMPCC2_MPCC_STATUS 0x004d 13844 #define mmMPCC2_MPCC_STATUS_BASE_IDX 3 13845 13846 13847 // addressBlock: dce_dc_mpc_mpcc3_dispdec 13848 // base address: 0x180 13849 #define mmMPCC3_MPCC_TOP_SEL 0x0060 13850 #define mmMPCC3_MPCC_TOP_SEL_BASE_IDX 3 13851 #define mmMPCC3_MPCC_BOT_SEL 0x0061 13852 #define mmMPCC3_MPCC_BOT_SEL_BASE_IDX 3 13853 #define mmMPCC3_MPCC_OPP_ID 0x0062 13854 #define mmMPCC3_MPCC_OPP_ID_BASE_IDX 3 13855 #define mmMPCC3_MPCC_CONTROL 0x0063 13856 #define mmMPCC3_MPCC_CONTROL_BASE_IDX 3 13857 #define mmMPCC3_MPCC_SM_CONTROL 0x0064 13858 #define mmMPCC3_MPCC_SM_CONTROL_BASE_IDX 3 13859 #define mmMPCC3_MPCC_UPDATE_LOCK_SEL 0x0065 13860 #define mmMPCC3_MPCC_UPDATE_LOCK_SEL_BASE_IDX 3 13861 #define mmMPCC3_MPCC_TOP_GAIN 0x0066 13862 #define mmMPCC3_MPCC_TOP_GAIN_BASE_IDX 3 13863 #define mmMPCC3_MPCC_BOT_GAIN_INSIDE 0x0067 13864 #define mmMPCC3_MPCC_BOT_GAIN_INSIDE_BASE_IDX 3 13865 #define mmMPCC3_MPCC_BOT_GAIN_OUTSIDE 0x0068 13866 #define mmMPCC3_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 3 13867 #define mmMPCC3_MPCC_BG_R_CR 0x0069 13868 #define mmMPCC3_MPCC_BG_R_CR_BASE_IDX 3 13869 #define mmMPCC3_MPCC_BG_G_Y 0x006a 13870 #define mmMPCC3_MPCC_BG_G_Y_BASE_IDX 3 13871 #define mmMPCC3_MPCC_BG_B_CB 0x006b 13872 #define mmMPCC3_MPCC_BG_B_CB_BASE_IDX 3 13873 #define mmMPCC3_MPCC_MEM_PWR_CTRL 0x006c 13874 #define mmMPCC3_MPCC_MEM_PWR_CTRL_BASE_IDX 3 13875 #define mmMPCC3_MPCC_STATUS 0x006d 13876 #define mmMPCC3_MPCC_STATUS_BASE_IDX 3 13877 13878 13879 // addressBlock: dce_dc_mpc_mpcc4_dispdec 13880 // base address: 0x200 13881 #define mmMPCC4_MPCC_TOP_SEL 0x0080 13882 #define mmMPCC4_MPCC_TOP_SEL_BASE_IDX 3 13883 #define mmMPCC4_MPCC_BOT_SEL 0x0081 13884 #define mmMPCC4_MPCC_BOT_SEL_BASE_IDX 3 13885 #define mmMPCC4_MPCC_OPP_ID 0x0082 13886 #define mmMPCC4_MPCC_OPP_ID_BASE_IDX 3 13887 #define mmMPCC4_MPCC_CONTROL 0x0083 13888 #define mmMPCC4_MPCC_CONTROL_BASE_IDX 3 13889 #define mmMPCC4_MPCC_SM_CONTROL 0x0084 13890 #define mmMPCC4_MPCC_SM_CONTROL_BASE_IDX 3 13891 #define mmMPCC4_MPCC_UPDATE_LOCK_SEL 0x0085 13892 #define mmMPCC4_MPCC_UPDATE_LOCK_SEL_BASE_IDX 3 13893 #define mmMPCC4_MPCC_TOP_GAIN 0x0086 13894 #define mmMPCC4_MPCC_TOP_GAIN_BASE_IDX 3 13895 #define mmMPCC4_MPCC_BOT_GAIN_INSIDE 0x0087 13896 #define mmMPCC4_MPCC_BOT_GAIN_INSIDE_BASE_IDX 3 13897 #define mmMPCC4_MPCC_BOT_GAIN_OUTSIDE 0x0088 13898 #define mmMPCC4_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 3 13899 #define mmMPCC4_MPCC_BG_R_CR 0x0089 13900 #define mmMPCC4_MPCC_BG_R_CR_BASE_IDX 3 13901 #define mmMPCC4_MPCC_BG_G_Y 0x008a 13902 #define mmMPCC4_MPCC_BG_G_Y_BASE_IDX 3 13903 #define mmMPCC4_MPCC_BG_B_CB 0x008b 13904 #define mmMPCC4_MPCC_BG_B_CB_BASE_IDX 3 13905 #define mmMPCC4_MPCC_MEM_PWR_CTRL 0x008c 13906 #define mmMPCC4_MPCC_MEM_PWR_CTRL_BASE_IDX 3 13907 #define mmMPCC4_MPCC_STATUS 0x008d 13908 #define mmMPCC4_MPCC_STATUS_BASE_IDX 3 13909 13910 13911 // addressBlock: dce_dc_mpc_mpcc5_dispdec 13912 // base address: 0x280 13913 #define mmMPCC5_MPCC_TOP_SEL 0x00a0 13914 #define mmMPCC5_MPCC_TOP_SEL_BASE_IDX 3 13915 #define mmMPCC5_MPCC_BOT_SEL 0x00a1 13916 #define mmMPCC5_MPCC_BOT_SEL_BASE_IDX 3 13917 #define mmMPCC5_MPCC_OPP_ID 0x00a2 13918 #define mmMPCC5_MPCC_OPP_ID_BASE_IDX 3 13919 #define mmMPCC5_MPCC_CONTROL 0x00a3 13920 #define mmMPCC5_MPCC_CONTROL_BASE_IDX 3 13921 #define mmMPCC5_MPCC_SM_CONTROL 0x00a4 13922 #define mmMPCC5_MPCC_SM_CONTROL_BASE_IDX 3 13923 #define mmMPCC5_MPCC_UPDATE_LOCK_SEL 0x00a5 13924 #define mmMPCC5_MPCC_UPDATE_LOCK_SEL_BASE_IDX 3 13925 #define mmMPCC5_MPCC_TOP_GAIN 0x00a6 13926 #define mmMPCC5_MPCC_TOP_GAIN_BASE_IDX 3 13927 #define mmMPCC5_MPCC_BOT_GAIN_INSIDE 0x00a7 13928 #define mmMPCC5_MPCC_BOT_GAIN_INSIDE_BASE_IDX 3 13929 #define mmMPCC5_MPCC_BOT_GAIN_OUTSIDE 0x00a8 13930 #define mmMPCC5_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 3 13931 #define mmMPCC5_MPCC_BG_R_CR 0x00a9 13932 #define mmMPCC5_MPCC_BG_R_CR_BASE_IDX 3 13933 #define mmMPCC5_MPCC_BG_G_Y 0x00aa 13934 #define mmMPCC5_MPCC_BG_G_Y_BASE_IDX 3 13935 #define mmMPCC5_MPCC_BG_B_CB 0x00ab 13936 #define mmMPCC5_MPCC_BG_B_CB_BASE_IDX 3 13937 #define mmMPCC5_MPCC_MEM_PWR_CTRL 0x00ac 13938 #define mmMPCC5_MPCC_MEM_PWR_CTRL_BASE_IDX 3 13939 #define mmMPCC5_MPCC_STATUS 0x00ad 13940 #define mmMPCC5_MPCC_STATUS_BASE_IDX 3 13941 13942 13943 // addressBlock: dce_dc_mpc_mpcc_ogam0_dispdec 13944 // base address: 0x0 13945 #define mmMPCC_OGAM0_MPCC_OGAM_CONTROL 0x0100 13946 #define mmMPCC_OGAM0_MPCC_OGAM_CONTROL_BASE_IDX 3 13947 #define mmMPCC_OGAM0_MPCC_OGAM_LUT_INDEX 0x0101 13948 #define mmMPCC_OGAM0_MPCC_OGAM_LUT_INDEX_BASE_IDX 3 13949 #define mmMPCC_OGAM0_MPCC_OGAM_LUT_DATA 0x0102 13950 #define mmMPCC_OGAM0_MPCC_OGAM_LUT_DATA_BASE_IDX 3 13951 #define mmMPCC_OGAM0_MPCC_OGAM_LUT_CONTROL 0x0103 13952 #define mmMPCC_OGAM0_MPCC_OGAM_LUT_CONTROL_BASE_IDX 3 13953 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B 0x0104 13954 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 3 13955 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G 0x0105 13956 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 3 13957 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R 0x0106 13958 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 3 13959 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B 0x0107 13960 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3 13961 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G 0x0108 13962 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3 13963 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R 0x0109 13964 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3 13965 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B 0x010a 13966 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 3 13967 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G 0x010b 13968 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 3 13969 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R 0x010c 13970 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 3 13971 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B 0x010d 13972 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 3 13973 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B 0x010e 13974 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 3 13975 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G 0x010f 13976 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 3 13977 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G 0x0110 13978 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 3 13979 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R 0x0111 13980 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 3 13981 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R 0x0112 13982 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 3 13983 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B 0x0113 13984 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX 3 13985 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G 0x0114 13986 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX 3 13987 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R 0x0115 13988 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX 3 13989 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1 0x0116 13990 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 3 13991 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3 0x0117 13992 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 3 13993 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5 0x0118 13994 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 3 13995 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7 0x0119 13996 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 3 13997 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9 0x011a 13998 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 3 13999 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11 0x011b 14000 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 3 14001 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13 0x011c 14002 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 3 14003 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15 0x011d 14004 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 3 14005 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17 0x011e 14006 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 3 14007 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19 0x011f 14008 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 3 14009 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21 0x0120 14010 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 3 14011 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23 0x0121 14012 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 3 14013 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25 0x0122 14014 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 3 14015 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27 0x0123 14016 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 3 14017 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29 0x0124 14018 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 3 14019 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31 0x0125 14020 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 3 14021 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33 0x0126 14022 #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 3 14023 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B 0x0127 14024 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 3 14025 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G 0x0128 14026 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 3 14027 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R 0x0129 14028 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 3 14029 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B 0x012a 14030 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3 14031 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G 0x012b 14032 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3 14033 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R 0x012c 14034 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3 14035 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B 0x012d 14036 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 3 14037 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G 0x012e 14038 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 3 14039 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R 0x012f 14040 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 3 14041 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B 0x0130 14042 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 3 14043 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B 0x0131 14044 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 3 14045 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G 0x0132 14046 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 3 14047 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G 0x0133 14048 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 3 14049 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R 0x0134 14050 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 3 14051 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R 0x0135 14052 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 3 14053 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B 0x0136 14054 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX 3 14055 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G 0x0137 14056 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX 3 14057 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R 0x0138 14058 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX 3 14059 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1 0x0139 14060 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 3 14061 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3 0x013a 14062 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 3 14063 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5 0x013b 14064 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 3 14065 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7 0x013c 14066 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 3 14067 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9 0x013d 14068 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 3 14069 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11 0x013e 14070 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 3 14071 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13 0x013f 14072 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 3 14073 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15 0x0140 14074 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 3 14075 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17 0x0141 14076 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 3 14077 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19 0x0142 14078 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 3 14079 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21 0x0143 14080 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 3 14081 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23 0x0144 14082 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 3 14083 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25 0x0145 14084 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 3 14085 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27 0x0146 14086 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 3 14087 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29 0x0147 14088 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 3 14089 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31 0x0148 14090 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 3 14091 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33 0x0149 14092 #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 3 14093 #define mmMPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT 0x014a 14094 #define mmMPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3 14095 #define mmMPCC_OGAM0_MPCC_GAMUT_REMAP_MODE 0x014b 14096 #define mmMPCC_OGAM0_MPCC_GAMUT_REMAP_MODE_BASE_IDX 3 14097 #define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A 0x014c 14098 #define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX 3 14099 #define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A 0x014d 14100 #define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX 3 14101 #define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A 0x014e 14102 #define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX 3 14103 #define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A 0x014f 14104 #define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX 3 14105 #define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A 0x0150 14106 #define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX 3 14107 #define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A 0x0151 14108 #define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX 3 14109 #define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B 0x0152 14110 #define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX 3 14111 #define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B 0x0153 14112 #define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX 3 14113 #define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B 0x0154 14114 #define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX 3 14115 #define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B 0x0155 14116 #define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX 3 14117 #define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B 0x0156 14118 #define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX 3 14119 #define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B 0x0157 14120 #define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX 3 14121 14122 14123 // addressBlock: dce_dc_mpc_mpcc_ogam1_dispdec 14124 // base address: 0x200 14125 #define mmMPCC_OGAM1_MPCC_OGAM_CONTROL 0x0180 14126 #define mmMPCC_OGAM1_MPCC_OGAM_CONTROL_BASE_IDX 3 14127 #define mmMPCC_OGAM1_MPCC_OGAM_LUT_INDEX 0x0181 14128 #define mmMPCC_OGAM1_MPCC_OGAM_LUT_INDEX_BASE_IDX 3 14129 #define mmMPCC_OGAM1_MPCC_OGAM_LUT_DATA 0x0182 14130 #define mmMPCC_OGAM1_MPCC_OGAM_LUT_DATA_BASE_IDX 3 14131 #define mmMPCC_OGAM1_MPCC_OGAM_LUT_CONTROL 0x0183 14132 #define mmMPCC_OGAM1_MPCC_OGAM_LUT_CONTROL_BASE_IDX 3 14133 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B 0x0184 14134 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 3 14135 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G 0x0185 14136 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 3 14137 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R 0x0186 14138 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 3 14139 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B 0x0187 14140 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3 14141 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G 0x0188 14142 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3 14143 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R 0x0189 14144 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3 14145 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B 0x018a 14146 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 3 14147 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G 0x018b 14148 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 3 14149 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R 0x018c 14150 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 3 14151 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B 0x018d 14152 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 3 14153 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B 0x018e 14154 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 3 14155 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G 0x018f 14156 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 3 14157 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G 0x0190 14158 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 3 14159 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R 0x0191 14160 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 3 14161 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R 0x0192 14162 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 3 14163 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B 0x0193 14164 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX 3 14165 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G 0x0194 14166 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX 3 14167 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R 0x0195 14168 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX 3 14169 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1 0x0196 14170 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 3 14171 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3 0x0197 14172 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 3 14173 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5 0x0198 14174 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 3 14175 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7 0x0199 14176 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 3 14177 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9 0x019a 14178 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 3 14179 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11 0x019b 14180 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 3 14181 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13 0x019c 14182 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 3 14183 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15 0x019d 14184 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 3 14185 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17 0x019e 14186 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 3 14187 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19 0x019f 14188 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 3 14189 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21 0x01a0 14190 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 3 14191 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23 0x01a1 14192 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 3 14193 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25 0x01a2 14194 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 3 14195 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27 0x01a3 14196 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 3 14197 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29 0x01a4 14198 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 3 14199 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31 0x01a5 14200 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 3 14201 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33 0x01a6 14202 #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 3 14203 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B 0x01a7 14204 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 3 14205 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G 0x01a8 14206 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 3 14207 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R 0x01a9 14208 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 3 14209 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B 0x01aa 14210 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3 14211 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G 0x01ab 14212 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3 14213 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R 0x01ac 14214 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3 14215 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B 0x01ad 14216 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 3 14217 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G 0x01ae 14218 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 3 14219 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R 0x01af 14220 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 3 14221 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B 0x01b0 14222 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 3 14223 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B 0x01b1 14224 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 3 14225 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G 0x01b2 14226 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 3 14227 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G 0x01b3 14228 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 3 14229 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R 0x01b4 14230 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 3 14231 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R 0x01b5 14232 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 3 14233 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B 0x01b6 14234 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX 3 14235 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G 0x01b7 14236 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX 3 14237 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R 0x01b8 14238 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX 3 14239 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1 0x01b9 14240 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 3 14241 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3 0x01ba 14242 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 3 14243 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5 0x01bb 14244 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 3 14245 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7 0x01bc 14246 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 3 14247 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9 0x01bd 14248 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 3 14249 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11 0x01be 14250 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 3 14251 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13 0x01bf 14252 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 3 14253 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15 0x01c0 14254 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 3 14255 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17 0x01c1 14256 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 3 14257 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19 0x01c2 14258 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 3 14259 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21 0x01c3 14260 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 3 14261 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23 0x01c4 14262 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 3 14263 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25 0x01c5 14264 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 3 14265 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27 0x01c6 14266 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 3 14267 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29 0x01c7 14268 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 3 14269 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31 0x01c8 14270 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 3 14271 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33 0x01c9 14272 #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 3 14273 #define mmMPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT 0x01ca 14274 #define mmMPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3 14275 #define mmMPCC_OGAM1_MPCC_GAMUT_REMAP_MODE 0x01cb 14276 #define mmMPCC_OGAM1_MPCC_GAMUT_REMAP_MODE_BASE_IDX 3 14277 #define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A 0x01cc 14278 #define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX 3 14279 #define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A 0x01cd 14280 #define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX 3 14281 #define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A 0x01ce 14282 #define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX 3 14283 #define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A 0x01cf 14284 #define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX 3 14285 #define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A 0x01d0 14286 #define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX 3 14287 #define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A 0x01d1 14288 #define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX 3 14289 #define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B 0x01d2 14290 #define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX 3 14291 #define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B 0x01d3 14292 #define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX 3 14293 #define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B 0x01d4 14294 #define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX 3 14295 #define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B 0x01d5 14296 #define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX 3 14297 #define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B 0x01d6 14298 #define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX 3 14299 #define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B 0x01d7 14300 #define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX 3 14301 14302 14303 // addressBlock: dce_dc_mpc_mpcc_ogam2_dispdec 14304 // base address: 0x400 14305 #define mmMPCC_OGAM2_MPCC_OGAM_CONTROL 0x0200 14306 #define mmMPCC_OGAM2_MPCC_OGAM_CONTROL_BASE_IDX 3 14307 #define mmMPCC_OGAM2_MPCC_OGAM_LUT_INDEX 0x0201 14308 #define mmMPCC_OGAM2_MPCC_OGAM_LUT_INDEX_BASE_IDX 3 14309 #define mmMPCC_OGAM2_MPCC_OGAM_LUT_DATA 0x0202 14310 #define mmMPCC_OGAM2_MPCC_OGAM_LUT_DATA_BASE_IDX 3 14311 #define mmMPCC_OGAM2_MPCC_OGAM_LUT_CONTROL 0x0203 14312 #define mmMPCC_OGAM2_MPCC_OGAM_LUT_CONTROL_BASE_IDX 3 14313 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B 0x0204 14314 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 3 14315 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G 0x0205 14316 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 3 14317 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R 0x0206 14318 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 3 14319 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B 0x0207 14320 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3 14321 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G 0x0208 14322 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3 14323 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R 0x0209 14324 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3 14325 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_B 0x020a 14326 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 3 14327 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_G 0x020b 14328 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 3 14329 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_R 0x020c 14330 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 3 14331 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B 0x020d 14332 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 3 14333 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B 0x020e 14334 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 3 14335 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G 0x020f 14336 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 3 14337 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G 0x0210 14338 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 3 14339 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R 0x0211 14340 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 3 14341 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R 0x0212 14342 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 3 14343 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_B 0x0213 14344 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX 3 14345 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_G 0x0214 14346 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX 3 14347 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_R 0x0215 14348 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX 3 14349 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1 0x0216 14350 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 3 14351 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3 0x0217 14352 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 3 14353 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5 0x0218 14354 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 3 14355 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7 0x0219 14356 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 3 14357 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9 0x021a 14358 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 3 14359 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11 0x021b 14360 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 3 14361 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13 0x021c 14362 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 3 14363 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15 0x021d 14364 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 3 14365 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17 0x021e 14366 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 3 14367 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19 0x021f 14368 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 3 14369 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21 0x0220 14370 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 3 14371 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23 0x0221 14372 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 3 14373 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25 0x0222 14374 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 3 14375 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27 0x0223 14376 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 3 14377 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29 0x0224 14378 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 3 14379 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31 0x0225 14380 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 3 14381 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33 0x0226 14382 #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 3 14383 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B 0x0227 14384 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 3 14385 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G 0x0228 14386 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 3 14387 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R 0x0229 14388 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 3 14389 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B 0x022a 14390 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3 14391 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G 0x022b 14392 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3 14393 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R 0x022c 14394 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3 14395 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_B 0x022d 14396 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 3 14397 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_G 0x022e 14398 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 3 14399 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_R 0x022f 14400 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 3 14401 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B 0x0230 14402 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 3 14403 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B 0x0231 14404 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 3 14405 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G 0x0232 14406 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 3 14407 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G 0x0233 14408 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 3 14409 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R 0x0234 14410 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 3 14411 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R 0x0235 14412 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 3 14413 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_B 0x0236 14414 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX 3 14415 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_G 0x0237 14416 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX 3 14417 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_R 0x0238 14418 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX 3 14419 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1 0x0239 14420 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 3 14421 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3 0x023a 14422 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 3 14423 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5 0x023b 14424 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 3 14425 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7 0x023c 14426 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 3 14427 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9 0x023d 14428 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 3 14429 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11 0x023e 14430 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 3 14431 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13 0x023f 14432 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 3 14433 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15 0x0240 14434 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 3 14435 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17 0x0241 14436 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 3 14437 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19 0x0242 14438 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 3 14439 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21 0x0243 14440 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 3 14441 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23 0x0244 14442 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 3 14443 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25 0x0245 14444 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 3 14445 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27 0x0246 14446 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 3 14447 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29 0x0247 14448 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 3 14449 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31 0x0248 14450 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 3 14451 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33 0x0249 14452 #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 3 14453 #define mmMPCC_OGAM2_MPCC_GAMUT_REMAP_COEF_FORMAT 0x024a 14454 #define mmMPCC_OGAM2_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3 14455 #define mmMPCC_OGAM2_MPCC_GAMUT_REMAP_MODE 0x024b 14456 #define mmMPCC_OGAM2_MPCC_GAMUT_REMAP_MODE_BASE_IDX 3 14457 #define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A 0x024c 14458 #define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX 3 14459 #define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A 0x024d 14460 #define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX 3 14461 #define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A 0x024e 14462 #define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX 3 14463 #define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A 0x024f 14464 #define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX 3 14465 #define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A 0x0250 14466 #define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX 3 14467 #define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A 0x0251 14468 #define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX 3 14469 #define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B 0x0252 14470 #define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX 3 14471 #define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B 0x0253 14472 #define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX 3 14473 #define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B 0x0254 14474 #define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX 3 14475 #define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B 0x0255 14476 #define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX 3 14477 #define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B 0x0256 14478 #define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX 3 14479 #define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B 0x0257 14480 #define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX 3 14481 14482 14483 // addressBlock: dce_dc_mpc_mpcc_ogam3_dispdec 14484 // base address: 0x600 14485 #define mmMPCC_OGAM3_MPCC_OGAM_CONTROL 0x0280 14486 #define mmMPCC_OGAM3_MPCC_OGAM_CONTROL_BASE_IDX 3 14487 #define mmMPCC_OGAM3_MPCC_OGAM_LUT_INDEX 0x0281 14488 #define mmMPCC_OGAM3_MPCC_OGAM_LUT_INDEX_BASE_IDX 3 14489 #define mmMPCC_OGAM3_MPCC_OGAM_LUT_DATA 0x0282 14490 #define mmMPCC_OGAM3_MPCC_OGAM_LUT_DATA_BASE_IDX 3 14491 #define mmMPCC_OGAM3_MPCC_OGAM_LUT_CONTROL 0x0283 14492 #define mmMPCC_OGAM3_MPCC_OGAM_LUT_CONTROL_BASE_IDX 3 14493 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B 0x0284 14494 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 3 14495 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G 0x0285 14496 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 3 14497 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R 0x0286 14498 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 3 14499 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B 0x0287 14500 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3 14501 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G 0x0288 14502 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3 14503 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R 0x0289 14504 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3 14505 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B 0x028a 14506 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 3 14507 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G 0x028b 14508 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 3 14509 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_R 0x028c 14510 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 3 14511 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B 0x028d 14512 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 3 14513 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B 0x028e 14514 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 3 14515 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G 0x028f 14516 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 3 14517 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G 0x0290 14518 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 3 14519 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R 0x0291 14520 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 3 14521 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R 0x0292 14522 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 3 14523 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_B 0x0293 14524 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX 3 14525 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_G 0x0294 14526 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX 3 14527 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_R 0x0295 14528 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX 3 14529 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1 0x0296 14530 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 3 14531 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3 0x0297 14532 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 3 14533 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5 0x0298 14534 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 3 14535 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7 0x0299 14536 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 3 14537 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9 0x029a 14538 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 3 14539 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11 0x029b 14540 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 3 14541 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13 0x029c 14542 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 3 14543 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15 0x029d 14544 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 3 14545 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17 0x029e 14546 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 3 14547 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19 0x029f 14548 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 3 14549 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21 0x02a0 14550 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 3 14551 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23 0x02a1 14552 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 3 14553 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25 0x02a2 14554 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 3 14555 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27 0x02a3 14556 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 3 14557 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29 0x02a4 14558 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 3 14559 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31 0x02a5 14560 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 3 14561 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33 0x02a6 14562 #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 3 14563 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B 0x02a7 14564 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 3 14565 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G 0x02a8 14566 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 3 14567 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R 0x02a9 14568 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 3 14569 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B 0x02aa 14570 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3 14571 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G 0x02ab 14572 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3 14573 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R 0x02ac 14574 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3 14575 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_B 0x02ad 14576 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 3 14577 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_G 0x02ae 14578 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 3 14579 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_R 0x02af 14580 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 3 14581 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B 0x02b0 14582 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 3 14583 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B 0x02b1 14584 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 3 14585 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G 0x02b2 14586 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 3 14587 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G 0x02b3 14588 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 3 14589 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R 0x02b4 14590 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 3 14591 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R 0x02b5 14592 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 3 14593 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_B 0x02b6 14594 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX 3 14595 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_G 0x02b7 14596 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX 3 14597 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_R 0x02b8 14598 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX 3 14599 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1 0x02b9 14600 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 3 14601 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3 0x02ba 14602 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 3 14603 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5 0x02bb 14604 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 3 14605 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7 0x02bc 14606 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 3 14607 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9 0x02bd 14608 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 3 14609 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11 0x02be 14610 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 3 14611 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13 0x02bf 14612 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 3 14613 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15 0x02c0 14614 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 3 14615 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17 0x02c1 14616 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 3 14617 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19 0x02c2 14618 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 3 14619 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21 0x02c3 14620 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 3 14621 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23 0x02c4 14622 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 3 14623 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25 0x02c5 14624 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 3 14625 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27 0x02c6 14626 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 3 14627 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29 0x02c7 14628 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 3 14629 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31 0x02c8 14630 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 3 14631 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33 0x02c9 14632 #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 3 14633 #define mmMPCC_OGAM3_MPCC_GAMUT_REMAP_COEF_FORMAT 0x02ca 14634 #define mmMPCC_OGAM3_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3 14635 #define mmMPCC_OGAM3_MPCC_GAMUT_REMAP_MODE 0x02cb 14636 #define mmMPCC_OGAM3_MPCC_GAMUT_REMAP_MODE_BASE_IDX 3 14637 #define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A 0x02cc 14638 #define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX 3 14639 #define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A 0x02cd 14640 #define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX 3 14641 #define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A 0x02ce 14642 #define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX 3 14643 #define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A 0x02cf 14644 #define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX 3 14645 #define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A 0x02d0 14646 #define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX 3 14647 #define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A 0x02d1 14648 #define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX 3 14649 #define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B 0x02d2 14650 #define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX 3 14651 #define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B 0x02d3 14652 #define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX 3 14653 #define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B 0x02d4 14654 #define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX 3 14655 #define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B 0x02d5 14656 #define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX 3 14657 #define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B 0x02d6 14658 #define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX 3 14659 #define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B 0x02d7 14660 #define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX 3 14661 14662 14663 // addressBlock: dce_dc_mpc_mpcc_ogam4_dispdec 14664 // base address: 0x800 14665 #define mmMPCC_OGAM4_MPCC_OGAM_CONTROL 0x0300 14666 #define mmMPCC_OGAM4_MPCC_OGAM_CONTROL_BASE_IDX 3 14667 #define mmMPCC_OGAM4_MPCC_OGAM_LUT_INDEX 0x0301 14668 #define mmMPCC_OGAM4_MPCC_OGAM_LUT_INDEX_BASE_IDX 3 14669 #define mmMPCC_OGAM4_MPCC_OGAM_LUT_DATA 0x0302 14670 #define mmMPCC_OGAM4_MPCC_OGAM_LUT_DATA_BASE_IDX 3 14671 #define mmMPCC_OGAM4_MPCC_OGAM_LUT_CONTROL 0x0303 14672 #define mmMPCC_OGAM4_MPCC_OGAM_LUT_CONTROL_BASE_IDX 3 14673 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_B 0x0304 14674 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 3 14675 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_G 0x0305 14676 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 3 14677 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_R 0x0306 14678 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 3 14679 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B 0x0307 14680 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3 14681 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G 0x0308 14682 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3 14683 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R 0x0309 14684 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3 14685 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_BASE_CNTL_B 0x030a 14686 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 3 14687 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_BASE_CNTL_G 0x030b 14688 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 3 14689 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_BASE_CNTL_R 0x030c 14690 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 3 14691 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_B 0x030d 14692 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 3 14693 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_B 0x030e 14694 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 3 14695 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_G 0x030f 14696 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 3 14697 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_G 0x0310 14698 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 3 14699 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_R 0x0311 14700 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 3 14701 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_R 0x0312 14702 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 3 14703 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_OFFSET_B 0x0313 14704 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX 3 14705 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_OFFSET_G 0x0314 14706 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX 3 14707 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_OFFSET_R 0x0315 14708 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX 3 14709 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_0_1 0x0316 14710 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 3 14711 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_2_3 0x0317 14712 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 3 14713 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_4_5 0x0318 14714 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 3 14715 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_6_7 0x0319 14716 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 3 14717 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_8_9 0x031a 14718 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 3 14719 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_10_11 0x031b 14720 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 3 14721 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_12_13 0x031c 14722 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 3 14723 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_14_15 0x031d 14724 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 3 14725 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_16_17 0x031e 14726 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 3 14727 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_18_19 0x031f 14728 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 3 14729 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_20_21 0x0320 14730 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 3 14731 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_22_23 0x0321 14732 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 3 14733 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_24_25 0x0322 14734 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 3 14735 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_26_27 0x0323 14736 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 3 14737 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_28_29 0x0324 14738 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 3 14739 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_30_31 0x0325 14740 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 3 14741 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_32_33 0x0326 14742 #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 3 14743 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_B 0x0327 14744 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 3 14745 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_G 0x0328 14746 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 3 14747 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_R 0x0329 14748 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 3 14749 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B 0x032a 14750 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3 14751 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G 0x032b 14752 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3 14753 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R 0x032c 14754 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3 14755 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_BASE_CNTL_B 0x032d 14756 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 3 14757 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_BASE_CNTL_G 0x032e 14758 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 3 14759 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_BASE_CNTL_R 0x032f 14760 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 3 14761 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_B 0x0330 14762 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 3 14763 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_B 0x0331 14764 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 3 14765 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_G 0x0332 14766 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 3 14767 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_G 0x0333 14768 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 3 14769 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_R 0x0334 14770 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 3 14771 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_R 0x0335 14772 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 3 14773 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_OFFSET_B 0x0336 14774 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX 3 14775 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_OFFSET_G 0x0337 14776 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX 3 14777 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_OFFSET_R 0x0338 14778 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX 3 14779 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_0_1 0x0339 14780 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 3 14781 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_2_3 0x033a 14782 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 3 14783 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_4_5 0x033b 14784 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 3 14785 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_6_7 0x033c 14786 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 3 14787 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_8_9 0x033d 14788 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 3 14789 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_10_11 0x033e 14790 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 3 14791 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_12_13 0x033f 14792 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 3 14793 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_14_15 0x0340 14794 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 3 14795 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_16_17 0x0341 14796 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 3 14797 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_18_19 0x0342 14798 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 3 14799 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_20_21 0x0343 14800 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 3 14801 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_22_23 0x0344 14802 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 3 14803 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_24_25 0x0345 14804 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 3 14805 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_26_27 0x0346 14806 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 3 14807 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_28_29 0x0347 14808 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 3 14809 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_30_31 0x0348 14810 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 3 14811 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_32_33 0x0349 14812 #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 3 14813 #define mmMPCC_OGAM4_MPCC_GAMUT_REMAP_COEF_FORMAT 0x034a 14814 #define mmMPCC_OGAM4_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3 14815 #define mmMPCC_OGAM4_MPCC_GAMUT_REMAP_MODE 0x034b 14816 #define mmMPCC_OGAM4_MPCC_GAMUT_REMAP_MODE_BASE_IDX 3 14817 #define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C11_C12_A 0x034c 14818 #define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX 3 14819 #define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C13_C14_A 0x034d 14820 #define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX 3 14821 #define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C21_C22_A 0x034e 14822 #define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX 3 14823 #define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C23_C24_A 0x034f 14824 #define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX 3 14825 #define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C31_C32_A 0x0350 14826 #define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX 3 14827 #define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C33_C34_A 0x0351 14828 #define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX 3 14829 #define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C11_C12_B 0x0352 14830 #define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX 3 14831 #define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C13_C14_B 0x0353 14832 #define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX 3 14833 #define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C21_C22_B 0x0354 14834 #define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX 3 14835 #define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C23_C24_B 0x0355 14836 #define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX 3 14837 #define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C31_C32_B 0x0356 14838 #define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX 3 14839 #define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C33_C34_B 0x0357 14840 #define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX 3 14841 14842 14843 // addressBlock: dce_dc_mpc_mpcc_ogam5_dispdec 14844 // base address: 0xa00 14845 #define mmMPCC_OGAM5_MPCC_OGAM_CONTROL 0x0380 14846 #define mmMPCC_OGAM5_MPCC_OGAM_CONTROL_BASE_IDX 3 14847 #define mmMPCC_OGAM5_MPCC_OGAM_LUT_INDEX 0x0381 14848 #define mmMPCC_OGAM5_MPCC_OGAM_LUT_INDEX_BASE_IDX 3 14849 #define mmMPCC_OGAM5_MPCC_OGAM_LUT_DATA 0x0382 14850 #define mmMPCC_OGAM5_MPCC_OGAM_LUT_DATA_BASE_IDX 3 14851 #define mmMPCC_OGAM5_MPCC_OGAM_LUT_CONTROL 0x0383 14852 #define mmMPCC_OGAM5_MPCC_OGAM_LUT_CONTROL_BASE_IDX 3 14853 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_B 0x0384 14854 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 3 14855 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_G 0x0385 14856 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 3 14857 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_R 0x0386 14858 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 3 14859 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B 0x0387 14860 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3 14861 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G 0x0388 14862 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3 14863 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R 0x0389 14864 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3 14865 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_START_BASE_CNTL_B 0x038a 14866 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 3 14867 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_START_BASE_CNTL_G 0x038b 14868 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 3 14869 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_START_BASE_CNTL_R 0x038c 14870 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 3 14871 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL1_B 0x038d 14872 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 3 14873 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_B 0x038e 14874 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 3 14875 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL1_G 0x038f 14876 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 3 14877 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_G 0x0390 14878 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 3 14879 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL1_R 0x0391 14880 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 3 14881 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_R 0x0392 14882 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 3 14883 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_OFFSET_B 0x0393 14884 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX 3 14885 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_OFFSET_G 0x0394 14886 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX 3 14887 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_OFFSET_R 0x0395 14888 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX 3 14889 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_0_1 0x0396 14890 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 3 14891 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_2_3 0x0397 14892 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 3 14893 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_4_5 0x0398 14894 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 3 14895 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_6_7 0x0399 14896 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 3 14897 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_8_9 0x039a 14898 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 3 14899 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_10_11 0x039b 14900 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 3 14901 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_12_13 0x039c 14902 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 3 14903 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_14_15 0x039d 14904 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 3 14905 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_16_17 0x039e 14906 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 3 14907 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_18_19 0x039f 14908 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 3 14909 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_20_21 0x03a0 14910 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 3 14911 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_22_23 0x03a1 14912 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 3 14913 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_24_25 0x03a2 14914 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 3 14915 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_26_27 0x03a3 14916 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 3 14917 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_28_29 0x03a4 14918 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 3 14919 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_30_31 0x03a5 14920 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 3 14921 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_32_33 0x03a6 14922 #define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 3 14923 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_B 0x03a7 14924 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 3 14925 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_G 0x03a8 14926 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 3 14927 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_R 0x03a9 14928 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 3 14929 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B 0x03aa 14930 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3 14931 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G 0x03ab 14932 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3 14933 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R 0x03ac 14934 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3 14935 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_START_BASE_CNTL_B 0x03ad 14936 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 3 14937 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_START_BASE_CNTL_G 0x03ae 14938 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 3 14939 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_START_BASE_CNTL_R 0x03af 14940 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 3 14941 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL1_B 0x03b0 14942 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 3 14943 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_B 0x03b1 14944 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 3 14945 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL1_G 0x03b2 14946 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 3 14947 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_G 0x03b3 14948 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 3 14949 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL1_R 0x03b4 14950 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 3 14951 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_R 0x03b5 14952 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 3 14953 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_OFFSET_B 0x03b6 14954 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX 3 14955 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_OFFSET_G 0x03b7 14956 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX 3 14957 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_OFFSET_R 0x03b8 14958 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX 3 14959 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_0_1 0x03b9 14960 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 3 14961 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_2_3 0x03ba 14962 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 3 14963 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_4_5 0x03bb 14964 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 3 14965 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_6_7 0x03bc 14966 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 3 14967 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_8_9 0x03bd 14968 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 3 14969 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_10_11 0x03be 14970 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 3 14971 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_12_13 0x03bf 14972 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 3 14973 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_14_15 0x03c0 14974 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 3 14975 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_16_17 0x03c1 14976 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 3 14977 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_18_19 0x03c2 14978 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 3 14979 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_20_21 0x03c3 14980 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 3 14981 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_22_23 0x03c4 14982 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 3 14983 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_24_25 0x03c5 14984 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 3 14985 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_26_27 0x03c6 14986 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 3 14987 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_28_29 0x03c7 14988 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 3 14989 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_30_31 0x03c8 14990 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 3 14991 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_32_33 0x03c9 14992 #define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 3 14993 #define mmMPCC_OGAM5_MPCC_GAMUT_REMAP_COEF_FORMAT 0x03ca 14994 #define mmMPCC_OGAM5_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3 14995 #define mmMPCC_OGAM5_MPCC_GAMUT_REMAP_MODE 0x03cb 14996 #define mmMPCC_OGAM5_MPCC_GAMUT_REMAP_MODE_BASE_IDX 3 14997 #define mmMPCC_OGAM5_MPC_GAMUT_REMAP_C11_C12_A 0x03cc 14998 #define mmMPCC_OGAM5_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX 3 14999 #define mmMPCC_OGAM5_MPC_GAMUT_REMAP_C13_C14_A 0x03cd 15000 #define mmMPCC_OGAM5_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX 3 15001 #define mmMPCC_OGAM5_MPC_GAMUT_REMAP_C21_C22_A 0x03ce 15002 #define mmMPCC_OGAM5_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX 3 15003 #define mmMPCC_OGAM5_MPC_GAMUT_REMAP_C23_C24_A 0x03cf 15004 #define mmMPCC_OGAM5_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX 3 15005 #define mmMPCC_OGAM5_MPC_GAMUT_REMAP_C31_C32_A 0x03d0 15006 #define mmMPCC_OGAM5_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX 3 15007 #define mmMPCC_OGAM5_MPC_GAMUT_REMAP_C33_C34_A 0x03d1 15008 #define mmMPCC_OGAM5_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX 3 15009 #define mmMPCC_OGAM5_MPC_GAMUT_REMAP_C11_C12_B 0x03d2 15010 #define mmMPCC_OGAM5_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX 3 15011 #define mmMPCC_OGAM5_MPC_GAMUT_REMAP_C13_C14_B 0x03d3 15012 #define mmMPCC_OGAM5_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX 3 15013 #define mmMPCC_OGAM5_MPC_GAMUT_REMAP_C21_C22_B 0x03d4 15014 #define mmMPCC_OGAM5_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX 3 15015 #define mmMPCC_OGAM5_MPC_GAMUT_REMAP_C23_C24_B 0x03d5 15016 #define mmMPCC_OGAM5_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX 3 15017 #define mmMPCC_OGAM5_MPC_GAMUT_REMAP_C31_C32_B 0x03d6 15018 #define mmMPCC_OGAM5_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX 3 15019 #define mmMPCC_OGAM5_MPC_GAMUT_REMAP_C33_C34_B 0x03d7 15020 #define mmMPCC_OGAM5_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX 3 15021 15022 15023 // addressBlock: dce_dc_mpc_mpc_cfg_dispdec 15024 // base address: 0x0 15025 #define mmMPC_CLOCK_CONTROL 0x0500 15026 #define mmMPC_CLOCK_CONTROL_BASE_IDX 3 15027 #define mmMPC_SOFT_RESET 0x0501 15028 #define mmMPC_SOFT_RESET_BASE_IDX 3 15029 #define mmMPC_CRC_CTRL 0x0502 15030 #define mmMPC_CRC_CTRL_BASE_IDX 3 15031 #define mmMPC_CRC_SEL_CONTROL 0x0503 15032 #define mmMPC_CRC_SEL_CONTROL_BASE_IDX 3 15033 #define mmMPC_CRC_RESULT_AR 0x0504 15034 #define mmMPC_CRC_RESULT_AR_BASE_IDX 3 15035 #define mmMPC_CRC_RESULT_GB 0x0505 15036 #define mmMPC_CRC_RESULT_GB_BASE_IDX 3 15037 #define mmMPC_CRC_RESULT_C 0x0506 15038 #define mmMPC_CRC_RESULT_C_BASE_IDX 3 15039 #define mmMPC_PERFMON_EVENT_CTRL 0x0509 15040 #define mmMPC_PERFMON_EVENT_CTRL_BASE_IDX 3 15041 #define mmMPC_BYPASS_BG_AR 0x050a 15042 #define mmMPC_BYPASS_BG_AR_BASE_IDX 3 15043 #define mmMPC_BYPASS_BG_GB 0x050b 15044 #define mmMPC_BYPASS_BG_GB_BASE_IDX 3 15045 #define mmMPC_HOST_READ_CONTROL 0x050c 15046 #define mmMPC_HOST_READ_CONTROL_BASE_IDX 3 15047 #define mmMPC_DPP_PENDING_STATUS 0x050d 15048 #define mmMPC_DPP_PENDING_STATUS_BASE_IDX 3 15049 #define mmMPC_PENDING_STATUS_MISC 0x050e 15050 #define mmMPC_PENDING_STATUS_MISC_BASE_IDX 3 15051 #define mmADR_CFG_CUR_VUPDATE_LOCK_SET0 0x050f 15052 #define mmADR_CFG_CUR_VUPDATE_LOCK_SET0_BASE_IDX 3 15053 #define mmADR_CFG_VUPDATE_LOCK_SET0 0x0510 15054 #define mmADR_CFG_VUPDATE_LOCK_SET0_BASE_IDX 3 15055 #define mmADR_VUPDATE_LOCK_SET0 0x0511 15056 #define mmADR_VUPDATE_LOCK_SET0_BASE_IDX 3 15057 #define mmCFG_VUPDATE_LOCK_SET0 0x0512 15058 #define mmCFG_VUPDATE_LOCK_SET0_BASE_IDX 3 15059 #define mmCUR_VUPDATE_LOCK_SET0 0x0513 15060 #define mmCUR_VUPDATE_LOCK_SET0_BASE_IDX 3 15061 #define mmADR_CFG_CUR_VUPDATE_LOCK_SET1 0x0514 15062 #define mmADR_CFG_CUR_VUPDATE_LOCK_SET1_BASE_IDX 3 15063 #define mmADR_CFG_VUPDATE_LOCK_SET1 0x0515 15064 #define mmADR_CFG_VUPDATE_LOCK_SET1_BASE_IDX 3 15065 #define mmADR_VUPDATE_LOCK_SET1 0x0516 15066 #define mmADR_VUPDATE_LOCK_SET1_BASE_IDX 3 15067 #define mmCFG_VUPDATE_LOCK_SET1 0x0517 15068 #define mmCFG_VUPDATE_LOCK_SET1_BASE_IDX 3 15069 #define mmCUR_VUPDATE_LOCK_SET1 0x0518 15070 #define mmCUR_VUPDATE_LOCK_SET1_BASE_IDX 3 15071 #define mmADR_CFG_CUR_VUPDATE_LOCK_SET2 0x0519 15072 #define mmADR_CFG_CUR_VUPDATE_LOCK_SET2_BASE_IDX 3 15073 #define mmADR_CFG_VUPDATE_LOCK_SET2 0x051a 15074 #define mmADR_CFG_VUPDATE_LOCK_SET2_BASE_IDX 3 15075 #define mmADR_VUPDATE_LOCK_SET2 0x051b 15076 #define mmADR_VUPDATE_LOCK_SET2_BASE_IDX 3 15077 #define mmCFG_VUPDATE_LOCK_SET2 0x051c 15078 #define mmCFG_VUPDATE_LOCK_SET2_BASE_IDX 3 15079 #define mmCUR_VUPDATE_LOCK_SET2 0x051d 15080 #define mmCUR_VUPDATE_LOCK_SET2_BASE_IDX 3 15081 #define mmADR_CFG_CUR_VUPDATE_LOCK_SET3 0x051e 15082 #define mmADR_CFG_CUR_VUPDATE_LOCK_SET3_BASE_IDX 3 15083 #define mmADR_CFG_VUPDATE_LOCK_SET3 0x051f 15084 #define mmADR_CFG_VUPDATE_LOCK_SET3_BASE_IDX 3 15085 #define mmADR_VUPDATE_LOCK_SET3 0x0520 15086 #define mmADR_VUPDATE_LOCK_SET3_BASE_IDX 3 15087 #define mmCFG_VUPDATE_LOCK_SET3 0x0521 15088 #define mmCFG_VUPDATE_LOCK_SET3_BASE_IDX 3 15089 #define mmCUR_VUPDATE_LOCK_SET3 0x0522 15090 #define mmCUR_VUPDATE_LOCK_SET3_BASE_IDX 3 15091 #define mmADR_CFG_CUR_VUPDATE_LOCK_SET4 0x0523 15092 #define mmADR_CFG_CUR_VUPDATE_LOCK_SET4_BASE_IDX 3 15093 #define mmADR_CFG_VUPDATE_LOCK_SET4 0x0524 15094 #define mmADR_CFG_VUPDATE_LOCK_SET4_BASE_IDX 3 15095 #define mmADR_VUPDATE_LOCK_SET4 0x0525 15096 #define mmADR_VUPDATE_LOCK_SET4_BASE_IDX 3 15097 #define mmCFG_VUPDATE_LOCK_SET4 0x0526 15098 #define mmCFG_VUPDATE_LOCK_SET4_BASE_IDX 3 15099 #define mmCUR_VUPDATE_LOCK_SET4 0x0527 15100 #define mmCUR_VUPDATE_LOCK_SET4_BASE_IDX 3 15101 #define mmADR_CFG_CUR_VUPDATE_LOCK_SET5 0x0528 15102 #define mmADR_CFG_CUR_VUPDATE_LOCK_SET5_BASE_IDX 3 15103 #define mmADR_CFG_VUPDATE_LOCK_SET5 0x0529 15104 #define mmADR_CFG_VUPDATE_LOCK_SET5_BASE_IDX 3 15105 #define mmADR_VUPDATE_LOCK_SET5 0x052a 15106 #define mmADR_VUPDATE_LOCK_SET5_BASE_IDX 3 15107 #define mmCFG_VUPDATE_LOCK_SET5 0x052b 15108 #define mmCFG_VUPDATE_LOCK_SET5_BASE_IDX 3 15109 #define mmCUR_VUPDATE_LOCK_SET5 0x052c 15110 #define mmCUR_VUPDATE_LOCK_SET5_BASE_IDX 3 15111 #define mmMPC_DWB0_MUX 0x055c 15112 #define mmMPC_DWB0_MUX_BASE_IDX 3 15113 15114 15115 // addressBlock: dce_dc_mpc_mpc_ocsc_dispdec 15116 // base address: 0x0 15117 #define mmMPC_OUT0_MUX 0x0580 15118 #define mmMPC_OUT0_MUX_BASE_IDX 3 15119 #define mmMPC_OUT0_DENORM_CONTROL 0x0581 15120 #define mmMPC_OUT0_DENORM_CONTROL_BASE_IDX 3 15121 #define mmMPC_OUT0_DENORM_CLAMP_G_Y 0x0582 15122 #define mmMPC_OUT0_DENORM_CLAMP_G_Y_BASE_IDX 3 15123 #define mmMPC_OUT0_DENORM_CLAMP_B_CB 0x0583 15124 #define mmMPC_OUT0_DENORM_CLAMP_B_CB_BASE_IDX 3 15125 #define mmMPC_OUT1_MUX 0x0584 15126 #define mmMPC_OUT1_MUX_BASE_IDX 3 15127 #define mmMPC_OUT1_DENORM_CONTROL 0x0585 15128 #define mmMPC_OUT1_DENORM_CONTROL_BASE_IDX 3 15129 #define mmMPC_OUT1_DENORM_CLAMP_G_Y 0x0586 15130 #define mmMPC_OUT1_DENORM_CLAMP_G_Y_BASE_IDX 3 15131 #define mmMPC_OUT1_DENORM_CLAMP_B_CB 0x0587 15132 #define mmMPC_OUT1_DENORM_CLAMP_B_CB_BASE_IDX 3 15133 #define mmMPC_OUT2_MUX 0x0588 15134 #define mmMPC_OUT2_MUX_BASE_IDX 3 15135 #define mmMPC_OUT2_DENORM_CONTROL 0x0589 15136 #define mmMPC_OUT2_DENORM_CONTROL_BASE_IDX 3 15137 #define mmMPC_OUT2_DENORM_CLAMP_G_Y 0x058a 15138 #define mmMPC_OUT2_DENORM_CLAMP_G_Y_BASE_IDX 3 15139 #define mmMPC_OUT2_DENORM_CLAMP_B_CB 0x058b 15140 #define mmMPC_OUT2_DENORM_CLAMP_B_CB_BASE_IDX 3 15141 #define mmMPC_OUT3_MUX 0x058c 15142 #define mmMPC_OUT3_MUX_BASE_IDX 3 15143 #define mmMPC_OUT3_DENORM_CONTROL 0x058d 15144 #define mmMPC_OUT3_DENORM_CONTROL_BASE_IDX 3 15145 #define mmMPC_OUT3_DENORM_CLAMP_G_Y 0x058e 15146 #define mmMPC_OUT3_DENORM_CLAMP_G_Y_BASE_IDX 3 15147 #define mmMPC_OUT3_DENORM_CLAMP_B_CB 0x058f 15148 #define mmMPC_OUT3_DENORM_CLAMP_B_CB_BASE_IDX 3 15149 #define mmMPC_OUT4_MUX 0x0590 15150 #define mmMPC_OUT4_MUX_BASE_IDX 3 15151 #define mmMPC_OUT4_DENORM_CONTROL 0x0591 15152 #define mmMPC_OUT4_DENORM_CONTROL_BASE_IDX 3 15153 #define mmMPC_OUT4_DENORM_CLAMP_G_Y 0x0592 15154 #define mmMPC_OUT4_DENORM_CLAMP_G_Y_BASE_IDX 3 15155 #define mmMPC_OUT4_DENORM_CLAMP_B_CB 0x0593 15156 #define mmMPC_OUT4_DENORM_CLAMP_B_CB_BASE_IDX 3 15157 #define mmMPC_OUT5_MUX 0x0594 15158 #define mmMPC_OUT5_MUX_BASE_IDX 3 15159 #define mmMPC_OUT5_DENORM_CONTROL 0x0595 15160 #define mmMPC_OUT5_DENORM_CONTROL_BASE_IDX 3 15161 #define mmMPC_OUT5_DENORM_CLAMP_G_Y 0x0596 15162 #define mmMPC_OUT5_DENORM_CLAMP_G_Y_BASE_IDX 3 15163 #define mmMPC_OUT5_DENORM_CLAMP_B_CB 0x0597 15164 #define mmMPC_OUT5_DENORM_CLAMP_B_CB_BASE_IDX 3 15165 #define mmMPC_OUT_CSC_COEF_FORMAT 0x0598 15166 #define mmMPC_OUT_CSC_COEF_FORMAT_BASE_IDX 3 15167 #define mmMPC_OUT0_CSC_MODE 0x0599 15168 #define mmMPC_OUT0_CSC_MODE_BASE_IDX 3 15169 #define mmMPC_OUT0_CSC_C11_C12_A 0x059a 15170 #define mmMPC_OUT0_CSC_C11_C12_A_BASE_IDX 3 15171 #define mmMPC_OUT0_CSC_C13_C14_A 0x059b 15172 #define mmMPC_OUT0_CSC_C13_C14_A_BASE_IDX 3 15173 #define mmMPC_OUT0_CSC_C21_C22_A 0x059c 15174 #define mmMPC_OUT0_CSC_C21_C22_A_BASE_IDX 3 15175 #define mmMPC_OUT0_CSC_C23_C24_A 0x059d 15176 #define mmMPC_OUT0_CSC_C23_C24_A_BASE_IDX 3 15177 #define mmMPC_OUT0_CSC_C31_C32_A 0x059e 15178 #define mmMPC_OUT0_CSC_C31_C32_A_BASE_IDX 3 15179 #define mmMPC_OUT0_CSC_C33_C34_A 0x059f 15180 #define mmMPC_OUT0_CSC_C33_C34_A_BASE_IDX 3 15181 #define mmMPC_OUT0_CSC_C11_C12_B 0x05a0 15182 #define mmMPC_OUT0_CSC_C11_C12_B_BASE_IDX 3 15183 #define mmMPC_OUT0_CSC_C13_C14_B 0x05a1 15184 #define mmMPC_OUT0_CSC_C13_C14_B_BASE_IDX 3 15185 #define mmMPC_OUT0_CSC_C21_C22_B 0x05a2 15186 #define mmMPC_OUT0_CSC_C21_C22_B_BASE_IDX 3 15187 #define mmMPC_OUT0_CSC_C23_C24_B 0x05a3 15188 #define mmMPC_OUT0_CSC_C23_C24_B_BASE_IDX 3 15189 #define mmMPC_OUT0_CSC_C31_C32_B 0x05a4 15190 #define mmMPC_OUT0_CSC_C31_C32_B_BASE_IDX 3 15191 #define mmMPC_OUT0_CSC_C33_C34_B 0x05a5 15192 #define mmMPC_OUT0_CSC_C33_C34_B_BASE_IDX 3 15193 #define mmMPC_OUT1_CSC_MODE 0x05a6 15194 #define mmMPC_OUT1_CSC_MODE_BASE_IDX 3 15195 #define mmMPC_OUT1_CSC_C11_C12_A 0x05a7 15196 #define mmMPC_OUT1_CSC_C11_C12_A_BASE_IDX 3 15197 #define mmMPC_OUT1_CSC_C13_C14_A 0x05a8 15198 #define mmMPC_OUT1_CSC_C13_C14_A_BASE_IDX 3 15199 #define mmMPC_OUT1_CSC_C21_C22_A 0x05a9 15200 #define mmMPC_OUT1_CSC_C21_C22_A_BASE_IDX 3 15201 #define mmMPC_OUT1_CSC_C23_C24_A 0x05aa 15202 #define mmMPC_OUT1_CSC_C23_C24_A_BASE_IDX 3 15203 #define mmMPC_OUT1_CSC_C31_C32_A 0x05ab 15204 #define mmMPC_OUT1_CSC_C31_C32_A_BASE_IDX 3 15205 #define mmMPC_OUT1_CSC_C33_C34_A 0x05ac 15206 #define mmMPC_OUT1_CSC_C33_C34_A_BASE_IDX 3 15207 #define mmMPC_OUT1_CSC_C11_C12_B 0x05ad 15208 #define mmMPC_OUT1_CSC_C11_C12_B_BASE_IDX 3 15209 #define mmMPC_OUT1_CSC_C13_C14_B 0x05ae 15210 #define mmMPC_OUT1_CSC_C13_C14_B_BASE_IDX 3 15211 #define mmMPC_OUT1_CSC_C21_C22_B 0x05af 15212 #define mmMPC_OUT1_CSC_C21_C22_B_BASE_IDX 3 15213 #define mmMPC_OUT1_CSC_C23_C24_B 0x05b0 15214 #define mmMPC_OUT1_CSC_C23_C24_B_BASE_IDX 3 15215 #define mmMPC_OUT1_CSC_C31_C32_B 0x05b1 15216 #define mmMPC_OUT1_CSC_C31_C32_B_BASE_IDX 3 15217 #define mmMPC_OUT1_CSC_C33_C34_B 0x05b2 15218 #define mmMPC_OUT1_CSC_C33_C34_B_BASE_IDX 3 15219 #define mmMPC_OUT2_CSC_MODE 0x05b3 15220 #define mmMPC_OUT2_CSC_MODE_BASE_IDX 3 15221 #define mmMPC_OUT2_CSC_C11_C12_A 0x05b4 15222 #define mmMPC_OUT2_CSC_C11_C12_A_BASE_IDX 3 15223 #define mmMPC_OUT2_CSC_C13_C14_A 0x05b5 15224 #define mmMPC_OUT2_CSC_C13_C14_A_BASE_IDX 3 15225 #define mmMPC_OUT2_CSC_C21_C22_A 0x05b6 15226 #define mmMPC_OUT2_CSC_C21_C22_A_BASE_IDX 3 15227 #define mmMPC_OUT2_CSC_C23_C24_A 0x05b7 15228 #define mmMPC_OUT2_CSC_C23_C24_A_BASE_IDX 3 15229 #define mmMPC_OUT2_CSC_C31_C32_A 0x05b8 15230 #define mmMPC_OUT2_CSC_C31_C32_A_BASE_IDX 3 15231 #define mmMPC_OUT2_CSC_C33_C34_A 0x05b9 15232 #define mmMPC_OUT2_CSC_C33_C34_A_BASE_IDX 3 15233 #define mmMPC_OUT2_CSC_C11_C12_B 0x05ba 15234 #define mmMPC_OUT2_CSC_C11_C12_B_BASE_IDX 3 15235 #define mmMPC_OUT2_CSC_C13_C14_B 0x05bb 15236 #define mmMPC_OUT2_CSC_C13_C14_B_BASE_IDX 3 15237 #define mmMPC_OUT2_CSC_C21_C22_B 0x05bc 15238 #define mmMPC_OUT2_CSC_C21_C22_B_BASE_IDX 3 15239 #define mmMPC_OUT2_CSC_C23_C24_B 0x05bd 15240 #define mmMPC_OUT2_CSC_C23_C24_B_BASE_IDX 3 15241 #define mmMPC_OUT2_CSC_C31_C32_B 0x05be 15242 #define mmMPC_OUT2_CSC_C31_C32_B_BASE_IDX 3 15243 #define mmMPC_OUT2_CSC_C33_C34_B 0x05bf 15244 #define mmMPC_OUT2_CSC_C33_C34_B_BASE_IDX 3 15245 #define mmMPC_OUT3_CSC_MODE 0x05c0 15246 #define mmMPC_OUT3_CSC_MODE_BASE_IDX 3 15247 #define mmMPC_OUT3_CSC_C11_C12_A 0x05c1 15248 #define mmMPC_OUT3_CSC_C11_C12_A_BASE_IDX 3 15249 #define mmMPC_OUT3_CSC_C13_C14_A 0x05c2 15250 #define mmMPC_OUT3_CSC_C13_C14_A_BASE_IDX 3 15251 #define mmMPC_OUT3_CSC_C21_C22_A 0x05c3 15252 #define mmMPC_OUT3_CSC_C21_C22_A_BASE_IDX 3 15253 #define mmMPC_OUT3_CSC_C23_C24_A 0x05c4 15254 #define mmMPC_OUT3_CSC_C23_C24_A_BASE_IDX 3 15255 #define mmMPC_OUT3_CSC_C31_C32_A 0x05c5 15256 #define mmMPC_OUT3_CSC_C31_C32_A_BASE_IDX 3 15257 #define mmMPC_OUT3_CSC_C33_C34_A 0x05c6 15258 #define mmMPC_OUT3_CSC_C33_C34_A_BASE_IDX 3 15259 #define mmMPC_OUT3_CSC_C11_C12_B 0x05c7 15260 #define mmMPC_OUT3_CSC_C11_C12_B_BASE_IDX 3 15261 #define mmMPC_OUT3_CSC_C13_C14_B 0x05c8 15262 #define mmMPC_OUT3_CSC_C13_C14_B_BASE_IDX 3 15263 #define mmMPC_OUT3_CSC_C21_C22_B 0x05c9 15264 #define mmMPC_OUT3_CSC_C21_C22_B_BASE_IDX 3 15265 #define mmMPC_OUT3_CSC_C23_C24_B 0x05ca 15266 #define mmMPC_OUT3_CSC_C23_C24_B_BASE_IDX 3 15267 #define mmMPC_OUT3_CSC_C31_C32_B 0x05cb 15268 #define mmMPC_OUT3_CSC_C31_C32_B_BASE_IDX 3 15269 #define mmMPC_OUT3_CSC_C33_C34_B 0x05cc 15270 #define mmMPC_OUT3_CSC_C33_C34_B_BASE_IDX 3 15271 #define mmMPC_OUT4_CSC_MODE 0x05cd 15272 #define mmMPC_OUT4_CSC_MODE_BASE_IDX 3 15273 #define mmMPC_OUT4_CSC_C11_C12_A 0x05ce 15274 #define mmMPC_OUT4_CSC_C11_C12_A_BASE_IDX 3 15275 #define mmMPC_OUT4_CSC_C13_C14_A 0x05cf 15276 #define mmMPC_OUT4_CSC_C13_C14_A_BASE_IDX 3 15277 #define mmMPC_OUT4_CSC_C21_C22_A 0x05d0 15278 #define mmMPC_OUT4_CSC_C21_C22_A_BASE_IDX 3 15279 #define mmMPC_OUT4_CSC_C23_C24_A 0x05d1 15280 #define mmMPC_OUT4_CSC_C23_C24_A_BASE_IDX 3 15281 #define mmMPC_OUT4_CSC_C31_C32_A 0x05d2 15282 #define mmMPC_OUT4_CSC_C31_C32_A_BASE_IDX 3 15283 #define mmMPC_OUT4_CSC_C33_C34_A 0x05d3 15284 #define mmMPC_OUT4_CSC_C33_C34_A_BASE_IDX 3 15285 #define mmMPC_OUT4_CSC_C11_C12_B 0x05d4 15286 #define mmMPC_OUT4_CSC_C11_C12_B_BASE_IDX 3 15287 #define mmMPC_OUT4_CSC_C13_C14_B 0x05d5 15288 #define mmMPC_OUT4_CSC_C13_C14_B_BASE_IDX 3 15289 #define mmMPC_OUT4_CSC_C21_C22_B 0x05d6 15290 #define mmMPC_OUT4_CSC_C21_C22_B_BASE_IDX 3 15291 #define mmMPC_OUT4_CSC_C23_C24_B 0x05d7 15292 #define mmMPC_OUT4_CSC_C23_C24_B_BASE_IDX 3 15293 #define mmMPC_OUT4_CSC_C31_C32_B 0x05d8 15294 #define mmMPC_OUT4_CSC_C31_C32_B_BASE_IDX 3 15295 #define mmMPC_OUT4_CSC_C33_C34_B 0x05d9 15296 #define mmMPC_OUT4_CSC_C33_C34_B_BASE_IDX 3 15297 #define mmMPC_OUT5_CSC_MODE 0x05da 15298 #define mmMPC_OUT5_CSC_MODE_BASE_IDX 3 15299 #define mmMPC_OUT5_CSC_C11_C12_A 0x05db 15300 #define mmMPC_OUT5_CSC_C11_C12_A_BASE_IDX 3 15301 #define mmMPC_OUT5_CSC_C13_C14_A 0x05dc 15302 #define mmMPC_OUT5_CSC_C13_C14_A_BASE_IDX 3 15303 #define mmMPC_OUT5_CSC_C21_C22_A 0x05dd 15304 #define mmMPC_OUT5_CSC_C21_C22_A_BASE_IDX 3 15305 #define mmMPC_OUT5_CSC_C23_C24_A 0x05de 15306 #define mmMPC_OUT5_CSC_C23_C24_A_BASE_IDX 3 15307 #define mmMPC_OUT5_CSC_C31_C32_A 0x05df 15308 #define mmMPC_OUT5_CSC_C31_C32_A_BASE_IDX 3 15309 #define mmMPC_OUT5_CSC_C33_C34_A 0x05e0 15310 #define mmMPC_OUT5_CSC_C33_C34_A_BASE_IDX 3 15311 #define mmMPC_OUT5_CSC_C11_C12_B 0x05e1 15312 #define mmMPC_OUT5_CSC_C11_C12_B_BASE_IDX 3 15313 #define mmMPC_OUT5_CSC_C13_C14_B 0x05e2 15314 #define mmMPC_OUT5_CSC_C13_C14_B_BASE_IDX 3 15315 #define mmMPC_OUT5_CSC_C21_C22_B 0x05e3 15316 #define mmMPC_OUT5_CSC_C21_C22_B_BASE_IDX 3 15317 #define mmMPC_OUT5_CSC_C23_C24_B 0x05e4 15318 #define mmMPC_OUT5_CSC_C23_C24_B_BASE_IDX 3 15319 #define mmMPC_OUT5_CSC_C31_C32_B 0x05e5 15320 #define mmMPC_OUT5_CSC_C31_C32_B_BASE_IDX 3 15321 #define mmMPC_OUT5_CSC_C33_C34_B 0x05e6 15322 #define mmMPC_OUT5_CSC_C33_C34_B_BASE_IDX 3 15323 15324 15325 // addressBlock: dce_dc_mpc_mpc_rmu_dispdec 15326 // base address: 0x0 15327 #define mmMPC_RMU_CONTROL 0x0680 15328 #define mmMPC_RMU_CONTROL_BASE_IDX 3 15329 #define mmMPC_RMU_MEM_PWR_CTRL 0x0681 15330 #define mmMPC_RMU_MEM_PWR_CTRL_BASE_IDX 3 15331 #define mmMPC_RMU0_SHAPER_CONTROL 0x0682 15332 #define mmMPC_RMU0_SHAPER_CONTROL_BASE_IDX 3 15333 #define mmMPC_RMU0_SHAPER_OFFSET_R 0x0683 15334 #define mmMPC_RMU0_SHAPER_OFFSET_R_BASE_IDX 3 15335 #define mmMPC_RMU0_SHAPER_OFFSET_G 0x0684 15336 #define mmMPC_RMU0_SHAPER_OFFSET_G_BASE_IDX 3 15337 #define mmMPC_RMU0_SHAPER_OFFSET_B 0x0685 15338 #define mmMPC_RMU0_SHAPER_OFFSET_B_BASE_IDX 3 15339 #define mmMPC_RMU0_SHAPER_SCALE_R 0x0686 15340 #define mmMPC_RMU0_SHAPER_SCALE_R_BASE_IDX 3 15341 #define mmMPC_RMU0_SHAPER_SCALE_G_B 0x0687 15342 #define mmMPC_RMU0_SHAPER_SCALE_G_B_BASE_IDX 3 15343 #define mmMPC_RMU0_SHAPER_LUT_INDEX 0x0688 15344 #define mmMPC_RMU0_SHAPER_LUT_INDEX_BASE_IDX 3 15345 #define mmMPC_RMU0_SHAPER_LUT_DATA 0x0689 15346 #define mmMPC_RMU0_SHAPER_LUT_DATA_BASE_IDX 3 15347 #define mmMPC_RMU0_SHAPER_LUT_WRITE_EN_MASK 0x068a 15348 #define mmMPC_RMU0_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 3 15349 #define mmMPC_RMU0_SHAPER_RAMA_START_CNTL_B 0x068b 15350 #define mmMPC_RMU0_SHAPER_RAMA_START_CNTL_B_BASE_IDX 3 15351 #define mmMPC_RMU0_SHAPER_RAMA_START_CNTL_G 0x068c 15352 #define mmMPC_RMU0_SHAPER_RAMA_START_CNTL_G_BASE_IDX 3 15353 #define mmMPC_RMU0_SHAPER_RAMA_START_CNTL_R 0x068d 15354 #define mmMPC_RMU0_SHAPER_RAMA_START_CNTL_R_BASE_IDX 3 15355 #define mmMPC_RMU0_SHAPER_RAMA_END_CNTL_B 0x068e 15356 #define mmMPC_RMU0_SHAPER_RAMA_END_CNTL_B_BASE_IDX 3 15357 #define mmMPC_RMU0_SHAPER_RAMA_END_CNTL_G 0x068f 15358 #define mmMPC_RMU0_SHAPER_RAMA_END_CNTL_G_BASE_IDX 3 15359 #define mmMPC_RMU0_SHAPER_RAMA_END_CNTL_R 0x0690 15360 #define mmMPC_RMU0_SHAPER_RAMA_END_CNTL_R_BASE_IDX 3 15361 #define mmMPC_RMU0_SHAPER_RAMA_REGION_0_1 0x0691 15362 #define mmMPC_RMU0_SHAPER_RAMA_REGION_0_1_BASE_IDX 3 15363 #define mmMPC_RMU0_SHAPER_RAMA_REGION_2_3 0x0692 15364 #define mmMPC_RMU0_SHAPER_RAMA_REGION_2_3_BASE_IDX 3 15365 #define mmMPC_RMU0_SHAPER_RAMA_REGION_4_5 0x0693 15366 #define mmMPC_RMU0_SHAPER_RAMA_REGION_4_5_BASE_IDX 3 15367 #define mmMPC_RMU0_SHAPER_RAMA_REGION_6_7 0x0694 15368 #define mmMPC_RMU0_SHAPER_RAMA_REGION_6_7_BASE_IDX 3 15369 #define mmMPC_RMU0_SHAPER_RAMA_REGION_8_9 0x0695 15370 #define mmMPC_RMU0_SHAPER_RAMA_REGION_8_9_BASE_IDX 3 15371 #define mmMPC_RMU0_SHAPER_RAMA_REGION_10_11 0x0696 15372 #define mmMPC_RMU0_SHAPER_RAMA_REGION_10_11_BASE_IDX 3 15373 #define mmMPC_RMU0_SHAPER_RAMA_REGION_12_13 0x0697 15374 #define mmMPC_RMU0_SHAPER_RAMA_REGION_12_13_BASE_IDX 3 15375 #define mmMPC_RMU0_SHAPER_RAMA_REGION_14_15 0x0698 15376 #define mmMPC_RMU0_SHAPER_RAMA_REGION_14_15_BASE_IDX 3 15377 #define mmMPC_RMU0_SHAPER_RAMA_REGION_16_17 0x0699 15378 #define mmMPC_RMU0_SHAPER_RAMA_REGION_16_17_BASE_IDX 3 15379 #define mmMPC_RMU0_SHAPER_RAMA_REGION_18_19 0x069a 15380 #define mmMPC_RMU0_SHAPER_RAMA_REGION_18_19_BASE_IDX 3 15381 #define mmMPC_RMU0_SHAPER_RAMA_REGION_20_21 0x069b 15382 #define mmMPC_RMU0_SHAPER_RAMA_REGION_20_21_BASE_IDX 3 15383 #define mmMPC_RMU0_SHAPER_RAMA_REGION_22_23 0x069c 15384 #define mmMPC_RMU0_SHAPER_RAMA_REGION_22_23_BASE_IDX 3 15385 #define mmMPC_RMU0_SHAPER_RAMA_REGION_24_25 0x069d 15386 #define mmMPC_RMU0_SHAPER_RAMA_REGION_24_25_BASE_IDX 3 15387 #define mmMPC_RMU0_SHAPER_RAMA_REGION_26_27 0x069e 15388 #define mmMPC_RMU0_SHAPER_RAMA_REGION_26_27_BASE_IDX 3 15389 #define mmMPC_RMU0_SHAPER_RAMA_REGION_28_29 0x069f 15390 #define mmMPC_RMU0_SHAPER_RAMA_REGION_28_29_BASE_IDX 3 15391 #define mmMPC_RMU0_SHAPER_RAMA_REGION_30_31 0x06a0 15392 #define mmMPC_RMU0_SHAPER_RAMA_REGION_30_31_BASE_IDX 3 15393 #define mmMPC_RMU0_SHAPER_RAMA_REGION_32_33 0x06a1 15394 #define mmMPC_RMU0_SHAPER_RAMA_REGION_32_33_BASE_IDX 3 15395 #define mmMPC_RMU0_SHAPER_RAMB_START_CNTL_B 0x06a2 15396 #define mmMPC_RMU0_SHAPER_RAMB_START_CNTL_B_BASE_IDX 3 15397 #define mmMPC_RMU0_SHAPER_RAMB_START_CNTL_G 0x06a3 15398 #define mmMPC_RMU0_SHAPER_RAMB_START_CNTL_G_BASE_IDX 3 15399 #define mmMPC_RMU0_SHAPER_RAMB_START_CNTL_R 0x06a4 15400 #define mmMPC_RMU0_SHAPER_RAMB_START_CNTL_R_BASE_IDX 3 15401 #define mmMPC_RMU0_SHAPER_RAMB_END_CNTL_B 0x06a5 15402 #define mmMPC_RMU0_SHAPER_RAMB_END_CNTL_B_BASE_IDX 3 15403 #define mmMPC_RMU0_SHAPER_RAMB_END_CNTL_G 0x06a6 15404 #define mmMPC_RMU0_SHAPER_RAMB_END_CNTL_G_BASE_IDX 3 15405 #define mmMPC_RMU0_SHAPER_RAMB_END_CNTL_R 0x06a7 15406 #define mmMPC_RMU0_SHAPER_RAMB_END_CNTL_R_BASE_IDX 3 15407 #define mmMPC_RMU0_SHAPER_RAMB_REGION_0_1 0x06a8 15408 #define mmMPC_RMU0_SHAPER_RAMB_REGION_0_1_BASE_IDX 3 15409 #define mmMPC_RMU0_SHAPER_RAMB_REGION_2_3 0x06a9 15410 #define mmMPC_RMU0_SHAPER_RAMB_REGION_2_3_BASE_IDX 3 15411 #define mmMPC_RMU0_SHAPER_RAMB_REGION_4_5 0x06aa 15412 #define mmMPC_RMU0_SHAPER_RAMB_REGION_4_5_BASE_IDX 3 15413 #define mmMPC_RMU0_SHAPER_RAMB_REGION_6_7 0x06ab 15414 #define mmMPC_RMU0_SHAPER_RAMB_REGION_6_7_BASE_IDX 3 15415 #define mmMPC_RMU0_SHAPER_RAMB_REGION_8_9 0x06ac 15416 #define mmMPC_RMU0_SHAPER_RAMB_REGION_8_9_BASE_IDX 3 15417 #define mmMPC_RMU0_SHAPER_RAMB_REGION_10_11 0x06ad 15418 #define mmMPC_RMU0_SHAPER_RAMB_REGION_10_11_BASE_IDX 3 15419 #define mmMPC_RMU0_SHAPER_RAMB_REGION_12_13 0x06ae 15420 #define mmMPC_RMU0_SHAPER_RAMB_REGION_12_13_BASE_IDX 3 15421 #define mmMPC_RMU0_SHAPER_RAMB_REGION_14_15 0x06af 15422 #define mmMPC_RMU0_SHAPER_RAMB_REGION_14_15_BASE_IDX 3 15423 #define mmMPC_RMU0_SHAPER_RAMB_REGION_16_17 0x06b0 15424 #define mmMPC_RMU0_SHAPER_RAMB_REGION_16_17_BASE_IDX 3 15425 #define mmMPC_RMU0_SHAPER_RAMB_REGION_18_19 0x06b1 15426 #define mmMPC_RMU0_SHAPER_RAMB_REGION_18_19_BASE_IDX 3 15427 #define mmMPC_RMU0_SHAPER_RAMB_REGION_20_21 0x06b2 15428 #define mmMPC_RMU0_SHAPER_RAMB_REGION_20_21_BASE_IDX 3 15429 #define mmMPC_RMU0_SHAPER_RAMB_REGION_22_23 0x06b3 15430 #define mmMPC_RMU0_SHAPER_RAMB_REGION_22_23_BASE_IDX 3 15431 #define mmMPC_RMU0_SHAPER_RAMB_REGION_24_25 0x06b4 15432 #define mmMPC_RMU0_SHAPER_RAMB_REGION_24_25_BASE_IDX 3 15433 #define mmMPC_RMU0_SHAPER_RAMB_REGION_26_27 0x06b5 15434 #define mmMPC_RMU0_SHAPER_RAMB_REGION_26_27_BASE_IDX 3 15435 #define mmMPC_RMU0_SHAPER_RAMB_REGION_28_29 0x06b6 15436 #define mmMPC_RMU0_SHAPER_RAMB_REGION_28_29_BASE_IDX 3 15437 #define mmMPC_RMU0_SHAPER_RAMB_REGION_30_31 0x06b7 15438 #define mmMPC_RMU0_SHAPER_RAMB_REGION_30_31_BASE_IDX 3 15439 #define mmMPC_RMU0_SHAPER_RAMB_REGION_32_33 0x06b8 15440 #define mmMPC_RMU0_SHAPER_RAMB_REGION_32_33_BASE_IDX 3 15441 #define mmMPC_RMU0_3DLUT_MODE 0x06b9 15442 #define mmMPC_RMU0_3DLUT_MODE_BASE_IDX 3 15443 #define mmMPC_RMU0_3DLUT_INDEX 0x06ba 15444 #define mmMPC_RMU0_3DLUT_INDEX_BASE_IDX 3 15445 #define mmMPC_RMU0_3DLUT_DATA 0x06bb 15446 #define mmMPC_RMU0_3DLUT_DATA_BASE_IDX 3 15447 #define mmMPC_RMU0_3DLUT_DATA_30BIT 0x06bc 15448 #define mmMPC_RMU0_3DLUT_DATA_30BIT_BASE_IDX 3 15449 #define mmMPC_RMU0_3DLUT_READ_WRITE_CONTROL 0x06bd 15450 #define mmMPC_RMU0_3DLUT_READ_WRITE_CONTROL_BASE_IDX 3 15451 #define mmMPC_RMU0_3DLUT_OUT_NORM_FACTOR 0x06be 15452 #define mmMPC_RMU0_3DLUT_OUT_NORM_FACTOR_BASE_IDX 3 15453 #define mmMPC_RMU0_3DLUT_OUT_OFFSET_R 0x06bf 15454 #define mmMPC_RMU0_3DLUT_OUT_OFFSET_R_BASE_IDX 3 15455 #define mmMPC_RMU0_3DLUT_OUT_OFFSET_G 0x06c0 15456 #define mmMPC_RMU0_3DLUT_OUT_OFFSET_G_BASE_IDX 3 15457 #define mmMPC_RMU0_3DLUT_OUT_OFFSET_B 0x06c1 15458 #define mmMPC_RMU0_3DLUT_OUT_OFFSET_B_BASE_IDX 3 15459 #define mmMPC_RMU1_SHAPER_CONTROL 0x06c2 15460 #define mmMPC_RMU1_SHAPER_CONTROL_BASE_IDX 3 15461 #define mmMPC_RMU1_SHAPER_OFFSET_R 0x06c3 15462 #define mmMPC_RMU1_SHAPER_OFFSET_R_BASE_IDX 3 15463 #define mmMPC_RMU1_SHAPER_OFFSET_G 0x06c4 15464 #define mmMPC_RMU1_SHAPER_OFFSET_G_BASE_IDX 3 15465 #define mmMPC_RMU1_SHAPER_OFFSET_B 0x06c5 15466 #define mmMPC_RMU1_SHAPER_OFFSET_B_BASE_IDX 3 15467 #define mmMPC_RMU1_SHAPER_SCALE_R 0x06c6 15468 #define mmMPC_RMU1_SHAPER_SCALE_R_BASE_IDX 3 15469 #define mmMPC_RMU1_SHAPER_SCALE_G_B 0x06c7 15470 #define mmMPC_RMU1_SHAPER_SCALE_G_B_BASE_IDX 3 15471 #define mmMPC_RMU1_SHAPER_LUT_INDEX 0x06c8 15472 #define mmMPC_RMU1_SHAPER_LUT_INDEX_BASE_IDX 3 15473 #define mmMPC_RMU1_SHAPER_LUT_DATA 0x06c9 15474 #define mmMPC_RMU1_SHAPER_LUT_DATA_BASE_IDX 3 15475 #define mmMPC_RMU1_SHAPER_LUT_WRITE_EN_MASK 0x06ca 15476 #define mmMPC_RMU1_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 3 15477 #define mmMPC_RMU1_SHAPER_RAMA_START_CNTL_B 0x06cb 15478 #define mmMPC_RMU1_SHAPER_RAMA_START_CNTL_B_BASE_IDX 3 15479 #define mmMPC_RMU1_SHAPER_RAMA_START_CNTL_G 0x06cc 15480 #define mmMPC_RMU1_SHAPER_RAMA_START_CNTL_G_BASE_IDX 3 15481 #define mmMPC_RMU1_SHAPER_RAMA_START_CNTL_R 0x06cd 15482 #define mmMPC_RMU1_SHAPER_RAMA_START_CNTL_R_BASE_IDX 3 15483 #define mmMPC_RMU1_SHAPER_RAMA_END_CNTL_B 0x06ce 15484 #define mmMPC_RMU1_SHAPER_RAMA_END_CNTL_B_BASE_IDX 3 15485 #define mmMPC_RMU1_SHAPER_RAMA_END_CNTL_G 0x06cf 15486 #define mmMPC_RMU1_SHAPER_RAMA_END_CNTL_G_BASE_IDX 3 15487 #define mmMPC_RMU1_SHAPER_RAMA_END_CNTL_R 0x06d0 15488 #define mmMPC_RMU1_SHAPER_RAMA_END_CNTL_R_BASE_IDX 3 15489 #define mmMPC_RMU1_SHAPER_RAMA_REGION_0_1 0x06d1 15490 #define mmMPC_RMU1_SHAPER_RAMA_REGION_0_1_BASE_IDX 3 15491 #define mmMPC_RMU1_SHAPER_RAMA_REGION_2_3 0x06d2 15492 #define mmMPC_RMU1_SHAPER_RAMA_REGION_2_3_BASE_IDX 3 15493 #define mmMPC_RMU1_SHAPER_RAMA_REGION_4_5 0x06d3 15494 #define mmMPC_RMU1_SHAPER_RAMA_REGION_4_5_BASE_IDX 3 15495 #define mmMPC_RMU1_SHAPER_RAMA_REGION_6_7 0x06d4 15496 #define mmMPC_RMU1_SHAPER_RAMA_REGION_6_7_BASE_IDX 3 15497 #define mmMPC_RMU1_SHAPER_RAMA_REGION_8_9 0x06d5 15498 #define mmMPC_RMU1_SHAPER_RAMA_REGION_8_9_BASE_IDX 3 15499 #define mmMPC_RMU1_SHAPER_RAMA_REGION_10_11 0x06d6 15500 #define mmMPC_RMU1_SHAPER_RAMA_REGION_10_11_BASE_IDX 3 15501 #define mmMPC_RMU1_SHAPER_RAMA_REGION_12_13 0x06d7 15502 #define mmMPC_RMU1_SHAPER_RAMA_REGION_12_13_BASE_IDX 3 15503 #define mmMPC_RMU1_SHAPER_RAMA_REGION_14_15 0x06d8 15504 #define mmMPC_RMU1_SHAPER_RAMA_REGION_14_15_BASE_IDX 3 15505 #define mmMPC_RMU1_SHAPER_RAMA_REGION_16_17 0x06d9 15506 #define mmMPC_RMU1_SHAPER_RAMA_REGION_16_17_BASE_IDX 3 15507 #define mmMPC_RMU1_SHAPER_RAMA_REGION_18_19 0x06da 15508 #define mmMPC_RMU1_SHAPER_RAMA_REGION_18_19_BASE_IDX 3 15509 #define mmMPC_RMU1_SHAPER_RAMA_REGION_20_21 0x06db 15510 #define mmMPC_RMU1_SHAPER_RAMA_REGION_20_21_BASE_IDX 3 15511 #define mmMPC_RMU1_SHAPER_RAMA_REGION_22_23 0x06dc 15512 #define mmMPC_RMU1_SHAPER_RAMA_REGION_22_23_BASE_IDX 3 15513 #define mmMPC_RMU1_SHAPER_RAMA_REGION_24_25 0x06dd 15514 #define mmMPC_RMU1_SHAPER_RAMA_REGION_24_25_BASE_IDX 3 15515 #define mmMPC_RMU1_SHAPER_RAMA_REGION_26_27 0x06de 15516 #define mmMPC_RMU1_SHAPER_RAMA_REGION_26_27_BASE_IDX 3 15517 #define mmMPC_RMU1_SHAPER_RAMA_REGION_28_29 0x06df 15518 #define mmMPC_RMU1_SHAPER_RAMA_REGION_28_29_BASE_IDX 3 15519 #define mmMPC_RMU1_SHAPER_RAMA_REGION_30_31 0x06e0 15520 #define mmMPC_RMU1_SHAPER_RAMA_REGION_30_31_BASE_IDX 3 15521 #define mmMPC_RMU1_SHAPER_RAMA_REGION_32_33 0x06e1 15522 #define mmMPC_RMU1_SHAPER_RAMA_REGION_32_33_BASE_IDX 3 15523 #define mmMPC_RMU1_SHAPER_RAMB_START_CNTL_B 0x06e2 15524 #define mmMPC_RMU1_SHAPER_RAMB_START_CNTL_B_BASE_IDX 3 15525 #define mmMPC_RMU1_SHAPER_RAMB_START_CNTL_G 0x06e3 15526 #define mmMPC_RMU1_SHAPER_RAMB_START_CNTL_G_BASE_IDX 3 15527 #define mmMPC_RMU1_SHAPER_RAMB_START_CNTL_R 0x06e4 15528 #define mmMPC_RMU1_SHAPER_RAMB_START_CNTL_R_BASE_IDX 3 15529 #define mmMPC_RMU1_SHAPER_RAMB_END_CNTL_B 0x06e5 15530 #define mmMPC_RMU1_SHAPER_RAMB_END_CNTL_B_BASE_IDX 3 15531 #define mmMPC_RMU1_SHAPER_RAMB_END_CNTL_G 0x06e6 15532 #define mmMPC_RMU1_SHAPER_RAMB_END_CNTL_G_BASE_IDX 3 15533 #define mmMPC_RMU1_SHAPER_RAMB_END_CNTL_R 0x06e7 15534 #define mmMPC_RMU1_SHAPER_RAMB_END_CNTL_R_BASE_IDX 3 15535 #define mmMPC_RMU1_SHAPER_RAMB_REGION_0_1 0x06e8 15536 #define mmMPC_RMU1_SHAPER_RAMB_REGION_0_1_BASE_IDX 3 15537 #define mmMPC_RMU1_SHAPER_RAMB_REGION_2_3 0x06e9 15538 #define mmMPC_RMU1_SHAPER_RAMB_REGION_2_3_BASE_IDX 3 15539 #define mmMPC_RMU1_SHAPER_RAMB_REGION_4_5 0x06ea 15540 #define mmMPC_RMU1_SHAPER_RAMB_REGION_4_5_BASE_IDX 3 15541 #define mmMPC_RMU1_SHAPER_RAMB_REGION_6_7 0x06eb 15542 #define mmMPC_RMU1_SHAPER_RAMB_REGION_6_7_BASE_IDX 3 15543 #define mmMPC_RMU1_SHAPER_RAMB_REGION_8_9 0x06ec 15544 #define mmMPC_RMU1_SHAPER_RAMB_REGION_8_9_BASE_IDX 3 15545 #define mmMPC_RMU1_SHAPER_RAMB_REGION_10_11 0x06ed 15546 #define mmMPC_RMU1_SHAPER_RAMB_REGION_10_11_BASE_IDX 3 15547 #define mmMPC_RMU1_SHAPER_RAMB_REGION_12_13 0x06ee 15548 #define mmMPC_RMU1_SHAPER_RAMB_REGION_12_13_BASE_IDX 3 15549 #define mmMPC_RMU1_SHAPER_RAMB_REGION_14_15 0x06ef 15550 #define mmMPC_RMU1_SHAPER_RAMB_REGION_14_15_BASE_IDX 3 15551 #define mmMPC_RMU1_SHAPER_RAMB_REGION_16_17 0x06f0 15552 #define mmMPC_RMU1_SHAPER_RAMB_REGION_16_17_BASE_IDX 3 15553 #define mmMPC_RMU1_SHAPER_RAMB_REGION_18_19 0x06f1 15554 #define mmMPC_RMU1_SHAPER_RAMB_REGION_18_19_BASE_IDX 3 15555 #define mmMPC_RMU1_SHAPER_RAMB_REGION_20_21 0x06f2 15556 #define mmMPC_RMU1_SHAPER_RAMB_REGION_20_21_BASE_IDX 3 15557 #define mmMPC_RMU1_SHAPER_RAMB_REGION_22_23 0x06f3 15558 #define mmMPC_RMU1_SHAPER_RAMB_REGION_22_23_BASE_IDX 3 15559 #define mmMPC_RMU1_SHAPER_RAMB_REGION_24_25 0x06f4 15560 #define mmMPC_RMU1_SHAPER_RAMB_REGION_24_25_BASE_IDX 3 15561 #define mmMPC_RMU1_SHAPER_RAMB_REGION_26_27 0x06f5 15562 #define mmMPC_RMU1_SHAPER_RAMB_REGION_26_27_BASE_IDX 3 15563 #define mmMPC_RMU1_SHAPER_RAMB_REGION_28_29 0x06f6 15564 #define mmMPC_RMU1_SHAPER_RAMB_REGION_28_29_BASE_IDX 3 15565 #define mmMPC_RMU1_SHAPER_RAMB_REGION_30_31 0x06f7 15566 #define mmMPC_RMU1_SHAPER_RAMB_REGION_30_31_BASE_IDX 3 15567 #define mmMPC_RMU1_SHAPER_RAMB_REGION_32_33 0x06f8 15568 #define mmMPC_RMU1_SHAPER_RAMB_REGION_32_33_BASE_IDX 3 15569 #define mmMPC_RMU1_3DLUT_MODE 0x06f9 15570 #define mmMPC_RMU1_3DLUT_MODE_BASE_IDX 3 15571 #define mmMPC_RMU1_3DLUT_INDEX 0x06fa 15572 #define mmMPC_RMU1_3DLUT_INDEX_BASE_IDX 3 15573 #define mmMPC_RMU1_3DLUT_DATA 0x06fb 15574 #define mmMPC_RMU1_3DLUT_DATA_BASE_IDX 3 15575 #define mmMPC_RMU1_3DLUT_DATA_30BIT 0x06fc 15576 #define mmMPC_RMU1_3DLUT_DATA_30BIT_BASE_IDX 3 15577 #define mmMPC_RMU1_3DLUT_READ_WRITE_CONTROL 0x06fd 15578 #define mmMPC_RMU1_3DLUT_READ_WRITE_CONTROL_BASE_IDX 3 15579 #define mmMPC_RMU1_3DLUT_OUT_NORM_FACTOR 0x06fe 15580 #define mmMPC_RMU1_3DLUT_OUT_NORM_FACTOR_BASE_IDX 3 15581 #define mmMPC_RMU1_3DLUT_OUT_OFFSET_R 0x06ff 15582 #define mmMPC_RMU1_3DLUT_OUT_OFFSET_R_BASE_IDX 3 15583 #define mmMPC_RMU1_3DLUT_OUT_OFFSET_G 0x0700 15584 #define mmMPC_RMU1_3DLUT_OUT_OFFSET_G_BASE_IDX 3 15585 #define mmMPC_RMU1_3DLUT_OUT_OFFSET_B 0x0701 15586 #define mmMPC_RMU1_3DLUT_OUT_OFFSET_B_BASE_IDX 3 15587 #define mmMPC_RMU2_SHAPER_CONTROL 0x0702 15588 #define mmMPC_RMU2_SHAPER_CONTROL_BASE_IDX 3 15589 #define mmMPC_RMU2_SHAPER_OFFSET_R 0x0703 15590 #define mmMPC_RMU2_SHAPER_OFFSET_R_BASE_IDX 3 15591 #define mmMPC_RMU2_SHAPER_OFFSET_G 0x0704 15592 #define mmMPC_RMU2_SHAPER_OFFSET_G_BASE_IDX 3 15593 #define mmMPC_RMU2_SHAPER_OFFSET_B 0x0705 15594 #define mmMPC_RMU2_SHAPER_OFFSET_B_BASE_IDX 3 15595 #define mmMPC_RMU2_SHAPER_SCALE_R 0x0706 15596 #define mmMPC_RMU2_SHAPER_SCALE_R_BASE_IDX 3 15597 #define mmMPC_RMU2_SHAPER_SCALE_G_B 0x0707 15598 #define mmMPC_RMU2_SHAPER_SCALE_G_B_BASE_IDX 3 15599 #define mmMPC_RMU2_SHAPER_LUT_INDEX 0x0708 15600 #define mmMPC_RMU2_SHAPER_LUT_INDEX_BASE_IDX 3 15601 #define mmMPC_RMU2_SHAPER_LUT_DATA 0x0709 15602 #define mmMPC_RMU2_SHAPER_LUT_DATA_BASE_IDX 3 15603 #define mmMPC_RMU2_SHAPER_LUT_WRITE_EN_MASK 0x070a 15604 #define mmMPC_RMU2_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 3 15605 #define mmMPC_RMU2_SHAPER_RAMA_START_CNTL_B 0x070b 15606 #define mmMPC_RMU2_SHAPER_RAMA_START_CNTL_B_BASE_IDX 3 15607 #define mmMPC_RMU2_SHAPER_RAMA_START_CNTL_G 0x070c 15608 #define mmMPC_RMU2_SHAPER_RAMA_START_CNTL_G_BASE_IDX 3 15609 #define mmMPC_RMU2_SHAPER_RAMA_START_CNTL_R 0x070d 15610 #define mmMPC_RMU2_SHAPER_RAMA_START_CNTL_R_BASE_IDX 3 15611 #define mmMPC_RMU2_SHAPER_RAMA_END_CNTL_B 0x070e 15612 #define mmMPC_RMU2_SHAPER_RAMA_END_CNTL_B_BASE_IDX 3 15613 #define mmMPC_RMU2_SHAPER_RAMA_END_CNTL_G 0x070f 15614 #define mmMPC_RMU2_SHAPER_RAMA_END_CNTL_G_BASE_IDX 3 15615 #define mmMPC_RMU2_SHAPER_RAMA_END_CNTL_R 0x0710 15616 #define mmMPC_RMU2_SHAPER_RAMA_END_CNTL_R_BASE_IDX 3 15617 #define mmMPC_RMU2_SHAPER_RAMA_REGION_0_1 0x0711 15618 #define mmMPC_RMU2_SHAPER_RAMA_REGION_0_1_BASE_IDX 3 15619 #define mmMPC_RMU2_SHAPER_RAMA_REGION_2_3 0x0712 15620 #define mmMPC_RMU2_SHAPER_RAMA_REGION_2_3_BASE_IDX 3 15621 #define mmMPC_RMU2_SHAPER_RAMA_REGION_4_5 0x0713 15622 #define mmMPC_RMU2_SHAPER_RAMA_REGION_4_5_BASE_IDX 3 15623 #define mmMPC_RMU2_SHAPER_RAMA_REGION_6_7 0x0714 15624 #define mmMPC_RMU2_SHAPER_RAMA_REGION_6_7_BASE_IDX 3 15625 #define mmMPC_RMU2_SHAPER_RAMA_REGION_8_9 0x0715 15626 #define mmMPC_RMU2_SHAPER_RAMA_REGION_8_9_BASE_IDX 3 15627 #define mmMPC_RMU2_SHAPER_RAMA_REGION_10_11 0x0716 15628 #define mmMPC_RMU2_SHAPER_RAMA_REGION_10_11_BASE_IDX 3 15629 #define mmMPC_RMU2_SHAPER_RAMA_REGION_12_13 0x0717 15630 #define mmMPC_RMU2_SHAPER_RAMA_REGION_12_13_BASE_IDX 3 15631 #define mmMPC_RMU2_SHAPER_RAMA_REGION_14_15 0x0718 15632 #define mmMPC_RMU2_SHAPER_RAMA_REGION_14_15_BASE_IDX 3 15633 #define mmMPC_RMU2_SHAPER_RAMA_REGION_16_17 0x0719 15634 #define mmMPC_RMU2_SHAPER_RAMA_REGION_16_17_BASE_IDX 3 15635 #define mmMPC_RMU2_SHAPER_RAMA_REGION_18_19 0x071a 15636 #define mmMPC_RMU2_SHAPER_RAMA_REGION_18_19_BASE_IDX 3 15637 #define mmMPC_RMU2_SHAPER_RAMA_REGION_20_21 0x071b 15638 #define mmMPC_RMU2_SHAPER_RAMA_REGION_20_21_BASE_IDX 3 15639 #define mmMPC_RMU2_SHAPER_RAMA_REGION_22_23 0x071c 15640 #define mmMPC_RMU2_SHAPER_RAMA_REGION_22_23_BASE_IDX 3 15641 #define mmMPC_RMU2_SHAPER_RAMA_REGION_24_25 0x071d 15642 #define mmMPC_RMU2_SHAPER_RAMA_REGION_24_25_BASE_IDX 3 15643 #define mmMPC_RMU2_SHAPER_RAMA_REGION_26_27 0x071e 15644 #define mmMPC_RMU2_SHAPER_RAMA_REGION_26_27_BASE_IDX 3 15645 #define mmMPC_RMU2_SHAPER_RAMA_REGION_28_29 0x071f 15646 #define mmMPC_RMU2_SHAPER_RAMA_REGION_28_29_BASE_IDX 3 15647 #define mmMPC_RMU2_SHAPER_RAMA_REGION_30_31 0x0720 15648 #define mmMPC_RMU2_SHAPER_RAMA_REGION_30_31_BASE_IDX 3 15649 #define mmMPC_RMU2_SHAPER_RAMA_REGION_32_33 0x0721 15650 #define mmMPC_RMU2_SHAPER_RAMA_REGION_32_33_BASE_IDX 3 15651 #define mmMPC_RMU2_SHAPER_RAMB_START_CNTL_B 0x0722 15652 #define mmMPC_RMU2_SHAPER_RAMB_START_CNTL_B_BASE_IDX 3 15653 #define mmMPC_RMU2_SHAPER_RAMB_START_CNTL_G 0x0723 15654 #define mmMPC_RMU2_SHAPER_RAMB_START_CNTL_G_BASE_IDX 3 15655 #define mmMPC_RMU2_SHAPER_RAMB_START_CNTL_R 0x0724 15656 #define mmMPC_RMU2_SHAPER_RAMB_START_CNTL_R_BASE_IDX 3 15657 #define mmMPC_RMU2_SHAPER_RAMB_END_CNTL_B 0x0725 15658 #define mmMPC_RMU2_SHAPER_RAMB_END_CNTL_B_BASE_IDX 3 15659 #define mmMPC_RMU2_SHAPER_RAMB_END_CNTL_G 0x0726 15660 #define mmMPC_RMU2_SHAPER_RAMB_END_CNTL_G_BASE_IDX 3 15661 #define mmMPC_RMU2_SHAPER_RAMB_END_CNTL_R 0x0727 15662 #define mmMPC_RMU2_SHAPER_RAMB_END_CNTL_R_BASE_IDX 3 15663 #define mmMPC_RMU2_SHAPER_RAMB_REGION_0_1 0x0728 15664 #define mmMPC_RMU2_SHAPER_RAMB_REGION_0_1_BASE_IDX 3 15665 #define mmMPC_RMU2_SHAPER_RAMB_REGION_2_3 0x0729 15666 #define mmMPC_RMU2_SHAPER_RAMB_REGION_2_3_BASE_IDX 3 15667 #define mmMPC_RMU2_SHAPER_RAMB_REGION_4_5 0x072a 15668 #define mmMPC_RMU2_SHAPER_RAMB_REGION_4_5_BASE_IDX 3 15669 #define mmMPC_RMU2_SHAPER_RAMB_REGION_6_7 0x072b 15670 #define mmMPC_RMU2_SHAPER_RAMB_REGION_6_7_BASE_IDX 3 15671 #define mmMPC_RMU2_SHAPER_RAMB_REGION_8_9 0x072c 15672 #define mmMPC_RMU2_SHAPER_RAMB_REGION_8_9_BASE_IDX 3 15673 #define mmMPC_RMU2_SHAPER_RAMB_REGION_10_11 0x072d 15674 #define mmMPC_RMU2_SHAPER_RAMB_REGION_10_11_BASE_IDX 3 15675 #define mmMPC_RMU2_SHAPER_RAMB_REGION_12_13 0x072e 15676 #define mmMPC_RMU2_SHAPER_RAMB_REGION_12_13_BASE_IDX 3 15677 #define mmMPC_RMU2_SHAPER_RAMB_REGION_14_15 0x072f 15678 #define mmMPC_RMU2_SHAPER_RAMB_REGION_14_15_BASE_IDX 3 15679 #define mmMPC_RMU2_SHAPER_RAMB_REGION_16_17 0x0730 15680 #define mmMPC_RMU2_SHAPER_RAMB_REGION_16_17_BASE_IDX 3 15681 #define mmMPC_RMU2_SHAPER_RAMB_REGION_18_19 0x0731 15682 #define mmMPC_RMU2_SHAPER_RAMB_REGION_18_19_BASE_IDX 3 15683 #define mmMPC_RMU2_SHAPER_RAMB_REGION_20_21 0x0732 15684 #define mmMPC_RMU2_SHAPER_RAMB_REGION_20_21_BASE_IDX 3 15685 #define mmMPC_RMU2_SHAPER_RAMB_REGION_22_23 0x0733 15686 #define mmMPC_RMU2_SHAPER_RAMB_REGION_22_23_BASE_IDX 3 15687 #define mmMPC_RMU2_SHAPER_RAMB_REGION_24_25 0x0734 15688 #define mmMPC_RMU2_SHAPER_RAMB_REGION_24_25_BASE_IDX 3 15689 #define mmMPC_RMU2_SHAPER_RAMB_REGION_26_27 0x0735 15690 #define mmMPC_RMU2_SHAPER_RAMB_REGION_26_27_BASE_IDX 3 15691 #define mmMPC_RMU2_SHAPER_RAMB_REGION_28_29 0x0736 15692 #define mmMPC_RMU2_SHAPER_RAMB_REGION_28_29_BASE_IDX 3 15693 #define mmMPC_RMU2_SHAPER_RAMB_REGION_30_31 0x0737 15694 #define mmMPC_RMU2_SHAPER_RAMB_REGION_30_31_BASE_IDX 3 15695 #define mmMPC_RMU2_SHAPER_RAMB_REGION_32_33 0x0738 15696 #define mmMPC_RMU2_SHAPER_RAMB_REGION_32_33_BASE_IDX 3 15697 #define mmMPC_RMU2_3DLUT_MODE 0x0739 15698 #define mmMPC_RMU2_3DLUT_MODE_BASE_IDX 3 15699 #define mmMPC_RMU2_3DLUT_INDEX 0x073a 15700 #define mmMPC_RMU2_3DLUT_INDEX_BASE_IDX 3 15701 #define mmMPC_RMU2_3DLUT_DATA 0x073b 15702 #define mmMPC_RMU2_3DLUT_DATA_BASE_IDX 3 15703 #define mmMPC_RMU2_3DLUT_DATA_30BIT 0x073c 15704 #define mmMPC_RMU2_3DLUT_DATA_30BIT_BASE_IDX 3 15705 #define mmMPC_RMU2_3DLUT_READ_WRITE_CONTROL 0x073d 15706 #define mmMPC_RMU2_3DLUT_READ_WRITE_CONTROL_BASE_IDX 3 15707 #define mmMPC_RMU2_3DLUT_OUT_NORM_FACTOR 0x073e 15708 #define mmMPC_RMU2_3DLUT_OUT_NORM_FACTOR_BASE_IDX 3 15709 #define mmMPC_RMU2_3DLUT_OUT_OFFSET_R 0x073f 15710 #define mmMPC_RMU2_3DLUT_OUT_OFFSET_R_BASE_IDX 3 15711 #define mmMPC_RMU2_3DLUT_OUT_OFFSET_G 0x0740 15712 #define mmMPC_RMU2_3DLUT_OUT_OFFSET_G_BASE_IDX 3 15713 #define mmMPC_RMU2_3DLUT_OUT_OFFSET_B 0x0741 15714 #define mmMPC_RMU2_3DLUT_OUT_OFFSET_B_BASE_IDX 3 15715 15716 15717 // addressBlock: dce_dc_mpc_mpc_dcperfmon_dc_perfmon_dispdec 15718 // base address: 0x1901c 15719 #define mmDC_PERFMON28_PERFCOUNTER_CNTL 0x08c7 15720 #define mmDC_PERFMON28_PERFCOUNTER_CNTL_BASE_IDX 3 15721 #define mmDC_PERFMON28_PERFCOUNTER_CNTL2 0x08c8 15722 #define mmDC_PERFMON28_PERFCOUNTER_CNTL2_BASE_IDX 3 15723 #define mmDC_PERFMON28_PERFCOUNTER_STATE 0x08c9 15724 #define mmDC_PERFMON28_PERFCOUNTER_STATE_BASE_IDX 3 15725 #define mmDC_PERFMON28_PERFMON_CNTL 0x08ca 15726 #define mmDC_PERFMON28_PERFMON_CNTL_BASE_IDX 3 15727 #define mmDC_PERFMON28_PERFMON_CNTL2 0x08cb 15728 #define mmDC_PERFMON28_PERFMON_CNTL2_BASE_IDX 3 15729 #define mmDC_PERFMON28_PERFMON_CVALUE_INT_MISC 0x08cc 15730 #define mmDC_PERFMON28_PERFMON_CVALUE_INT_MISC_BASE_IDX 3 15731 #define mmDC_PERFMON28_PERFMON_CVALUE_LOW 0x08cd 15732 #define mmDC_PERFMON28_PERFMON_CVALUE_LOW_BASE_IDX 3 15733 #define mmDC_PERFMON28_PERFMON_HI 0x08ce 15734 #define mmDC_PERFMON28_PERFMON_HI_BASE_IDX 3 15735 #define mmDC_PERFMON28_PERFMON_LOW 0x08cf 15736 #define mmDC_PERFMON28_PERFMON_LOW_BASE_IDX 3 15737 15738 // base address: 0x2646c 15739 #define mmAFMT6_AFMT_VBI_PACKET_CONTROL 0x091c 15740 #define mmAFMT6_AFMT_VBI_PACKET_CONTROL_BASE_IDX 3 15741 #define mmAFMT6_AFMT_AUDIO_PACKET_CONTROL2 0x091d 15742 #define mmAFMT6_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 3 15743 #define mmAFMT6_AFMT_AUDIO_INFO0 0x091e 15744 #define mmAFMT6_AFMT_AUDIO_INFO0_BASE_IDX 3 15745 #define mmAFMT6_AFMT_AUDIO_INFO1 0x091f 15746 #define mmAFMT6_AFMT_AUDIO_INFO1_BASE_IDX 3 15747 #define mmAFMT6_AFMT_60958_0 0x0920 15748 #define mmAFMT6_AFMT_60958_0_BASE_IDX 3 15749 #define mmAFMT6_AFMT_60958_1 0x0921 15750 #define mmAFMT6_AFMT_60958_1_BASE_IDX 3 15751 #define mmAFMT6_AFMT_AUDIO_CRC_CONTROL 0x0922 15752 #define mmAFMT6_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 3 15753 #define mmAFMT6_AFMT_RAMP_CONTROL0 0x0923 15754 #define mmAFMT6_AFMT_RAMP_CONTROL0_BASE_IDX 3 15755 #define mmAFMT6_AFMT_RAMP_CONTROL1 0x0924 15756 #define mmAFMT6_AFMT_RAMP_CONTROL1_BASE_IDX 3 15757 #define mmAFMT6_AFMT_RAMP_CONTROL2 0x0925 15758 #define mmAFMT6_AFMT_RAMP_CONTROL2_BASE_IDX 3 15759 #define mmAFMT6_AFMT_RAMP_CONTROL3 0x0926 15760 #define mmAFMT6_AFMT_RAMP_CONTROL3_BASE_IDX 3 15761 #define mmAFMT6_AFMT_60958_2 0x0927 15762 #define mmAFMT6_AFMT_60958_2_BASE_IDX 3 15763 #define mmAFMT6_AFMT_AUDIO_CRC_RESULT 0x0928 15764 #define mmAFMT6_AFMT_AUDIO_CRC_RESULT_BASE_IDX 3 15765 #define mmAFMT6_AFMT_STATUS 0x0929 15766 #define mmAFMT6_AFMT_STATUS_BASE_IDX 3 15767 #define mmAFMT6_AFMT_AUDIO_PACKET_CONTROL 0x092a 15768 #define mmAFMT6_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 3 15769 #define mmAFMT6_AFMT_INFOFRAME_CONTROL0 0x092b 15770 #define mmAFMT6_AFMT_INFOFRAME_CONTROL0_BASE_IDX 3 15771 #define mmAFMT6_AFMT_INTERRUPT_STATUS 0x092c 15772 #define mmAFMT6_AFMT_INTERRUPT_STATUS_BASE_IDX 3 15773 #define mmAFMT6_AFMT_AUDIO_SRC_CONTROL 0x092d 15774 #define mmAFMT6_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 3 15775 #define mmAFMT6_AFMT_MEM_PWR 0x092f 15776 #define mmAFMT6_AFMT_MEM_PWR_BASE_IDX 3 15777 15778 15779 // base address: 0x264c4 15780 #define mmVPG6_VPG_GENERIC_PACKET_ACCESS_CTRL 0x0931 15781 #define mmVPG6_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 3 15782 #define mmVPG6_VPG_GENERIC_PACKET_DATA 0x0932 15783 #define mmVPG6_VPG_GENERIC_PACKET_DATA_BASE_IDX 3 15784 #define mmVPG6_VPG_GSP_FRAME_UPDATE_CTRL 0x0933 15785 #define mmVPG6_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 3 15786 #define mmVPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x0934 15787 #define mmVPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 3 15788 #define mmVPG6_VPG_GENERIC_STATUS 0x0935 15789 #define mmVPG6_VPG_GENERIC_STATUS_BASE_IDX 3 15790 #define mmVPG6_VPG_MEM_PWR 0x0936 15791 #define mmVPG6_VPG_MEM_PWR_BASE_IDX 3 15792 #define mmVPG6_VPG_ISRC1_2_ACCESS_CTRL 0x0937 15793 #define mmVPG6_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 3 15794 #define mmVPG6_VPG_ISRC1_2_DATA 0x0938 15795 #define mmVPG6_VPG_ISRC1_2_DATA_BASE_IDX 3 15796 #define mmVPG6_VPG_MPEG_INFO0 0x0939 15797 #define mmVPG6_VPG_MPEG_INFO0_BASE_IDX 3 15798 #define mmVPG6_VPG_MPEG_INFO1 0x093a 15799 #define mmVPG6_VPG_MPEG_INFO1_BASE_IDX 3 15800 15801 15802 // base address: 0x264f0 15803 #define mmDME6_DME_CONTROL 0x093c 15804 #define mmDME6_DME_CONTROL_BASE_IDX 3 15805 #define mmDME6_DME_MEMORY_CONTROL 0x093d 15806 #define mmDME6_DME_MEMORY_CONTROL_BASE_IDX 3 15807 15808 // addressBlock: dce_dc_hpo_hpo_top_dispdec 15809 // base address: 0x0 15810 #define mmHPO_TOP_CLOCK_CONTROL 0x0e43 15811 #define mmHPO_TOP_CLOCK_CONTROL_BASE_IDX 3 15812 15813 // base address: 0x1a698 15814 #define mmDC_PERFMON29_PERFCOUNTER_CNTL 0x0e66 15815 #define mmDC_PERFMON29_PERFCOUNTER_CNTL_BASE_IDX 3 15816 #define mmDC_PERFMON29_PERFCOUNTER_CNTL2 0x0e67 15817 #define mmDC_PERFMON29_PERFCOUNTER_CNTL2_BASE_IDX 3 15818 #define mmDC_PERFMON29_PERFCOUNTER_STATE 0x0e68 15819 #define mmDC_PERFMON29_PERFCOUNTER_STATE_BASE_IDX 3 15820 #define mmDC_PERFMON29_PERFMON_CNTL 0x0e69 15821 #define mmDC_PERFMON29_PERFMON_CNTL_BASE_IDX 3 15822 #define mmDC_PERFMON29_PERFMON_CNTL2 0x0e6a 15823 #define mmDC_PERFMON29_PERFMON_CNTL2_BASE_IDX 3 15824 #define mmDC_PERFMON29_PERFMON_CVALUE_INT_MISC 0x0e6b 15825 #define mmDC_PERFMON29_PERFMON_CVALUE_INT_MISC_BASE_IDX 3 15826 #define mmDC_PERFMON29_PERFMON_CVALUE_LOW 0x0e6c 15827 #define mmDC_PERFMON29_PERFMON_CVALUE_LOW_BASE_IDX 3 15828 #define mmDC_PERFMON29_PERFMON_HI 0x0e6d 15829 #define mmDC_PERFMON29_PERFMON_HI_BASE_IDX 3 15830 #define mmDC_PERFMON29_PERFMON_LOW 0x0e6e 15831 #define mmDC_PERFMON29_PERFMON_LOW_BASE_IDX 3 15832 15833 15834 // addressBlock: dce_dc_opp_abm0_dispdec 15835 // base address: 0x0 15836 #define mmABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL 0x0e7a 15837 #define mmABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 3 15838 #define mmABM0_BL1_PWM_USER_LEVEL 0x0e7b 15839 #define mmABM0_BL1_PWM_USER_LEVEL_BASE_IDX 3 15840 #define mmABM0_BL1_PWM_TARGET_ABM_LEVEL 0x0e7c 15841 #define mmABM0_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 3 15842 #define mmABM0_BL1_PWM_CURRENT_ABM_LEVEL 0x0e7d 15843 #define mmABM0_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 3 15844 #define mmABM0_BL1_PWM_FINAL_DUTY_CYCLE 0x0e7e 15845 #define mmABM0_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 3 15846 #define mmABM0_BL1_PWM_MINIMUM_DUTY_CYCLE 0x0e7f 15847 #define mmABM0_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 3 15848 #define mmABM0_BL1_PWM_ABM_CNTL 0x0e80 15849 #define mmABM0_BL1_PWM_ABM_CNTL_BASE_IDX 3 15850 #define mmABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE 0x0e81 15851 #define mmABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 3 15852 #define mmABM0_BL1_PWM_GRP2_REG_LOCK 0x0e82 15853 #define mmABM0_BL1_PWM_GRP2_REG_LOCK_BASE_IDX 3 15854 #define mmABM0_DC_ABM1_CNTL 0x0e83 15855 #define mmABM0_DC_ABM1_CNTL_BASE_IDX 3 15856 #define mmABM0_DC_ABM1_IPCSC_COEFF_SEL 0x0e84 15857 #define mmABM0_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 3 15858 #define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_0 0x0e85 15859 #define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX 3 15860 #define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_1 0x0e86 15861 #define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX 3 15862 #define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_2 0x0e87 15863 #define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX 3 15864 #define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_3 0x0e88 15865 #define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX 3 15866 #define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_4 0x0e89 15867 #define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX 3 15868 #define mmABM0_DC_ABM1_ACE_THRES_12 0x0e8a 15869 #define mmABM0_DC_ABM1_ACE_THRES_12_BASE_IDX 3 15870 #define mmABM0_DC_ABM1_ACE_THRES_34 0x0e8b 15871 #define mmABM0_DC_ABM1_ACE_THRES_34_BASE_IDX 3 15872 #define mmABM0_DC_ABM1_ACE_CNTL_MISC 0x0e8c 15873 #define mmABM0_DC_ABM1_ACE_CNTL_MISC_BASE_IDX 3 15874 #define mmABM0_DC_ABM1_HGLS_REG_READ_PROGRESS 0x0e8e 15875 #define mmABM0_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 3 15876 #define mmABM0_DC_ABM1_HG_MISC_CTRL 0x0e8f 15877 #define mmABM0_DC_ABM1_HG_MISC_CTRL_BASE_IDX 3 15878 #define mmABM0_DC_ABM1_LS_SUM_OF_LUMA 0x0e90 15879 #define mmABM0_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 3 15880 #define mmABM0_DC_ABM1_LS_MIN_MAX_LUMA 0x0e91 15881 #define mmABM0_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 3 15882 #define mmABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x0e92 15883 #define mmABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 3 15884 #define mmABM0_DC_ABM1_LS_PIXEL_COUNT 0x0e93 15885 #define mmABM0_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX 3 15886 #define mmABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x0e94 15887 #define mmABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 3 15888 #define mmABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x0e95 15889 #define mmABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 3 15890 #define mmABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x0e96 15891 #define mmABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 3 15892 #define mmABM0_DC_ABM1_HG_SAMPLE_RATE 0x0e97 15893 #define mmABM0_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX 3 15894 #define mmABM0_DC_ABM1_LS_SAMPLE_RATE 0x0e98 15895 #define mmABM0_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX 3 15896 #define mmABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x0e99 15897 #define mmABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 3 15898 #define mmABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x0e9a 15899 #define mmABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 3 15900 #define mmABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x0e9b 15901 #define mmABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 3 15902 #define mmABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x0e9c 15903 #define mmABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 3 15904 #define mmABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x0e9d 15905 #define mmABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 3 15906 #define mmABM0_DC_ABM1_HG_RESULT_1 0x0e9e 15907 #define mmABM0_DC_ABM1_HG_RESULT_1_BASE_IDX 3 15908 #define mmABM0_DC_ABM1_HG_RESULT_2 0x0e9f 15909 #define mmABM0_DC_ABM1_HG_RESULT_2_BASE_IDX 3 15910 #define mmABM0_DC_ABM1_HG_RESULT_3 0x0ea0 15911 #define mmABM0_DC_ABM1_HG_RESULT_3_BASE_IDX 3 15912 #define mmABM0_DC_ABM1_HG_RESULT_4 0x0ea1 15913 #define mmABM0_DC_ABM1_HG_RESULT_4_BASE_IDX 3 15914 #define mmABM0_DC_ABM1_HG_RESULT_5 0x0ea2 15915 #define mmABM0_DC_ABM1_HG_RESULT_5_BASE_IDX 3 15916 #define mmABM0_DC_ABM1_HG_RESULT_6 0x0ea3 15917 #define mmABM0_DC_ABM1_HG_RESULT_6_BASE_IDX 3 15918 #define mmABM0_DC_ABM1_HG_RESULT_7 0x0ea4 15919 #define mmABM0_DC_ABM1_HG_RESULT_7_BASE_IDX 3 15920 #define mmABM0_DC_ABM1_HG_RESULT_8 0x0ea5 15921 #define mmABM0_DC_ABM1_HG_RESULT_8_BASE_IDX 3 15922 #define mmABM0_DC_ABM1_HG_RESULT_9 0x0ea6 15923 #define mmABM0_DC_ABM1_HG_RESULT_9_BASE_IDX 3 15924 #define mmABM0_DC_ABM1_HG_RESULT_10 0x0ea7 15925 #define mmABM0_DC_ABM1_HG_RESULT_10_BASE_IDX 3 15926 #define mmABM0_DC_ABM1_HG_RESULT_11 0x0ea8 15927 #define mmABM0_DC_ABM1_HG_RESULT_11_BASE_IDX 3 15928 #define mmABM0_DC_ABM1_HG_RESULT_12 0x0ea9 15929 #define mmABM0_DC_ABM1_HG_RESULT_12_BASE_IDX 3 15930 #define mmABM0_DC_ABM1_HG_RESULT_13 0x0eaa 15931 #define mmABM0_DC_ABM1_HG_RESULT_13_BASE_IDX 3 15932 #define mmABM0_DC_ABM1_HG_RESULT_14 0x0eab 15933 #define mmABM0_DC_ABM1_HG_RESULT_14_BASE_IDX 3 15934 #define mmABM0_DC_ABM1_HG_RESULT_15 0x0eac 15935 #define mmABM0_DC_ABM1_HG_RESULT_15_BASE_IDX 3 15936 #define mmABM0_DC_ABM1_HG_RESULT_16 0x0ead 15937 #define mmABM0_DC_ABM1_HG_RESULT_16_BASE_IDX 3 15938 #define mmABM0_DC_ABM1_HG_RESULT_17 0x0eae 15939 #define mmABM0_DC_ABM1_HG_RESULT_17_BASE_IDX 3 15940 #define mmABM0_DC_ABM1_HG_RESULT_18 0x0eaf 15941 #define mmABM0_DC_ABM1_HG_RESULT_18_BASE_IDX 3 15942 #define mmABM0_DC_ABM1_HG_RESULT_19 0x0eb0 15943 #define mmABM0_DC_ABM1_HG_RESULT_19_BASE_IDX 3 15944 #define mmABM0_DC_ABM1_HG_RESULT_20 0x0eb1 15945 #define mmABM0_DC_ABM1_HG_RESULT_20_BASE_IDX 3 15946 #define mmABM0_DC_ABM1_HG_RESULT_21 0x0eb2 15947 #define mmABM0_DC_ABM1_HG_RESULT_21_BASE_IDX 3 15948 #define mmABM0_DC_ABM1_HG_RESULT_22 0x0eb3 15949 #define mmABM0_DC_ABM1_HG_RESULT_22_BASE_IDX 3 15950 #define mmABM0_DC_ABM1_HG_RESULT_23 0x0eb4 15951 #define mmABM0_DC_ABM1_HG_RESULT_23_BASE_IDX 3 15952 #define mmABM0_DC_ABM1_HG_RESULT_24 0x0eb5 15953 #define mmABM0_DC_ABM1_HG_RESULT_24_BASE_IDX 3 15954 #define mmABM0_DC_ABM1_BL_MASTER_LOCK 0x0eb6 15955 #define mmABM0_DC_ABM1_BL_MASTER_LOCK_BASE_IDX 3 15956 15957 15958 // addressBlock: dce_dc_opp_abm1_dispdec 15959 // base address: 0x104 15960 #define mmABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL 0x0ebb 15961 #define mmABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 3 15962 #define mmABM1_BL1_PWM_USER_LEVEL 0x0ebc 15963 #define mmABM1_BL1_PWM_USER_LEVEL_BASE_IDX 3 15964 #define mmABM1_BL1_PWM_TARGET_ABM_LEVEL 0x0ebd 15965 #define mmABM1_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 3 15966 #define mmABM1_BL1_PWM_CURRENT_ABM_LEVEL 0x0ebe 15967 #define mmABM1_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 3 15968 #define mmABM1_BL1_PWM_FINAL_DUTY_CYCLE 0x0ebf 15969 #define mmABM1_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 3 15970 #define mmABM1_BL1_PWM_MINIMUM_DUTY_CYCLE 0x0ec0 15971 #define mmABM1_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 3 15972 #define mmABM1_BL1_PWM_ABM_CNTL 0x0ec1 15973 #define mmABM1_BL1_PWM_ABM_CNTL_BASE_IDX 3 15974 #define mmABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE 0x0ec2 15975 #define mmABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 3 15976 #define mmABM1_BL1_PWM_GRP2_REG_LOCK 0x0ec3 15977 #define mmABM1_BL1_PWM_GRP2_REG_LOCK_BASE_IDX 3 15978 #define mmABM1_DC_ABM1_CNTL 0x0ec4 15979 #define mmABM1_DC_ABM1_CNTL_BASE_IDX 3 15980 #define mmABM1_DC_ABM1_IPCSC_COEFF_SEL 0x0ec5 15981 #define mmABM1_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 3 15982 #define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_0 0x0ec6 15983 #define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX 3 15984 #define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_1 0x0ec7 15985 #define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX 3 15986 #define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_2 0x0ec8 15987 #define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX 3 15988 #define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_3 0x0ec9 15989 #define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX 3 15990 #define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_4 0x0eca 15991 #define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX 3 15992 #define mmABM1_DC_ABM1_ACE_THRES_12 0x0ecb 15993 #define mmABM1_DC_ABM1_ACE_THRES_12_BASE_IDX 3 15994 #define mmABM1_DC_ABM1_ACE_THRES_34 0x0ecc 15995 #define mmABM1_DC_ABM1_ACE_THRES_34_BASE_IDX 3 15996 #define mmABM1_DC_ABM1_ACE_CNTL_MISC 0x0ecd 15997 #define mmABM1_DC_ABM1_ACE_CNTL_MISC_BASE_IDX 3 15998 #define mmABM1_DC_ABM1_HGLS_REG_READ_PROGRESS 0x0ecf 15999 #define mmABM1_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 3 16000 #define mmABM1_DC_ABM1_HG_MISC_CTRL 0x0ed0 16001 #define mmABM1_DC_ABM1_HG_MISC_CTRL_BASE_IDX 3 16002 #define mmABM1_DC_ABM1_LS_SUM_OF_LUMA 0x0ed1 16003 #define mmABM1_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 3 16004 #define mmABM1_DC_ABM1_LS_MIN_MAX_LUMA 0x0ed2 16005 #define mmABM1_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 3 16006 #define mmABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x0ed3 16007 #define mmABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 3 16008 #define mmABM1_DC_ABM1_LS_PIXEL_COUNT 0x0ed4 16009 #define mmABM1_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX 3 16010 #define mmABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x0ed5 16011 #define mmABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 3 16012 #define mmABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x0ed6 16013 #define mmABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 3 16014 #define mmABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x0ed7 16015 #define mmABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 3 16016 #define mmABM1_DC_ABM1_HG_SAMPLE_RATE 0x0ed8 16017 #define mmABM1_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX 3 16018 #define mmABM1_DC_ABM1_LS_SAMPLE_RATE 0x0ed9 16019 #define mmABM1_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX 3 16020 #define mmABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x0eda 16021 #define mmABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 3 16022 #define mmABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x0edb 16023 #define mmABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 3 16024 #define mmABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x0edc 16025 #define mmABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 3 16026 #define mmABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x0edd 16027 #define mmABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 3 16028 #define mmABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x0ede 16029 #define mmABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 3 16030 #define mmABM1_DC_ABM1_HG_RESULT_1 0x0edf 16031 #define mmABM1_DC_ABM1_HG_RESULT_1_BASE_IDX 3 16032 #define mmABM1_DC_ABM1_HG_RESULT_2 0x0ee0 16033 #define mmABM1_DC_ABM1_HG_RESULT_2_BASE_IDX 3 16034 #define mmABM1_DC_ABM1_HG_RESULT_3 0x0ee1 16035 #define mmABM1_DC_ABM1_HG_RESULT_3_BASE_IDX 3 16036 #define mmABM1_DC_ABM1_HG_RESULT_4 0x0ee2 16037 #define mmABM1_DC_ABM1_HG_RESULT_4_BASE_IDX 3 16038 #define mmABM1_DC_ABM1_HG_RESULT_5 0x0ee3 16039 #define mmABM1_DC_ABM1_HG_RESULT_5_BASE_IDX 3 16040 #define mmABM1_DC_ABM1_HG_RESULT_6 0x0ee4 16041 #define mmABM1_DC_ABM1_HG_RESULT_6_BASE_IDX 3 16042 #define mmABM1_DC_ABM1_HG_RESULT_7 0x0ee5 16043 #define mmABM1_DC_ABM1_HG_RESULT_7_BASE_IDX 3 16044 #define mmABM1_DC_ABM1_HG_RESULT_8 0x0ee6 16045 #define mmABM1_DC_ABM1_HG_RESULT_8_BASE_IDX 3 16046 #define mmABM1_DC_ABM1_HG_RESULT_9 0x0ee7 16047 #define mmABM1_DC_ABM1_HG_RESULT_9_BASE_IDX 3 16048 #define mmABM1_DC_ABM1_HG_RESULT_10 0x0ee8 16049 #define mmABM1_DC_ABM1_HG_RESULT_10_BASE_IDX 3 16050 #define mmABM1_DC_ABM1_HG_RESULT_11 0x0ee9 16051 #define mmABM1_DC_ABM1_HG_RESULT_11_BASE_IDX 3 16052 #define mmABM1_DC_ABM1_HG_RESULT_12 0x0eea 16053 #define mmABM1_DC_ABM1_HG_RESULT_12_BASE_IDX 3 16054 #define mmABM1_DC_ABM1_HG_RESULT_13 0x0eeb 16055 #define mmABM1_DC_ABM1_HG_RESULT_13_BASE_IDX 3 16056 #define mmABM1_DC_ABM1_HG_RESULT_14 0x0eec 16057 #define mmABM1_DC_ABM1_HG_RESULT_14_BASE_IDX 3 16058 #define mmABM1_DC_ABM1_HG_RESULT_15 0x0eed 16059 #define mmABM1_DC_ABM1_HG_RESULT_15_BASE_IDX 3 16060 #define mmABM1_DC_ABM1_HG_RESULT_16 0x0eee 16061 #define mmABM1_DC_ABM1_HG_RESULT_16_BASE_IDX 3 16062 #define mmABM1_DC_ABM1_HG_RESULT_17 0x0eef 16063 #define mmABM1_DC_ABM1_HG_RESULT_17_BASE_IDX 3 16064 #define mmABM1_DC_ABM1_HG_RESULT_18 0x0ef0 16065 #define mmABM1_DC_ABM1_HG_RESULT_18_BASE_IDX 3 16066 #define mmABM1_DC_ABM1_HG_RESULT_19 0x0ef1 16067 #define mmABM1_DC_ABM1_HG_RESULT_19_BASE_IDX 3 16068 #define mmABM1_DC_ABM1_HG_RESULT_20 0x0ef2 16069 #define mmABM1_DC_ABM1_HG_RESULT_20_BASE_IDX 3 16070 #define mmABM1_DC_ABM1_HG_RESULT_21 0x0ef3 16071 #define mmABM1_DC_ABM1_HG_RESULT_21_BASE_IDX 3 16072 #define mmABM1_DC_ABM1_HG_RESULT_22 0x0ef4 16073 #define mmABM1_DC_ABM1_HG_RESULT_22_BASE_IDX 3 16074 #define mmABM1_DC_ABM1_HG_RESULT_23 0x0ef5 16075 #define mmABM1_DC_ABM1_HG_RESULT_23_BASE_IDX 3 16076 #define mmABM1_DC_ABM1_HG_RESULT_24 0x0ef6 16077 #define mmABM1_DC_ABM1_HG_RESULT_24_BASE_IDX 3 16078 #define mmABM1_DC_ABM1_BL_MASTER_LOCK 0x0ef7 16079 #define mmABM1_DC_ABM1_BL_MASTER_LOCK_BASE_IDX 3 16080 16081 16082 // addressBlock: dce_dc_opp_abm2_dispdec 16083 // base address: 0x208 16084 #define mmABM2_BL1_PWM_AMBIENT_LIGHT_LEVEL 0x0efc 16085 #define mmABM2_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 3 16086 #define mmABM2_BL1_PWM_USER_LEVEL 0x0efd 16087 #define mmABM2_BL1_PWM_USER_LEVEL_BASE_IDX 3 16088 #define mmABM2_BL1_PWM_TARGET_ABM_LEVEL 0x0efe 16089 #define mmABM2_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 3 16090 #define mmABM2_BL1_PWM_CURRENT_ABM_LEVEL 0x0eff 16091 #define mmABM2_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 3 16092 #define mmABM2_BL1_PWM_FINAL_DUTY_CYCLE 0x0f00 16093 #define mmABM2_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 3 16094 #define mmABM2_BL1_PWM_MINIMUM_DUTY_CYCLE 0x0f01 16095 #define mmABM2_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 3 16096 #define mmABM2_BL1_PWM_ABM_CNTL 0x0f02 16097 #define mmABM2_BL1_PWM_ABM_CNTL_BASE_IDX 3 16098 #define mmABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE 0x0f03 16099 #define mmABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 3 16100 #define mmABM2_BL1_PWM_GRP2_REG_LOCK 0x0f04 16101 #define mmABM2_BL1_PWM_GRP2_REG_LOCK_BASE_IDX 3 16102 #define mmABM2_DC_ABM1_CNTL 0x0f05 16103 #define mmABM2_DC_ABM1_CNTL_BASE_IDX 3 16104 #define mmABM2_DC_ABM1_IPCSC_COEFF_SEL 0x0f06 16105 #define mmABM2_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 3 16106 #define mmABM2_DC_ABM1_ACE_OFFSET_SLOPE_0 0x0f07 16107 #define mmABM2_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX 3 16108 #define mmABM2_DC_ABM1_ACE_OFFSET_SLOPE_1 0x0f08 16109 #define mmABM2_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX 3 16110 #define mmABM2_DC_ABM1_ACE_OFFSET_SLOPE_2 0x0f09 16111 #define mmABM2_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX 3 16112 #define mmABM2_DC_ABM1_ACE_OFFSET_SLOPE_3 0x0f0a 16113 #define mmABM2_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX 3 16114 #define mmABM2_DC_ABM1_ACE_OFFSET_SLOPE_4 0x0f0b 16115 #define mmABM2_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX 3 16116 #define mmABM2_DC_ABM1_ACE_THRES_12 0x0f0c 16117 #define mmABM2_DC_ABM1_ACE_THRES_12_BASE_IDX 3 16118 #define mmABM2_DC_ABM1_ACE_THRES_34 0x0f0d 16119 #define mmABM2_DC_ABM1_ACE_THRES_34_BASE_IDX 3 16120 #define mmABM2_DC_ABM1_ACE_CNTL_MISC 0x0f0e 16121 #define mmABM2_DC_ABM1_ACE_CNTL_MISC_BASE_IDX 3 16122 #define mmABM2_DC_ABM1_HGLS_REG_READ_PROGRESS 0x0f10 16123 #define mmABM2_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 3 16124 #define mmABM2_DC_ABM1_HG_MISC_CTRL 0x0f11 16125 #define mmABM2_DC_ABM1_HG_MISC_CTRL_BASE_IDX 3 16126 #define mmABM2_DC_ABM1_LS_SUM_OF_LUMA 0x0f12 16127 #define mmABM2_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 3 16128 #define mmABM2_DC_ABM1_LS_MIN_MAX_LUMA 0x0f13 16129 #define mmABM2_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 3 16130 #define mmABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x0f14 16131 #define mmABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 3 16132 #define mmABM2_DC_ABM1_LS_PIXEL_COUNT 0x0f15 16133 #define mmABM2_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX 3 16134 #define mmABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x0f16 16135 #define mmABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 3 16136 #define mmABM2_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x0f17 16137 #define mmABM2_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 3 16138 #define mmABM2_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x0f18 16139 #define mmABM2_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 3 16140 #define mmABM2_DC_ABM1_HG_SAMPLE_RATE 0x0f19 16141 #define mmABM2_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX 3 16142 #define mmABM2_DC_ABM1_LS_SAMPLE_RATE 0x0f1a 16143 #define mmABM2_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX 3 16144 #define mmABM2_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x0f1b 16145 #define mmABM2_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 3 16146 #define mmABM2_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x0f1c 16147 #define mmABM2_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 3 16148 #define mmABM2_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x0f1d 16149 #define mmABM2_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 3 16150 #define mmABM2_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x0f1e 16151 #define mmABM2_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 3 16152 #define mmABM2_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x0f1f 16153 #define mmABM2_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 3 16154 #define mmABM2_DC_ABM1_HG_RESULT_1 0x0f20 16155 #define mmABM2_DC_ABM1_HG_RESULT_1_BASE_IDX 3 16156 #define mmABM2_DC_ABM1_HG_RESULT_2 0x0f21 16157 #define mmABM2_DC_ABM1_HG_RESULT_2_BASE_IDX 3 16158 #define mmABM2_DC_ABM1_HG_RESULT_3 0x0f22 16159 #define mmABM2_DC_ABM1_HG_RESULT_3_BASE_IDX 3 16160 #define mmABM2_DC_ABM1_HG_RESULT_4 0x0f23 16161 #define mmABM2_DC_ABM1_HG_RESULT_4_BASE_IDX 3 16162 #define mmABM2_DC_ABM1_HG_RESULT_5 0x0f24 16163 #define mmABM2_DC_ABM1_HG_RESULT_5_BASE_IDX 3 16164 #define mmABM2_DC_ABM1_HG_RESULT_6 0x0f25 16165 #define mmABM2_DC_ABM1_HG_RESULT_6_BASE_IDX 3 16166 #define mmABM2_DC_ABM1_HG_RESULT_7 0x0f26 16167 #define mmABM2_DC_ABM1_HG_RESULT_7_BASE_IDX 3 16168 #define mmABM2_DC_ABM1_HG_RESULT_8 0x0f27 16169 #define mmABM2_DC_ABM1_HG_RESULT_8_BASE_IDX 3 16170 #define mmABM2_DC_ABM1_HG_RESULT_9 0x0f28 16171 #define mmABM2_DC_ABM1_HG_RESULT_9_BASE_IDX 3 16172 #define mmABM2_DC_ABM1_HG_RESULT_10 0x0f29 16173 #define mmABM2_DC_ABM1_HG_RESULT_10_BASE_IDX 3 16174 #define mmABM2_DC_ABM1_HG_RESULT_11 0x0f2a 16175 #define mmABM2_DC_ABM1_HG_RESULT_11_BASE_IDX 3 16176 #define mmABM2_DC_ABM1_HG_RESULT_12 0x0f2b 16177 #define mmABM2_DC_ABM1_HG_RESULT_12_BASE_IDX 3 16178 #define mmABM2_DC_ABM1_HG_RESULT_13 0x0f2c 16179 #define mmABM2_DC_ABM1_HG_RESULT_13_BASE_IDX 3 16180 #define mmABM2_DC_ABM1_HG_RESULT_14 0x0f2d 16181 #define mmABM2_DC_ABM1_HG_RESULT_14_BASE_IDX 3 16182 #define mmABM2_DC_ABM1_HG_RESULT_15 0x0f2e 16183 #define mmABM2_DC_ABM1_HG_RESULT_15_BASE_IDX 3 16184 #define mmABM2_DC_ABM1_HG_RESULT_16 0x0f2f 16185 #define mmABM2_DC_ABM1_HG_RESULT_16_BASE_IDX 3 16186 #define mmABM2_DC_ABM1_HG_RESULT_17 0x0f30 16187 #define mmABM2_DC_ABM1_HG_RESULT_17_BASE_IDX 3 16188 #define mmABM2_DC_ABM1_HG_RESULT_18 0x0f31 16189 #define mmABM2_DC_ABM1_HG_RESULT_18_BASE_IDX 3 16190 #define mmABM2_DC_ABM1_HG_RESULT_19 0x0f32 16191 #define mmABM2_DC_ABM1_HG_RESULT_19_BASE_IDX 3 16192 #define mmABM2_DC_ABM1_HG_RESULT_20 0x0f33 16193 #define mmABM2_DC_ABM1_HG_RESULT_20_BASE_IDX 3 16194 #define mmABM2_DC_ABM1_HG_RESULT_21 0x0f34 16195 #define mmABM2_DC_ABM1_HG_RESULT_21_BASE_IDX 3 16196 #define mmABM2_DC_ABM1_HG_RESULT_22 0x0f35 16197 #define mmABM2_DC_ABM1_HG_RESULT_22_BASE_IDX 3 16198 #define mmABM2_DC_ABM1_HG_RESULT_23 0x0f36 16199 #define mmABM2_DC_ABM1_HG_RESULT_23_BASE_IDX 3 16200 #define mmABM2_DC_ABM1_HG_RESULT_24 0x0f37 16201 #define mmABM2_DC_ABM1_HG_RESULT_24_BASE_IDX 3 16202 #define mmABM2_DC_ABM1_BL_MASTER_LOCK 0x0f38 16203 #define mmABM2_DC_ABM1_BL_MASTER_LOCK_BASE_IDX 3 16204 16205 16206 // addressBlock: dce_dc_opp_abm3_dispdec 16207 // base address: 0x30c 16208 #define mmABM3_BL1_PWM_AMBIENT_LIGHT_LEVEL 0x0f3d 16209 #define mmABM3_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 3 16210 #define mmABM3_BL1_PWM_USER_LEVEL 0x0f3e 16211 #define mmABM3_BL1_PWM_USER_LEVEL_BASE_IDX 3 16212 #define mmABM3_BL1_PWM_TARGET_ABM_LEVEL 0x0f3f 16213 #define mmABM3_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 3 16214 #define mmABM3_BL1_PWM_CURRENT_ABM_LEVEL 0x0f40 16215 #define mmABM3_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 3 16216 #define mmABM3_BL1_PWM_FINAL_DUTY_CYCLE 0x0f41 16217 #define mmABM3_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 3 16218 #define mmABM3_BL1_PWM_MINIMUM_DUTY_CYCLE 0x0f42 16219 #define mmABM3_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 3 16220 #define mmABM3_BL1_PWM_ABM_CNTL 0x0f43 16221 #define mmABM3_BL1_PWM_ABM_CNTL_BASE_IDX 3 16222 #define mmABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE 0x0f44 16223 #define mmABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 3 16224 #define mmABM3_BL1_PWM_GRP2_REG_LOCK 0x0f45 16225 #define mmABM3_BL1_PWM_GRP2_REG_LOCK_BASE_IDX 3 16226 #define mmABM3_DC_ABM1_CNTL 0x0f46 16227 #define mmABM3_DC_ABM1_CNTL_BASE_IDX 3 16228 #define mmABM3_DC_ABM1_IPCSC_COEFF_SEL 0x0f47 16229 #define mmABM3_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 3 16230 #define mmABM3_DC_ABM1_ACE_OFFSET_SLOPE_0 0x0f48 16231 #define mmABM3_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX 3 16232 #define mmABM3_DC_ABM1_ACE_OFFSET_SLOPE_1 0x0f49 16233 #define mmABM3_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX 3 16234 #define mmABM3_DC_ABM1_ACE_OFFSET_SLOPE_2 0x0f4a 16235 #define mmABM3_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX 3 16236 #define mmABM3_DC_ABM1_ACE_OFFSET_SLOPE_3 0x0f4b 16237 #define mmABM3_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX 3 16238 #define mmABM3_DC_ABM1_ACE_OFFSET_SLOPE_4 0x0f4c 16239 #define mmABM3_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX 3 16240 #define mmABM3_DC_ABM1_ACE_THRES_12 0x0f4d 16241 #define mmABM3_DC_ABM1_ACE_THRES_12_BASE_IDX 3 16242 #define mmABM3_DC_ABM1_ACE_THRES_34 0x0f4e 16243 #define mmABM3_DC_ABM1_ACE_THRES_34_BASE_IDX 3 16244 #define mmABM3_DC_ABM1_ACE_CNTL_MISC 0x0f4f 16245 #define mmABM3_DC_ABM1_ACE_CNTL_MISC_BASE_IDX 3 16246 #define mmABM3_DC_ABM1_HGLS_REG_READ_PROGRESS 0x0f51 16247 #define mmABM3_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 3 16248 #define mmABM3_DC_ABM1_HG_MISC_CTRL 0x0f52 16249 #define mmABM3_DC_ABM1_HG_MISC_CTRL_BASE_IDX 3 16250 #define mmABM3_DC_ABM1_LS_SUM_OF_LUMA 0x0f53 16251 #define mmABM3_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 3 16252 #define mmABM3_DC_ABM1_LS_MIN_MAX_LUMA 0x0f54 16253 #define mmABM3_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 3 16254 #define mmABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x0f55 16255 #define mmABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 3 16256 #define mmABM3_DC_ABM1_LS_PIXEL_COUNT 0x0f56 16257 #define mmABM3_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX 3 16258 #define mmABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x0f57 16259 #define mmABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 3 16260 #define mmABM3_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x0f58 16261 #define mmABM3_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 3 16262 #define mmABM3_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x0f59 16263 #define mmABM3_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 3 16264 #define mmABM3_DC_ABM1_HG_SAMPLE_RATE 0x0f5a 16265 #define mmABM3_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX 3 16266 #define mmABM3_DC_ABM1_LS_SAMPLE_RATE 0x0f5b 16267 #define mmABM3_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX 3 16268 #define mmABM3_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x0f5c 16269 #define mmABM3_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 3 16270 #define mmABM3_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x0f5d 16271 #define mmABM3_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 3 16272 #define mmABM3_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x0f5e 16273 #define mmABM3_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 3 16274 #define mmABM3_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x0f5f 16275 #define mmABM3_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 3 16276 #define mmABM3_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x0f60 16277 #define mmABM3_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 3 16278 #define mmABM3_DC_ABM1_HG_RESULT_1 0x0f61 16279 #define mmABM3_DC_ABM1_HG_RESULT_1_BASE_IDX 3 16280 #define mmABM3_DC_ABM1_HG_RESULT_2 0x0f62 16281 #define mmABM3_DC_ABM1_HG_RESULT_2_BASE_IDX 3 16282 #define mmABM3_DC_ABM1_HG_RESULT_3 0x0f63 16283 #define mmABM3_DC_ABM1_HG_RESULT_3_BASE_IDX 3 16284 #define mmABM3_DC_ABM1_HG_RESULT_4 0x0f64 16285 #define mmABM3_DC_ABM1_HG_RESULT_4_BASE_IDX 3 16286 #define mmABM3_DC_ABM1_HG_RESULT_5 0x0f65 16287 #define mmABM3_DC_ABM1_HG_RESULT_5_BASE_IDX 3 16288 #define mmABM3_DC_ABM1_HG_RESULT_6 0x0f66 16289 #define mmABM3_DC_ABM1_HG_RESULT_6_BASE_IDX 3 16290 #define mmABM3_DC_ABM1_HG_RESULT_7 0x0f67 16291 #define mmABM3_DC_ABM1_HG_RESULT_7_BASE_IDX 3 16292 #define mmABM3_DC_ABM1_HG_RESULT_8 0x0f68 16293 #define mmABM3_DC_ABM1_HG_RESULT_8_BASE_IDX 3 16294 #define mmABM3_DC_ABM1_HG_RESULT_9 0x0f69 16295 #define mmABM3_DC_ABM1_HG_RESULT_9_BASE_IDX 3 16296 #define mmABM3_DC_ABM1_HG_RESULT_10 0x0f6a 16297 #define mmABM3_DC_ABM1_HG_RESULT_10_BASE_IDX 3 16298 #define mmABM3_DC_ABM1_HG_RESULT_11 0x0f6b 16299 #define mmABM3_DC_ABM1_HG_RESULT_11_BASE_IDX 3 16300 #define mmABM3_DC_ABM1_HG_RESULT_12 0x0f6c 16301 #define mmABM3_DC_ABM1_HG_RESULT_12_BASE_IDX 3 16302 #define mmABM3_DC_ABM1_HG_RESULT_13 0x0f6d 16303 #define mmABM3_DC_ABM1_HG_RESULT_13_BASE_IDX 3 16304 #define mmABM3_DC_ABM1_HG_RESULT_14 0x0f6e 16305 #define mmABM3_DC_ABM1_HG_RESULT_14_BASE_IDX 3 16306 #define mmABM3_DC_ABM1_HG_RESULT_15 0x0f6f 16307 #define mmABM3_DC_ABM1_HG_RESULT_15_BASE_IDX 3 16308 #define mmABM3_DC_ABM1_HG_RESULT_16 0x0f70 16309 #define mmABM3_DC_ABM1_HG_RESULT_16_BASE_IDX 3 16310 #define mmABM3_DC_ABM1_HG_RESULT_17 0x0f71 16311 #define mmABM3_DC_ABM1_HG_RESULT_17_BASE_IDX 3 16312 #define mmABM3_DC_ABM1_HG_RESULT_18 0x0f72 16313 #define mmABM3_DC_ABM1_HG_RESULT_18_BASE_IDX 3 16314 #define mmABM3_DC_ABM1_HG_RESULT_19 0x0f73 16315 #define mmABM3_DC_ABM1_HG_RESULT_19_BASE_IDX 3 16316 #define mmABM3_DC_ABM1_HG_RESULT_20 0x0f74 16317 #define mmABM3_DC_ABM1_HG_RESULT_20_BASE_IDX 3 16318 #define mmABM3_DC_ABM1_HG_RESULT_21 0x0f75 16319 #define mmABM3_DC_ABM1_HG_RESULT_21_BASE_IDX 3 16320 #define mmABM3_DC_ABM1_HG_RESULT_22 0x0f76 16321 #define mmABM3_DC_ABM1_HG_RESULT_22_BASE_IDX 3 16322 #define mmABM3_DC_ABM1_HG_RESULT_23 0x0f77 16323 #define mmABM3_DC_ABM1_HG_RESULT_23_BASE_IDX 3 16324 #define mmABM3_DC_ABM1_HG_RESULT_24 0x0f78 16325 #define mmABM3_DC_ABM1_HG_RESULT_24_BASE_IDX 3 16326 #define mmABM3_DC_ABM1_BL_MASTER_LOCK 0x0f79 16327 #define mmABM3_DC_ABM1_BL_MASTER_LOCK_BASE_IDX 3 16328 16329 16330 // addressBlock: dce_dc_opp_abm4_dispdec 16331 // base address: 0x410 16332 #define mmABM4_BL1_PWM_AMBIENT_LIGHT_LEVEL 0x0f7e 16333 #define mmABM4_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 3 16334 #define mmABM4_BL1_PWM_USER_LEVEL 0x0f7f 16335 #define mmABM4_BL1_PWM_USER_LEVEL_BASE_IDX 3 16336 #define mmABM4_BL1_PWM_TARGET_ABM_LEVEL 0x0f80 16337 #define mmABM4_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 3 16338 #define mmABM4_BL1_PWM_CURRENT_ABM_LEVEL 0x0f81 16339 #define mmABM4_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 3 16340 #define mmABM4_BL1_PWM_FINAL_DUTY_CYCLE 0x0f82 16341 #define mmABM4_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 3 16342 #define mmABM4_BL1_PWM_MINIMUM_DUTY_CYCLE 0x0f83 16343 #define mmABM4_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 3 16344 #define mmABM4_BL1_PWM_ABM_CNTL 0x0f84 16345 #define mmABM4_BL1_PWM_ABM_CNTL_BASE_IDX 3 16346 #define mmABM4_BL1_PWM_BL_UPDATE_SAMPLE_RATE 0x0f85 16347 #define mmABM4_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 3 16348 #define mmABM4_BL1_PWM_GRP2_REG_LOCK 0x0f86 16349 #define mmABM4_BL1_PWM_GRP2_REG_LOCK_BASE_IDX 3 16350 #define mmABM4_DC_ABM1_CNTL 0x0f87 16351 #define mmABM4_DC_ABM1_CNTL_BASE_IDX 3 16352 #define mmABM4_DC_ABM1_IPCSC_COEFF_SEL 0x0f88 16353 #define mmABM4_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 3 16354 #define mmABM4_DC_ABM1_ACE_OFFSET_SLOPE_0 0x0f89 16355 #define mmABM4_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX 3 16356 #define mmABM4_DC_ABM1_ACE_OFFSET_SLOPE_1 0x0f8a 16357 #define mmABM4_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX 3 16358 #define mmABM4_DC_ABM1_ACE_OFFSET_SLOPE_2 0x0f8b 16359 #define mmABM4_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX 3 16360 #define mmABM4_DC_ABM1_ACE_OFFSET_SLOPE_3 0x0f8c 16361 #define mmABM4_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX 3 16362 #define mmABM4_DC_ABM1_ACE_OFFSET_SLOPE_4 0x0f8d 16363 #define mmABM4_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX 3 16364 #define mmABM4_DC_ABM1_ACE_THRES_12 0x0f8e 16365 #define mmABM4_DC_ABM1_ACE_THRES_12_BASE_IDX 3 16366 #define mmABM4_DC_ABM1_ACE_THRES_34 0x0f8f 16367 #define mmABM4_DC_ABM1_ACE_THRES_34_BASE_IDX 3 16368 #define mmABM4_DC_ABM1_ACE_CNTL_MISC 0x0f90 16369 #define mmABM4_DC_ABM1_ACE_CNTL_MISC_BASE_IDX 3 16370 #define mmABM4_DC_ABM1_HGLS_REG_READ_PROGRESS 0x0f92 16371 #define mmABM4_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 3 16372 #define mmABM4_DC_ABM1_HG_MISC_CTRL 0x0f93 16373 #define mmABM4_DC_ABM1_HG_MISC_CTRL_BASE_IDX 3 16374 #define mmABM4_DC_ABM1_LS_SUM_OF_LUMA 0x0f94 16375 #define mmABM4_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 3 16376 #define mmABM4_DC_ABM1_LS_MIN_MAX_LUMA 0x0f95 16377 #define mmABM4_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 3 16378 #define mmABM4_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x0f96 16379 #define mmABM4_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 3 16380 #define mmABM4_DC_ABM1_LS_PIXEL_COUNT 0x0f97 16381 #define mmABM4_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX 3 16382 #define mmABM4_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x0f98 16383 #define mmABM4_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 3 16384 #define mmABM4_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x0f99 16385 #define mmABM4_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 3 16386 #define mmABM4_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x0f9a 16387 #define mmABM4_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 3 16388 #define mmABM4_DC_ABM1_HG_SAMPLE_RATE 0x0f9b 16389 #define mmABM4_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX 3 16390 #define mmABM4_DC_ABM1_LS_SAMPLE_RATE 0x0f9c 16391 #define mmABM4_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX 3 16392 #define mmABM4_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x0f9d 16393 #define mmABM4_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 3 16394 #define mmABM4_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x0f9e 16395 #define mmABM4_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 3 16396 #define mmABM4_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x0f9f 16397 #define mmABM4_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 3 16398 #define mmABM4_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x0fa0 16399 #define mmABM4_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 3 16400 #define mmABM4_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x0fa1 16401 #define mmABM4_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 3 16402 #define mmABM4_DC_ABM1_HG_RESULT_1 0x0fa2 16403 #define mmABM4_DC_ABM1_HG_RESULT_1_BASE_IDX 3 16404 #define mmABM4_DC_ABM1_HG_RESULT_2 0x0fa3 16405 #define mmABM4_DC_ABM1_HG_RESULT_2_BASE_IDX 3 16406 #define mmABM4_DC_ABM1_HG_RESULT_3 0x0fa4 16407 #define mmABM4_DC_ABM1_HG_RESULT_3_BASE_IDX 3 16408 #define mmABM4_DC_ABM1_HG_RESULT_4 0x0fa5 16409 #define mmABM4_DC_ABM1_HG_RESULT_4_BASE_IDX 3 16410 #define mmABM4_DC_ABM1_HG_RESULT_5 0x0fa6 16411 #define mmABM4_DC_ABM1_HG_RESULT_5_BASE_IDX 3 16412 #define mmABM4_DC_ABM1_HG_RESULT_6 0x0fa7 16413 #define mmABM4_DC_ABM1_HG_RESULT_6_BASE_IDX 3 16414 #define mmABM4_DC_ABM1_HG_RESULT_7 0x0fa8 16415 #define mmABM4_DC_ABM1_HG_RESULT_7_BASE_IDX 3 16416 #define mmABM4_DC_ABM1_HG_RESULT_8 0x0fa9 16417 #define mmABM4_DC_ABM1_HG_RESULT_8_BASE_IDX 3 16418 #define mmABM4_DC_ABM1_HG_RESULT_9 0x0faa 16419 #define mmABM4_DC_ABM1_HG_RESULT_9_BASE_IDX 3 16420 #define mmABM4_DC_ABM1_HG_RESULT_10 0x0fab 16421 #define mmABM4_DC_ABM1_HG_RESULT_10_BASE_IDX 3 16422 #define mmABM4_DC_ABM1_HG_RESULT_11 0x0fac 16423 #define mmABM4_DC_ABM1_HG_RESULT_11_BASE_IDX 3 16424 #define mmABM4_DC_ABM1_HG_RESULT_12 0x0fad 16425 #define mmABM4_DC_ABM1_HG_RESULT_12_BASE_IDX 3 16426 #define mmABM4_DC_ABM1_HG_RESULT_13 0x0fae 16427 #define mmABM4_DC_ABM1_HG_RESULT_13_BASE_IDX 3 16428 #define mmABM4_DC_ABM1_HG_RESULT_14 0x0faf 16429 #define mmABM4_DC_ABM1_HG_RESULT_14_BASE_IDX 3 16430 #define mmABM4_DC_ABM1_HG_RESULT_15 0x0fb0 16431 #define mmABM4_DC_ABM1_HG_RESULT_15_BASE_IDX 3 16432 #define mmABM4_DC_ABM1_HG_RESULT_16 0x0fb1 16433 #define mmABM4_DC_ABM1_HG_RESULT_16_BASE_IDX 3 16434 #define mmABM4_DC_ABM1_HG_RESULT_17 0x0fb2 16435 #define mmABM4_DC_ABM1_HG_RESULT_17_BASE_IDX 3 16436 #define mmABM4_DC_ABM1_HG_RESULT_18 0x0fb3 16437 #define mmABM4_DC_ABM1_HG_RESULT_18_BASE_IDX 3 16438 #define mmABM4_DC_ABM1_HG_RESULT_19 0x0fb4 16439 #define mmABM4_DC_ABM1_HG_RESULT_19_BASE_IDX 3 16440 #define mmABM4_DC_ABM1_HG_RESULT_20 0x0fb5 16441 #define mmABM4_DC_ABM1_HG_RESULT_20_BASE_IDX 3 16442 #define mmABM4_DC_ABM1_HG_RESULT_21 0x0fb6 16443 #define mmABM4_DC_ABM1_HG_RESULT_21_BASE_IDX 3 16444 #define mmABM4_DC_ABM1_HG_RESULT_22 0x0fb7 16445 #define mmABM4_DC_ABM1_HG_RESULT_22_BASE_IDX 3 16446 #define mmABM4_DC_ABM1_HG_RESULT_23 0x0fb8 16447 #define mmABM4_DC_ABM1_HG_RESULT_23_BASE_IDX 3 16448 #define mmABM4_DC_ABM1_HG_RESULT_24 0x0fb9 16449 #define mmABM4_DC_ABM1_HG_RESULT_24_BASE_IDX 3 16450 #define mmABM4_DC_ABM1_BL_MASTER_LOCK 0x0fba 16451 #define mmABM4_DC_ABM1_BL_MASTER_LOCK_BASE_IDX 3 16452 16453 16454 // addressBlock: dce_dc_opp_abm5_dispdec 16455 // base address: 0x514 16456 #define mmABM5_BL1_PWM_AMBIENT_LIGHT_LEVEL 0x0fbf 16457 #define mmABM5_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 3 16458 #define mmABM5_BL1_PWM_USER_LEVEL 0x0fc0 16459 #define mmABM5_BL1_PWM_USER_LEVEL_BASE_IDX 3 16460 #define mmABM5_BL1_PWM_TARGET_ABM_LEVEL 0x0fc1 16461 #define mmABM5_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 3 16462 #define mmABM5_BL1_PWM_CURRENT_ABM_LEVEL 0x0fc2 16463 #define mmABM5_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 3 16464 #define mmABM5_BL1_PWM_FINAL_DUTY_CYCLE 0x0fc3 16465 #define mmABM5_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 3 16466 #define mmABM5_BL1_PWM_MINIMUM_DUTY_CYCLE 0x0fc4 16467 #define mmABM5_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 3 16468 #define mmABM5_BL1_PWM_ABM_CNTL 0x0fc5 16469 #define mmABM5_BL1_PWM_ABM_CNTL_BASE_IDX 3 16470 #define mmABM5_BL1_PWM_BL_UPDATE_SAMPLE_RATE 0x0fc6 16471 #define mmABM5_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 3 16472 #define mmABM5_BL1_PWM_GRP2_REG_LOCK 0x0fc7 16473 #define mmABM5_BL1_PWM_GRP2_REG_LOCK_BASE_IDX 3 16474 #define mmABM5_DC_ABM1_CNTL 0x0fc8 16475 #define mmABM5_DC_ABM1_CNTL_BASE_IDX 3 16476 #define mmABM5_DC_ABM1_IPCSC_COEFF_SEL 0x0fc9 16477 #define mmABM5_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 3 16478 #define mmABM5_DC_ABM1_ACE_OFFSET_SLOPE_0 0x0fca 16479 #define mmABM5_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX 3 16480 #define mmABM5_DC_ABM1_ACE_OFFSET_SLOPE_1 0x0fcb 16481 #define mmABM5_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX 3 16482 #define mmABM5_DC_ABM1_ACE_OFFSET_SLOPE_2 0x0fcc 16483 #define mmABM5_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX 3 16484 #define mmABM5_DC_ABM1_ACE_OFFSET_SLOPE_3 0x0fcd 16485 #define mmABM5_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX 3 16486 #define mmABM5_DC_ABM1_ACE_OFFSET_SLOPE_4 0x0fce 16487 #define mmABM5_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX 3 16488 #define mmABM5_DC_ABM1_ACE_THRES_12 0x0fcf 16489 #define mmABM5_DC_ABM1_ACE_THRES_12_BASE_IDX 3 16490 #define mmABM5_DC_ABM1_ACE_THRES_34 0x0fd0 16491 #define mmABM5_DC_ABM1_ACE_THRES_34_BASE_IDX 3 16492 #define mmABM5_DC_ABM1_ACE_CNTL_MISC 0x0fd1 16493 #define mmABM5_DC_ABM1_ACE_CNTL_MISC_BASE_IDX 3 16494 #define mmABM5_DC_ABM1_HGLS_REG_READ_PROGRESS 0x0fd3 16495 #define mmABM5_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 3 16496 #define mmABM5_DC_ABM1_HG_MISC_CTRL 0x0fd4 16497 #define mmABM5_DC_ABM1_HG_MISC_CTRL_BASE_IDX 3 16498 #define mmABM5_DC_ABM1_LS_SUM_OF_LUMA 0x0fd5 16499 #define mmABM5_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 3 16500 #define mmABM5_DC_ABM1_LS_MIN_MAX_LUMA 0x0fd6 16501 #define mmABM5_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 3 16502 #define mmABM5_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x0fd7 16503 #define mmABM5_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 3 16504 #define mmABM5_DC_ABM1_LS_PIXEL_COUNT 0x0fd8 16505 #define mmABM5_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX 3 16506 #define mmABM5_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x0fd9 16507 #define mmABM5_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 3 16508 #define mmABM5_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x0fda 16509 #define mmABM5_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 3 16510 #define mmABM5_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x0fdb 16511 #define mmABM5_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 3 16512 #define mmABM5_DC_ABM1_HG_SAMPLE_RATE 0x0fdc 16513 #define mmABM5_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX 3 16514 #define mmABM5_DC_ABM1_LS_SAMPLE_RATE 0x0fdd 16515 #define mmABM5_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX 3 16516 #define mmABM5_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x0fde 16517 #define mmABM5_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 3 16518 #define mmABM5_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x0fdf 16519 #define mmABM5_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 3 16520 #define mmABM5_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x0fe0 16521 #define mmABM5_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 3 16522 #define mmABM5_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x0fe1 16523 #define mmABM5_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 3 16524 #define mmABM5_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x0fe2 16525 #define mmABM5_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 3 16526 #define mmABM5_DC_ABM1_HG_RESULT_1 0x0fe3 16527 #define mmABM5_DC_ABM1_HG_RESULT_1_BASE_IDX 3 16528 #define mmABM5_DC_ABM1_HG_RESULT_2 0x0fe4 16529 #define mmABM5_DC_ABM1_HG_RESULT_2_BASE_IDX 3 16530 #define mmABM5_DC_ABM1_HG_RESULT_3 0x0fe5 16531 #define mmABM5_DC_ABM1_HG_RESULT_3_BASE_IDX 3 16532 #define mmABM5_DC_ABM1_HG_RESULT_4 0x0fe6 16533 #define mmABM5_DC_ABM1_HG_RESULT_4_BASE_IDX 3 16534 #define mmABM5_DC_ABM1_HG_RESULT_5 0x0fe7 16535 #define mmABM5_DC_ABM1_HG_RESULT_5_BASE_IDX 3 16536 #define mmABM5_DC_ABM1_HG_RESULT_6 0x0fe8 16537 #define mmABM5_DC_ABM1_HG_RESULT_6_BASE_IDX 3 16538 #define mmABM5_DC_ABM1_HG_RESULT_7 0x0fe9 16539 #define mmABM5_DC_ABM1_HG_RESULT_7_BASE_IDX 3 16540 #define mmABM5_DC_ABM1_HG_RESULT_8 0x0fea 16541 #define mmABM5_DC_ABM1_HG_RESULT_8_BASE_IDX 3 16542 #define mmABM5_DC_ABM1_HG_RESULT_9 0x0feb 16543 #define mmABM5_DC_ABM1_HG_RESULT_9_BASE_IDX 3 16544 #define mmABM5_DC_ABM1_HG_RESULT_10 0x0fec 16545 #define mmABM5_DC_ABM1_HG_RESULT_10_BASE_IDX 3 16546 #define mmABM5_DC_ABM1_HG_RESULT_11 0x0fed 16547 #define mmABM5_DC_ABM1_HG_RESULT_11_BASE_IDX 3 16548 #define mmABM5_DC_ABM1_HG_RESULT_12 0x0fee 16549 #define mmABM5_DC_ABM1_HG_RESULT_12_BASE_IDX 3 16550 #define mmABM5_DC_ABM1_HG_RESULT_13 0x0fef 16551 #define mmABM5_DC_ABM1_HG_RESULT_13_BASE_IDX 3 16552 #define mmABM5_DC_ABM1_HG_RESULT_14 0x0ff0 16553 #define mmABM5_DC_ABM1_HG_RESULT_14_BASE_IDX 3 16554 #define mmABM5_DC_ABM1_HG_RESULT_15 0x0ff1 16555 #define mmABM5_DC_ABM1_HG_RESULT_15_BASE_IDX 3 16556 #define mmABM5_DC_ABM1_HG_RESULT_16 0x0ff2 16557 #define mmABM5_DC_ABM1_HG_RESULT_16_BASE_IDX 3 16558 #define mmABM5_DC_ABM1_HG_RESULT_17 0x0ff3 16559 #define mmABM5_DC_ABM1_HG_RESULT_17_BASE_IDX 3 16560 #define mmABM5_DC_ABM1_HG_RESULT_18 0x0ff4 16561 #define mmABM5_DC_ABM1_HG_RESULT_18_BASE_IDX 3 16562 #define mmABM5_DC_ABM1_HG_RESULT_19 0x0ff5 16563 #define mmABM5_DC_ABM1_HG_RESULT_19_BASE_IDX 3 16564 #define mmABM5_DC_ABM1_HG_RESULT_20 0x0ff6 16565 #define mmABM5_DC_ABM1_HG_RESULT_20_BASE_IDX 3 16566 #define mmABM5_DC_ABM1_HG_RESULT_21 0x0ff7 16567 #define mmABM5_DC_ABM1_HG_RESULT_21_BASE_IDX 3 16568 #define mmABM5_DC_ABM1_HG_RESULT_22 0x0ff8 16569 #define mmABM5_DC_ABM1_HG_RESULT_22_BASE_IDX 3 16570 #define mmABM5_DC_ABM1_HG_RESULT_23 0x0ff9 16571 #define mmABM5_DC_ABM1_HG_RESULT_23_BASE_IDX 3 16572 #define mmABM5_DC_ABM1_HG_RESULT_24 0x0ffa 16573 #define mmABM5_DC_ABM1_HG_RESULT_24_BASE_IDX 3 16574 #define mmABM5_DC_ABM1_BL_MASTER_LOCK 0x0ffb 16575 #define mmABM5_DC_ABM1_BL_MASTER_LOCK_BASE_IDX 3 16576 16577 16578 // addressBlock: dce_dc_hda_azcontroller_azdec 16579 // base address: 0x0 16580 #define mmCORB_WRITE_POINTER 0x0000 16581 #define mmCORB_WRITE_POINTER_BASE_IDX 0 16582 #define mmCORB_READ_POINTER 0x0000 16583 #define mmCORB_READ_POINTER_BASE_IDX 0 16584 #define mmCORB_CONTROL 0x0001 16585 #define mmCORB_CONTROL_BASE_IDX 0 16586 #define mmCORB_STATUS 0x0001 16587 #define mmCORB_STATUS_BASE_IDX 0 16588 #define mmCORB_SIZE 0x0001 16589 #define mmCORB_SIZE_BASE_IDX 0 16590 #define mmRIRB_LOWER_BASE_ADDRESS 0x0002 16591 #define mmRIRB_LOWER_BASE_ADDRESS_BASE_IDX 0 16592 #define mmRIRB_UPPER_BASE_ADDRESS 0x0003 16593 #define mmRIRB_UPPER_BASE_ADDRESS_BASE_IDX 0 16594 #define mmRIRB_WRITE_POINTER 0x0004 16595 #define mmRIRB_WRITE_POINTER_BASE_IDX 0 16596 #define mmRESPONSE_INTERRUPT_COUNT 0x0004 16597 #define mmRESPONSE_INTERRUPT_COUNT_BASE_IDX 0 16598 #define mmRIRB_CONTROL 0x0005 16599 #define mmRIRB_CONTROL_BASE_IDX 0 16600 #define mmRIRB_STATUS 0x0005 16601 #define mmRIRB_STATUS_BASE_IDX 0 16602 #define mmRIRB_SIZE 0x0005 16603 #define mmRIRB_SIZE_BASE_IDX 0 16604 #define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE 0x0006 16605 #define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_BASE_IDX 0 16606 #define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x0006 16607 #define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 0 16608 #define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x0006 16609 #define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 0 16610 #define mmIMMEDIATE_RESPONSE_INPUT_INTERFACE 0x0007 16611 #define mmIMMEDIATE_RESPONSE_INPUT_INTERFACE_BASE_IDX 0 16612 #define mmIMMEDIATE_COMMAND_STATUS 0x0008 16613 #define mmIMMEDIATE_COMMAND_STATUS_BASE_IDX 0 16614 #define mmDMA_POSITION_LOWER_BASE_ADDRESS 0x000a 16615 #define mmDMA_POSITION_LOWER_BASE_ADDRESS_BASE_IDX 0 16616 #define mmDMA_POSITION_UPPER_BASE_ADDRESS 0x000b 16617 #define mmDMA_POSITION_UPPER_BASE_ADDRESS_BASE_IDX 0 16618 #define mmWALL_CLOCK_COUNTER_ALIAS 0x074c 16619 #define mmWALL_CLOCK_COUNTER_ALIAS_BASE_IDX 1 16620 16621 16622 // addressBlock: dce_dc_hda_azendpoint_azdec 16623 // base address: 0x0 16624 #define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x0006 16625 #define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 0 16626 #define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x0006 16627 #define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 0 16628 16629 16630 // addressBlock: dce_dc_hda_azinputendpoint_azdec 16631 // base address: 0x0 16632 #define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA 0x0006 16633 #define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA_BASE_IDX 0 16634 #define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX 0x0006 16635 #define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX_BASE_IDX 0 16636 16637 16638 16639 // addressBlock: vga_vgaseqind 16640 // base address: 0x0 16641 #define ixSEQ00 0x0000 16642 #define ixSEQ01 0x0001 16643 #define ixSEQ02 0x0002 16644 #define ixSEQ03 0x0003 16645 #define ixSEQ04 0x0004 16646 16647 16648 // addressBlock: vga_vgacrtind 16649 // base address: 0x0 16650 #define ixCRT00 0x0000 16651 #define ixCRT01 0x0001 16652 #define ixCRT02 0x0002 16653 #define ixCRT03 0x0003 16654 #define ixCRT04 0x0004 16655 #define ixCRT05 0x0005 16656 #define ixCRT06 0x0006 16657 #define ixCRT07 0x0007 16658 #define ixCRT08 0x0008 16659 #define ixCRT09 0x0009 16660 #define ixCRT0A 0x000a 16661 #define ixCRT0B 0x000b 16662 #define ixCRT0C 0x000c 16663 #define ixCRT0D 0x000d 16664 #define ixCRT0E 0x000e 16665 #define ixCRT0F 0x000f 16666 #define ixCRT10 0x0010 16667 #define ixCRT11 0x0011 16668 #define ixCRT12 0x0012 16669 #define ixCRT13 0x0013 16670 #define ixCRT14 0x0014 16671 #define ixCRT15 0x0015 16672 #define ixCRT16 0x0016 16673 #define ixCRT17 0x0017 16674 #define ixCRT18 0x0018 16675 #define ixCRT1E 0x001e 16676 #define ixCRT1F 0x001f 16677 #define ixCRT22 0x0022 16678 16679 16680 // addressBlock: vga_vgagrphind 16681 // base address: 0x0 16682 #define ixGRA00 0x0000 16683 #define ixGRA01 0x0001 16684 #define ixGRA02 0x0002 16685 #define ixGRA03 0x0003 16686 #define ixGRA04 0x0004 16687 #define ixGRA05 0x0005 16688 #define ixGRA06 0x0006 16689 #define ixGRA07 0x0007 16690 #define ixGRA08 0x0008 16691 16692 16693 // addressBlock: vga_vgaattrind 16694 // base address: 0x0 16695 #define ixATTR00 0x0000 16696 #define ixATTR01 0x0001 16697 #define ixATTR02 0x0002 16698 #define ixATTR03 0x0003 16699 #define ixATTR04 0x0004 16700 #define ixATTR05 0x0005 16701 #define ixATTR06 0x0006 16702 #define ixATTR07 0x0007 16703 #define ixATTR08 0x0008 16704 #define ixATTR09 0x0009 16705 #define ixATTR0A 0x000a 16706 #define ixATTR0B 0x000b 16707 #define ixATTR0C 0x000c 16708 #define ixATTR0D 0x000d 16709 #define ixATTR0E 0x000e 16710 #define ixATTR0F 0x000f 16711 #define ixATTR10 0x0010 16712 #define ixATTR11 0x0011 16713 #define ixATTR12 0x0012 16714 #define ixATTR13 0x0013 16715 #define ixATTR14 0x0014 16716 16717 16718 // addressBlock: azendpoint_f2codecind 16719 // base address: 0x0 16720 #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x2200 16721 #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x2706 16722 #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x270d 16723 #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2 0x270e 16724 #define ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL 0x2724 16725 #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3 0x273e 16726 #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x2770 16727 #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x2771 16728 #define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x2f09 16729 #define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x2f0a 16730 #define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x2f0b 16731 #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY 0x3702 16732 #define ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x3707 16733 #define ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x3708 16734 #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x3709 16735 #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x371c 16736 #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x371d 16737 #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x371e 16738 #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x371f 16739 #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION 0x3770 16740 #define ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION 0x3771 16741 #define ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO 0x3772 16742 #define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR 0x3776 16743 #define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA 0x3776 16744 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE 0x3777 16745 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE 0x3778 16746 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE 0x3779 16747 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE 0x377a 16748 #define ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC 0x377b 16749 #define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR 0x377c 16750 #define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX 0x3780 16751 #define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA 0x3781 16752 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x3785 16753 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x3786 16754 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x3787 16755 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x3788 16756 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x3789 16757 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x378a 16758 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x378b 16759 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x378c 16760 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x378d 16761 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x378e 16762 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x378f 16763 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x3790 16764 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x3791 16765 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x3792 16766 #define ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO 0x3793 16767 #define ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x3797 16768 #define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x3798 16769 #define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB 0x3799 16770 #define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x379a 16771 #define ixAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE 0x379b 16772 #define ixAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x379c 16773 #define ixAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x379d 16774 #define ixAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x379e 16775 #define ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x3f09 16776 #define ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES 0x3f0c 16777 #define ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH 0x3f0e 16778 16779 16780 // addressBlock: azendpoint_descriptorind 16781 // base address: 0x0 16782 #define ixAUDIO_DESCRIPTOR0 0x0001 16783 #define ixAUDIO_DESCRIPTOR1 0x0002 16784 #define ixAUDIO_DESCRIPTOR2 0x0003 16785 #define ixAUDIO_DESCRIPTOR3 0x0004 16786 #define ixAUDIO_DESCRIPTOR4 0x0005 16787 #define ixAUDIO_DESCRIPTOR5 0x0006 16788 #define ixAUDIO_DESCRIPTOR6 0x0007 16789 #define ixAUDIO_DESCRIPTOR7 0x0008 16790 #define ixAUDIO_DESCRIPTOR8 0x0009 16791 #define ixAUDIO_DESCRIPTOR9 0x000a 16792 #define ixAUDIO_DESCRIPTOR10 0x000b 16793 #define ixAUDIO_DESCRIPTOR11 0x000c 16794 #define ixAUDIO_DESCRIPTOR12 0x000d 16795 #define ixAUDIO_DESCRIPTOR13 0x000e 16796 16797 16798 // addressBlock: azendpoint_sinkinfoind 16799 // base address: 0x0 16800 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID 0x0000 16801 #define ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID 0x0001 16802 #define ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN 0x0002 16803 #define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0 0x0003 16804 #define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1 0x0004 16805 #define ixSINK_DESCRIPTION0 0x0005 16806 #define ixSINK_DESCRIPTION1 0x0006 16807 #define ixSINK_DESCRIPTION2 0x0007 16808 #define ixSINK_DESCRIPTION3 0x0008 16809 #define ixSINK_DESCRIPTION4 0x0009 16810 #define ixSINK_DESCRIPTION5 0x000a 16811 #define ixSINK_DESCRIPTION6 0x000b 16812 #define ixSINK_DESCRIPTION7 0x000c 16813 #define ixSINK_DESCRIPTION8 0x000d 16814 #define ixSINK_DESCRIPTION9 0x000e 16815 #define ixSINK_DESCRIPTION10 0x000f 16816 #define ixSINK_DESCRIPTION11 0x0010 16817 #define ixSINK_DESCRIPTION12 0x0011 16818 #define ixSINK_DESCRIPTION13 0x0012 16819 #define ixSINK_DESCRIPTION14 0x0013 16820 #define ixSINK_DESCRIPTION15 0x0014 16821 #define ixSINK_DESCRIPTION16 0x0015 16822 #define ixSINK_DESCRIPTION17 0x0016 16823 16824 16825 // addressBlock: azf0controller_azinputcrc0resultind 16826 // base address: 0x0 16827 #define ixAZALIA_INPUT_CRC0_CHANNEL0 0x0000 16828 #define ixAZALIA_INPUT_CRC0_CHANNEL1 0x0001 16829 #define ixAZALIA_INPUT_CRC0_CHANNEL2 0x0002 16830 #define ixAZALIA_INPUT_CRC0_CHANNEL3 0x0003 16831 #define ixAZALIA_INPUT_CRC0_CHANNEL4 0x0004 16832 #define ixAZALIA_INPUT_CRC0_CHANNEL5 0x0005 16833 #define ixAZALIA_INPUT_CRC0_CHANNEL6 0x0006 16834 #define ixAZALIA_INPUT_CRC0_CHANNEL7 0x0007 16835 16836 16837 // addressBlock: azf0controller_azinputcrc1resultind 16838 // base address: 0x0 16839 #define ixAZALIA_INPUT_CRC1_CHANNEL0 0x0000 16840 #define ixAZALIA_INPUT_CRC1_CHANNEL1 0x0001 16841 #define ixAZALIA_INPUT_CRC1_CHANNEL2 0x0002 16842 #define ixAZALIA_INPUT_CRC1_CHANNEL3 0x0003 16843 #define ixAZALIA_INPUT_CRC1_CHANNEL4 0x0004 16844 #define ixAZALIA_INPUT_CRC1_CHANNEL5 0x0005 16845 #define ixAZALIA_INPUT_CRC1_CHANNEL6 0x0006 16846 #define ixAZALIA_INPUT_CRC1_CHANNEL7 0x0007 16847 16848 16849 // addressBlock: azf0controller_azcrc0resultind 16850 // base address: 0x0 16851 #define ixAZALIA_CRC0_CHANNEL0 0x0000 16852 #define ixAZALIA_CRC0_CHANNEL1 0x0001 16853 #define ixAZALIA_CRC0_CHANNEL2 0x0002 16854 #define ixAZALIA_CRC0_CHANNEL3 0x0003 16855 #define ixAZALIA_CRC0_CHANNEL4 0x0004 16856 #define ixAZALIA_CRC0_CHANNEL5 0x0005 16857 #define ixAZALIA_CRC0_CHANNEL6 0x0006 16858 #define ixAZALIA_CRC0_CHANNEL7 0x0007 16859 16860 16861 // addressBlock: azf0controller_azcrc1resultind 16862 // base address: 0x0 16863 #define ixAZALIA_CRC1_CHANNEL0 0x0000 16864 #define ixAZALIA_CRC1_CHANNEL1 0x0001 16865 #define ixAZALIA_CRC1_CHANNEL2 0x0002 16866 #define ixAZALIA_CRC1_CHANNEL3 0x0003 16867 #define ixAZALIA_CRC1_CHANNEL4 0x0004 16868 #define ixAZALIA_CRC1_CHANNEL5 0x0005 16869 #define ixAZALIA_CRC1_CHANNEL6 0x0006 16870 #define ixAZALIA_CRC1_CHANNEL7 0x0007 16871 16872 16873 // addressBlock: azinputendpoint_f2codecind 16874 // base address: 0x0 16875 #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x6200 16876 #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x6706 16877 #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x670d 16878 #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x6f09 16879 #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x6f0a 16880 #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x6f0b 16881 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x7707 16882 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x7708 16883 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE 0x7709 16884 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x771c 16885 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x771d 16886 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x771e 16887 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x771f 16888 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x7771 16889 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE 0x7777 16890 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE 0x7778 16891 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE 0x7779 16892 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE 0x777a 16893 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR 0x777c 16894 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x7785 16895 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x7786 16896 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x7787 16897 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x7788 16898 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x7798 16899 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB 0x7799 16900 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x779a 16901 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x779b 16902 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x779c 16903 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L 0x779d 16904 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H 0x779e 16905 #define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x7f09 16906 #define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x7f0c 16907 16908 16909 // addressBlock: azroot_f2codecind 16910 // base address: 0x0 16911 #define ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x0f00 16912 #define ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID 0x0f02 16913 #define ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT 0x0f04 16914 #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE 0x1705 16915 #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x1720 16916 #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2 0x1721 16917 #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3 0x1722 16918 #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4 0x1723 16919 #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x1770 16920 #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET 0x17ff 16921 #define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT 0x1f04 16922 #define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x1f05 16923 #define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x1f0a 16924 #define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x1f0b 16925 #define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x1f0f 16926 16927 16928 // addressBlock: azf0stream0_streamind 16929 // base address: 0x0 16930 #define ixAZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL 0x0000 16931 #define ixAZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 16932 #define ixAZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 16933 #define ixAZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 16934 #define ixAZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 16935 16936 16937 // addressBlock: azf0stream1_streamind 16938 // base address: 0x0 16939 #define ixAZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL 0x0000 16940 #define ixAZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 16941 #define ixAZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 16942 #define ixAZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 16943 #define ixAZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 16944 16945 16946 // addressBlock: azf0stream2_streamind 16947 // base address: 0x0 16948 #define ixAZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL 0x0000 16949 #define ixAZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 16950 #define ixAZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 16951 #define ixAZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 16952 #define ixAZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 16953 16954 16955 // addressBlock: azf0stream3_streamind 16956 // base address: 0x0 16957 #define ixAZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL 0x0000 16958 #define ixAZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 16959 #define ixAZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 16960 #define ixAZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 16961 #define ixAZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 16962 16963 // addressBlock: azf0stream4_streamind 16964 // base address: 0x0 16965 #define ixAZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL 0x0000 16966 #define ixAZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 16967 #define ixAZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 16968 #define ixAZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 16969 #define ixAZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 16970 16971 16972 // addressBlock: azf0stream5_streamind 16973 // base address: 0x0 16974 #define ixAZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL 0x0000 16975 #define ixAZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 16976 #define ixAZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 16977 #define ixAZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 16978 #define ixAZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 16979 16980 16981 // addressBlock: azf0stream6_streamind 16982 // base address: 0x0 16983 #define ixAZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL 0x0000 16984 #define ixAZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 16985 #define ixAZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 16986 #define ixAZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 16987 #define ixAZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 16988 16989 16990 // addressBlock: azf0stream7_streamind 16991 // base address: 0x0 16992 #define ixAZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL 0x0000 16993 #define ixAZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 16994 #define ixAZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 16995 #define ixAZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 16996 #define ixAZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 16997 16998 16999 // addressBlock: azf0stream8_streamind 17000 // base address: 0x0 17001 #define ixAZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL 0x0000 17002 #define ixAZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 17003 #define ixAZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 17004 #define ixAZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 17005 #define ixAZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 17006 17007 17008 // addressBlock: azf0stream9_streamind 17009 // base address: 0x0 17010 #define ixAZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL 0x0000 17011 #define ixAZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 17012 #define ixAZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 17013 #define ixAZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 17014 #define ixAZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 17015 17016 17017 // addressBlock: azf0stream10_streamind 17018 // base address: 0x0 17019 #define ixAZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL 0x0000 17020 #define ixAZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 17021 #define ixAZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 17022 #define ixAZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 17023 #define ixAZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 17024 17025 17026 // addressBlock: azf0stream11_streamind 17027 // base address: 0x0 17028 #define ixAZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL 0x0000 17029 #define ixAZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 17030 #define ixAZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 17031 #define ixAZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 17032 #define ixAZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 17033 17034 17035 // addressBlock: azf0stream12_streamind 17036 // base address: 0x0 17037 #define ixAZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL 0x0000 17038 #define ixAZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 17039 #define ixAZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 17040 #define ixAZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 17041 #define ixAZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 17042 17043 17044 // addressBlock: azf0stream13_streamind 17045 // base address: 0x0 17046 #define ixAZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL 0x0000 17047 #define ixAZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 17048 #define ixAZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 17049 #define ixAZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 17050 #define ixAZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 17051 17052 17053 // addressBlock: azf0stream14_streamind 17054 // base address: 0x0 17055 #define ixAZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL 0x0000 17056 #define ixAZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 17057 #define ixAZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 17058 #define ixAZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 17059 #define ixAZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 17060 17061 17062 // addressBlock: azf0stream15_streamind 17063 // base address: 0x0 17064 #define ixAZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL 0x0000 17065 #define ixAZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 17066 #define ixAZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 17067 #define ixAZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 17068 #define ixAZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 17069 17070 17071 // addressBlock: azf0endpoint0_endpointind 17072 // base address: 0x0 17073 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 17074 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 17075 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 17076 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 17077 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 17078 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 17079 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 17080 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 17081 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 17082 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c 17083 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d 17084 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e 17085 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 17086 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 17087 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 17088 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 17089 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 17090 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 17091 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 17092 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 17093 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a 17094 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b 17095 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c 17096 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d 17097 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e 17098 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f 17099 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 17100 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 17101 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 17102 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 17103 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 17104 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 17105 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 17106 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 17107 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 17108 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a 17109 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b 17110 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c 17111 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d 17112 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e 17113 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f 17114 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 17115 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 17116 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 17117 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 17118 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 17119 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 17120 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 17121 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 17122 #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 17123 #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a 17124 #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b 17125 #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c 17126 #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d 17127 #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e 17128 #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f 17129 #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 17130 #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 17131 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 17132 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 17133 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 17134 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 17135 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 17136 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 17137 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 17138 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 17139 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a 17140 #define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b 17141 #define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c 17142 #define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d 17143 #define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e 17144 17145 17146 // addressBlock: azf0endpoint1_endpointind 17147 // base address: 0x0 17148 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 17149 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 17150 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 17151 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 17152 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 17153 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 17154 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 17155 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 17156 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 17157 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c 17158 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d 17159 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e 17160 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 17161 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 17162 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 17163 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 17164 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 17165 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 17166 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 17167 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 17168 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a 17169 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b 17170 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c 17171 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d 17172 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e 17173 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f 17174 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 17175 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 17176 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 17177 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 17178 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 17179 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 17180 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 17181 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 17182 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 17183 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a 17184 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b 17185 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c 17186 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d 17187 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e 17188 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f 17189 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 17190 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 17191 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 17192 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 17193 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 17194 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 17195 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 17196 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 17197 #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 17198 #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a 17199 #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b 17200 #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c 17201 #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d 17202 #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e 17203 #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f 17204 #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 17205 #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 17206 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 17207 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 17208 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 17209 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 17210 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 17211 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 17212 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 17213 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 17214 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a 17215 #define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b 17216 #define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c 17217 #define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d 17218 #define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e 17219 17220 17221 // addressBlock: azf0endpoint2_endpointind 17222 // base address: 0x0 17223 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 17224 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 17225 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 17226 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 17227 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 17228 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 17229 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 17230 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 17231 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 17232 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c 17233 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d 17234 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e 17235 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 17236 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 17237 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 17238 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 17239 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 17240 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 17241 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 17242 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 17243 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a 17244 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b 17245 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c 17246 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d 17247 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e 17248 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f 17249 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 17250 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 17251 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 17252 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 17253 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 17254 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 17255 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 17256 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 17257 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 17258 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a 17259 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b 17260 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c 17261 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d 17262 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e 17263 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f 17264 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 17265 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 17266 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 17267 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 17268 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 17269 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 17270 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 17271 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 17272 #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 17273 #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a 17274 #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b 17275 #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c 17276 #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d 17277 #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e 17278 #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f 17279 #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 17280 #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 17281 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 17282 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 17283 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 17284 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 17285 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 17286 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 17287 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 17288 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 17289 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a 17290 #define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b 17291 #define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c 17292 #define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d 17293 #define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e 17294 17295 17296 // addressBlock: azf0endpoint3_endpointind 17297 // base address: 0x0 17298 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 17299 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 17300 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 17301 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 17302 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 17303 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 17304 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 17305 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 17306 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 17307 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c 17308 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d 17309 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e 17310 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 17311 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 17312 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 17313 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 17314 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 17315 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 17316 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 17317 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 17318 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a 17319 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b 17320 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c 17321 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d 17322 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e 17323 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f 17324 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 17325 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 17326 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 17327 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 17328 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 17329 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 17330 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 17331 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 17332 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 17333 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a 17334 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b 17335 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c 17336 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d 17337 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e 17338 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f 17339 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 17340 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 17341 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 17342 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 17343 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 17344 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 17345 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 17346 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 17347 #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 17348 #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a 17349 #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b 17350 #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c 17351 #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d 17352 #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e 17353 #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f 17354 #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 17355 #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 17356 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 17357 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 17358 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 17359 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 17360 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 17361 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 17362 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 17363 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 17364 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a 17365 #define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b 17366 #define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c 17367 #define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d 17368 #define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e 17369 17370 17371 // addressBlock: azf0endpoint4_endpointind 17372 // base address: 0x0 17373 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 17374 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 17375 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 17376 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 17377 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 17378 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 17379 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 17380 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 17381 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 17382 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c 17383 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d 17384 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e 17385 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 17386 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 17387 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 17388 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 17389 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 17390 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 17391 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 17392 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 17393 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a 17394 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b 17395 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c 17396 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d 17397 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e 17398 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f 17399 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 17400 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 17401 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 17402 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 17403 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 17404 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 17405 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 17406 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 17407 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 17408 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a 17409 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b 17410 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c 17411 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d 17412 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e 17413 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f 17414 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 17415 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 17416 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 17417 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 17418 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 17419 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 17420 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 17421 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 17422 #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 17423 #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a 17424 #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b 17425 #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c 17426 #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d 17427 #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e 17428 #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f 17429 #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 17430 #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 17431 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 17432 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 17433 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 17434 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 17435 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 17436 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 17437 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 17438 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 17439 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a 17440 #define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b 17441 #define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c 17442 #define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d 17443 #define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e 17444 17445 17446 // addressBlock: azf0endpoint5_endpointind 17447 // base address: 0x0 17448 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 17449 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 17450 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 17451 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 17452 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 17453 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 17454 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 17455 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 17456 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 17457 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c 17458 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d 17459 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e 17460 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 17461 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 17462 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 17463 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 17464 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 17465 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 17466 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 17467 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 17468 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a 17469 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b 17470 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c 17471 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d 17472 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e 17473 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f 17474 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 17475 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 17476 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 17477 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 17478 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 17479 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 17480 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 17481 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 17482 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 17483 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a 17484 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b 17485 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c 17486 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d 17487 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e 17488 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f 17489 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 17490 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 17491 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 17492 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 17493 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 17494 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 17495 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 17496 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 17497 #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 17498 #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a 17499 #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b 17500 #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c 17501 #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d 17502 #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e 17503 #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f 17504 #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 17505 #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 17506 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 17507 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 17508 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 17509 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 17510 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 17511 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 17512 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 17513 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 17514 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a 17515 #define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b 17516 #define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c 17517 #define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d 17518 #define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e 17519 17520 17521 // addressBlock: azf0endpoint6_endpointind 17522 // base address: 0x0 17523 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 17524 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 17525 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 17526 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 17527 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 17528 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 17529 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 17530 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 17531 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 17532 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c 17533 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d 17534 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e 17535 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 17536 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 17537 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 17538 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 17539 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 17540 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 17541 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 17542 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 17543 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a 17544 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b 17545 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c 17546 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d 17547 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e 17548 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f 17549 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 17550 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 17551 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 17552 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 17553 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 17554 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 17555 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 17556 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 17557 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 17558 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a 17559 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b 17560 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c 17561 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d 17562 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e 17563 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f 17564 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 17565 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 17566 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 17567 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 17568 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 17569 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 17570 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 17571 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 17572 #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 17573 #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a 17574 #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b 17575 #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c 17576 #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d 17577 #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e 17578 #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f 17579 #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 17580 #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 17581 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 17582 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 17583 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 17584 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 17585 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 17586 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 17587 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 17588 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 17589 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a 17590 #define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b 17591 #define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c 17592 #define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d 17593 #define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e 17594 17595 17596 // addressBlock: azf0endpoint7_endpointind 17597 // base address: 0x0 17598 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 17599 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 17600 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 17601 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 17602 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 17603 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 17604 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 17605 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 17606 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 17607 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c 17608 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d 17609 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e 17610 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 17611 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 17612 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 17613 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 17614 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 17615 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 17616 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 17617 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 17618 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a 17619 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b 17620 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c 17621 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d 17622 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e 17623 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f 17624 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 17625 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 17626 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 17627 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 17628 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 17629 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 17630 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 17631 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 17632 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 17633 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a 17634 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b 17635 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c 17636 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d 17637 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e 17638 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f 17639 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 17640 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 17641 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 17642 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 17643 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 17644 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 17645 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 17646 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 17647 #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 17648 #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a 17649 #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b 17650 #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c 17651 #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d 17652 #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e 17653 #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f 17654 #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 17655 #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 17656 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 17657 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 17658 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 17659 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 17660 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 17661 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 17662 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 17663 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 17664 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a 17665 #define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b 17666 #define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c 17667 #define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d 17668 #define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e 17669 17670 17671 // addressBlock: azf0inputendpoint0_inputendpointind 17672 // base address: 0x0 17673 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 17674 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 17675 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 17676 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 17677 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 17678 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 17679 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 17680 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 17681 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 17682 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 17683 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 17684 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 17685 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 17686 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 17687 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 17688 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 17689 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 17690 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 17691 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 17692 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 17693 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 17694 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 17695 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 17696 17697 17698 // addressBlock: azf0inputendpoint1_inputendpointind 17699 // base address: 0x0 17700 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 17701 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 17702 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 17703 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 17704 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 17705 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 17706 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 17707 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 17708 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 17709 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 17710 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 17711 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 17712 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 17713 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 17714 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 17715 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 17716 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 17717 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 17718 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 17719 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 17720 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 17721 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 17722 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 17723 17724 17725 // addressBlock: azf0inputendpoint2_inputendpointind 17726 // base address: 0x0 17727 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 17728 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 17729 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 17730 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 17731 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 17732 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 17733 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 17734 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 17735 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 17736 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 17737 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 17738 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 17739 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 17740 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 17741 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 17742 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 17743 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 17744 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 17745 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 17746 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 17747 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 17748 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 17749 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 17750 17751 17752 // addressBlock: azf0inputendpoint3_inputendpointind 17753 // base address: 0x0 17754 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 17755 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 17756 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 17757 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 17758 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 17759 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 17760 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 17761 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 17762 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 17763 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 17764 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 17765 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 17766 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 17767 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 17768 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 17769 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 17770 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 17771 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 17772 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 17773 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 17774 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 17775 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 17776 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 17777 17778 17779 // addressBlock: azf0inputendpoint4_inputendpointind 17780 // base address: 0x0 17781 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 17782 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 17783 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 17784 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 17785 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 17786 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 17787 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 17788 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 17789 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 17790 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 17791 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 17792 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 17793 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 17794 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 17795 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 17796 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 17797 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 17798 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 17799 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 17800 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 17801 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 17802 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 17803 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 17804 17805 17806 // addressBlock: azf0inputendpoint5_inputendpointind 17807 // base address: 0x0 17808 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 17809 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 17810 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 17811 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 17812 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 17813 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 17814 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 17815 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 17816 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 17817 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 17818 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 17819 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 17820 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 17821 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 17822 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 17823 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 17824 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 17825 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 17826 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 17827 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 17828 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 17829 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 17830 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 17831 17832 17833 // addressBlock: azf0inputendpoint6_inputendpointind 17834 // base address: 0x0 17835 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 17836 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 17837 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 17838 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 17839 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 17840 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 17841 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 17842 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 17843 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 17844 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 17845 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 17846 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 17847 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 17848 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 17849 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 17850 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 17851 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 17852 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 17853 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 17854 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 17855 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 17856 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 17857 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 17858 17859 17860 // addressBlock: azf0inputendpoint7_inputendpointind 17861 // base address: 0x0 17862 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 17863 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 17864 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 17865 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 17866 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 17867 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 17868 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 17869 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 17870 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 17871 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 17872 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 17873 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 17874 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 17875 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 17876 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 17877 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 17878 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 17879 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 17880 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 17881 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 17882 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 17883 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 17884 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 17885 17886 #endif 17887