1 /*
2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <linux/tcp.h>
34 #include <linux/if_vlan.h>
35 #include <net/geneve.h>
36 #include <net/dsfield.h>
37 #include "en.h"
38 #include "en/txrx.h"
39 #include "ipoib/ipoib.h"
40 #include "en_accel/en_accel.h"
41 #include "en_accel/ipsec_rxtx.h"
42 #include "en_accel/macsec.h"
43 #include "en/ptp.h"
44 #include <net/ipv6.h>
45
mlx5e_dma_unmap_wqe_err(struct mlx5e_txqsq * sq,u8 num_dma)46 static void mlx5e_dma_unmap_wqe_err(struct mlx5e_txqsq *sq, u8 num_dma)
47 {
48 int i;
49
50 for (i = 0; i < num_dma; i++) {
51 struct mlx5e_sq_dma *last_pushed_dma =
52 mlx5e_dma_get(sq, --sq->dma_fifo_pc);
53
54 mlx5e_tx_dma_unmap(sq->pdev, last_pushed_dma);
55 }
56 }
57
mlx5e_skb_l2_header_offset(struct sk_buff * skb)58 static inline int mlx5e_skb_l2_header_offset(struct sk_buff *skb)
59 {
60 #define MLX5E_MIN_INLINE (ETH_HLEN + VLAN_HLEN)
61
62 return max(skb_network_offset(skb), MLX5E_MIN_INLINE);
63 }
64
mlx5e_skb_l3_header_offset(struct sk_buff * skb)65 static inline int mlx5e_skb_l3_header_offset(struct sk_buff *skb)
66 {
67 if (skb_transport_header_was_set(skb))
68 return skb_transport_offset(skb);
69 else
70 return mlx5e_skb_l2_header_offset(skb);
71 }
72
mlx5e_calc_min_inline(enum mlx5_inline_modes mode,struct sk_buff * skb)73 static inline u16 mlx5e_calc_min_inline(enum mlx5_inline_modes mode,
74 struct sk_buff *skb)
75 {
76 u16 hlen;
77
78 switch (mode) {
79 case MLX5_INLINE_MODE_NONE:
80 return 0;
81 case MLX5_INLINE_MODE_TCP_UDP:
82 hlen = eth_get_headlen(skb->dev, skb->data, skb_headlen(skb));
83 if (hlen == ETH_HLEN && !skb_vlan_tag_present(skb))
84 hlen += VLAN_HLEN;
85 break;
86 case MLX5_INLINE_MODE_IP:
87 hlen = mlx5e_skb_l3_header_offset(skb);
88 break;
89 case MLX5_INLINE_MODE_L2:
90 default:
91 hlen = mlx5e_skb_l2_header_offset(skb);
92 }
93 return min_t(u16, hlen, skb_headlen(skb));
94 }
95
96 #define MLX5_UNSAFE_MEMCPY_DISCLAIMER \
97 "This copy has been bounds-checked earlier in " \
98 "mlx5i_sq_calc_wqe_attr() and intentionally " \
99 "crosses a flex array boundary. Since it is " \
100 "performance sensitive, splitting the copy is " \
101 "undesirable."
102
mlx5e_insert_vlan(void * start,struct sk_buff * skb,u16 ihs)103 static inline void mlx5e_insert_vlan(void *start, struct sk_buff *skb, u16 ihs)
104 {
105 struct vlan_ethhdr *vhdr = (struct vlan_ethhdr *)start;
106 int cpy1_sz = 2 * ETH_ALEN;
107 int cpy2_sz = ihs - cpy1_sz;
108
109 memcpy(&vhdr->addrs, skb->data, cpy1_sz);
110 vhdr->h_vlan_proto = skb->vlan_proto;
111 vhdr->h_vlan_TCI = cpu_to_be16(skb_vlan_tag_get(skb));
112 unsafe_memcpy(&vhdr->h_vlan_encapsulated_proto,
113 skb->data + cpy1_sz,
114 cpy2_sz,
115 MLX5_UNSAFE_MEMCPY_DISCLAIMER);
116 }
117
118 static inline void
mlx5e_txwqe_build_eseg_csum(struct mlx5e_txqsq * sq,struct sk_buff * skb,struct mlx5e_accel_tx_state * accel,struct mlx5_wqe_eth_seg * eseg)119 mlx5e_txwqe_build_eseg_csum(struct mlx5e_txqsq *sq, struct sk_buff *skb,
120 struct mlx5e_accel_tx_state *accel,
121 struct mlx5_wqe_eth_seg *eseg)
122 {
123 if (unlikely(mlx5e_ipsec_txwqe_build_eseg_csum(sq, skb, eseg)))
124 return;
125
126 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
127 eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM;
128 if (skb->encapsulation) {
129 eseg->cs_flags |= MLX5_ETH_WQE_L3_INNER_CSUM |
130 MLX5_ETH_WQE_L4_INNER_CSUM;
131 sq->stats->csum_partial_inner++;
132 } else {
133 eseg->cs_flags |= MLX5_ETH_WQE_L4_CSUM;
134 sq->stats->csum_partial++;
135 }
136 #ifdef CONFIG_MLX5_EN_TLS
137 } else if (unlikely(accel && accel->tls.tls_tisn)) {
138 eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
139 sq->stats->csum_partial++;
140 #endif
141 } else
142 sq->stats->csum_none++;
143 }
144
145 /* Returns the number of header bytes that we plan
146 * to inline later in the transmit descriptor
147 */
148 static inline u16
mlx5e_tx_get_gso_ihs(struct mlx5e_txqsq * sq,struct sk_buff * skb,int * hopbyhop)149 mlx5e_tx_get_gso_ihs(struct mlx5e_txqsq *sq, struct sk_buff *skb, int *hopbyhop)
150 {
151 struct mlx5e_sq_stats *stats = sq->stats;
152 u16 ihs;
153
154 *hopbyhop = 0;
155 if (skb->encapsulation) {
156 if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4)
157 ihs = skb_inner_transport_offset(skb) +
158 sizeof(struct udphdr);
159 else
160 ihs = skb_inner_tcp_all_headers(skb);
161 stats->tso_inner_packets++;
162 stats->tso_inner_bytes += skb->len - ihs;
163 } else {
164 if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) {
165 ihs = skb_transport_offset(skb) + sizeof(struct udphdr);
166 } else {
167 ihs = skb_tcp_all_headers(skb);
168 if (ipv6_has_hopopt_jumbo(skb)) {
169 *hopbyhop = sizeof(struct hop_jumbo_hdr);
170 ihs -= sizeof(struct hop_jumbo_hdr);
171 }
172 }
173 stats->tso_packets++;
174 stats->tso_bytes += skb->len - ihs - *hopbyhop;
175 }
176
177 return ihs;
178 }
179
180 static inline int
mlx5e_txwqe_build_dsegs(struct mlx5e_txqsq * sq,struct sk_buff * skb,unsigned char * skb_data,u16 headlen,struct mlx5_wqe_data_seg * dseg)181 mlx5e_txwqe_build_dsegs(struct mlx5e_txqsq *sq, struct sk_buff *skb,
182 unsigned char *skb_data, u16 headlen,
183 struct mlx5_wqe_data_seg *dseg)
184 {
185 dma_addr_t dma_addr = 0;
186 u8 num_dma = 0;
187 int i;
188
189 if (headlen) {
190 dma_addr = dma_map_single(sq->pdev, skb_data, headlen,
191 DMA_TO_DEVICE);
192 if (unlikely(dma_mapping_error(sq->pdev, dma_addr)))
193 goto dma_unmap_wqe_err;
194
195 dseg->addr = cpu_to_be64(dma_addr);
196 dseg->lkey = sq->mkey_be;
197 dseg->byte_count = cpu_to_be32(headlen);
198
199 mlx5e_dma_push(sq, dma_addr, headlen, MLX5E_DMA_MAP_SINGLE);
200 num_dma++;
201 dseg++;
202 }
203
204 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
205 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
206 int fsz = skb_frag_size(frag);
207
208 dma_addr = skb_frag_dma_map(sq->pdev, frag, 0, fsz,
209 DMA_TO_DEVICE);
210 if (unlikely(dma_mapping_error(sq->pdev, dma_addr)))
211 goto dma_unmap_wqe_err;
212
213 dseg->addr = cpu_to_be64(dma_addr);
214 dseg->lkey = sq->mkey_be;
215 dseg->byte_count = cpu_to_be32(fsz);
216
217 mlx5e_dma_push(sq, dma_addr, fsz, MLX5E_DMA_MAP_PAGE);
218 num_dma++;
219 dseg++;
220 }
221
222 return num_dma;
223
224 dma_unmap_wqe_err:
225 mlx5e_dma_unmap_wqe_err(sq, num_dma);
226 return -ENOMEM;
227 }
228
229 struct mlx5e_tx_attr {
230 u32 num_bytes;
231 u16 headlen;
232 u16 ihs;
233 __be16 mss;
234 u16 insz;
235 u8 opcode;
236 u8 hopbyhop;
237 };
238
239 struct mlx5e_tx_wqe_attr {
240 u16 ds_cnt;
241 u16 ds_cnt_inl;
242 u16 ds_cnt_ids;
243 u8 num_wqebbs;
244 };
245
246 static u8
mlx5e_tx_wqe_inline_mode(struct mlx5e_txqsq * sq,struct sk_buff * skb,struct mlx5e_accel_tx_state * accel)247 mlx5e_tx_wqe_inline_mode(struct mlx5e_txqsq *sq, struct sk_buff *skb,
248 struct mlx5e_accel_tx_state *accel)
249 {
250 u8 mode;
251
252 #ifdef CONFIG_MLX5_EN_TLS
253 if (accel && accel->tls.tls_tisn)
254 return MLX5_INLINE_MODE_TCP_UDP;
255 #endif
256
257 mode = sq->min_inline_mode;
258
259 if (skb_vlan_tag_present(skb) &&
260 test_bit(MLX5E_SQ_STATE_VLAN_NEED_L2_INLINE, &sq->state))
261 mode = max_t(u8, MLX5_INLINE_MODE_L2, mode);
262
263 return mode;
264 }
265
mlx5e_sq_xmit_prepare(struct mlx5e_txqsq * sq,struct sk_buff * skb,struct mlx5e_accel_tx_state * accel,struct mlx5e_tx_attr * attr)266 static void mlx5e_sq_xmit_prepare(struct mlx5e_txqsq *sq, struct sk_buff *skb,
267 struct mlx5e_accel_tx_state *accel,
268 struct mlx5e_tx_attr *attr)
269 {
270 struct mlx5e_sq_stats *stats = sq->stats;
271
272 if (skb_is_gso(skb)) {
273 int hopbyhop;
274 u16 ihs = mlx5e_tx_get_gso_ihs(sq, skb, &hopbyhop);
275
276 *attr = (struct mlx5e_tx_attr) {
277 .opcode = MLX5_OPCODE_LSO,
278 .mss = cpu_to_be16(skb_shinfo(skb)->gso_size),
279 .ihs = ihs,
280 .num_bytes = skb->len + (skb_shinfo(skb)->gso_segs - 1) * ihs,
281 .headlen = skb_headlen(skb) - ihs - hopbyhop,
282 .hopbyhop = hopbyhop,
283 };
284
285 stats->packets += skb_shinfo(skb)->gso_segs;
286 } else {
287 u8 mode = mlx5e_tx_wqe_inline_mode(sq, skb, accel);
288 u16 ihs = mlx5e_calc_min_inline(mode, skb);
289
290 *attr = (struct mlx5e_tx_attr) {
291 .opcode = MLX5_OPCODE_SEND,
292 .mss = cpu_to_be16(0),
293 .ihs = ihs,
294 .num_bytes = max_t(unsigned int, skb->len, ETH_ZLEN),
295 .headlen = skb_headlen(skb) - ihs,
296 };
297
298 stats->packets++;
299 }
300
301 attr->insz = mlx5e_accel_tx_ids_len(sq, accel);
302 stats->bytes += attr->num_bytes;
303 }
304
mlx5e_sq_calc_wqe_attr(struct sk_buff * skb,const struct mlx5e_tx_attr * attr,struct mlx5e_tx_wqe_attr * wqe_attr)305 static void mlx5e_sq_calc_wqe_attr(struct sk_buff *skb, const struct mlx5e_tx_attr *attr,
306 struct mlx5e_tx_wqe_attr *wqe_attr)
307 {
308 u16 ds_cnt = MLX5E_TX_WQE_EMPTY_DS_COUNT;
309 u16 ds_cnt_inl = 0;
310 u16 ds_cnt_ids = 0;
311
312 /* Sync the calculation with MLX5E_MAX_TX_WQEBBS. */
313
314 if (attr->insz)
315 ds_cnt_ids = DIV_ROUND_UP(sizeof(struct mlx5_wqe_inline_seg) + attr->insz,
316 MLX5_SEND_WQE_DS);
317
318 ds_cnt += !!attr->headlen + skb_shinfo(skb)->nr_frags + ds_cnt_ids;
319 if (attr->ihs) {
320 u16 inl = attr->ihs - INL_HDR_START_SZ;
321
322 if (skb_vlan_tag_present(skb))
323 inl += VLAN_HLEN;
324
325 ds_cnt_inl = DIV_ROUND_UP(inl, MLX5_SEND_WQE_DS);
326 if (WARN_ON_ONCE(ds_cnt_inl > MLX5E_MAX_TX_INLINE_DS))
327 netdev_warn(skb->dev, "ds_cnt_inl = %u > max %u\n", ds_cnt_inl,
328 (u16)MLX5E_MAX_TX_INLINE_DS);
329 ds_cnt += ds_cnt_inl;
330 }
331
332 *wqe_attr = (struct mlx5e_tx_wqe_attr) {
333 .ds_cnt = ds_cnt,
334 .ds_cnt_inl = ds_cnt_inl,
335 .ds_cnt_ids = ds_cnt_ids,
336 .num_wqebbs = DIV_ROUND_UP(ds_cnt, MLX5_SEND_WQEBB_NUM_DS),
337 };
338 }
339
mlx5e_tx_skb_update_hwts_flags(struct sk_buff * skb)340 static void mlx5e_tx_skb_update_hwts_flags(struct sk_buff *skb)
341 {
342 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP))
343 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
344 }
345
mlx5e_tx_check_stop(struct mlx5e_txqsq * sq)346 static void mlx5e_tx_check_stop(struct mlx5e_txqsq *sq)
347 {
348 if (unlikely(!mlx5e_wqc_has_room_for(&sq->wq, sq->cc, sq->pc, sq->stop_room))) {
349 netif_tx_stop_queue(sq->txq);
350 sq->stats->stopped++;
351 }
352 }
353
mlx5e_tx_flush(struct mlx5e_txqsq * sq)354 static void mlx5e_tx_flush(struct mlx5e_txqsq *sq)
355 {
356 struct mlx5e_tx_wqe_info *wi;
357 struct mlx5e_tx_wqe *wqe;
358 u16 pi;
359
360 /* Must not be called when a MPWQE session is active but empty. */
361 mlx5e_tx_mpwqe_ensure_complete(sq);
362
363 pi = mlx5_wq_cyc_ctr2ix(&sq->wq, sq->pc);
364 wi = &sq->db.wqe_info[pi];
365
366 *wi = (struct mlx5e_tx_wqe_info) {
367 .num_wqebbs = 1,
368 };
369
370 wqe = mlx5e_post_nop(&sq->wq, sq->sqn, &sq->pc);
371 mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, &wqe->ctrl);
372 }
373
374 static inline void
mlx5e_txwqe_complete(struct mlx5e_txqsq * sq,struct sk_buff * skb,const struct mlx5e_tx_attr * attr,const struct mlx5e_tx_wqe_attr * wqe_attr,u8 num_dma,struct mlx5e_tx_wqe_info * wi,struct mlx5_wqe_ctrl_seg * cseg,struct mlx5_wqe_eth_seg * eseg,bool xmit_more)375 mlx5e_txwqe_complete(struct mlx5e_txqsq *sq, struct sk_buff *skb,
376 const struct mlx5e_tx_attr *attr,
377 const struct mlx5e_tx_wqe_attr *wqe_attr, u8 num_dma,
378 struct mlx5e_tx_wqe_info *wi, struct mlx5_wqe_ctrl_seg *cseg,
379 struct mlx5_wqe_eth_seg *eseg, bool xmit_more)
380 {
381 struct mlx5_wq_cyc *wq = &sq->wq;
382 bool send_doorbell;
383
384 *wi = (struct mlx5e_tx_wqe_info) {
385 .skb = skb,
386 .num_bytes = attr->num_bytes,
387 .num_dma = num_dma,
388 .num_wqebbs = wqe_attr->num_wqebbs,
389 .num_fifo_pkts = 0,
390 };
391
392 cseg->opmod_idx_opcode = cpu_to_be32((sq->pc << 8) | attr->opcode);
393 cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | wqe_attr->ds_cnt);
394
395 mlx5e_tx_skb_update_hwts_flags(skb);
396
397 sq->pc += wi->num_wqebbs;
398
399 mlx5e_tx_check_stop(sq);
400
401 if (unlikely(sq->ptpsq &&
402 (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP))) {
403 u8 metadata_index = be32_to_cpu(eseg->flow_table_metadata);
404
405 mlx5e_ptp_metadata_fifo_pop(&sq->ptpsq->metadata_freelist);
406
407 mlx5e_skb_cb_hwtstamp_init(skb);
408 mlx5e_ptp_metadata_map_put(&sq->ptpsq->metadata_map, skb,
409 metadata_index);
410 /* ensure skb is put on metadata_map before tracking the index */
411 wmb();
412 mlx5e_ptpsq_track_metadata(sq->ptpsq, metadata_index);
413 if (!netif_tx_queue_stopped(sq->txq) &&
414 mlx5e_ptpsq_metadata_freelist_empty(sq->ptpsq)) {
415 netif_tx_stop_queue(sq->txq);
416 sq->stats->stopped++;
417 }
418 skb_get(skb);
419 }
420
421 send_doorbell = __netdev_tx_sent_queue(sq->txq, attr->num_bytes, xmit_more);
422 if (send_doorbell)
423 mlx5e_notify_hw(wq, sq->pc, sq->uar_map, cseg);
424 }
425
426 static void
mlx5e_sq_xmit_wqe(struct mlx5e_txqsq * sq,struct sk_buff * skb,const struct mlx5e_tx_attr * attr,const struct mlx5e_tx_wqe_attr * wqe_attr,struct mlx5e_tx_wqe * wqe,u16 pi,bool xmit_more)427 mlx5e_sq_xmit_wqe(struct mlx5e_txqsq *sq, struct sk_buff *skb,
428 const struct mlx5e_tx_attr *attr, const struct mlx5e_tx_wqe_attr *wqe_attr,
429 struct mlx5e_tx_wqe *wqe, u16 pi, bool xmit_more)
430 {
431 struct mlx5_wqe_ctrl_seg *cseg;
432 struct mlx5_wqe_eth_seg *eseg;
433 struct mlx5_wqe_data_seg *dseg;
434 struct mlx5e_tx_wqe_info *wi;
435 u16 ihs = attr->ihs;
436 struct ipv6hdr *h6;
437 struct mlx5e_sq_stats *stats = sq->stats;
438 int num_dma;
439
440 stats->xmit_more += xmit_more;
441
442 /* fill wqe */
443 wi = &sq->db.wqe_info[pi];
444 cseg = &wqe->ctrl;
445 eseg = &wqe->eth;
446 dseg = wqe->data;
447
448 eseg->mss = attr->mss;
449
450 if (ihs) {
451 u8 *start = eseg->inline_hdr.start;
452
453 if (unlikely(attr->hopbyhop)) {
454 /* remove the HBH header.
455 * Layout: [Ethernet header][IPv6 header][HBH][TCP header]
456 */
457 if (skb_vlan_tag_present(skb)) {
458 mlx5e_insert_vlan(start, skb, ETH_HLEN + sizeof(*h6));
459 ihs += VLAN_HLEN;
460 h6 = (struct ipv6hdr *)(start + sizeof(struct vlan_ethhdr));
461 } else {
462 unsafe_memcpy(start, skb->data,
463 ETH_HLEN + sizeof(*h6),
464 MLX5_UNSAFE_MEMCPY_DISCLAIMER);
465 h6 = (struct ipv6hdr *)(start + ETH_HLEN);
466 }
467 h6->nexthdr = IPPROTO_TCP;
468 /* Copy the TCP header after the IPv6 one */
469 memcpy(h6 + 1,
470 skb->data + ETH_HLEN + sizeof(*h6) +
471 sizeof(struct hop_jumbo_hdr),
472 tcp_hdrlen(skb));
473 /* Leave ipv6 payload_len set to 0, as LSO v2 specs request. */
474 } else if (skb_vlan_tag_present(skb)) {
475 mlx5e_insert_vlan(start, skb, ihs);
476 ihs += VLAN_HLEN;
477 stats->added_vlan_packets++;
478 } else {
479 unsafe_memcpy(eseg->inline_hdr.start, skb->data,
480 attr->ihs,
481 MLX5_UNSAFE_MEMCPY_DISCLAIMER);
482 }
483 eseg->inline_hdr.sz |= cpu_to_be16(ihs);
484 dseg += wqe_attr->ds_cnt_inl;
485 } else if (skb_vlan_tag_present(skb)) {
486 eseg->insert.type = cpu_to_be16(MLX5_ETH_WQE_INSERT_VLAN);
487 if (skb->vlan_proto == cpu_to_be16(ETH_P_8021AD))
488 eseg->insert.type |= cpu_to_be16(MLX5_ETH_WQE_SVLAN);
489 eseg->insert.vlan_tci = cpu_to_be16(skb_vlan_tag_get(skb));
490 stats->added_vlan_packets++;
491 }
492
493 dseg += wqe_attr->ds_cnt_ids;
494 num_dma = mlx5e_txwqe_build_dsegs(sq, skb, skb->data + attr->ihs + attr->hopbyhop,
495 attr->headlen, dseg);
496 if (unlikely(num_dma < 0))
497 goto err_drop;
498
499 mlx5e_txwqe_complete(sq, skb, attr, wqe_attr, num_dma, wi, cseg, eseg, xmit_more);
500
501 return;
502
503 err_drop:
504 stats->dropped++;
505 dev_kfree_skb_any(skb);
506 mlx5e_tx_flush(sq);
507 }
508
mlx5e_tx_skb_supports_mpwqe(struct sk_buff * skb,struct mlx5e_tx_attr * attr)509 static bool mlx5e_tx_skb_supports_mpwqe(struct sk_buff *skb, struct mlx5e_tx_attr *attr)
510 {
511 return !skb_is_nonlinear(skb) && !skb_vlan_tag_present(skb) && !attr->ihs &&
512 !attr->insz && !mlx5e_macsec_skb_is_offload(skb);
513 }
514
mlx5e_tx_mpwqe_same_eseg(struct mlx5e_txqsq * sq,struct mlx5_wqe_eth_seg * eseg)515 static bool mlx5e_tx_mpwqe_same_eseg(struct mlx5e_txqsq *sq, struct mlx5_wqe_eth_seg *eseg)
516 {
517 struct mlx5e_tx_mpwqe *session = &sq->mpwqe;
518
519 /* Assumes the session is already running and has at least one packet. */
520 return !memcmp(&session->wqe->eth, eseg, MLX5E_ACCEL_ESEG_LEN);
521 }
522
mlx5e_tx_mpwqe_session_start(struct mlx5e_txqsq * sq,struct mlx5_wqe_eth_seg * eseg)523 static void mlx5e_tx_mpwqe_session_start(struct mlx5e_txqsq *sq,
524 struct mlx5_wqe_eth_seg *eseg)
525 {
526 struct mlx5e_tx_mpwqe *session = &sq->mpwqe;
527 struct mlx5e_tx_wqe *wqe;
528 u16 pi;
529
530 pi = mlx5e_txqsq_get_next_pi(sq, sq->max_sq_mpw_wqebbs);
531 wqe = MLX5E_TX_FETCH_WQE(sq, pi);
532 net_prefetchw(wqe->data);
533
534 *session = (struct mlx5e_tx_mpwqe) {
535 .wqe = wqe,
536 .bytes_count = 0,
537 .ds_count = MLX5E_TX_WQE_EMPTY_DS_COUNT,
538 .pkt_count = 0,
539 .inline_on = 0,
540 };
541
542 memcpy(&session->wqe->eth, eseg, MLX5E_ACCEL_ESEG_LEN);
543
544 sq->stats->mpwqe_blks++;
545 }
546
mlx5e_tx_mpwqe_session_is_active(struct mlx5e_txqsq * sq)547 static bool mlx5e_tx_mpwqe_session_is_active(struct mlx5e_txqsq *sq)
548 {
549 return sq->mpwqe.wqe;
550 }
551
mlx5e_tx_mpwqe_add_dseg(struct mlx5e_txqsq * sq,struct mlx5e_xmit_data * txd)552 static void mlx5e_tx_mpwqe_add_dseg(struct mlx5e_txqsq *sq, struct mlx5e_xmit_data *txd)
553 {
554 struct mlx5e_tx_mpwqe *session = &sq->mpwqe;
555 struct mlx5_wqe_data_seg *dseg;
556
557 dseg = (struct mlx5_wqe_data_seg *)session->wqe + session->ds_count;
558
559 session->pkt_count++;
560 session->bytes_count += txd->len;
561
562 dseg->addr = cpu_to_be64(txd->dma_addr);
563 dseg->byte_count = cpu_to_be32(txd->len);
564 dseg->lkey = sq->mkey_be;
565 session->ds_count++;
566
567 sq->stats->mpwqe_pkts++;
568 }
569
mlx5e_tx_mpwqe_session_complete(struct mlx5e_txqsq * sq)570 static struct mlx5_wqe_ctrl_seg *mlx5e_tx_mpwqe_session_complete(struct mlx5e_txqsq *sq)
571 {
572 struct mlx5e_tx_mpwqe *session = &sq->mpwqe;
573 u8 ds_count = session->ds_count;
574 struct mlx5_wqe_ctrl_seg *cseg;
575 struct mlx5e_tx_wqe_info *wi;
576 u16 pi;
577
578 cseg = &session->wqe->ctrl;
579 cseg->opmod_idx_opcode = cpu_to_be32((sq->pc << 8) | MLX5_OPCODE_ENHANCED_MPSW);
580 cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_count);
581
582 pi = mlx5_wq_cyc_ctr2ix(&sq->wq, sq->pc);
583 wi = &sq->db.wqe_info[pi];
584 *wi = (struct mlx5e_tx_wqe_info) {
585 .skb = NULL,
586 .num_bytes = session->bytes_count,
587 .num_wqebbs = DIV_ROUND_UP(ds_count, MLX5_SEND_WQEBB_NUM_DS),
588 .num_dma = session->pkt_count,
589 .num_fifo_pkts = session->pkt_count,
590 };
591
592 sq->pc += wi->num_wqebbs;
593
594 session->wqe = NULL;
595
596 mlx5e_tx_check_stop(sq);
597
598 return cseg;
599 }
600
601 static void
mlx5e_sq_xmit_mpwqe(struct mlx5e_txqsq * sq,struct sk_buff * skb,struct mlx5_wqe_eth_seg * eseg,bool xmit_more)602 mlx5e_sq_xmit_mpwqe(struct mlx5e_txqsq *sq, struct sk_buff *skb,
603 struct mlx5_wqe_eth_seg *eseg, bool xmit_more)
604 {
605 struct mlx5_wqe_ctrl_seg *cseg;
606 struct mlx5e_xmit_data txd;
607
608 txd.data = skb->data;
609 txd.len = skb->len;
610
611 txd.dma_addr = dma_map_single(sq->pdev, txd.data, txd.len, DMA_TO_DEVICE);
612 if (unlikely(dma_mapping_error(sq->pdev, txd.dma_addr)))
613 goto err_unmap;
614
615 if (!mlx5e_tx_mpwqe_session_is_active(sq)) {
616 mlx5e_tx_mpwqe_session_start(sq, eseg);
617 } else if (!mlx5e_tx_mpwqe_same_eseg(sq, eseg)) {
618 mlx5e_tx_mpwqe_session_complete(sq);
619 mlx5e_tx_mpwqe_session_start(sq, eseg);
620 }
621
622 sq->stats->xmit_more += xmit_more;
623
624 mlx5e_dma_push(sq, txd.dma_addr, txd.len, MLX5E_DMA_MAP_SINGLE);
625 mlx5e_skb_fifo_push(&sq->db.skb_fifo, skb);
626 mlx5e_tx_mpwqe_add_dseg(sq, &txd);
627 mlx5e_tx_skb_update_hwts_flags(skb);
628
629 if (unlikely(mlx5e_tx_mpwqe_is_full(&sq->mpwqe, sq->max_sq_mpw_wqebbs))) {
630 /* Might stop the queue and affect the retval of __netdev_tx_sent_queue. */
631 cseg = mlx5e_tx_mpwqe_session_complete(sq);
632
633 if (__netdev_tx_sent_queue(sq->txq, txd.len, xmit_more))
634 mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, cseg);
635 } else if (__netdev_tx_sent_queue(sq->txq, txd.len, xmit_more)) {
636 /* Might stop the queue, but we were asked to ring the doorbell anyway. */
637 cseg = mlx5e_tx_mpwqe_session_complete(sq);
638
639 mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, cseg);
640 }
641
642 return;
643
644 err_unmap:
645 sq->stats->dropped++;
646 dev_kfree_skb_any(skb);
647 mlx5e_tx_flush(sq);
648 }
649
mlx5e_tx_mpwqe_ensure_complete(struct mlx5e_txqsq * sq)650 void mlx5e_tx_mpwqe_ensure_complete(struct mlx5e_txqsq *sq)
651 {
652 /* Unlikely in non-MPWQE workloads; not important in MPWQE workloads. */
653 if (unlikely(mlx5e_tx_mpwqe_session_is_active(sq)))
654 mlx5e_tx_mpwqe_session_complete(sq);
655 }
656
mlx5e_cqe_ts_id_eseg(struct mlx5e_ptpsq * ptpsq,struct sk_buff * skb,struct mlx5_wqe_eth_seg * eseg)657 static void mlx5e_cqe_ts_id_eseg(struct mlx5e_ptpsq *ptpsq, struct sk_buff *skb,
658 struct mlx5_wqe_eth_seg *eseg)
659 {
660 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP))
661 eseg->flow_table_metadata =
662 cpu_to_be32(mlx5e_ptp_metadata_fifo_peek(&ptpsq->metadata_freelist));
663 }
664
mlx5e_txwqe_build_eseg(struct mlx5e_priv * priv,struct mlx5e_txqsq * sq,struct sk_buff * skb,struct mlx5e_accel_tx_state * accel,struct mlx5_wqe_eth_seg * eseg,u16 ihs)665 static void mlx5e_txwqe_build_eseg(struct mlx5e_priv *priv, struct mlx5e_txqsq *sq,
666 struct sk_buff *skb, struct mlx5e_accel_tx_state *accel,
667 struct mlx5_wqe_eth_seg *eseg, u16 ihs)
668 {
669 mlx5e_accel_tx_eseg(priv, skb, eseg, ihs);
670 mlx5e_txwqe_build_eseg_csum(sq, skb, accel, eseg);
671 if (unlikely(sq->ptpsq))
672 mlx5e_cqe_ts_id_eseg(sq->ptpsq, skb, eseg);
673 }
674
mlx5e_xmit(struct sk_buff * skb,struct net_device * dev)675 netdev_tx_t mlx5e_xmit(struct sk_buff *skb, struct net_device *dev)
676 {
677 struct mlx5e_priv *priv = netdev_priv(dev);
678 struct mlx5e_accel_tx_state accel = {};
679 struct mlx5e_tx_wqe_attr wqe_attr;
680 struct mlx5e_tx_attr attr;
681 struct mlx5e_tx_wqe *wqe;
682 struct mlx5e_txqsq *sq;
683 u16 pi;
684
685 /* All changes to txq2sq are performed in sync with mlx5e_xmit, when the
686 * queue being changed is disabled, and smp_wmb guarantees that the
687 * changes are visible before mlx5e_xmit tries to read from txq2sq. It
688 * guarantees that the value of txq2sq[qid] doesn't change while
689 * mlx5e_xmit is running on queue number qid. smb_wmb is paired with
690 * HARD_TX_LOCK around ndo_start_xmit, which serves as an ACQUIRE.
691 */
692 sq = priv->txq2sq[skb_get_queue_mapping(skb)];
693 if (unlikely(!sq)) {
694 /* Two cases when sq can be NULL:
695 * 1. The HTB node is registered, and mlx5e_select_queue
696 * selected its queue ID, but the SQ itself is not yet created.
697 * 2. HTB SQ creation failed. Similar to the previous case, but
698 * the SQ won't be created.
699 */
700 dev_kfree_skb_any(skb);
701 return NETDEV_TX_OK;
702 }
703
704 /* May send SKBs and WQEs. */
705 if (unlikely(!mlx5e_accel_tx_begin(dev, sq, skb, &accel)))
706 return NETDEV_TX_OK;
707
708 mlx5e_sq_xmit_prepare(sq, skb, &accel, &attr);
709
710 if (test_bit(MLX5E_SQ_STATE_MPWQE, &sq->state)) {
711 if (mlx5e_tx_skb_supports_mpwqe(skb, &attr)) {
712 struct mlx5_wqe_eth_seg eseg = {};
713
714 mlx5e_txwqe_build_eseg(priv, sq, skb, &accel, &eseg, attr.ihs);
715 mlx5e_sq_xmit_mpwqe(sq, skb, &eseg, netdev_xmit_more());
716 return NETDEV_TX_OK;
717 }
718
719 mlx5e_tx_mpwqe_ensure_complete(sq);
720 }
721
722 mlx5e_sq_calc_wqe_attr(skb, &attr, &wqe_attr);
723 pi = mlx5e_txqsq_get_next_pi(sq, wqe_attr.num_wqebbs);
724 wqe = MLX5E_TX_FETCH_WQE(sq, pi);
725
726 /* May update the WQE, but may not post other WQEs. */
727 mlx5e_accel_tx_finish(sq, wqe, &accel,
728 (struct mlx5_wqe_inline_seg *)(wqe->data + wqe_attr.ds_cnt_inl));
729 mlx5e_txwqe_build_eseg(priv, sq, skb, &accel, &wqe->eth, attr.ihs);
730 mlx5e_sq_xmit_wqe(sq, skb, &attr, &wqe_attr, wqe, pi, netdev_xmit_more());
731
732 return NETDEV_TX_OK;
733 }
734
mlx5e_tx_wi_dma_unmap(struct mlx5e_txqsq * sq,struct mlx5e_tx_wqe_info * wi,u32 * dma_fifo_cc)735 static void mlx5e_tx_wi_dma_unmap(struct mlx5e_txqsq *sq, struct mlx5e_tx_wqe_info *wi,
736 u32 *dma_fifo_cc)
737 {
738 int i;
739
740 for (i = 0; i < wi->num_dma; i++) {
741 struct mlx5e_sq_dma *dma = mlx5e_dma_get(sq, (*dma_fifo_cc)++);
742
743 mlx5e_tx_dma_unmap(sq->pdev, dma);
744 }
745 }
746
mlx5e_consume_skb(struct mlx5e_txqsq * sq,struct sk_buff * skb,struct mlx5_cqe64 * cqe,int napi_budget)747 static void mlx5e_consume_skb(struct mlx5e_txqsq *sq, struct sk_buff *skb,
748 struct mlx5_cqe64 *cqe, int napi_budget)
749 {
750 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
751 struct skb_shared_hwtstamps hwts = {};
752 u64 ts = get_cqe_ts(cqe);
753
754 hwts.hwtstamp = mlx5e_cqe_ts_to_ns(sq->ptp_cyc2time, sq->clock, ts);
755 if (sq->ptpsq)
756 mlx5e_skb_cb_hwtstamp_handler(skb, MLX5E_SKB_CB_CQE_HWTSTAMP,
757 hwts.hwtstamp, sq->ptpsq->cq_stats);
758 else
759 skb_tstamp_tx(skb, &hwts);
760 }
761
762 napi_consume_skb(skb, napi_budget);
763 }
764
mlx5e_tx_wi_consume_fifo_skbs(struct mlx5e_txqsq * sq,struct mlx5e_tx_wqe_info * wi,struct mlx5_cqe64 * cqe,int napi_budget)765 static void mlx5e_tx_wi_consume_fifo_skbs(struct mlx5e_txqsq *sq, struct mlx5e_tx_wqe_info *wi,
766 struct mlx5_cqe64 *cqe, int napi_budget)
767 {
768 int i;
769
770 for (i = 0; i < wi->num_fifo_pkts; i++) {
771 struct sk_buff *skb = mlx5e_skb_fifo_pop(&sq->db.skb_fifo);
772
773 mlx5e_consume_skb(sq, skb, cqe, napi_budget);
774 }
775 }
776
mlx5e_txqsq_wake(struct mlx5e_txqsq * sq)777 void mlx5e_txqsq_wake(struct mlx5e_txqsq *sq)
778 {
779 if (netif_tx_queue_stopped(sq->txq) &&
780 mlx5e_wqc_has_room_for(&sq->wq, sq->cc, sq->pc, sq->stop_room) &&
781 !mlx5e_ptpsq_metadata_freelist_empty(sq->ptpsq) &&
782 !test_bit(MLX5E_SQ_STATE_RECOVERING, &sq->state)) {
783 netif_tx_wake_queue(sq->txq);
784 sq->stats->wake++;
785 }
786 }
787
mlx5e_poll_tx_cq(struct mlx5e_cq * cq,int napi_budget)788 bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq, int napi_budget)
789 {
790 struct mlx5e_sq_stats *stats;
791 struct mlx5e_txqsq *sq;
792 struct mlx5_cqe64 *cqe;
793 u32 dma_fifo_cc;
794 u32 nbytes;
795 u16 npkts;
796 u16 sqcc;
797 int i;
798
799 sq = container_of(cq, struct mlx5e_txqsq, cq);
800
801 if (unlikely(!test_bit(MLX5E_SQ_STATE_ENABLED, &sq->state)))
802 return false;
803
804 cqe = mlx5_cqwq_get_cqe(&cq->wq);
805 if (!cqe)
806 return false;
807
808 stats = sq->stats;
809
810 npkts = 0;
811 nbytes = 0;
812
813 /* sq->cc must be updated only after mlx5_cqwq_update_db_record(),
814 * otherwise a cq overrun may occur
815 */
816 sqcc = sq->cc;
817
818 /* avoid dirtying sq cache line every cqe */
819 dma_fifo_cc = sq->dma_fifo_cc;
820
821 i = 0;
822 do {
823 struct mlx5e_tx_wqe_info *wi;
824 u16 wqe_counter;
825 bool last_wqe;
826 u16 ci;
827
828 mlx5_cqwq_pop(&cq->wq);
829
830 wqe_counter = be16_to_cpu(cqe->wqe_counter);
831
832 do {
833 last_wqe = (sqcc == wqe_counter);
834
835 ci = mlx5_wq_cyc_ctr2ix(&sq->wq, sqcc);
836 wi = &sq->db.wqe_info[ci];
837
838 sqcc += wi->num_wqebbs;
839
840 if (likely(wi->skb)) {
841 mlx5e_tx_wi_dma_unmap(sq, wi, &dma_fifo_cc);
842 mlx5e_consume_skb(sq, wi->skb, cqe, napi_budget);
843
844 npkts++;
845 nbytes += wi->num_bytes;
846 continue;
847 }
848
849 if (unlikely(mlx5e_ktls_tx_try_handle_resync_dump_comp(sq, wi,
850 &dma_fifo_cc)))
851 continue;
852
853 if (wi->num_fifo_pkts) {
854 mlx5e_tx_wi_dma_unmap(sq, wi, &dma_fifo_cc);
855 mlx5e_tx_wi_consume_fifo_skbs(sq, wi, cqe, napi_budget);
856
857 npkts += wi->num_fifo_pkts;
858 nbytes += wi->num_bytes;
859 }
860 } while (!last_wqe);
861
862 if (unlikely(get_cqe_opcode(cqe) == MLX5_CQE_REQ_ERR)) {
863 if (!test_and_set_bit(MLX5E_SQ_STATE_RECOVERING,
864 &sq->state)) {
865 mlx5e_dump_error_cqe(&sq->cq, sq->sqn,
866 (struct mlx5_err_cqe *)cqe);
867 mlx5_wq_cyc_wqe_dump(&sq->wq, ci, wi->num_wqebbs);
868 queue_work(cq->priv->wq, &sq->recover_work);
869 }
870 stats->cqe_err++;
871 }
872
873 } while ((++i < MLX5E_TX_CQ_POLL_BUDGET) && (cqe = mlx5_cqwq_get_cqe(&cq->wq)));
874
875 stats->cqes += i;
876
877 mlx5_cqwq_update_db_record(&cq->wq);
878
879 /* ensure cq space is freed before enabling more cqes */
880 wmb();
881
882 sq->dma_fifo_cc = dma_fifo_cc;
883 sq->cc = sqcc;
884
885 netdev_tx_completed_queue(sq->txq, npkts, nbytes);
886
887 mlx5e_txqsq_wake(sq);
888
889 return (i == MLX5E_TX_CQ_POLL_BUDGET);
890 }
891
mlx5e_tx_wi_kfree_fifo_skbs(struct mlx5e_txqsq * sq,struct mlx5e_tx_wqe_info * wi)892 static void mlx5e_tx_wi_kfree_fifo_skbs(struct mlx5e_txqsq *sq, struct mlx5e_tx_wqe_info *wi)
893 {
894 int i;
895
896 for (i = 0; i < wi->num_fifo_pkts; i++)
897 dev_kfree_skb_any(mlx5e_skb_fifo_pop(&sq->db.skb_fifo));
898 }
899
mlx5e_free_txqsq_descs(struct mlx5e_txqsq * sq)900 void mlx5e_free_txqsq_descs(struct mlx5e_txqsq *sq)
901 {
902 struct mlx5e_tx_wqe_info *wi;
903 u32 dma_fifo_cc, nbytes = 0;
904 u16 ci, sqcc, npkts = 0;
905
906 sqcc = sq->cc;
907 dma_fifo_cc = sq->dma_fifo_cc;
908
909 while (sqcc != sq->pc) {
910 ci = mlx5_wq_cyc_ctr2ix(&sq->wq, sqcc);
911 wi = &sq->db.wqe_info[ci];
912
913 sqcc += wi->num_wqebbs;
914
915 if (likely(wi->skb)) {
916 mlx5e_tx_wi_dma_unmap(sq, wi, &dma_fifo_cc);
917 dev_kfree_skb_any(wi->skb);
918
919 npkts++;
920 nbytes += wi->num_bytes;
921 continue;
922 }
923
924 if (unlikely(mlx5e_ktls_tx_try_handle_resync_dump_comp(sq, wi, &dma_fifo_cc)))
925 continue;
926
927 if (wi->num_fifo_pkts) {
928 mlx5e_tx_wi_dma_unmap(sq, wi, &dma_fifo_cc);
929 mlx5e_tx_wi_kfree_fifo_skbs(sq, wi);
930
931 npkts += wi->num_fifo_pkts;
932 nbytes += wi->num_bytes;
933 }
934 }
935
936 sq->dma_fifo_cc = dma_fifo_cc;
937 sq->cc = sqcc;
938
939 netdev_tx_completed_queue(sq->txq, npkts, nbytes);
940 }
941
942 #ifdef CONFIG_MLX5_CORE_IPOIB
943 static inline void
mlx5i_txwqe_build_datagram(struct mlx5_av * av,u32 dqpn,u32 dqkey,struct mlx5_wqe_datagram_seg * dseg)944 mlx5i_txwqe_build_datagram(struct mlx5_av *av, u32 dqpn, u32 dqkey,
945 struct mlx5_wqe_datagram_seg *dseg)
946 {
947 memcpy(&dseg->av, av, sizeof(struct mlx5_av));
948 dseg->av.dqp_dct = cpu_to_be32(dqpn | MLX5_EXTENDED_UD_AV);
949 dseg->av.key.qkey.qkey = cpu_to_be32(dqkey);
950 }
951
mlx5i_sq_calc_wqe_attr(struct sk_buff * skb,const struct mlx5e_tx_attr * attr,struct mlx5e_tx_wqe_attr * wqe_attr)952 static void mlx5i_sq_calc_wqe_attr(struct sk_buff *skb,
953 const struct mlx5e_tx_attr *attr,
954 struct mlx5e_tx_wqe_attr *wqe_attr)
955 {
956 u16 ds_cnt = sizeof(struct mlx5i_tx_wqe) / MLX5_SEND_WQE_DS;
957 u16 ds_cnt_inl = 0;
958
959 ds_cnt += !!attr->headlen + skb_shinfo(skb)->nr_frags;
960
961 if (attr->ihs) {
962 u16 inl = attr->ihs - INL_HDR_START_SZ;
963
964 ds_cnt_inl = DIV_ROUND_UP(inl, MLX5_SEND_WQE_DS);
965 ds_cnt += ds_cnt_inl;
966 }
967
968 *wqe_attr = (struct mlx5e_tx_wqe_attr) {
969 .ds_cnt = ds_cnt,
970 .ds_cnt_inl = ds_cnt_inl,
971 .num_wqebbs = DIV_ROUND_UP(ds_cnt, MLX5_SEND_WQEBB_NUM_DS),
972 };
973 }
974
mlx5i_sq_xmit(struct mlx5e_txqsq * sq,struct sk_buff * skb,struct mlx5_av * av,u32 dqpn,u32 dqkey,bool xmit_more)975 void mlx5i_sq_xmit(struct mlx5e_txqsq *sq, struct sk_buff *skb,
976 struct mlx5_av *av, u32 dqpn, u32 dqkey, bool xmit_more)
977 {
978 struct mlx5e_tx_wqe_attr wqe_attr;
979 struct mlx5e_tx_attr attr;
980 struct mlx5i_tx_wqe *wqe;
981
982 struct mlx5_wqe_datagram_seg *datagram;
983 struct mlx5_wqe_ctrl_seg *cseg;
984 struct mlx5_wqe_eth_seg *eseg;
985 struct mlx5_wqe_data_seg *dseg;
986 struct mlx5e_tx_wqe_info *wi;
987
988 struct mlx5e_sq_stats *stats = sq->stats;
989 int num_dma;
990 u16 pi;
991
992 mlx5e_sq_xmit_prepare(sq, skb, NULL, &attr);
993 mlx5i_sq_calc_wqe_attr(skb, &attr, &wqe_attr);
994
995 pi = mlx5e_txqsq_get_next_pi(sq, wqe_attr.num_wqebbs);
996 wqe = MLX5I_SQ_FETCH_WQE(sq, pi);
997
998 stats->xmit_more += xmit_more;
999
1000 /* fill wqe */
1001 wi = &sq->db.wqe_info[pi];
1002 cseg = &wqe->ctrl;
1003 datagram = &wqe->datagram;
1004 eseg = &wqe->eth;
1005 dseg = wqe->data;
1006
1007 mlx5i_txwqe_build_datagram(av, dqpn, dqkey, datagram);
1008
1009 mlx5e_txwqe_build_eseg_csum(sq, skb, NULL, eseg);
1010
1011 eseg->mss = attr.mss;
1012
1013 if (attr.ihs) {
1014 if (unlikely(attr.hopbyhop)) {
1015 struct ipv6hdr *h6;
1016
1017 /* remove the HBH header.
1018 * Layout: [Ethernet header][IPv6 header][HBH][TCP header]
1019 */
1020 unsafe_memcpy(eseg->inline_hdr.start, skb->data,
1021 ETH_HLEN + sizeof(*h6),
1022 MLX5_UNSAFE_MEMCPY_DISCLAIMER);
1023 h6 = (struct ipv6hdr *)((char *)eseg->inline_hdr.start + ETH_HLEN);
1024 h6->nexthdr = IPPROTO_TCP;
1025 /* Copy the TCP header after the IPv6 one */
1026 unsafe_memcpy(h6 + 1,
1027 skb->data + ETH_HLEN + sizeof(*h6) +
1028 sizeof(struct hop_jumbo_hdr),
1029 tcp_hdrlen(skb),
1030 MLX5_UNSAFE_MEMCPY_DISCLAIMER);
1031 /* Leave ipv6 payload_len set to 0, as LSO v2 specs request. */
1032 } else {
1033 unsafe_memcpy(eseg->inline_hdr.start, skb->data,
1034 attr.ihs,
1035 MLX5_UNSAFE_MEMCPY_DISCLAIMER);
1036 }
1037 eseg->inline_hdr.sz = cpu_to_be16(attr.ihs);
1038 dseg += wqe_attr.ds_cnt_inl;
1039 }
1040
1041 num_dma = mlx5e_txwqe_build_dsegs(sq, skb, skb->data + attr.ihs + attr.hopbyhop,
1042 attr.headlen, dseg);
1043 if (unlikely(num_dma < 0))
1044 goto err_drop;
1045
1046 mlx5e_txwqe_complete(sq, skb, &attr, &wqe_attr, num_dma, wi, cseg, eseg, xmit_more);
1047
1048 return;
1049
1050 err_drop:
1051 stats->dropped++;
1052 dev_kfree_skb_any(skb);
1053 mlx5e_tx_flush(sq);
1054 }
1055 #endif
1056