1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
2 /*
3 * Copyright (c) 2013-2020, Mellanox Technologies inc. All rights reserved.
4 * Copyright (c) 2020, Intel Corporation. All rights reserved.
5 */
6
7 #include <linux/debugfs.h>
8 #include <linux/highmem.h>
9 #include <linux/module.h>
10 #include <linux/init.h>
11 #include <linux/errno.h>
12 #include <linux/pci.h>
13 #include <linux/dma-mapping.h>
14 #include <linux/slab.h>
15 #include <linux/bitmap.h>
16 #include <linux/sched.h>
17 #include <linux/sched/mm.h>
18 #include <linux/sched/task.h>
19 #include <linux/delay.h>
20 #include <rdma/ib_user_verbs.h>
21 #include <rdma/ib_addr.h>
22 #include <rdma/ib_cache.h>
23 #include <linux/mlx5/port.h>
24 #include <linux/mlx5/vport.h>
25 #include <linux/mlx5/fs.h>
26 #include <linux/mlx5/eswitch.h>
27 #include <linux/mlx5/driver.h>
28 #include <linux/list.h>
29 #include <rdma/ib_smi.h>
30 #include <rdma/ib_umem_odp.h>
31 #include <rdma/lag.h>
32 #include <linux/in.h>
33 #include <linux/etherdevice.h>
34 #include "mlx5_ib.h"
35 #include "ib_rep.h"
36 #include "cmd.h"
37 #include "devx.h"
38 #include "dm.h"
39 #include "fs.h"
40 #include "srq.h"
41 #include "qp.h"
42 #include "wr.h"
43 #include "restrack.h"
44 #include "counters.h"
45 #include "umr.h"
46 #include <rdma/uverbs_std_types.h>
47 #include <rdma/uverbs_ioctl.h>
48 #include <rdma/mlx5_user_ioctl_verbs.h>
49 #include <rdma/mlx5_user_ioctl_cmds.h>
50 #include "macsec.h"
51
52 #define UVERBS_MODULE_NAME mlx5_ib
53 #include <rdma/uverbs_named_ioctl.h>
54
55 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
56 MODULE_DESCRIPTION("Mellanox 5th generation network adapters (ConnectX series) IB driver");
57 MODULE_LICENSE("Dual BSD/GPL");
58
59 struct mlx5_ib_event_work {
60 struct work_struct work;
61 union {
62 struct mlx5_ib_dev *dev;
63 struct mlx5_ib_multiport_info *mpi;
64 };
65 bool is_slave;
66 unsigned int event;
67 void *param;
68 };
69
70 enum {
71 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3,
72 };
73
74 static struct workqueue_struct *mlx5_ib_event_wq;
75 static LIST_HEAD(mlx5_ib_unaffiliated_port_list);
76 static LIST_HEAD(mlx5_ib_dev_list);
77 /*
78 * This mutex should be held when accessing either of the above lists
79 */
80 static DEFINE_MUTEX(mlx5_ib_multiport_mutex);
81
mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info * mpi)82 struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi)
83 {
84 struct mlx5_ib_dev *dev;
85
86 mutex_lock(&mlx5_ib_multiport_mutex);
87 dev = mpi->ibdev;
88 mutex_unlock(&mlx5_ib_multiport_mutex);
89 return dev;
90 }
91
92 static enum rdma_link_layer
mlx5_port_type_cap_to_rdma_ll(int port_type_cap)93 mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
94 {
95 switch (port_type_cap) {
96 case MLX5_CAP_PORT_TYPE_IB:
97 return IB_LINK_LAYER_INFINIBAND;
98 case MLX5_CAP_PORT_TYPE_ETH:
99 return IB_LINK_LAYER_ETHERNET;
100 default:
101 return IB_LINK_LAYER_UNSPECIFIED;
102 }
103 }
104
105 static enum rdma_link_layer
mlx5_ib_port_link_layer(struct ib_device * device,u32 port_num)106 mlx5_ib_port_link_layer(struct ib_device *device, u32 port_num)
107 {
108 struct mlx5_ib_dev *dev = to_mdev(device);
109 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);
110
111 return mlx5_port_type_cap_to_rdma_ll(port_type_cap);
112 }
113
get_port_state(struct ib_device * ibdev,u32 port_num,enum ib_port_state * state)114 static int get_port_state(struct ib_device *ibdev,
115 u32 port_num,
116 enum ib_port_state *state)
117 {
118 struct ib_port_attr attr;
119 int ret;
120
121 memset(&attr, 0, sizeof(attr));
122 ret = ibdev->ops.query_port(ibdev, port_num, &attr);
123 if (!ret)
124 *state = attr.state;
125 return ret;
126 }
127
mlx5_get_rep_roce(struct mlx5_ib_dev * dev,struct net_device * ndev,struct net_device * upper,u32 * port_num)128 static struct mlx5_roce *mlx5_get_rep_roce(struct mlx5_ib_dev *dev,
129 struct net_device *ndev,
130 struct net_device *upper,
131 u32 *port_num)
132 {
133 struct net_device *rep_ndev;
134 struct mlx5_ib_port *port;
135 int i;
136
137 for (i = 0; i < dev->num_ports; i++) {
138 port = &dev->port[i];
139 if (!port->rep)
140 continue;
141
142 if (upper == ndev && port->rep->vport == MLX5_VPORT_UPLINK) {
143 *port_num = i + 1;
144 return &port->roce;
145 }
146
147 if (upper && port->rep->vport == MLX5_VPORT_UPLINK)
148 continue;
149
150 read_lock(&port->roce.netdev_lock);
151 rep_ndev = mlx5_ib_get_rep_netdev(port->rep->esw,
152 port->rep->vport);
153 if (rep_ndev == ndev) {
154 read_unlock(&port->roce.netdev_lock);
155 *port_num = i + 1;
156 return &port->roce;
157 }
158 read_unlock(&port->roce.netdev_lock);
159 }
160
161 return NULL;
162 }
163
mlx5_netdev_event(struct notifier_block * this,unsigned long event,void * ptr)164 static int mlx5_netdev_event(struct notifier_block *this,
165 unsigned long event, void *ptr)
166 {
167 struct mlx5_roce *roce = container_of(this, struct mlx5_roce, nb);
168 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
169 u32 port_num = roce->native_port_num;
170 struct mlx5_core_dev *mdev;
171 struct mlx5_ib_dev *ibdev;
172
173 ibdev = roce->dev;
174 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL);
175 if (!mdev)
176 return NOTIFY_DONE;
177
178 switch (event) {
179 case NETDEV_REGISTER:
180 /* Should already be registered during the load */
181 if (ibdev->is_rep)
182 break;
183 write_lock(&roce->netdev_lock);
184 if (ndev->dev.parent == mdev->device)
185 roce->netdev = ndev;
186 write_unlock(&roce->netdev_lock);
187 break;
188
189 case NETDEV_UNREGISTER:
190 /* In case of reps, ib device goes away before the netdevs */
191 write_lock(&roce->netdev_lock);
192 if (roce->netdev == ndev)
193 roce->netdev = NULL;
194 write_unlock(&roce->netdev_lock);
195 break;
196
197 case NETDEV_CHANGE:
198 case NETDEV_UP:
199 case NETDEV_DOWN: {
200 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(mdev);
201 struct net_device *upper = NULL;
202
203 if (lag_ndev) {
204 upper = netdev_master_upper_dev_get(lag_ndev);
205 dev_put(lag_ndev);
206 }
207
208 if (ibdev->is_rep)
209 roce = mlx5_get_rep_roce(ibdev, ndev, upper, &port_num);
210 if (!roce)
211 return NOTIFY_DONE;
212 if ((upper == ndev ||
213 ((!upper || ibdev->is_rep) && ndev == roce->netdev)) &&
214 ibdev->ib_active) {
215 struct ib_event ibev = { };
216 enum ib_port_state port_state;
217
218 if (get_port_state(&ibdev->ib_dev, port_num,
219 &port_state))
220 goto done;
221
222 if (roce->last_port_state == port_state)
223 goto done;
224
225 roce->last_port_state = port_state;
226 ibev.device = &ibdev->ib_dev;
227 if (port_state == IB_PORT_DOWN)
228 ibev.event = IB_EVENT_PORT_ERR;
229 else if (port_state == IB_PORT_ACTIVE)
230 ibev.event = IB_EVENT_PORT_ACTIVE;
231 else
232 goto done;
233
234 ibev.element.port_num = port_num;
235 ib_dispatch_event(&ibev);
236 }
237 break;
238 }
239
240 default:
241 break;
242 }
243 done:
244 mlx5_ib_put_native_port_mdev(ibdev, port_num);
245 return NOTIFY_DONE;
246 }
247
mlx5_ib_get_netdev(struct ib_device * device,u32 port_num)248 static struct net_device *mlx5_ib_get_netdev(struct ib_device *device,
249 u32 port_num)
250 {
251 struct mlx5_ib_dev *ibdev = to_mdev(device);
252 struct net_device *ndev;
253 struct mlx5_core_dev *mdev;
254
255 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL);
256 if (!mdev)
257 return NULL;
258
259 ndev = mlx5_lag_get_roce_netdev(mdev);
260 if (ndev)
261 goto out;
262
263 /* Ensure ndev does not disappear before we invoke dev_hold()
264 */
265 read_lock(&ibdev->port[port_num - 1].roce.netdev_lock);
266 ndev = ibdev->port[port_num - 1].roce.netdev;
267 if (ndev)
268 dev_hold(ndev);
269 read_unlock(&ibdev->port[port_num - 1].roce.netdev_lock);
270
271 out:
272 mlx5_ib_put_native_port_mdev(ibdev, port_num);
273 return ndev;
274 }
275
mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev * ibdev,u32 ib_port_num,u32 * native_port_num)276 struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *ibdev,
277 u32 ib_port_num,
278 u32 *native_port_num)
279 {
280 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev,
281 ib_port_num);
282 struct mlx5_core_dev *mdev = NULL;
283 struct mlx5_ib_multiport_info *mpi;
284 struct mlx5_ib_port *port;
285
286 if (!mlx5_core_mp_enabled(ibdev->mdev) ||
287 ll != IB_LINK_LAYER_ETHERNET) {
288 if (native_port_num)
289 *native_port_num = ib_port_num;
290 return ibdev->mdev;
291 }
292
293 if (native_port_num)
294 *native_port_num = 1;
295
296 port = &ibdev->port[ib_port_num - 1];
297 spin_lock(&port->mp.mpi_lock);
298 mpi = ibdev->port[ib_port_num - 1].mp.mpi;
299 if (mpi && !mpi->unaffiliate) {
300 mdev = mpi->mdev;
301 /* If it's the master no need to refcount, it'll exist
302 * as long as the ib_dev exists.
303 */
304 if (!mpi->is_master)
305 mpi->mdev_refcnt++;
306 }
307 spin_unlock(&port->mp.mpi_lock);
308
309 return mdev;
310 }
311
mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev * ibdev,u32 port_num)312 void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *ibdev, u32 port_num)
313 {
314 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev,
315 port_num);
316 struct mlx5_ib_multiport_info *mpi;
317 struct mlx5_ib_port *port;
318
319 if (!mlx5_core_mp_enabled(ibdev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
320 return;
321
322 port = &ibdev->port[port_num - 1];
323
324 spin_lock(&port->mp.mpi_lock);
325 mpi = ibdev->port[port_num - 1].mp.mpi;
326 if (mpi->is_master)
327 goto out;
328
329 mpi->mdev_refcnt--;
330 if (mpi->unaffiliate)
331 complete(&mpi->unref_comp);
332 out:
333 spin_unlock(&port->mp.mpi_lock);
334 }
335
translate_eth_legacy_proto_oper(u32 eth_proto_oper,u16 * active_speed,u8 * active_width)336 static int translate_eth_legacy_proto_oper(u32 eth_proto_oper,
337 u16 *active_speed, u8 *active_width)
338 {
339 switch (eth_proto_oper) {
340 case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII):
341 case MLX5E_PROT_MASK(MLX5E_1000BASE_KX):
342 case MLX5E_PROT_MASK(MLX5E_100BASE_TX):
343 case MLX5E_PROT_MASK(MLX5E_1000BASE_T):
344 *active_width = IB_WIDTH_1X;
345 *active_speed = IB_SPEED_SDR;
346 break;
347 case MLX5E_PROT_MASK(MLX5E_10GBASE_T):
348 case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4):
349 case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4):
350 case MLX5E_PROT_MASK(MLX5E_10GBASE_KR):
351 case MLX5E_PROT_MASK(MLX5E_10GBASE_CR):
352 case MLX5E_PROT_MASK(MLX5E_10GBASE_SR):
353 case MLX5E_PROT_MASK(MLX5E_10GBASE_ER):
354 *active_width = IB_WIDTH_1X;
355 *active_speed = IB_SPEED_QDR;
356 break;
357 case MLX5E_PROT_MASK(MLX5E_25GBASE_CR):
358 case MLX5E_PROT_MASK(MLX5E_25GBASE_KR):
359 case MLX5E_PROT_MASK(MLX5E_25GBASE_SR):
360 *active_width = IB_WIDTH_1X;
361 *active_speed = IB_SPEED_EDR;
362 break;
363 case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4):
364 case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4):
365 case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4):
366 case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4):
367 *active_width = IB_WIDTH_4X;
368 *active_speed = IB_SPEED_QDR;
369 break;
370 case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2):
371 case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2):
372 case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2):
373 *active_width = IB_WIDTH_1X;
374 *active_speed = IB_SPEED_HDR;
375 break;
376 case MLX5E_PROT_MASK(MLX5E_56GBASE_R4):
377 *active_width = IB_WIDTH_4X;
378 *active_speed = IB_SPEED_FDR;
379 break;
380 case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4):
381 case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4):
382 case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4):
383 case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4):
384 *active_width = IB_WIDTH_4X;
385 *active_speed = IB_SPEED_EDR;
386 break;
387 default:
388 return -EINVAL;
389 }
390
391 return 0;
392 }
393
translate_eth_ext_proto_oper(u32 eth_proto_oper,u16 * active_speed,u8 * active_width)394 static int translate_eth_ext_proto_oper(u32 eth_proto_oper, u16 *active_speed,
395 u8 *active_width)
396 {
397 switch (eth_proto_oper) {
398 case MLX5E_PROT_MASK(MLX5E_SGMII_100M):
399 case MLX5E_PROT_MASK(MLX5E_1000BASE_X_SGMII):
400 *active_width = IB_WIDTH_1X;
401 *active_speed = IB_SPEED_SDR;
402 break;
403 case MLX5E_PROT_MASK(MLX5E_5GBASE_R):
404 *active_width = IB_WIDTH_1X;
405 *active_speed = IB_SPEED_DDR;
406 break;
407 case MLX5E_PROT_MASK(MLX5E_10GBASE_XFI_XAUI_1):
408 *active_width = IB_WIDTH_1X;
409 *active_speed = IB_SPEED_QDR;
410 break;
411 case MLX5E_PROT_MASK(MLX5E_40GBASE_XLAUI_4_XLPPI_4):
412 *active_width = IB_WIDTH_4X;
413 *active_speed = IB_SPEED_QDR;
414 break;
415 case MLX5E_PROT_MASK(MLX5E_25GAUI_1_25GBASE_CR_KR):
416 *active_width = IB_WIDTH_1X;
417 *active_speed = IB_SPEED_EDR;
418 break;
419 case MLX5E_PROT_MASK(MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2):
420 *active_width = IB_WIDTH_2X;
421 *active_speed = IB_SPEED_EDR;
422 break;
423 case MLX5E_PROT_MASK(MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR):
424 *active_width = IB_WIDTH_1X;
425 *active_speed = IB_SPEED_HDR;
426 break;
427 case MLX5E_PROT_MASK(MLX5E_CAUI_4_100GBASE_CR4_KR4):
428 *active_width = IB_WIDTH_4X;
429 *active_speed = IB_SPEED_EDR;
430 break;
431 case MLX5E_PROT_MASK(MLX5E_100GAUI_2_100GBASE_CR2_KR2):
432 *active_width = IB_WIDTH_2X;
433 *active_speed = IB_SPEED_HDR;
434 break;
435 case MLX5E_PROT_MASK(MLX5E_100GAUI_1_100GBASE_CR_KR):
436 *active_width = IB_WIDTH_1X;
437 *active_speed = IB_SPEED_NDR;
438 break;
439 case MLX5E_PROT_MASK(MLX5E_200GAUI_4_200GBASE_CR4_KR4):
440 *active_width = IB_WIDTH_4X;
441 *active_speed = IB_SPEED_HDR;
442 break;
443 case MLX5E_PROT_MASK(MLX5E_200GAUI_2_200GBASE_CR2_KR2):
444 *active_width = IB_WIDTH_2X;
445 *active_speed = IB_SPEED_NDR;
446 break;
447 case MLX5E_PROT_MASK(MLX5E_400GAUI_8_400GBASE_CR8):
448 *active_width = IB_WIDTH_8X;
449 *active_speed = IB_SPEED_HDR;
450 break;
451 case MLX5E_PROT_MASK(MLX5E_400GAUI_4_400GBASE_CR4_KR4):
452 *active_width = IB_WIDTH_4X;
453 *active_speed = IB_SPEED_NDR;
454 break;
455 default:
456 return -EINVAL;
457 }
458
459 return 0;
460 }
461
translate_eth_proto_oper(u32 eth_proto_oper,u16 * active_speed,u8 * active_width,bool ext)462 static int translate_eth_proto_oper(u32 eth_proto_oper, u16 *active_speed,
463 u8 *active_width, bool ext)
464 {
465 return ext ?
466 translate_eth_ext_proto_oper(eth_proto_oper, active_speed,
467 active_width) :
468 translate_eth_legacy_proto_oper(eth_proto_oper, active_speed,
469 active_width);
470 }
471
mlx5_query_port_roce(struct ib_device * device,u32 port_num,struct ib_port_attr * props)472 static int mlx5_query_port_roce(struct ib_device *device, u32 port_num,
473 struct ib_port_attr *props)
474 {
475 struct mlx5_ib_dev *dev = to_mdev(device);
476 u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {0};
477 struct mlx5_core_dev *mdev;
478 struct net_device *ndev, *upper;
479 enum ib_mtu ndev_ib_mtu;
480 bool put_mdev = true;
481 u32 eth_prot_oper;
482 u32 mdev_port_num;
483 bool ext;
484 int err;
485
486 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num);
487 if (!mdev) {
488 /* This means the port isn't affiliated yet. Get the
489 * info for the master port instead.
490 */
491 put_mdev = false;
492 mdev = dev->mdev;
493 mdev_port_num = 1;
494 port_num = 1;
495 }
496
497 /* Possible bad flows are checked before filling out props so in case
498 * of an error it will still be zeroed out.
499 * Use native port in case of reps
500 */
501 if (dev->is_rep)
502 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN,
503 1);
504 else
505 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN,
506 mdev_port_num);
507 if (err)
508 goto out;
509 ext = !!MLX5_GET_ETH_PROTO(ptys_reg, out, true, eth_proto_capability);
510 eth_prot_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, eth_proto_oper);
511
512 props->active_width = IB_WIDTH_4X;
513 props->active_speed = IB_SPEED_QDR;
514
515 translate_eth_proto_oper(eth_prot_oper, &props->active_speed,
516 &props->active_width, ext);
517
518 if (!dev->is_rep && dev->mdev->roce.roce_en) {
519 u16 qkey_viol_cntr;
520
521 props->port_cap_flags |= IB_PORT_CM_SUP;
522 props->ip_gids = true;
523 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev,
524 roce_address_table_size);
525 mlx5_query_nic_vport_qkey_viol_cntr(mdev, &qkey_viol_cntr);
526 props->qkey_viol_cntr = qkey_viol_cntr;
527 }
528 props->max_mtu = IB_MTU_4096;
529 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
530 props->pkey_tbl_len = 1;
531 props->state = IB_PORT_DOWN;
532 props->phys_state = IB_PORT_PHYS_STATE_DISABLED;
533
534 /* If this is a stub query for an unaffiliated port stop here */
535 if (!put_mdev)
536 goto out;
537
538 ndev = mlx5_ib_get_netdev(device, port_num);
539 if (!ndev)
540 goto out;
541
542 if (mlx5_lag_is_roce(mdev) || mlx5_lag_is_sriov(mdev)) {
543 rcu_read_lock();
544 upper = netdev_master_upper_dev_get_rcu(ndev);
545 if (upper) {
546 dev_put(ndev);
547 ndev = upper;
548 dev_hold(ndev);
549 }
550 rcu_read_unlock();
551 }
552
553 if (netif_running(ndev) && netif_carrier_ok(ndev)) {
554 props->state = IB_PORT_ACTIVE;
555 props->phys_state = IB_PORT_PHYS_STATE_LINK_UP;
556 }
557
558 ndev_ib_mtu = iboe_get_mtu(ndev->mtu);
559
560 dev_put(ndev);
561
562 props->active_mtu = min(props->max_mtu, ndev_ib_mtu);
563 out:
564 if (put_mdev)
565 mlx5_ib_put_native_port_mdev(dev, port_num);
566 return err;
567 }
568
set_roce_addr(struct mlx5_ib_dev * dev,u32 port_num,unsigned int index,const union ib_gid * gid,const struct ib_gid_attr * attr)569 int set_roce_addr(struct mlx5_ib_dev *dev, u32 port_num,
570 unsigned int index, const union ib_gid *gid,
571 const struct ib_gid_attr *attr)
572 {
573 enum ib_gid_type gid_type;
574 u16 vlan_id = 0xffff;
575 u8 roce_version = 0;
576 u8 roce_l3_type = 0;
577 u8 mac[ETH_ALEN];
578 int ret;
579
580 gid_type = attr->gid_type;
581 if (gid) {
582 ret = rdma_read_gid_l2_fields(attr, &vlan_id, &mac[0]);
583 if (ret)
584 return ret;
585 }
586
587 switch (gid_type) {
588 case IB_GID_TYPE_ROCE:
589 roce_version = MLX5_ROCE_VERSION_1;
590 break;
591 case IB_GID_TYPE_ROCE_UDP_ENCAP:
592 roce_version = MLX5_ROCE_VERSION_2;
593 if (gid && ipv6_addr_v4mapped((void *)gid))
594 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4;
595 else
596 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6;
597 break;
598
599 default:
600 mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type);
601 }
602
603 return mlx5_core_roce_gid_set(dev->mdev, index, roce_version,
604 roce_l3_type, gid->raw, mac,
605 vlan_id < VLAN_CFI_MASK, vlan_id,
606 port_num);
607 }
608
mlx5_ib_add_gid(const struct ib_gid_attr * attr,__always_unused void ** context)609 static int mlx5_ib_add_gid(const struct ib_gid_attr *attr,
610 __always_unused void **context)
611 {
612 int ret;
613
614 ret = mlx5r_add_gid_macsec_operations(attr);
615 if (ret)
616 return ret;
617
618 return set_roce_addr(to_mdev(attr->device), attr->port_num,
619 attr->index, &attr->gid, attr);
620 }
621
mlx5_ib_del_gid(const struct ib_gid_attr * attr,__always_unused void ** context)622 static int mlx5_ib_del_gid(const struct ib_gid_attr *attr,
623 __always_unused void **context)
624 {
625 int ret;
626
627 ret = set_roce_addr(to_mdev(attr->device), attr->port_num,
628 attr->index, NULL, attr);
629 if (ret)
630 return ret;
631
632 mlx5r_del_gid_macsec_operations(attr);
633 return 0;
634 }
635
mlx5_get_roce_udp_sport_min(const struct mlx5_ib_dev * dev,const struct ib_gid_attr * attr)636 __be16 mlx5_get_roce_udp_sport_min(const struct mlx5_ib_dev *dev,
637 const struct ib_gid_attr *attr)
638 {
639 if (attr->gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP)
640 return 0;
641
642 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port));
643 }
644
mlx5_use_mad_ifc(struct mlx5_ib_dev * dev)645 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
646 {
647 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB)
648 return !MLX5_CAP_GEN(dev->mdev, ib_virt);
649 return 0;
650 }
651
652 enum {
653 MLX5_VPORT_ACCESS_METHOD_MAD,
654 MLX5_VPORT_ACCESS_METHOD_HCA,
655 MLX5_VPORT_ACCESS_METHOD_NIC,
656 };
657
mlx5_get_vport_access_method(struct ib_device * ibdev)658 static int mlx5_get_vport_access_method(struct ib_device *ibdev)
659 {
660 if (mlx5_use_mad_ifc(to_mdev(ibdev)))
661 return MLX5_VPORT_ACCESS_METHOD_MAD;
662
663 if (mlx5_ib_port_link_layer(ibdev, 1) ==
664 IB_LINK_LAYER_ETHERNET)
665 return MLX5_VPORT_ACCESS_METHOD_NIC;
666
667 return MLX5_VPORT_ACCESS_METHOD_HCA;
668 }
669
get_atomic_caps(struct mlx5_ib_dev * dev,u8 atomic_size_qp,struct ib_device_attr * props)670 static void get_atomic_caps(struct mlx5_ib_dev *dev,
671 u8 atomic_size_qp,
672 struct ib_device_attr *props)
673 {
674 u8 tmp;
675 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
676 u8 atomic_req_8B_endianness_mode =
677 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode);
678
679 /* Check if HW supports 8 bytes standard atomic operations and capable
680 * of host endianness respond
681 */
682 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD;
683 if (((atomic_operations & tmp) == tmp) &&
684 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) &&
685 (atomic_req_8B_endianness_mode)) {
686 props->atomic_cap = IB_ATOMIC_HCA;
687 } else {
688 props->atomic_cap = IB_ATOMIC_NONE;
689 }
690 }
691
get_atomic_caps_qp(struct mlx5_ib_dev * dev,struct ib_device_attr * props)692 static void get_atomic_caps_qp(struct mlx5_ib_dev *dev,
693 struct ib_device_attr *props)
694 {
695 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
696
697 get_atomic_caps(dev, atomic_size_qp, props);
698 }
699
mlx5_query_system_image_guid(struct ib_device * ibdev,__be64 * sys_image_guid)700 static int mlx5_query_system_image_guid(struct ib_device *ibdev,
701 __be64 *sys_image_guid)
702 {
703 struct mlx5_ib_dev *dev = to_mdev(ibdev);
704 struct mlx5_core_dev *mdev = dev->mdev;
705 u64 tmp;
706 int err;
707
708 switch (mlx5_get_vport_access_method(ibdev)) {
709 case MLX5_VPORT_ACCESS_METHOD_MAD:
710 return mlx5_query_mad_ifc_system_image_guid(ibdev,
711 sys_image_guid);
712
713 case MLX5_VPORT_ACCESS_METHOD_HCA:
714 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
715 break;
716
717 case MLX5_VPORT_ACCESS_METHOD_NIC:
718 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp);
719 break;
720
721 default:
722 return -EINVAL;
723 }
724
725 if (!err)
726 *sys_image_guid = cpu_to_be64(tmp);
727
728 return err;
729
730 }
731
mlx5_query_max_pkeys(struct ib_device * ibdev,u16 * max_pkeys)732 static int mlx5_query_max_pkeys(struct ib_device *ibdev,
733 u16 *max_pkeys)
734 {
735 struct mlx5_ib_dev *dev = to_mdev(ibdev);
736 struct mlx5_core_dev *mdev = dev->mdev;
737
738 switch (mlx5_get_vport_access_method(ibdev)) {
739 case MLX5_VPORT_ACCESS_METHOD_MAD:
740 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);
741
742 case MLX5_VPORT_ACCESS_METHOD_HCA:
743 case MLX5_VPORT_ACCESS_METHOD_NIC:
744 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
745 pkey_table_size));
746 return 0;
747
748 default:
749 return -EINVAL;
750 }
751 }
752
mlx5_query_vendor_id(struct ib_device * ibdev,u32 * vendor_id)753 static int mlx5_query_vendor_id(struct ib_device *ibdev,
754 u32 *vendor_id)
755 {
756 struct mlx5_ib_dev *dev = to_mdev(ibdev);
757
758 switch (mlx5_get_vport_access_method(ibdev)) {
759 case MLX5_VPORT_ACCESS_METHOD_MAD:
760 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);
761
762 case MLX5_VPORT_ACCESS_METHOD_HCA:
763 case MLX5_VPORT_ACCESS_METHOD_NIC:
764 return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
765
766 default:
767 return -EINVAL;
768 }
769 }
770
mlx5_query_node_guid(struct mlx5_ib_dev * dev,__be64 * node_guid)771 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
772 __be64 *node_guid)
773 {
774 u64 tmp;
775 int err;
776
777 switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
778 case MLX5_VPORT_ACCESS_METHOD_MAD:
779 return mlx5_query_mad_ifc_node_guid(dev, node_guid);
780
781 case MLX5_VPORT_ACCESS_METHOD_HCA:
782 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
783 break;
784
785 case MLX5_VPORT_ACCESS_METHOD_NIC:
786 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp);
787 break;
788
789 default:
790 return -EINVAL;
791 }
792
793 if (!err)
794 *node_guid = cpu_to_be64(tmp);
795
796 return err;
797 }
798
799 struct mlx5_reg_node_desc {
800 u8 desc[IB_DEVICE_NODE_DESC_MAX];
801 };
802
mlx5_query_node_desc(struct mlx5_ib_dev * dev,char * node_desc)803 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
804 {
805 struct mlx5_reg_node_desc in;
806
807 if (mlx5_use_mad_ifc(dev))
808 return mlx5_query_mad_ifc_node_desc(dev, node_desc);
809
810 memset(&in, 0, sizeof(in));
811
812 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
813 sizeof(struct mlx5_reg_node_desc),
814 MLX5_REG_NODE_DESC, 0, 0);
815 }
816
mlx5_ib_query_device(struct ib_device * ibdev,struct ib_device_attr * props,struct ib_udata * uhw)817 static int mlx5_ib_query_device(struct ib_device *ibdev,
818 struct ib_device_attr *props,
819 struct ib_udata *uhw)
820 {
821 size_t uhw_outlen = (uhw) ? uhw->outlen : 0;
822 struct mlx5_ib_dev *dev = to_mdev(ibdev);
823 struct mlx5_core_dev *mdev = dev->mdev;
824 int err = -ENOMEM;
825 int max_sq_desc;
826 int max_rq_sg;
827 int max_sq_sg;
828 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
829 bool raw_support = !mlx5_core_mp_enabled(mdev);
830 struct mlx5_ib_query_device_resp resp = {};
831 size_t resp_len;
832 u64 max_tso;
833
834 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length);
835 if (uhw_outlen && uhw_outlen < resp_len)
836 return -EINVAL;
837
838 resp.response_length = resp_len;
839
840 if (uhw && uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen))
841 return -EINVAL;
842
843 memset(props, 0, sizeof(*props));
844 err = mlx5_query_system_image_guid(ibdev,
845 &props->sys_image_guid);
846 if (err)
847 return err;
848
849 props->max_pkeys = dev->pkey_table_len;
850
851 err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
852 if (err)
853 return err;
854
855 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
856 (fw_rev_min(dev->mdev) << 16) |
857 fw_rev_sub(dev->mdev);
858 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
859 IB_DEVICE_PORT_ACTIVE_EVENT |
860 IB_DEVICE_SYS_IMAGE_GUID |
861 IB_DEVICE_RC_RNR_NAK_GEN;
862
863 if (MLX5_CAP_GEN(mdev, pkv))
864 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
865 if (MLX5_CAP_GEN(mdev, qkv))
866 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
867 if (MLX5_CAP_GEN(mdev, apm))
868 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
869 if (MLX5_CAP_GEN(mdev, xrc))
870 props->device_cap_flags |= IB_DEVICE_XRC;
871 if (MLX5_CAP_GEN(mdev, imaicl)) {
872 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW |
873 IB_DEVICE_MEM_WINDOW_TYPE_2B;
874 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
875 /* We support 'Gappy' memory registration too */
876 props->kernel_cap_flags |= IBK_SG_GAPS_REG;
877 }
878 /* IB_WR_REG_MR always requires changing the entity size with UMR */
879 if (!MLX5_CAP_GEN(dev->mdev, umr_modify_entity_size_disabled))
880 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
881 if (MLX5_CAP_GEN(mdev, sho)) {
882 props->kernel_cap_flags |= IBK_INTEGRITY_HANDOVER;
883 /* At this stage no support for signature handover */
884 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
885 IB_PROT_T10DIF_TYPE_2 |
886 IB_PROT_T10DIF_TYPE_3;
887 props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
888 IB_GUARD_T10DIF_CSUM;
889 }
890 if (MLX5_CAP_GEN(mdev, block_lb_mc))
891 props->kernel_cap_flags |= IBK_BLOCK_MULTICAST_LOOPBACK;
892
893 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && raw_support) {
894 if (MLX5_CAP_ETH(mdev, csum_cap)) {
895 /* Legacy bit to support old userspace libraries */
896 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
897 props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM;
898 }
899
900 if (MLX5_CAP_ETH(dev->mdev, vlan_cap))
901 props->raw_packet_caps |=
902 IB_RAW_PACKET_CAP_CVLAN_STRIPPING;
903
904 if (offsetofend(typeof(resp), tso_caps) <= uhw_outlen) {
905 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap);
906 if (max_tso) {
907 resp.tso_caps.max_tso = 1 << max_tso;
908 resp.tso_caps.supported_qpts |=
909 1 << IB_QPT_RAW_PACKET;
910 resp.response_length += sizeof(resp.tso_caps);
911 }
912 }
913
914 if (offsetofend(typeof(resp), rss_caps) <= uhw_outlen) {
915 resp.rss_caps.rx_hash_function =
916 MLX5_RX_HASH_FUNC_TOEPLITZ;
917 resp.rss_caps.rx_hash_fields_mask =
918 MLX5_RX_HASH_SRC_IPV4 |
919 MLX5_RX_HASH_DST_IPV4 |
920 MLX5_RX_HASH_SRC_IPV6 |
921 MLX5_RX_HASH_DST_IPV6 |
922 MLX5_RX_HASH_SRC_PORT_TCP |
923 MLX5_RX_HASH_DST_PORT_TCP |
924 MLX5_RX_HASH_SRC_PORT_UDP |
925 MLX5_RX_HASH_DST_PORT_UDP |
926 MLX5_RX_HASH_INNER;
927 resp.response_length += sizeof(resp.rss_caps);
928 }
929 } else {
930 if (offsetofend(typeof(resp), tso_caps) <= uhw_outlen)
931 resp.response_length += sizeof(resp.tso_caps);
932 if (offsetofend(typeof(resp), rss_caps) <= uhw_outlen)
933 resp.response_length += sizeof(resp.rss_caps);
934 }
935
936 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
937 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
938 props->kernel_cap_flags |= IBK_UD_TSO;
939 }
940
941 if (MLX5_CAP_GEN(dev->mdev, rq_delay_drop) &&
942 MLX5_CAP_GEN(dev->mdev, general_notification_event) &&
943 raw_support)
944 props->raw_packet_caps |= IB_RAW_PACKET_CAP_DELAY_DROP;
945
946 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) &&
947 MLX5_CAP_IPOIB_ENHANCED(mdev, csum_cap))
948 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
949
950 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
951 MLX5_CAP_ETH(dev->mdev, scatter_fcs) &&
952 raw_support) {
953 /* Legacy bit to support old userspace libraries */
954 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS;
955 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS;
956 }
957
958 if (MLX5_CAP_DEV_MEM(mdev, memic)) {
959 props->max_dm_size =
960 MLX5_CAP_DEV_MEM(mdev, max_memic_size);
961 }
962
963 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS))
964 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
965
966 if (MLX5_CAP_GEN(mdev, end_pad))
967 props->device_cap_flags |= IB_DEVICE_PCI_WRITE_END_PADDING;
968
969 props->vendor_part_id = mdev->pdev->device;
970 props->hw_ver = mdev->pdev->revision;
971
972 props->max_mr_size = ~0ull;
973 props->page_size_cap = ~(min_page_size - 1);
974 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
975 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
976 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
977 sizeof(struct mlx5_wqe_data_seg);
978 max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512);
979 max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) -
980 sizeof(struct mlx5_wqe_raddr_seg)) /
981 sizeof(struct mlx5_wqe_data_seg);
982 props->max_send_sge = max_sq_sg;
983 props->max_recv_sge = max_rq_sg;
984 props->max_sge_rd = MLX5_MAX_SGE_RD;
985 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
986 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1;
987 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
988 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
989 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
990 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
991 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
992 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
993 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
994 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp;
995 props->max_srq_sge = max_rq_sg - 1;
996 props->max_fast_reg_page_list_len =
997 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size);
998 props->max_pi_fast_reg_page_list_len =
999 props->max_fast_reg_page_list_len / 2;
1000 props->max_sgl_rd =
1001 MLX5_CAP_GEN(mdev, max_sgl_for_optimized_performance);
1002 get_atomic_caps_qp(dev, props);
1003 props->masked_atomic_cap = IB_ATOMIC_NONE;
1004 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
1005 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
1006 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
1007 props->max_mcast_grp;
1008 props->max_ah = INT_MAX;
1009 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz);
1010 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL;
1011
1012 if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING)) {
1013 if (dev->odp_caps.general_caps & IB_ODP_SUPPORT)
1014 props->kernel_cap_flags |= IBK_ON_DEMAND_PAGING;
1015 props->odp_caps = dev->odp_caps;
1016 if (!uhw) {
1017 /* ODP for kernel QPs is not implemented for receive
1018 * WQEs and SRQ WQEs
1019 */
1020 props->odp_caps.per_transport_caps.rc_odp_caps &=
1021 ~(IB_ODP_SUPPORT_READ |
1022 IB_ODP_SUPPORT_SRQ_RECV);
1023 props->odp_caps.per_transport_caps.uc_odp_caps &=
1024 ~(IB_ODP_SUPPORT_READ |
1025 IB_ODP_SUPPORT_SRQ_RECV);
1026 props->odp_caps.per_transport_caps.ud_odp_caps &=
1027 ~(IB_ODP_SUPPORT_READ |
1028 IB_ODP_SUPPORT_SRQ_RECV);
1029 props->odp_caps.per_transport_caps.xrc_odp_caps &=
1030 ~(IB_ODP_SUPPORT_READ |
1031 IB_ODP_SUPPORT_SRQ_RECV);
1032 }
1033 }
1034
1035 if (mlx5_core_is_vf(mdev))
1036 props->kernel_cap_flags |= IBK_VIRTUAL_FUNCTION;
1037
1038 if (mlx5_ib_port_link_layer(ibdev, 1) ==
1039 IB_LINK_LAYER_ETHERNET && raw_support) {
1040 props->rss_caps.max_rwq_indirection_tables =
1041 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt);
1042 props->rss_caps.max_rwq_indirection_table_size =
1043 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size);
1044 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET;
1045 props->max_wq_type_rq =
1046 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq);
1047 }
1048
1049 if (MLX5_CAP_GEN(mdev, tag_matching)) {
1050 props->tm_caps.max_num_tags =
1051 (1 << MLX5_CAP_GEN(mdev, log_tag_matching_list_sz)) - 1;
1052 props->tm_caps.max_ops =
1053 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
1054 props->tm_caps.max_sge = MLX5_TM_MAX_SGE;
1055 }
1056
1057 if (MLX5_CAP_GEN(mdev, tag_matching) &&
1058 MLX5_CAP_GEN(mdev, rndv_offload_rc)) {
1059 props->tm_caps.flags = IB_TM_CAP_RNDV_RC;
1060 props->tm_caps.max_rndv_hdr_size = MLX5_TM_MAX_RNDV_MSG_SIZE;
1061 }
1062
1063 if (MLX5_CAP_GEN(dev->mdev, cq_moderation)) {
1064 props->cq_caps.max_cq_moderation_count =
1065 MLX5_MAX_CQ_COUNT;
1066 props->cq_caps.max_cq_moderation_period =
1067 MLX5_MAX_CQ_PERIOD;
1068 }
1069
1070 if (offsetofend(typeof(resp), cqe_comp_caps) <= uhw_outlen) {
1071 resp.response_length += sizeof(resp.cqe_comp_caps);
1072
1073 if (MLX5_CAP_GEN(dev->mdev, cqe_compression)) {
1074 resp.cqe_comp_caps.max_num =
1075 MLX5_CAP_GEN(dev->mdev,
1076 cqe_compression_max_num);
1077
1078 resp.cqe_comp_caps.supported_format =
1079 MLX5_IB_CQE_RES_FORMAT_HASH |
1080 MLX5_IB_CQE_RES_FORMAT_CSUM;
1081
1082 if (MLX5_CAP_GEN(dev->mdev, mini_cqe_resp_stride_index))
1083 resp.cqe_comp_caps.supported_format |=
1084 MLX5_IB_CQE_RES_FORMAT_CSUM_STRIDX;
1085 }
1086 }
1087
1088 if (offsetofend(typeof(resp), packet_pacing_caps) <= uhw_outlen &&
1089 raw_support) {
1090 if (MLX5_CAP_QOS(mdev, packet_pacing) &&
1091 MLX5_CAP_GEN(mdev, qos)) {
1092 resp.packet_pacing_caps.qp_rate_limit_max =
1093 MLX5_CAP_QOS(mdev, packet_pacing_max_rate);
1094 resp.packet_pacing_caps.qp_rate_limit_min =
1095 MLX5_CAP_QOS(mdev, packet_pacing_min_rate);
1096 resp.packet_pacing_caps.supported_qpts |=
1097 1 << IB_QPT_RAW_PACKET;
1098 if (MLX5_CAP_QOS(mdev, packet_pacing_burst_bound) &&
1099 MLX5_CAP_QOS(mdev, packet_pacing_typical_size))
1100 resp.packet_pacing_caps.cap_flags |=
1101 MLX5_IB_PP_SUPPORT_BURST;
1102 }
1103 resp.response_length += sizeof(resp.packet_pacing_caps);
1104 }
1105
1106 if (offsetofend(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes) <=
1107 uhw_outlen) {
1108 if (MLX5_CAP_ETH(mdev, multi_pkt_send_wqe))
1109 resp.mlx5_ib_support_multi_pkt_send_wqes =
1110 MLX5_IB_ALLOW_MPW;
1111
1112 if (MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe))
1113 resp.mlx5_ib_support_multi_pkt_send_wqes |=
1114 MLX5_IB_SUPPORT_EMPW;
1115
1116 resp.response_length +=
1117 sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes);
1118 }
1119
1120 if (offsetofend(typeof(resp), flags) <= uhw_outlen) {
1121 resp.response_length += sizeof(resp.flags);
1122
1123 if (MLX5_CAP_GEN(mdev, cqe_compression_128))
1124 resp.flags |=
1125 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP;
1126
1127 if (MLX5_CAP_GEN(mdev, cqe_128_always))
1128 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD;
1129 if (MLX5_CAP_GEN(mdev, qp_packet_based))
1130 resp.flags |=
1131 MLX5_IB_QUERY_DEV_RESP_PACKET_BASED_CREDIT_MODE;
1132
1133 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_SCAT2CQE_DCT;
1134 }
1135
1136 if (offsetofend(typeof(resp), sw_parsing_caps) <= uhw_outlen) {
1137 resp.response_length += sizeof(resp.sw_parsing_caps);
1138 if (MLX5_CAP_ETH(mdev, swp)) {
1139 resp.sw_parsing_caps.sw_parsing_offloads |=
1140 MLX5_IB_SW_PARSING;
1141
1142 if (MLX5_CAP_ETH(mdev, swp_csum))
1143 resp.sw_parsing_caps.sw_parsing_offloads |=
1144 MLX5_IB_SW_PARSING_CSUM;
1145
1146 if (MLX5_CAP_ETH(mdev, swp_lso))
1147 resp.sw_parsing_caps.sw_parsing_offloads |=
1148 MLX5_IB_SW_PARSING_LSO;
1149
1150 if (resp.sw_parsing_caps.sw_parsing_offloads)
1151 resp.sw_parsing_caps.supported_qpts =
1152 BIT(IB_QPT_RAW_PACKET);
1153 }
1154 }
1155
1156 if (offsetofend(typeof(resp), striding_rq_caps) <= uhw_outlen &&
1157 raw_support) {
1158 resp.response_length += sizeof(resp.striding_rq_caps);
1159 if (MLX5_CAP_GEN(mdev, striding_rq)) {
1160 resp.striding_rq_caps.min_single_stride_log_num_of_bytes =
1161 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES;
1162 resp.striding_rq_caps.max_single_stride_log_num_of_bytes =
1163 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES;
1164 if (MLX5_CAP_GEN(dev->mdev, ext_stride_num_range))
1165 resp.striding_rq_caps
1166 .min_single_wqe_log_num_of_strides =
1167 MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES;
1168 else
1169 resp.striding_rq_caps
1170 .min_single_wqe_log_num_of_strides =
1171 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES;
1172 resp.striding_rq_caps.max_single_wqe_log_num_of_strides =
1173 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES;
1174 resp.striding_rq_caps.supported_qpts =
1175 BIT(IB_QPT_RAW_PACKET);
1176 }
1177 }
1178
1179 if (offsetofend(typeof(resp), tunnel_offloads_caps) <= uhw_outlen) {
1180 resp.response_length += sizeof(resp.tunnel_offloads_caps);
1181 if (MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan))
1182 resp.tunnel_offloads_caps |=
1183 MLX5_IB_TUNNELED_OFFLOADS_VXLAN;
1184 if (MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx))
1185 resp.tunnel_offloads_caps |=
1186 MLX5_IB_TUNNELED_OFFLOADS_GENEVE;
1187 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre))
1188 resp.tunnel_offloads_caps |=
1189 MLX5_IB_TUNNELED_OFFLOADS_GRE;
1190 if (MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_gre))
1191 resp.tunnel_offloads_caps |=
1192 MLX5_IB_TUNNELED_OFFLOADS_MPLS_GRE;
1193 if (MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_udp))
1194 resp.tunnel_offloads_caps |=
1195 MLX5_IB_TUNNELED_OFFLOADS_MPLS_UDP;
1196 }
1197
1198 if (offsetofend(typeof(resp), dci_streams_caps) <= uhw_outlen) {
1199 resp.response_length += sizeof(resp.dci_streams_caps);
1200
1201 resp.dci_streams_caps.max_log_num_concurent =
1202 MLX5_CAP_GEN(mdev, log_max_dci_stream_channels);
1203
1204 resp.dci_streams_caps.max_log_num_errored =
1205 MLX5_CAP_GEN(mdev, log_max_dci_errored_streams);
1206 }
1207
1208 if (uhw_outlen) {
1209 err = ib_copy_to_udata(uhw, &resp, resp.response_length);
1210
1211 if (err)
1212 return err;
1213 }
1214
1215 return 0;
1216 }
1217
translate_active_width(struct ib_device * ibdev,u16 active_width,u8 * ib_width)1218 static void translate_active_width(struct ib_device *ibdev, u16 active_width,
1219 u8 *ib_width)
1220 {
1221 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1222
1223 if (active_width & MLX5_PTYS_WIDTH_1X)
1224 *ib_width = IB_WIDTH_1X;
1225 else if (active_width & MLX5_PTYS_WIDTH_2X)
1226 *ib_width = IB_WIDTH_2X;
1227 else if (active_width & MLX5_PTYS_WIDTH_4X)
1228 *ib_width = IB_WIDTH_4X;
1229 else if (active_width & MLX5_PTYS_WIDTH_8X)
1230 *ib_width = IB_WIDTH_8X;
1231 else if (active_width & MLX5_PTYS_WIDTH_12X)
1232 *ib_width = IB_WIDTH_12X;
1233 else {
1234 mlx5_ib_dbg(dev, "Invalid active_width %d, setting width to default value: 4x\n",
1235 active_width);
1236 *ib_width = IB_WIDTH_4X;
1237 }
1238
1239 return;
1240 }
1241
mlx5_mtu_to_ib_mtu(int mtu)1242 static int mlx5_mtu_to_ib_mtu(int mtu)
1243 {
1244 switch (mtu) {
1245 case 256: return 1;
1246 case 512: return 2;
1247 case 1024: return 3;
1248 case 2048: return 4;
1249 case 4096: return 5;
1250 default:
1251 pr_warn("invalid mtu\n");
1252 return -1;
1253 }
1254 }
1255
1256 enum ib_max_vl_num {
1257 __IB_MAX_VL_0 = 1,
1258 __IB_MAX_VL_0_1 = 2,
1259 __IB_MAX_VL_0_3 = 3,
1260 __IB_MAX_VL_0_7 = 4,
1261 __IB_MAX_VL_0_14 = 5,
1262 };
1263
1264 enum mlx5_vl_hw_cap {
1265 MLX5_VL_HW_0 = 1,
1266 MLX5_VL_HW_0_1 = 2,
1267 MLX5_VL_HW_0_2 = 3,
1268 MLX5_VL_HW_0_3 = 4,
1269 MLX5_VL_HW_0_4 = 5,
1270 MLX5_VL_HW_0_5 = 6,
1271 MLX5_VL_HW_0_6 = 7,
1272 MLX5_VL_HW_0_7 = 8,
1273 MLX5_VL_HW_0_14 = 15
1274 };
1275
translate_max_vl_num(struct ib_device * ibdev,u8 vl_hw_cap,u8 * max_vl_num)1276 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
1277 u8 *max_vl_num)
1278 {
1279 switch (vl_hw_cap) {
1280 case MLX5_VL_HW_0:
1281 *max_vl_num = __IB_MAX_VL_0;
1282 break;
1283 case MLX5_VL_HW_0_1:
1284 *max_vl_num = __IB_MAX_VL_0_1;
1285 break;
1286 case MLX5_VL_HW_0_3:
1287 *max_vl_num = __IB_MAX_VL_0_3;
1288 break;
1289 case MLX5_VL_HW_0_7:
1290 *max_vl_num = __IB_MAX_VL_0_7;
1291 break;
1292 case MLX5_VL_HW_0_14:
1293 *max_vl_num = __IB_MAX_VL_0_14;
1294 break;
1295
1296 default:
1297 return -EINVAL;
1298 }
1299
1300 return 0;
1301 }
1302
mlx5_query_hca_port(struct ib_device * ibdev,u32 port,struct ib_port_attr * props)1303 static int mlx5_query_hca_port(struct ib_device *ibdev, u32 port,
1304 struct ib_port_attr *props)
1305 {
1306 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1307 struct mlx5_core_dev *mdev = dev->mdev;
1308 struct mlx5_hca_vport_context *rep;
1309 u16 max_mtu;
1310 u16 oper_mtu;
1311 int err;
1312 u16 ib_link_width_oper;
1313 u8 vl_hw_cap;
1314
1315 rep = kzalloc(sizeof(*rep), GFP_KERNEL);
1316 if (!rep) {
1317 err = -ENOMEM;
1318 goto out;
1319 }
1320
1321 /* props being zeroed by the caller, avoid zeroing it here */
1322
1323 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep);
1324 if (err)
1325 goto out;
1326
1327 props->lid = rep->lid;
1328 props->lmc = rep->lmc;
1329 props->sm_lid = rep->sm_lid;
1330 props->sm_sl = rep->sm_sl;
1331 props->state = rep->vport_state;
1332 props->phys_state = rep->port_physical_state;
1333 props->port_cap_flags = rep->cap_mask1;
1334 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
1335 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
1336 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
1337 props->bad_pkey_cntr = rep->pkey_violation_counter;
1338 props->qkey_viol_cntr = rep->qkey_violation_counter;
1339 props->subnet_timeout = rep->subnet_timeout;
1340 props->init_type_reply = rep->init_type_reply;
1341
1342 if (props->port_cap_flags & IB_PORT_CAP_MASK2_SUP)
1343 props->port_cap_flags2 = rep->cap_mask2;
1344
1345 err = mlx5_query_ib_port_oper(mdev, &ib_link_width_oper,
1346 &props->active_speed, port);
1347 if (err)
1348 goto out;
1349
1350 translate_active_width(ibdev, ib_link_width_oper, &props->active_width);
1351
1352 mlx5_query_port_max_mtu(mdev, &max_mtu, port);
1353
1354 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu);
1355
1356 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port);
1357
1358 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu);
1359
1360 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port);
1361 if (err)
1362 goto out;
1363
1364 err = translate_max_vl_num(ibdev, vl_hw_cap,
1365 &props->max_vl_num);
1366 out:
1367 kfree(rep);
1368 return err;
1369 }
1370
mlx5_ib_query_port(struct ib_device * ibdev,u32 port,struct ib_port_attr * props)1371 int mlx5_ib_query_port(struct ib_device *ibdev, u32 port,
1372 struct ib_port_attr *props)
1373 {
1374 unsigned int count;
1375 int ret;
1376
1377 switch (mlx5_get_vport_access_method(ibdev)) {
1378 case MLX5_VPORT_ACCESS_METHOD_MAD:
1379 ret = mlx5_query_mad_ifc_port(ibdev, port, props);
1380 break;
1381
1382 case MLX5_VPORT_ACCESS_METHOD_HCA:
1383 ret = mlx5_query_hca_port(ibdev, port, props);
1384 break;
1385
1386 case MLX5_VPORT_ACCESS_METHOD_NIC:
1387 ret = mlx5_query_port_roce(ibdev, port, props);
1388 break;
1389
1390 default:
1391 ret = -EINVAL;
1392 }
1393
1394 if (!ret && props) {
1395 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1396 struct mlx5_core_dev *mdev;
1397 bool put_mdev = true;
1398
1399 mdev = mlx5_ib_get_native_port_mdev(dev, port, NULL);
1400 if (!mdev) {
1401 /* If the port isn't affiliated yet query the master.
1402 * The master and slave will have the same values.
1403 */
1404 mdev = dev->mdev;
1405 port = 1;
1406 put_mdev = false;
1407 }
1408 count = mlx5_core_reserved_gids_count(mdev);
1409 if (put_mdev)
1410 mlx5_ib_put_native_port_mdev(dev, port);
1411 props->gid_tbl_len -= count;
1412 }
1413 return ret;
1414 }
1415
mlx5_ib_rep_query_port(struct ib_device * ibdev,u32 port,struct ib_port_attr * props)1416 static int mlx5_ib_rep_query_port(struct ib_device *ibdev, u32 port,
1417 struct ib_port_attr *props)
1418 {
1419 return mlx5_query_port_roce(ibdev, port, props);
1420 }
1421
mlx5_ib_rep_query_pkey(struct ib_device * ibdev,u32 port,u16 index,u16 * pkey)1422 static int mlx5_ib_rep_query_pkey(struct ib_device *ibdev, u32 port, u16 index,
1423 u16 *pkey)
1424 {
1425 /* Default special Pkey for representor device port as per the
1426 * IB specification 1.3 section 10.9.1.2.
1427 */
1428 *pkey = 0xffff;
1429 return 0;
1430 }
1431
mlx5_ib_query_gid(struct ib_device * ibdev,u32 port,int index,union ib_gid * gid)1432 static int mlx5_ib_query_gid(struct ib_device *ibdev, u32 port, int index,
1433 union ib_gid *gid)
1434 {
1435 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1436 struct mlx5_core_dev *mdev = dev->mdev;
1437
1438 switch (mlx5_get_vport_access_method(ibdev)) {
1439 case MLX5_VPORT_ACCESS_METHOD_MAD:
1440 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);
1441
1442 case MLX5_VPORT_ACCESS_METHOD_HCA:
1443 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid);
1444
1445 default:
1446 return -EINVAL;
1447 }
1448
1449 }
1450
mlx5_query_hca_nic_pkey(struct ib_device * ibdev,u32 port,u16 index,u16 * pkey)1451 static int mlx5_query_hca_nic_pkey(struct ib_device *ibdev, u32 port,
1452 u16 index, u16 *pkey)
1453 {
1454 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1455 struct mlx5_core_dev *mdev;
1456 bool put_mdev = true;
1457 u32 mdev_port_num;
1458 int err;
1459
1460 mdev = mlx5_ib_get_native_port_mdev(dev, port, &mdev_port_num);
1461 if (!mdev) {
1462 /* The port isn't affiliated yet, get the PKey from the master
1463 * port. For RoCE the PKey tables will be the same.
1464 */
1465 put_mdev = false;
1466 mdev = dev->mdev;
1467 mdev_port_num = 1;
1468 }
1469
1470 err = mlx5_query_hca_vport_pkey(mdev, 0, mdev_port_num, 0,
1471 index, pkey);
1472 if (put_mdev)
1473 mlx5_ib_put_native_port_mdev(dev, port);
1474
1475 return err;
1476 }
1477
mlx5_ib_query_pkey(struct ib_device * ibdev,u32 port,u16 index,u16 * pkey)1478 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u32 port, u16 index,
1479 u16 *pkey)
1480 {
1481 switch (mlx5_get_vport_access_method(ibdev)) {
1482 case MLX5_VPORT_ACCESS_METHOD_MAD:
1483 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);
1484
1485 case MLX5_VPORT_ACCESS_METHOD_HCA:
1486 case MLX5_VPORT_ACCESS_METHOD_NIC:
1487 return mlx5_query_hca_nic_pkey(ibdev, port, index, pkey);
1488 default:
1489 return -EINVAL;
1490 }
1491 }
1492
mlx5_ib_modify_device(struct ib_device * ibdev,int mask,struct ib_device_modify * props)1493 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
1494 struct ib_device_modify *props)
1495 {
1496 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1497 struct mlx5_reg_node_desc in;
1498 struct mlx5_reg_node_desc out;
1499 int err;
1500
1501 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
1502 return -EOPNOTSUPP;
1503
1504 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
1505 return 0;
1506
1507 /*
1508 * If possible, pass node desc to FW, so it can generate
1509 * a 144 trap. If cmd fails, just ignore.
1510 */
1511 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
1512 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
1513 sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
1514 if (err)
1515 return err;
1516
1517 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
1518
1519 return err;
1520 }
1521
set_port_caps_atomic(struct mlx5_ib_dev * dev,u32 port_num,u32 mask,u32 value)1522 static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u32 port_num, u32 mask,
1523 u32 value)
1524 {
1525 struct mlx5_hca_vport_context ctx = {};
1526 struct mlx5_core_dev *mdev;
1527 u32 mdev_port_num;
1528 int err;
1529
1530 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num);
1531 if (!mdev)
1532 return -ENODEV;
1533
1534 err = mlx5_query_hca_vport_context(mdev, 0, mdev_port_num, 0, &ctx);
1535 if (err)
1536 goto out;
1537
1538 if (~ctx.cap_mask1_perm & mask) {
1539 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n",
1540 mask, ctx.cap_mask1_perm);
1541 err = -EINVAL;
1542 goto out;
1543 }
1544
1545 ctx.cap_mask1 = value;
1546 ctx.cap_mask1_perm = mask;
1547 err = mlx5_core_modify_hca_vport_context(mdev, 0, mdev_port_num,
1548 0, &ctx);
1549
1550 out:
1551 mlx5_ib_put_native_port_mdev(dev, port_num);
1552
1553 return err;
1554 }
1555
mlx5_ib_modify_port(struct ib_device * ibdev,u32 port,int mask,struct ib_port_modify * props)1556 static int mlx5_ib_modify_port(struct ib_device *ibdev, u32 port, int mask,
1557 struct ib_port_modify *props)
1558 {
1559 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1560 struct ib_port_attr attr;
1561 u32 tmp;
1562 int err;
1563 u32 change_mask;
1564 u32 value;
1565 bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) ==
1566 IB_LINK_LAYER_INFINIBAND);
1567
1568 /* CM layer calls ib_modify_port() regardless of the link layer. For
1569 * Ethernet ports, qkey violation and Port capabilities are meaningless.
1570 */
1571 if (!is_ib)
1572 return 0;
1573
1574 if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) {
1575 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask;
1576 value = ~props->clr_port_cap_mask | props->set_port_cap_mask;
1577 return set_port_caps_atomic(dev, port, change_mask, value);
1578 }
1579
1580 mutex_lock(&dev->cap_mask_mutex);
1581
1582 err = ib_query_port(ibdev, port, &attr);
1583 if (err)
1584 goto out;
1585
1586 tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
1587 ~props->clr_port_cap_mask;
1588
1589 err = mlx5_set_port_caps(dev->mdev, port, tmp);
1590
1591 out:
1592 mutex_unlock(&dev->cap_mask_mutex);
1593 return err;
1594 }
1595
print_lib_caps(struct mlx5_ib_dev * dev,u64 caps)1596 static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps)
1597 {
1598 mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n",
1599 caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n");
1600 }
1601
calc_dynamic_bfregs(int uars_per_sys_page)1602 static u16 calc_dynamic_bfregs(int uars_per_sys_page)
1603 {
1604 /* Large page with non 4k uar support might limit the dynamic size */
1605 if (uars_per_sys_page == 1 && PAGE_SIZE > 4096)
1606 return MLX5_MIN_DYN_BFREGS;
1607
1608 return MLX5_MAX_DYN_BFREGS;
1609 }
1610
calc_total_bfregs(struct mlx5_ib_dev * dev,bool lib_uar_4k,struct mlx5_ib_alloc_ucontext_req_v2 * req,struct mlx5_bfreg_info * bfregi)1611 static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k,
1612 struct mlx5_ib_alloc_ucontext_req_v2 *req,
1613 struct mlx5_bfreg_info *bfregi)
1614 {
1615 int uars_per_sys_page;
1616 int bfregs_per_sys_page;
1617 int ref_bfregs = req->total_num_bfregs;
1618
1619 if (req->total_num_bfregs == 0)
1620 return -EINVAL;
1621
1622 BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE);
1623 BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE);
1624
1625 if (req->total_num_bfregs > MLX5_MAX_BFREGS)
1626 return -ENOMEM;
1627
1628 uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k);
1629 bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR;
1630 /* This holds the required static allocation asked by the user */
1631 req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page);
1632 if (req->num_low_latency_bfregs > req->total_num_bfregs - 1)
1633 return -EINVAL;
1634
1635 bfregi->num_static_sys_pages = req->total_num_bfregs / bfregs_per_sys_page;
1636 bfregi->num_dyn_bfregs = ALIGN(calc_dynamic_bfregs(uars_per_sys_page), bfregs_per_sys_page);
1637 bfregi->total_num_bfregs = req->total_num_bfregs + bfregi->num_dyn_bfregs;
1638 bfregi->num_sys_pages = bfregi->total_num_bfregs / bfregs_per_sys_page;
1639
1640 mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, total bfregs %d, using %d sys pages\n",
1641 MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no",
1642 lib_uar_4k ? "yes" : "no", ref_bfregs,
1643 req->total_num_bfregs, bfregi->total_num_bfregs,
1644 bfregi->num_sys_pages);
1645
1646 return 0;
1647 }
1648
allocate_uars(struct mlx5_ib_dev * dev,struct mlx5_ib_ucontext * context)1649 static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
1650 {
1651 struct mlx5_bfreg_info *bfregi;
1652 int err;
1653 int i;
1654
1655 bfregi = &context->bfregi;
1656 for (i = 0; i < bfregi->num_static_sys_pages; i++) {
1657 err = mlx5_cmd_uar_alloc(dev->mdev, &bfregi->sys_pages[i],
1658 context->devx_uid);
1659 if (err)
1660 goto error;
1661
1662 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]);
1663 }
1664
1665 for (i = bfregi->num_static_sys_pages; i < bfregi->num_sys_pages; i++)
1666 bfregi->sys_pages[i] = MLX5_IB_INVALID_UAR_INDEX;
1667
1668 return 0;
1669
1670 error:
1671 for (--i; i >= 0; i--)
1672 if (mlx5_cmd_uar_dealloc(dev->mdev, bfregi->sys_pages[i],
1673 context->devx_uid))
1674 mlx5_ib_warn(dev, "failed to free uar %d\n", i);
1675
1676 return err;
1677 }
1678
deallocate_uars(struct mlx5_ib_dev * dev,struct mlx5_ib_ucontext * context)1679 static void deallocate_uars(struct mlx5_ib_dev *dev,
1680 struct mlx5_ib_ucontext *context)
1681 {
1682 struct mlx5_bfreg_info *bfregi;
1683 int i;
1684
1685 bfregi = &context->bfregi;
1686 for (i = 0; i < bfregi->num_sys_pages; i++)
1687 if (i < bfregi->num_static_sys_pages ||
1688 bfregi->sys_pages[i] != MLX5_IB_INVALID_UAR_INDEX)
1689 mlx5_cmd_uar_dealloc(dev->mdev, bfregi->sys_pages[i],
1690 context->devx_uid);
1691 }
1692
mlx5_ib_enable_lb_mp(struct mlx5_core_dev * master,struct mlx5_core_dev * slave)1693 static int mlx5_ib_enable_lb_mp(struct mlx5_core_dev *master,
1694 struct mlx5_core_dev *slave)
1695 {
1696 int err;
1697
1698 err = mlx5_nic_vport_update_local_lb(master, true);
1699 if (err)
1700 return err;
1701
1702 err = mlx5_nic_vport_update_local_lb(slave, true);
1703 if (err)
1704 goto out;
1705
1706 return 0;
1707
1708 out:
1709 mlx5_nic_vport_update_local_lb(master, false);
1710 return err;
1711 }
1712
mlx5_ib_disable_lb_mp(struct mlx5_core_dev * master,struct mlx5_core_dev * slave)1713 static void mlx5_ib_disable_lb_mp(struct mlx5_core_dev *master,
1714 struct mlx5_core_dev *slave)
1715 {
1716 mlx5_nic_vport_update_local_lb(slave, false);
1717 mlx5_nic_vport_update_local_lb(master, false);
1718 }
1719
mlx5_ib_enable_lb(struct mlx5_ib_dev * dev,bool td,bool qp)1720 int mlx5_ib_enable_lb(struct mlx5_ib_dev *dev, bool td, bool qp)
1721 {
1722 int err = 0;
1723
1724 mutex_lock(&dev->lb.mutex);
1725 if (td)
1726 dev->lb.user_td++;
1727 if (qp)
1728 dev->lb.qps++;
1729
1730 if (dev->lb.user_td == 2 ||
1731 dev->lb.qps == 1) {
1732 if (!dev->lb.enabled) {
1733 err = mlx5_nic_vport_update_local_lb(dev->mdev, true);
1734 dev->lb.enabled = true;
1735 }
1736 }
1737
1738 mutex_unlock(&dev->lb.mutex);
1739
1740 return err;
1741 }
1742
mlx5_ib_disable_lb(struct mlx5_ib_dev * dev,bool td,bool qp)1743 void mlx5_ib_disable_lb(struct mlx5_ib_dev *dev, bool td, bool qp)
1744 {
1745 mutex_lock(&dev->lb.mutex);
1746 if (td)
1747 dev->lb.user_td--;
1748 if (qp)
1749 dev->lb.qps--;
1750
1751 if (dev->lb.user_td == 1 &&
1752 dev->lb.qps == 0) {
1753 if (dev->lb.enabled) {
1754 mlx5_nic_vport_update_local_lb(dev->mdev, false);
1755 dev->lb.enabled = false;
1756 }
1757 }
1758
1759 mutex_unlock(&dev->lb.mutex);
1760 }
1761
mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev * dev,u32 * tdn,u16 uid)1762 static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn,
1763 u16 uid)
1764 {
1765 int err;
1766
1767 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1768 return 0;
1769
1770 err = mlx5_cmd_alloc_transport_domain(dev->mdev, tdn, uid);
1771 if (err)
1772 return err;
1773
1774 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
1775 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
1776 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
1777 return err;
1778
1779 return mlx5_ib_enable_lb(dev, true, false);
1780 }
1781
mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev * dev,u32 tdn,u16 uid)1782 static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn,
1783 u16 uid)
1784 {
1785 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1786 return;
1787
1788 mlx5_cmd_dealloc_transport_domain(dev->mdev, tdn, uid);
1789
1790 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
1791 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
1792 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
1793 return;
1794
1795 mlx5_ib_disable_lb(dev, true, false);
1796 }
1797
set_ucontext_resp(struct ib_ucontext * uctx,struct mlx5_ib_alloc_ucontext_resp * resp)1798 static int set_ucontext_resp(struct ib_ucontext *uctx,
1799 struct mlx5_ib_alloc_ucontext_resp *resp)
1800 {
1801 struct ib_device *ibdev = uctx->device;
1802 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1803 struct mlx5_ib_ucontext *context = to_mucontext(uctx);
1804 struct mlx5_bfreg_info *bfregi = &context->bfregi;
1805
1806 if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) {
1807 resp->dump_fill_mkey = dev->mkeys.dump_fill_mkey;
1808 resp->comp_mask |=
1809 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_DUMP_FILL_MKEY;
1810 }
1811
1812 resp->qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
1813 if (dev->wc_support)
1814 resp->bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev,
1815 log_bf_reg_size);
1816 resp->cache_line_size = cache_line_size();
1817 resp->max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
1818 resp->max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
1819 resp->max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1820 resp->max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1821 resp->max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
1822 resp->cqe_version = context->cqe_version;
1823 resp->log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1824 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT;
1825 resp->num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1826 MLX5_CAP_GEN(dev->mdev,
1827 num_of_uars_per_page) : 1;
1828 resp->tot_bfregs = bfregi->lib_uar_dyn ? 0 :
1829 bfregi->total_num_bfregs - bfregi->num_dyn_bfregs;
1830 resp->num_ports = dev->num_ports;
1831 resp->cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE |
1832 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH;
1833
1834 if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) {
1835 mlx5_query_min_inline(dev->mdev, &resp->eth_min_inline);
1836 resp->eth_min_inline++;
1837 }
1838
1839 if (dev->mdev->clock_info)
1840 resp->clock_info_versions = BIT(MLX5_IB_CLOCK_INFO_V1);
1841
1842 /*
1843 * We don't want to expose information from the PCI bar that is located
1844 * after 4096 bytes, so if the arch only supports larger pages, let's
1845 * pretend we don't support reading the HCA's core clock. This is also
1846 * forced by mmap function.
1847 */
1848 if (PAGE_SIZE <= 4096) {
1849 resp->comp_mask |=
1850 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET;
1851 resp->hca_core_clock_offset =
1852 offsetof(struct mlx5_init_seg,
1853 internal_timer_h) % PAGE_SIZE;
1854 }
1855
1856 if (MLX5_CAP_GEN(dev->mdev, ece_support))
1857 resp->comp_mask |= MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_ECE;
1858
1859 if (rt_supported(MLX5_CAP_GEN(dev->mdev, sq_ts_format)) &&
1860 rt_supported(MLX5_CAP_GEN(dev->mdev, rq_ts_format)) &&
1861 rt_supported(MLX5_CAP_ROCE(dev->mdev, qp_ts_format)))
1862 resp->comp_mask |=
1863 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_REAL_TIME_TS;
1864
1865 resp->num_dyn_bfregs = bfregi->num_dyn_bfregs;
1866
1867 if (MLX5_CAP_GEN(dev->mdev, drain_sigerr))
1868 resp->comp_mask |= MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_SQD2RTS;
1869
1870 resp->comp_mask |=
1871 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_MKEY_UPDATE_TAG;
1872
1873 return 0;
1874 }
1875
mlx5_ib_alloc_ucontext(struct ib_ucontext * uctx,struct ib_udata * udata)1876 static int mlx5_ib_alloc_ucontext(struct ib_ucontext *uctx,
1877 struct ib_udata *udata)
1878 {
1879 struct ib_device *ibdev = uctx->device;
1880 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1881 struct mlx5_ib_alloc_ucontext_req_v2 req = {};
1882 struct mlx5_ib_alloc_ucontext_resp resp = {};
1883 struct mlx5_ib_ucontext *context = to_mucontext(uctx);
1884 struct mlx5_bfreg_info *bfregi;
1885 int ver;
1886 int err;
1887 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2,
1888 max_cqe_version);
1889 bool lib_uar_4k;
1890 bool lib_uar_dyn;
1891
1892 if (!dev->ib_active)
1893 return -EAGAIN;
1894
1895 if (udata->inlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
1896 ver = 0;
1897 else if (udata->inlen >= min_req_v2)
1898 ver = 2;
1899 else
1900 return -EINVAL;
1901
1902 err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req)));
1903 if (err)
1904 return err;
1905
1906 if (req.flags & ~MLX5_IB_ALLOC_UCTX_DEVX)
1907 return -EOPNOTSUPP;
1908
1909 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2)
1910 return -EOPNOTSUPP;
1911
1912 req.total_num_bfregs = ALIGN(req.total_num_bfregs,
1913 MLX5_NON_FP_BFREGS_PER_UAR);
1914 if (req.num_low_latency_bfregs > req.total_num_bfregs - 1)
1915 return -EINVAL;
1916
1917 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX) {
1918 err = mlx5_ib_devx_create(dev, true);
1919 if (err < 0)
1920 goto out_ctx;
1921 context->devx_uid = err;
1922 }
1923
1924 lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR;
1925 lib_uar_dyn = req.lib_caps & MLX5_LIB_CAP_DYN_UAR;
1926 bfregi = &context->bfregi;
1927
1928 if (lib_uar_dyn) {
1929 bfregi->lib_uar_dyn = lib_uar_dyn;
1930 goto uar_done;
1931 }
1932
1933 /* updates req->total_num_bfregs */
1934 err = calc_total_bfregs(dev, lib_uar_4k, &req, bfregi);
1935 if (err)
1936 goto out_devx;
1937
1938 mutex_init(&bfregi->lock);
1939 bfregi->lib_uar_4k = lib_uar_4k;
1940 bfregi->count = kcalloc(bfregi->total_num_bfregs, sizeof(*bfregi->count),
1941 GFP_KERNEL);
1942 if (!bfregi->count) {
1943 err = -ENOMEM;
1944 goto out_devx;
1945 }
1946
1947 bfregi->sys_pages = kcalloc(bfregi->num_sys_pages,
1948 sizeof(*bfregi->sys_pages),
1949 GFP_KERNEL);
1950 if (!bfregi->sys_pages) {
1951 err = -ENOMEM;
1952 goto out_count;
1953 }
1954
1955 err = allocate_uars(dev, context);
1956 if (err)
1957 goto out_sys_pages;
1958
1959 uar_done:
1960 err = mlx5_ib_alloc_transport_domain(dev, &context->tdn,
1961 context->devx_uid);
1962 if (err)
1963 goto out_uars;
1964
1965 INIT_LIST_HEAD(&context->db_page_list);
1966 mutex_init(&context->db_page_mutex);
1967
1968 context->cqe_version = min_t(__u8,
1969 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version),
1970 req.max_cqe_version);
1971
1972 err = set_ucontext_resp(uctx, &resp);
1973 if (err)
1974 goto out_mdev;
1975
1976 resp.response_length = min(udata->outlen, sizeof(resp));
1977 err = ib_copy_to_udata(udata, &resp, resp.response_length);
1978 if (err)
1979 goto out_mdev;
1980
1981 bfregi->ver = ver;
1982 bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs;
1983 context->lib_caps = req.lib_caps;
1984 print_lib_caps(dev, context->lib_caps);
1985
1986 if (mlx5_ib_lag_should_assign_affinity(dev)) {
1987 u32 port = mlx5_core_native_port_num(dev->mdev) - 1;
1988
1989 atomic_set(&context->tx_port_affinity,
1990 atomic_add_return(
1991 1, &dev->port[port].roce.tx_port_affinity));
1992 }
1993
1994 return 0;
1995
1996 out_mdev:
1997 mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid);
1998
1999 out_uars:
2000 deallocate_uars(dev, context);
2001
2002 out_sys_pages:
2003 kfree(bfregi->sys_pages);
2004
2005 out_count:
2006 kfree(bfregi->count);
2007
2008 out_devx:
2009 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX)
2010 mlx5_ib_devx_destroy(dev, context->devx_uid);
2011
2012 out_ctx:
2013 return err;
2014 }
2015
mlx5_ib_query_ucontext(struct ib_ucontext * ibcontext,struct uverbs_attr_bundle * attrs)2016 static int mlx5_ib_query_ucontext(struct ib_ucontext *ibcontext,
2017 struct uverbs_attr_bundle *attrs)
2018 {
2019 struct mlx5_ib_alloc_ucontext_resp uctx_resp = {};
2020 int ret;
2021
2022 ret = set_ucontext_resp(ibcontext, &uctx_resp);
2023 if (ret)
2024 return ret;
2025
2026 uctx_resp.response_length =
2027 min_t(size_t,
2028 uverbs_attr_get_len(attrs,
2029 MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX),
2030 sizeof(uctx_resp));
2031
2032 ret = uverbs_copy_to_struct_or_zero(attrs,
2033 MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX,
2034 &uctx_resp,
2035 sizeof(uctx_resp));
2036 return ret;
2037 }
2038
mlx5_ib_dealloc_ucontext(struct ib_ucontext * ibcontext)2039 static void mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
2040 {
2041 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
2042 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
2043 struct mlx5_bfreg_info *bfregi;
2044
2045 bfregi = &context->bfregi;
2046 mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid);
2047
2048 deallocate_uars(dev, context);
2049 kfree(bfregi->sys_pages);
2050 kfree(bfregi->count);
2051
2052 if (context->devx_uid)
2053 mlx5_ib_devx_destroy(dev, context->devx_uid);
2054 }
2055
uar_index2pfn(struct mlx5_ib_dev * dev,int uar_idx)2056 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev,
2057 int uar_idx)
2058 {
2059 int fw_uars_per_page;
2060
2061 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1;
2062
2063 return (dev->mdev->bar_addr >> PAGE_SHIFT) + uar_idx / fw_uars_per_page;
2064 }
2065
uar_index2paddress(struct mlx5_ib_dev * dev,int uar_idx)2066 static u64 uar_index2paddress(struct mlx5_ib_dev *dev,
2067 int uar_idx)
2068 {
2069 unsigned int fw_uars_per_page;
2070
2071 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
2072 MLX5_UARS_IN_PAGE : 1;
2073
2074 return (dev->mdev->bar_addr + (uar_idx / fw_uars_per_page) * PAGE_SIZE);
2075 }
2076
get_command(unsigned long offset)2077 static int get_command(unsigned long offset)
2078 {
2079 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
2080 }
2081
get_arg(unsigned long offset)2082 static int get_arg(unsigned long offset)
2083 {
2084 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
2085 }
2086
get_index(unsigned long offset)2087 static int get_index(unsigned long offset)
2088 {
2089 return get_arg(offset);
2090 }
2091
2092 /* Index resides in an extra byte to enable larger values than 255 */
get_extended_index(unsigned long offset)2093 static int get_extended_index(unsigned long offset)
2094 {
2095 return get_arg(offset) | ((offset >> 16) & 0xff) << 8;
2096 }
2097
2098
mlx5_ib_disassociate_ucontext(struct ib_ucontext * ibcontext)2099 static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
2100 {
2101 }
2102
mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd)2103 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd)
2104 {
2105 switch (cmd) {
2106 case MLX5_IB_MMAP_WC_PAGE:
2107 return "WC";
2108 case MLX5_IB_MMAP_REGULAR_PAGE:
2109 return "best effort WC";
2110 case MLX5_IB_MMAP_NC_PAGE:
2111 return "NC";
2112 case MLX5_IB_MMAP_DEVICE_MEM:
2113 return "Device Memory";
2114 default:
2115 return "Unknown";
2116 }
2117 }
2118
mlx5_ib_mmap_clock_info_page(struct mlx5_ib_dev * dev,struct vm_area_struct * vma,struct mlx5_ib_ucontext * context)2119 static int mlx5_ib_mmap_clock_info_page(struct mlx5_ib_dev *dev,
2120 struct vm_area_struct *vma,
2121 struct mlx5_ib_ucontext *context)
2122 {
2123 if ((vma->vm_end - vma->vm_start != PAGE_SIZE) ||
2124 !(vma->vm_flags & VM_SHARED))
2125 return -EINVAL;
2126
2127 if (get_index(vma->vm_pgoff) != MLX5_IB_CLOCK_INFO_V1)
2128 return -EOPNOTSUPP;
2129
2130 if (vma->vm_flags & (VM_WRITE | VM_EXEC))
2131 return -EPERM;
2132 vm_flags_clear(vma, VM_MAYWRITE);
2133
2134 if (!dev->mdev->clock_info)
2135 return -EOPNOTSUPP;
2136
2137 return vm_insert_page(vma, vma->vm_start,
2138 virt_to_page(dev->mdev->clock_info));
2139 }
2140
mlx5_ib_mmap_free(struct rdma_user_mmap_entry * entry)2141 static void mlx5_ib_mmap_free(struct rdma_user_mmap_entry *entry)
2142 {
2143 struct mlx5_user_mmap_entry *mentry = to_mmmap(entry);
2144 struct mlx5_ib_dev *dev = to_mdev(entry->ucontext->device);
2145 struct mlx5_var_table *var_table = &dev->var_table;
2146 struct mlx5_ib_ucontext *context = to_mucontext(entry->ucontext);
2147
2148 switch (mentry->mmap_flag) {
2149 case MLX5_IB_MMAP_TYPE_MEMIC:
2150 case MLX5_IB_MMAP_TYPE_MEMIC_OP:
2151 mlx5_ib_dm_mmap_free(dev, mentry);
2152 break;
2153 case MLX5_IB_MMAP_TYPE_VAR:
2154 mutex_lock(&var_table->bitmap_lock);
2155 clear_bit(mentry->page_idx, var_table->bitmap);
2156 mutex_unlock(&var_table->bitmap_lock);
2157 kfree(mentry);
2158 break;
2159 case MLX5_IB_MMAP_TYPE_UAR_WC:
2160 case MLX5_IB_MMAP_TYPE_UAR_NC:
2161 mlx5_cmd_uar_dealloc(dev->mdev, mentry->page_idx,
2162 context->devx_uid);
2163 kfree(mentry);
2164 break;
2165 default:
2166 WARN_ON(true);
2167 }
2168 }
2169
uar_mmap(struct mlx5_ib_dev * dev,enum mlx5_ib_mmap_cmd cmd,struct vm_area_struct * vma,struct mlx5_ib_ucontext * context)2170 static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd,
2171 struct vm_area_struct *vma,
2172 struct mlx5_ib_ucontext *context)
2173 {
2174 struct mlx5_bfreg_info *bfregi = &context->bfregi;
2175 int err;
2176 unsigned long idx;
2177 phys_addr_t pfn;
2178 pgprot_t prot;
2179 u32 bfreg_dyn_idx = 0;
2180 u32 uar_index;
2181 int dyn_uar = (cmd == MLX5_IB_MMAP_ALLOC_WC);
2182 int max_valid_idx = dyn_uar ? bfregi->num_sys_pages :
2183 bfregi->num_static_sys_pages;
2184
2185 if (bfregi->lib_uar_dyn)
2186 return -EINVAL;
2187
2188 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2189 return -EINVAL;
2190
2191 if (dyn_uar)
2192 idx = get_extended_index(vma->vm_pgoff) + bfregi->num_static_sys_pages;
2193 else
2194 idx = get_index(vma->vm_pgoff);
2195
2196 if (idx >= max_valid_idx) {
2197 mlx5_ib_warn(dev, "invalid uar index %lu, max=%d\n",
2198 idx, max_valid_idx);
2199 return -EINVAL;
2200 }
2201
2202 switch (cmd) {
2203 case MLX5_IB_MMAP_WC_PAGE:
2204 case MLX5_IB_MMAP_ALLOC_WC:
2205 case MLX5_IB_MMAP_REGULAR_PAGE:
2206 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */
2207 prot = pgprot_writecombine(vma->vm_page_prot);
2208 break;
2209 case MLX5_IB_MMAP_NC_PAGE:
2210 prot = pgprot_noncached(vma->vm_page_prot);
2211 break;
2212 default:
2213 return -EINVAL;
2214 }
2215
2216 if (dyn_uar) {
2217 int uars_per_page;
2218
2219 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k);
2220 bfreg_dyn_idx = idx * (uars_per_page * MLX5_NON_FP_BFREGS_PER_UAR);
2221 if (bfreg_dyn_idx >= bfregi->total_num_bfregs) {
2222 mlx5_ib_warn(dev, "invalid bfreg_dyn_idx %u, max=%u\n",
2223 bfreg_dyn_idx, bfregi->total_num_bfregs);
2224 return -EINVAL;
2225 }
2226
2227 mutex_lock(&bfregi->lock);
2228 /* Fail if uar already allocated, first bfreg index of each
2229 * page holds its count.
2230 */
2231 if (bfregi->count[bfreg_dyn_idx]) {
2232 mlx5_ib_warn(dev, "wrong offset, idx %lu is busy, bfregn=%u\n", idx, bfreg_dyn_idx);
2233 mutex_unlock(&bfregi->lock);
2234 return -EINVAL;
2235 }
2236
2237 bfregi->count[bfreg_dyn_idx]++;
2238 mutex_unlock(&bfregi->lock);
2239
2240 err = mlx5_cmd_uar_alloc(dev->mdev, &uar_index,
2241 context->devx_uid);
2242 if (err) {
2243 mlx5_ib_warn(dev, "UAR alloc failed\n");
2244 goto free_bfreg;
2245 }
2246 } else {
2247 uar_index = bfregi->sys_pages[idx];
2248 }
2249
2250 pfn = uar_index2pfn(dev, uar_index);
2251 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn);
2252
2253 err = rdma_user_mmap_io(&context->ibucontext, vma, pfn, PAGE_SIZE,
2254 prot, NULL);
2255 if (err) {
2256 mlx5_ib_err(dev,
2257 "rdma_user_mmap_io failed with error=%d, mmap_cmd=%s\n",
2258 err, mmap_cmd2str(cmd));
2259 goto err;
2260 }
2261
2262 if (dyn_uar)
2263 bfregi->sys_pages[idx] = uar_index;
2264 return 0;
2265
2266 err:
2267 if (!dyn_uar)
2268 return err;
2269
2270 mlx5_cmd_uar_dealloc(dev->mdev, idx, context->devx_uid);
2271
2272 free_bfreg:
2273 mlx5_ib_free_bfreg(dev, bfregi, bfreg_dyn_idx);
2274
2275 return err;
2276 }
2277
mlx5_vma_to_pgoff(struct vm_area_struct * vma)2278 static unsigned long mlx5_vma_to_pgoff(struct vm_area_struct *vma)
2279 {
2280 unsigned long idx;
2281 u8 command;
2282
2283 command = get_command(vma->vm_pgoff);
2284 idx = get_extended_index(vma->vm_pgoff);
2285
2286 return (command << 16 | idx);
2287 }
2288
mlx5_ib_mmap_offset(struct mlx5_ib_dev * dev,struct vm_area_struct * vma,struct ib_ucontext * ucontext)2289 static int mlx5_ib_mmap_offset(struct mlx5_ib_dev *dev,
2290 struct vm_area_struct *vma,
2291 struct ib_ucontext *ucontext)
2292 {
2293 struct mlx5_user_mmap_entry *mentry;
2294 struct rdma_user_mmap_entry *entry;
2295 unsigned long pgoff;
2296 pgprot_t prot;
2297 phys_addr_t pfn;
2298 int ret;
2299
2300 pgoff = mlx5_vma_to_pgoff(vma);
2301 entry = rdma_user_mmap_entry_get_pgoff(ucontext, pgoff);
2302 if (!entry)
2303 return -EINVAL;
2304
2305 mentry = to_mmmap(entry);
2306 pfn = (mentry->address >> PAGE_SHIFT);
2307 if (mentry->mmap_flag == MLX5_IB_MMAP_TYPE_VAR ||
2308 mentry->mmap_flag == MLX5_IB_MMAP_TYPE_UAR_NC)
2309 prot = pgprot_noncached(vma->vm_page_prot);
2310 else
2311 prot = pgprot_writecombine(vma->vm_page_prot);
2312 ret = rdma_user_mmap_io(ucontext, vma, pfn,
2313 entry->npages * PAGE_SIZE,
2314 prot,
2315 entry);
2316 rdma_user_mmap_entry_put(&mentry->rdma_entry);
2317 return ret;
2318 }
2319
mlx5_entry_to_mmap_offset(struct mlx5_user_mmap_entry * entry)2320 static u64 mlx5_entry_to_mmap_offset(struct mlx5_user_mmap_entry *entry)
2321 {
2322 u64 cmd = (entry->rdma_entry.start_pgoff >> 16) & 0xFFFF;
2323 u64 index = entry->rdma_entry.start_pgoff & 0xFFFF;
2324
2325 return (((index >> 8) << 16) | (cmd << MLX5_IB_MMAP_CMD_SHIFT) |
2326 (index & 0xFF)) << PAGE_SHIFT;
2327 }
2328
mlx5_ib_mmap(struct ib_ucontext * ibcontext,struct vm_area_struct * vma)2329 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
2330 {
2331 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
2332 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
2333 unsigned long command;
2334 phys_addr_t pfn;
2335
2336 command = get_command(vma->vm_pgoff);
2337 switch (command) {
2338 case MLX5_IB_MMAP_WC_PAGE:
2339 case MLX5_IB_MMAP_ALLOC_WC:
2340 if (!dev->wc_support)
2341 return -EPERM;
2342 fallthrough;
2343 case MLX5_IB_MMAP_NC_PAGE:
2344 case MLX5_IB_MMAP_REGULAR_PAGE:
2345 return uar_mmap(dev, command, vma, context);
2346
2347 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
2348 return -ENOSYS;
2349
2350 case MLX5_IB_MMAP_CORE_CLOCK:
2351 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2352 return -EINVAL;
2353
2354 if (vma->vm_flags & VM_WRITE)
2355 return -EPERM;
2356 vm_flags_clear(vma, VM_MAYWRITE);
2357
2358 /* Don't expose to user-space information it shouldn't have */
2359 if (PAGE_SIZE > 4096)
2360 return -EOPNOTSUPP;
2361
2362 pfn = (dev->mdev->iseg_base +
2363 offsetof(struct mlx5_init_seg, internal_timer_h)) >>
2364 PAGE_SHIFT;
2365 return rdma_user_mmap_io(&context->ibucontext, vma, pfn,
2366 PAGE_SIZE,
2367 pgprot_noncached(vma->vm_page_prot),
2368 NULL);
2369 case MLX5_IB_MMAP_CLOCK_INFO:
2370 return mlx5_ib_mmap_clock_info_page(dev, vma, context);
2371
2372 default:
2373 return mlx5_ib_mmap_offset(dev, vma, ibcontext);
2374 }
2375
2376 return 0;
2377 }
2378
mlx5_ib_alloc_pd(struct ib_pd * ibpd,struct ib_udata * udata)2379 static int mlx5_ib_alloc_pd(struct ib_pd *ibpd, struct ib_udata *udata)
2380 {
2381 struct mlx5_ib_pd *pd = to_mpd(ibpd);
2382 struct ib_device *ibdev = ibpd->device;
2383 struct mlx5_ib_alloc_pd_resp resp;
2384 int err;
2385 u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {};
2386 u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {};
2387 u16 uid = 0;
2388 struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context(
2389 udata, struct mlx5_ib_ucontext, ibucontext);
2390
2391 uid = context ? context->devx_uid : 0;
2392 MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD);
2393 MLX5_SET(alloc_pd_in, in, uid, uid);
2394 err = mlx5_cmd_exec_inout(to_mdev(ibdev)->mdev, alloc_pd, in, out);
2395 if (err)
2396 return err;
2397
2398 pd->pdn = MLX5_GET(alloc_pd_out, out, pd);
2399 pd->uid = uid;
2400 if (udata) {
2401 resp.pdn = pd->pdn;
2402 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
2403 mlx5_cmd_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn, uid);
2404 return -EFAULT;
2405 }
2406 }
2407
2408 return 0;
2409 }
2410
mlx5_ib_dealloc_pd(struct ib_pd * pd,struct ib_udata * udata)2411 static int mlx5_ib_dealloc_pd(struct ib_pd *pd, struct ib_udata *udata)
2412 {
2413 struct mlx5_ib_dev *mdev = to_mdev(pd->device);
2414 struct mlx5_ib_pd *mpd = to_mpd(pd);
2415
2416 return mlx5_cmd_dealloc_pd(mdev->mdev, mpd->pdn, mpd->uid);
2417 }
2418
mlx5_ib_mcg_attach(struct ib_qp * ibqp,union ib_gid * gid,u16 lid)2419 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
2420 {
2421 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2422 struct mlx5_ib_qp *mqp = to_mqp(ibqp);
2423 int err;
2424 u16 uid;
2425
2426 uid = ibqp->pd ?
2427 to_mpd(ibqp->pd)->uid : 0;
2428
2429 if (mqp->flags & IB_QP_CREATE_SOURCE_QPN) {
2430 mlx5_ib_dbg(dev, "Attaching a multi cast group to underlay QP is not supported\n");
2431 return -EOPNOTSUPP;
2432 }
2433
2434 err = mlx5_cmd_attach_mcg(dev->mdev, gid, ibqp->qp_num, uid);
2435 if (err)
2436 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
2437 ibqp->qp_num, gid->raw);
2438
2439 return err;
2440 }
2441
mlx5_ib_mcg_detach(struct ib_qp * ibqp,union ib_gid * gid,u16 lid)2442 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
2443 {
2444 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2445 int err;
2446 u16 uid;
2447
2448 uid = ibqp->pd ?
2449 to_mpd(ibqp->pd)->uid : 0;
2450 err = mlx5_cmd_detach_mcg(dev->mdev, gid, ibqp->qp_num, uid);
2451 if (err)
2452 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
2453 ibqp->qp_num, gid->raw);
2454
2455 return err;
2456 }
2457
init_node_data(struct mlx5_ib_dev * dev)2458 static int init_node_data(struct mlx5_ib_dev *dev)
2459 {
2460 int err;
2461
2462 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc);
2463 if (err)
2464 return err;
2465
2466 dev->mdev->rev_id = dev->mdev->pdev->revision;
2467
2468 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid);
2469 }
2470
fw_pages_show(struct device * device,struct device_attribute * attr,char * buf)2471 static ssize_t fw_pages_show(struct device *device,
2472 struct device_attribute *attr, char *buf)
2473 {
2474 struct mlx5_ib_dev *dev =
2475 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
2476
2477 return sysfs_emit(buf, "%d\n", dev->mdev->priv.fw_pages);
2478 }
2479 static DEVICE_ATTR_RO(fw_pages);
2480
reg_pages_show(struct device * device,struct device_attribute * attr,char * buf)2481 static ssize_t reg_pages_show(struct device *device,
2482 struct device_attribute *attr, char *buf)
2483 {
2484 struct mlx5_ib_dev *dev =
2485 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
2486
2487 return sysfs_emit(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
2488 }
2489 static DEVICE_ATTR_RO(reg_pages);
2490
hca_type_show(struct device * device,struct device_attribute * attr,char * buf)2491 static ssize_t hca_type_show(struct device *device,
2492 struct device_attribute *attr, char *buf)
2493 {
2494 struct mlx5_ib_dev *dev =
2495 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
2496
2497 return sysfs_emit(buf, "MT%d\n", dev->mdev->pdev->device);
2498 }
2499 static DEVICE_ATTR_RO(hca_type);
2500
hw_rev_show(struct device * device,struct device_attribute * attr,char * buf)2501 static ssize_t hw_rev_show(struct device *device,
2502 struct device_attribute *attr, char *buf)
2503 {
2504 struct mlx5_ib_dev *dev =
2505 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
2506
2507 return sysfs_emit(buf, "%x\n", dev->mdev->rev_id);
2508 }
2509 static DEVICE_ATTR_RO(hw_rev);
2510
board_id_show(struct device * device,struct device_attribute * attr,char * buf)2511 static ssize_t board_id_show(struct device *device,
2512 struct device_attribute *attr, char *buf)
2513 {
2514 struct mlx5_ib_dev *dev =
2515 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
2516
2517 return sysfs_emit(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
2518 dev->mdev->board_id);
2519 }
2520 static DEVICE_ATTR_RO(board_id);
2521
2522 static struct attribute *mlx5_class_attributes[] = {
2523 &dev_attr_hw_rev.attr,
2524 &dev_attr_hca_type.attr,
2525 &dev_attr_board_id.attr,
2526 &dev_attr_fw_pages.attr,
2527 &dev_attr_reg_pages.attr,
2528 NULL,
2529 };
2530
2531 static const struct attribute_group mlx5_attr_group = {
2532 .attrs = mlx5_class_attributes,
2533 };
2534
pkey_change_handler(struct work_struct * work)2535 static void pkey_change_handler(struct work_struct *work)
2536 {
2537 struct mlx5_ib_port_resources *ports =
2538 container_of(work, struct mlx5_ib_port_resources,
2539 pkey_change_work);
2540
2541 if (!ports->gsi)
2542 /*
2543 * We got this event before device was fully configured
2544 * and MAD registration code wasn't called/finished yet.
2545 */
2546 return;
2547
2548 mlx5_ib_gsi_pkey_change(ports->gsi);
2549 }
2550
mlx5_ib_handle_internal_error(struct mlx5_ib_dev * ibdev)2551 static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev)
2552 {
2553 struct mlx5_ib_qp *mqp;
2554 struct mlx5_ib_cq *send_mcq, *recv_mcq;
2555 struct mlx5_core_cq *mcq;
2556 struct list_head cq_armed_list;
2557 unsigned long flags_qp;
2558 unsigned long flags_cq;
2559 unsigned long flags;
2560
2561 INIT_LIST_HEAD(&cq_armed_list);
2562
2563 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
2564 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
2565 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
2566 spin_lock_irqsave(&mqp->sq.lock, flags_qp);
2567 if (mqp->sq.tail != mqp->sq.head) {
2568 send_mcq = to_mcq(mqp->ibqp.send_cq);
2569 spin_lock_irqsave(&send_mcq->lock, flags_cq);
2570 if (send_mcq->mcq.comp &&
2571 mqp->ibqp.send_cq->comp_handler) {
2572 if (!send_mcq->mcq.reset_notify_added) {
2573 send_mcq->mcq.reset_notify_added = 1;
2574 list_add_tail(&send_mcq->mcq.reset_notify,
2575 &cq_armed_list);
2576 }
2577 }
2578 spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
2579 }
2580 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
2581 spin_lock_irqsave(&mqp->rq.lock, flags_qp);
2582 /* no handling is needed for SRQ */
2583 if (!mqp->ibqp.srq) {
2584 if (mqp->rq.tail != mqp->rq.head) {
2585 recv_mcq = to_mcq(mqp->ibqp.recv_cq);
2586 spin_lock_irqsave(&recv_mcq->lock, flags_cq);
2587 if (recv_mcq->mcq.comp &&
2588 mqp->ibqp.recv_cq->comp_handler) {
2589 if (!recv_mcq->mcq.reset_notify_added) {
2590 recv_mcq->mcq.reset_notify_added = 1;
2591 list_add_tail(&recv_mcq->mcq.reset_notify,
2592 &cq_armed_list);
2593 }
2594 }
2595 spin_unlock_irqrestore(&recv_mcq->lock,
2596 flags_cq);
2597 }
2598 }
2599 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
2600 }
2601 /*At that point all inflight post send were put to be executed as of we
2602 * lock/unlock above locks Now need to arm all involved CQs.
2603 */
2604 list_for_each_entry(mcq, &cq_armed_list, reset_notify) {
2605 mcq->comp(mcq, NULL);
2606 }
2607 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
2608 }
2609
delay_drop_handler(struct work_struct * work)2610 static void delay_drop_handler(struct work_struct *work)
2611 {
2612 int err;
2613 struct mlx5_ib_delay_drop *delay_drop =
2614 container_of(work, struct mlx5_ib_delay_drop,
2615 delay_drop_work);
2616
2617 atomic_inc(&delay_drop->events_cnt);
2618
2619 mutex_lock(&delay_drop->lock);
2620 err = mlx5_core_set_delay_drop(delay_drop->dev, delay_drop->timeout);
2621 if (err) {
2622 mlx5_ib_warn(delay_drop->dev, "Failed to set delay drop, timeout=%u\n",
2623 delay_drop->timeout);
2624 delay_drop->activate = false;
2625 }
2626 mutex_unlock(&delay_drop->lock);
2627 }
2628
handle_general_event(struct mlx5_ib_dev * ibdev,struct mlx5_eqe * eqe,struct ib_event * ibev)2629 static void handle_general_event(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe,
2630 struct ib_event *ibev)
2631 {
2632 u32 port = (eqe->data.port.port >> 4) & 0xf;
2633
2634 switch (eqe->sub_type) {
2635 case MLX5_GENERAL_SUBTYPE_DELAY_DROP_TIMEOUT:
2636 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
2637 IB_LINK_LAYER_ETHERNET)
2638 schedule_work(&ibdev->delay_drop.delay_drop_work);
2639 break;
2640 default: /* do nothing */
2641 return;
2642 }
2643 }
2644
handle_port_change(struct mlx5_ib_dev * ibdev,struct mlx5_eqe * eqe,struct ib_event * ibev)2645 static int handle_port_change(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe,
2646 struct ib_event *ibev)
2647 {
2648 u32 port = (eqe->data.port.port >> 4) & 0xf;
2649
2650 ibev->element.port_num = port;
2651
2652 switch (eqe->sub_type) {
2653 case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
2654 case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
2655 case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED:
2656 /* In RoCE, port up/down events are handled in
2657 * mlx5_netdev_event().
2658 */
2659 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
2660 IB_LINK_LAYER_ETHERNET)
2661 return -EINVAL;
2662
2663 ibev->event = (eqe->sub_type == MLX5_PORT_CHANGE_SUBTYPE_ACTIVE) ?
2664 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
2665 break;
2666
2667 case MLX5_PORT_CHANGE_SUBTYPE_LID:
2668 ibev->event = IB_EVENT_LID_CHANGE;
2669 break;
2670
2671 case MLX5_PORT_CHANGE_SUBTYPE_PKEY:
2672 ibev->event = IB_EVENT_PKEY_CHANGE;
2673 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work);
2674 break;
2675
2676 case MLX5_PORT_CHANGE_SUBTYPE_GUID:
2677 ibev->event = IB_EVENT_GID_CHANGE;
2678 break;
2679
2680 case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG:
2681 ibev->event = IB_EVENT_CLIENT_REREGISTER;
2682 break;
2683 default:
2684 return -EINVAL;
2685 }
2686
2687 return 0;
2688 }
2689
mlx5_ib_handle_event(struct work_struct * _work)2690 static void mlx5_ib_handle_event(struct work_struct *_work)
2691 {
2692 struct mlx5_ib_event_work *work =
2693 container_of(_work, struct mlx5_ib_event_work, work);
2694 struct mlx5_ib_dev *ibdev;
2695 struct ib_event ibev;
2696 bool fatal = false;
2697
2698 if (work->is_slave) {
2699 ibdev = mlx5_ib_get_ibdev_from_mpi(work->mpi);
2700 if (!ibdev)
2701 goto out;
2702 } else {
2703 ibdev = work->dev;
2704 }
2705
2706 switch (work->event) {
2707 case MLX5_DEV_EVENT_SYS_ERROR:
2708 ibev.event = IB_EVENT_DEVICE_FATAL;
2709 mlx5_ib_handle_internal_error(ibdev);
2710 ibev.element.port_num = (u8)(unsigned long)work->param;
2711 fatal = true;
2712 break;
2713 case MLX5_EVENT_TYPE_PORT_CHANGE:
2714 if (handle_port_change(ibdev, work->param, &ibev))
2715 goto out;
2716 break;
2717 case MLX5_EVENT_TYPE_GENERAL_EVENT:
2718 handle_general_event(ibdev, work->param, &ibev);
2719 fallthrough;
2720 default:
2721 goto out;
2722 }
2723
2724 ibev.device = &ibdev->ib_dev;
2725
2726 if (!rdma_is_port_valid(&ibdev->ib_dev, ibev.element.port_num)) {
2727 mlx5_ib_warn(ibdev, "warning: event on port %d\n", ibev.element.port_num);
2728 goto out;
2729 }
2730
2731 if (ibdev->ib_active)
2732 ib_dispatch_event(&ibev);
2733
2734 if (fatal)
2735 ibdev->ib_active = false;
2736 out:
2737 kfree(work);
2738 }
2739
mlx5_ib_event(struct notifier_block * nb,unsigned long event,void * param)2740 static int mlx5_ib_event(struct notifier_block *nb,
2741 unsigned long event, void *param)
2742 {
2743 struct mlx5_ib_event_work *work;
2744
2745 work = kmalloc(sizeof(*work), GFP_ATOMIC);
2746 if (!work)
2747 return NOTIFY_DONE;
2748
2749 INIT_WORK(&work->work, mlx5_ib_handle_event);
2750 work->dev = container_of(nb, struct mlx5_ib_dev, mdev_events);
2751 work->is_slave = false;
2752 work->param = param;
2753 work->event = event;
2754
2755 queue_work(mlx5_ib_event_wq, &work->work);
2756
2757 return NOTIFY_OK;
2758 }
2759
mlx5_ib_event_slave_port(struct notifier_block * nb,unsigned long event,void * param)2760 static int mlx5_ib_event_slave_port(struct notifier_block *nb,
2761 unsigned long event, void *param)
2762 {
2763 struct mlx5_ib_event_work *work;
2764
2765 work = kmalloc(sizeof(*work), GFP_ATOMIC);
2766 if (!work)
2767 return NOTIFY_DONE;
2768
2769 INIT_WORK(&work->work, mlx5_ib_handle_event);
2770 work->mpi = container_of(nb, struct mlx5_ib_multiport_info, mdev_events);
2771 work->is_slave = true;
2772 work->param = param;
2773 work->event = event;
2774 queue_work(mlx5_ib_event_wq, &work->work);
2775
2776 return NOTIFY_OK;
2777 }
2778
set_has_smi_cap(struct mlx5_ib_dev * dev)2779 static int set_has_smi_cap(struct mlx5_ib_dev *dev)
2780 {
2781 struct mlx5_hca_vport_context vport_ctx;
2782 int err;
2783 int port;
2784
2785 if (MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_IB)
2786 return 0;
2787
2788 for (port = 1; port <= dev->num_ports; port++) {
2789 if (!MLX5_CAP_GEN(dev->mdev, ib_virt)) {
2790 dev->port_caps[port - 1].has_smi = true;
2791 continue;
2792 }
2793 err = mlx5_query_hca_vport_context(dev->mdev, 0, port, 0,
2794 &vport_ctx);
2795 if (err) {
2796 mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n",
2797 port, err);
2798 return err;
2799 }
2800 dev->port_caps[port - 1].has_smi = vport_ctx.has_smi;
2801 }
2802
2803 return 0;
2804 }
2805
get_ext_port_caps(struct mlx5_ib_dev * dev)2806 static void get_ext_port_caps(struct mlx5_ib_dev *dev)
2807 {
2808 unsigned int port;
2809
2810 rdma_for_each_port (&dev->ib_dev, port)
2811 mlx5_query_ext_port_caps(dev, port);
2812 }
2813
mlx5_get_umr_fence(u8 umr_fence_cap)2814 static u8 mlx5_get_umr_fence(u8 umr_fence_cap)
2815 {
2816 switch (umr_fence_cap) {
2817 case MLX5_CAP_UMR_FENCE_NONE:
2818 return MLX5_FENCE_MODE_NONE;
2819 case MLX5_CAP_UMR_FENCE_SMALL:
2820 return MLX5_FENCE_MODE_INITIATOR_SMALL;
2821 default:
2822 return MLX5_FENCE_MODE_STRONG_ORDERING;
2823 }
2824 }
2825
mlx5_ib_dev_res_cq_init(struct mlx5_ib_dev * dev)2826 int mlx5_ib_dev_res_cq_init(struct mlx5_ib_dev *dev)
2827 {
2828 struct mlx5_ib_resources *devr = &dev->devr;
2829 struct ib_cq_init_attr cq_attr = {.cqe = 1};
2830 struct ib_device *ibdev;
2831 struct ib_pd *pd;
2832 struct ib_cq *cq;
2833 int ret = 0;
2834
2835
2836 /*
2837 * devr->c0 is set once, never changed until device unload.
2838 * Avoid taking the mutex if initialization is already done.
2839 */
2840 if (devr->c0)
2841 return 0;
2842
2843 mutex_lock(&devr->cq_lock);
2844 if (devr->c0)
2845 goto unlock;
2846
2847 ibdev = &dev->ib_dev;
2848 pd = ib_alloc_pd(ibdev, 0);
2849 if (IS_ERR(pd)) {
2850 ret = PTR_ERR(pd);
2851 mlx5_ib_err(dev, "Couldn't allocate PD for res init, err=%d\n", ret);
2852 goto unlock;
2853 }
2854
2855 cq = ib_create_cq(ibdev, NULL, NULL, NULL, &cq_attr);
2856 if (IS_ERR(cq)) {
2857 ret = PTR_ERR(cq);
2858 mlx5_ib_err(dev, "Couldn't create CQ for res init, err=%d\n", ret);
2859 ib_dealloc_pd(pd);
2860 goto unlock;
2861 }
2862
2863 devr->p0 = pd;
2864 devr->c0 = cq;
2865
2866 unlock:
2867 mutex_unlock(&devr->cq_lock);
2868 return ret;
2869 }
2870
mlx5_ib_dev_res_srq_init(struct mlx5_ib_dev * dev)2871 int mlx5_ib_dev_res_srq_init(struct mlx5_ib_dev *dev)
2872 {
2873 struct mlx5_ib_resources *devr = &dev->devr;
2874 struct ib_srq_init_attr attr;
2875 struct ib_srq *s0, *s1;
2876 int ret = 0;
2877
2878 /*
2879 * devr->s1 is set once, never changed until device unload.
2880 * Avoid taking the mutex if initialization is already done.
2881 */
2882 if (devr->s1)
2883 return 0;
2884
2885 mutex_lock(&devr->srq_lock);
2886 if (devr->s1)
2887 goto unlock;
2888
2889 ret = mlx5_ib_dev_res_cq_init(dev);
2890 if (ret)
2891 goto unlock;
2892
2893 memset(&attr, 0, sizeof(attr));
2894 attr.attr.max_sge = 1;
2895 attr.attr.max_wr = 1;
2896 attr.srq_type = IB_SRQT_XRC;
2897 attr.ext.cq = devr->c0;
2898
2899 s0 = ib_create_srq(devr->p0, &attr);
2900 if (IS_ERR(s0)) {
2901 ret = PTR_ERR(s0);
2902 mlx5_ib_err(dev, "Couldn't create SRQ 0 for res init, err=%d\n", ret);
2903 goto unlock;
2904 }
2905
2906 memset(&attr, 0, sizeof(attr));
2907 attr.attr.max_sge = 1;
2908 attr.attr.max_wr = 1;
2909 attr.srq_type = IB_SRQT_BASIC;
2910
2911 s1 = ib_create_srq(devr->p0, &attr);
2912 if (IS_ERR(s1)) {
2913 ret = PTR_ERR(s1);
2914 mlx5_ib_err(dev, "Couldn't create SRQ 1 for res init, err=%d\n", ret);
2915 ib_destroy_srq(s0);
2916 }
2917
2918 devr->s0 = s0;
2919 devr->s1 = s1;
2920
2921 unlock:
2922 mutex_unlock(&devr->srq_lock);
2923 return ret;
2924 }
2925
mlx5_ib_dev_res_init(struct mlx5_ib_dev * dev)2926 static int mlx5_ib_dev_res_init(struct mlx5_ib_dev *dev)
2927 {
2928 struct mlx5_ib_resources *devr = &dev->devr;
2929 int ret;
2930
2931 if (!MLX5_CAP_GEN(dev->mdev, xrc))
2932 return -EOPNOTSUPP;
2933
2934 ret = mlx5_cmd_xrcd_alloc(dev->mdev, &devr->xrcdn0, 0);
2935 if (ret)
2936 return ret;
2937
2938 ret = mlx5_cmd_xrcd_alloc(dev->mdev, &devr->xrcdn1, 0);
2939 if (ret) {
2940 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn0, 0);
2941 return ret;
2942 }
2943
2944 mutex_init(&devr->cq_lock);
2945 mutex_init(&devr->srq_lock);
2946
2947 return 0;
2948 }
2949
mlx5_ib_dev_res_cleanup(struct mlx5_ib_dev * dev)2950 static void mlx5_ib_dev_res_cleanup(struct mlx5_ib_dev *dev)
2951 {
2952 struct mlx5_ib_resources *devr = &dev->devr;
2953
2954 /* After s0/s1 init, they are not unset during the device lifetime. */
2955 if (devr->s1) {
2956 ib_destroy_srq(devr->s1);
2957 ib_destroy_srq(devr->s0);
2958 }
2959 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn1, 0);
2960 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn0, 0);
2961 /* After p0/c0 init, they are not unset during the device lifetime. */
2962 if (devr->c0) {
2963 ib_destroy_cq(devr->c0);
2964 ib_dealloc_pd(devr->p0);
2965 }
2966 mutex_destroy(&devr->cq_lock);
2967 mutex_destroy(&devr->srq_lock);
2968 }
2969
get_core_cap_flags(struct ib_device * ibdev,struct mlx5_hca_vport_context * rep)2970 static u32 get_core_cap_flags(struct ib_device *ibdev,
2971 struct mlx5_hca_vport_context *rep)
2972 {
2973 struct mlx5_ib_dev *dev = to_mdev(ibdev);
2974 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1);
2975 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type);
2976 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version);
2977 bool raw_support = !mlx5_core_mp_enabled(dev->mdev);
2978 u32 ret = 0;
2979
2980 if (rep->grh_required)
2981 ret |= RDMA_CORE_CAP_IB_GRH_REQUIRED;
2982
2983 if (ll == IB_LINK_LAYER_INFINIBAND)
2984 return ret | RDMA_CORE_PORT_IBA_IB;
2985
2986 if (raw_support)
2987 ret |= RDMA_CORE_PORT_RAW_PACKET;
2988
2989 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP))
2990 return ret;
2991
2992 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP))
2993 return ret;
2994
2995 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP)
2996 ret |= RDMA_CORE_PORT_IBA_ROCE;
2997
2998 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP)
2999 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
3000
3001 return ret;
3002 }
3003
mlx5_port_immutable(struct ib_device * ibdev,u32 port_num,struct ib_port_immutable * immutable)3004 static int mlx5_port_immutable(struct ib_device *ibdev, u32 port_num,
3005 struct ib_port_immutable *immutable)
3006 {
3007 struct ib_port_attr attr;
3008 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3009 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num);
3010 struct mlx5_hca_vport_context rep = {0};
3011 int err;
3012
3013 err = ib_query_port(ibdev, port_num, &attr);
3014 if (err)
3015 return err;
3016
3017 if (ll == IB_LINK_LAYER_INFINIBAND) {
3018 err = mlx5_query_hca_vport_context(dev->mdev, 0, port_num, 0,
3019 &rep);
3020 if (err)
3021 return err;
3022 }
3023
3024 immutable->pkey_tbl_len = attr.pkey_tbl_len;
3025 immutable->gid_tbl_len = attr.gid_tbl_len;
3026 immutable->core_cap_flags = get_core_cap_flags(ibdev, &rep);
3027 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
3028
3029 return 0;
3030 }
3031
mlx5_port_rep_immutable(struct ib_device * ibdev,u32 port_num,struct ib_port_immutable * immutable)3032 static int mlx5_port_rep_immutable(struct ib_device *ibdev, u32 port_num,
3033 struct ib_port_immutable *immutable)
3034 {
3035 struct ib_port_attr attr;
3036 int err;
3037
3038 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET;
3039
3040 err = ib_query_port(ibdev, port_num, &attr);
3041 if (err)
3042 return err;
3043
3044 immutable->pkey_tbl_len = attr.pkey_tbl_len;
3045 immutable->gid_tbl_len = attr.gid_tbl_len;
3046 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET;
3047
3048 return 0;
3049 }
3050
get_dev_fw_str(struct ib_device * ibdev,char * str)3051 static void get_dev_fw_str(struct ib_device *ibdev, char *str)
3052 {
3053 struct mlx5_ib_dev *dev =
3054 container_of(ibdev, struct mlx5_ib_dev, ib_dev);
3055 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%04d",
3056 fw_rev_maj(dev->mdev), fw_rev_min(dev->mdev),
3057 fw_rev_sub(dev->mdev));
3058 }
3059
mlx5_eth_lag_init(struct mlx5_ib_dev * dev)3060 static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev)
3061 {
3062 struct mlx5_core_dev *mdev = dev->mdev;
3063 struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev,
3064 MLX5_FLOW_NAMESPACE_LAG);
3065 struct mlx5_flow_table *ft;
3066 int err;
3067
3068 if (!ns || !mlx5_lag_is_active(mdev))
3069 return 0;
3070
3071 err = mlx5_cmd_create_vport_lag(mdev);
3072 if (err)
3073 return err;
3074
3075 ft = mlx5_create_lag_demux_flow_table(ns, 0, 0);
3076 if (IS_ERR(ft)) {
3077 err = PTR_ERR(ft);
3078 goto err_destroy_vport_lag;
3079 }
3080
3081 dev->flow_db->lag_demux_ft = ft;
3082 dev->lag_ports = mlx5_lag_get_num_ports(mdev);
3083 dev->lag_active = true;
3084 return 0;
3085
3086 err_destroy_vport_lag:
3087 mlx5_cmd_destroy_vport_lag(mdev);
3088 return err;
3089 }
3090
mlx5_eth_lag_cleanup(struct mlx5_ib_dev * dev)3091 static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev)
3092 {
3093 struct mlx5_core_dev *mdev = dev->mdev;
3094
3095 if (dev->lag_active) {
3096 dev->lag_active = false;
3097
3098 mlx5_destroy_flow_table(dev->flow_db->lag_demux_ft);
3099 dev->flow_db->lag_demux_ft = NULL;
3100
3101 mlx5_cmd_destroy_vport_lag(mdev);
3102 }
3103 }
3104
mlx5_netdev_notifier_register(struct mlx5_roce * roce,struct net_device * netdev)3105 static void mlx5_netdev_notifier_register(struct mlx5_roce *roce,
3106 struct net_device *netdev)
3107 {
3108 int err;
3109
3110 if (roce->tracking_netdev)
3111 return;
3112 roce->tracking_netdev = netdev;
3113 roce->nb.notifier_call = mlx5_netdev_event;
3114 err = register_netdevice_notifier_dev_net(netdev, &roce->nb, &roce->nn);
3115 WARN_ON(err);
3116 }
3117
mlx5_netdev_notifier_unregister(struct mlx5_roce * roce)3118 static void mlx5_netdev_notifier_unregister(struct mlx5_roce *roce)
3119 {
3120 if (!roce->tracking_netdev)
3121 return;
3122 unregister_netdevice_notifier_dev_net(roce->tracking_netdev, &roce->nb,
3123 &roce->nn);
3124 roce->tracking_netdev = NULL;
3125 }
3126
mlx5e_mdev_notifier_event(struct notifier_block * nb,unsigned long event,void * data)3127 static int mlx5e_mdev_notifier_event(struct notifier_block *nb,
3128 unsigned long event, void *data)
3129 {
3130 struct mlx5_roce *roce = container_of(nb, struct mlx5_roce, mdev_nb);
3131 struct net_device *netdev = data;
3132
3133 switch (event) {
3134 case MLX5_DRIVER_EVENT_UPLINK_NETDEV:
3135 if (netdev)
3136 mlx5_netdev_notifier_register(roce, netdev);
3137 else
3138 mlx5_netdev_notifier_unregister(roce);
3139 break;
3140 default:
3141 return NOTIFY_DONE;
3142 }
3143
3144 return NOTIFY_OK;
3145 }
3146
mlx5_mdev_netdev_track(struct mlx5_ib_dev * dev,u32 port_num)3147 static void mlx5_mdev_netdev_track(struct mlx5_ib_dev *dev, u32 port_num)
3148 {
3149 struct mlx5_roce *roce = &dev->port[port_num].roce;
3150
3151 roce->mdev_nb.notifier_call = mlx5e_mdev_notifier_event;
3152 mlx5_blocking_notifier_register(dev->mdev, &roce->mdev_nb);
3153 mlx5_core_uplink_netdev_event_replay(dev->mdev);
3154 }
3155
mlx5_mdev_netdev_untrack(struct mlx5_ib_dev * dev,u32 port_num)3156 static void mlx5_mdev_netdev_untrack(struct mlx5_ib_dev *dev, u32 port_num)
3157 {
3158 struct mlx5_roce *roce = &dev->port[port_num].roce;
3159
3160 mlx5_blocking_notifier_unregister(dev->mdev, &roce->mdev_nb);
3161 mlx5_netdev_notifier_unregister(roce);
3162 }
3163
mlx5_enable_eth(struct mlx5_ib_dev * dev)3164 static int mlx5_enable_eth(struct mlx5_ib_dev *dev)
3165 {
3166 int err;
3167
3168 if (!dev->is_rep && dev->profile != &raw_eth_profile) {
3169 err = mlx5_nic_vport_enable_roce(dev->mdev);
3170 if (err)
3171 return err;
3172 }
3173
3174 err = mlx5_eth_lag_init(dev);
3175 if (err)
3176 goto err_disable_roce;
3177
3178 return 0;
3179
3180 err_disable_roce:
3181 if (!dev->is_rep && dev->profile != &raw_eth_profile)
3182 mlx5_nic_vport_disable_roce(dev->mdev);
3183
3184 return err;
3185 }
3186
mlx5_disable_eth(struct mlx5_ib_dev * dev)3187 static void mlx5_disable_eth(struct mlx5_ib_dev *dev)
3188 {
3189 mlx5_eth_lag_cleanup(dev);
3190 if (!dev->is_rep && dev->profile != &raw_eth_profile)
3191 mlx5_nic_vport_disable_roce(dev->mdev);
3192 }
3193
mlx5_ib_rn_get_params(struct ib_device * device,u32 port_num,enum rdma_netdev_t type,struct rdma_netdev_alloc_params * params)3194 static int mlx5_ib_rn_get_params(struct ib_device *device, u32 port_num,
3195 enum rdma_netdev_t type,
3196 struct rdma_netdev_alloc_params *params)
3197 {
3198 if (type != RDMA_NETDEV_IPOIB)
3199 return -EOPNOTSUPP;
3200
3201 return mlx5_rdma_rn_get_params(to_mdev(device)->mdev, device, params);
3202 }
3203
delay_drop_timeout_read(struct file * filp,char __user * buf,size_t count,loff_t * pos)3204 static ssize_t delay_drop_timeout_read(struct file *filp, char __user *buf,
3205 size_t count, loff_t *pos)
3206 {
3207 struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
3208 char lbuf[20];
3209 int len;
3210
3211 len = snprintf(lbuf, sizeof(lbuf), "%u\n", delay_drop->timeout);
3212 return simple_read_from_buffer(buf, count, pos, lbuf, len);
3213 }
3214
delay_drop_timeout_write(struct file * filp,const char __user * buf,size_t count,loff_t * pos)3215 static ssize_t delay_drop_timeout_write(struct file *filp, const char __user *buf,
3216 size_t count, loff_t *pos)
3217 {
3218 struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
3219 u32 timeout;
3220 u32 var;
3221
3222 if (kstrtouint_from_user(buf, count, 0, &var))
3223 return -EFAULT;
3224
3225 timeout = min_t(u32, roundup(var, 100), MLX5_MAX_DELAY_DROP_TIMEOUT_MS *
3226 1000);
3227 if (timeout != var)
3228 mlx5_ib_dbg(delay_drop->dev, "Round delay drop timeout to %u usec\n",
3229 timeout);
3230
3231 delay_drop->timeout = timeout;
3232
3233 return count;
3234 }
3235
3236 static const struct file_operations fops_delay_drop_timeout = {
3237 .owner = THIS_MODULE,
3238 .open = simple_open,
3239 .write = delay_drop_timeout_write,
3240 .read = delay_drop_timeout_read,
3241 };
3242
mlx5_ib_unbind_slave_port(struct mlx5_ib_dev * ibdev,struct mlx5_ib_multiport_info * mpi)3243 static void mlx5_ib_unbind_slave_port(struct mlx5_ib_dev *ibdev,
3244 struct mlx5_ib_multiport_info *mpi)
3245 {
3246 u32 port_num = mlx5_core_native_port_num(mpi->mdev) - 1;
3247 struct mlx5_ib_port *port = &ibdev->port[port_num];
3248 int comps;
3249 int err;
3250 int i;
3251
3252 lockdep_assert_held(&mlx5_ib_multiport_mutex);
3253
3254 mlx5_ib_disable_lb_mp(ibdev->mdev, mpi->mdev);
3255
3256 mlx5_core_mp_event_replay(ibdev->mdev,
3257 MLX5_DRIVER_EVENT_AFFILIATION_REMOVED,
3258 NULL);
3259 mlx5_core_mp_event_replay(mpi->mdev,
3260 MLX5_DRIVER_EVENT_AFFILIATION_REMOVED,
3261 NULL);
3262
3263 mlx5_ib_cleanup_cong_debugfs(ibdev, port_num);
3264
3265 spin_lock(&port->mp.mpi_lock);
3266 if (!mpi->ibdev) {
3267 spin_unlock(&port->mp.mpi_lock);
3268 return;
3269 }
3270
3271 mpi->ibdev = NULL;
3272
3273 spin_unlock(&port->mp.mpi_lock);
3274 if (mpi->mdev_events.notifier_call)
3275 mlx5_notifier_unregister(mpi->mdev, &mpi->mdev_events);
3276 mpi->mdev_events.notifier_call = NULL;
3277 mlx5_mdev_netdev_untrack(ibdev, port_num);
3278 spin_lock(&port->mp.mpi_lock);
3279
3280 comps = mpi->mdev_refcnt;
3281 if (comps) {
3282 mpi->unaffiliate = true;
3283 init_completion(&mpi->unref_comp);
3284 spin_unlock(&port->mp.mpi_lock);
3285
3286 for (i = 0; i < comps; i++)
3287 wait_for_completion(&mpi->unref_comp);
3288
3289 spin_lock(&port->mp.mpi_lock);
3290 mpi->unaffiliate = false;
3291 }
3292
3293 port->mp.mpi = NULL;
3294
3295 spin_unlock(&port->mp.mpi_lock);
3296
3297 err = mlx5_nic_vport_unaffiliate_multiport(mpi->mdev);
3298
3299 mlx5_ib_dbg(ibdev, "unaffiliated port %u\n", port_num + 1);
3300 /* Log an error, still needed to cleanup the pointers and add
3301 * it back to the list.
3302 */
3303 if (err)
3304 mlx5_ib_err(ibdev, "Failed to unaffiliate port %u\n",
3305 port_num + 1);
3306
3307 ibdev->port[port_num].roce.last_port_state = IB_PORT_DOWN;
3308 }
3309
mlx5_ib_bind_slave_port(struct mlx5_ib_dev * ibdev,struct mlx5_ib_multiport_info * mpi)3310 static bool mlx5_ib_bind_slave_port(struct mlx5_ib_dev *ibdev,
3311 struct mlx5_ib_multiport_info *mpi)
3312 {
3313 u32 port_num = mlx5_core_native_port_num(mpi->mdev) - 1;
3314 u64 key;
3315 int err;
3316
3317 lockdep_assert_held(&mlx5_ib_multiport_mutex);
3318
3319 spin_lock(&ibdev->port[port_num].mp.mpi_lock);
3320 if (ibdev->port[port_num].mp.mpi) {
3321 mlx5_ib_dbg(ibdev, "port %u already affiliated.\n",
3322 port_num + 1);
3323 spin_unlock(&ibdev->port[port_num].mp.mpi_lock);
3324 return false;
3325 }
3326
3327 ibdev->port[port_num].mp.mpi = mpi;
3328 mpi->ibdev = ibdev;
3329 mpi->mdev_events.notifier_call = NULL;
3330 spin_unlock(&ibdev->port[port_num].mp.mpi_lock);
3331
3332 err = mlx5_nic_vport_affiliate_multiport(ibdev->mdev, mpi->mdev);
3333 if (err)
3334 goto unbind;
3335
3336 mlx5_mdev_netdev_track(ibdev, port_num);
3337
3338 mpi->mdev_events.notifier_call = mlx5_ib_event_slave_port;
3339 mlx5_notifier_register(mpi->mdev, &mpi->mdev_events);
3340
3341 mlx5_ib_init_cong_debugfs(ibdev, port_num);
3342
3343 key = mpi->mdev->priv.adev_idx;
3344 mlx5_core_mp_event_replay(mpi->mdev,
3345 MLX5_DRIVER_EVENT_AFFILIATION_DONE,
3346 &key);
3347 mlx5_core_mp_event_replay(ibdev->mdev,
3348 MLX5_DRIVER_EVENT_AFFILIATION_DONE,
3349 &key);
3350
3351 err = mlx5_ib_enable_lb_mp(ibdev->mdev, mpi->mdev);
3352 if (err)
3353 goto unbind;
3354
3355 return true;
3356
3357 unbind:
3358 mlx5_ib_unbind_slave_port(ibdev, mpi);
3359 return false;
3360 }
3361
mlx5_ib_init_multiport_master(struct mlx5_ib_dev * dev)3362 static int mlx5_ib_init_multiport_master(struct mlx5_ib_dev *dev)
3363 {
3364 u32 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
3365 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev,
3366 port_num + 1);
3367 struct mlx5_ib_multiport_info *mpi;
3368 int err;
3369 u32 i;
3370
3371 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
3372 return 0;
3373
3374 err = mlx5_query_nic_vport_system_image_guid(dev->mdev,
3375 &dev->sys_image_guid);
3376 if (err)
3377 return err;
3378
3379 err = mlx5_nic_vport_enable_roce(dev->mdev);
3380 if (err)
3381 return err;
3382
3383 mutex_lock(&mlx5_ib_multiport_mutex);
3384 for (i = 0; i < dev->num_ports; i++) {
3385 bool bound = false;
3386
3387 /* build a stub multiport info struct for the native port. */
3388 if (i == port_num) {
3389 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL);
3390 if (!mpi) {
3391 mutex_unlock(&mlx5_ib_multiport_mutex);
3392 mlx5_nic_vport_disable_roce(dev->mdev);
3393 return -ENOMEM;
3394 }
3395
3396 mpi->is_master = true;
3397 mpi->mdev = dev->mdev;
3398 mpi->sys_image_guid = dev->sys_image_guid;
3399 dev->port[i].mp.mpi = mpi;
3400 mpi->ibdev = dev;
3401 mpi = NULL;
3402 continue;
3403 }
3404
3405 list_for_each_entry(mpi, &mlx5_ib_unaffiliated_port_list,
3406 list) {
3407 if (dev->sys_image_guid == mpi->sys_image_guid &&
3408 (mlx5_core_native_port_num(mpi->mdev) - 1) == i &&
3409 mlx5_core_same_coredev_type(dev->mdev, mpi->mdev)) {
3410 bound = mlx5_ib_bind_slave_port(dev, mpi);
3411 }
3412
3413 if (bound) {
3414 dev_dbg(mpi->mdev->device,
3415 "removing port from unaffiliated list.\n");
3416 mlx5_ib_dbg(dev, "port %d bound\n", i + 1);
3417 list_del(&mpi->list);
3418 break;
3419 }
3420 }
3421 if (!bound)
3422 mlx5_ib_dbg(dev, "no free port found for port %d\n",
3423 i + 1);
3424 }
3425
3426 list_add_tail(&dev->ib_dev_list, &mlx5_ib_dev_list);
3427 mutex_unlock(&mlx5_ib_multiport_mutex);
3428 return err;
3429 }
3430
mlx5_ib_cleanup_multiport_master(struct mlx5_ib_dev * dev)3431 static void mlx5_ib_cleanup_multiport_master(struct mlx5_ib_dev *dev)
3432 {
3433 u32 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
3434 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev,
3435 port_num + 1);
3436 u32 i;
3437
3438 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
3439 return;
3440
3441 mutex_lock(&mlx5_ib_multiport_mutex);
3442 for (i = 0; i < dev->num_ports; i++) {
3443 if (dev->port[i].mp.mpi) {
3444 /* Destroy the native port stub */
3445 if (i == port_num) {
3446 kfree(dev->port[i].mp.mpi);
3447 dev->port[i].mp.mpi = NULL;
3448 } else {
3449 mlx5_ib_dbg(dev, "unbinding port_num: %u\n",
3450 i + 1);
3451 list_add_tail(&dev->port[i].mp.mpi->list,
3452 &mlx5_ib_unaffiliated_port_list);
3453 mlx5_ib_unbind_slave_port(dev,
3454 dev->port[i].mp.mpi);
3455 }
3456 }
3457 }
3458
3459 mlx5_ib_dbg(dev, "removing from devlist\n");
3460 list_del(&dev->ib_dev_list);
3461 mutex_unlock(&mlx5_ib_multiport_mutex);
3462
3463 mlx5_nic_vport_disable_roce(dev->mdev);
3464 }
3465
mmap_obj_cleanup(struct ib_uobject * uobject,enum rdma_remove_reason why,struct uverbs_attr_bundle * attrs)3466 static int mmap_obj_cleanup(struct ib_uobject *uobject,
3467 enum rdma_remove_reason why,
3468 struct uverbs_attr_bundle *attrs)
3469 {
3470 struct mlx5_user_mmap_entry *obj = uobject->object;
3471
3472 rdma_user_mmap_entry_remove(&obj->rdma_entry);
3473 return 0;
3474 }
3475
mlx5_rdma_user_mmap_entry_insert(struct mlx5_ib_ucontext * c,struct mlx5_user_mmap_entry * entry,size_t length)3476 static int mlx5_rdma_user_mmap_entry_insert(struct mlx5_ib_ucontext *c,
3477 struct mlx5_user_mmap_entry *entry,
3478 size_t length)
3479 {
3480 return rdma_user_mmap_entry_insert_range(
3481 &c->ibucontext, &entry->rdma_entry, length,
3482 (MLX5_IB_MMAP_OFFSET_START << 16),
3483 ((MLX5_IB_MMAP_OFFSET_END << 16) + (1UL << 16) - 1));
3484 }
3485
3486 static struct mlx5_user_mmap_entry *
alloc_var_entry(struct mlx5_ib_ucontext * c)3487 alloc_var_entry(struct mlx5_ib_ucontext *c)
3488 {
3489 struct mlx5_user_mmap_entry *entry;
3490 struct mlx5_var_table *var_table;
3491 u32 page_idx;
3492 int err;
3493
3494 var_table = &to_mdev(c->ibucontext.device)->var_table;
3495 entry = kzalloc(sizeof(*entry), GFP_KERNEL);
3496 if (!entry)
3497 return ERR_PTR(-ENOMEM);
3498
3499 mutex_lock(&var_table->bitmap_lock);
3500 page_idx = find_first_zero_bit(var_table->bitmap,
3501 var_table->num_var_hw_entries);
3502 if (page_idx >= var_table->num_var_hw_entries) {
3503 err = -ENOSPC;
3504 mutex_unlock(&var_table->bitmap_lock);
3505 goto end;
3506 }
3507
3508 set_bit(page_idx, var_table->bitmap);
3509 mutex_unlock(&var_table->bitmap_lock);
3510
3511 entry->address = var_table->hw_start_addr +
3512 (page_idx * var_table->stride_size);
3513 entry->page_idx = page_idx;
3514 entry->mmap_flag = MLX5_IB_MMAP_TYPE_VAR;
3515
3516 err = mlx5_rdma_user_mmap_entry_insert(c, entry,
3517 var_table->stride_size);
3518 if (err)
3519 goto err_insert;
3520
3521 return entry;
3522
3523 err_insert:
3524 mutex_lock(&var_table->bitmap_lock);
3525 clear_bit(page_idx, var_table->bitmap);
3526 mutex_unlock(&var_table->bitmap_lock);
3527 end:
3528 kfree(entry);
3529 return ERR_PTR(err);
3530 }
3531
UVERBS_HANDLER(MLX5_IB_METHOD_VAR_OBJ_ALLOC)3532 static int UVERBS_HANDLER(MLX5_IB_METHOD_VAR_OBJ_ALLOC)(
3533 struct uverbs_attr_bundle *attrs)
3534 {
3535 struct ib_uobject *uobj = uverbs_attr_get_uobject(
3536 attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE);
3537 struct mlx5_ib_ucontext *c;
3538 struct mlx5_user_mmap_entry *entry;
3539 u64 mmap_offset;
3540 u32 length;
3541 int err;
3542
3543 c = to_mucontext(ib_uverbs_get_ucontext(attrs));
3544 if (IS_ERR(c))
3545 return PTR_ERR(c);
3546
3547 entry = alloc_var_entry(c);
3548 if (IS_ERR(entry))
3549 return PTR_ERR(entry);
3550
3551 mmap_offset = mlx5_entry_to_mmap_offset(entry);
3552 length = entry->rdma_entry.npages * PAGE_SIZE;
3553 uobj->object = entry;
3554 uverbs_finalize_uobj_create(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE);
3555
3556 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_OFFSET,
3557 &mmap_offset, sizeof(mmap_offset));
3558 if (err)
3559 return err;
3560
3561 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_PAGE_ID,
3562 &entry->page_idx, sizeof(entry->page_idx));
3563 if (err)
3564 return err;
3565
3566 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_LENGTH,
3567 &length, sizeof(length));
3568 return err;
3569 }
3570
3571 DECLARE_UVERBS_NAMED_METHOD(
3572 MLX5_IB_METHOD_VAR_OBJ_ALLOC,
3573 UVERBS_ATTR_IDR(MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE,
3574 MLX5_IB_OBJECT_VAR,
3575 UVERBS_ACCESS_NEW,
3576 UA_MANDATORY),
3577 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_PAGE_ID,
3578 UVERBS_ATTR_TYPE(u32),
3579 UA_MANDATORY),
3580 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_LENGTH,
3581 UVERBS_ATTR_TYPE(u32),
3582 UA_MANDATORY),
3583 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_OFFSET,
3584 UVERBS_ATTR_TYPE(u64),
3585 UA_MANDATORY));
3586
3587 DECLARE_UVERBS_NAMED_METHOD_DESTROY(
3588 MLX5_IB_METHOD_VAR_OBJ_DESTROY,
3589 UVERBS_ATTR_IDR(MLX5_IB_ATTR_VAR_OBJ_DESTROY_HANDLE,
3590 MLX5_IB_OBJECT_VAR,
3591 UVERBS_ACCESS_DESTROY,
3592 UA_MANDATORY));
3593
3594 DECLARE_UVERBS_NAMED_OBJECT(MLX5_IB_OBJECT_VAR,
3595 UVERBS_TYPE_ALLOC_IDR(mmap_obj_cleanup),
3596 &UVERBS_METHOD(MLX5_IB_METHOD_VAR_OBJ_ALLOC),
3597 &UVERBS_METHOD(MLX5_IB_METHOD_VAR_OBJ_DESTROY));
3598
var_is_supported(struct ib_device * device)3599 static bool var_is_supported(struct ib_device *device)
3600 {
3601 struct mlx5_ib_dev *dev = to_mdev(device);
3602
3603 return (MLX5_CAP_GEN_64(dev->mdev, general_obj_types) &
3604 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q);
3605 }
3606
3607 static struct mlx5_user_mmap_entry *
alloc_uar_entry(struct mlx5_ib_ucontext * c,enum mlx5_ib_uapi_uar_alloc_type alloc_type)3608 alloc_uar_entry(struct mlx5_ib_ucontext *c,
3609 enum mlx5_ib_uapi_uar_alloc_type alloc_type)
3610 {
3611 struct mlx5_user_mmap_entry *entry;
3612 struct mlx5_ib_dev *dev;
3613 u32 uar_index;
3614 int err;
3615
3616 entry = kzalloc(sizeof(*entry), GFP_KERNEL);
3617 if (!entry)
3618 return ERR_PTR(-ENOMEM);
3619
3620 dev = to_mdev(c->ibucontext.device);
3621 err = mlx5_cmd_uar_alloc(dev->mdev, &uar_index, c->devx_uid);
3622 if (err)
3623 goto end;
3624
3625 entry->page_idx = uar_index;
3626 entry->address = uar_index2paddress(dev, uar_index);
3627 if (alloc_type == MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF)
3628 entry->mmap_flag = MLX5_IB_MMAP_TYPE_UAR_WC;
3629 else
3630 entry->mmap_flag = MLX5_IB_MMAP_TYPE_UAR_NC;
3631
3632 err = mlx5_rdma_user_mmap_entry_insert(c, entry, PAGE_SIZE);
3633 if (err)
3634 goto err_insert;
3635
3636 return entry;
3637
3638 err_insert:
3639 mlx5_cmd_uar_dealloc(dev->mdev, uar_index, c->devx_uid);
3640 end:
3641 kfree(entry);
3642 return ERR_PTR(err);
3643 }
3644
UVERBS_HANDLER(MLX5_IB_METHOD_UAR_OBJ_ALLOC)3645 static int UVERBS_HANDLER(MLX5_IB_METHOD_UAR_OBJ_ALLOC)(
3646 struct uverbs_attr_bundle *attrs)
3647 {
3648 struct ib_uobject *uobj = uverbs_attr_get_uobject(
3649 attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE);
3650 enum mlx5_ib_uapi_uar_alloc_type alloc_type;
3651 struct mlx5_ib_ucontext *c;
3652 struct mlx5_user_mmap_entry *entry;
3653 u64 mmap_offset;
3654 u32 length;
3655 int err;
3656
3657 c = to_mucontext(ib_uverbs_get_ucontext(attrs));
3658 if (IS_ERR(c))
3659 return PTR_ERR(c);
3660
3661 err = uverbs_get_const(&alloc_type, attrs,
3662 MLX5_IB_ATTR_UAR_OBJ_ALLOC_TYPE);
3663 if (err)
3664 return err;
3665
3666 if (alloc_type != MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF &&
3667 alloc_type != MLX5_IB_UAPI_UAR_ALLOC_TYPE_NC)
3668 return -EOPNOTSUPP;
3669
3670 if (!to_mdev(c->ibucontext.device)->wc_support &&
3671 alloc_type == MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF)
3672 return -EOPNOTSUPP;
3673
3674 entry = alloc_uar_entry(c, alloc_type);
3675 if (IS_ERR(entry))
3676 return PTR_ERR(entry);
3677
3678 mmap_offset = mlx5_entry_to_mmap_offset(entry);
3679 length = entry->rdma_entry.npages * PAGE_SIZE;
3680 uobj->object = entry;
3681 uverbs_finalize_uobj_create(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE);
3682
3683 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_OFFSET,
3684 &mmap_offset, sizeof(mmap_offset));
3685 if (err)
3686 return err;
3687
3688 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_PAGE_ID,
3689 &entry->page_idx, sizeof(entry->page_idx));
3690 if (err)
3691 return err;
3692
3693 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_LENGTH,
3694 &length, sizeof(length));
3695 return err;
3696 }
3697
3698 DECLARE_UVERBS_NAMED_METHOD(
3699 MLX5_IB_METHOD_UAR_OBJ_ALLOC,
3700 UVERBS_ATTR_IDR(MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE,
3701 MLX5_IB_OBJECT_UAR,
3702 UVERBS_ACCESS_NEW,
3703 UA_MANDATORY),
3704 UVERBS_ATTR_CONST_IN(MLX5_IB_ATTR_UAR_OBJ_ALLOC_TYPE,
3705 enum mlx5_ib_uapi_uar_alloc_type,
3706 UA_MANDATORY),
3707 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_PAGE_ID,
3708 UVERBS_ATTR_TYPE(u32),
3709 UA_MANDATORY),
3710 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_LENGTH,
3711 UVERBS_ATTR_TYPE(u32),
3712 UA_MANDATORY),
3713 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_OFFSET,
3714 UVERBS_ATTR_TYPE(u64),
3715 UA_MANDATORY));
3716
3717 DECLARE_UVERBS_NAMED_METHOD_DESTROY(
3718 MLX5_IB_METHOD_UAR_OBJ_DESTROY,
3719 UVERBS_ATTR_IDR(MLX5_IB_ATTR_UAR_OBJ_DESTROY_HANDLE,
3720 MLX5_IB_OBJECT_UAR,
3721 UVERBS_ACCESS_DESTROY,
3722 UA_MANDATORY));
3723
3724 DECLARE_UVERBS_NAMED_OBJECT(MLX5_IB_OBJECT_UAR,
3725 UVERBS_TYPE_ALLOC_IDR(mmap_obj_cleanup),
3726 &UVERBS_METHOD(MLX5_IB_METHOD_UAR_OBJ_ALLOC),
3727 &UVERBS_METHOD(MLX5_IB_METHOD_UAR_OBJ_DESTROY));
3728
3729 ADD_UVERBS_ATTRIBUTES_SIMPLE(
3730 mlx5_ib_query_context,
3731 UVERBS_OBJECT_DEVICE,
3732 UVERBS_METHOD_QUERY_CONTEXT,
3733 UVERBS_ATTR_PTR_OUT(
3734 MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX,
3735 UVERBS_ATTR_STRUCT(struct mlx5_ib_alloc_ucontext_resp,
3736 dump_fill_mkey),
3737 UA_MANDATORY));
3738
3739 static const struct uapi_definition mlx5_ib_defs[] = {
3740 UAPI_DEF_CHAIN(mlx5_ib_devx_defs),
3741 UAPI_DEF_CHAIN(mlx5_ib_flow_defs),
3742 UAPI_DEF_CHAIN(mlx5_ib_qos_defs),
3743 UAPI_DEF_CHAIN(mlx5_ib_std_types_defs),
3744 UAPI_DEF_CHAIN(mlx5_ib_dm_defs),
3745
3746 UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_DEVICE, &mlx5_ib_query_context),
3747 UAPI_DEF_CHAIN_OBJ_TREE_NAMED(MLX5_IB_OBJECT_VAR,
3748 UAPI_DEF_IS_OBJ_SUPPORTED(var_is_supported)),
3749 UAPI_DEF_CHAIN_OBJ_TREE_NAMED(MLX5_IB_OBJECT_UAR),
3750 {}
3751 };
3752
mlx5_ib_stage_init_cleanup(struct mlx5_ib_dev * dev)3753 static void mlx5_ib_stage_init_cleanup(struct mlx5_ib_dev *dev)
3754 {
3755 mlx5_ib_cleanup_multiport_master(dev);
3756 WARN_ON(!xa_empty(&dev->odp_mkeys));
3757 mutex_destroy(&dev->cap_mask_mutex);
3758 WARN_ON(!xa_empty(&dev->sig_mrs));
3759 WARN_ON(!bitmap_empty(dev->dm.memic_alloc_pages, MLX5_MAX_MEMIC_PAGES));
3760 mlx5r_macsec_dealloc_gids(dev);
3761 }
3762
mlx5_ib_stage_init_init(struct mlx5_ib_dev * dev)3763 static int mlx5_ib_stage_init_init(struct mlx5_ib_dev *dev)
3764 {
3765 struct mlx5_core_dev *mdev = dev->mdev;
3766 int err, i;
3767
3768 dev->ib_dev.node_type = RDMA_NODE_IB_CA;
3769 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */;
3770 dev->ib_dev.phys_port_cnt = dev->num_ports;
3771 dev->ib_dev.dev.parent = mdev->device;
3772 dev->ib_dev.lag_flags = RDMA_LAG_FLAGS_HASH_ALL_SLAVES;
3773
3774 for (i = 0; i < dev->num_ports; i++) {
3775 spin_lock_init(&dev->port[i].mp.mpi_lock);
3776 rwlock_init(&dev->port[i].roce.netdev_lock);
3777 dev->port[i].roce.dev = dev;
3778 dev->port[i].roce.native_port_num = i + 1;
3779 dev->port[i].roce.last_port_state = IB_PORT_DOWN;
3780 }
3781
3782 err = mlx5r_cmd_query_special_mkeys(dev);
3783 if (err)
3784 return err;
3785
3786 err = mlx5r_macsec_init_gids_and_devlist(dev);
3787 if (err)
3788 return err;
3789
3790 err = mlx5_ib_init_multiport_master(dev);
3791 if (err)
3792 goto err;
3793
3794 err = set_has_smi_cap(dev);
3795 if (err)
3796 goto err_mp;
3797
3798 err = mlx5_query_max_pkeys(&dev->ib_dev, &dev->pkey_table_len);
3799 if (err)
3800 goto err_mp;
3801
3802 if (mlx5_use_mad_ifc(dev))
3803 get_ext_port_caps(dev);
3804
3805 dev->ib_dev.num_comp_vectors = mlx5_comp_vectors_max(mdev);
3806
3807 mutex_init(&dev->cap_mask_mutex);
3808 INIT_LIST_HEAD(&dev->qp_list);
3809 spin_lock_init(&dev->reset_flow_resource_lock);
3810 xa_init(&dev->odp_mkeys);
3811 xa_init(&dev->sig_mrs);
3812 atomic_set(&dev->mkey_var, 0);
3813
3814 spin_lock_init(&dev->dm.lock);
3815 dev->dm.dev = mdev;
3816 return 0;
3817 err_mp:
3818 mlx5_ib_cleanup_multiport_master(dev);
3819 err:
3820 mlx5r_macsec_dealloc_gids(dev);
3821 return err;
3822 }
3823
mlx5_ib_enable_driver(struct ib_device * dev)3824 static int mlx5_ib_enable_driver(struct ib_device *dev)
3825 {
3826 struct mlx5_ib_dev *mdev = to_mdev(dev);
3827 int ret;
3828
3829 ret = mlx5_ib_test_wc(mdev);
3830 mlx5_ib_dbg(mdev, "Write-Combining %s",
3831 mdev->wc_support ? "supported" : "not supported");
3832
3833 return ret;
3834 }
3835
3836 static const struct ib_device_ops mlx5_ib_dev_ops = {
3837 .owner = THIS_MODULE,
3838 .driver_id = RDMA_DRIVER_MLX5,
3839 .uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION,
3840
3841 .add_gid = mlx5_ib_add_gid,
3842 .alloc_mr = mlx5_ib_alloc_mr,
3843 .alloc_mr_integrity = mlx5_ib_alloc_mr_integrity,
3844 .alloc_pd = mlx5_ib_alloc_pd,
3845 .alloc_ucontext = mlx5_ib_alloc_ucontext,
3846 .attach_mcast = mlx5_ib_mcg_attach,
3847 .check_mr_status = mlx5_ib_check_mr_status,
3848 .create_ah = mlx5_ib_create_ah,
3849 .create_cq = mlx5_ib_create_cq,
3850 .create_qp = mlx5_ib_create_qp,
3851 .create_srq = mlx5_ib_create_srq,
3852 .create_user_ah = mlx5_ib_create_ah,
3853 .dealloc_pd = mlx5_ib_dealloc_pd,
3854 .dealloc_ucontext = mlx5_ib_dealloc_ucontext,
3855 .del_gid = mlx5_ib_del_gid,
3856 .dereg_mr = mlx5_ib_dereg_mr,
3857 .destroy_ah = mlx5_ib_destroy_ah,
3858 .destroy_cq = mlx5_ib_destroy_cq,
3859 .destroy_qp = mlx5_ib_destroy_qp,
3860 .destroy_srq = mlx5_ib_destroy_srq,
3861 .detach_mcast = mlx5_ib_mcg_detach,
3862 .disassociate_ucontext = mlx5_ib_disassociate_ucontext,
3863 .drain_rq = mlx5_ib_drain_rq,
3864 .drain_sq = mlx5_ib_drain_sq,
3865 .device_group = &mlx5_attr_group,
3866 .enable_driver = mlx5_ib_enable_driver,
3867 .get_dev_fw_str = get_dev_fw_str,
3868 .get_dma_mr = mlx5_ib_get_dma_mr,
3869 .get_link_layer = mlx5_ib_port_link_layer,
3870 .map_mr_sg = mlx5_ib_map_mr_sg,
3871 .map_mr_sg_pi = mlx5_ib_map_mr_sg_pi,
3872 .mmap = mlx5_ib_mmap,
3873 .mmap_free = mlx5_ib_mmap_free,
3874 .modify_cq = mlx5_ib_modify_cq,
3875 .modify_device = mlx5_ib_modify_device,
3876 .modify_port = mlx5_ib_modify_port,
3877 .modify_qp = mlx5_ib_modify_qp,
3878 .modify_srq = mlx5_ib_modify_srq,
3879 .poll_cq = mlx5_ib_poll_cq,
3880 .post_recv = mlx5_ib_post_recv_nodrain,
3881 .post_send = mlx5_ib_post_send_nodrain,
3882 .post_srq_recv = mlx5_ib_post_srq_recv,
3883 .process_mad = mlx5_ib_process_mad,
3884 .query_ah = mlx5_ib_query_ah,
3885 .query_device = mlx5_ib_query_device,
3886 .query_gid = mlx5_ib_query_gid,
3887 .query_pkey = mlx5_ib_query_pkey,
3888 .query_qp = mlx5_ib_query_qp,
3889 .query_srq = mlx5_ib_query_srq,
3890 .query_ucontext = mlx5_ib_query_ucontext,
3891 .reg_user_mr = mlx5_ib_reg_user_mr,
3892 .reg_user_mr_dmabuf = mlx5_ib_reg_user_mr_dmabuf,
3893 .req_notify_cq = mlx5_ib_arm_cq,
3894 .rereg_user_mr = mlx5_ib_rereg_user_mr,
3895 .resize_cq = mlx5_ib_resize_cq,
3896
3897 INIT_RDMA_OBJ_SIZE(ib_ah, mlx5_ib_ah, ibah),
3898 INIT_RDMA_OBJ_SIZE(ib_counters, mlx5_ib_mcounters, ibcntrs),
3899 INIT_RDMA_OBJ_SIZE(ib_cq, mlx5_ib_cq, ibcq),
3900 INIT_RDMA_OBJ_SIZE(ib_pd, mlx5_ib_pd, ibpd),
3901 INIT_RDMA_OBJ_SIZE(ib_qp, mlx5_ib_qp, ibqp),
3902 INIT_RDMA_OBJ_SIZE(ib_srq, mlx5_ib_srq, ibsrq),
3903 INIT_RDMA_OBJ_SIZE(ib_ucontext, mlx5_ib_ucontext, ibucontext),
3904 };
3905
3906 static const struct ib_device_ops mlx5_ib_dev_ipoib_enhanced_ops = {
3907 .rdma_netdev_get_params = mlx5_ib_rn_get_params,
3908 };
3909
3910 static const struct ib_device_ops mlx5_ib_dev_sriov_ops = {
3911 .get_vf_config = mlx5_ib_get_vf_config,
3912 .get_vf_guid = mlx5_ib_get_vf_guid,
3913 .get_vf_stats = mlx5_ib_get_vf_stats,
3914 .set_vf_guid = mlx5_ib_set_vf_guid,
3915 .set_vf_link_state = mlx5_ib_set_vf_link_state,
3916 };
3917
3918 static const struct ib_device_ops mlx5_ib_dev_mw_ops = {
3919 .alloc_mw = mlx5_ib_alloc_mw,
3920 .dealloc_mw = mlx5_ib_dealloc_mw,
3921
3922 INIT_RDMA_OBJ_SIZE(ib_mw, mlx5_ib_mw, ibmw),
3923 };
3924
3925 static const struct ib_device_ops mlx5_ib_dev_xrc_ops = {
3926 .alloc_xrcd = mlx5_ib_alloc_xrcd,
3927 .dealloc_xrcd = mlx5_ib_dealloc_xrcd,
3928
3929 INIT_RDMA_OBJ_SIZE(ib_xrcd, mlx5_ib_xrcd, ibxrcd),
3930 };
3931
mlx5_ib_init_var_table(struct mlx5_ib_dev * dev)3932 static int mlx5_ib_init_var_table(struct mlx5_ib_dev *dev)
3933 {
3934 struct mlx5_core_dev *mdev = dev->mdev;
3935 struct mlx5_var_table *var_table = &dev->var_table;
3936 u8 log_doorbell_bar_size;
3937 u8 log_doorbell_stride;
3938 u64 bar_size;
3939
3940 log_doorbell_bar_size = MLX5_CAP_DEV_VDPA_EMULATION(mdev,
3941 log_doorbell_bar_size);
3942 log_doorbell_stride = MLX5_CAP_DEV_VDPA_EMULATION(mdev,
3943 log_doorbell_stride);
3944 var_table->hw_start_addr = dev->mdev->bar_addr +
3945 MLX5_CAP64_DEV_VDPA_EMULATION(mdev,
3946 doorbell_bar_offset);
3947 bar_size = (1ULL << log_doorbell_bar_size) * 4096;
3948 var_table->stride_size = 1ULL << log_doorbell_stride;
3949 var_table->num_var_hw_entries = div_u64(bar_size,
3950 var_table->stride_size);
3951 mutex_init(&var_table->bitmap_lock);
3952 var_table->bitmap = bitmap_zalloc(var_table->num_var_hw_entries,
3953 GFP_KERNEL);
3954 return (var_table->bitmap) ? 0 : -ENOMEM;
3955 }
3956
mlx5_ib_stage_caps_cleanup(struct mlx5_ib_dev * dev)3957 static void mlx5_ib_stage_caps_cleanup(struct mlx5_ib_dev *dev)
3958 {
3959 bitmap_free(dev->var_table.bitmap);
3960 }
3961
mlx5_ib_stage_caps_init(struct mlx5_ib_dev * dev)3962 static int mlx5_ib_stage_caps_init(struct mlx5_ib_dev *dev)
3963 {
3964 struct mlx5_core_dev *mdev = dev->mdev;
3965 int err;
3966
3967 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) &&
3968 IS_ENABLED(CONFIG_MLX5_CORE_IPOIB))
3969 ib_set_device_ops(&dev->ib_dev,
3970 &mlx5_ib_dev_ipoib_enhanced_ops);
3971
3972 if (mlx5_core_is_pf(mdev))
3973 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_sriov_ops);
3974
3975 dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence));
3976
3977 if (MLX5_CAP_GEN(mdev, imaicl))
3978 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_mw_ops);
3979
3980 if (MLX5_CAP_GEN(mdev, xrc))
3981 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_xrc_ops);
3982
3983 if (MLX5_CAP_DEV_MEM(mdev, memic) ||
3984 MLX5_CAP_GEN_64(dev->mdev, general_obj_types) &
3985 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM)
3986 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_dm_ops);
3987
3988 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_ops);
3989
3990 if (IS_ENABLED(CONFIG_INFINIBAND_USER_ACCESS))
3991 dev->ib_dev.driver_def = mlx5_ib_defs;
3992
3993 err = init_node_data(dev);
3994 if (err)
3995 return err;
3996
3997 if ((MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) &&
3998 (MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) ||
3999 MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
4000 mutex_init(&dev->lb.mutex);
4001
4002 if (MLX5_CAP_GEN_64(dev->mdev, general_obj_types) &
4003 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q) {
4004 err = mlx5_ib_init_var_table(dev);
4005 if (err)
4006 return err;
4007 }
4008
4009 dev->ib_dev.use_cq_dim = true;
4010
4011 return 0;
4012 }
4013
4014 static const struct ib_device_ops mlx5_ib_dev_port_ops = {
4015 .get_port_immutable = mlx5_port_immutable,
4016 .query_port = mlx5_ib_query_port,
4017 };
4018
mlx5_ib_stage_non_default_cb(struct mlx5_ib_dev * dev)4019 static int mlx5_ib_stage_non_default_cb(struct mlx5_ib_dev *dev)
4020 {
4021 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_ops);
4022 return 0;
4023 }
4024
4025 static const struct ib_device_ops mlx5_ib_dev_port_rep_ops = {
4026 .get_port_immutable = mlx5_port_rep_immutable,
4027 .query_port = mlx5_ib_rep_query_port,
4028 .query_pkey = mlx5_ib_rep_query_pkey,
4029 };
4030
mlx5_ib_stage_raw_eth_non_default_cb(struct mlx5_ib_dev * dev)4031 static int mlx5_ib_stage_raw_eth_non_default_cb(struct mlx5_ib_dev *dev)
4032 {
4033 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_rep_ops);
4034 return 0;
4035 }
4036
4037 static const struct ib_device_ops mlx5_ib_dev_common_roce_ops = {
4038 .create_rwq_ind_table = mlx5_ib_create_rwq_ind_table,
4039 .create_wq = mlx5_ib_create_wq,
4040 .destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table,
4041 .destroy_wq = mlx5_ib_destroy_wq,
4042 .get_netdev = mlx5_ib_get_netdev,
4043 .modify_wq = mlx5_ib_modify_wq,
4044
4045 INIT_RDMA_OBJ_SIZE(ib_rwq_ind_table, mlx5_ib_rwq_ind_table,
4046 ib_rwq_ind_tbl),
4047 };
4048
mlx5_ib_roce_init(struct mlx5_ib_dev * dev)4049 static int mlx5_ib_roce_init(struct mlx5_ib_dev *dev)
4050 {
4051 struct mlx5_core_dev *mdev = dev->mdev;
4052 enum rdma_link_layer ll;
4053 int port_type_cap;
4054 u32 port_num = 0;
4055 int err;
4056
4057 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
4058 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
4059
4060 if (ll == IB_LINK_LAYER_ETHERNET) {
4061 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_common_roce_ops);
4062
4063 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
4064
4065 /* Register only for native ports */
4066 mlx5_mdev_netdev_track(dev, port_num);
4067
4068 err = mlx5_enable_eth(dev);
4069 if (err)
4070 goto cleanup;
4071 }
4072
4073 return 0;
4074 cleanup:
4075 mlx5_mdev_netdev_untrack(dev, port_num);
4076 return err;
4077 }
4078
mlx5_ib_roce_cleanup(struct mlx5_ib_dev * dev)4079 static void mlx5_ib_roce_cleanup(struct mlx5_ib_dev *dev)
4080 {
4081 struct mlx5_core_dev *mdev = dev->mdev;
4082 enum rdma_link_layer ll;
4083 int port_type_cap;
4084 u32 port_num;
4085
4086 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
4087 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
4088
4089 if (ll == IB_LINK_LAYER_ETHERNET) {
4090 mlx5_disable_eth(dev);
4091
4092 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
4093 mlx5_mdev_netdev_untrack(dev, port_num);
4094 }
4095 }
4096
mlx5_ib_stage_cong_debugfs_init(struct mlx5_ib_dev * dev)4097 static int mlx5_ib_stage_cong_debugfs_init(struct mlx5_ib_dev *dev)
4098 {
4099 mlx5_ib_init_cong_debugfs(dev,
4100 mlx5_core_native_port_num(dev->mdev) - 1);
4101 return 0;
4102 }
4103
mlx5_ib_stage_cong_debugfs_cleanup(struct mlx5_ib_dev * dev)4104 static void mlx5_ib_stage_cong_debugfs_cleanup(struct mlx5_ib_dev *dev)
4105 {
4106 mlx5_ib_cleanup_cong_debugfs(dev,
4107 mlx5_core_native_port_num(dev->mdev) - 1);
4108 }
4109
mlx5_ib_stage_uar_init(struct mlx5_ib_dev * dev)4110 static int mlx5_ib_stage_uar_init(struct mlx5_ib_dev *dev)
4111 {
4112 dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev);
4113 return PTR_ERR_OR_ZERO(dev->mdev->priv.uar);
4114 }
4115
mlx5_ib_stage_uar_cleanup(struct mlx5_ib_dev * dev)4116 static void mlx5_ib_stage_uar_cleanup(struct mlx5_ib_dev *dev)
4117 {
4118 mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar);
4119 }
4120
mlx5_ib_stage_bfrag_init(struct mlx5_ib_dev * dev)4121 static int mlx5_ib_stage_bfrag_init(struct mlx5_ib_dev *dev)
4122 {
4123 int err;
4124
4125 err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false);
4126 if (err)
4127 return err;
4128
4129 err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true);
4130 if (err)
4131 mlx5_free_bfreg(dev->mdev, &dev->bfreg);
4132
4133 return err;
4134 }
4135
mlx5_ib_stage_bfrag_cleanup(struct mlx5_ib_dev * dev)4136 static void mlx5_ib_stage_bfrag_cleanup(struct mlx5_ib_dev *dev)
4137 {
4138 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
4139 mlx5_free_bfreg(dev->mdev, &dev->bfreg);
4140 }
4141
mlx5_ib_stage_ib_reg_init(struct mlx5_ib_dev * dev)4142 static int mlx5_ib_stage_ib_reg_init(struct mlx5_ib_dev *dev)
4143 {
4144 const char *name;
4145
4146 if (!mlx5_lag_is_active(dev->mdev))
4147 name = "mlx5_%d";
4148 else
4149 name = "mlx5_bond_%d";
4150 return ib_register_device(&dev->ib_dev, name, &dev->mdev->pdev->dev);
4151 }
4152
mlx5_ib_stage_pre_ib_reg_umr_cleanup(struct mlx5_ib_dev * dev)4153 static void mlx5_ib_stage_pre_ib_reg_umr_cleanup(struct mlx5_ib_dev *dev)
4154 {
4155 mlx5_mkey_cache_cleanup(dev);
4156 mlx5r_umr_resource_cleanup(dev);
4157 }
4158
mlx5_ib_stage_ib_reg_cleanup(struct mlx5_ib_dev * dev)4159 static void mlx5_ib_stage_ib_reg_cleanup(struct mlx5_ib_dev *dev)
4160 {
4161 ib_unregister_device(&dev->ib_dev);
4162 }
4163
mlx5_ib_stage_post_ib_reg_umr_init(struct mlx5_ib_dev * dev)4164 static int mlx5_ib_stage_post_ib_reg_umr_init(struct mlx5_ib_dev *dev)
4165 {
4166 int ret;
4167
4168 ret = mlx5r_umr_resource_init(dev);
4169 if (ret)
4170 return ret;
4171
4172 ret = mlx5_mkey_cache_init(dev);
4173 if (ret)
4174 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
4175 return ret;
4176 }
4177
mlx5_ib_stage_delay_drop_init(struct mlx5_ib_dev * dev)4178 static int mlx5_ib_stage_delay_drop_init(struct mlx5_ib_dev *dev)
4179 {
4180 struct dentry *root;
4181
4182 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
4183 return 0;
4184
4185 mutex_init(&dev->delay_drop.lock);
4186 dev->delay_drop.dev = dev;
4187 dev->delay_drop.activate = false;
4188 dev->delay_drop.timeout = MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 1000;
4189 INIT_WORK(&dev->delay_drop.delay_drop_work, delay_drop_handler);
4190 atomic_set(&dev->delay_drop.rqs_cnt, 0);
4191 atomic_set(&dev->delay_drop.events_cnt, 0);
4192
4193 if (!mlx5_debugfs_root)
4194 return 0;
4195
4196 root = debugfs_create_dir("delay_drop", mlx5_debugfs_get_dev_root(dev->mdev));
4197 dev->delay_drop.dir_debugfs = root;
4198
4199 debugfs_create_atomic_t("num_timeout_events", 0400, root,
4200 &dev->delay_drop.events_cnt);
4201 debugfs_create_atomic_t("num_rqs", 0400, root,
4202 &dev->delay_drop.rqs_cnt);
4203 debugfs_create_file("timeout", 0600, root, &dev->delay_drop,
4204 &fops_delay_drop_timeout);
4205 return 0;
4206 }
4207
mlx5_ib_stage_delay_drop_cleanup(struct mlx5_ib_dev * dev)4208 static void mlx5_ib_stage_delay_drop_cleanup(struct mlx5_ib_dev *dev)
4209 {
4210 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
4211 return;
4212
4213 cancel_work_sync(&dev->delay_drop.delay_drop_work);
4214 if (!dev->delay_drop.dir_debugfs)
4215 return;
4216
4217 debugfs_remove_recursive(dev->delay_drop.dir_debugfs);
4218 dev->delay_drop.dir_debugfs = NULL;
4219 }
4220
mlx5_ib_stage_dev_notifier_init(struct mlx5_ib_dev * dev)4221 static int mlx5_ib_stage_dev_notifier_init(struct mlx5_ib_dev *dev)
4222 {
4223 struct mlx5_ib_resources *devr = &dev->devr;
4224 int port;
4225
4226 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port)
4227 INIT_WORK(&devr->ports[port].pkey_change_work,
4228 pkey_change_handler);
4229
4230 dev->mdev_events.notifier_call = mlx5_ib_event;
4231 mlx5_notifier_register(dev->mdev, &dev->mdev_events);
4232
4233 mlx5r_macsec_event_register(dev);
4234
4235 return 0;
4236 }
4237
mlx5_ib_stage_dev_notifier_cleanup(struct mlx5_ib_dev * dev)4238 static void mlx5_ib_stage_dev_notifier_cleanup(struct mlx5_ib_dev *dev)
4239 {
4240 struct mlx5_ib_resources *devr = &dev->devr;
4241 int port;
4242
4243 mlx5r_macsec_event_unregister(dev);
4244 mlx5_notifier_unregister(dev->mdev, &dev->mdev_events);
4245
4246 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port)
4247 cancel_work_sync(&devr->ports[port].pkey_change_work);
4248 }
4249
__mlx5_ib_remove(struct mlx5_ib_dev * dev,const struct mlx5_ib_profile * profile,int stage)4250 void __mlx5_ib_remove(struct mlx5_ib_dev *dev,
4251 const struct mlx5_ib_profile *profile,
4252 int stage)
4253 {
4254 dev->ib_active = false;
4255
4256 /* Number of stages to cleanup */
4257 while (stage) {
4258 stage--;
4259 if (profile->stage[stage].cleanup)
4260 profile->stage[stage].cleanup(dev);
4261 }
4262
4263 kfree(dev->port);
4264 ib_dealloc_device(&dev->ib_dev);
4265 }
4266
__mlx5_ib_add(struct mlx5_ib_dev * dev,const struct mlx5_ib_profile * profile)4267 int __mlx5_ib_add(struct mlx5_ib_dev *dev,
4268 const struct mlx5_ib_profile *profile)
4269 {
4270 int err;
4271 int i;
4272
4273 dev->profile = profile;
4274
4275 for (i = 0; i < MLX5_IB_STAGE_MAX; i++) {
4276 if (profile->stage[i].init) {
4277 err = profile->stage[i].init(dev);
4278 if (err)
4279 goto err_out;
4280 }
4281 }
4282
4283 dev->ib_active = true;
4284 return 0;
4285
4286 err_out:
4287 /* Clean up stages which were initialized */
4288 while (i) {
4289 i--;
4290 if (profile->stage[i].cleanup)
4291 profile->stage[i].cleanup(dev);
4292 }
4293 return -ENOMEM;
4294 }
4295
4296 static const struct mlx5_ib_profile pf_profile = {
4297 STAGE_CREATE(MLX5_IB_STAGE_INIT,
4298 mlx5_ib_stage_init_init,
4299 mlx5_ib_stage_init_cleanup),
4300 STAGE_CREATE(MLX5_IB_STAGE_FS,
4301 mlx5_ib_fs_init,
4302 mlx5_ib_fs_cleanup),
4303 STAGE_CREATE(MLX5_IB_STAGE_CAPS,
4304 mlx5_ib_stage_caps_init,
4305 mlx5_ib_stage_caps_cleanup),
4306 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB,
4307 mlx5_ib_stage_non_default_cb,
4308 NULL),
4309 STAGE_CREATE(MLX5_IB_STAGE_ROCE,
4310 mlx5_ib_roce_init,
4311 mlx5_ib_roce_cleanup),
4312 STAGE_CREATE(MLX5_IB_STAGE_QP,
4313 mlx5_init_qp_table,
4314 mlx5_cleanup_qp_table),
4315 STAGE_CREATE(MLX5_IB_STAGE_SRQ,
4316 mlx5_init_srq_table,
4317 mlx5_cleanup_srq_table),
4318 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES,
4319 mlx5_ib_dev_res_init,
4320 mlx5_ib_dev_res_cleanup),
4321 STAGE_CREATE(MLX5_IB_STAGE_ODP,
4322 mlx5_ib_odp_init_one,
4323 mlx5_ib_odp_cleanup_one),
4324 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS,
4325 mlx5_ib_counters_init,
4326 mlx5_ib_counters_cleanup),
4327 STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS,
4328 mlx5_ib_stage_cong_debugfs_init,
4329 mlx5_ib_stage_cong_debugfs_cleanup),
4330 STAGE_CREATE(MLX5_IB_STAGE_UAR,
4331 mlx5_ib_stage_uar_init,
4332 mlx5_ib_stage_uar_cleanup),
4333 STAGE_CREATE(MLX5_IB_STAGE_BFREG,
4334 mlx5_ib_stage_bfrag_init,
4335 mlx5_ib_stage_bfrag_cleanup),
4336 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR,
4337 NULL,
4338 mlx5_ib_stage_pre_ib_reg_umr_cleanup),
4339 STAGE_CREATE(MLX5_IB_STAGE_WHITELIST_UID,
4340 mlx5_ib_devx_init,
4341 mlx5_ib_devx_cleanup),
4342 STAGE_CREATE(MLX5_IB_STAGE_IB_REG,
4343 mlx5_ib_stage_ib_reg_init,
4344 mlx5_ib_stage_ib_reg_cleanup),
4345 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER,
4346 mlx5_ib_stage_dev_notifier_init,
4347 mlx5_ib_stage_dev_notifier_cleanup),
4348 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR,
4349 mlx5_ib_stage_post_ib_reg_umr_init,
4350 NULL),
4351 STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP,
4352 mlx5_ib_stage_delay_drop_init,
4353 mlx5_ib_stage_delay_drop_cleanup),
4354 STAGE_CREATE(MLX5_IB_STAGE_RESTRACK,
4355 mlx5_ib_restrack_init,
4356 NULL),
4357 };
4358
4359 const struct mlx5_ib_profile raw_eth_profile = {
4360 STAGE_CREATE(MLX5_IB_STAGE_INIT,
4361 mlx5_ib_stage_init_init,
4362 mlx5_ib_stage_init_cleanup),
4363 STAGE_CREATE(MLX5_IB_STAGE_FS,
4364 mlx5_ib_fs_init,
4365 mlx5_ib_fs_cleanup),
4366 STAGE_CREATE(MLX5_IB_STAGE_CAPS,
4367 mlx5_ib_stage_caps_init,
4368 mlx5_ib_stage_caps_cleanup),
4369 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB,
4370 mlx5_ib_stage_raw_eth_non_default_cb,
4371 NULL),
4372 STAGE_CREATE(MLX5_IB_STAGE_ROCE,
4373 mlx5_ib_roce_init,
4374 mlx5_ib_roce_cleanup),
4375 STAGE_CREATE(MLX5_IB_STAGE_QP,
4376 mlx5_init_qp_table,
4377 mlx5_cleanup_qp_table),
4378 STAGE_CREATE(MLX5_IB_STAGE_SRQ,
4379 mlx5_init_srq_table,
4380 mlx5_cleanup_srq_table),
4381 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES,
4382 mlx5_ib_dev_res_init,
4383 mlx5_ib_dev_res_cleanup),
4384 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS,
4385 mlx5_ib_counters_init,
4386 mlx5_ib_counters_cleanup),
4387 STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS,
4388 mlx5_ib_stage_cong_debugfs_init,
4389 mlx5_ib_stage_cong_debugfs_cleanup),
4390 STAGE_CREATE(MLX5_IB_STAGE_UAR,
4391 mlx5_ib_stage_uar_init,
4392 mlx5_ib_stage_uar_cleanup),
4393 STAGE_CREATE(MLX5_IB_STAGE_BFREG,
4394 mlx5_ib_stage_bfrag_init,
4395 mlx5_ib_stage_bfrag_cleanup),
4396 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR,
4397 NULL,
4398 mlx5_ib_stage_pre_ib_reg_umr_cleanup),
4399 STAGE_CREATE(MLX5_IB_STAGE_WHITELIST_UID,
4400 mlx5_ib_devx_init,
4401 mlx5_ib_devx_cleanup),
4402 STAGE_CREATE(MLX5_IB_STAGE_IB_REG,
4403 mlx5_ib_stage_ib_reg_init,
4404 mlx5_ib_stage_ib_reg_cleanup),
4405 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER,
4406 mlx5_ib_stage_dev_notifier_init,
4407 mlx5_ib_stage_dev_notifier_cleanup),
4408 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR,
4409 mlx5_ib_stage_post_ib_reg_umr_init,
4410 NULL),
4411 STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP,
4412 mlx5_ib_stage_delay_drop_init,
4413 mlx5_ib_stage_delay_drop_cleanup),
4414 STAGE_CREATE(MLX5_IB_STAGE_RESTRACK,
4415 mlx5_ib_restrack_init,
4416 NULL),
4417 };
4418
mlx5r_mp_probe(struct auxiliary_device * adev,const struct auxiliary_device_id * id)4419 static int mlx5r_mp_probe(struct auxiliary_device *adev,
4420 const struct auxiliary_device_id *id)
4421 {
4422 struct mlx5_adev *idev = container_of(adev, struct mlx5_adev, adev);
4423 struct mlx5_core_dev *mdev = idev->mdev;
4424 struct mlx5_ib_multiport_info *mpi;
4425 struct mlx5_ib_dev *dev;
4426 bool bound = false;
4427 int err;
4428
4429 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL);
4430 if (!mpi)
4431 return -ENOMEM;
4432
4433 mpi->mdev = mdev;
4434 err = mlx5_query_nic_vport_system_image_guid(mdev,
4435 &mpi->sys_image_guid);
4436 if (err) {
4437 kfree(mpi);
4438 return err;
4439 }
4440
4441 mutex_lock(&mlx5_ib_multiport_mutex);
4442 list_for_each_entry(dev, &mlx5_ib_dev_list, ib_dev_list) {
4443 if (dev->sys_image_guid == mpi->sys_image_guid &&
4444 mlx5_core_same_coredev_type(dev->mdev, mpi->mdev))
4445 bound = mlx5_ib_bind_slave_port(dev, mpi);
4446
4447 if (bound) {
4448 rdma_roce_rescan_device(&dev->ib_dev);
4449 mpi->ibdev->ib_active = true;
4450 break;
4451 }
4452 }
4453
4454 if (!bound) {
4455 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list);
4456 dev_dbg(mdev->device,
4457 "no suitable IB device found to bind to, added to unaffiliated list.\n");
4458 }
4459 mutex_unlock(&mlx5_ib_multiport_mutex);
4460
4461 auxiliary_set_drvdata(adev, mpi);
4462 return 0;
4463 }
4464
mlx5r_mp_remove(struct auxiliary_device * adev)4465 static void mlx5r_mp_remove(struct auxiliary_device *adev)
4466 {
4467 struct mlx5_ib_multiport_info *mpi;
4468
4469 mpi = auxiliary_get_drvdata(adev);
4470 mutex_lock(&mlx5_ib_multiport_mutex);
4471 if (mpi->ibdev)
4472 mlx5_ib_unbind_slave_port(mpi->ibdev, mpi);
4473 else
4474 list_del(&mpi->list);
4475 mutex_unlock(&mlx5_ib_multiport_mutex);
4476 kfree(mpi);
4477 }
4478
mlx5r_probe(struct auxiliary_device * adev,const struct auxiliary_device_id * id)4479 static int mlx5r_probe(struct auxiliary_device *adev,
4480 const struct auxiliary_device_id *id)
4481 {
4482 struct mlx5_adev *idev = container_of(adev, struct mlx5_adev, adev);
4483 struct mlx5_core_dev *mdev = idev->mdev;
4484 const struct mlx5_ib_profile *profile;
4485 int port_type_cap, num_ports, ret;
4486 enum rdma_link_layer ll;
4487 struct mlx5_ib_dev *dev;
4488
4489 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
4490 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
4491
4492 num_ports = max(MLX5_CAP_GEN(mdev, num_ports),
4493 MLX5_CAP_GEN(mdev, num_vhca_ports));
4494 dev = ib_alloc_device(mlx5_ib_dev, ib_dev);
4495 if (!dev)
4496 return -ENOMEM;
4497 dev->port = kcalloc(num_ports, sizeof(*dev->port),
4498 GFP_KERNEL);
4499 if (!dev->port) {
4500 ib_dealloc_device(&dev->ib_dev);
4501 return -ENOMEM;
4502 }
4503
4504 dev->mdev = mdev;
4505 dev->num_ports = num_ports;
4506
4507 if (ll == IB_LINK_LAYER_ETHERNET && !mlx5_get_roce_state(mdev))
4508 profile = &raw_eth_profile;
4509 else
4510 profile = &pf_profile;
4511
4512 ret = __mlx5_ib_add(dev, profile);
4513 if (ret) {
4514 kfree(dev->port);
4515 ib_dealloc_device(&dev->ib_dev);
4516 return ret;
4517 }
4518
4519 auxiliary_set_drvdata(adev, dev);
4520 return 0;
4521 }
4522
mlx5r_remove(struct auxiliary_device * adev)4523 static void mlx5r_remove(struct auxiliary_device *adev)
4524 {
4525 struct mlx5_ib_dev *dev;
4526
4527 dev = auxiliary_get_drvdata(adev);
4528 __mlx5_ib_remove(dev, dev->profile, MLX5_IB_STAGE_MAX);
4529 }
4530
4531 static const struct auxiliary_device_id mlx5r_mp_id_table[] = {
4532 { .name = MLX5_ADEV_NAME ".multiport", },
4533 {},
4534 };
4535
4536 static const struct auxiliary_device_id mlx5r_id_table[] = {
4537 { .name = MLX5_ADEV_NAME ".rdma", },
4538 {},
4539 };
4540
4541 MODULE_DEVICE_TABLE(auxiliary, mlx5r_mp_id_table);
4542 MODULE_DEVICE_TABLE(auxiliary, mlx5r_id_table);
4543
4544 static struct auxiliary_driver mlx5r_mp_driver = {
4545 .name = "multiport",
4546 .probe = mlx5r_mp_probe,
4547 .remove = mlx5r_mp_remove,
4548 .id_table = mlx5r_mp_id_table,
4549 };
4550
4551 static struct auxiliary_driver mlx5r_driver = {
4552 .name = "rdma",
4553 .probe = mlx5r_probe,
4554 .remove = mlx5r_remove,
4555 .id_table = mlx5r_id_table,
4556 };
4557
mlx5_ib_init(void)4558 static int __init mlx5_ib_init(void)
4559 {
4560 int ret;
4561
4562 xlt_emergency_page = (void *)__get_free_page(GFP_KERNEL);
4563 if (!xlt_emergency_page)
4564 return -ENOMEM;
4565
4566 mlx5_ib_event_wq = alloc_ordered_workqueue("mlx5_ib_event_wq", 0);
4567 if (!mlx5_ib_event_wq) {
4568 free_page((unsigned long)xlt_emergency_page);
4569 return -ENOMEM;
4570 }
4571
4572 ret = mlx5_ib_qp_event_init();
4573 if (ret)
4574 goto qp_event_err;
4575
4576 mlx5_ib_odp_init();
4577 ret = mlx5r_rep_init();
4578 if (ret)
4579 goto rep_err;
4580 ret = auxiliary_driver_register(&mlx5r_mp_driver);
4581 if (ret)
4582 goto mp_err;
4583 ret = auxiliary_driver_register(&mlx5r_driver);
4584 if (ret)
4585 goto drv_err;
4586 return 0;
4587
4588 drv_err:
4589 auxiliary_driver_unregister(&mlx5r_mp_driver);
4590 mp_err:
4591 mlx5r_rep_cleanup();
4592 rep_err:
4593 mlx5_ib_qp_event_cleanup();
4594 qp_event_err:
4595 destroy_workqueue(mlx5_ib_event_wq);
4596 free_page((unsigned long)xlt_emergency_page);
4597 return ret;
4598 }
4599
mlx5_ib_cleanup(void)4600 static void __exit mlx5_ib_cleanup(void)
4601 {
4602 auxiliary_driver_unregister(&mlx5r_driver);
4603 auxiliary_driver_unregister(&mlx5r_mp_driver);
4604 mlx5r_rep_cleanup();
4605
4606 mlx5_ib_qp_event_cleanup();
4607 destroy_workqueue(mlx5_ib_event_wq);
4608 free_page((unsigned long)xlt_emergency_page);
4609 }
4610
4611 module_init(mlx5_ib_init);
4612 module_exit(mlx5_ib_cleanup);
4613