1 /*
2 * Copyright (c) 2013-2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <linux/highmem.h>
34 #include <linux/errno.h>
35 #include <linux/pci.h>
36 #include <linux/dma-mapping.h>
37 #include <linux/slab.h>
38 #include <linux/delay.h>
39 #include <linux/random.h>
40 #include <linux/mlx5/driver.h>
41 #include <linux/mlx5/eq.h>
42 #include <linux/debugfs.h>
43
44 #include "mlx5_core.h"
45 #include "lib/eq.h"
46 #include "lib/tout.h"
47 #define CREATE_TRACE_POINTS
48 #include "diag/cmd_tracepoint.h"
49
50 struct mlx5_ifc_mbox_out_bits {
51 u8 status[0x8];
52 u8 reserved_at_8[0x18];
53
54 u8 syndrome[0x20];
55
56 u8 reserved_at_40[0x40];
57 };
58
59 struct mlx5_ifc_mbox_in_bits {
60 u8 opcode[0x10];
61 u8 uid[0x10];
62
63 u8 reserved_at_20[0x10];
64 u8 op_mod[0x10];
65
66 u8 reserved_at_40[0x40];
67 };
68
69 enum {
70 CMD_IF_REV = 5,
71 };
72
73 enum {
74 CMD_MODE_POLLING,
75 CMD_MODE_EVENTS
76 };
77
78 enum {
79 MLX5_CMD_DELIVERY_STAT_OK = 0x0,
80 MLX5_CMD_DELIVERY_STAT_SIGNAT_ERR = 0x1,
81 MLX5_CMD_DELIVERY_STAT_TOK_ERR = 0x2,
82 MLX5_CMD_DELIVERY_STAT_BAD_BLK_NUM_ERR = 0x3,
83 MLX5_CMD_DELIVERY_STAT_OUT_PTR_ALIGN_ERR = 0x4,
84 MLX5_CMD_DELIVERY_STAT_IN_PTR_ALIGN_ERR = 0x5,
85 MLX5_CMD_DELIVERY_STAT_FW_ERR = 0x6,
86 MLX5_CMD_DELIVERY_STAT_IN_LENGTH_ERR = 0x7,
87 MLX5_CMD_DELIVERY_STAT_OUT_LENGTH_ERR = 0x8,
88 MLX5_CMD_DELIVERY_STAT_RES_FLD_NOT_CLR_ERR = 0x9,
89 MLX5_CMD_DELIVERY_STAT_CMD_DESCR_ERR = 0x10,
90 };
91
in_to_opcode(void * in)92 static u16 in_to_opcode(void *in)
93 {
94 return MLX5_GET(mbox_in, in, opcode);
95 }
96
97 /* Returns true for opcodes that might be triggered very frequently and throttle
98 * the command interface. Limit their command slots usage.
99 */
mlx5_cmd_is_throttle_opcode(u16 op)100 static bool mlx5_cmd_is_throttle_opcode(u16 op)
101 {
102 switch (op) {
103 case MLX5_CMD_OP_CREATE_GENERAL_OBJECT:
104 case MLX5_CMD_OP_DESTROY_GENERAL_OBJECT:
105 case MLX5_CMD_OP_MODIFY_GENERAL_OBJECT:
106 case MLX5_CMD_OP_QUERY_GENERAL_OBJECT:
107 case MLX5_CMD_OP_SYNC_CRYPTO:
108 return true;
109 }
110 return false;
111 }
112
113 static struct mlx5_cmd_work_ent *
cmd_alloc_ent(struct mlx5_cmd * cmd,struct mlx5_cmd_msg * in,struct mlx5_cmd_msg * out,void * uout,int uout_size,mlx5_cmd_cbk_t cbk,void * context,int page_queue)114 cmd_alloc_ent(struct mlx5_cmd *cmd, struct mlx5_cmd_msg *in,
115 struct mlx5_cmd_msg *out, void *uout, int uout_size,
116 mlx5_cmd_cbk_t cbk, void *context, int page_queue)
117 {
118 gfp_t alloc_flags = cbk ? GFP_ATOMIC : GFP_KERNEL;
119 struct mlx5_cmd_work_ent *ent;
120
121 ent = kzalloc(sizeof(*ent), alloc_flags);
122 if (!ent)
123 return ERR_PTR(-ENOMEM);
124
125 ent->idx = -EINVAL;
126 ent->in = in;
127 ent->out = out;
128 ent->uout = uout;
129 ent->uout_size = uout_size;
130 ent->callback = cbk;
131 ent->context = context;
132 ent->cmd = cmd;
133 ent->page_queue = page_queue;
134 ent->op = in_to_opcode(in->first.data);
135 refcount_set(&ent->refcnt, 1);
136
137 return ent;
138 }
139
cmd_free_ent(struct mlx5_cmd_work_ent * ent)140 static void cmd_free_ent(struct mlx5_cmd_work_ent *ent)
141 {
142 kfree(ent);
143 }
144
alloc_token(struct mlx5_cmd * cmd)145 static u8 alloc_token(struct mlx5_cmd *cmd)
146 {
147 u8 token;
148
149 spin_lock(&cmd->token_lock);
150 cmd->token++;
151 if (cmd->token == 0)
152 cmd->token++;
153 token = cmd->token;
154 spin_unlock(&cmd->token_lock);
155
156 return token;
157 }
158
cmd_alloc_index(struct mlx5_cmd * cmd,struct mlx5_cmd_work_ent * ent)159 static int cmd_alloc_index(struct mlx5_cmd *cmd, struct mlx5_cmd_work_ent *ent)
160 {
161 unsigned long flags;
162 int ret;
163
164 spin_lock_irqsave(&cmd->alloc_lock, flags);
165 ret = find_first_bit(&cmd->vars.bitmask, cmd->vars.max_reg_cmds);
166 if (ret < cmd->vars.max_reg_cmds) {
167 clear_bit(ret, &cmd->vars.bitmask);
168 ent->idx = ret;
169 cmd->ent_arr[ent->idx] = ent;
170 }
171 spin_unlock_irqrestore(&cmd->alloc_lock, flags);
172
173 return ret < cmd->vars.max_reg_cmds ? ret : -ENOMEM;
174 }
175
cmd_free_index(struct mlx5_cmd * cmd,int idx)176 static void cmd_free_index(struct mlx5_cmd *cmd, int idx)
177 {
178 lockdep_assert_held(&cmd->alloc_lock);
179 set_bit(idx, &cmd->vars.bitmask);
180 }
181
cmd_ent_get(struct mlx5_cmd_work_ent * ent)182 static void cmd_ent_get(struct mlx5_cmd_work_ent *ent)
183 {
184 refcount_inc(&ent->refcnt);
185 }
186
cmd_ent_put(struct mlx5_cmd_work_ent * ent)187 static void cmd_ent_put(struct mlx5_cmd_work_ent *ent)
188 {
189 struct mlx5_cmd *cmd = ent->cmd;
190 unsigned long flags;
191
192 spin_lock_irqsave(&cmd->alloc_lock, flags);
193 if (!refcount_dec_and_test(&ent->refcnt))
194 goto out;
195
196 if (ent->idx >= 0) {
197 cmd_free_index(cmd, ent->idx);
198 up(ent->page_queue ? &cmd->vars.pages_sem : &cmd->vars.sem);
199 }
200
201 cmd_free_ent(ent);
202 out:
203 spin_unlock_irqrestore(&cmd->alloc_lock, flags);
204 }
205
get_inst(struct mlx5_cmd * cmd,int idx)206 static struct mlx5_cmd_layout *get_inst(struct mlx5_cmd *cmd, int idx)
207 {
208 return cmd->cmd_buf + (idx << cmd->vars.log_stride);
209 }
210
mlx5_calc_cmd_blocks(struct mlx5_cmd_msg * msg)211 static int mlx5_calc_cmd_blocks(struct mlx5_cmd_msg *msg)
212 {
213 int size = msg->len;
214 int blen = size - min_t(int, sizeof(msg->first.data), size);
215
216 return DIV_ROUND_UP(blen, MLX5_CMD_DATA_BLOCK_SIZE);
217 }
218
xor8_buf(void * buf,size_t offset,int len)219 static u8 xor8_buf(void *buf, size_t offset, int len)
220 {
221 u8 *ptr = buf;
222 u8 sum = 0;
223 int i;
224 int end = len + offset;
225
226 for (i = offset; i < end; i++)
227 sum ^= ptr[i];
228
229 return sum;
230 }
231
verify_block_sig(struct mlx5_cmd_prot_block * block)232 static int verify_block_sig(struct mlx5_cmd_prot_block *block)
233 {
234 size_t rsvd0_off = offsetof(struct mlx5_cmd_prot_block, rsvd0);
235 int xor_len = sizeof(*block) - sizeof(block->data) - 1;
236
237 if (xor8_buf(block, rsvd0_off, xor_len) != 0xff)
238 return -EHWPOISON;
239
240 if (xor8_buf(block, 0, sizeof(*block)) != 0xff)
241 return -EHWPOISON;
242
243 return 0;
244 }
245
calc_block_sig(struct mlx5_cmd_prot_block * block)246 static void calc_block_sig(struct mlx5_cmd_prot_block *block)
247 {
248 int ctrl_xor_len = sizeof(*block) - sizeof(block->data) - 2;
249 size_t rsvd0_off = offsetof(struct mlx5_cmd_prot_block, rsvd0);
250
251 block->ctrl_sig = ~xor8_buf(block, rsvd0_off, ctrl_xor_len);
252 block->sig = ~xor8_buf(block, 0, sizeof(*block) - 1);
253 }
254
calc_chain_sig(struct mlx5_cmd_msg * msg)255 static void calc_chain_sig(struct mlx5_cmd_msg *msg)
256 {
257 struct mlx5_cmd_mailbox *next = msg->next;
258 int n = mlx5_calc_cmd_blocks(msg);
259 int i = 0;
260
261 for (i = 0; i < n && next; i++) {
262 calc_block_sig(next->buf);
263 next = next->next;
264 }
265 }
266
set_signature(struct mlx5_cmd_work_ent * ent,int csum)267 static void set_signature(struct mlx5_cmd_work_ent *ent, int csum)
268 {
269 ent->lay->sig = ~xor8_buf(ent->lay, 0, sizeof(*ent->lay));
270 if (csum) {
271 calc_chain_sig(ent->in);
272 calc_chain_sig(ent->out);
273 }
274 }
275
poll_timeout(struct mlx5_cmd_work_ent * ent)276 static void poll_timeout(struct mlx5_cmd_work_ent *ent)
277 {
278 struct mlx5_core_dev *dev = container_of(ent->cmd, struct mlx5_core_dev, cmd);
279 u64 cmd_to_ms = mlx5_tout_ms(dev, CMD);
280 unsigned long poll_end;
281 u8 own;
282
283 poll_end = jiffies + msecs_to_jiffies(cmd_to_ms + 1000);
284
285 do {
286 own = READ_ONCE(ent->lay->status_own);
287 if (!(own & CMD_OWNER_HW)) {
288 ent->ret = 0;
289 return;
290 }
291 cond_resched();
292 } while (time_before(jiffies, poll_end));
293
294 ent->ret = -ETIMEDOUT;
295 }
296
verify_signature(struct mlx5_cmd_work_ent * ent)297 static int verify_signature(struct mlx5_cmd_work_ent *ent)
298 {
299 struct mlx5_cmd_mailbox *next = ent->out->next;
300 int n = mlx5_calc_cmd_blocks(ent->out);
301 int err;
302 u8 sig;
303 int i = 0;
304
305 sig = xor8_buf(ent->lay, 0, sizeof(*ent->lay));
306 if (sig != 0xff)
307 return -EHWPOISON;
308
309 for (i = 0; i < n && next; i++) {
310 err = verify_block_sig(next->buf);
311 if (err)
312 return -EHWPOISON;
313
314 next = next->next;
315 }
316
317 return 0;
318 }
319
dump_buf(void * buf,int size,int data_only,int offset,int idx)320 static void dump_buf(void *buf, int size, int data_only, int offset, int idx)
321 {
322 __be32 *p = buf;
323 int i;
324
325 for (i = 0; i < size; i += 16) {
326 pr_debug("cmd[%d]: %03x: %08x %08x %08x %08x\n", idx, offset,
327 be32_to_cpu(p[0]), be32_to_cpu(p[1]),
328 be32_to_cpu(p[2]), be32_to_cpu(p[3]));
329 p += 4;
330 offset += 16;
331 }
332 if (!data_only)
333 pr_debug("\n");
334 }
335
mlx5_internal_err_ret_value(struct mlx5_core_dev * dev,u16 op,u32 * synd,u8 * status)336 static int mlx5_internal_err_ret_value(struct mlx5_core_dev *dev, u16 op,
337 u32 *synd, u8 *status)
338 {
339 *synd = 0;
340 *status = 0;
341
342 switch (op) {
343 case MLX5_CMD_OP_TEARDOWN_HCA:
344 case MLX5_CMD_OP_DISABLE_HCA:
345 case MLX5_CMD_OP_MANAGE_PAGES:
346 case MLX5_CMD_OP_DESTROY_MKEY:
347 case MLX5_CMD_OP_DESTROY_EQ:
348 case MLX5_CMD_OP_DESTROY_CQ:
349 case MLX5_CMD_OP_DESTROY_QP:
350 case MLX5_CMD_OP_DESTROY_PSV:
351 case MLX5_CMD_OP_DESTROY_SRQ:
352 case MLX5_CMD_OP_DESTROY_XRC_SRQ:
353 case MLX5_CMD_OP_DESTROY_XRQ:
354 case MLX5_CMD_OP_DESTROY_DCT:
355 case MLX5_CMD_OP_DEALLOC_Q_COUNTER:
356 case MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT:
357 case MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT:
358 case MLX5_CMD_OP_DEALLOC_PD:
359 case MLX5_CMD_OP_DEALLOC_UAR:
360 case MLX5_CMD_OP_DETACH_FROM_MCG:
361 case MLX5_CMD_OP_DEALLOC_XRCD:
362 case MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN:
363 case MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT:
364 case MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY:
365 case MLX5_CMD_OP_DESTROY_LAG:
366 case MLX5_CMD_OP_DESTROY_VPORT_LAG:
367 case MLX5_CMD_OP_DESTROY_TIR:
368 case MLX5_CMD_OP_DESTROY_SQ:
369 case MLX5_CMD_OP_DESTROY_RQ:
370 case MLX5_CMD_OP_DESTROY_RMP:
371 case MLX5_CMD_OP_DESTROY_TIS:
372 case MLX5_CMD_OP_DESTROY_RQT:
373 case MLX5_CMD_OP_DESTROY_FLOW_TABLE:
374 case MLX5_CMD_OP_DESTROY_FLOW_GROUP:
375 case MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY:
376 case MLX5_CMD_OP_DEALLOC_FLOW_COUNTER:
377 case MLX5_CMD_OP_2ERR_QP:
378 case MLX5_CMD_OP_2RST_QP:
379 case MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT:
380 case MLX5_CMD_OP_MODIFY_FLOW_TABLE:
381 case MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY:
382 case MLX5_CMD_OP_SET_FLOW_TABLE_ROOT:
383 case MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT:
384 case MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT:
385 case MLX5_CMD_OP_FPGA_DESTROY_QP:
386 case MLX5_CMD_OP_DESTROY_GENERAL_OBJECT:
387 case MLX5_CMD_OP_DEALLOC_MEMIC:
388 case MLX5_CMD_OP_PAGE_FAULT_RESUME:
389 case MLX5_CMD_OP_QUERY_ESW_FUNCTIONS:
390 case MLX5_CMD_OP_DEALLOC_SF:
391 case MLX5_CMD_OP_DESTROY_UCTX:
392 case MLX5_CMD_OP_DESTROY_UMEM:
393 case MLX5_CMD_OP_MODIFY_RQT:
394 return MLX5_CMD_STAT_OK;
395
396 case MLX5_CMD_OP_QUERY_HCA_CAP:
397 case MLX5_CMD_OP_QUERY_ADAPTER:
398 case MLX5_CMD_OP_INIT_HCA:
399 case MLX5_CMD_OP_ENABLE_HCA:
400 case MLX5_CMD_OP_QUERY_PAGES:
401 case MLX5_CMD_OP_SET_HCA_CAP:
402 case MLX5_CMD_OP_QUERY_ISSI:
403 case MLX5_CMD_OP_SET_ISSI:
404 case MLX5_CMD_OP_CREATE_MKEY:
405 case MLX5_CMD_OP_QUERY_MKEY:
406 case MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS:
407 case MLX5_CMD_OP_CREATE_EQ:
408 case MLX5_CMD_OP_QUERY_EQ:
409 case MLX5_CMD_OP_GEN_EQE:
410 case MLX5_CMD_OP_CREATE_CQ:
411 case MLX5_CMD_OP_QUERY_CQ:
412 case MLX5_CMD_OP_MODIFY_CQ:
413 case MLX5_CMD_OP_CREATE_QP:
414 case MLX5_CMD_OP_RST2INIT_QP:
415 case MLX5_CMD_OP_INIT2RTR_QP:
416 case MLX5_CMD_OP_RTR2RTS_QP:
417 case MLX5_CMD_OP_RTS2RTS_QP:
418 case MLX5_CMD_OP_SQERR2RTS_QP:
419 case MLX5_CMD_OP_QUERY_QP:
420 case MLX5_CMD_OP_SQD_RTS_QP:
421 case MLX5_CMD_OP_INIT2INIT_QP:
422 case MLX5_CMD_OP_CREATE_PSV:
423 case MLX5_CMD_OP_CREATE_SRQ:
424 case MLX5_CMD_OP_QUERY_SRQ:
425 case MLX5_CMD_OP_ARM_RQ:
426 case MLX5_CMD_OP_CREATE_XRC_SRQ:
427 case MLX5_CMD_OP_QUERY_XRC_SRQ:
428 case MLX5_CMD_OP_ARM_XRC_SRQ:
429 case MLX5_CMD_OP_CREATE_XRQ:
430 case MLX5_CMD_OP_QUERY_XRQ:
431 case MLX5_CMD_OP_ARM_XRQ:
432 case MLX5_CMD_OP_CREATE_DCT:
433 case MLX5_CMD_OP_DRAIN_DCT:
434 case MLX5_CMD_OP_QUERY_DCT:
435 case MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION:
436 case MLX5_CMD_OP_QUERY_VPORT_STATE:
437 case MLX5_CMD_OP_MODIFY_VPORT_STATE:
438 case MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT:
439 case MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT:
440 case MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT:
441 case MLX5_CMD_OP_QUERY_ROCE_ADDRESS:
442 case MLX5_CMD_OP_SET_ROCE_ADDRESS:
443 case MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT:
444 case MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT:
445 case MLX5_CMD_OP_QUERY_HCA_VPORT_GID:
446 case MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY:
447 case MLX5_CMD_OP_QUERY_VNIC_ENV:
448 case MLX5_CMD_OP_QUERY_VPORT_COUNTER:
449 case MLX5_CMD_OP_ALLOC_Q_COUNTER:
450 case MLX5_CMD_OP_QUERY_Q_COUNTER:
451 case MLX5_CMD_OP_SET_MONITOR_COUNTER:
452 case MLX5_CMD_OP_ARM_MONITOR_COUNTER:
453 case MLX5_CMD_OP_SET_PP_RATE_LIMIT:
454 case MLX5_CMD_OP_QUERY_RATE_LIMIT:
455 case MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT:
456 case MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT:
457 case MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT:
458 case MLX5_CMD_OP_CREATE_QOS_PARA_VPORT:
459 case MLX5_CMD_OP_ALLOC_PD:
460 case MLX5_CMD_OP_ALLOC_UAR:
461 case MLX5_CMD_OP_CONFIG_INT_MODERATION:
462 case MLX5_CMD_OP_ACCESS_REG:
463 case MLX5_CMD_OP_ATTACH_TO_MCG:
464 case MLX5_CMD_OP_GET_DROPPED_PACKET_LOG:
465 case MLX5_CMD_OP_MAD_IFC:
466 case MLX5_CMD_OP_QUERY_MAD_DEMUX:
467 case MLX5_CMD_OP_SET_MAD_DEMUX:
468 case MLX5_CMD_OP_NOP:
469 case MLX5_CMD_OP_ALLOC_XRCD:
470 case MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN:
471 case MLX5_CMD_OP_QUERY_CONG_STATUS:
472 case MLX5_CMD_OP_MODIFY_CONG_STATUS:
473 case MLX5_CMD_OP_QUERY_CONG_PARAMS:
474 case MLX5_CMD_OP_MODIFY_CONG_PARAMS:
475 case MLX5_CMD_OP_QUERY_CONG_STATISTICS:
476 case MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT:
477 case MLX5_CMD_OP_SET_L2_TABLE_ENTRY:
478 case MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY:
479 case MLX5_CMD_OP_CREATE_LAG:
480 case MLX5_CMD_OP_MODIFY_LAG:
481 case MLX5_CMD_OP_QUERY_LAG:
482 case MLX5_CMD_OP_CREATE_VPORT_LAG:
483 case MLX5_CMD_OP_CREATE_TIR:
484 case MLX5_CMD_OP_MODIFY_TIR:
485 case MLX5_CMD_OP_QUERY_TIR:
486 case MLX5_CMD_OP_CREATE_SQ:
487 case MLX5_CMD_OP_MODIFY_SQ:
488 case MLX5_CMD_OP_QUERY_SQ:
489 case MLX5_CMD_OP_CREATE_RQ:
490 case MLX5_CMD_OP_MODIFY_RQ:
491 case MLX5_CMD_OP_QUERY_RQ:
492 case MLX5_CMD_OP_CREATE_RMP:
493 case MLX5_CMD_OP_MODIFY_RMP:
494 case MLX5_CMD_OP_QUERY_RMP:
495 case MLX5_CMD_OP_CREATE_TIS:
496 case MLX5_CMD_OP_MODIFY_TIS:
497 case MLX5_CMD_OP_QUERY_TIS:
498 case MLX5_CMD_OP_CREATE_RQT:
499 case MLX5_CMD_OP_QUERY_RQT:
500
501 case MLX5_CMD_OP_CREATE_FLOW_TABLE:
502 case MLX5_CMD_OP_QUERY_FLOW_TABLE:
503 case MLX5_CMD_OP_CREATE_FLOW_GROUP:
504 case MLX5_CMD_OP_QUERY_FLOW_GROUP:
505 case MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY:
506 case MLX5_CMD_OP_ALLOC_FLOW_COUNTER:
507 case MLX5_CMD_OP_QUERY_FLOW_COUNTER:
508 case MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT:
509 case MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT:
510 case MLX5_CMD_OP_FPGA_CREATE_QP:
511 case MLX5_CMD_OP_FPGA_MODIFY_QP:
512 case MLX5_CMD_OP_FPGA_QUERY_QP:
513 case MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS:
514 case MLX5_CMD_OP_CREATE_GENERAL_OBJECT:
515 case MLX5_CMD_OP_MODIFY_GENERAL_OBJECT:
516 case MLX5_CMD_OP_QUERY_GENERAL_OBJECT:
517 case MLX5_CMD_OP_CREATE_UCTX:
518 case MLX5_CMD_OP_CREATE_UMEM:
519 case MLX5_CMD_OP_ALLOC_MEMIC:
520 case MLX5_CMD_OP_MODIFY_XRQ:
521 case MLX5_CMD_OP_RELEASE_XRQ_ERROR:
522 case MLX5_CMD_OP_QUERY_VHCA_STATE:
523 case MLX5_CMD_OP_MODIFY_VHCA_STATE:
524 case MLX5_CMD_OP_ALLOC_SF:
525 case MLX5_CMD_OP_SUSPEND_VHCA:
526 case MLX5_CMD_OP_RESUME_VHCA:
527 case MLX5_CMD_OP_QUERY_VHCA_MIGRATION_STATE:
528 case MLX5_CMD_OP_SAVE_VHCA_STATE:
529 case MLX5_CMD_OP_LOAD_VHCA_STATE:
530 case MLX5_CMD_OP_SYNC_CRYPTO:
531 *status = MLX5_DRIVER_STATUS_ABORTED;
532 *synd = MLX5_DRIVER_SYND;
533 return -ENOLINK;
534 default:
535 mlx5_core_err(dev, "Unknown FW command (%d)\n", op);
536 return -EINVAL;
537 }
538 }
539
mlx5_command_str(int command)540 const char *mlx5_command_str(int command)
541 {
542 #define MLX5_COMMAND_STR_CASE(__cmd) case MLX5_CMD_OP_ ## __cmd: return #__cmd
543
544 switch (command) {
545 MLX5_COMMAND_STR_CASE(QUERY_HCA_CAP);
546 MLX5_COMMAND_STR_CASE(QUERY_ADAPTER);
547 MLX5_COMMAND_STR_CASE(INIT_HCA);
548 MLX5_COMMAND_STR_CASE(TEARDOWN_HCA);
549 MLX5_COMMAND_STR_CASE(ENABLE_HCA);
550 MLX5_COMMAND_STR_CASE(DISABLE_HCA);
551 MLX5_COMMAND_STR_CASE(QUERY_PAGES);
552 MLX5_COMMAND_STR_CASE(MANAGE_PAGES);
553 MLX5_COMMAND_STR_CASE(SET_HCA_CAP);
554 MLX5_COMMAND_STR_CASE(QUERY_ISSI);
555 MLX5_COMMAND_STR_CASE(SET_ISSI);
556 MLX5_COMMAND_STR_CASE(SET_DRIVER_VERSION);
557 MLX5_COMMAND_STR_CASE(CREATE_MKEY);
558 MLX5_COMMAND_STR_CASE(QUERY_MKEY);
559 MLX5_COMMAND_STR_CASE(DESTROY_MKEY);
560 MLX5_COMMAND_STR_CASE(QUERY_SPECIAL_CONTEXTS);
561 MLX5_COMMAND_STR_CASE(PAGE_FAULT_RESUME);
562 MLX5_COMMAND_STR_CASE(CREATE_EQ);
563 MLX5_COMMAND_STR_CASE(DESTROY_EQ);
564 MLX5_COMMAND_STR_CASE(QUERY_EQ);
565 MLX5_COMMAND_STR_CASE(GEN_EQE);
566 MLX5_COMMAND_STR_CASE(CREATE_CQ);
567 MLX5_COMMAND_STR_CASE(DESTROY_CQ);
568 MLX5_COMMAND_STR_CASE(QUERY_CQ);
569 MLX5_COMMAND_STR_CASE(MODIFY_CQ);
570 MLX5_COMMAND_STR_CASE(CREATE_QP);
571 MLX5_COMMAND_STR_CASE(DESTROY_QP);
572 MLX5_COMMAND_STR_CASE(RST2INIT_QP);
573 MLX5_COMMAND_STR_CASE(INIT2RTR_QP);
574 MLX5_COMMAND_STR_CASE(RTR2RTS_QP);
575 MLX5_COMMAND_STR_CASE(RTS2RTS_QP);
576 MLX5_COMMAND_STR_CASE(SQERR2RTS_QP);
577 MLX5_COMMAND_STR_CASE(2ERR_QP);
578 MLX5_COMMAND_STR_CASE(2RST_QP);
579 MLX5_COMMAND_STR_CASE(QUERY_QP);
580 MLX5_COMMAND_STR_CASE(SQD_RTS_QP);
581 MLX5_COMMAND_STR_CASE(INIT2INIT_QP);
582 MLX5_COMMAND_STR_CASE(CREATE_PSV);
583 MLX5_COMMAND_STR_CASE(DESTROY_PSV);
584 MLX5_COMMAND_STR_CASE(CREATE_SRQ);
585 MLX5_COMMAND_STR_CASE(DESTROY_SRQ);
586 MLX5_COMMAND_STR_CASE(QUERY_SRQ);
587 MLX5_COMMAND_STR_CASE(ARM_RQ);
588 MLX5_COMMAND_STR_CASE(CREATE_XRC_SRQ);
589 MLX5_COMMAND_STR_CASE(DESTROY_XRC_SRQ);
590 MLX5_COMMAND_STR_CASE(QUERY_XRC_SRQ);
591 MLX5_COMMAND_STR_CASE(ARM_XRC_SRQ);
592 MLX5_COMMAND_STR_CASE(CREATE_DCT);
593 MLX5_COMMAND_STR_CASE(DESTROY_DCT);
594 MLX5_COMMAND_STR_CASE(DRAIN_DCT);
595 MLX5_COMMAND_STR_CASE(QUERY_DCT);
596 MLX5_COMMAND_STR_CASE(ARM_DCT_FOR_KEY_VIOLATION);
597 MLX5_COMMAND_STR_CASE(QUERY_VPORT_STATE);
598 MLX5_COMMAND_STR_CASE(MODIFY_VPORT_STATE);
599 MLX5_COMMAND_STR_CASE(QUERY_ESW_VPORT_CONTEXT);
600 MLX5_COMMAND_STR_CASE(MODIFY_ESW_VPORT_CONTEXT);
601 MLX5_COMMAND_STR_CASE(QUERY_NIC_VPORT_CONTEXT);
602 MLX5_COMMAND_STR_CASE(MODIFY_NIC_VPORT_CONTEXT);
603 MLX5_COMMAND_STR_CASE(QUERY_ROCE_ADDRESS);
604 MLX5_COMMAND_STR_CASE(SET_ROCE_ADDRESS);
605 MLX5_COMMAND_STR_CASE(QUERY_HCA_VPORT_CONTEXT);
606 MLX5_COMMAND_STR_CASE(MODIFY_HCA_VPORT_CONTEXT);
607 MLX5_COMMAND_STR_CASE(QUERY_HCA_VPORT_GID);
608 MLX5_COMMAND_STR_CASE(QUERY_HCA_VPORT_PKEY);
609 MLX5_COMMAND_STR_CASE(QUERY_VNIC_ENV);
610 MLX5_COMMAND_STR_CASE(QUERY_VPORT_COUNTER);
611 MLX5_COMMAND_STR_CASE(ALLOC_Q_COUNTER);
612 MLX5_COMMAND_STR_CASE(DEALLOC_Q_COUNTER);
613 MLX5_COMMAND_STR_CASE(QUERY_Q_COUNTER);
614 MLX5_COMMAND_STR_CASE(SET_MONITOR_COUNTER);
615 MLX5_COMMAND_STR_CASE(ARM_MONITOR_COUNTER);
616 MLX5_COMMAND_STR_CASE(SET_PP_RATE_LIMIT);
617 MLX5_COMMAND_STR_CASE(QUERY_RATE_LIMIT);
618 MLX5_COMMAND_STR_CASE(CREATE_SCHEDULING_ELEMENT);
619 MLX5_COMMAND_STR_CASE(DESTROY_SCHEDULING_ELEMENT);
620 MLX5_COMMAND_STR_CASE(QUERY_SCHEDULING_ELEMENT);
621 MLX5_COMMAND_STR_CASE(MODIFY_SCHEDULING_ELEMENT);
622 MLX5_COMMAND_STR_CASE(CREATE_QOS_PARA_VPORT);
623 MLX5_COMMAND_STR_CASE(DESTROY_QOS_PARA_VPORT);
624 MLX5_COMMAND_STR_CASE(ALLOC_PD);
625 MLX5_COMMAND_STR_CASE(DEALLOC_PD);
626 MLX5_COMMAND_STR_CASE(ALLOC_UAR);
627 MLX5_COMMAND_STR_CASE(DEALLOC_UAR);
628 MLX5_COMMAND_STR_CASE(CONFIG_INT_MODERATION);
629 MLX5_COMMAND_STR_CASE(ACCESS_REG);
630 MLX5_COMMAND_STR_CASE(ATTACH_TO_MCG);
631 MLX5_COMMAND_STR_CASE(DETACH_FROM_MCG);
632 MLX5_COMMAND_STR_CASE(GET_DROPPED_PACKET_LOG);
633 MLX5_COMMAND_STR_CASE(MAD_IFC);
634 MLX5_COMMAND_STR_CASE(QUERY_MAD_DEMUX);
635 MLX5_COMMAND_STR_CASE(SET_MAD_DEMUX);
636 MLX5_COMMAND_STR_CASE(NOP);
637 MLX5_COMMAND_STR_CASE(ALLOC_XRCD);
638 MLX5_COMMAND_STR_CASE(DEALLOC_XRCD);
639 MLX5_COMMAND_STR_CASE(ALLOC_TRANSPORT_DOMAIN);
640 MLX5_COMMAND_STR_CASE(DEALLOC_TRANSPORT_DOMAIN);
641 MLX5_COMMAND_STR_CASE(QUERY_CONG_STATUS);
642 MLX5_COMMAND_STR_CASE(MODIFY_CONG_STATUS);
643 MLX5_COMMAND_STR_CASE(QUERY_CONG_PARAMS);
644 MLX5_COMMAND_STR_CASE(MODIFY_CONG_PARAMS);
645 MLX5_COMMAND_STR_CASE(QUERY_CONG_STATISTICS);
646 MLX5_COMMAND_STR_CASE(ADD_VXLAN_UDP_DPORT);
647 MLX5_COMMAND_STR_CASE(DELETE_VXLAN_UDP_DPORT);
648 MLX5_COMMAND_STR_CASE(SET_L2_TABLE_ENTRY);
649 MLX5_COMMAND_STR_CASE(QUERY_L2_TABLE_ENTRY);
650 MLX5_COMMAND_STR_CASE(DELETE_L2_TABLE_ENTRY);
651 MLX5_COMMAND_STR_CASE(SET_WOL_ROL);
652 MLX5_COMMAND_STR_CASE(QUERY_WOL_ROL);
653 MLX5_COMMAND_STR_CASE(CREATE_LAG);
654 MLX5_COMMAND_STR_CASE(MODIFY_LAG);
655 MLX5_COMMAND_STR_CASE(QUERY_LAG);
656 MLX5_COMMAND_STR_CASE(DESTROY_LAG);
657 MLX5_COMMAND_STR_CASE(CREATE_VPORT_LAG);
658 MLX5_COMMAND_STR_CASE(DESTROY_VPORT_LAG);
659 MLX5_COMMAND_STR_CASE(CREATE_TIR);
660 MLX5_COMMAND_STR_CASE(MODIFY_TIR);
661 MLX5_COMMAND_STR_CASE(DESTROY_TIR);
662 MLX5_COMMAND_STR_CASE(QUERY_TIR);
663 MLX5_COMMAND_STR_CASE(CREATE_SQ);
664 MLX5_COMMAND_STR_CASE(MODIFY_SQ);
665 MLX5_COMMAND_STR_CASE(DESTROY_SQ);
666 MLX5_COMMAND_STR_CASE(QUERY_SQ);
667 MLX5_COMMAND_STR_CASE(CREATE_RQ);
668 MLX5_COMMAND_STR_CASE(MODIFY_RQ);
669 MLX5_COMMAND_STR_CASE(DESTROY_RQ);
670 MLX5_COMMAND_STR_CASE(QUERY_RQ);
671 MLX5_COMMAND_STR_CASE(CREATE_RMP);
672 MLX5_COMMAND_STR_CASE(MODIFY_RMP);
673 MLX5_COMMAND_STR_CASE(DESTROY_RMP);
674 MLX5_COMMAND_STR_CASE(QUERY_RMP);
675 MLX5_COMMAND_STR_CASE(CREATE_TIS);
676 MLX5_COMMAND_STR_CASE(MODIFY_TIS);
677 MLX5_COMMAND_STR_CASE(DESTROY_TIS);
678 MLX5_COMMAND_STR_CASE(QUERY_TIS);
679 MLX5_COMMAND_STR_CASE(CREATE_RQT);
680 MLX5_COMMAND_STR_CASE(MODIFY_RQT);
681 MLX5_COMMAND_STR_CASE(DESTROY_RQT);
682 MLX5_COMMAND_STR_CASE(QUERY_RQT);
683 MLX5_COMMAND_STR_CASE(SET_FLOW_TABLE_ROOT);
684 MLX5_COMMAND_STR_CASE(CREATE_FLOW_TABLE);
685 MLX5_COMMAND_STR_CASE(DESTROY_FLOW_TABLE);
686 MLX5_COMMAND_STR_CASE(QUERY_FLOW_TABLE);
687 MLX5_COMMAND_STR_CASE(CREATE_FLOW_GROUP);
688 MLX5_COMMAND_STR_CASE(DESTROY_FLOW_GROUP);
689 MLX5_COMMAND_STR_CASE(QUERY_FLOW_GROUP);
690 MLX5_COMMAND_STR_CASE(SET_FLOW_TABLE_ENTRY);
691 MLX5_COMMAND_STR_CASE(QUERY_FLOW_TABLE_ENTRY);
692 MLX5_COMMAND_STR_CASE(DELETE_FLOW_TABLE_ENTRY);
693 MLX5_COMMAND_STR_CASE(ALLOC_FLOW_COUNTER);
694 MLX5_COMMAND_STR_CASE(DEALLOC_FLOW_COUNTER);
695 MLX5_COMMAND_STR_CASE(QUERY_FLOW_COUNTER);
696 MLX5_COMMAND_STR_CASE(MODIFY_FLOW_TABLE);
697 MLX5_COMMAND_STR_CASE(ALLOC_PACKET_REFORMAT_CONTEXT);
698 MLX5_COMMAND_STR_CASE(DEALLOC_PACKET_REFORMAT_CONTEXT);
699 MLX5_COMMAND_STR_CASE(ALLOC_MODIFY_HEADER_CONTEXT);
700 MLX5_COMMAND_STR_CASE(DEALLOC_MODIFY_HEADER_CONTEXT);
701 MLX5_COMMAND_STR_CASE(FPGA_CREATE_QP);
702 MLX5_COMMAND_STR_CASE(FPGA_MODIFY_QP);
703 MLX5_COMMAND_STR_CASE(FPGA_QUERY_QP);
704 MLX5_COMMAND_STR_CASE(FPGA_QUERY_QP_COUNTERS);
705 MLX5_COMMAND_STR_CASE(FPGA_DESTROY_QP);
706 MLX5_COMMAND_STR_CASE(CREATE_XRQ);
707 MLX5_COMMAND_STR_CASE(DESTROY_XRQ);
708 MLX5_COMMAND_STR_CASE(QUERY_XRQ);
709 MLX5_COMMAND_STR_CASE(ARM_XRQ);
710 MLX5_COMMAND_STR_CASE(CREATE_GENERAL_OBJECT);
711 MLX5_COMMAND_STR_CASE(DESTROY_GENERAL_OBJECT);
712 MLX5_COMMAND_STR_CASE(MODIFY_GENERAL_OBJECT);
713 MLX5_COMMAND_STR_CASE(QUERY_GENERAL_OBJECT);
714 MLX5_COMMAND_STR_CASE(QUERY_MODIFY_HEADER_CONTEXT);
715 MLX5_COMMAND_STR_CASE(ALLOC_MEMIC);
716 MLX5_COMMAND_STR_CASE(DEALLOC_MEMIC);
717 MLX5_COMMAND_STR_CASE(QUERY_ESW_FUNCTIONS);
718 MLX5_COMMAND_STR_CASE(CREATE_UCTX);
719 MLX5_COMMAND_STR_CASE(DESTROY_UCTX);
720 MLX5_COMMAND_STR_CASE(CREATE_UMEM);
721 MLX5_COMMAND_STR_CASE(DESTROY_UMEM);
722 MLX5_COMMAND_STR_CASE(RELEASE_XRQ_ERROR);
723 MLX5_COMMAND_STR_CASE(MODIFY_XRQ);
724 MLX5_COMMAND_STR_CASE(QUERY_VHCA_STATE);
725 MLX5_COMMAND_STR_CASE(MODIFY_VHCA_STATE);
726 MLX5_COMMAND_STR_CASE(ALLOC_SF);
727 MLX5_COMMAND_STR_CASE(DEALLOC_SF);
728 MLX5_COMMAND_STR_CASE(SUSPEND_VHCA);
729 MLX5_COMMAND_STR_CASE(RESUME_VHCA);
730 MLX5_COMMAND_STR_CASE(QUERY_VHCA_MIGRATION_STATE);
731 MLX5_COMMAND_STR_CASE(SAVE_VHCA_STATE);
732 MLX5_COMMAND_STR_CASE(LOAD_VHCA_STATE);
733 MLX5_COMMAND_STR_CASE(SYNC_CRYPTO);
734 default: return "unknown command opcode";
735 }
736 }
737
cmd_status_str(u8 status)738 static const char *cmd_status_str(u8 status)
739 {
740 switch (status) {
741 case MLX5_CMD_STAT_OK:
742 return "OK";
743 case MLX5_CMD_STAT_INT_ERR:
744 return "internal error";
745 case MLX5_CMD_STAT_BAD_OP_ERR:
746 return "bad operation";
747 case MLX5_CMD_STAT_BAD_PARAM_ERR:
748 return "bad parameter";
749 case MLX5_CMD_STAT_BAD_SYS_STATE_ERR:
750 return "bad system state";
751 case MLX5_CMD_STAT_BAD_RES_ERR:
752 return "bad resource";
753 case MLX5_CMD_STAT_RES_BUSY:
754 return "resource busy";
755 case MLX5_CMD_STAT_LIM_ERR:
756 return "limits exceeded";
757 case MLX5_CMD_STAT_BAD_RES_STATE_ERR:
758 return "bad resource state";
759 case MLX5_CMD_STAT_IX_ERR:
760 return "bad index";
761 case MLX5_CMD_STAT_NO_RES_ERR:
762 return "no resources";
763 case MLX5_CMD_STAT_BAD_INP_LEN_ERR:
764 return "bad input length";
765 case MLX5_CMD_STAT_BAD_OUTP_LEN_ERR:
766 return "bad output length";
767 case MLX5_CMD_STAT_BAD_QP_STATE_ERR:
768 return "bad QP state";
769 case MLX5_CMD_STAT_BAD_PKT_ERR:
770 return "bad packet (discarded)";
771 case MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR:
772 return "bad size too many outstanding CQEs";
773 default:
774 return "unknown status";
775 }
776 }
777
cmd_status_to_err(u8 status)778 static int cmd_status_to_err(u8 status)
779 {
780 switch (status) {
781 case MLX5_CMD_STAT_OK: return 0;
782 case MLX5_CMD_STAT_INT_ERR: return -EIO;
783 case MLX5_CMD_STAT_BAD_OP_ERR: return -EINVAL;
784 case MLX5_CMD_STAT_BAD_PARAM_ERR: return -EINVAL;
785 case MLX5_CMD_STAT_BAD_SYS_STATE_ERR: return -EIO;
786 case MLX5_CMD_STAT_BAD_RES_ERR: return -EINVAL;
787 case MLX5_CMD_STAT_RES_BUSY: return -EBUSY;
788 case MLX5_CMD_STAT_LIM_ERR: return -ENOMEM;
789 case MLX5_CMD_STAT_BAD_RES_STATE_ERR: return -EINVAL;
790 case MLX5_CMD_STAT_IX_ERR: return -EINVAL;
791 case MLX5_CMD_STAT_NO_RES_ERR: return -EAGAIN;
792 case MLX5_CMD_STAT_BAD_INP_LEN_ERR: return -EIO;
793 case MLX5_CMD_STAT_BAD_OUTP_LEN_ERR: return -EIO;
794 case MLX5_CMD_STAT_BAD_QP_STATE_ERR: return -EINVAL;
795 case MLX5_CMD_STAT_BAD_PKT_ERR: return -EINVAL;
796 case MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR: return -EINVAL;
797 default: return -EIO;
798 }
799 }
800
mlx5_cmd_out_err(struct mlx5_core_dev * dev,u16 opcode,u16 op_mod,void * out)801 void mlx5_cmd_out_err(struct mlx5_core_dev *dev, u16 opcode, u16 op_mod, void *out)
802 {
803 u32 syndrome = MLX5_GET(mbox_out, out, syndrome);
804 u8 status = MLX5_GET(mbox_out, out, status);
805
806 mlx5_core_err_rl(dev,
807 "%s(0x%x) op_mod(0x%x) failed, status %s(0x%x), syndrome (0x%x), err(%d)\n",
808 mlx5_command_str(opcode), opcode, op_mod,
809 cmd_status_str(status), status, syndrome, cmd_status_to_err(status));
810 }
811 EXPORT_SYMBOL(mlx5_cmd_out_err);
812
cmd_status_print(struct mlx5_core_dev * dev,void * in,void * out)813 static void cmd_status_print(struct mlx5_core_dev *dev, void *in, void *out)
814 {
815 u16 opcode, op_mod;
816 u16 uid;
817
818 opcode = in_to_opcode(in);
819 op_mod = MLX5_GET(mbox_in, in, op_mod);
820 uid = MLX5_GET(mbox_in, in, uid);
821
822 if (!uid && opcode != MLX5_CMD_OP_DESTROY_MKEY &&
823 opcode != MLX5_CMD_OP_CREATE_UCTX)
824 mlx5_cmd_out_err(dev, opcode, op_mod, out);
825 }
826
mlx5_cmd_check(struct mlx5_core_dev * dev,int err,void * in,void * out)827 int mlx5_cmd_check(struct mlx5_core_dev *dev, int err, void *in, void *out)
828 {
829 /* aborted due to PCI error or via reset flow mlx5_cmd_trigger_completions() */
830 if (err == -ENXIO) {
831 u16 opcode = in_to_opcode(in);
832 u32 syndrome;
833 u8 status;
834
835 /* PCI Error, emulate command return status, for smooth reset */
836 err = mlx5_internal_err_ret_value(dev, opcode, &syndrome, &status);
837 MLX5_SET(mbox_out, out, status, status);
838 MLX5_SET(mbox_out, out, syndrome, syndrome);
839 if (!err)
840 return 0;
841 }
842
843 /* driver or FW delivery error */
844 if (err != -EREMOTEIO && err)
845 return err;
846
847 /* check outbox status */
848 err = cmd_status_to_err(MLX5_GET(mbox_out, out, status));
849 if (err)
850 cmd_status_print(dev, in, out);
851
852 return err;
853 }
854 EXPORT_SYMBOL(mlx5_cmd_check);
855
dump_command(struct mlx5_core_dev * dev,struct mlx5_cmd_work_ent * ent,int input)856 static void dump_command(struct mlx5_core_dev *dev,
857 struct mlx5_cmd_work_ent *ent, int input)
858 {
859 struct mlx5_cmd_msg *msg = input ? ent->in : ent->out;
860 struct mlx5_cmd_mailbox *next = msg->next;
861 int n = mlx5_calc_cmd_blocks(msg);
862 u16 op = ent->op;
863 int data_only;
864 u32 offset = 0;
865 int dump_len;
866 int i;
867
868 mlx5_core_dbg(dev, "cmd[%d]: start dump\n", ent->idx);
869 data_only = !!(mlx5_core_debug_mask & (1 << MLX5_CMD_DATA));
870
871 if (data_only)
872 mlx5_core_dbg_mask(dev, 1 << MLX5_CMD_DATA,
873 "cmd[%d]: dump command data %s(0x%x) %s\n",
874 ent->idx, mlx5_command_str(op), op,
875 input ? "INPUT" : "OUTPUT");
876 else
877 mlx5_core_dbg(dev, "cmd[%d]: dump command %s(0x%x) %s\n",
878 ent->idx, mlx5_command_str(op), op,
879 input ? "INPUT" : "OUTPUT");
880
881 if (data_only) {
882 if (input) {
883 dump_buf(ent->lay->in, sizeof(ent->lay->in), 1, offset, ent->idx);
884 offset += sizeof(ent->lay->in);
885 } else {
886 dump_buf(ent->lay->out, sizeof(ent->lay->out), 1, offset, ent->idx);
887 offset += sizeof(ent->lay->out);
888 }
889 } else {
890 dump_buf(ent->lay, sizeof(*ent->lay), 0, offset, ent->idx);
891 offset += sizeof(*ent->lay);
892 }
893
894 for (i = 0; i < n && next; i++) {
895 if (data_only) {
896 dump_len = min_t(int, MLX5_CMD_DATA_BLOCK_SIZE, msg->len - offset);
897 dump_buf(next->buf, dump_len, 1, offset, ent->idx);
898 offset += MLX5_CMD_DATA_BLOCK_SIZE;
899 } else {
900 mlx5_core_dbg(dev, "cmd[%d]: command block:\n", ent->idx);
901 dump_buf(next->buf, sizeof(struct mlx5_cmd_prot_block), 0, offset,
902 ent->idx);
903 offset += sizeof(struct mlx5_cmd_prot_block);
904 }
905 next = next->next;
906 }
907
908 if (data_only)
909 pr_debug("\n");
910
911 mlx5_core_dbg(dev, "cmd[%d]: end dump\n", ent->idx);
912 }
913
914 static void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vec, bool forced);
915
cb_timeout_handler(struct work_struct * work)916 static void cb_timeout_handler(struct work_struct *work)
917 {
918 struct delayed_work *dwork = container_of(work, struct delayed_work,
919 work);
920 struct mlx5_cmd_work_ent *ent = container_of(dwork,
921 struct mlx5_cmd_work_ent,
922 cb_timeout_work);
923 struct mlx5_core_dev *dev = container_of(ent->cmd, struct mlx5_core_dev,
924 cmd);
925
926 mlx5_cmd_eq_recover(dev);
927
928 /* Maybe got handled by eq recover ? */
929 if (!test_bit(MLX5_CMD_ENT_STATE_PENDING_COMP, &ent->state)) {
930 mlx5_core_warn(dev, "cmd[%d]: %s(0x%x) Async, recovered after timeout\n", ent->idx,
931 mlx5_command_str(ent->op), ent->op);
932 goto out; /* phew, already handled */
933 }
934
935 ent->ret = -ETIMEDOUT;
936 mlx5_core_warn(dev, "cmd[%d]: %s(0x%x) Async, timeout. Will cause a leak of a command resource\n",
937 ent->idx, mlx5_command_str(ent->op), ent->op);
938 mlx5_cmd_comp_handler(dev, 1ULL << ent->idx, true);
939
940 out:
941 cmd_ent_put(ent); /* for the cmd_ent_get() took on schedule delayed work */
942 }
943
944 static void free_msg(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *msg);
945 static void mlx5_free_cmd_msg(struct mlx5_core_dev *dev,
946 struct mlx5_cmd_msg *msg);
947
opcode_allowed(struct mlx5_cmd * cmd,u16 opcode)948 static bool opcode_allowed(struct mlx5_cmd *cmd, u16 opcode)
949 {
950 if (cmd->allowed_opcode == CMD_ALLOWED_OPCODE_ALL)
951 return true;
952
953 return cmd->allowed_opcode == opcode;
954 }
955
mlx5_cmd_is_down(struct mlx5_core_dev * dev)956 bool mlx5_cmd_is_down(struct mlx5_core_dev *dev)
957 {
958 return pci_channel_offline(dev->pdev) ||
959 dev->cmd.state != MLX5_CMDIF_STATE_UP ||
960 dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR;
961 }
962
cmd_work_handler(struct work_struct * work)963 static void cmd_work_handler(struct work_struct *work)
964 {
965 struct mlx5_cmd_work_ent *ent = container_of(work, struct mlx5_cmd_work_ent, work);
966 struct mlx5_cmd *cmd = ent->cmd;
967 bool poll_cmd = ent->polling;
968 struct mlx5_cmd_layout *lay;
969 struct mlx5_core_dev *dev;
970 unsigned long timeout;
971 unsigned long flags;
972 int alloc_ret;
973 int cmd_mode;
974
975 complete(&ent->handling);
976
977 dev = container_of(cmd, struct mlx5_core_dev, cmd);
978 timeout = msecs_to_jiffies(mlx5_tout_ms(dev, CMD));
979
980 if (!ent->page_queue) {
981 if (down_timeout(&cmd->vars.sem, timeout)) {
982 mlx5_core_warn(dev, "%s(0x%x) timed out while waiting for a slot.\n",
983 mlx5_command_str(ent->op), ent->op);
984 if (ent->callback) {
985 ent->callback(-EBUSY, ent->context);
986 mlx5_free_cmd_msg(dev, ent->out);
987 free_msg(dev, ent->in);
988 cmd_ent_put(ent);
989 } else {
990 ent->ret = -EBUSY;
991 complete(&ent->done);
992 }
993 complete(&ent->slotted);
994 return;
995 }
996 alloc_ret = cmd_alloc_index(cmd, ent);
997 if (alloc_ret < 0) {
998 mlx5_core_err_rl(dev, "failed to allocate command entry\n");
999 if (ent->callback) {
1000 ent->callback(-EAGAIN, ent->context);
1001 mlx5_free_cmd_msg(dev, ent->out);
1002 free_msg(dev, ent->in);
1003 cmd_ent_put(ent);
1004 } else {
1005 ent->ret = -EAGAIN;
1006 complete(&ent->done);
1007 }
1008 up(&cmd->vars.sem);
1009 return;
1010 }
1011 } else {
1012 down(&cmd->vars.pages_sem);
1013 ent->idx = cmd->vars.max_reg_cmds;
1014 spin_lock_irqsave(&cmd->alloc_lock, flags);
1015 clear_bit(ent->idx, &cmd->vars.bitmask);
1016 cmd->ent_arr[ent->idx] = ent;
1017 spin_unlock_irqrestore(&cmd->alloc_lock, flags);
1018 }
1019
1020 complete(&ent->slotted);
1021
1022 lay = get_inst(cmd, ent->idx);
1023 ent->lay = lay;
1024 memset(lay, 0, sizeof(*lay));
1025 memcpy(lay->in, ent->in->first.data, sizeof(lay->in));
1026 if (ent->in->next)
1027 lay->in_ptr = cpu_to_be64(ent->in->next->dma);
1028 lay->inlen = cpu_to_be32(ent->in->len);
1029 if (ent->out->next)
1030 lay->out_ptr = cpu_to_be64(ent->out->next->dma);
1031 lay->outlen = cpu_to_be32(ent->out->len);
1032 lay->type = MLX5_PCI_CMD_XPORT;
1033 lay->token = ent->token;
1034 lay->status_own = CMD_OWNER_HW;
1035 set_signature(ent, !cmd->checksum_disabled);
1036 dump_command(dev, ent, 1);
1037 ent->ts1 = ktime_get_ns();
1038 cmd_mode = cmd->mode;
1039
1040 if (ent->callback && schedule_delayed_work(&ent->cb_timeout_work, timeout))
1041 cmd_ent_get(ent);
1042 set_bit(MLX5_CMD_ENT_STATE_PENDING_COMP, &ent->state);
1043
1044 cmd_ent_get(ent); /* for the _real_ FW event on completion */
1045 /* Skip sending command to fw if internal error */
1046 if (mlx5_cmd_is_down(dev) || !opcode_allowed(&dev->cmd, ent->op)) {
1047 ent->ret = -ENXIO;
1048 mlx5_cmd_comp_handler(dev, 1ULL << ent->idx, true);
1049 return;
1050 }
1051
1052 /* ring doorbell after the descriptor is valid */
1053 mlx5_core_dbg(dev, "writing 0x%x to command doorbell\n", 1 << ent->idx);
1054 wmb();
1055 iowrite32be(1 << ent->idx, &dev->iseg->cmd_dbell);
1056 /* if not in polling don't use ent after this point */
1057 if (cmd_mode == CMD_MODE_POLLING || poll_cmd) {
1058 poll_timeout(ent);
1059 /* make sure we read the descriptor after ownership is SW */
1060 rmb();
1061 mlx5_cmd_comp_handler(dev, 1ULL << ent->idx, (ent->ret == -ETIMEDOUT));
1062 }
1063 }
1064
deliv_status_to_err(u8 status)1065 static int deliv_status_to_err(u8 status)
1066 {
1067 switch (status) {
1068 case MLX5_CMD_DELIVERY_STAT_OK:
1069 case MLX5_DRIVER_STATUS_ABORTED:
1070 return 0;
1071 case MLX5_CMD_DELIVERY_STAT_SIGNAT_ERR:
1072 case MLX5_CMD_DELIVERY_STAT_TOK_ERR:
1073 return -EBADR;
1074 case MLX5_CMD_DELIVERY_STAT_BAD_BLK_NUM_ERR:
1075 case MLX5_CMD_DELIVERY_STAT_OUT_PTR_ALIGN_ERR:
1076 case MLX5_CMD_DELIVERY_STAT_IN_PTR_ALIGN_ERR:
1077 return -EFAULT; /* Bad address */
1078 case MLX5_CMD_DELIVERY_STAT_IN_LENGTH_ERR:
1079 case MLX5_CMD_DELIVERY_STAT_OUT_LENGTH_ERR:
1080 case MLX5_CMD_DELIVERY_STAT_CMD_DESCR_ERR:
1081 case MLX5_CMD_DELIVERY_STAT_RES_FLD_NOT_CLR_ERR:
1082 return -ENOMSG;
1083 case MLX5_CMD_DELIVERY_STAT_FW_ERR:
1084 return -EIO;
1085 default:
1086 return -EINVAL;
1087 }
1088 }
1089
deliv_status_to_str(u8 status)1090 static const char *deliv_status_to_str(u8 status)
1091 {
1092 switch (status) {
1093 case MLX5_CMD_DELIVERY_STAT_OK:
1094 return "no errors";
1095 case MLX5_CMD_DELIVERY_STAT_SIGNAT_ERR:
1096 return "signature error";
1097 case MLX5_CMD_DELIVERY_STAT_TOK_ERR:
1098 return "token error";
1099 case MLX5_CMD_DELIVERY_STAT_BAD_BLK_NUM_ERR:
1100 return "bad block number";
1101 case MLX5_CMD_DELIVERY_STAT_OUT_PTR_ALIGN_ERR:
1102 return "output pointer not aligned to block size";
1103 case MLX5_CMD_DELIVERY_STAT_IN_PTR_ALIGN_ERR:
1104 return "input pointer not aligned to block size";
1105 case MLX5_CMD_DELIVERY_STAT_FW_ERR:
1106 return "firmware internal error";
1107 case MLX5_CMD_DELIVERY_STAT_IN_LENGTH_ERR:
1108 return "command input length error";
1109 case MLX5_CMD_DELIVERY_STAT_OUT_LENGTH_ERR:
1110 return "command output length error";
1111 case MLX5_CMD_DELIVERY_STAT_RES_FLD_NOT_CLR_ERR:
1112 return "reserved fields not cleared";
1113 case MLX5_CMD_DELIVERY_STAT_CMD_DESCR_ERR:
1114 return "bad command descriptor type";
1115 default:
1116 return "unknown status code";
1117 }
1118 }
1119
1120 enum {
1121 MLX5_CMD_TIMEOUT_RECOVER_MSEC = 5 * 1000,
1122 };
1123
wait_func_handle_exec_timeout(struct mlx5_core_dev * dev,struct mlx5_cmd_work_ent * ent)1124 static void wait_func_handle_exec_timeout(struct mlx5_core_dev *dev,
1125 struct mlx5_cmd_work_ent *ent)
1126 {
1127 unsigned long timeout = msecs_to_jiffies(MLX5_CMD_TIMEOUT_RECOVER_MSEC);
1128
1129 mlx5_cmd_eq_recover(dev);
1130
1131 /* Re-wait on the ent->done after executing the recovery flow. If the
1132 * recovery flow (or any other recovery flow running simultaneously)
1133 * has recovered an EQE, it should cause the entry to be completed by
1134 * the command interface.
1135 */
1136 if (wait_for_completion_timeout(&ent->done, timeout)) {
1137 mlx5_core_warn(dev, "cmd[%d]: %s(0x%x) recovered after timeout\n", ent->idx,
1138 mlx5_command_str(ent->op), ent->op);
1139 return;
1140 }
1141
1142 mlx5_core_warn(dev, "cmd[%d]: %s(0x%x) No done completion\n", ent->idx,
1143 mlx5_command_str(ent->op), ent->op);
1144
1145 ent->ret = -ETIMEDOUT;
1146 mlx5_cmd_comp_handler(dev, 1ULL << ent->idx, true);
1147 }
1148
wait_func(struct mlx5_core_dev * dev,struct mlx5_cmd_work_ent * ent)1149 static int wait_func(struct mlx5_core_dev *dev, struct mlx5_cmd_work_ent *ent)
1150 {
1151 unsigned long timeout = msecs_to_jiffies(mlx5_tout_ms(dev, CMD));
1152 struct mlx5_cmd *cmd = &dev->cmd;
1153 int err;
1154
1155 if (!wait_for_completion_timeout(&ent->handling, timeout) &&
1156 cancel_work_sync(&ent->work)) {
1157 ent->ret = -ECANCELED;
1158 goto out_err;
1159 }
1160
1161 wait_for_completion(&ent->slotted);
1162
1163 if (cmd->mode == CMD_MODE_POLLING || ent->polling)
1164 wait_for_completion(&ent->done);
1165 else if (!wait_for_completion_timeout(&ent->done, timeout))
1166 wait_func_handle_exec_timeout(dev, ent);
1167
1168 out_err:
1169 err = ent->ret;
1170
1171 if (err == -ETIMEDOUT) {
1172 mlx5_core_warn(dev, "%s(0x%x) timeout. Will cause a leak of a command resource\n",
1173 mlx5_command_str(ent->op), ent->op);
1174 } else if (err == -ECANCELED) {
1175 mlx5_core_warn(dev, "%s(0x%x) canceled on out of queue timeout.\n",
1176 mlx5_command_str(ent->op), ent->op);
1177 } else if (err == -EBUSY) {
1178 mlx5_core_warn(dev, "%s(0x%x) timeout while waiting for command semaphore.\n",
1179 mlx5_command_str(ent->op), ent->op);
1180 }
1181 mlx5_core_dbg(dev, "err %d, delivery status %s(%d)\n",
1182 err, deliv_status_to_str(ent->status), ent->status);
1183
1184 return err;
1185 }
1186
1187 /* Notes:
1188 * 1. Callback functions may not sleep
1189 * 2. page queue commands do not support asynchrous completion
1190 *
1191 * return value in case (!callback):
1192 * ret < 0 : Command execution couldn't be submitted by driver
1193 * ret > 0 : Command execution couldn't be performed by firmware
1194 * ret == 0: Command was executed by FW, Caller must check FW outbox status.
1195 *
1196 * return value in case (callback):
1197 * ret < 0 : Command execution couldn't be submitted by driver
1198 * ret == 0: Command will be submitted to FW for execution
1199 * and the callback will be called for further status updates
1200 */
mlx5_cmd_invoke(struct mlx5_core_dev * dev,struct mlx5_cmd_msg * in,struct mlx5_cmd_msg * out,void * uout,int uout_size,mlx5_cmd_cbk_t callback,void * context,int page_queue,u8 token,bool force_polling)1201 static int mlx5_cmd_invoke(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *in,
1202 struct mlx5_cmd_msg *out, void *uout, int uout_size,
1203 mlx5_cmd_cbk_t callback,
1204 void *context, int page_queue,
1205 u8 token, bool force_polling)
1206 {
1207 struct mlx5_cmd *cmd = &dev->cmd;
1208 struct mlx5_cmd_work_ent *ent;
1209 struct mlx5_cmd_stats *stats;
1210 u8 status = 0;
1211 int err = 0;
1212 s64 ds;
1213
1214 if (callback && page_queue)
1215 return -EINVAL;
1216
1217 ent = cmd_alloc_ent(cmd, in, out, uout, uout_size,
1218 callback, context, page_queue);
1219 if (IS_ERR(ent))
1220 return PTR_ERR(ent);
1221
1222 /* put for this ent is when consumed, depending on the use case
1223 * 1) (!callback) blocking flow: by caller after wait_func completes
1224 * 2) (callback) flow: by mlx5_cmd_comp_handler() when ent is handled
1225 */
1226
1227 ent->token = token;
1228 ent->polling = force_polling;
1229
1230 init_completion(&ent->handling);
1231 init_completion(&ent->slotted);
1232 if (!callback)
1233 init_completion(&ent->done);
1234
1235 INIT_DELAYED_WORK(&ent->cb_timeout_work, cb_timeout_handler);
1236 INIT_WORK(&ent->work, cmd_work_handler);
1237 if (page_queue) {
1238 cmd_work_handler(&ent->work);
1239 } else if (!queue_work(cmd->wq, &ent->work)) {
1240 mlx5_core_warn(dev, "failed to queue work\n");
1241 err = -EALREADY;
1242 goto out_free;
1243 }
1244
1245 if (callback)
1246 return 0; /* mlx5_cmd_comp_handler() will put(ent) */
1247
1248 err = wait_func(dev, ent);
1249 if (err == -ETIMEDOUT || err == -ECANCELED || err == -EBUSY)
1250 goto out_free;
1251
1252 ds = ent->ts2 - ent->ts1;
1253 stats = xa_load(&cmd->stats, ent->op);
1254 if (stats) {
1255 spin_lock_irq(&stats->lock);
1256 stats->sum += ds;
1257 ++stats->n;
1258 spin_unlock_irq(&stats->lock);
1259 }
1260 mlx5_core_dbg_mask(dev, 1 << MLX5_CMD_TIME,
1261 "fw exec time for %s is %lld nsec\n",
1262 mlx5_command_str(ent->op), ds);
1263
1264 out_free:
1265 status = ent->status;
1266 cmd_ent_put(ent);
1267 return err ? : status;
1268 }
1269
dbg_write(struct file * filp,const char __user * buf,size_t count,loff_t * pos)1270 static ssize_t dbg_write(struct file *filp, const char __user *buf,
1271 size_t count, loff_t *pos)
1272 {
1273 struct mlx5_core_dev *dev = filp->private_data;
1274 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1275 char lbuf[3];
1276 int err;
1277
1278 if (!dbg->in_msg || !dbg->out_msg)
1279 return -ENOMEM;
1280
1281 if (count < sizeof(lbuf) - 1)
1282 return -EINVAL;
1283
1284 if (copy_from_user(lbuf, buf, sizeof(lbuf) - 1))
1285 return -EFAULT;
1286
1287 lbuf[sizeof(lbuf) - 1] = 0;
1288
1289 if (strcmp(lbuf, "go"))
1290 return -EINVAL;
1291
1292 err = mlx5_cmd_exec(dev, dbg->in_msg, dbg->inlen, dbg->out_msg, dbg->outlen);
1293
1294 return err ? err : count;
1295 }
1296
1297 static const struct file_operations fops = {
1298 .owner = THIS_MODULE,
1299 .open = simple_open,
1300 .write = dbg_write,
1301 };
1302
mlx5_copy_to_msg(struct mlx5_cmd_msg * to,void * from,int size,u8 token)1303 static int mlx5_copy_to_msg(struct mlx5_cmd_msg *to, void *from, int size,
1304 u8 token)
1305 {
1306 struct mlx5_cmd_prot_block *block;
1307 struct mlx5_cmd_mailbox *next;
1308 int copy;
1309
1310 if (!to || !from)
1311 return -ENOMEM;
1312
1313 copy = min_t(int, size, sizeof(to->first.data));
1314 memcpy(to->first.data, from, copy);
1315 size -= copy;
1316 from += copy;
1317
1318 next = to->next;
1319 while (size) {
1320 if (!next) {
1321 /* this is a BUG */
1322 return -ENOMEM;
1323 }
1324
1325 copy = min_t(int, size, MLX5_CMD_DATA_BLOCK_SIZE);
1326 block = next->buf;
1327 memcpy(block->data, from, copy);
1328 from += copy;
1329 size -= copy;
1330 block->token = token;
1331 next = next->next;
1332 }
1333
1334 return 0;
1335 }
1336
mlx5_copy_from_msg(void * to,struct mlx5_cmd_msg * from,int size)1337 static int mlx5_copy_from_msg(void *to, struct mlx5_cmd_msg *from, int size)
1338 {
1339 struct mlx5_cmd_prot_block *block;
1340 struct mlx5_cmd_mailbox *next;
1341 int copy;
1342
1343 if (!to || !from)
1344 return -ENOMEM;
1345
1346 copy = min_t(int, size, sizeof(from->first.data));
1347 memcpy(to, from->first.data, copy);
1348 size -= copy;
1349 to += copy;
1350
1351 next = from->next;
1352 while (size) {
1353 if (!next) {
1354 /* this is a BUG */
1355 return -ENOMEM;
1356 }
1357
1358 copy = min_t(int, size, MLX5_CMD_DATA_BLOCK_SIZE);
1359 block = next->buf;
1360
1361 memcpy(to, block->data, copy);
1362 to += copy;
1363 size -= copy;
1364 next = next->next;
1365 }
1366
1367 return 0;
1368 }
1369
alloc_cmd_box(struct mlx5_core_dev * dev,gfp_t flags)1370 static struct mlx5_cmd_mailbox *alloc_cmd_box(struct mlx5_core_dev *dev,
1371 gfp_t flags)
1372 {
1373 struct mlx5_cmd_mailbox *mailbox;
1374
1375 mailbox = kmalloc(sizeof(*mailbox), flags);
1376 if (!mailbox)
1377 return ERR_PTR(-ENOMEM);
1378
1379 mailbox->buf = dma_pool_zalloc(dev->cmd.pool, flags,
1380 &mailbox->dma);
1381 if (!mailbox->buf) {
1382 mlx5_core_dbg(dev, "failed allocation\n");
1383 kfree(mailbox);
1384 return ERR_PTR(-ENOMEM);
1385 }
1386 mailbox->next = NULL;
1387
1388 return mailbox;
1389 }
1390
free_cmd_box(struct mlx5_core_dev * dev,struct mlx5_cmd_mailbox * mailbox)1391 static void free_cmd_box(struct mlx5_core_dev *dev,
1392 struct mlx5_cmd_mailbox *mailbox)
1393 {
1394 dma_pool_free(dev->cmd.pool, mailbox->buf, mailbox->dma);
1395 kfree(mailbox);
1396 }
1397
mlx5_alloc_cmd_msg(struct mlx5_core_dev * dev,gfp_t flags,int size,u8 token)1398 static struct mlx5_cmd_msg *mlx5_alloc_cmd_msg(struct mlx5_core_dev *dev,
1399 gfp_t flags, int size,
1400 u8 token)
1401 {
1402 struct mlx5_cmd_mailbox *tmp, *head = NULL;
1403 struct mlx5_cmd_prot_block *block;
1404 struct mlx5_cmd_msg *msg;
1405 int err;
1406 int n;
1407 int i;
1408
1409 msg = kzalloc(sizeof(*msg), flags);
1410 if (!msg)
1411 return ERR_PTR(-ENOMEM);
1412
1413 msg->len = size;
1414 n = mlx5_calc_cmd_blocks(msg);
1415
1416 for (i = 0; i < n; i++) {
1417 tmp = alloc_cmd_box(dev, flags);
1418 if (IS_ERR(tmp)) {
1419 mlx5_core_warn(dev, "failed allocating block\n");
1420 err = PTR_ERR(tmp);
1421 goto err_alloc;
1422 }
1423
1424 block = tmp->buf;
1425 tmp->next = head;
1426 block->next = cpu_to_be64(tmp->next ? tmp->next->dma : 0);
1427 block->block_num = cpu_to_be32(n - i - 1);
1428 block->token = token;
1429 head = tmp;
1430 }
1431 msg->next = head;
1432 return msg;
1433
1434 err_alloc:
1435 while (head) {
1436 tmp = head->next;
1437 free_cmd_box(dev, head);
1438 head = tmp;
1439 }
1440 kfree(msg);
1441
1442 return ERR_PTR(err);
1443 }
1444
mlx5_free_cmd_msg(struct mlx5_core_dev * dev,struct mlx5_cmd_msg * msg)1445 static void mlx5_free_cmd_msg(struct mlx5_core_dev *dev,
1446 struct mlx5_cmd_msg *msg)
1447 {
1448 struct mlx5_cmd_mailbox *head = msg->next;
1449 struct mlx5_cmd_mailbox *next;
1450
1451 while (head) {
1452 next = head->next;
1453 free_cmd_box(dev, head);
1454 head = next;
1455 }
1456 kfree(msg);
1457 }
1458
data_write(struct file * filp,const char __user * buf,size_t count,loff_t * pos)1459 static ssize_t data_write(struct file *filp, const char __user *buf,
1460 size_t count, loff_t *pos)
1461 {
1462 struct mlx5_core_dev *dev = filp->private_data;
1463 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1464 void *ptr;
1465
1466 if (*pos != 0)
1467 return -EINVAL;
1468
1469 kfree(dbg->in_msg);
1470 dbg->in_msg = NULL;
1471 dbg->inlen = 0;
1472 ptr = memdup_user(buf, count);
1473 if (IS_ERR(ptr))
1474 return PTR_ERR(ptr);
1475 dbg->in_msg = ptr;
1476 dbg->inlen = count;
1477
1478 *pos = count;
1479
1480 return count;
1481 }
1482
data_read(struct file * filp,char __user * buf,size_t count,loff_t * pos)1483 static ssize_t data_read(struct file *filp, char __user *buf, size_t count,
1484 loff_t *pos)
1485 {
1486 struct mlx5_core_dev *dev = filp->private_data;
1487 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1488
1489 if (!dbg->out_msg)
1490 return -ENOMEM;
1491
1492 return simple_read_from_buffer(buf, count, pos, dbg->out_msg,
1493 dbg->outlen);
1494 }
1495
1496 static const struct file_operations dfops = {
1497 .owner = THIS_MODULE,
1498 .open = simple_open,
1499 .write = data_write,
1500 .read = data_read,
1501 };
1502
outlen_read(struct file * filp,char __user * buf,size_t count,loff_t * pos)1503 static ssize_t outlen_read(struct file *filp, char __user *buf, size_t count,
1504 loff_t *pos)
1505 {
1506 struct mlx5_core_dev *dev = filp->private_data;
1507 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1508 char outlen[8];
1509 int err;
1510
1511 err = snprintf(outlen, sizeof(outlen), "%d", dbg->outlen);
1512 if (err < 0)
1513 return err;
1514
1515 return simple_read_from_buffer(buf, count, pos, outlen, err);
1516 }
1517
outlen_write(struct file * filp,const char __user * buf,size_t count,loff_t * pos)1518 static ssize_t outlen_write(struct file *filp, const char __user *buf,
1519 size_t count, loff_t *pos)
1520 {
1521 struct mlx5_core_dev *dev = filp->private_data;
1522 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1523 char outlen_str[8] = {0};
1524 int outlen;
1525 void *ptr;
1526 int err;
1527
1528 if (*pos != 0 || count > 6)
1529 return -EINVAL;
1530
1531 kfree(dbg->out_msg);
1532 dbg->out_msg = NULL;
1533 dbg->outlen = 0;
1534
1535 if (copy_from_user(outlen_str, buf, count))
1536 return -EFAULT;
1537
1538 err = sscanf(outlen_str, "%d", &outlen);
1539 if (err != 1)
1540 return -EINVAL;
1541
1542 ptr = kzalloc(outlen, GFP_KERNEL);
1543 if (!ptr)
1544 return -ENOMEM;
1545
1546 dbg->out_msg = ptr;
1547 dbg->outlen = outlen;
1548
1549 *pos = count;
1550
1551 return count;
1552 }
1553
1554 static const struct file_operations olfops = {
1555 .owner = THIS_MODULE,
1556 .open = simple_open,
1557 .write = outlen_write,
1558 .read = outlen_read,
1559 };
1560
set_wqname(struct mlx5_core_dev * dev)1561 static void set_wqname(struct mlx5_core_dev *dev)
1562 {
1563 struct mlx5_cmd *cmd = &dev->cmd;
1564
1565 snprintf(cmd->wq_name, sizeof(cmd->wq_name), "mlx5_cmd_%s",
1566 dev_name(dev->device));
1567 }
1568
clean_debug_files(struct mlx5_core_dev * dev)1569 static void clean_debug_files(struct mlx5_core_dev *dev)
1570 {
1571 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1572
1573 if (!mlx5_debugfs_root)
1574 return;
1575
1576 debugfs_remove_recursive(dbg->dbg_root);
1577 }
1578
create_debugfs_files(struct mlx5_core_dev * dev)1579 static void create_debugfs_files(struct mlx5_core_dev *dev)
1580 {
1581 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1582
1583 dbg->dbg_root = debugfs_create_dir("cmd", mlx5_debugfs_get_dev_root(dev));
1584
1585 debugfs_create_file("in", 0400, dbg->dbg_root, dev, &dfops);
1586 debugfs_create_file("out", 0200, dbg->dbg_root, dev, &dfops);
1587 debugfs_create_file("out_len", 0600, dbg->dbg_root, dev, &olfops);
1588 debugfs_create_u8("status", 0600, dbg->dbg_root, &dbg->status);
1589 debugfs_create_file("run", 0200, dbg->dbg_root, dev, &fops);
1590 }
1591
mlx5_cmd_allowed_opcode(struct mlx5_core_dev * dev,u16 opcode)1592 void mlx5_cmd_allowed_opcode(struct mlx5_core_dev *dev, u16 opcode)
1593 {
1594 struct mlx5_cmd *cmd = &dev->cmd;
1595 int i;
1596
1597 for (i = 0; i < cmd->vars.max_reg_cmds; i++)
1598 down(&cmd->vars.sem);
1599 down(&cmd->vars.pages_sem);
1600
1601 cmd->allowed_opcode = opcode;
1602
1603 up(&cmd->vars.pages_sem);
1604 for (i = 0; i < cmd->vars.max_reg_cmds; i++)
1605 up(&cmd->vars.sem);
1606 }
1607
mlx5_cmd_change_mod(struct mlx5_core_dev * dev,int mode)1608 static void mlx5_cmd_change_mod(struct mlx5_core_dev *dev, int mode)
1609 {
1610 struct mlx5_cmd *cmd = &dev->cmd;
1611 int i;
1612
1613 for (i = 0; i < cmd->vars.max_reg_cmds; i++)
1614 down(&cmd->vars.sem);
1615 down(&cmd->vars.pages_sem);
1616
1617 cmd->mode = mode;
1618
1619 up(&cmd->vars.pages_sem);
1620 for (i = 0; i < cmd->vars.max_reg_cmds; i++)
1621 up(&cmd->vars.sem);
1622 }
1623
cmd_comp_notifier(struct notifier_block * nb,unsigned long type,void * data)1624 static int cmd_comp_notifier(struct notifier_block *nb,
1625 unsigned long type, void *data)
1626 {
1627 struct mlx5_core_dev *dev;
1628 struct mlx5_cmd *cmd;
1629 struct mlx5_eqe *eqe;
1630
1631 cmd = mlx5_nb_cof(nb, struct mlx5_cmd, nb);
1632 dev = container_of(cmd, struct mlx5_core_dev, cmd);
1633 eqe = data;
1634
1635 if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR)
1636 return NOTIFY_DONE;
1637
1638 mlx5_cmd_comp_handler(dev, be32_to_cpu(eqe->data.cmd.vector), false);
1639
1640 return NOTIFY_OK;
1641 }
mlx5_cmd_use_events(struct mlx5_core_dev * dev)1642 void mlx5_cmd_use_events(struct mlx5_core_dev *dev)
1643 {
1644 MLX5_NB_INIT(&dev->cmd.nb, cmd_comp_notifier, CMD);
1645 mlx5_eq_notifier_register(dev, &dev->cmd.nb);
1646 mlx5_cmd_change_mod(dev, CMD_MODE_EVENTS);
1647 }
1648
mlx5_cmd_use_polling(struct mlx5_core_dev * dev)1649 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev)
1650 {
1651 mlx5_cmd_change_mod(dev, CMD_MODE_POLLING);
1652 mlx5_eq_notifier_unregister(dev, &dev->cmd.nb);
1653 }
1654
free_msg(struct mlx5_core_dev * dev,struct mlx5_cmd_msg * msg)1655 static void free_msg(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *msg)
1656 {
1657 unsigned long flags;
1658
1659 if (msg->parent) {
1660 spin_lock_irqsave(&msg->parent->lock, flags);
1661 list_add_tail(&msg->list, &msg->parent->head);
1662 spin_unlock_irqrestore(&msg->parent->lock, flags);
1663 } else {
1664 mlx5_free_cmd_msg(dev, msg);
1665 }
1666 }
1667
mlx5_cmd_comp_handler(struct mlx5_core_dev * dev,u64 vec,bool forced)1668 static void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vec, bool forced)
1669 {
1670 struct mlx5_cmd *cmd = &dev->cmd;
1671 struct mlx5_cmd_work_ent *ent;
1672 mlx5_cmd_cbk_t callback;
1673 void *context;
1674 int err;
1675 int i;
1676 s64 ds;
1677 struct mlx5_cmd_stats *stats;
1678 unsigned long flags;
1679 unsigned long vector;
1680
1681 /* there can be at most 32 command queues */
1682 vector = vec & 0xffffffff;
1683 for (i = 0; i < (1 << cmd->vars.log_sz); i++) {
1684 if (test_bit(i, &vector)) {
1685 ent = cmd->ent_arr[i];
1686
1687 /* if we already completed the command, ignore it */
1688 if (!test_and_clear_bit(MLX5_CMD_ENT_STATE_PENDING_COMP,
1689 &ent->state)) {
1690 /* only real completion can free the cmd slot */
1691 if (!forced) {
1692 mlx5_core_err(dev, "Command completion arrived after timeout (entry idx = %d).\n",
1693 ent->idx);
1694 cmd_ent_put(ent);
1695 }
1696 continue;
1697 }
1698
1699 if (ent->callback && cancel_delayed_work(&ent->cb_timeout_work))
1700 cmd_ent_put(ent); /* timeout work was canceled */
1701
1702 if (!forced || /* Real FW completion */
1703 mlx5_cmd_is_down(dev) || /* No real FW completion is expected */
1704 !opcode_allowed(cmd, ent->op))
1705 cmd_ent_put(ent);
1706
1707 ent->ts2 = ktime_get_ns();
1708 memcpy(ent->out->first.data, ent->lay->out, sizeof(ent->lay->out));
1709 dump_command(dev, ent, 0);
1710
1711 if (vec & MLX5_TRIGGERED_CMD_COMP)
1712 ent->ret = -ENXIO;
1713
1714 if (!ent->ret) { /* Command completed by FW */
1715 if (!cmd->checksum_disabled)
1716 ent->ret = verify_signature(ent);
1717
1718 ent->status = ent->lay->status_own >> 1;
1719
1720 mlx5_core_dbg(dev, "command completed. ret 0x%x, delivery status %s(0x%x)\n",
1721 ent->ret, deliv_status_to_str(ent->status), ent->status);
1722 }
1723
1724 if (ent->callback) {
1725 ds = ent->ts2 - ent->ts1;
1726 stats = xa_load(&cmd->stats, ent->op);
1727 if (stats) {
1728 spin_lock_irqsave(&stats->lock, flags);
1729 stats->sum += ds;
1730 ++stats->n;
1731 spin_unlock_irqrestore(&stats->lock, flags);
1732 }
1733
1734 callback = ent->callback;
1735 context = ent->context;
1736 err = ent->ret ? : ent->status;
1737 if (err > 0) /* Failed in FW, command didn't execute */
1738 err = deliv_status_to_err(err);
1739
1740 if (!err)
1741 err = mlx5_copy_from_msg(ent->uout,
1742 ent->out,
1743 ent->uout_size);
1744
1745 mlx5_free_cmd_msg(dev, ent->out);
1746 free_msg(dev, ent->in);
1747
1748 /* final consumer is done, release ent */
1749 cmd_ent_put(ent);
1750 callback(err, context);
1751 } else {
1752 /* release wait_func() so mlx5_cmd_invoke()
1753 * can make the final ent_put()
1754 */
1755 complete(&ent->done);
1756 }
1757 }
1758 }
1759 }
1760
1761 #define MLX5_MAX_MANAGE_PAGES_CMD_ENT 1
1762 #define MLX5_CMD_MASK ((1UL << (cmd->vars.max_reg_cmds + \
1763 MLX5_MAX_MANAGE_PAGES_CMD_ENT)) - 1)
1764
mlx5_cmd_trigger_completions(struct mlx5_core_dev * dev)1765 static void mlx5_cmd_trigger_completions(struct mlx5_core_dev *dev)
1766 {
1767 struct mlx5_cmd *cmd = &dev->cmd;
1768 unsigned long bitmask;
1769 unsigned long flags;
1770 u64 vector;
1771 int i;
1772
1773 /* wait for pending handlers to complete */
1774 mlx5_eq_synchronize_cmd_irq(dev);
1775 spin_lock_irqsave(&dev->cmd.alloc_lock, flags);
1776 vector = ~dev->cmd.vars.bitmask & MLX5_CMD_MASK;
1777 if (!vector)
1778 goto no_trig;
1779
1780 bitmask = vector;
1781 /* we must increment the allocated entries refcount before triggering the completions
1782 * to guarantee pending commands will not get freed in the meanwhile.
1783 * For that reason, it also has to be done inside the alloc_lock.
1784 */
1785 for_each_set_bit(i, &bitmask, (1 << cmd->vars.log_sz))
1786 cmd_ent_get(cmd->ent_arr[i]);
1787 vector |= MLX5_TRIGGERED_CMD_COMP;
1788 spin_unlock_irqrestore(&dev->cmd.alloc_lock, flags);
1789
1790 mlx5_core_dbg(dev, "vector 0x%llx\n", vector);
1791 mlx5_cmd_comp_handler(dev, vector, true);
1792 for_each_set_bit(i, &bitmask, (1 << cmd->vars.log_sz))
1793 cmd_ent_put(cmd->ent_arr[i]);
1794 return;
1795
1796 no_trig:
1797 spin_unlock_irqrestore(&dev->cmd.alloc_lock, flags);
1798 }
1799
mlx5_cmd_flush(struct mlx5_core_dev * dev)1800 void mlx5_cmd_flush(struct mlx5_core_dev *dev)
1801 {
1802 struct mlx5_cmd *cmd = &dev->cmd;
1803 int i;
1804
1805 for (i = 0; i < cmd->vars.max_reg_cmds; i++) {
1806 while (down_trylock(&cmd->vars.sem)) {
1807 mlx5_cmd_trigger_completions(dev);
1808 cond_resched();
1809 }
1810 }
1811
1812 while (down_trylock(&cmd->vars.pages_sem)) {
1813 mlx5_cmd_trigger_completions(dev);
1814 cond_resched();
1815 }
1816
1817 /* Unlock cmdif */
1818 up(&cmd->vars.pages_sem);
1819 for (i = 0; i < cmd->vars.max_reg_cmds; i++)
1820 up(&cmd->vars.sem);
1821 }
1822
alloc_msg(struct mlx5_core_dev * dev,int in_size,gfp_t gfp)1823 static struct mlx5_cmd_msg *alloc_msg(struct mlx5_core_dev *dev, int in_size,
1824 gfp_t gfp)
1825 {
1826 struct mlx5_cmd_msg *msg = ERR_PTR(-ENOMEM);
1827 struct cmd_msg_cache *ch = NULL;
1828 struct mlx5_cmd *cmd = &dev->cmd;
1829 int i;
1830
1831 if (in_size <= 16)
1832 goto cache_miss;
1833
1834 for (i = 0; i < dev->profile.num_cmd_caches; i++) {
1835 ch = &cmd->cache[i];
1836 if (in_size > ch->max_inbox_size)
1837 continue;
1838 spin_lock_irq(&ch->lock);
1839 if (list_empty(&ch->head)) {
1840 spin_unlock_irq(&ch->lock);
1841 continue;
1842 }
1843 msg = list_entry(ch->head.next, typeof(*msg), list);
1844 /* For cached lists, we must explicitly state what is
1845 * the real size
1846 */
1847 msg->len = in_size;
1848 list_del(&msg->list);
1849 spin_unlock_irq(&ch->lock);
1850 break;
1851 }
1852
1853 if (!IS_ERR(msg))
1854 return msg;
1855
1856 cache_miss:
1857 msg = mlx5_alloc_cmd_msg(dev, gfp, in_size, 0);
1858 return msg;
1859 }
1860
is_manage_pages(void * in)1861 static int is_manage_pages(void *in)
1862 {
1863 return in_to_opcode(in) == MLX5_CMD_OP_MANAGE_PAGES;
1864 }
1865
1866 /* Notes:
1867 * 1. Callback functions may not sleep
1868 * 2. Page queue commands do not support asynchrous completion
1869 */
cmd_exec(struct mlx5_core_dev * dev,void * in,int in_size,void * out,int out_size,mlx5_cmd_cbk_t callback,void * context,bool force_polling)1870 static int cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
1871 int out_size, mlx5_cmd_cbk_t callback, void *context,
1872 bool force_polling)
1873 {
1874 struct mlx5_cmd_msg *inb, *outb;
1875 u16 opcode = in_to_opcode(in);
1876 bool throttle_op;
1877 int pages_queue;
1878 gfp_t gfp;
1879 u8 token;
1880 int err;
1881
1882 if (mlx5_cmd_is_down(dev) || !opcode_allowed(&dev->cmd, opcode))
1883 return -ENXIO;
1884
1885 throttle_op = mlx5_cmd_is_throttle_opcode(opcode);
1886 if (throttle_op) {
1887 /* atomic context may not sleep */
1888 if (callback)
1889 return -EINVAL;
1890 down(&dev->cmd.vars.throttle_sem);
1891 }
1892
1893 pages_queue = is_manage_pages(in);
1894 gfp = callback ? GFP_ATOMIC : GFP_KERNEL;
1895
1896 inb = alloc_msg(dev, in_size, gfp);
1897 if (IS_ERR(inb)) {
1898 err = PTR_ERR(inb);
1899 goto out_up;
1900 }
1901
1902 token = alloc_token(&dev->cmd);
1903
1904 err = mlx5_copy_to_msg(inb, in, in_size, token);
1905 if (err) {
1906 mlx5_core_warn(dev, "err %d\n", err);
1907 goto out_in;
1908 }
1909
1910 outb = mlx5_alloc_cmd_msg(dev, gfp, out_size, token);
1911 if (IS_ERR(outb)) {
1912 err = PTR_ERR(outb);
1913 goto out_in;
1914 }
1915
1916 err = mlx5_cmd_invoke(dev, inb, outb, out, out_size, callback, context,
1917 pages_queue, token, force_polling);
1918 if (callback)
1919 return err;
1920
1921 if (err > 0) /* Failed in FW, command didn't execute */
1922 err = deliv_status_to_err(err);
1923
1924 if (err)
1925 goto out_out;
1926
1927 /* command completed by FW */
1928 err = mlx5_copy_from_msg(out, outb, out_size);
1929 out_out:
1930 mlx5_free_cmd_msg(dev, outb);
1931 out_in:
1932 free_msg(dev, inb);
1933 out_up:
1934 if (throttle_op)
1935 up(&dev->cmd.vars.throttle_sem);
1936 return err;
1937 }
1938
mlx5_cmd_err_trace(struct mlx5_core_dev * dev,u16 opcode,u16 op_mod,void * out)1939 static void mlx5_cmd_err_trace(struct mlx5_core_dev *dev, u16 opcode, u16 op_mod, void *out)
1940 {
1941 u32 syndrome = MLX5_GET(mbox_out, out, syndrome);
1942 u8 status = MLX5_GET(mbox_out, out, status);
1943
1944 trace_mlx5_cmd(mlx5_command_str(opcode), opcode, op_mod,
1945 cmd_status_str(status), status, syndrome,
1946 cmd_status_to_err(status));
1947 }
1948
cmd_status_log(struct mlx5_core_dev * dev,u16 opcode,u8 status,u32 syndrome,int err)1949 static void cmd_status_log(struct mlx5_core_dev *dev, u16 opcode, u8 status,
1950 u32 syndrome, int err)
1951 {
1952 const char *namep = mlx5_command_str(opcode);
1953 struct mlx5_cmd_stats *stats;
1954 unsigned long flags;
1955
1956 if (!err || !(strcmp(namep, "unknown command opcode")))
1957 return;
1958
1959 stats = xa_load(&dev->cmd.stats, opcode);
1960 if (!stats)
1961 return;
1962 spin_lock_irqsave(&stats->lock, flags);
1963 stats->failed++;
1964 if (err < 0)
1965 stats->last_failed_errno = -err;
1966 if (err == -EREMOTEIO) {
1967 stats->failed_mbox_status++;
1968 stats->last_failed_mbox_status = status;
1969 stats->last_failed_syndrome = syndrome;
1970 }
1971 spin_unlock_irqrestore(&stats->lock, flags);
1972 }
1973
1974 /* preserve -EREMOTEIO for outbox.status != OK, otherwise return err as is */
cmd_status_err(struct mlx5_core_dev * dev,int err,u16 opcode,u16 op_mod,void * out)1975 static int cmd_status_err(struct mlx5_core_dev *dev, int err, u16 opcode, u16 op_mod, void *out)
1976 {
1977 u32 syndrome = MLX5_GET(mbox_out, out, syndrome);
1978 u8 status = MLX5_GET(mbox_out, out, status);
1979
1980 if (err == -EREMOTEIO) /* -EREMOTEIO is preserved */
1981 err = -EIO;
1982
1983 if (!err && status != MLX5_CMD_STAT_OK) {
1984 err = -EREMOTEIO;
1985 mlx5_cmd_err_trace(dev, opcode, op_mod, out);
1986 }
1987
1988 cmd_status_log(dev, opcode, status, syndrome, err);
1989 return err;
1990 }
1991
1992 /**
1993 * mlx5_cmd_do - Executes a fw command, wait for completion.
1994 * Unlike mlx5_cmd_exec, this function will not translate or intercept
1995 * outbox.status and will return -EREMOTEIO when
1996 * outbox.status != MLX5_CMD_STAT_OK
1997 *
1998 * @dev: mlx5 core device
1999 * @in: inbox mlx5_ifc command buffer
2000 * @in_size: inbox buffer size
2001 * @out: outbox mlx5_ifc buffer
2002 * @out_size: outbox size
2003 *
2004 * @return:
2005 * -EREMOTEIO : Command executed by FW, outbox.status != MLX5_CMD_STAT_OK.
2006 * Caller must check FW outbox status.
2007 * 0 : Command execution successful, outbox.status == MLX5_CMD_STAT_OK.
2008 * < 0 : Command execution couldn't be performed by firmware or driver
2009 */
mlx5_cmd_do(struct mlx5_core_dev * dev,void * in,int in_size,void * out,int out_size)2010 int mlx5_cmd_do(struct mlx5_core_dev *dev, void *in, int in_size, void *out, int out_size)
2011 {
2012 int err = cmd_exec(dev, in, in_size, out, out_size, NULL, NULL, false);
2013 u16 op_mod = MLX5_GET(mbox_in, in, op_mod);
2014 u16 opcode = in_to_opcode(in);
2015
2016 return cmd_status_err(dev, err, opcode, op_mod, out);
2017 }
2018 EXPORT_SYMBOL(mlx5_cmd_do);
2019
2020 /**
2021 * mlx5_cmd_exec - Executes a fw command, wait for completion
2022 *
2023 * @dev: mlx5 core device
2024 * @in: inbox mlx5_ifc command buffer
2025 * @in_size: inbox buffer size
2026 * @out: outbox mlx5_ifc buffer
2027 * @out_size: outbox size
2028 *
2029 * @return: 0 if no error, FW command execution was successful
2030 * and outbox status is ok.
2031 */
mlx5_cmd_exec(struct mlx5_core_dev * dev,void * in,int in_size,void * out,int out_size)2032 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
2033 int out_size)
2034 {
2035 int err = mlx5_cmd_do(dev, in, in_size, out, out_size);
2036
2037 return mlx5_cmd_check(dev, err, in, out);
2038 }
2039 EXPORT_SYMBOL(mlx5_cmd_exec);
2040
2041 /**
2042 * mlx5_cmd_exec_polling - Executes a fw command, poll for completion
2043 * Needed for driver force teardown, when command completion EQ
2044 * will not be available to complete the command
2045 *
2046 * @dev: mlx5 core device
2047 * @in: inbox mlx5_ifc command buffer
2048 * @in_size: inbox buffer size
2049 * @out: outbox mlx5_ifc buffer
2050 * @out_size: outbox size
2051 *
2052 * @return: 0 if no error, FW command execution was successful
2053 * and outbox status is ok.
2054 */
mlx5_cmd_exec_polling(struct mlx5_core_dev * dev,void * in,int in_size,void * out,int out_size)2055 int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size,
2056 void *out, int out_size)
2057 {
2058 int err = cmd_exec(dev, in, in_size, out, out_size, NULL, NULL, true);
2059 u16 op_mod = MLX5_GET(mbox_in, in, op_mod);
2060 u16 opcode = in_to_opcode(in);
2061
2062 err = cmd_status_err(dev, err, opcode, op_mod, out);
2063 return mlx5_cmd_check(dev, err, in, out);
2064 }
2065 EXPORT_SYMBOL(mlx5_cmd_exec_polling);
2066
mlx5_cmd_init_async_ctx(struct mlx5_core_dev * dev,struct mlx5_async_ctx * ctx)2067 void mlx5_cmd_init_async_ctx(struct mlx5_core_dev *dev,
2068 struct mlx5_async_ctx *ctx)
2069 {
2070 ctx->dev = dev;
2071 /* Starts at 1 to avoid doing wake_up if we are not cleaning up */
2072 atomic_set(&ctx->num_inflight, 1);
2073 init_completion(&ctx->inflight_done);
2074 }
2075 EXPORT_SYMBOL(mlx5_cmd_init_async_ctx);
2076
2077 /**
2078 * mlx5_cmd_cleanup_async_ctx - Clean up an async_ctx
2079 * @ctx: The ctx to clean
2080 *
2081 * Upon return all callbacks given to mlx5_cmd_exec_cb() have been called. The
2082 * caller must ensure that mlx5_cmd_exec_cb() is not called during or after
2083 * the call mlx5_cleanup_async_ctx().
2084 */
mlx5_cmd_cleanup_async_ctx(struct mlx5_async_ctx * ctx)2085 void mlx5_cmd_cleanup_async_ctx(struct mlx5_async_ctx *ctx)
2086 {
2087 if (!atomic_dec_and_test(&ctx->num_inflight))
2088 wait_for_completion(&ctx->inflight_done);
2089 }
2090 EXPORT_SYMBOL(mlx5_cmd_cleanup_async_ctx);
2091
mlx5_cmd_exec_cb_handler(int status,void * _work)2092 static void mlx5_cmd_exec_cb_handler(int status, void *_work)
2093 {
2094 struct mlx5_async_work *work = _work;
2095 struct mlx5_async_ctx *ctx;
2096
2097 ctx = work->ctx;
2098 status = cmd_status_err(ctx->dev, status, work->opcode, work->op_mod, work->out);
2099 work->user_callback(status, work);
2100 if (atomic_dec_and_test(&ctx->num_inflight))
2101 complete(&ctx->inflight_done);
2102 }
2103
mlx5_cmd_exec_cb(struct mlx5_async_ctx * ctx,void * in,int in_size,void * out,int out_size,mlx5_async_cbk_t callback,struct mlx5_async_work * work)2104 int mlx5_cmd_exec_cb(struct mlx5_async_ctx *ctx, void *in, int in_size,
2105 void *out, int out_size, mlx5_async_cbk_t callback,
2106 struct mlx5_async_work *work)
2107 {
2108 int ret;
2109
2110 work->ctx = ctx;
2111 work->user_callback = callback;
2112 work->opcode = in_to_opcode(in);
2113 work->op_mod = MLX5_GET(mbox_in, in, op_mod);
2114 work->out = out;
2115 if (WARN_ON(!atomic_inc_not_zero(&ctx->num_inflight)))
2116 return -EIO;
2117 ret = cmd_exec(ctx->dev, in, in_size, out, out_size,
2118 mlx5_cmd_exec_cb_handler, work, false);
2119 if (ret && atomic_dec_and_test(&ctx->num_inflight))
2120 complete(&ctx->inflight_done);
2121
2122 return ret;
2123 }
2124 EXPORT_SYMBOL(mlx5_cmd_exec_cb);
2125
destroy_msg_cache(struct mlx5_core_dev * dev)2126 static void destroy_msg_cache(struct mlx5_core_dev *dev)
2127 {
2128 struct cmd_msg_cache *ch;
2129 struct mlx5_cmd_msg *msg;
2130 struct mlx5_cmd_msg *n;
2131 int i;
2132
2133 for (i = 0; i < dev->profile.num_cmd_caches; i++) {
2134 ch = &dev->cmd.cache[i];
2135 list_for_each_entry_safe(msg, n, &ch->head, list) {
2136 list_del(&msg->list);
2137 mlx5_free_cmd_msg(dev, msg);
2138 }
2139 }
2140 }
2141
2142 static unsigned cmd_cache_num_ent[MLX5_NUM_COMMAND_CACHES] = {
2143 512, 32, 16, 8, 2
2144 };
2145
2146 static unsigned cmd_cache_ent_size[MLX5_NUM_COMMAND_CACHES] = {
2147 16 + MLX5_CMD_DATA_BLOCK_SIZE,
2148 16 + MLX5_CMD_DATA_BLOCK_SIZE * 2,
2149 16 + MLX5_CMD_DATA_BLOCK_SIZE * 16,
2150 16 + MLX5_CMD_DATA_BLOCK_SIZE * 256,
2151 16 + MLX5_CMD_DATA_BLOCK_SIZE * 512,
2152 };
2153
create_msg_cache(struct mlx5_core_dev * dev)2154 static void create_msg_cache(struct mlx5_core_dev *dev)
2155 {
2156 struct mlx5_cmd *cmd = &dev->cmd;
2157 struct cmd_msg_cache *ch;
2158 struct mlx5_cmd_msg *msg;
2159 int i;
2160 int k;
2161
2162 /* Initialize and fill the caches with initial entries */
2163 for (k = 0; k < dev->profile.num_cmd_caches; k++) {
2164 ch = &cmd->cache[k];
2165 spin_lock_init(&ch->lock);
2166 INIT_LIST_HEAD(&ch->head);
2167 ch->num_ent = cmd_cache_num_ent[k];
2168 ch->max_inbox_size = cmd_cache_ent_size[k];
2169 for (i = 0; i < ch->num_ent; i++) {
2170 msg = mlx5_alloc_cmd_msg(dev, GFP_KERNEL | __GFP_NOWARN,
2171 ch->max_inbox_size, 0);
2172 if (IS_ERR(msg))
2173 break;
2174 msg->parent = ch;
2175 list_add_tail(&msg->list, &ch->head);
2176 }
2177 }
2178 }
2179
alloc_cmd_page(struct mlx5_core_dev * dev,struct mlx5_cmd * cmd)2180 static int alloc_cmd_page(struct mlx5_core_dev *dev, struct mlx5_cmd *cmd)
2181 {
2182 cmd->cmd_alloc_buf = dma_alloc_coherent(mlx5_core_dma_dev(dev), MLX5_ADAPTER_PAGE_SIZE,
2183 &cmd->alloc_dma, GFP_KERNEL);
2184 if (!cmd->cmd_alloc_buf)
2185 return -ENOMEM;
2186
2187 /* make sure it is aligned to 4K */
2188 if (!((uintptr_t)cmd->cmd_alloc_buf & (MLX5_ADAPTER_PAGE_SIZE - 1))) {
2189 cmd->cmd_buf = cmd->cmd_alloc_buf;
2190 cmd->dma = cmd->alloc_dma;
2191 cmd->alloc_size = MLX5_ADAPTER_PAGE_SIZE;
2192 return 0;
2193 }
2194
2195 dma_free_coherent(mlx5_core_dma_dev(dev), MLX5_ADAPTER_PAGE_SIZE, cmd->cmd_alloc_buf,
2196 cmd->alloc_dma);
2197 cmd->cmd_alloc_buf = dma_alloc_coherent(mlx5_core_dma_dev(dev),
2198 2 * MLX5_ADAPTER_PAGE_SIZE - 1,
2199 &cmd->alloc_dma, GFP_KERNEL);
2200 if (!cmd->cmd_alloc_buf)
2201 return -ENOMEM;
2202
2203 cmd->cmd_buf = PTR_ALIGN(cmd->cmd_alloc_buf, MLX5_ADAPTER_PAGE_SIZE);
2204 cmd->dma = ALIGN(cmd->alloc_dma, MLX5_ADAPTER_PAGE_SIZE);
2205 cmd->alloc_size = 2 * MLX5_ADAPTER_PAGE_SIZE - 1;
2206 return 0;
2207 }
2208
free_cmd_page(struct mlx5_core_dev * dev,struct mlx5_cmd * cmd)2209 static void free_cmd_page(struct mlx5_core_dev *dev, struct mlx5_cmd *cmd)
2210 {
2211 dma_free_coherent(mlx5_core_dma_dev(dev), cmd->alloc_size, cmd->cmd_alloc_buf,
2212 cmd->alloc_dma);
2213 }
2214
cmdif_rev(struct mlx5_core_dev * dev)2215 static u16 cmdif_rev(struct mlx5_core_dev *dev)
2216 {
2217 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16;
2218 }
2219
mlx5_cmd_init(struct mlx5_core_dev * dev)2220 int mlx5_cmd_init(struct mlx5_core_dev *dev)
2221 {
2222 struct mlx5_cmd *cmd = &dev->cmd;
2223
2224 cmd->checksum_disabled = 1;
2225
2226 spin_lock_init(&cmd->alloc_lock);
2227 spin_lock_init(&cmd->token_lock);
2228
2229 set_wqname(dev);
2230 cmd->wq = create_singlethread_workqueue(cmd->wq_name);
2231 if (!cmd->wq) {
2232 mlx5_core_err(dev, "failed to create command workqueue\n");
2233 return -ENOMEM;
2234 }
2235
2236 mlx5_cmdif_debugfs_init(dev);
2237
2238 return 0;
2239 }
2240
mlx5_cmd_cleanup(struct mlx5_core_dev * dev)2241 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev)
2242 {
2243 struct mlx5_cmd *cmd = &dev->cmd;
2244
2245 mlx5_cmdif_debugfs_cleanup(dev);
2246 destroy_workqueue(cmd->wq);
2247 }
2248
mlx5_cmd_enable(struct mlx5_core_dev * dev)2249 int mlx5_cmd_enable(struct mlx5_core_dev *dev)
2250 {
2251 int size = sizeof(struct mlx5_cmd_prot_block);
2252 int align = roundup_pow_of_two(size);
2253 struct mlx5_cmd *cmd = &dev->cmd;
2254 u32 cmd_h, cmd_l;
2255 int err;
2256
2257 memset(&cmd->vars, 0, sizeof(cmd->vars));
2258 cmd->vars.cmdif_rev = cmdif_rev(dev);
2259 if (cmd->vars.cmdif_rev != CMD_IF_REV) {
2260 mlx5_core_err(dev,
2261 "Driver cmdif rev(%d) differs from firmware's(%d)\n",
2262 CMD_IF_REV, cmd->vars.cmdif_rev);
2263 return -EINVAL;
2264 }
2265
2266 cmd_l = ioread32be(&dev->iseg->cmdq_addr_l_sz) & 0xff;
2267 cmd->vars.log_sz = cmd_l >> 4 & 0xf;
2268 cmd->vars.log_stride = cmd_l & 0xf;
2269 if (1 << cmd->vars.log_sz > MLX5_MAX_COMMANDS) {
2270 mlx5_core_err(dev, "firmware reports too many outstanding commands %d\n",
2271 1 << cmd->vars.log_sz);
2272 return -EINVAL;
2273 }
2274
2275 if (cmd->vars.log_sz + cmd->vars.log_stride > MLX5_ADAPTER_PAGE_SHIFT) {
2276 mlx5_core_err(dev, "command queue size overflow\n");
2277 return -EINVAL;
2278 }
2279
2280 cmd->state = MLX5_CMDIF_STATE_DOWN;
2281 cmd->vars.max_reg_cmds = (1 << cmd->vars.log_sz) - 1;
2282 cmd->vars.bitmask = MLX5_CMD_MASK;
2283
2284 sema_init(&cmd->vars.sem, cmd->vars.max_reg_cmds);
2285 sema_init(&cmd->vars.pages_sem, 1);
2286 sema_init(&cmd->vars.throttle_sem, DIV_ROUND_UP(cmd->vars.max_reg_cmds, 2));
2287
2288 cmd->pool = dma_pool_create("mlx5_cmd", mlx5_core_dma_dev(dev), size, align, 0);
2289 if (!cmd->pool)
2290 return -ENOMEM;
2291
2292 err = alloc_cmd_page(dev, cmd);
2293 if (err)
2294 goto err_free_pool;
2295
2296 cmd_h = (u32)((u64)(cmd->dma) >> 32);
2297 cmd_l = (u32)(cmd->dma);
2298 if (cmd_l & 0xfff) {
2299 mlx5_core_err(dev, "invalid command queue address\n");
2300 err = -ENOMEM;
2301 goto err_cmd_page;
2302 }
2303
2304 iowrite32be(cmd_h, &dev->iseg->cmdq_addr_h);
2305 iowrite32be(cmd_l, &dev->iseg->cmdq_addr_l_sz);
2306
2307 /* Make sure firmware sees the complete address before we proceed */
2308 wmb();
2309
2310 mlx5_core_dbg(dev, "descriptor at dma 0x%llx\n", (unsigned long long)(cmd->dma));
2311
2312 cmd->mode = CMD_MODE_POLLING;
2313 cmd->allowed_opcode = CMD_ALLOWED_OPCODE_ALL;
2314
2315 create_msg_cache(dev);
2316 create_debugfs_files(dev);
2317
2318 return 0;
2319
2320 err_cmd_page:
2321 free_cmd_page(dev, cmd);
2322 err_free_pool:
2323 dma_pool_destroy(cmd->pool);
2324 return err;
2325 }
2326
mlx5_cmd_disable(struct mlx5_core_dev * dev)2327 void mlx5_cmd_disable(struct mlx5_core_dev *dev)
2328 {
2329 struct mlx5_cmd *cmd = &dev->cmd;
2330
2331 flush_workqueue(cmd->wq);
2332 clean_debug_files(dev);
2333 destroy_msg_cache(dev);
2334 free_cmd_page(dev, cmd);
2335 dma_pool_destroy(cmd->pool);
2336 }
2337
mlx5_cmd_set_state(struct mlx5_core_dev * dev,enum mlx5_cmdif_state cmdif_state)2338 void mlx5_cmd_set_state(struct mlx5_core_dev *dev,
2339 enum mlx5_cmdif_state cmdif_state)
2340 {
2341 dev->cmd.state = cmdif_state;
2342 }
2343