1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3 * Copyright (C) 2013 Imagination Technologies
4 * Author: Paul Burton <paul.burton@mips.com>
5 */
6
7 #ifndef __MIPS_ASM_MIPS_CPS_H__
8 # error Please include asm/mips-cps.h rather than asm/mips-cm.h
9 #endif
10
11 #ifndef __MIPS_ASM_MIPS_CM_H__
12 #define __MIPS_ASM_MIPS_CM_H__
13
14 #include <linux/bitfield.h>
15 #include <linux/bitops.h>
16 #include <linux/errno.h>
17
18 /* The base address of the CM GCR block */
19 extern void __iomem *mips_gcr_base;
20
21 /* The base address of the CM L2-only sync region */
22 extern void __iomem *mips_cm_l2sync_base;
23
24 /**
25 * __mips_cm_phys_base - retrieve the physical base address of the CM
26 *
27 * This function returns the physical base address of the Coherence Manager
28 * global control block, or 0 if no Coherence Manager is present. It provides
29 * a default implementation which reads the CMGCRBase register where available,
30 * and may be overridden by platforms which determine this address in a
31 * different way by defining a function with the same prototype except for the
32 * name mips_cm_phys_base (without underscores).
33 */
34 extern phys_addr_t __mips_cm_phys_base(void);
35
36 /*
37 * mips_cm_is64 - determine CM register width
38 *
39 * The CM register width is determined by the version of the CM, with CM3
40 * introducing 64 bit GCRs and all prior CM versions having 32 bit GCRs.
41 * However we may run a kernel built for MIPS32 on a system with 64 bit GCRs,
42 * or vice-versa. This variable indicates the width of the memory accesses
43 * that the kernel will perform to GCRs, which may differ from the actual
44 * width of the GCRs.
45 *
46 * It's set to 0 for 32-bit accesses and 1 for 64-bit accesses.
47 */
48 extern int mips_cm_is64;
49
50 /*
51 * mips_cm_is_l2_hci_broken - determine if HCI is broken
52 *
53 * Some CM reports show that Hardware Cache Initialization is
54 * complete, but in reality it's not the case. They also incorrectly
55 * indicate that Hardware Cache Initialization is supported. This
56 * flags allows warning about this broken feature.
57 */
58 extern bool mips_cm_is_l2_hci_broken;
59
60 /**
61 * mips_cm_error_report - Report CM cache errors
62 */
63 #ifdef CONFIG_MIPS_CM
64 extern void mips_cm_error_report(void);
65 #else
mips_cm_error_report(void)66 static inline void mips_cm_error_report(void) {}
67 #endif
68
69 /**
70 * mips_cm_probe - probe for a Coherence Manager
71 *
72 * Attempt to detect the presence of a Coherence Manager. Returns 0 if a CM
73 * is successfully detected, else -errno.
74 */
75 #ifdef CONFIG_MIPS_CM
76 extern int mips_cm_probe(void);
77 #else
mips_cm_probe(void)78 static inline int mips_cm_probe(void)
79 {
80 return -ENODEV;
81 }
82 #endif
83
84 /**
85 * mips_cm_present - determine whether a Coherence Manager is present
86 *
87 * Returns true if a CM is present in the system, else false.
88 */
mips_cm_present(void)89 static inline bool mips_cm_present(void)
90 {
91 #ifdef CONFIG_MIPS_CM
92 return mips_gcr_base != NULL;
93 #else
94 return false;
95 #endif
96 }
97
98 /**
99 * mips_cm_update_property - update property from the device tree
100 *
101 * Retrieve the properties from the device tree if a CM node exist and
102 * update the internal variable based on this.
103 */
104 #ifdef CONFIG_MIPS_CM
105 extern void mips_cm_update_property(void);
106 #else
mips_cm_update_property(void)107 static inline void mips_cm_update_property(void) {}
108 #endif
109
110 /**
111 * mips_cm_has_l2sync - determine whether an L2-only sync region is present
112 *
113 * Returns true if the system implements an L2-only sync region, else false.
114 */
mips_cm_has_l2sync(void)115 static inline bool mips_cm_has_l2sync(void)
116 {
117 #ifdef CONFIG_MIPS_CM
118 return mips_cm_l2sync_base != NULL;
119 #else
120 return false;
121 #endif
122 }
123
124 /* Offsets to register blocks from the CM base address */
125 #define MIPS_CM_GCB_OFS 0x0000 /* Global Control Block */
126 #define MIPS_CM_CLCB_OFS 0x2000 /* Core Local Control Block */
127 #define MIPS_CM_COCB_OFS 0x4000 /* Core Other Control Block */
128 #define MIPS_CM_GDB_OFS 0x6000 /* Global Debug Block */
129
130 /* Total size of the CM memory mapped registers */
131 #define MIPS_CM_GCR_SIZE 0x8000
132
133 /* Size of the L2-only sync region */
134 #define MIPS_CM_L2SYNC_SIZE 0x1000
135
136 #define GCR_ACCESSOR_RO(sz, off, name) \
137 CPS_ACCESSOR_RO(gcr, sz, MIPS_CM_GCB_OFS + off, name) \
138 CPS_ACCESSOR_RO(gcr, sz, MIPS_CM_COCB_OFS + off, redir_##name)
139
140 #define GCR_ACCESSOR_RW(sz, off, name) \
141 CPS_ACCESSOR_RW(gcr, sz, MIPS_CM_GCB_OFS + off, name) \
142 CPS_ACCESSOR_RW(gcr, sz, MIPS_CM_COCB_OFS + off, redir_##name)
143
144 #define GCR_CX_ACCESSOR_RO(sz, off, name) \
145 CPS_ACCESSOR_RO(gcr, sz, MIPS_CM_CLCB_OFS + off, cl_##name) \
146 CPS_ACCESSOR_RO(gcr, sz, MIPS_CM_COCB_OFS + off, co_##name)
147
148 #define GCR_CX_ACCESSOR_RW(sz, off, name) \
149 CPS_ACCESSOR_RW(gcr, sz, MIPS_CM_CLCB_OFS + off, cl_##name) \
150 CPS_ACCESSOR_RW(gcr, sz, MIPS_CM_COCB_OFS + off, co_##name)
151
152 /* GCR_CONFIG - Information about the system */
153 GCR_ACCESSOR_RO(64, 0x000, config)
154 #define CM_GCR_CONFIG_CLUSTER_COH_CAPABLE BIT_ULL(43)
155 #define CM_GCR_CONFIG_CLUSTER_ID GENMASK_ULL(39, 32)
156 #define CM_GCR_CONFIG_NUM_CLUSTERS GENMASK(29, 23)
157 #define CM_GCR_CONFIG_NUMIOCU GENMASK(15, 8)
158 #define CM_GCR_CONFIG_PCORES GENMASK(7, 0)
159
160 /* GCR_BASE - Base address of the Global Configuration Registers (GCRs) */
161 GCR_ACCESSOR_RW(64, 0x008, base)
162 #define CM_GCR_BASE_GCRBASE GENMASK_ULL(47, 15)
163 #define CM_GCR_BASE_CMDEFTGT GENMASK(1, 0)
164 #define CM_GCR_BASE_CMDEFTGT_MEM 0
165 #define CM_GCR_BASE_CMDEFTGT_RESERVED 1
166 #define CM_GCR_BASE_CMDEFTGT_IOCU0 2
167 #define CM_GCR_BASE_CMDEFTGT_IOCU1 3
168
169 /* GCR_ACCESS - Controls core/IOCU access to GCRs */
170 GCR_ACCESSOR_RW(32, 0x020, access)
171 #define CM_GCR_ACCESS_ACCESSEN GENMASK(7, 0)
172
173 /* GCR_REV - Indicates the Coherence Manager revision */
174 GCR_ACCESSOR_RO(32, 0x030, rev)
175 #define CM_GCR_REV_MAJOR GENMASK(15, 8)
176 #define CM_GCR_REV_MINOR GENMASK(7, 0)
177
178 #define CM_ENCODE_REV(major, minor) \
179 (FIELD_PREP(CM_GCR_REV_MAJOR, major) | \
180 FIELD_PREP(CM_GCR_REV_MINOR, minor))
181
182 #define CM_REV_CM2 CM_ENCODE_REV(6, 0)
183 #define CM_REV_CM2_5 CM_ENCODE_REV(7, 0)
184 #define CM_REV_CM3 CM_ENCODE_REV(8, 0)
185 #define CM_REV_CM3_5 CM_ENCODE_REV(9, 0)
186
187 /* GCR_ERR_CONTROL - Control error checking logic */
188 GCR_ACCESSOR_RW(32, 0x038, err_control)
189 #define CM_GCR_ERR_CONTROL_L2_ECC_EN BIT(1)
190 #define CM_GCR_ERR_CONTROL_L2_ECC_SUPPORT BIT(0)
191
192 /* GCR_ERR_MASK - Control which errors are reported as interrupts */
193 GCR_ACCESSOR_RW(64, 0x040, error_mask)
194
195 /* GCR_ERR_CAUSE - Indicates the type of error that occurred */
196 GCR_ACCESSOR_RW(64, 0x048, error_cause)
197 #define CM_GCR_ERROR_CAUSE_ERRTYPE GENMASK(31, 27)
198 #define CM3_GCR_ERROR_CAUSE_ERRTYPE GENMASK_ULL(63, 58)
199 #define CM_GCR_ERROR_CAUSE_ERRINFO GENMASK(26, 0)
200
201 /* GCR_ERR_ADDR - Indicates the address associated with an error */
202 GCR_ACCESSOR_RW(64, 0x050, error_addr)
203
204 /* GCR_ERR_MULT - Indicates when multiple errors have occurred */
205 GCR_ACCESSOR_RW(64, 0x058, error_mult)
206 #define CM_GCR_ERROR_MULT_ERR2ND GENMASK(4, 0)
207
208 /* GCR_L2_ONLY_SYNC_BASE - Base address of the L2 cache-only sync region */
209 GCR_ACCESSOR_RW(64, 0x070, l2_only_sync_base)
210 #define CM_GCR_L2_ONLY_SYNC_BASE_SYNCBASE GENMASK(31, 12)
211 #define CM_GCR_L2_ONLY_SYNC_BASE_SYNCEN BIT(0)
212
213 /* GCR_GIC_BASE - Base address of the Global Interrupt Controller (GIC) */
214 GCR_ACCESSOR_RW(64, 0x080, gic_base)
215 #define CM_GCR_GIC_BASE_GICBASE GENMASK(31, 17)
216 #define CM_GCR_GIC_BASE_GICEN BIT(0)
217
218 /* GCR_CPC_BASE - Base address of the Cluster Power Controller (CPC) */
219 GCR_ACCESSOR_RW(64, 0x088, cpc_base)
220 #define CM_GCR_CPC_BASE_CPCBASE GENMASK(31, 15)
221 #define CM_GCR_CPC_BASE_CPCEN BIT(0)
222
223 /* GCR_REGn_BASE - Base addresses of CM address regions */
224 GCR_ACCESSOR_RW(64, 0x090, reg0_base)
225 GCR_ACCESSOR_RW(64, 0x0a0, reg1_base)
226 GCR_ACCESSOR_RW(64, 0x0b0, reg2_base)
227 GCR_ACCESSOR_RW(64, 0x0c0, reg3_base)
228 #define CM_GCR_REGn_BASE_BASEADDR GENMASK(31, 16)
229
230 /* GCR_REGn_MASK - Size & destination of CM address regions */
231 GCR_ACCESSOR_RW(64, 0x098, reg0_mask)
232 GCR_ACCESSOR_RW(64, 0x0a8, reg1_mask)
233 GCR_ACCESSOR_RW(64, 0x0b8, reg2_mask)
234 GCR_ACCESSOR_RW(64, 0x0c8, reg3_mask)
235 #define CM_GCR_REGn_MASK_ADDRMASK GENMASK(31, 16)
236 #define CM_GCR_REGn_MASK_CCAOVR GENMASK(7, 5)
237 #define CM_GCR_REGn_MASK_CCAOVREN BIT(4)
238 #define CM_GCR_REGn_MASK_DROPL2 BIT(2)
239 #define CM_GCR_REGn_MASK_CMTGT GENMASK(1, 0)
240 #define CM_GCR_REGn_MASK_CMTGT_DISABLED 0x0
241 #define CM_GCR_REGn_MASK_CMTGT_MEM 0x1
242 #define CM_GCR_REGn_MASK_CMTGT_IOCU0 0x2
243 #define CM_GCR_REGn_MASK_CMTGT_IOCU1 0x3
244
245 /* GCR_GIC_STATUS - Indicates presence of a Global Interrupt Controller (GIC) */
246 GCR_ACCESSOR_RO(32, 0x0d0, gic_status)
247 #define CM_GCR_GIC_STATUS_EX BIT(0)
248
249 /* GCR_CPC_STATUS - Indicates presence of a Cluster Power Controller (CPC) */
250 GCR_ACCESSOR_RO(32, 0x0f0, cpc_status)
251 #define CM_GCR_CPC_STATUS_EX BIT(0)
252
253 /* GCR_ACCESS - Controls core/IOCU access to GCRs */
254 GCR_ACCESSOR_RW(32, 0x120, access_cm3)
255 #define CM_GCR_ACCESS_ACCESSEN GENMASK(7, 0)
256
257 /* GCR_L2_CONFIG - Indicates L2 cache configuration when Config5.L2C=1 */
258 GCR_ACCESSOR_RW(32, 0x130, l2_config)
259 #define CM_GCR_L2_CONFIG_BYPASS BIT(20)
260 #define CM_GCR_L2_CONFIG_SET_SIZE GENMASK(15, 12)
261 #define CM_GCR_L2_CONFIG_LINE_SIZE GENMASK(11, 8)
262 #define CM_GCR_L2_CONFIG_ASSOC GENMASK(7, 0)
263
264 /* GCR_SYS_CONFIG2 - Further information about the system */
265 GCR_ACCESSOR_RO(32, 0x150, sys_config2)
266 #define CM_GCR_SYS_CONFIG2_MAXVPW GENMASK(3, 0)
267
268 /* GCR_L2_PFT_CONTROL - Controls hardware L2 prefetching */
269 GCR_ACCESSOR_RW(32, 0x300, l2_pft_control)
270 #define CM_GCR_L2_PFT_CONTROL_PAGEMASK GENMASK(31, 12)
271 #define CM_GCR_L2_PFT_CONTROL_PFTEN BIT(8)
272 #define CM_GCR_L2_PFT_CONTROL_NPFT GENMASK(7, 0)
273
274 /* GCR_L2_PFT_CONTROL_B - Controls hardware L2 prefetching */
275 GCR_ACCESSOR_RW(32, 0x308, l2_pft_control_b)
276 #define CM_GCR_L2_PFT_CONTROL_B_CEN BIT(8)
277 #define CM_GCR_L2_PFT_CONTROL_B_PORTID GENMASK(7, 0)
278
279 /* GCR_L2SM_COP - L2 cache op state machine control */
280 GCR_ACCESSOR_RW(32, 0x620, l2sm_cop)
281 #define CM_GCR_L2SM_COP_PRESENT BIT(31)
282 #define CM_GCR_L2SM_COP_RESULT GENMASK(8, 6)
283 #define CM_GCR_L2SM_COP_RESULT_DONTCARE 0
284 #define CM_GCR_L2SM_COP_RESULT_DONE_OK 1
285 #define CM_GCR_L2SM_COP_RESULT_DONE_ERROR 2
286 #define CM_GCR_L2SM_COP_RESULT_ABORT_OK 3
287 #define CM_GCR_L2SM_COP_RESULT_ABORT_ERROR 4
288 #define CM_GCR_L2SM_COP_RUNNING BIT(5)
289 #define CM_GCR_L2SM_COP_TYPE GENMASK(4, 2)
290 #define CM_GCR_L2SM_COP_TYPE_IDX_WBINV 0
291 #define CM_GCR_L2SM_COP_TYPE_IDX_STORETAG 1
292 #define CM_GCR_L2SM_COP_TYPE_IDX_STORETAGDATA 2
293 #define CM_GCR_L2SM_COP_TYPE_HIT_INV 4
294 #define CM_GCR_L2SM_COP_TYPE_HIT_WBINV 5
295 #define CM_GCR_L2SM_COP_TYPE_HIT_WB 6
296 #define CM_GCR_L2SM_COP_TYPE_FETCHLOCK 7
297 #define CM_GCR_L2SM_COP_CMD GENMASK(1, 0)
298 #define CM_GCR_L2SM_COP_CMD_START 1 /* only when idle */
299 #define CM_GCR_L2SM_COP_CMD_ABORT 3 /* only when running */
300
301 /* GCR_L2SM_TAG_ADDR_COP - L2 cache op state machine address control */
302 GCR_ACCESSOR_RW(64, 0x628, l2sm_tag_addr_cop)
303 #define CM_GCR_L2SM_TAG_ADDR_COP_NUM_LINES GENMASK_ULL(63, 48)
304 #define CM_GCR_L2SM_TAG_ADDR_COP_START_TAG GENMASK_ULL(47, 6)
305
306 /* GCR_BEV_BASE - Controls the location of the BEV for powered up cores */
307 GCR_ACCESSOR_RW(64, 0x680, bev_base)
308
309 /* GCR_Cx_RESET_RELEASE - Controls core reset for CM 1.x */
310 GCR_CX_ACCESSOR_RW(32, 0x000, reset_release)
311
312 /* GCR_Cx_COHERENCE - Controls core coherence */
313 GCR_CX_ACCESSOR_RW(32, 0x008, coherence)
314 #define CM_GCR_Cx_COHERENCE_COHDOMAINEN GENMASK(7, 0)
315 #define CM3_GCR_Cx_COHERENCE_COHEN BIT(0)
316
317 /* GCR_Cx_CONFIG - Information about a core's configuration */
318 GCR_CX_ACCESSOR_RO(32, 0x010, config)
319 #define CM_GCR_Cx_CONFIG_IOCUTYPE GENMASK(11, 10)
320 #define CM_GCR_Cx_CONFIG_PVPE GENMASK(9, 0)
321
322 /* GCR_Cx_OTHER - Configure the core-other/redirect GCR block */
323 GCR_CX_ACCESSOR_RW(32, 0x018, other)
324 #define CM_GCR_Cx_OTHER_CORENUM GENMASK(31, 16) /* CM < 3 */
325 #define CM_GCR_Cx_OTHER_CLUSTER_EN BIT(31) /* CM >= 3.5 */
326 #define CM_GCR_Cx_OTHER_GIC_EN BIT(30) /* CM >= 3.5 */
327 #define CM_GCR_Cx_OTHER_BLOCK GENMASK(25, 24) /* CM >= 3.5 */
328 #define CM_GCR_Cx_OTHER_BLOCK_LOCAL 0
329 #define CM_GCR_Cx_OTHER_BLOCK_GLOBAL 1
330 #define CM_GCR_Cx_OTHER_BLOCK_USER 2
331 #define CM_GCR_Cx_OTHER_BLOCK_GLOBAL_HIGH 3
332 #define CM_GCR_Cx_OTHER_CLUSTER GENMASK(21, 16) /* CM >= 3.5 */
333 #define CM3_GCR_Cx_OTHER_CORE GENMASK(13, 8) /* CM >= 3 */
334 #define CM_GCR_Cx_OTHER_CORE_CM 32
335 #define CM3_GCR_Cx_OTHER_VP GENMASK(2, 0) /* CM >= 3 */
336
337 /* GCR_Cx_RESET_BASE - Configure where powered up cores will fetch from */
338 GCR_CX_ACCESSOR_RW(32, 0x020, reset_base)
339 #define CM_GCR_Cx_RESET_BASE_BEVEXCBASE GENMASK(31, 12)
340
341 /* GCR_Cx_ID - Identify the current core */
342 GCR_CX_ACCESSOR_RO(32, 0x028, id)
343 #define CM_GCR_Cx_ID_CLUSTER GENMASK(15, 8)
344 #define CM_GCR_Cx_ID_CORE GENMASK(7, 0)
345
346 /* GCR_Cx_RESET_EXT_BASE - Configure behaviour when cores reset or power up */
347 GCR_CX_ACCESSOR_RW(32, 0x030, reset_ext_base)
348 #define CM_GCR_Cx_RESET_EXT_BASE_EVARESET BIT(31)
349 #define CM_GCR_Cx_RESET_EXT_BASE_UEB BIT(30)
350 #define CM_GCR_Cx_RESET_EXT_BASE_BEVEXCMASK GENMASK(27, 20)
351 #define CM_GCR_Cx_RESET_EXT_BASE_BEVEXCPA GENMASK(7, 1)
352 #define CM_GCR_Cx_RESET_EXT_BASE_PRESENT BIT(0)
353
354 /**
355 * mips_cm_l2sync - perform an L2-only sync operation
356 *
357 * If an L2-only sync region is present in the system then this function
358 * performs and L2-only sync and returns zero. Otherwise it returns -ENODEV.
359 */
mips_cm_l2sync(void)360 static inline int mips_cm_l2sync(void)
361 {
362 if (!mips_cm_has_l2sync())
363 return -ENODEV;
364
365 writel(0, mips_cm_l2sync_base);
366 return 0;
367 }
368
369 /**
370 * mips_cm_revision() - return CM revision
371 *
372 * Return: The revision of the CM, from GCR_REV, or 0 if no CM is present. The
373 * return value should be checked against the CM_REV_* macros.
374 */
mips_cm_revision(void)375 static inline int mips_cm_revision(void)
376 {
377 if (!mips_cm_present())
378 return 0;
379
380 return read_gcr_rev();
381 }
382
383 /**
384 * mips_cm_max_vp_width() - return the width in bits of VP indices
385 *
386 * Return: the width, in bits, of VP indices in fields that combine core & VP
387 * indices.
388 */
mips_cm_max_vp_width(void)389 static inline unsigned int mips_cm_max_vp_width(void)
390 {
391 extern int smp_num_siblings;
392
393 if (mips_cm_revision() >= CM_REV_CM3)
394 return FIELD_GET(CM_GCR_SYS_CONFIG2_MAXVPW,
395 read_gcr_sys_config2());
396
397 if (mips_cm_present()) {
398 /*
399 * We presume that all cores in the system will have the same
400 * number of VP(E)s, and if that ever changes then this will
401 * need revisiting.
402 */
403 return FIELD_GET(CM_GCR_Cx_CONFIG_PVPE, read_gcr_cl_config()) + 1;
404 }
405
406 if (IS_ENABLED(CONFIG_SMP))
407 return smp_num_siblings;
408
409 return 1;
410 }
411
412 /**
413 * mips_cm_vp_id() - calculate the hardware VP ID for a CPU
414 * @cpu: the CPU whose VP ID to calculate
415 *
416 * Hardware such as the GIC uses identifiers for VPs which may not match the
417 * CPU numbers used by Linux. This function calculates the hardware VP
418 * identifier corresponding to a given CPU.
419 *
420 * Return: the VP ID for the CPU.
421 */
mips_cm_vp_id(unsigned int cpu)422 static inline unsigned int mips_cm_vp_id(unsigned int cpu)
423 {
424 unsigned int core = cpu_core(&cpu_data[cpu]);
425 unsigned int vp = cpu_vpe_id(&cpu_data[cpu]);
426
427 return (core * mips_cm_max_vp_width()) + vp;
428 }
429
430 #ifdef CONFIG_MIPS_CM
431
432 /**
433 * mips_cm_lock_other - lock access to redirect/other region
434 * @cluster: the other cluster to be accessed
435 * @core: the other core to be accessed
436 * @vp: the VP within the other core to be accessed
437 * @block: the register block to be accessed
438 *
439 * Configure the redirect/other region for the local core/VP (depending upon
440 * the CM revision) to target the specified @cluster, @core, @vp & register
441 * @block. Must be called before using the redirect/other region, and followed
442 * by a call to mips_cm_unlock_other() when access to the redirect/other region
443 * is complete.
444 *
445 * This function acquires a spinlock such that code between it &
446 * mips_cm_unlock_other() calls cannot be pre-empted by anything which may
447 * reconfigure the redirect/other region, and cannot be interfered with by
448 * another VP in the core. As such calls to this function should not be nested.
449 */
450 extern void mips_cm_lock_other(unsigned int cluster, unsigned int core,
451 unsigned int vp, unsigned int block);
452
453 /**
454 * mips_cm_unlock_other - unlock access to redirect/other region
455 *
456 * Must be called after mips_cm_lock_other() once all required access to the
457 * redirect/other region has been completed.
458 */
459 extern void mips_cm_unlock_other(void);
460
461 #else /* !CONFIG_MIPS_CM */
462
mips_cm_lock_other(unsigned int cluster,unsigned int core,unsigned int vp,unsigned int block)463 static inline void mips_cm_lock_other(unsigned int cluster, unsigned int core,
464 unsigned int vp, unsigned int block) { }
mips_cm_unlock_other(void)465 static inline void mips_cm_unlock_other(void) { }
466
467 #endif /* !CONFIG_MIPS_CM */
468
469 /**
470 * mips_cm_lock_other_cpu - lock access to redirect/other region
471 * @cpu: the other CPU whose register we want to access
472 *
473 * Configure the redirect/other region for the local core/VP (depending upon
474 * the CM revision) to target the specified @cpu & register @block. This is
475 * equivalent to calling mips_cm_lock_other() but accepts a Linux CPU number
476 * for convenience.
477 */
mips_cm_lock_other_cpu(unsigned int cpu,unsigned int block)478 static inline void mips_cm_lock_other_cpu(unsigned int cpu, unsigned int block)
479 {
480 struct cpuinfo_mips *d = &cpu_data[cpu];
481
482 mips_cm_lock_other(cpu_cluster(d), cpu_core(d), cpu_vpe_id(d), block);
483 }
484
485 #endif /* __MIPS_ASM_MIPS_CM_H__ */
486