xref: /openbmc/linux/arch/mips/include/asm/processor.h (revision b6007ff8)
1 /*
2  * This file is subject to the terms and conditions of the GNU General Public
3  * License.  See the file "COPYING" in the main directory of this archive
4  * for more details.
5  *
6  * Copyright (C) 1994 Waldorf GMBH
7  * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003 Ralf Baechle
8  * Copyright (C) 1996 Paul M. Antoine
9  * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
10  */
11 #ifndef _ASM_PROCESSOR_H
12 #define _ASM_PROCESSOR_H
13 
14 #include <linux/atomic.h>
15 #include <linux/cpumask.h>
16 #include <linux/sizes.h>
17 #include <linux/threads.h>
18 
19 #include <asm/cachectl.h>
20 #include <asm/cpu.h>
21 #include <asm/cpu-info.h>
22 #include <asm/dsemul.h>
23 #include <asm/mipsregs.h>
24 #include <asm/prefetch.h>
25 #include <asm/vdso/processor.h>
26 
27 /*
28  * System setup and hardware flags..
29  */
30 
31 extern unsigned int vced_count, vcei_count;
32 extern int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src);
33 
34 #ifdef CONFIG_32BIT
35 /*
36  * User space process size: 2GB. This is hardcoded into a few places,
37  * so don't change it unless you know what you are doing.
38  */
39 #define TASK_SIZE	0x80000000UL
40 
41 #define STACK_TOP_MAX	TASK_SIZE
42 
43 #define TASK_IS_32BIT_ADDR 1
44 
45 #endif
46 
47 #ifdef CONFIG_64BIT
48 /*
49  * User space process size: 1TB. This is hardcoded into a few places,
50  * so don't change it unless you know what you are doing.  TASK_SIZE
51  * is limited to 1TB by the R4000 architecture; R10000 and better can
52  * support 16TB; the architectural reserve for future expansion is
53  * 8192EB ...
54  */
55 #define TASK_SIZE32	0x7fff8000UL
56 #ifdef CONFIG_MIPS_VA_BITS_48
57 #define TASK_SIZE64     (0x1UL << ((cpu_data[0].vmbits>48)?48:cpu_data[0].vmbits))
58 #else
59 #define TASK_SIZE64     0x10000000000UL
60 #endif
61 #define TASK_SIZE (test_thread_flag(TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE64)
62 #define STACK_TOP_MAX	TASK_SIZE64
63 
64 #define TASK_SIZE_OF(tsk)						\
65 	(test_tsk_thread_flag(tsk, TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE64)
66 
67 #define TASK_IS_32BIT_ADDR test_thread_flag(TIF_32BIT_ADDR)
68 
69 #endif
70 
71 #define VDSO_RANDOMIZE_SIZE	(TASK_IS_32BIT_ADDR ? SZ_1M : SZ_64M)
72 
73 extern unsigned long mips_stack_top(void);
74 #define STACK_TOP		mips_stack_top()
75 
76 /*
77  * This decides where the kernel will search for a free chunk of vm
78  * space during mmap's.
79  */
80 #define TASK_UNMAPPED_BASE PAGE_ALIGN(TASK_SIZE / 3)
81 
82 
83 #define NUM_FPU_REGS	32
84 
85 #ifdef CONFIG_CPU_HAS_MSA
86 # define FPU_REG_WIDTH	128
87 #else
88 # define FPU_REG_WIDTH	64
89 #endif
90 
91 union fpureg {
92 	__u32	val32[FPU_REG_WIDTH / 32];
93 	__u64	val64[FPU_REG_WIDTH / 64];
94 };
95 
96 #ifdef CONFIG_CPU_LITTLE_ENDIAN
97 # define FPR_IDX(width, idx)	(idx)
98 #else
99 # define FPR_IDX(width, idx)	((idx) ^ ((64 / (width)) - 1))
100 #endif
101 
102 #define BUILD_FPR_ACCESS(width) \
103 static inline u##width get_fpr##width(union fpureg *fpr, unsigned idx)	\
104 {									\
105 	return fpr->val##width[FPR_IDX(width, idx)];			\
106 }									\
107 									\
108 static inline void set_fpr##width(union fpureg *fpr, unsigned idx,	\
109 				  u##width val)				\
110 {									\
111 	fpr->val##width[FPR_IDX(width, idx)] = val;			\
112 }
113 
114 BUILD_FPR_ACCESS(32)
115 BUILD_FPR_ACCESS(64)
116 
117 /*
118  * It would be nice to add some more fields for emulator statistics,
119  * the additional information is private to the FPU emulator for now.
120  * See arch/mips/include/asm/fpu_emulator.h.
121  */
122 
123 struct mips_fpu_struct {
124 	union fpureg	fpr[NUM_FPU_REGS];
125 	unsigned int	fcr31;
126 	unsigned int	msacsr;
127 };
128 
129 #define NUM_DSP_REGS   6
130 
131 typedef unsigned long dspreg_t;
132 
133 struct mips_dsp_state {
134 	dspreg_t	dspr[NUM_DSP_REGS];
135 	unsigned int	dspcontrol;
136 };
137 
138 #define INIT_CPUMASK { \
139 	{0,} \
140 }
141 
142 struct mips3264_watch_reg_state {
143 	/* The width of watchlo is 32 in a 32 bit kernel and 64 in a
144 	   64 bit kernel.  We use unsigned long as it has the same
145 	   property. */
146 	unsigned long watchlo[NUM_WATCH_REGS];
147 	/* Only the mask and IRW bits from watchhi. */
148 	u16 watchhi[NUM_WATCH_REGS];
149 };
150 
151 union mips_watch_reg_state {
152 	struct mips3264_watch_reg_state mips3264;
153 };
154 
155 #if defined(CONFIG_CPU_CAVIUM_OCTEON)
156 
157 struct octeon_cop2_state {
158 	/* DMFC2 rt, 0x0201 */
159 	unsigned long	cop2_crc_iv;
160 	/* DMFC2 rt, 0x0202 (Set with DMTC2 rt, 0x1202) */
161 	unsigned long	cop2_crc_length;
162 	/* DMFC2 rt, 0x0200 (set with DMTC2 rt, 0x4200) */
163 	unsigned long	cop2_crc_poly;
164 	/* DMFC2 rt, 0x0402; DMFC2 rt, 0x040A */
165 	unsigned long	cop2_llm_dat[2];
166        /* DMFC2 rt, 0x0084 */
167 	unsigned long	cop2_3des_iv;
168 	/* DMFC2 rt, 0x0080; DMFC2 rt, 0x0081; DMFC2 rt, 0x0082 */
169 	unsigned long	cop2_3des_key[3];
170 	/* DMFC2 rt, 0x0088 (Set with DMTC2 rt, 0x0098) */
171 	unsigned long	cop2_3des_result;
172 	/* DMFC2 rt, 0x0111 (FIXME: Read Pass1 Errata) */
173 	unsigned long	cop2_aes_inp0;
174 	/* DMFC2 rt, 0x0102; DMFC2 rt, 0x0103 */
175 	unsigned long	cop2_aes_iv[2];
176 	/* DMFC2 rt, 0x0104; DMFC2 rt, 0x0105; DMFC2 rt, 0x0106; DMFC2
177 	 * rt, 0x0107 */
178 	unsigned long	cop2_aes_key[4];
179 	/* DMFC2 rt, 0x0110 */
180 	unsigned long	cop2_aes_keylen;
181 	/* DMFC2 rt, 0x0100; DMFC2 rt, 0x0101 */
182 	unsigned long	cop2_aes_result[2];
183 	/* DMFC2 rt, 0x0240; DMFC2 rt, 0x0241; DMFC2 rt, 0x0242; DMFC2
184 	 * rt, 0x0243; DMFC2 rt, 0x0244; DMFC2 rt, 0x0245; DMFC2 rt,
185 	 * 0x0246; DMFC2 rt, 0x0247; DMFC2 rt, 0x0248; DMFC2 rt,
186 	 * 0x0249; DMFC2 rt, 0x024A; DMFC2 rt, 0x024B; DMFC2 rt,
187 	 * 0x024C; DMFC2 rt, 0x024D; DMFC2 rt, 0x024E - Pass2 */
188 	unsigned long	cop2_hsh_datw[15];
189 	/* DMFC2 rt, 0x0250; DMFC2 rt, 0x0251; DMFC2 rt, 0x0252; DMFC2
190 	 * rt, 0x0253; DMFC2 rt, 0x0254; DMFC2 rt, 0x0255; DMFC2 rt,
191 	 * 0x0256; DMFC2 rt, 0x0257 - Pass2 */
192 	unsigned long	cop2_hsh_ivw[8];
193 	/* DMFC2 rt, 0x0258; DMFC2 rt, 0x0259 - Pass2 */
194 	unsigned long	cop2_gfm_mult[2];
195 	/* DMFC2 rt, 0x025E - Pass2 */
196 	unsigned long	cop2_gfm_poly;
197 	/* DMFC2 rt, 0x025A; DMFC2 rt, 0x025B - Pass2 */
198 	unsigned long	cop2_gfm_result[2];
199 	/* DMFC2 rt, 0x24F, DMFC2 rt, 0x50, OCTEON III */
200 	unsigned long	cop2_sha3[2];
201 };
202 #define COP2_INIT						\
203 	.cp2			= {0,},
204 
205 #if defined(CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE) && \
206 	CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0
207 struct octeon_cvmseg_state {
208 	unsigned long cvmseg[CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE]
209 			    [cpu_dcache_line_size() / sizeof(unsigned long)];
210 };
211 #endif
212 #else
213 #define COP2_INIT
214 #endif
215 
216 #ifdef CONFIG_CPU_HAS_MSA
217 # define ARCH_MIN_TASKALIGN	16
218 # define FPU_ALIGN		__aligned(16)
219 #else
220 # define ARCH_MIN_TASKALIGN	8
221 # define FPU_ALIGN
222 #endif
223 
224 struct mips_abi;
225 
226 /*
227  * If you change thread_struct remember to change the #defines below too!
228  */
229 struct thread_struct {
230 	/* Saved main processor registers. */
231 	unsigned long reg16;
232 	unsigned long reg17, reg18, reg19, reg20, reg21, reg22, reg23;
233 	unsigned long reg29, reg30, reg31;
234 
235 	/* Saved cp0 stuff. */
236 	unsigned long cp0_status;
237 
238 #ifdef CONFIG_MIPS_FP_SUPPORT
239 	/* Saved fpu/fpu emulator stuff. */
240 	struct mips_fpu_struct fpu FPU_ALIGN;
241 	/* Assigned branch delay slot 'emulation' frame */
242 	atomic_t bd_emu_frame;
243 	/* PC of the branch from a branch delay slot 'emulation' */
244 	unsigned long bd_emu_branch_pc;
245 	/* PC to continue from following a branch delay slot 'emulation' */
246 	unsigned long bd_emu_cont_pc;
247 #endif
248 #ifdef CONFIG_MIPS_MT_FPAFF
249 	/* Emulated instruction count */
250 	unsigned long emulated_fp;
251 	/* Saved per-thread scheduler affinity mask */
252 	cpumask_t user_cpus_allowed;
253 #endif /* CONFIG_MIPS_MT_FPAFF */
254 
255 	/* Saved state of the DSP ASE, if available. */
256 	struct mips_dsp_state dsp;
257 
258 	/* Saved watch register state, if available. */
259 	union mips_watch_reg_state watch;
260 
261 	/* Other stuff associated with the thread. */
262 	unsigned long cp0_badvaddr;	/* Last user fault */
263 	unsigned long cp0_baduaddr;	/* Last kernel fault accessing USEG */
264 	unsigned long error_code;
265 	unsigned long trap_nr;
266 #ifdef CONFIG_CPU_CAVIUM_OCTEON
267 	struct octeon_cop2_state cp2 __attribute__ ((__aligned__(128)));
268 #if defined(CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE) && \
269 	CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0
270 	struct octeon_cvmseg_state cvmseg __attribute__ ((__aligned__(128)));
271 #endif
272 #endif
273 	struct mips_abi *abi;
274 };
275 
276 #ifdef CONFIG_MIPS_MT_FPAFF
277 #define FPAFF_INIT						\
278 	.emulated_fp			= 0,			\
279 	.user_cpus_allowed		= INIT_CPUMASK,
280 #else
281 #define FPAFF_INIT
282 #endif /* CONFIG_MIPS_MT_FPAFF */
283 
284 #ifdef CONFIG_MIPS_FP_SUPPORT
285 # define FPU_INIT						\
286 	.fpu			= {				\
287 		.fpr		= {{{0,},},},			\
288 		.fcr31		= 0,				\
289 		.msacsr		= 0,				\
290 	},							\
291 	/* Delay slot emulation */				\
292 	.bd_emu_frame = ATOMIC_INIT(BD_EMUFRAME_NONE),		\
293 	.bd_emu_branch_pc = 0,					\
294 	.bd_emu_cont_pc = 0,
295 #else
296 # define FPU_INIT
297 #endif
298 
299 #define INIT_THREAD  {						\
300 	/*							\
301 	 * Saved main processor registers			\
302 	 */							\
303 	.reg16			= 0,				\
304 	.reg17			= 0,				\
305 	.reg18			= 0,				\
306 	.reg19			= 0,				\
307 	.reg20			= 0,				\
308 	.reg21			= 0,				\
309 	.reg22			= 0,				\
310 	.reg23			= 0,				\
311 	.reg29			= 0,				\
312 	.reg30			= 0,				\
313 	.reg31			= 0,				\
314 	/*							\
315 	 * Saved cp0 stuff					\
316 	 */							\
317 	.cp0_status		= 0,				\
318 	/*							\
319 	 * Saved FPU/FPU emulator stuff				\
320 	 */							\
321 	FPU_INIT						\
322 	/*							\
323 	 * FPU affinity state (null if not FPAFF)		\
324 	 */							\
325 	FPAFF_INIT						\
326 	/*							\
327 	 * Saved DSP stuff					\
328 	 */							\
329 	.dsp			= {				\
330 		.dspr		= {0, },			\
331 		.dspcontrol	= 0,				\
332 	},							\
333 	/*							\
334 	 * saved watch register stuff				\
335 	 */							\
336 	.watch = {{{0,},},},					\
337 	/*							\
338 	 * Other stuff associated with the process		\
339 	 */							\
340 	.cp0_badvaddr		= 0,				\
341 	.cp0_baduaddr		= 0,				\
342 	.error_code		= 0,				\
343 	.trap_nr		= 0,				\
344 	/*							\
345 	 * Platform specific cop2 registers(null if no COP2)	\
346 	 */							\
347 	COP2_INIT						\
348 }
349 
350 struct task_struct;
351 
352 /*
353  * Do necessary setup to start up a newly executed thread.
354  */
355 extern void start_thread(struct pt_regs * regs, unsigned long pc, unsigned long sp);
356 
flush_thread(void)357 static inline void flush_thread(void)
358 {
359 }
360 
361 unsigned long __get_wchan(struct task_struct *p);
362 
363 #define __KSTK_TOS(tsk) ((unsigned long)task_stack_page(tsk) + \
364 			 THREAD_SIZE - 32 - sizeof(struct pt_regs))
365 #define task_pt_regs(tsk) ((struct pt_regs *)__KSTK_TOS(tsk))
366 #define KSTK_EIP(tsk) (task_pt_regs(tsk)->cp0_epc)
367 #define KSTK_ESP(tsk) (task_pt_regs(tsk)->regs[29])
368 #define KSTK_STATUS(tsk) (task_pt_regs(tsk)->cp0_status)
369 
370 /*
371  * Return_address is a replacement for __builtin_return_address(count)
372  * which on certain architectures cannot reasonably be implemented in GCC
373  * (MIPS, Alpha) or is unusable with -fomit-frame-pointer (i386).
374  * Note that __builtin_return_address(x>=1) is forbidden because GCC
375  * aborts compilation on some CPUs.  It's simply not possible to unwind
376  * some CPU's stackframes.
377  *
378  * __builtin_return_address works only for non-leaf functions.	We avoid the
379  * overhead of a function call by forcing the compiler to save the return
380  * address register on the stack.
381  */
382 #define return_address() ({__asm__ __volatile__("":::"$31");__builtin_return_address(0);})
383 
384 #ifdef CONFIG_CPU_HAS_PREFETCH
385 
386 #define ARCH_HAS_PREFETCH
387 #define prefetch(x) __builtin_prefetch((x), 0, 1)
388 
389 #define ARCH_HAS_PREFETCHW
390 #define prefetchw(x) __builtin_prefetch((x), 1, 1)
391 
392 #endif
393 
394 /*
395  * Functions & macros implementing the PR_GET_FP_MODE & PR_SET_FP_MODE options
396  * to the prctl syscall.
397  */
398 extern int mips_get_process_fp_mode(struct task_struct *task);
399 extern int mips_set_process_fp_mode(struct task_struct *task,
400 				    unsigned int value);
401 
402 #define GET_FP_MODE(task)		mips_get_process_fp_mode(task)
403 #define SET_FP_MODE(task,value)		mips_set_process_fp_mode(task, value)
404 
405 #endif /* _ASM_PROCESSOR_H */
406