1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Copyright 2008,2009 Ben Herrenschmidt <benh@kernel.crashing.org>
4 * IBM Corp.
5 *
6 * Derived from arch/ppc/mm/init.c:
7 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
8 *
9 * Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au)
10 * and Cort Dougan (PReP) (cort@cs.nmt.edu)
11 * Copyright (C) 1996 Paul Mackerras
12 *
13 * Derived from "arch/i386/mm/init.c"
14 * Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds
15 */
16
17 #include <linux/kernel.h>
18 #include <linux/export.h>
19 #include <linux/mm.h>
20 #include <linux/init.h>
21 #include <linux/pagemap.h>
22 #include <linux/memblock.h>
23
24 #include <asm/pgalloc.h>
25 #include <asm/tlbflush.h>
26 #include <asm/tlb.h>
27 #include <asm/code-patching.h>
28 #include <asm/cputhreads.h>
29
30 #include <mm/mmu_decl.h>
31
32 /* The variables below are currently only used on 64-bit Book3E
33 * though this will probably be made common with other nohash
34 * implementations at some point
35 */
36 static int mmu_pte_psize; /* Page size used for PTE pages */
37 int mmu_vmemmap_psize; /* Page size used for the virtual mem map */
38 int book3e_htw_mode; /* HW tablewalk? Value is PPC_HTW_* */
39 unsigned long linear_map_top; /* Top of linear mapping */
40
41
42 /*
43 * Number of bytes to add to SPRN_SPRG_TLB_EXFRAME on crit/mcheck/debug
44 * exceptions. This is used for bolted and e6500 TLB miss handlers which
45 * do not modify this SPRG in the TLB miss code; for other TLB miss handlers,
46 * this is set to zero.
47 */
48 int extlb_level_exc;
49
50 /*
51 * Handling of virtual linear page tables or indirect TLB entries
52 * flushing when PTE pages are freed
53 */
tlb_flush_pgtable(struct mmu_gather * tlb,unsigned long address)54 void tlb_flush_pgtable(struct mmu_gather *tlb, unsigned long address)
55 {
56 int tsize = mmu_psize_defs[mmu_pte_psize].enc;
57
58 if (book3e_htw_mode != PPC_HTW_NONE) {
59 unsigned long start = address & PMD_MASK;
60 unsigned long end = address + PMD_SIZE;
61 unsigned long size = 1UL << mmu_psize_defs[mmu_pte_psize].shift;
62
63 /* This isn't the most optimal, ideally we would factor out the
64 * while preempt & CPU mask mucking around, or even the IPI but
65 * it will do for now
66 */
67 while (start < end) {
68 __flush_tlb_page(tlb->mm, start, tsize, 1);
69 start += size;
70 }
71 } else {
72 unsigned long rmask = 0xf000000000000000ul;
73 unsigned long rid = (address & rmask) | 0x1000000000000000ul;
74 unsigned long vpte = address & ~rmask;
75
76 vpte = (vpte >> (PAGE_SHIFT - 3)) & ~0xffful;
77 vpte |= rid;
78 __flush_tlb_page(tlb->mm, vpte, tsize, 0);
79 }
80 }
81
setup_page_sizes(void)82 static void __init setup_page_sizes(void)
83 {
84 unsigned int tlb0cfg;
85 unsigned int eptcfg;
86 int psize;
87
88 #ifdef CONFIG_PPC_E500
89 unsigned int mmucfg = mfspr(SPRN_MMUCFG);
90 int fsl_mmu = mmu_has_feature(MMU_FTR_TYPE_FSL_E);
91
92 if (fsl_mmu && (mmucfg & MMUCFG_MAVN) == MMUCFG_MAVN_V1) {
93 unsigned int tlb1cfg = mfspr(SPRN_TLB1CFG);
94 unsigned int min_pg, max_pg;
95
96 min_pg = (tlb1cfg & TLBnCFG_MINSIZE) >> TLBnCFG_MINSIZE_SHIFT;
97 max_pg = (tlb1cfg & TLBnCFG_MAXSIZE) >> TLBnCFG_MAXSIZE_SHIFT;
98
99 for (psize = 0; psize < MMU_PAGE_COUNT; ++psize) {
100 struct mmu_psize_def *def;
101 unsigned int shift;
102
103 def = &mmu_psize_defs[psize];
104 shift = def->shift;
105
106 if (shift == 0 || shift & 1)
107 continue;
108
109 /* adjust to be in terms of 4^shift Kb */
110 shift = (shift - 10) >> 1;
111
112 if ((shift >= min_pg) && (shift <= max_pg))
113 def->flags |= MMU_PAGE_SIZE_DIRECT;
114 }
115
116 goto out;
117 }
118
119 if (fsl_mmu && (mmucfg & MMUCFG_MAVN) == MMUCFG_MAVN_V2) {
120 u32 tlb1cfg, tlb1ps;
121
122 tlb0cfg = mfspr(SPRN_TLB0CFG);
123 tlb1cfg = mfspr(SPRN_TLB1CFG);
124 tlb1ps = mfspr(SPRN_TLB1PS);
125 eptcfg = mfspr(SPRN_EPTCFG);
126
127 if ((tlb1cfg & TLBnCFG_IND) && (tlb0cfg & TLBnCFG_PT))
128 book3e_htw_mode = PPC_HTW_E6500;
129
130 /*
131 * We expect 4K subpage size and unrestricted indirect size.
132 * The lack of a restriction on indirect size is a Freescale
133 * extension, indicated by PSn = 0 but SPSn != 0.
134 */
135 if (eptcfg != 2)
136 book3e_htw_mode = PPC_HTW_NONE;
137
138 for (psize = 0; psize < MMU_PAGE_COUNT; ++psize) {
139 struct mmu_psize_def *def = &mmu_psize_defs[psize];
140
141 if (!def->shift)
142 continue;
143
144 if (tlb1ps & (1U << (def->shift - 10))) {
145 def->flags |= MMU_PAGE_SIZE_DIRECT;
146
147 if (book3e_htw_mode && psize == MMU_PAGE_2M)
148 def->flags |= MMU_PAGE_SIZE_INDIRECT;
149 }
150 }
151
152 goto out;
153 }
154 #endif
155 out:
156 /* Cleanup array and print summary */
157 pr_info("MMU: Supported page sizes\n");
158 for (psize = 0; psize < MMU_PAGE_COUNT; ++psize) {
159 struct mmu_psize_def *def = &mmu_psize_defs[psize];
160 const char *__page_type_names[] = {
161 "unsupported",
162 "direct",
163 "indirect",
164 "direct & indirect"
165 };
166 if (def->flags == 0) {
167 def->shift = 0;
168 continue;
169 }
170 pr_info(" %8ld KB as %s\n", 1ul << (def->shift - 10),
171 __page_type_names[def->flags & 0x3]);
172 }
173 }
174
setup_mmu_htw(void)175 static void __init setup_mmu_htw(void)
176 {
177 /*
178 * If we want to use HW tablewalk, enable it by patching the TLB miss
179 * handlers to branch to the one dedicated to it.
180 */
181
182 switch (book3e_htw_mode) {
183 #ifdef CONFIG_PPC_E500
184 case PPC_HTW_E6500:
185 extlb_level_exc = EX_TLB_SIZE;
186 patch_exception(0x1c0, exc_data_tlb_miss_e6500_book3e);
187 patch_exception(0x1e0, exc_instruction_tlb_miss_e6500_book3e);
188 break;
189 #endif
190 }
191 pr_info("MMU: Book3E HW tablewalk %s\n",
192 book3e_htw_mode != PPC_HTW_NONE ? "enabled" : "not supported");
193 }
194
195 /*
196 * Early initialization of the MMU TLB code
197 */
early_init_this_mmu(void)198 static void early_init_this_mmu(void)
199 {
200 unsigned int mas4;
201
202 /* Set MAS4 based on page table setting */
203
204 mas4 = 0x4 << MAS4_WIMGED_SHIFT;
205 switch (book3e_htw_mode) {
206 case PPC_HTW_E6500:
207 mas4 |= MAS4_INDD;
208 mas4 |= BOOK3E_PAGESZ_2M << MAS4_TSIZED_SHIFT;
209 mas4 |= MAS4_TLBSELD(1);
210 mmu_pte_psize = MMU_PAGE_2M;
211 break;
212
213 case PPC_HTW_NONE:
214 mas4 |= BOOK3E_PAGESZ_4K << MAS4_TSIZED_SHIFT;
215 mmu_pte_psize = mmu_virtual_psize;
216 break;
217 }
218 mtspr(SPRN_MAS4, mas4);
219
220 #ifdef CONFIG_PPC_E500
221 if (mmu_has_feature(MMU_FTR_TYPE_FSL_E)) {
222 unsigned int num_cams;
223 bool map = true;
224
225 /* use a quarter of the TLBCAM for bolted linear map */
226 num_cams = (mfspr(SPRN_TLB1CFG) & TLBnCFG_N_ENTRY) / 4;
227
228 /*
229 * Only do the mapping once per core, or else the
230 * transient mapping would cause problems.
231 */
232 #ifdef CONFIG_SMP
233 if (hweight32(get_tensr()) > 1)
234 map = false;
235 #endif
236
237 if (map)
238 linear_map_top = map_mem_in_cams(linear_map_top,
239 num_cams, false, true);
240 }
241 #endif
242
243 /* A sync won't hurt us after mucking around with
244 * the MMU configuration
245 */
246 mb();
247 }
248
early_init_mmu_global(void)249 static void __init early_init_mmu_global(void)
250 {
251 /* XXX This should be decided at runtime based on supported
252 * page sizes in the TLB, but for now let's assume 16M is
253 * always there and a good fit (which it probably is)
254 *
255 * Freescale booke only supports 4K pages in TLB0, so use that.
256 */
257 if (mmu_has_feature(MMU_FTR_TYPE_FSL_E))
258 mmu_vmemmap_psize = MMU_PAGE_4K;
259 else
260 mmu_vmemmap_psize = MMU_PAGE_16M;
261
262 /* XXX This code only checks for TLB 0 capabilities and doesn't
263 * check what page size combos are supported by the HW. It
264 * also doesn't handle the case where a separate array holds
265 * the IND entries from the array loaded by the PT.
266 */
267 /* Look for supported page sizes */
268 setup_page_sizes();
269
270 /* Look for HW tablewalk support */
271 setup_mmu_htw();
272
273 #ifdef CONFIG_PPC_E500
274 if (mmu_has_feature(MMU_FTR_TYPE_FSL_E)) {
275 if (book3e_htw_mode == PPC_HTW_NONE) {
276 extlb_level_exc = EX_TLB_SIZE;
277 patch_exception(0x1c0, exc_data_tlb_miss_bolted_book3e);
278 patch_exception(0x1e0,
279 exc_instruction_tlb_miss_bolted_book3e);
280 }
281 }
282 #endif
283
284 /* Set the global containing the top of the linear mapping
285 * for use by the TLB miss code
286 */
287 linear_map_top = memblock_end_of_DRAM();
288
289 ioremap_bot = IOREMAP_BASE;
290 }
291
early_mmu_set_memory_limit(void)292 static void __init early_mmu_set_memory_limit(void)
293 {
294 #ifdef CONFIG_PPC_E500
295 if (mmu_has_feature(MMU_FTR_TYPE_FSL_E)) {
296 /*
297 * Limit memory so we dont have linear faults.
298 * Unlike memblock_set_current_limit, which limits
299 * memory available during early boot, this permanently
300 * reduces the memory available to Linux. We need to
301 * do this because highmem is not supported on 64-bit.
302 */
303 memblock_enforce_memory_limit(linear_map_top);
304 }
305 #endif
306
307 memblock_set_current_limit(linear_map_top);
308 }
309
310 /* boot cpu only */
early_init_mmu(void)311 void __init early_init_mmu(void)
312 {
313 early_init_mmu_global();
314 early_init_this_mmu();
315 early_mmu_set_memory_limit();
316 }
317
early_init_mmu_secondary(void)318 void early_init_mmu_secondary(void)
319 {
320 early_init_this_mmu();
321 }
322
setup_initial_memory_limit(phys_addr_t first_memblock_base,phys_addr_t first_memblock_size)323 void setup_initial_memory_limit(phys_addr_t first_memblock_base,
324 phys_addr_t first_memblock_size)
325 {
326 /* On non-FSL Embedded 64-bit, we adjust the RMA size to match
327 * the bolted TLB entry. We know for now that only 1G
328 * entries are supported though that may eventually
329 * change.
330 *
331 * on FSL Embedded 64-bit, usually all RAM is bolted, but with
332 * unusual memory sizes it's possible for some RAM to not be mapped
333 * (such RAM is not used at all by Linux, since we don't support
334 * highmem on 64-bit). We limit ppc64_rma_size to what would be
335 * mappable if this memblock is the only one. Additional memblocks
336 * can only increase, not decrease, the amount that ends up getting
337 * mapped. We still limit max to 1G even if we'll eventually map
338 * more. This is due to what the early init code is set up to do.
339 *
340 * We crop it to the size of the first MEMBLOCK to
341 * avoid going over total available memory just in case...
342 */
343 #ifdef CONFIG_PPC_E500
344 if (early_mmu_has_feature(MMU_FTR_TYPE_FSL_E)) {
345 unsigned long linear_sz;
346 unsigned int num_cams;
347
348 /* use a quarter of the TLBCAM for bolted linear map */
349 num_cams = (mfspr(SPRN_TLB1CFG) & TLBnCFG_N_ENTRY) / 4;
350
351 linear_sz = map_mem_in_cams(first_memblock_size, num_cams,
352 true, true);
353
354 ppc64_rma_size = min_t(u64, linear_sz, 0x40000000);
355 } else
356 #endif
357 ppc64_rma_size = min_t(u64, first_memblock_size, 0x40000000);
358
359 /* Finally limit subsequent allocations */
360 memblock_set_current_limit(first_memblock_base + ppc64_rma_size);
361 }
362