1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright (C) 2015, Bachmann electronic GmbH
4  */
5 
6 #include <common.h>
7 #include <spl.h>
8 #include <asm/arch/mx6-ddr.h>
9 
10 /* Configure MX6Q/DUAL mmdc DDR io registers */
11 static struct mx6dq_iomux_ddr_regs ot1200_ddr_ioregs = {
12 	/* SDCLK[0:1], CAS, RAS, Reset: Differential input, 48ohm */
13 	.dram_sdclk_0   = 0x00000028,
14 	.dram_sdclk_1   = 0x00000028,
15 	.dram_cas       = 0x00000028,
16 	.dram_ras       = 0x00000028,
17 	.dram_reset     = 0x00000028,
18 	/* SDCKE[0:1]: 100k pull-up */
19 	.dram_sdcke0    = 0x00003000,
20 	.dram_sdcke1    = 0x00003000,
21 	/* SDBA2: pull-up disabled */
22 	.dram_sdba2	    = 0x00000000,
23 	/* SDODT[0:1]: 100k pull-up, 48 ohm */
24 	.dram_sdodt0    = 0x00000028,
25 	.dram_sdodt1    = 0x00000028,
26 	/* SDQS[0:7]: Differential input, 48 ohm */
27 	.dram_sdqs0     = 0x00000028,
28 	.dram_sdqs1     = 0x00000028,
29 	.dram_sdqs2     = 0x00000028,
30 	.dram_sdqs3     = 0x00000028,
31 	.dram_sdqs4     = 0x00000028,
32 	.dram_sdqs5     = 0x00000028,
33 	.dram_sdqs6     = 0x00000028,
34 	.dram_sdqs7     = 0x00000028,
35 	/* DQM[0:7]: Differential input, 48 ohm */
36 	.dram_dqm0      = 0x00000028,
37 	.dram_dqm1      = 0x00000028,
38 	.dram_dqm2      = 0x00000028,
39 	.dram_dqm3      = 0x00000028,
40 	.dram_dqm4      = 0x00000028,
41 	.dram_dqm5      = 0x00000028,
42 	.dram_dqm6      = 0x00000028,
43 	.dram_dqm7      = 0x00000028,
44 };
45 
46 /* Configure MX6Q/DUAL mmdc GRP io registers */
47 static struct mx6dq_iomux_grp_regs ot1200_grp_ioregs = {
48 	/* DDR3 */
49 	.grp_ddr_type    = 0x000c0000,
50 	.grp_ddrmode_ctl = 0x00020000,
51 	/* Disable DDR pullups */
52 	.grp_ddrpke      = 0x00000000,
53 	/* ADDR[00:16], SDBA[0:1]: 48 ohm */
54 	.grp_addds       = 0x00000028,
55 	/* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 48 ohm */
56 	.grp_ctlds       = 0x00000028,
57 	/* DATA[00:63]: Differential input, 48 ohm */
58 	.grp_ddrmode     = 0x00020000,
59 	.grp_b0ds        = 0x00000028,
60 	.grp_b1ds        = 0x00000028,
61 	.grp_b2ds        = 0x00000028,
62 	.grp_b3ds        = 0x00000028,
63 	.grp_b4ds        = 0x00000028,
64 	.grp_b5ds        = 0x00000028,
65 	.grp_b6ds        = 0x00000028,
66 	.grp_b7ds        = 0x00000028,
67 };
68 
69 static struct mx6_ddr_sysinfo ot1200_ddr_sysinfo = {
70 	/* Width of data bus: 0=16, 1=32, 2=64 */
71 	.dsize      = 2,
72 	/* config for full 4GB range so that get_mem_size() works */
73 	.cs_density = 32, /* 32Gb per CS */
74 	/* Single chip select */
75 	.ncs        = 1,
76 	.cs1_mirror = 0,	/* war 0 */
77 	.rtt_wr     = 1,	/* DDR3_RTT_60_OHM - RTT_Wr = RZQ/4 */
78 	.rtt_nom    = 1,	/* DDR3_RTT_60_OHM - RTT_Nom = RZQ/4 */
79 	.walat      = 1,	/* Write additional latency */
80 	.ralat      = 5,	/* Read additional latency */
81 	.mif3_mode  = 3,	/* Command prediction working mode */
82 	.bi_on      = 1,	/* Bank interleaving enabled */	/* war 1 */
83 	.sde_to_rst = 0x10,	/* 14 cycles, 200us (JEDEC default) */
84 	.rst_to_cke = 0x23,	/* 33 cycles, 500us (JEDEC default) */
85 	.refsel = 1,		/* Refresh cycles at 32KHz */
86 	.refr = 7,		/* 8 refresh commands per refresh cycle */
87 };
88 
89 /* MT41K128M16JT-125 */
90 static struct mx6_ddr3_cfg micron_2gib_1600 = {
91 	.mem_speed = 1600,
92 	.density   = 2,
93 	.width     = 16,
94 	.banks     = 8,
95 	.rowaddr   = 14,
96 	.coladdr   = 10,
97 	.pagesz    = 2,
98 	.trcd      = 1375,
99 	.trcmin    = 4875,
100 	.trasmin   = 3500,
101 	.SRT       = 1,
102 };
103 
104 static struct mx6_mmdc_calibration micron_2gib_1600_mmdc_calib = {
105 	/* write leveling calibration determine */
106 	.p0_mpwldectrl0 = 0x00260025,
107 	.p0_mpwldectrl1 = 0x00270021,
108 	.p1_mpwldectrl0 = 0x00180034,
109 	.p1_mpwldectrl1 = 0x00180024,
110 	/* Read DQS Gating calibration */
111 	.p0_mpdgctrl0   = 0x04380344,
112 	.p0_mpdgctrl1   = 0x0330032C,
113 	.p1_mpdgctrl0   = 0x0338033C,
114 	.p1_mpdgctrl1   = 0x032C0300,
115 	/* Read Calibration: DQS delay relative to DQ read access */
116 	.p0_mprddlctl   = 0x3C2E3238,
117 	.p1_mprddlctl   = 0x3A2E303C,
118 	/* Write Calibration: DQ/DM delay relative to DQS write access */
119 	.p0_mpwrdlctl   = 0x36384036,
120 	.p1_mpwrdlctl   = 0x442E4438,
121 };
122 
ot1200_spl_dram_init(void)123 static void ot1200_spl_dram_init(void)
124 {
125 	mx6dq_dram_iocfg(64, &ot1200_ddr_ioregs, &ot1200_grp_ioregs);
126 	mx6_dram_cfg(&ot1200_ddr_sysinfo, &micron_2gib_1600_mmdc_calib,
127 		     &micron_2gib_1600);
128 }
129 
130 /*
131  * called from C runtime startup code (arch/arm/lib/crt0.S:_main)
132  * - we have a stack and a place to store GD, both in SRAM
133  * - no variable global data is available
134  */
board_init_f(ulong dummy)135 void board_init_f(ulong dummy)
136 {
137 	/* setup AIPS and disable watchdog */
138 	arch_cpu_init();
139 
140 	/* iomux and setup of i2c */
141 	board_early_init_f();
142 
143 	/* setup GP timer */
144 	timer_init();
145 
146 	/* UART clocks enabled and gd valid - init serial console */
147 	preloader_console_init();
148 
149 	/* configure MMDC for SDRAM width/size and per-model calibration */
150 	ot1200_spl_dram_init();
151 }
152