1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
4 *
5 */
6
7 #include <linux/delay.h>
8 #include <linux/device.h>
9 #include <linux/dma-direction.h>
10 #include <linux/dma-mapping.h>
11 #include <linux/interrupt.h>
12 #include <linux/list.h>
13 #include <linux/mhi.h>
14 #include <linux/module.h>
15 #include <linux/slab.h>
16 #include <linux/wait.h>
17 #include "internal.h"
18
19 /*
20 * Not all MHI state transitions are synchronous. Transitions like Linkdown,
21 * SYS_ERR, and shutdown can happen anytime asynchronously. This function will
22 * transition to a new state only if we're allowed to.
23 *
24 * Priority increases as we go down. For instance, from any state in L0, the
25 * transition can be made to states in L1, L2 and L3. A notable exception to
26 * this rule is state DISABLE. From DISABLE state we can only transition to
27 * POR state. Also, while in L2 state, user cannot jump back to previous
28 * L1 or L0 states.
29 *
30 * Valid transitions:
31 * L0: DISABLE <--> POR
32 * POR <--> POR
33 * POR -> M0 -> M2 --> M0
34 * POR -> FW_DL_ERR
35 * FW_DL_ERR <--> FW_DL_ERR
36 * M0 <--> M0
37 * M0 -> FW_DL_ERR
38 * M0 -> M3_ENTER -> M3 -> M3_EXIT --> M0
39 * L1: SYS_ERR_DETECT -> SYS_ERR_PROCESS
40 * SYS_ERR_PROCESS -> SYS_ERR_FAIL
41 * SYS_ERR_FAIL -> SYS_ERR_DETECT
42 * SYS_ERR_PROCESS --> POR
43 * L2: SHUTDOWN_PROCESS -> LD_ERR_FATAL_DETECT
44 * SHUTDOWN_PROCESS -> DISABLE
45 * L3: LD_ERR_FATAL_DETECT <--> LD_ERR_FATAL_DETECT
46 * LD_ERR_FATAL_DETECT -> DISABLE
47 */
48 static const struct mhi_pm_transitions dev_state_transitions[] = {
49 /* L0 States */
50 {
51 MHI_PM_DISABLE,
52 MHI_PM_POR
53 },
54 {
55 MHI_PM_POR,
56 MHI_PM_POR | MHI_PM_DISABLE | MHI_PM_M0 |
57 MHI_PM_SYS_ERR_DETECT | MHI_PM_SHUTDOWN_PROCESS |
58 MHI_PM_LD_ERR_FATAL_DETECT | MHI_PM_FW_DL_ERR
59 },
60 {
61 MHI_PM_M0,
62 MHI_PM_M0 | MHI_PM_M2 | MHI_PM_M3_ENTER |
63 MHI_PM_SYS_ERR_DETECT | MHI_PM_SHUTDOWN_PROCESS |
64 MHI_PM_LD_ERR_FATAL_DETECT | MHI_PM_FW_DL_ERR
65 },
66 {
67 MHI_PM_M2,
68 MHI_PM_M0 | MHI_PM_SYS_ERR_DETECT | MHI_PM_SHUTDOWN_PROCESS |
69 MHI_PM_LD_ERR_FATAL_DETECT
70 },
71 {
72 MHI_PM_M3_ENTER,
73 MHI_PM_M3 | MHI_PM_SYS_ERR_DETECT | MHI_PM_SHUTDOWN_PROCESS |
74 MHI_PM_LD_ERR_FATAL_DETECT
75 },
76 {
77 MHI_PM_M3,
78 MHI_PM_M3_EXIT | MHI_PM_SYS_ERR_DETECT |
79 MHI_PM_LD_ERR_FATAL_DETECT
80 },
81 {
82 MHI_PM_M3_EXIT,
83 MHI_PM_M0 | MHI_PM_SYS_ERR_DETECT | MHI_PM_SHUTDOWN_PROCESS |
84 MHI_PM_LD_ERR_FATAL_DETECT
85 },
86 {
87 MHI_PM_FW_DL_ERR,
88 MHI_PM_FW_DL_ERR | MHI_PM_SYS_ERR_DETECT |
89 MHI_PM_SHUTDOWN_PROCESS | MHI_PM_LD_ERR_FATAL_DETECT
90 },
91 /* L1 States */
92 {
93 MHI_PM_SYS_ERR_DETECT,
94 MHI_PM_SYS_ERR_PROCESS | MHI_PM_SHUTDOWN_PROCESS |
95 MHI_PM_LD_ERR_FATAL_DETECT
96 },
97 {
98 MHI_PM_SYS_ERR_PROCESS,
99 MHI_PM_POR | MHI_PM_SYS_ERR_FAIL | MHI_PM_SHUTDOWN_PROCESS |
100 MHI_PM_LD_ERR_FATAL_DETECT
101 },
102 {
103 MHI_PM_SYS_ERR_FAIL,
104 MHI_PM_SYS_ERR_DETECT | MHI_PM_SHUTDOWN_PROCESS |
105 MHI_PM_LD_ERR_FATAL_DETECT
106 },
107 /* L2 States */
108 {
109 MHI_PM_SHUTDOWN_PROCESS,
110 MHI_PM_DISABLE | MHI_PM_LD_ERR_FATAL_DETECT
111 },
112 /* L3 States */
113 {
114 MHI_PM_LD_ERR_FATAL_DETECT,
115 MHI_PM_LD_ERR_FATAL_DETECT | MHI_PM_DISABLE
116 },
117 };
118
mhi_tryset_pm_state(struct mhi_controller * mhi_cntrl,enum mhi_pm_state state)119 enum mhi_pm_state __must_check mhi_tryset_pm_state(struct mhi_controller *mhi_cntrl,
120 enum mhi_pm_state state)
121 {
122 unsigned long cur_state = mhi_cntrl->pm_state;
123 int index = find_last_bit(&cur_state, 32);
124
125 if (unlikely(index >= ARRAY_SIZE(dev_state_transitions)))
126 return cur_state;
127
128 if (unlikely(dev_state_transitions[index].from_state != cur_state))
129 return cur_state;
130
131 if (unlikely(!(dev_state_transitions[index].to_states & state)))
132 return cur_state;
133
134 mhi_cntrl->pm_state = state;
135 return mhi_cntrl->pm_state;
136 }
137
mhi_set_mhi_state(struct mhi_controller * mhi_cntrl,enum mhi_state state)138 void mhi_set_mhi_state(struct mhi_controller *mhi_cntrl, enum mhi_state state)
139 {
140 struct device *dev = &mhi_cntrl->mhi_dev->dev;
141 int ret;
142
143 if (state == MHI_STATE_RESET) {
144 ret = mhi_write_reg_field(mhi_cntrl, mhi_cntrl->regs, MHICTRL,
145 MHICTRL_RESET_MASK, 1);
146 } else {
147 ret = mhi_write_reg_field(mhi_cntrl, mhi_cntrl->regs, MHICTRL,
148 MHICTRL_MHISTATE_MASK, state);
149 }
150
151 if (ret)
152 dev_err(dev, "Failed to set MHI state to: %s\n",
153 mhi_state_str(state));
154 }
155
156 /* NOP for backward compatibility, host allowed to ring DB in M2 state */
mhi_toggle_dev_wake_nop(struct mhi_controller * mhi_cntrl)157 static void mhi_toggle_dev_wake_nop(struct mhi_controller *mhi_cntrl)
158 {
159 }
160
mhi_toggle_dev_wake(struct mhi_controller * mhi_cntrl)161 static void mhi_toggle_dev_wake(struct mhi_controller *mhi_cntrl)
162 {
163 mhi_cntrl->wake_get(mhi_cntrl, false);
164 mhi_cntrl->wake_put(mhi_cntrl, true);
165 }
166
167 /* Handle device ready state transition */
mhi_ready_state_transition(struct mhi_controller * mhi_cntrl)168 int mhi_ready_state_transition(struct mhi_controller *mhi_cntrl)
169 {
170 struct mhi_event *mhi_event;
171 enum mhi_pm_state cur_state;
172 struct device *dev = &mhi_cntrl->mhi_dev->dev;
173 u32 interval_us = 25000; /* poll register field every 25 milliseconds */
174 int ret, i;
175
176 /* Check if device entered error state */
177 if (MHI_PM_IN_FATAL_STATE(mhi_cntrl->pm_state)) {
178 dev_err(dev, "Device link is not accessible\n");
179 return -EIO;
180 }
181
182 /* Wait for RESET to be cleared and READY bit to be set by the device */
183 ret = mhi_poll_reg_field(mhi_cntrl, mhi_cntrl->regs, MHICTRL,
184 MHICTRL_RESET_MASK, 0, interval_us);
185 if (ret) {
186 dev_err(dev, "Device failed to clear MHI Reset\n");
187 return ret;
188 }
189
190 ret = mhi_poll_reg_field(mhi_cntrl, mhi_cntrl->regs, MHISTATUS,
191 MHISTATUS_READY_MASK, 1, interval_us);
192 if (ret) {
193 dev_err(dev, "Device failed to enter MHI Ready\n");
194 return ret;
195 }
196
197 dev_dbg(dev, "Device in READY State\n");
198 write_lock_irq(&mhi_cntrl->pm_lock);
199 cur_state = mhi_tryset_pm_state(mhi_cntrl, MHI_PM_POR);
200 mhi_cntrl->dev_state = MHI_STATE_READY;
201 write_unlock_irq(&mhi_cntrl->pm_lock);
202
203 if (cur_state != MHI_PM_POR) {
204 dev_err(dev, "Error moving to state %s from %s\n",
205 to_mhi_pm_state_str(MHI_PM_POR),
206 to_mhi_pm_state_str(cur_state));
207 return -EIO;
208 }
209
210 read_lock_bh(&mhi_cntrl->pm_lock);
211 if (!MHI_REG_ACCESS_VALID(mhi_cntrl->pm_state)) {
212 dev_err(dev, "Device registers not accessible\n");
213 goto error_mmio;
214 }
215
216 /* Configure MMIO registers */
217 ret = mhi_init_mmio(mhi_cntrl);
218 if (ret) {
219 dev_err(dev, "Error configuring MMIO registers\n");
220 goto error_mmio;
221 }
222
223 /* Add elements to all SW event rings */
224 mhi_event = mhi_cntrl->mhi_event;
225 for (i = 0; i < mhi_cntrl->total_ev_rings; i++, mhi_event++) {
226 struct mhi_ring *ring = &mhi_event->ring;
227
228 /* Skip if this is an offload or HW event */
229 if (mhi_event->offload_ev || mhi_event->hw_ring)
230 continue;
231
232 ring->wp = ring->base + ring->len - ring->el_size;
233 *ring->ctxt_wp = cpu_to_le64(ring->iommu_base + ring->len - ring->el_size);
234 /* Update all cores */
235 smp_wmb();
236
237 /* Ring the event ring db */
238 spin_lock_irq(&mhi_event->lock);
239 mhi_ring_er_db(mhi_event);
240 spin_unlock_irq(&mhi_event->lock);
241 }
242
243 /* Set MHI to M0 state */
244 mhi_set_mhi_state(mhi_cntrl, MHI_STATE_M0);
245 read_unlock_bh(&mhi_cntrl->pm_lock);
246
247 return 0;
248
249 error_mmio:
250 read_unlock_bh(&mhi_cntrl->pm_lock);
251
252 return -EIO;
253 }
254
mhi_pm_m0_transition(struct mhi_controller * mhi_cntrl)255 int mhi_pm_m0_transition(struct mhi_controller *mhi_cntrl)
256 {
257 enum mhi_pm_state cur_state;
258 struct mhi_chan *mhi_chan;
259 struct device *dev = &mhi_cntrl->mhi_dev->dev;
260 int i;
261
262 write_lock_irq(&mhi_cntrl->pm_lock);
263 mhi_cntrl->dev_state = MHI_STATE_M0;
264 cur_state = mhi_tryset_pm_state(mhi_cntrl, MHI_PM_M0);
265 write_unlock_irq(&mhi_cntrl->pm_lock);
266 if (unlikely(cur_state != MHI_PM_M0)) {
267 dev_err(dev, "Unable to transition to M0 state\n");
268 return -EIO;
269 }
270 mhi_cntrl->M0++;
271
272 /* Wake up the device */
273 read_lock_bh(&mhi_cntrl->pm_lock);
274 mhi_cntrl->wake_get(mhi_cntrl, true);
275
276 /* Ring all event rings and CMD ring only if we're in mission mode */
277 if (MHI_IN_MISSION_MODE(mhi_cntrl->ee)) {
278 struct mhi_event *mhi_event = mhi_cntrl->mhi_event;
279 struct mhi_cmd *mhi_cmd =
280 &mhi_cntrl->mhi_cmd[PRIMARY_CMD_RING];
281
282 for (i = 0; i < mhi_cntrl->total_ev_rings; i++, mhi_event++) {
283 if (mhi_event->offload_ev)
284 continue;
285
286 spin_lock_irq(&mhi_event->lock);
287 mhi_ring_er_db(mhi_event);
288 spin_unlock_irq(&mhi_event->lock);
289 }
290
291 /* Only ring primary cmd ring if ring is not empty */
292 spin_lock_irq(&mhi_cmd->lock);
293 if (mhi_cmd->ring.rp != mhi_cmd->ring.wp)
294 mhi_ring_cmd_db(mhi_cntrl, mhi_cmd);
295 spin_unlock_irq(&mhi_cmd->lock);
296 }
297
298 /* Ring channel DB registers */
299 mhi_chan = mhi_cntrl->mhi_chan;
300 for (i = 0; i < mhi_cntrl->max_chan; i++, mhi_chan++) {
301 struct mhi_ring *tre_ring = &mhi_chan->tre_ring;
302
303 if (mhi_chan->db_cfg.reset_req) {
304 write_lock_irq(&mhi_chan->lock);
305 mhi_chan->db_cfg.db_mode = true;
306 write_unlock_irq(&mhi_chan->lock);
307 }
308
309 read_lock_irq(&mhi_chan->lock);
310
311 /* Only ring DB if ring is not empty */
312 if (tre_ring->base && tre_ring->wp != tre_ring->rp &&
313 mhi_chan->ch_state == MHI_CH_STATE_ENABLED)
314 mhi_ring_chan_db(mhi_cntrl, mhi_chan);
315 read_unlock_irq(&mhi_chan->lock);
316 }
317
318 mhi_cntrl->wake_put(mhi_cntrl, false);
319 read_unlock_bh(&mhi_cntrl->pm_lock);
320 wake_up_all(&mhi_cntrl->state_event);
321
322 return 0;
323 }
324
325 /*
326 * After receiving the MHI state change event from the device indicating the
327 * transition to M1 state, the host can transition the device to M2 state
328 * for keeping it in low power state.
329 */
mhi_pm_m1_transition(struct mhi_controller * mhi_cntrl)330 void mhi_pm_m1_transition(struct mhi_controller *mhi_cntrl)
331 {
332 enum mhi_pm_state state;
333 struct device *dev = &mhi_cntrl->mhi_dev->dev;
334
335 write_lock_irq(&mhi_cntrl->pm_lock);
336 state = mhi_tryset_pm_state(mhi_cntrl, MHI_PM_M2);
337 if (state == MHI_PM_M2) {
338 mhi_set_mhi_state(mhi_cntrl, MHI_STATE_M2);
339 mhi_cntrl->dev_state = MHI_STATE_M2;
340
341 write_unlock_irq(&mhi_cntrl->pm_lock);
342
343 mhi_cntrl->M2++;
344 wake_up_all(&mhi_cntrl->state_event);
345
346 /* If there are any pending resources, exit M2 immediately */
347 if (unlikely(atomic_read(&mhi_cntrl->pending_pkts) ||
348 atomic_read(&mhi_cntrl->dev_wake))) {
349 dev_dbg(dev,
350 "Exiting M2, pending_pkts: %d dev_wake: %d\n",
351 atomic_read(&mhi_cntrl->pending_pkts),
352 atomic_read(&mhi_cntrl->dev_wake));
353 read_lock_bh(&mhi_cntrl->pm_lock);
354 mhi_cntrl->wake_get(mhi_cntrl, true);
355 mhi_cntrl->wake_put(mhi_cntrl, true);
356 read_unlock_bh(&mhi_cntrl->pm_lock);
357 } else {
358 mhi_cntrl->status_cb(mhi_cntrl, MHI_CB_IDLE);
359 }
360 } else {
361 write_unlock_irq(&mhi_cntrl->pm_lock);
362 }
363 }
364
365 /* MHI M3 completion handler */
mhi_pm_m3_transition(struct mhi_controller * mhi_cntrl)366 int mhi_pm_m3_transition(struct mhi_controller *mhi_cntrl)
367 {
368 enum mhi_pm_state state;
369 struct device *dev = &mhi_cntrl->mhi_dev->dev;
370
371 write_lock_irq(&mhi_cntrl->pm_lock);
372 mhi_cntrl->dev_state = MHI_STATE_M3;
373 state = mhi_tryset_pm_state(mhi_cntrl, MHI_PM_M3);
374 write_unlock_irq(&mhi_cntrl->pm_lock);
375 if (state != MHI_PM_M3) {
376 dev_err(dev, "Unable to transition to M3 state\n");
377 return -EIO;
378 }
379
380 mhi_cntrl->M3++;
381 wake_up_all(&mhi_cntrl->state_event);
382
383 return 0;
384 }
385
386 /* Handle device Mission Mode transition */
mhi_pm_mission_mode_transition(struct mhi_controller * mhi_cntrl)387 static int mhi_pm_mission_mode_transition(struct mhi_controller *mhi_cntrl)
388 {
389 struct mhi_event *mhi_event;
390 struct device *dev = &mhi_cntrl->mhi_dev->dev;
391 enum mhi_ee_type ee = MHI_EE_MAX, current_ee = mhi_cntrl->ee;
392 int i, ret;
393
394 dev_dbg(dev, "Processing Mission Mode transition\n");
395
396 write_lock_irq(&mhi_cntrl->pm_lock);
397 if (MHI_REG_ACCESS_VALID(mhi_cntrl->pm_state))
398 ee = mhi_get_exec_env(mhi_cntrl);
399
400 if (!MHI_IN_MISSION_MODE(ee)) {
401 mhi_cntrl->pm_state = MHI_PM_LD_ERR_FATAL_DETECT;
402 write_unlock_irq(&mhi_cntrl->pm_lock);
403 wake_up_all(&mhi_cntrl->state_event);
404 return -EIO;
405 }
406 mhi_cntrl->ee = ee;
407 write_unlock_irq(&mhi_cntrl->pm_lock);
408
409 wake_up_all(&mhi_cntrl->state_event);
410
411 device_for_each_child(&mhi_cntrl->mhi_dev->dev, ¤t_ee,
412 mhi_destroy_device);
413 mhi_cntrl->status_cb(mhi_cntrl, MHI_CB_EE_MISSION_MODE);
414
415 /* Force MHI to be in M0 state before continuing */
416 ret = __mhi_device_get_sync(mhi_cntrl);
417 if (ret)
418 return ret;
419
420 read_lock_bh(&mhi_cntrl->pm_lock);
421
422 if (MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state)) {
423 ret = -EIO;
424 goto error_mission_mode;
425 }
426
427 /* Add elements to all HW event rings */
428 mhi_event = mhi_cntrl->mhi_event;
429 for (i = 0; i < mhi_cntrl->total_ev_rings; i++, mhi_event++) {
430 struct mhi_ring *ring = &mhi_event->ring;
431
432 if (mhi_event->offload_ev || !mhi_event->hw_ring)
433 continue;
434
435 ring->wp = ring->base + ring->len - ring->el_size;
436 *ring->ctxt_wp = cpu_to_le64(ring->iommu_base + ring->len - ring->el_size);
437 /* Update to all cores */
438 smp_wmb();
439
440 spin_lock_irq(&mhi_event->lock);
441 if (MHI_DB_ACCESS_VALID(mhi_cntrl))
442 mhi_ring_er_db(mhi_event);
443 spin_unlock_irq(&mhi_event->lock);
444 }
445
446 read_unlock_bh(&mhi_cntrl->pm_lock);
447
448 /*
449 * The MHI devices are only created when the client device switches its
450 * Execution Environment (EE) to either SBL or AMSS states
451 */
452 mhi_create_devices(mhi_cntrl);
453
454 read_lock_bh(&mhi_cntrl->pm_lock);
455
456 error_mission_mode:
457 mhi_cntrl->wake_put(mhi_cntrl, false);
458 read_unlock_bh(&mhi_cntrl->pm_lock);
459
460 return ret;
461 }
462
463 /* Handle shutdown transitions */
mhi_pm_disable_transition(struct mhi_controller * mhi_cntrl)464 static void mhi_pm_disable_transition(struct mhi_controller *mhi_cntrl)
465 {
466 enum mhi_pm_state cur_state;
467 struct mhi_event *mhi_event;
468 struct mhi_cmd_ctxt *cmd_ctxt;
469 struct mhi_cmd *mhi_cmd;
470 struct mhi_event_ctxt *er_ctxt;
471 struct device *dev = &mhi_cntrl->mhi_dev->dev;
472 int ret, i;
473
474 dev_dbg(dev, "Processing disable transition with PM state: %s\n",
475 to_mhi_pm_state_str(mhi_cntrl->pm_state));
476
477 mutex_lock(&mhi_cntrl->pm_mutex);
478
479 /* Trigger MHI RESET so that the device will not access host memory */
480 if (!MHI_PM_IN_FATAL_STATE(mhi_cntrl->pm_state)) {
481 /* Skip MHI RESET if in RDDM state */
482 if (mhi_cntrl->rddm_image && mhi_get_exec_env(mhi_cntrl) == MHI_EE_RDDM)
483 goto skip_mhi_reset;
484
485 dev_dbg(dev, "Triggering MHI Reset in device\n");
486 mhi_set_mhi_state(mhi_cntrl, MHI_STATE_RESET);
487
488 /* Wait for the reset bit to be cleared by the device */
489 ret = mhi_poll_reg_field(mhi_cntrl, mhi_cntrl->regs, MHICTRL,
490 MHICTRL_RESET_MASK, 0, 25000);
491 if (ret)
492 dev_err(dev, "Device failed to clear MHI Reset\n");
493
494 /*
495 * Device will clear BHI_INTVEC as a part of RESET processing,
496 * hence re-program it
497 */
498 mhi_write_reg(mhi_cntrl, mhi_cntrl->bhi, BHI_INTVEC, 0);
499
500 if (!MHI_IN_PBL(mhi_get_exec_env(mhi_cntrl))) {
501 /* wait for ready to be set */
502 ret = mhi_poll_reg_field(mhi_cntrl, mhi_cntrl->regs,
503 MHISTATUS,
504 MHISTATUS_READY_MASK, 1, 25000);
505 if (ret)
506 dev_err(dev, "Device failed to enter READY state\n");
507 }
508 }
509
510 skip_mhi_reset:
511 dev_dbg(dev,
512 "Waiting for all pending event ring processing to complete\n");
513 mhi_event = mhi_cntrl->mhi_event;
514 for (i = 0; i < mhi_cntrl->total_ev_rings; i++, mhi_event++) {
515 if (mhi_event->offload_ev)
516 continue;
517 disable_irq(mhi_cntrl->irq[mhi_event->irq]);
518 tasklet_kill(&mhi_event->task);
519 }
520
521 /* Release lock and wait for all pending threads to complete */
522 mutex_unlock(&mhi_cntrl->pm_mutex);
523 dev_dbg(dev, "Waiting for all pending threads to complete\n");
524 wake_up_all(&mhi_cntrl->state_event);
525
526 dev_dbg(dev, "Reset all active channels and remove MHI devices\n");
527 device_for_each_child(&mhi_cntrl->mhi_dev->dev, NULL, mhi_destroy_device);
528
529 mutex_lock(&mhi_cntrl->pm_mutex);
530
531 WARN_ON(atomic_read(&mhi_cntrl->dev_wake));
532 WARN_ON(atomic_read(&mhi_cntrl->pending_pkts));
533
534 /* Reset the ev rings and cmd rings */
535 dev_dbg(dev, "Resetting EV CTXT and CMD CTXT\n");
536 mhi_cmd = mhi_cntrl->mhi_cmd;
537 cmd_ctxt = mhi_cntrl->mhi_ctxt->cmd_ctxt;
538 for (i = 0; i < NR_OF_CMD_RINGS; i++, mhi_cmd++, cmd_ctxt++) {
539 struct mhi_ring *ring = &mhi_cmd->ring;
540
541 ring->rp = ring->base;
542 ring->wp = ring->base;
543 cmd_ctxt->rp = cmd_ctxt->rbase;
544 cmd_ctxt->wp = cmd_ctxt->rbase;
545 }
546
547 mhi_event = mhi_cntrl->mhi_event;
548 er_ctxt = mhi_cntrl->mhi_ctxt->er_ctxt;
549 for (i = 0; i < mhi_cntrl->total_ev_rings; i++, er_ctxt++,
550 mhi_event++) {
551 struct mhi_ring *ring = &mhi_event->ring;
552
553 /* Skip offload events */
554 if (mhi_event->offload_ev)
555 continue;
556
557 ring->rp = ring->base;
558 ring->wp = ring->base;
559 er_ctxt->rp = er_ctxt->rbase;
560 er_ctxt->wp = er_ctxt->rbase;
561 }
562
563 /* Move to disable state */
564 write_lock_irq(&mhi_cntrl->pm_lock);
565 cur_state = mhi_tryset_pm_state(mhi_cntrl, MHI_PM_DISABLE);
566 write_unlock_irq(&mhi_cntrl->pm_lock);
567 if (unlikely(cur_state != MHI_PM_DISABLE))
568 dev_err(dev, "Error moving from PM state: %s to: %s\n",
569 to_mhi_pm_state_str(cur_state),
570 to_mhi_pm_state_str(MHI_PM_DISABLE));
571
572 dev_dbg(dev, "Exiting with PM state: %s, MHI state: %s\n",
573 to_mhi_pm_state_str(mhi_cntrl->pm_state),
574 mhi_state_str(mhi_cntrl->dev_state));
575
576 mutex_unlock(&mhi_cntrl->pm_mutex);
577 }
578
579 /* Handle system error transitions */
mhi_pm_sys_error_transition(struct mhi_controller * mhi_cntrl)580 static void mhi_pm_sys_error_transition(struct mhi_controller *mhi_cntrl)
581 {
582 enum mhi_pm_state cur_state, prev_state;
583 enum dev_st_transition next_state;
584 struct mhi_event *mhi_event;
585 struct mhi_cmd_ctxt *cmd_ctxt;
586 struct mhi_cmd *mhi_cmd;
587 struct mhi_event_ctxt *er_ctxt;
588 struct device *dev = &mhi_cntrl->mhi_dev->dev;
589 bool reset_device = false;
590 int ret, i;
591
592 dev_dbg(dev, "Transitioning from PM state: %s to: %s\n",
593 to_mhi_pm_state_str(mhi_cntrl->pm_state),
594 to_mhi_pm_state_str(MHI_PM_SYS_ERR_PROCESS));
595
596 /* We must notify MHI control driver so it can clean up first */
597 mhi_cntrl->status_cb(mhi_cntrl, MHI_CB_SYS_ERROR);
598
599 mutex_lock(&mhi_cntrl->pm_mutex);
600 write_lock_irq(&mhi_cntrl->pm_lock);
601 prev_state = mhi_cntrl->pm_state;
602 cur_state = mhi_tryset_pm_state(mhi_cntrl, MHI_PM_SYS_ERR_PROCESS);
603 write_unlock_irq(&mhi_cntrl->pm_lock);
604
605 if (cur_state != MHI_PM_SYS_ERR_PROCESS) {
606 dev_err(dev, "Failed to transition from PM state: %s to: %s\n",
607 to_mhi_pm_state_str(cur_state),
608 to_mhi_pm_state_str(MHI_PM_SYS_ERR_PROCESS));
609 goto exit_sys_error_transition;
610 }
611
612 mhi_cntrl->ee = MHI_EE_DISABLE_TRANSITION;
613 mhi_cntrl->dev_state = MHI_STATE_RESET;
614
615 /* Wake up threads waiting for state transition */
616 wake_up_all(&mhi_cntrl->state_event);
617
618 if (MHI_REG_ACCESS_VALID(prev_state)) {
619 /*
620 * If the device is in PBL or SBL, it will only respond to
621 * RESET if the device is in SYSERR state. SYSERR might
622 * already be cleared at this point.
623 */
624 enum mhi_state cur_state = mhi_get_mhi_state(mhi_cntrl);
625 enum mhi_ee_type cur_ee = mhi_get_exec_env(mhi_cntrl);
626
627 if (cur_state == MHI_STATE_SYS_ERR)
628 reset_device = true;
629 else if (cur_ee != MHI_EE_PBL && cur_ee != MHI_EE_SBL)
630 reset_device = true;
631 }
632
633 /* Trigger MHI RESET so that the device will not access host memory */
634 if (reset_device) {
635 u32 in_reset = -1;
636 unsigned long timeout = msecs_to_jiffies(mhi_cntrl->timeout_ms);
637
638 dev_dbg(dev, "Triggering MHI Reset in device\n");
639 mhi_set_mhi_state(mhi_cntrl, MHI_STATE_RESET);
640
641 /* Wait for the reset bit to be cleared by the device */
642 ret = wait_event_timeout(mhi_cntrl->state_event,
643 mhi_read_reg_field(mhi_cntrl,
644 mhi_cntrl->regs,
645 MHICTRL,
646 MHICTRL_RESET_MASK,
647 &in_reset) ||
648 !in_reset, timeout);
649 if (!ret || in_reset) {
650 dev_err(dev, "Device failed to exit MHI Reset state\n");
651 write_lock_irq(&mhi_cntrl->pm_lock);
652 cur_state = mhi_tryset_pm_state(mhi_cntrl,
653 MHI_PM_SYS_ERR_FAIL);
654 write_unlock_irq(&mhi_cntrl->pm_lock);
655 /* Shutdown may have occurred, otherwise cleanup now */
656 if (cur_state != MHI_PM_SYS_ERR_FAIL)
657 goto exit_sys_error_transition;
658 }
659
660 /*
661 * Device will clear BHI_INTVEC as a part of RESET processing,
662 * hence re-program it
663 */
664 mhi_write_reg(mhi_cntrl, mhi_cntrl->bhi, BHI_INTVEC, 0);
665 }
666
667 dev_dbg(dev,
668 "Waiting for all pending event ring processing to complete\n");
669 mhi_event = mhi_cntrl->mhi_event;
670 for (i = 0; i < mhi_cntrl->total_ev_rings; i++, mhi_event++) {
671 if (mhi_event->offload_ev)
672 continue;
673 tasklet_kill(&mhi_event->task);
674 }
675
676 /* Release lock and wait for all pending threads to complete */
677 mutex_unlock(&mhi_cntrl->pm_mutex);
678 dev_dbg(dev, "Waiting for all pending threads to complete\n");
679 wake_up_all(&mhi_cntrl->state_event);
680
681 dev_dbg(dev, "Reset all active channels and remove MHI devices\n");
682 device_for_each_child(&mhi_cntrl->mhi_dev->dev, NULL, mhi_destroy_device);
683
684 mutex_lock(&mhi_cntrl->pm_mutex);
685
686 WARN_ON(atomic_read(&mhi_cntrl->dev_wake));
687 WARN_ON(atomic_read(&mhi_cntrl->pending_pkts));
688
689 /* Reset the ev rings and cmd rings */
690 dev_dbg(dev, "Resetting EV CTXT and CMD CTXT\n");
691 mhi_cmd = mhi_cntrl->mhi_cmd;
692 cmd_ctxt = mhi_cntrl->mhi_ctxt->cmd_ctxt;
693 for (i = 0; i < NR_OF_CMD_RINGS; i++, mhi_cmd++, cmd_ctxt++) {
694 struct mhi_ring *ring = &mhi_cmd->ring;
695
696 ring->rp = ring->base;
697 ring->wp = ring->base;
698 cmd_ctxt->rp = cmd_ctxt->rbase;
699 cmd_ctxt->wp = cmd_ctxt->rbase;
700 }
701
702 mhi_event = mhi_cntrl->mhi_event;
703 er_ctxt = mhi_cntrl->mhi_ctxt->er_ctxt;
704 for (i = 0; i < mhi_cntrl->total_ev_rings; i++, er_ctxt++,
705 mhi_event++) {
706 struct mhi_ring *ring = &mhi_event->ring;
707
708 /* Skip offload events */
709 if (mhi_event->offload_ev)
710 continue;
711
712 ring->rp = ring->base;
713 ring->wp = ring->base;
714 er_ctxt->rp = er_ctxt->rbase;
715 er_ctxt->wp = er_ctxt->rbase;
716 }
717
718 /* Transition to next state */
719 if (MHI_IN_PBL(mhi_get_exec_env(mhi_cntrl))) {
720 write_lock_irq(&mhi_cntrl->pm_lock);
721 cur_state = mhi_tryset_pm_state(mhi_cntrl, MHI_PM_POR);
722 write_unlock_irq(&mhi_cntrl->pm_lock);
723 if (cur_state != MHI_PM_POR) {
724 dev_err(dev, "Error moving to state %s from %s\n",
725 to_mhi_pm_state_str(MHI_PM_POR),
726 to_mhi_pm_state_str(cur_state));
727 goto exit_sys_error_transition;
728 }
729 next_state = DEV_ST_TRANSITION_PBL;
730 } else {
731 next_state = DEV_ST_TRANSITION_READY;
732 }
733
734 mhi_queue_state_transition(mhi_cntrl, next_state);
735
736 exit_sys_error_transition:
737 dev_dbg(dev, "Exiting with PM state: %s, MHI state: %s\n",
738 to_mhi_pm_state_str(mhi_cntrl->pm_state),
739 mhi_state_str(mhi_cntrl->dev_state));
740
741 mutex_unlock(&mhi_cntrl->pm_mutex);
742 }
743
744 /* Queue a new work item and schedule work */
mhi_queue_state_transition(struct mhi_controller * mhi_cntrl,enum dev_st_transition state)745 int mhi_queue_state_transition(struct mhi_controller *mhi_cntrl,
746 enum dev_st_transition state)
747 {
748 struct state_transition *item = kmalloc(sizeof(*item), GFP_ATOMIC);
749 unsigned long flags;
750
751 if (!item)
752 return -ENOMEM;
753
754 item->state = state;
755 spin_lock_irqsave(&mhi_cntrl->transition_lock, flags);
756 list_add_tail(&item->node, &mhi_cntrl->transition_list);
757 spin_unlock_irqrestore(&mhi_cntrl->transition_lock, flags);
758
759 queue_work(mhi_cntrl->hiprio_wq, &mhi_cntrl->st_worker);
760
761 return 0;
762 }
763
764 /* SYS_ERR worker */
mhi_pm_sys_err_handler(struct mhi_controller * mhi_cntrl)765 void mhi_pm_sys_err_handler(struct mhi_controller *mhi_cntrl)
766 {
767 struct device *dev = &mhi_cntrl->mhi_dev->dev;
768
769 /* skip if controller supports RDDM */
770 if (mhi_cntrl->rddm_image) {
771 dev_dbg(dev, "Controller supports RDDM, skip SYS_ERROR\n");
772 return;
773 }
774
775 mhi_queue_state_transition(mhi_cntrl, DEV_ST_TRANSITION_SYS_ERR);
776 }
777
778 /* Device State Transition worker */
mhi_pm_st_worker(struct work_struct * work)779 void mhi_pm_st_worker(struct work_struct *work)
780 {
781 struct state_transition *itr, *tmp;
782 LIST_HEAD(head);
783 struct mhi_controller *mhi_cntrl = container_of(work,
784 struct mhi_controller,
785 st_worker);
786 struct device *dev = &mhi_cntrl->mhi_dev->dev;
787
788 spin_lock_irq(&mhi_cntrl->transition_lock);
789 list_splice_tail_init(&mhi_cntrl->transition_list, &head);
790 spin_unlock_irq(&mhi_cntrl->transition_lock);
791
792 list_for_each_entry_safe(itr, tmp, &head, node) {
793 list_del(&itr->node);
794 dev_dbg(dev, "Handling state transition: %s\n",
795 TO_DEV_STATE_TRANS_STR(itr->state));
796
797 switch (itr->state) {
798 case DEV_ST_TRANSITION_PBL:
799 write_lock_irq(&mhi_cntrl->pm_lock);
800 if (MHI_REG_ACCESS_VALID(mhi_cntrl->pm_state))
801 mhi_cntrl->ee = mhi_get_exec_env(mhi_cntrl);
802 write_unlock_irq(&mhi_cntrl->pm_lock);
803 mhi_fw_load_handler(mhi_cntrl);
804 break;
805 case DEV_ST_TRANSITION_SBL:
806 write_lock_irq(&mhi_cntrl->pm_lock);
807 mhi_cntrl->ee = MHI_EE_SBL;
808 write_unlock_irq(&mhi_cntrl->pm_lock);
809 /*
810 * The MHI devices are only created when the client
811 * device switches its Execution Environment (EE) to
812 * either SBL or AMSS states
813 */
814 mhi_create_devices(mhi_cntrl);
815 if (mhi_cntrl->fbc_download)
816 mhi_download_amss_image(mhi_cntrl);
817 break;
818 case DEV_ST_TRANSITION_MISSION_MODE:
819 mhi_pm_mission_mode_transition(mhi_cntrl);
820 break;
821 case DEV_ST_TRANSITION_FP:
822 write_lock_irq(&mhi_cntrl->pm_lock);
823 mhi_cntrl->ee = MHI_EE_FP;
824 write_unlock_irq(&mhi_cntrl->pm_lock);
825 mhi_create_devices(mhi_cntrl);
826 break;
827 case DEV_ST_TRANSITION_READY:
828 mhi_ready_state_transition(mhi_cntrl);
829 break;
830 case DEV_ST_TRANSITION_SYS_ERR:
831 mhi_pm_sys_error_transition(mhi_cntrl);
832 break;
833 case DEV_ST_TRANSITION_DISABLE:
834 mhi_pm_disable_transition(mhi_cntrl);
835 break;
836 default:
837 break;
838 }
839 kfree(itr);
840 }
841 }
842
mhi_pm_suspend(struct mhi_controller * mhi_cntrl)843 int mhi_pm_suspend(struct mhi_controller *mhi_cntrl)
844 {
845 struct mhi_chan *itr, *tmp;
846 struct device *dev = &mhi_cntrl->mhi_dev->dev;
847 enum mhi_pm_state new_state;
848 int ret;
849
850 if (mhi_cntrl->pm_state == MHI_PM_DISABLE)
851 return -EINVAL;
852
853 if (MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state))
854 return -EIO;
855
856 /* Return busy if there are any pending resources */
857 if (atomic_read(&mhi_cntrl->dev_wake) ||
858 atomic_read(&mhi_cntrl->pending_pkts))
859 return -EBUSY;
860
861 /* Take MHI out of M2 state */
862 read_lock_bh(&mhi_cntrl->pm_lock);
863 mhi_cntrl->wake_get(mhi_cntrl, false);
864 read_unlock_bh(&mhi_cntrl->pm_lock);
865
866 ret = wait_event_timeout(mhi_cntrl->state_event,
867 mhi_cntrl->dev_state == MHI_STATE_M0 ||
868 mhi_cntrl->dev_state == MHI_STATE_M1 ||
869 MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state),
870 msecs_to_jiffies(mhi_cntrl->timeout_ms));
871
872 read_lock_bh(&mhi_cntrl->pm_lock);
873 mhi_cntrl->wake_put(mhi_cntrl, false);
874 read_unlock_bh(&mhi_cntrl->pm_lock);
875
876 if (!ret || MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state)) {
877 dev_err(dev,
878 "Could not enter M0/M1 state");
879 return -EIO;
880 }
881
882 write_lock_irq(&mhi_cntrl->pm_lock);
883
884 if (atomic_read(&mhi_cntrl->dev_wake) ||
885 atomic_read(&mhi_cntrl->pending_pkts)) {
886 write_unlock_irq(&mhi_cntrl->pm_lock);
887 return -EBUSY;
888 }
889
890 dev_dbg(dev, "Allowing M3 transition\n");
891 new_state = mhi_tryset_pm_state(mhi_cntrl, MHI_PM_M3_ENTER);
892 if (new_state != MHI_PM_M3_ENTER) {
893 write_unlock_irq(&mhi_cntrl->pm_lock);
894 dev_err(dev,
895 "Error setting to PM state: %s from: %s\n",
896 to_mhi_pm_state_str(MHI_PM_M3_ENTER),
897 to_mhi_pm_state_str(mhi_cntrl->pm_state));
898 return -EIO;
899 }
900
901 /* Set MHI to M3 and wait for completion */
902 mhi_set_mhi_state(mhi_cntrl, MHI_STATE_M3);
903 write_unlock_irq(&mhi_cntrl->pm_lock);
904 dev_dbg(dev, "Waiting for M3 completion\n");
905
906 ret = wait_event_timeout(mhi_cntrl->state_event,
907 mhi_cntrl->dev_state == MHI_STATE_M3 ||
908 MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state),
909 msecs_to_jiffies(mhi_cntrl->timeout_ms));
910
911 if (!ret || MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state)) {
912 dev_err(dev,
913 "Did not enter M3 state, MHI state: %s, PM state: %s\n",
914 mhi_state_str(mhi_cntrl->dev_state),
915 to_mhi_pm_state_str(mhi_cntrl->pm_state));
916 return -EIO;
917 }
918
919 /* Notify clients about entering LPM */
920 list_for_each_entry_safe(itr, tmp, &mhi_cntrl->lpm_chans, node) {
921 mutex_lock(&itr->mutex);
922 if (itr->mhi_dev)
923 mhi_notify(itr->mhi_dev, MHI_CB_LPM_ENTER);
924 mutex_unlock(&itr->mutex);
925 }
926
927 return 0;
928 }
929 EXPORT_SYMBOL_GPL(mhi_pm_suspend);
930
__mhi_pm_resume(struct mhi_controller * mhi_cntrl,bool force)931 static int __mhi_pm_resume(struct mhi_controller *mhi_cntrl, bool force)
932 {
933 struct mhi_chan *itr, *tmp;
934 struct device *dev = &mhi_cntrl->mhi_dev->dev;
935 enum mhi_pm_state cur_state;
936 int ret;
937
938 dev_dbg(dev, "Entered with PM state: %s, MHI state: %s\n",
939 to_mhi_pm_state_str(mhi_cntrl->pm_state),
940 mhi_state_str(mhi_cntrl->dev_state));
941
942 if (mhi_cntrl->pm_state == MHI_PM_DISABLE)
943 return 0;
944
945 if (MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state))
946 return -EIO;
947
948 if (mhi_get_mhi_state(mhi_cntrl) != MHI_STATE_M3) {
949 dev_warn(dev, "Resuming from non M3 state (%s)\n",
950 mhi_state_str(mhi_get_mhi_state(mhi_cntrl)));
951 if (!force)
952 return -EINVAL;
953 }
954
955 /* Notify clients about exiting LPM */
956 list_for_each_entry_safe(itr, tmp, &mhi_cntrl->lpm_chans, node) {
957 mutex_lock(&itr->mutex);
958 if (itr->mhi_dev)
959 mhi_notify(itr->mhi_dev, MHI_CB_LPM_EXIT);
960 mutex_unlock(&itr->mutex);
961 }
962
963 write_lock_irq(&mhi_cntrl->pm_lock);
964 cur_state = mhi_tryset_pm_state(mhi_cntrl, MHI_PM_M3_EXIT);
965 if (cur_state != MHI_PM_M3_EXIT) {
966 write_unlock_irq(&mhi_cntrl->pm_lock);
967 dev_info(dev,
968 "Error setting to PM state: %s from: %s\n",
969 to_mhi_pm_state_str(MHI_PM_M3_EXIT),
970 to_mhi_pm_state_str(mhi_cntrl->pm_state));
971 return -EIO;
972 }
973
974 /* Set MHI to M0 and wait for completion */
975 mhi_set_mhi_state(mhi_cntrl, MHI_STATE_M0);
976 write_unlock_irq(&mhi_cntrl->pm_lock);
977
978 ret = wait_event_timeout(mhi_cntrl->state_event,
979 mhi_cntrl->dev_state == MHI_STATE_M0 ||
980 mhi_cntrl->dev_state == MHI_STATE_M2 ||
981 MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state),
982 msecs_to_jiffies(mhi_cntrl->timeout_ms));
983
984 if (!ret || MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state)) {
985 dev_err(dev,
986 "Did not enter M0 state, MHI state: %s, PM state: %s\n",
987 mhi_state_str(mhi_cntrl->dev_state),
988 to_mhi_pm_state_str(mhi_cntrl->pm_state));
989 return -EIO;
990 }
991
992 return 0;
993 }
994
mhi_pm_resume(struct mhi_controller * mhi_cntrl)995 int mhi_pm_resume(struct mhi_controller *mhi_cntrl)
996 {
997 return __mhi_pm_resume(mhi_cntrl, false);
998 }
999 EXPORT_SYMBOL_GPL(mhi_pm_resume);
1000
mhi_pm_resume_force(struct mhi_controller * mhi_cntrl)1001 int mhi_pm_resume_force(struct mhi_controller *mhi_cntrl)
1002 {
1003 return __mhi_pm_resume(mhi_cntrl, true);
1004 }
1005 EXPORT_SYMBOL_GPL(mhi_pm_resume_force);
1006
__mhi_device_get_sync(struct mhi_controller * mhi_cntrl)1007 int __mhi_device_get_sync(struct mhi_controller *mhi_cntrl)
1008 {
1009 int ret;
1010
1011 /* Wake up the device */
1012 read_lock_bh(&mhi_cntrl->pm_lock);
1013 if (MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state)) {
1014 read_unlock_bh(&mhi_cntrl->pm_lock);
1015 return -EIO;
1016 }
1017 mhi_cntrl->wake_get(mhi_cntrl, true);
1018 if (MHI_PM_IN_SUSPEND_STATE(mhi_cntrl->pm_state))
1019 mhi_trigger_resume(mhi_cntrl);
1020 read_unlock_bh(&mhi_cntrl->pm_lock);
1021
1022 ret = wait_event_timeout(mhi_cntrl->state_event,
1023 mhi_cntrl->pm_state == MHI_PM_M0 ||
1024 MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state),
1025 msecs_to_jiffies(mhi_cntrl->timeout_ms));
1026
1027 if (!ret || MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state)) {
1028 read_lock_bh(&mhi_cntrl->pm_lock);
1029 mhi_cntrl->wake_put(mhi_cntrl, false);
1030 read_unlock_bh(&mhi_cntrl->pm_lock);
1031 return -EIO;
1032 }
1033
1034 return 0;
1035 }
1036
1037 /* Assert device wake db */
mhi_assert_dev_wake(struct mhi_controller * mhi_cntrl,bool force)1038 static void mhi_assert_dev_wake(struct mhi_controller *mhi_cntrl, bool force)
1039 {
1040 unsigned long flags;
1041
1042 /*
1043 * If force flag is set, then increment the wake count value and
1044 * ring wake db
1045 */
1046 if (unlikely(force)) {
1047 spin_lock_irqsave(&mhi_cntrl->wlock, flags);
1048 atomic_inc(&mhi_cntrl->dev_wake);
1049 if (MHI_WAKE_DB_FORCE_SET_VALID(mhi_cntrl->pm_state) &&
1050 !mhi_cntrl->wake_set) {
1051 mhi_write_db(mhi_cntrl, mhi_cntrl->wake_db, 1);
1052 mhi_cntrl->wake_set = true;
1053 }
1054 spin_unlock_irqrestore(&mhi_cntrl->wlock, flags);
1055 } else {
1056 /*
1057 * If resources are already requested, then just increment
1058 * the wake count value and return
1059 */
1060 if (likely(atomic_add_unless(&mhi_cntrl->dev_wake, 1, 0)))
1061 return;
1062
1063 spin_lock_irqsave(&mhi_cntrl->wlock, flags);
1064 if ((atomic_inc_return(&mhi_cntrl->dev_wake) == 1) &&
1065 MHI_WAKE_DB_SET_VALID(mhi_cntrl->pm_state) &&
1066 !mhi_cntrl->wake_set) {
1067 mhi_write_db(mhi_cntrl, mhi_cntrl->wake_db, 1);
1068 mhi_cntrl->wake_set = true;
1069 }
1070 spin_unlock_irqrestore(&mhi_cntrl->wlock, flags);
1071 }
1072 }
1073
1074 /* De-assert device wake db */
mhi_deassert_dev_wake(struct mhi_controller * mhi_cntrl,bool override)1075 static void mhi_deassert_dev_wake(struct mhi_controller *mhi_cntrl,
1076 bool override)
1077 {
1078 unsigned long flags;
1079
1080 /*
1081 * Only continue if there is a single resource, else just decrement
1082 * and return
1083 */
1084 if (likely(atomic_add_unless(&mhi_cntrl->dev_wake, -1, 1)))
1085 return;
1086
1087 spin_lock_irqsave(&mhi_cntrl->wlock, flags);
1088 if ((atomic_dec_return(&mhi_cntrl->dev_wake) == 0) &&
1089 MHI_WAKE_DB_CLEAR_VALID(mhi_cntrl->pm_state) && !override &&
1090 mhi_cntrl->wake_set) {
1091 mhi_write_db(mhi_cntrl, mhi_cntrl->wake_db, 0);
1092 mhi_cntrl->wake_set = false;
1093 }
1094 spin_unlock_irqrestore(&mhi_cntrl->wlock, flags);
1095 }
1096
mhi_async_power_up(struct mhi_controller * mhi_cntrl)1097 int mhi_async_power_up(struct mhi_controller *mhi_cntrl)
1098 {
1099 struct mhi_event *mhi_event = mhi_cntrl->mhi_event;
1100 enum mhi_state state;
1101 enum mhi_ee_type current_ee;
1102 enum dev_st_transition next_state;
1103 struct device *dev = &mhi_cntrl->mhi_dev->dev;
1104 u32 interval_us = 25000; /* poll register field every 25 milliseconds */
1105 int ret, i;
1106
1107 dev_info(dev, "Requested to power ON\n");
1108
1109 /* Supply default wake routines if not provided by controller driver */
1110 if (!mhi_cntrl->wake_get || !mhi_cntrl->wake_put ||
1111 !mhi_cntrl->wake_toggle) {
1112 mhi_cntrl->wake_get = mhi_assert_dev_wake;
1113 mhi_cntrl->wake_put = mhi_deassert_dev_wake;
1114 mhi_cntrl->wake_toggle = (mhi_cntrl->db_access & MHI_PM_M2) ?
1115 mhi_toggle_dev_wake_nop : mhi_toggle_dev_wake;
1116 }
1117
1118 mutex_lock(&mhi_cntrl->pm_mutex);
1119 mhi_cntrl->pm_state = MHI_PM_DISABLE;
1120
1121 /* Setup BHI INTVEC */
1122 write_lock_irq(&mhi_cntrl->pm_lock);
1123 mhi_write_reg(mhi_cntrl, mhi_cntrl->bhi, BHI_INTVEC, 0);
1124 mhi_cntrl->pm_state = MHI_PM_POR;
1125 mhi_cntrl->ee = MHI_EE_MAX;
1126 current_ee = mhi_get_exec_env(mhi_cntrl);
1127 write_unlock_irq(&mhi_cntrl->pm_lock);
1128
1129 /* Confirm that the device is in valid exec env */
1130 if (!MHI_POWER_UP_CAPABLE(current_ee)) {
1131 dev_err(dev, "%s is not a valid EE for power on\n",
1132 TO_MHI_EXEC_STR(current_ee));
1133 ret = -EIO;
1134 goto error_exit;
1135 }
1136
1137 state = mhi_get_mhi_state(mhi_cntrl);
1138 dev_dbg(dev, "Attempting power on with EE: %s, state: %s\n",
1139 TO_MHI_EXEC_STR(current_ee), mhi_state_str(state));
1140
1141 if (state == MHI_STATE_SYS_ERR) {
1142 mhi_set_mhi_state(mhi_cntrl, MHI_STATE_RESET);
1143 ret = mhi_poll_reg_field(mhi_cntrl, mhi_cntrl->regs, MHICTRL,
1144 MHICTRL_RESET_MASK, 0, interval_us);
1145 if (ret) {
1146 dev_info(dev, "Failed to reset MHI due to syserr state\n");
1147 goto error_exit;
1148 }
1149
1150 /*
1151 * device cleares INTVEC as part of RESET processing,
1152 * re-program it
1153 */
1154 mhi_write_reg(mhi_cntrl, mhi_cntrl->bhi, BHI_INTVEC, 0);
1155 }
1156
1157 /* IRQs have been requested during probe, so we just need to enable them. */
1158 enable_irq(mhi_cntrl->irq[0]);
1159
1160 for (i = 0; i < mhi_cntrl->total_ev_rings; i++, mhi_event++) {
1161 if (mhi_event->offload_ev)
1162 continue;
1163
1164 enable_irq(mhi_cntrl->irq[mhi_event->irq]);
1165 }
1166
1167 /* Transition to next state */
1168 next_state = MHI_IN_PBL(current_ee) ?
1169 DEV_ST_TRANSITION_PBL : DEV_ST_TRANSITION_READY;
1170
1171 mhi_queue_state_transition(mhi_cntrl, next_state);
1172
1173 mutex_unlock(&mhi_cntrl->pm_mutex);
1174
1175 dev_info(dev, "Power on setup success\n");
1176
1177 return 0;
1178
1179 error_exit:
1180 mhi_cntrl->pm_state = MHI_PM_DISABLE;
1181 mutex_unlock(&mhi_cntrl->pm_mutex);
1182
1183 return ret;
1184 }
1185 EXPORT_SYMBOL_GPL(mhi_async_power_up);
1186
mhi_power_down(struct mhi_controller * mhi_cntrl,bool graceful)1187 void mhi_power_down(struct mhi_controller *mhi_cntrl, bool graceful)
1188 {
1189 enum mhi_pm_state cur_state, transition_state;
1190 struct device *dev = &mhi_cntrl->mhi_dev->dev;
1191
1192 mutex_lock(&mhi_cntrl->pm_mutex);
1193 write_lock_irq(&mhi_cntrl->pm_lock);
1194 cur_state = mhi_cntrl->pm_state;
1195 if (cur_state == MHI_PM_DISABLE) {
1196 write_unlock_irq(&mhi_cntrl->pm_lock);
1197 mutex_unlock(&mhi_cntrl->pm_mutex);
1198 return; /* Already powered down */
1199 }
1200
1201 /* If it's not a graceful shutdown, force MHI to linkdown state */
1202 transition_state = (graceful) ? MHI_PM_SHUTDOWN_PROCESS :
1203 MHI_PM_LD_ERR_FATAL_DETECT;
1204
1205 cur_state = mhi_tryset_pm_state(mhi_cntrl, transition_state);
1206 if (cur_state != transition_state) {
1207 dev_err(dev, "Failed to move to state: %s from: %s\n",
1208 to_mhi_pm_state_str(transition_state),
1209 to_mhi_pm_state_str(mhi_cntrl->pm_state));
1210 /* Force link down or error fatal detected state */
1211 mhi_cntrl->pm_state = MHI_PM_LD_ERR_FATAL_DETECT;
1212 }
1213
1214 /* mark device inactive to avoid any further host processing */
1215 mhi_cntrl->ee = MHI_EE_DISABLE_TRANSITION;
1216 mhi_cntrl->dev_state = MHI_STATE_RESET;
1217
1218 wake_up_all(&mhi_cntrl->state_event);
1219
1220 write_unlock_irq(&mhi_cntrl->pm_lock);
1221 mutex_unlock(&mhi_cntrl->pm_mutex);
1222
1223 mhi_queue_state_transition(mhi_cntrl, DEV_ST_TRANSITION_DISABLE);
1224
1225 /* Wait for shutdown to complete */
1226 flush_work(&mhi_cntrl->st_worker);
1227
1228 disable_irq(mhi_cntrl->irq[0]);
1229 }
1230 EXPORT_SYMBOL_GPL(mhi_power_down);
1231
mhi_sync_power_up(struct mhi_controller * mhi_cntrl)1232 int mhi_sync_power_up(struct mhi_controller *mhi_cntrl)
1233 {
1234 int ret = mhi_async_power_up(mhi_cntrl);
1235
1236 if (ret)
1237 return ret;
1238
1239 wait_event_timeout(mhi_cntrl->state_event,
1240 MHI_IN_MISSION_MODE(mhi_cntrl->ee) ||
1241 MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state),
1242 msecs_to_jiffies(mhi_cntrl->timeout_ms));
1243
1244 ret = (MHI_IN_MISSION_MODE(mhi_cntrl->ee)) ? 0 : -ETIMEDOUT;
1245 if (ret)
1246 mhi_power_down(mhi_cntrl, false);
1247
1248 return ret;
1249 }
1250 EXPORT_SYMBOL(mhi_sync_power_up);
1251
mhi_force_rddm_mode(struct mhi_controller * mhi_cntrl)1252 int mhi_force_rddm_mode(struct mhi_controller *mhi_cntrl)
1253 {
1254 struct device *dev = &mhi_cntrl->mhi_dev->dev;
1255 int ret;
1256
1257 /* Check if device is already in RDDM */
1258 if (mhi_cntrl->ee == MHI_EE_RDDM)
1259 return 0;
1260
1261 dev_dbg(dev, "Triggering SYS_ERR to force RDDM state\n");
1262 mhi_set_mhi_state(mhi_cntrl, MHI_STATE_SYS_ERR);
1263
1264 /* Wait for RDDM event */
1265 ret = wait_event_timeout(mhi_cntrl->state_event,
1266 mhi_cntrl->ee == MHI_EE_RDDM,
1267 msecs_to_jiffies(mhi_cntrl->timeout_ms));
1268 ret = ret ? 0 : -EIO;
1269
1270 return ret;
1271 }
1272 EXPORT_SYMBOL_GPL(mhi_force_rddm_mode);
1273
mhi_device_get(struct mhi_device * mhi_dev)1274 void mhi_device_get(struct mhi_device *mhi_dev)
1275 {
1276 struct mhi_controller *mhi_cntrl = mhi_dev->mhi_cntrl;
1277
1278 mhi_dev->dev_wake++;
1279 read_lock_bh(&mhi_cntrl->pm_lock);
1280 if (MHI_PM_IN_SUSPEND_STATE(mhi_cntrl->pm_state))
1281 mhi_trigger_resume(mhi_cntrl);
1282
1283 mhi_cntrl->wake_get(mhi_cntrl, true);
1284 read_unlock_bh(&mhi_cntrl->pm_lock);
1285 }
1286 EXPORT_SYMBOL_GPL(mhi_device_get);
1287
mhi_device_get_sync(struct mhi_device * mhi_dev)1288 int mhi_device_get_sync(struct mhi_device *mhi_dev)
1289 {
1290 struct mhi_controller *mhi_cntrl = mhi_dev->mhi_cntrl;
1291 int ret;
1292
1293 ret = __mhi_device_get_sync(mhi_cntrl);
1294 if (!ret)
1295 mhi_dev->dev_wake++;
1296
1297 return ret;
1298 }
1299 EXPORT_SYMBOL_GPL(mhi_device_get_sync);
1300
mhi_device_put(struct mhi_device * mhi_dev)1301 void mhi_device_put(struct mhi_device *mhi_dev)
1302 {
1303 struct mhi_controller *mhi_cntrl = mhi_dev->mhi_cntrl;
1304
1305 mhi_dev->dev_wake--;
1306 read_lock_bh(&mhi_cntrl->pm_lock);
1307 if (MHI_PM_IN_SUSPEND_STATE(mhi_cntrl->pm_state))
1308 mhi_trigger_resume(mhi_cntrl);
1309
1310 mhi_cntrl->wake_put(mhi_cntrl, false);
1311 read_unlock_bh(&mhi_cntrl->pm_lock);
1312 }
1313 EXPORT_SYMBOL_GPL(mhi_device_put);
1314