1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * MHI PCI driver - MHI over PCI controller driver
4 *
5 * This module is a generic driver for registering MHI-over-PCI devices,
6 * such as PCIe QCOM modems.
7 *
8 * Copyright (C) 2020 Linaro Ltd <loic.poulain@linaro.org>
9 */
10
11 #include <linux/delay.h>
12 #include <linux/device.h>
13 #include <linux/mhi.h>
14 #include <linux/module.h>
15 #include <linux/pci.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/timer.h>
18 #include <linux/workqueue.h>
19
20 #define MHI_PCI_DEFAULT_BAR_NUM 0
21
22 #define MHI_POST_RESET_DELAY_MS 2000
23
24 #define HEALTH_CHECK_PERIOD (HZ * 2)
25
26 /* PCI VID definitions */
27 #define PCI_VENDOR_ID_THALES 0x1269
28 #define PCI_VENDOR_ID_QUECTEL 0x1eac
29
30 /**
31 * struct mhi_pci_dev_info - MHI PCI device specific information
32 * @config: MHI controller configuration
33 * @name: name of the PCI module
34 * @fw: firmware path (if any)
35 * @edl: emergency download mode firmware path (if any)
36 * @bar_num: PCI base address register to use for MHI MMIO register space
37 * @dma_data_width: DMA transfer word size (32 or 64 bits)
38 * @mru_default: default MRU size for MBIM network packets
39 * @sideband_wake: Devices using dedicated sideband GPIO for wakeup instead
40 * of inband wake support (such as sdx24)
41 */
42 struct mhi_pci_dev_info {
43 const struct mhi_controller_config *config;
44 const char *name;
45 const char *fw;
46 const char *edl;
47 unsigned int bar_num;
48 unsigned int dma_data_width;
49 unsigned int mru_default;
50 bool sideband_wake;
51 };
52
53 #define MHI_CHANNEL_CONFIG_UL(ch_num, ch_name, el_count, ev_ring) \
54 { \
55 .num = ch_num, \
56 .name = ch_name, \
57 .num_elements = el_count, \
58 .event_ring = ev_ring, \
59 .dir = DMA_TO_DEVICE, \
60 .ee_mask = BIT(MHI_EE_AMSS), \
61 .pollcfg = 0, \
62 .doorbell = MHI_DB_BRST_DISABLE, \
63 .lpm_notify = false, \
64 .offload_channel = false, \
65 .doorbell_mode_switch = false, \
66 } \
67
68 #define MHI_CHANNEL_CONFIG_DL(ch_num, ch_name, el_count, ev_ring) \
69 { \
70 .num = ch_num, \
71 .name = ch_name, \
72 .num_elements = el_count, \
73 .event_ring = ev_ring, \
74 .dir = DMA_FROM_DEVICE, \
75 .ee_mask = BIT(MHI_EE_AMSS), \
76 .pollcfg = 0, \
77 .doorbell = MHI_DB_BRST_DISABLE, \
78 .lpm_notify = false, \
79 .offload_channel = false, \
80 .doorbell_mode_switch = false, \
81 }
82
83 #define MHI_CHANNEL_CONFIG_DL_AUTOQUEUE(ch_num, ch_name, el_count, ev_ring) \
84 { \
85 .num = ch_num, \
86 .name = ch_name, \
87 .num_elements = el_count, \
88 .event_ring = ev_ring, \
89 .dir = DMA_FROM_DEVICE, \
90 .ee_mask = BIT(MHI_EE_AMSS), \
91 .pollcfg = 0, \
92 .doorbell = MHI_DB_BRST_DISABLE, \
93 .lpm_notify = false, \
94 .offload_channel = false, \
95 .doorbell_mode_switch = false, \
96 .auto_queue = true, \
97 }
98
99 #define MHI_EVENT_CONFIG_CTRL(ev_ring, el_count) \
100 { \
101 .num_elements = el_count, \
102 .irq_moderation_ms = 0, \
103 .irq = (ev_ring) + 1, \
104 .priority = 1, \
105 .mode = MHI_DB_BRST_DISABLE, \
106 .data_type = MHI_ER_CTRL, \
107 .hardware_event = false, \
108 .client_managed = false, \
109 .offload_channel = false, \
110 }
111
112 #define MHI_CHANNEL_CONFIG_HW_UL(ch_num, ch_name, el_count, ev_ring) \
113 { \
114 .num = ch_num, \
115 .name = ch_name, \
116 .num_elements = el_count, \
117 .event_ring = ev_ring, \
118 .dir = DMA_TO_DEVICE, \
119 .ee_mask = BIT(MHI_EE_AMSS), \
120 .pollcfg = 0, \
121 .doorbell = MHI_DB_BRST_ENABLE, \
122 .lpm_notify = false, \
123 .offload_channel = false, \
124 .doorbell_mode_switch = true, \
125 } \
126
127 #define MHI_CHANNEL_CONFIG_HW_DL(ch_num, ch_name, el_count, ev_ring) \
128 { \
129 .num = ch_num, \
130 .name = ch_name, \
131 .num_elements = el_count, \
132 .event_ring = ev_ring, \
133 .dir = DMA_FROM_DEVICE, \
134 .ee_mask = BIT(MHI_EE_AMSS), \
135 .pollcfg = 0, \
136 .doorbell = MHI_DB_BRST_ENABLE, \
137 .lpm_notify = false, \
138 .offload_channel = false, \
139 .doorbell_mode_switch = true, \
140 }
141
142 #define MHI_CHANNEL_CONFIG_UL_SBL(ch_num, ch_name, el_count, ev_ring) \
143 { \
144 .num = ch_num, \
145 .name = ch_name, \
146 .num_elements = el_count, \
147 .event_ring = ev_ring, \
148 .dir = DMA_TO_DEVICE, \
149 .ee_mask = BIT(MHI_EE_SBL), \
150 .pollcfg = 0, \
151 .doorbell = MHI_DB_BRST_DISABLE, \
152 .lpm_notify = false, \
153 .offload_channel = false, \
154 .doorbell_mode_switch = false, \
155 } \
156
157 #define MHI_CHANNEL_CONFIG_DL_SBL(ch_num, ch_name, el_count, ev_ring) \
158 { \
159 .num = ch_num, \
160 .name = ch_name, \
161 .num_elements = el_count, \
162 .event_ring = ev_ring, \
163 .dir = DMA_FROM_DEVICE, \
164 .ee_mask = BIT(MHI_EE_SBL), \
165 .pollcfg = 0, \
166 .doorbell = MHI_DB_BRST_DISABLE, \
167 .lpm_notify = false, \
168 .offload_channel = false, \
169 .doorbell_mode_switch = false, \
170 }
171
172 #define MHI_CHANNEL_CONFIG_UL_FP(ch_num, ch_name, el_count, ev_ring) \
173 { \
174 .num = ch_num, \
175 .name = ch_name, \
176 .num_elements = el_count, \
177 .event_ring = ev_ring, \
178 .dir = DMA_TO_DEVICE, \
179 .ee_mask = BIT(MHI_EE_FP), \
180 .pollcfg = 0, \
181 .doorbell = MHI_DB_BRST_DISABLE, \
182 .lpm_notify = false, \
183 .offload_channel = false, \
184 .doorbell_mode_switch = false, \
185 } \
186
187 #define MHI_CHANNEL_CONFIG_DL_FP(ch_num, ch_name, el_count, ev_ring) \
188 { \
189 .num = ch_num, \
190 .name = ch_name, \
191 .num_elements = el_count, \
192 .event_ring = ev_ring, \
193 .dir = DMA_FROM_DEVICE, \
194 .ee_mask = BIT(MHI_EE_FP), \
195 .pollcfg = 0, \
196 .doorbell = MHI_DB_BRST_DISABLE, \
197 .lpm_notify = false, \
198 .offload_channel = false, \
199 .doorbell_mode_switch = false, \
200 }
201
202 #define MHI_EVENT_CONFIG_DATA(ev_ring, el_count) \
203 { \
204 .num_elements = el_count, \
205 .irq_moderation_ms = 5, \
206 .irq = (ev_ring) + 1, \
207 .priority = 1, \
208 .mode = MHI_DB_BRST_DISABLE, \
209 .data_type = MHI_ER_DATA, \
210 .hardware_event = false, \
211 .client_managed = false, \
212 .offload_channel = false, \
213 }
214
215 #define MHI_EVENT_CONFIG_SW_DATA(ev_ring, el_count) \
216 { \
217 .num_elements = el_count, \
218 .irq_moderation_ms = 0, \
219 .irq = (ev_ring) + 1, \
220 .priority = 1, \
221 .mode = MHI_DB_BRST_DISABLE, \
222 .data_type = MHI_ER_DATA, \
223 .hardware_event = false, \
224 .client_managed = false, \
225 .offload_channel = false, \
226 }
227
228 #define MHI_EVENT_CONFIG_HW_DATA(ev_ring, el_count, ch_num) \
229 { \
230 .num_elements = el_count, \
231 .irq_moderation_ms = 1, \
232 .irq = (ev_ring) + 1, \
233 .priority = 1, \
234 .mode = MHI_DB_BRST_DISABLE, \
235 .data_type = MHI_ER_DATA, \
236 .hardware_event = true, \
237 .client_managed = false, \
238 .offload_channel = false, \
239 .channel = ch_num, \
240 }
241
242 static const struct mhi_channel_config modem_qcom_v1_mhi_channels[] = {
243 MHI_CHANNEL_CONFIG_UL(4, "DIAG", 16, 1),
244 MHI_CHANNEL_CONFIG_DL(5, "DIAG", 16, 1),
245 MHI_CHANNEL_CONFIG_UL(12, "MBIM", 4, 0),
246 MHI_CHANNEL_CONFIG_DL(13, "MBIM", 4, 0),
247 MHI_CHANNEL_CONFIG_UL(14, "QMI", 4, 0),
248 MHI_CHANNEL_CONFIG_DL(15, "QMI", 4, 0),
249 MHI_CHANNEL_CONFIG_UL(20, "IPCR", 8, 0),
250 MHI_CHANNEL_CONFIG_DL_AUTOQUEUE(21, "IPCR", 8, 0),
251 MHI_CHANNEL_CONFIG_UL_FP(34, "FIREHOSE", 32, 0),
252 MHI_CHANNEL_CONFIG_DL_FP(35, "FIREHOSE", 32, 0),
253 MHI_CHANNEL_CONFIG_UL(46, "IP_SW0", 64, 2),
254 MHI_CHANNEL_CONFIG_DL(47, "IP_SW0", 64, 3),
255 MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0", 128, 4),
256 MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0", 128, 5),
257 };
258
259 static struct mhi_event_config modem_qcom_v1_mhi_events[] = {
260 /* first ring is control+data ring */
261 MHI_EVENT_CONFIG_CTRL(0, 64),
262 /* DIAG dedicated event ring */
263 MHI_EVENT_CONFIG_DATA(1, 128),
264 /* Software channels dedicated event ring */
265 MHI_EVENT_CONFIG_SW_DATA(2, 64),
266 MHI_EVENT_CONFIG_SW_DATA(3, 64),
267 /* Hardware channels request dedicated hardware event rings */
268 MHI_EVENT_CONFIG_HW_DATA(4, 1024, 100),
269 MHI_EVENT_CONFIG_HW_DATA(5, 2048, 101)
270 };
271
272 static const struct mhi_controller_config modem_qcom_v1_mhiv_config = {
273 .max_channels = 128,
274 .timeout_ms = 8000,
275 .num_channels = ARRAY_SIZE(modem_qcom_v1_mhi_channels),
276 .ch_cfg = modem_qcom_v1_mhi_channels,
277 .num_events = ARRAY_SIZE(modem_qcom_v1_mhi_events),
278 .event_cfg = modem_qcom_v1_mhi_events,
279 };
280
281 static const struct mhi_pci_dev_info mhi_qcom_sdx65_info = {
282 .name = "qcom-sdx65m",
283 .fw = "qcom/sdx65m/xbl.elf",
284 .edl = "qcom/sdx65m/edl.mbn",
285 .config = &modem_qcom_v1_mhiv_config,
286 .bar_num = MHI_PCI_DEFAULT_BAR_NUM,
287 .dma_data_width = 32,
288 .sideband_wake = false,
289 };
290
291 static const struct mhi_pci_dev_info mhi_qcom_sdx55_info = {
292 .name = "qcom-sdx55m",
293 .fw = "qcom/sdx55m/sbl1.mbn",
294 .edl = "qcom/sdx55m/edl.mbn",
295 .config = &modem_qcom_v1_mhiv_config,
296 .bar_num = MHI_PCI_DEFAULT_BAR_NUM,
297 .dma_data_width = 32,
298 .mru_default = 32768,
299 .sideband_wake = false,
300 };
301
302 static const struct mhi_pci_dev_info mhi_qcom_sdx24_info = {
303 .name = "qcom-sdx24",
304 .edl = "qcom/prog_firehose_sdx24.mbn",
305 .config = &modem_qcom_v1_mhiv_config,
306 .bar_num = MHI_PCI_DEFAULT_BAR_NUM,
307 .dma_data_width = 32,
308 .sideband_wake = true,
309 };
310
311 static const struct mhi_channel_config mhi_quectel_em1xx_channels[] = {
312 MHI_CHANNEL_CONFIG_UL(0, "NMEA", 32, 0),
313 MHI_CHANNEL_CONFIG_DL(1, "NMEA", 32, 0),
314 MHI_CHANNEL_CONFIG_UL_SBL(2, "SAHARA", 32, 0),
315 MHI_CHANNEL_CONFIG_DL_SBL(3, "SAHARA", 32, 0),
316 MHI_CHANNEL_CONFIG_UL(4, "DIAG", 32, 1),
317 MHI_CHANNEL_CONFIG_DL(5, "DIAG", 32, 1),
318 MHI_CHANNEL_CONFIG_UL(12, "MBIM", 32, 0),
319 MHI_CHANNEL_CONFIG_DL(13, "MBIM", 32, 0),
320 MHI_CHANNEL_CONFIG_UL(32, "DUN", 32, 0),
321 MHI_CHANNEL_CONFIG_DL(33, "DUN", 32, 0),
322 /* The EDL firmware is a flash-programmer exposing firehose protocol */
323 MHI_CHANNEL_CONFIG_UL_FP(34, "FIREHOSE", 32, 0),
324 MHI_CHANNEL_CONFIG_DL_FP(35, "FIREHOSE", 32, 0),
325 MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0_MBIM", 128, 2),
326 MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0_MBIM", 128, 3),
327 };
328
329 static struct mhi_event_config mhi_quectel_em1xx_events[] = {
330 MHI_EVENT_CONFIG_CTRL(0, 128),
331 MHI_EVENT_CONFIG_DATA(1, 128),
332 MHI_EVENT_CONFIG_HW_DATA(2, 1024, 100),
333 MHI_EVENT_CONFIG_HW_DATA(3, 1024, 101)
334 };
335
336 static const struct mhi_controller_config modem_quectel_em1xx_config = {
337 .max_channels = 128,
338 .timeout_ms = 20000,
339 .num_channels = ARRAY_SIZE(mhi_quectel_em1xx_channels),
340 .ch_cfg = mhi_quectel_em1xx_channels,
341 .num_events = ARRAY_SIZE(mhi_quectel_em1xx_events),
342 .event_cfg = mhi_quectel_em1xx_events,
343 };
344
345 static const struct mhi_pci_dev_info mhi_quectel_em1xx_info = {
346 .name = "quectel-em1xx",
347 .edl = "qcom/prog_firehose_sdx24.mbn",
348 .config = &modem_quectel_em1xx_config,
349 .bar_num = MHI_PCI_DEFAULT_BAR_NUM,
350 .dma_data_width = 32,
351 .mru_default = 32768,
352 .sideband_wake = true,
353 };
354
355 static const struct mhi_pci_dev_info mhi_quectel_rm5xx_info = {
356 .name = "quectel-rm5xx",
357 .edl = "qcom/prog_firehose_sdx6x.elf",
358 .config = &modem_quectel_em1xx_config,
359 .bar_num = MHI_PCI_DEFAULT_BAR_NUM,
360 .dma_data_width = 32,
361 .mru_default = 32768,
362 .sideband_wake = true,
363 };
364
365 static const struct mhi_channel_config mhi_foxconn_sdx55_channels[] = {
366 MHI_CHANNEL_CONFIG_UL(0, "LOOPBACK", 32, 0),
367 MHI_CHANNEL_CONFIG_DL(1, "LOOPBACK", 32, 0),
368 MHI_CHANNEL_CONFIG_UL(4, "DIAG", 32, 1),
369 MHI_CHANNEL_CONFIG_DL(5, "DIAG", 32, 1),
370 MHI_CHANNEL_CONFIG_UL(12, "MBIM", 32, 0),
371 MHI_CHANNEL_CONFIG_DL(13, "MBIM", 32, 0),
372 MHI_CHANNEL_CONFIG_UL(32, "DUN", 32, 0),
373 MHI_CHANNEL_CONFIG_DL(33, "DUN", 32, 0),
374 MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0_MBIM", 128, 2),
375 MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0_MBIM", 128, 3),
376 };
377
378 static struct mhi_event_config mhi_foxconn_sdx55_events[] = {
379 MHI_EVENT_CONFIG_CTRL(0, 128),
380 MHI_EVENT_CONFIG_DATA(1, 128),
381 MHI_EVENT_CONFIG_HW_DATA(2, 1024, 100),
382 MHI_EVENT_CONFIG_HW_DATA(3, 1024, 101)
383 };
384
385 static const struct mhi_controller_config modem_foxconn_sdx55_config = {
386 .max_channels = 128,
387 .timeout_ms = 20000,
388 .num_channels = ARRAY_SIZE(mhi_foxconn_sdx55_channels),
389 .ch_cfg = mhi_foxconn_sdx55_channels,
390 .num_events = ARRAY_SIZE(mhi_foxconn_sdx55_events),
391 .event_cfg = mhi_foxconn_sdx55_events,
392 };
393
394 static const struct mhi_pci_dev_info mhi_foxconn_sdx24_info = {
395 .name = "foxconn-sdx24",
396 .config = &modem_foxconn_sdx55_config,
397 .bar_num = MHI_PCI_DEFAULT_BAR_NUM,
398 .dma_data_width = 32,
399 .mru_default = 32768,
400 .sideband_wake = false,
401 };
402
403 static const struct mhi_pci_dev_info mhi_foxconn_sdx55_info = {
404 .name = "foxconn-sdx55",
405 .fw = "qcom/sdx55m/sbl1.mbn",
406 .edl = "qcom/sdx55m/edl.mbn",
407 .config = &modem_foxconn_sdx55_config,
408 .bar_num = MHI_PCI_DEFAULT_BAR_NUM,
409 .dma_data_width = 32,
410 .mru_default = 32768,
411 .sideband_wake = false,
412 };
413
414 static const struct mhi_pci_dev_info mhi_foxconn_sdx65_info = {
415 .name = "foxconn-sdx65",
416 .config = &modem_foxconn_sdx55_config,
417 .bar_num = MHI_PCI_DEFAULT_BAR_NUM,
418 .dma_data_width = 32,
419 .mru_default = 32768,
420 .sideband_wake = false,
421 };
422
423 static const struct mhi_channel_config mhi_mv3x_channels[] = {
424 MHI_CHANNEL_CONFIG_UL(0, "LOOPBACK", 64, 0),
425 MHI_CHANNEL_CONFIG_DL(1, "LOOPBACK", 64, 0),
426 /* MBIM Control Channel */
427 MHI_CHANNEL_CONFIG_UL(12, "MBIM", 64, 0),
428 MHI_CHANNEL_CONFIG_DL(13, "MBIM", 64, 0),
429 /* MBIM Data Channel */
430 MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0_MBIM", 512, 2),
431 MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0_MBIM", 512, 3),
432 };
433
434 static struct mhi_event_config mhi_mv3x_events[] = {
435 MHI_EVENT_CONFIG_CTRL(0, 256),
436 MHI_EVENT_CONFIG_DATA(1, 256),
437 MHI_EVENT_CONFIG_HW_DATA(2, 1024, 100),
438 MHI_EVENT_CONFIG_HW_DATA(3, 1024, 101),
439 };
440
441 static const struct mhi_controller_config modem_mv3x_config = {
442 .max_channels = 128,
443 .timeout_ms = 20000,
444 .num_channels = ARRAY_SIZE(mhi_mv3x_channels),
445 .ch_cfg = mhi_mv3x_channels,
446 .num_events = ARRAY_SIZE(mhi_mv3x_events),
447 .event_cfg = mhi_mv3x_events,
448 };
449
450 static const struct mhi_pci_dev_info mhi_mv31_info = {
451 .name = "cinterion-mv31",
452 .config = &modem_mv3x_config,
453 .bar_num = MHI_PCI_DEFAULT_BAR_NUM,
454 .dma_data_width = 32,
455 .mru_default = 32768,
456 };
457
458 static const struct mhi_pci_dev_info mhi_mv32_info = {
459 .name = "cinterion-mv32",
460 .config = &modem_mv3x_config,
461 .bar_num = MHI_PCI_DEFAULT_BAR_NUM,
462 .dma_data_width = 32,
463 .mru_default = 32768,
464 };
465
466 static const struct mhi_channel_config mhi_sierra_em919x_channels[] = {
467 MHI_CHANNEL_CONFIG_UL_SBL(2, "SAHARA", 32, 0),
468 MHI_CHANNEL_CONFIG_DL_SBL(3, "SAHARA", 256, 0),
469 MHI_CHANNEL_CONFIG_UL(4, "DIAG", 32, 0),
470 MHI_CHANNEL_CONFIG_DL(5, "DIAG", 32, 0),
471 MHI_CHANNEL_CONFIG_UL(12, "MBIM", 128, 0),
472 MHI_CHANNEL_CONFIG_DL(13, "MBIM", 128, 0),
473 MHI_CHANNEL_CONFIG_UL(14, "QMI", 32, 0),
474 MHI_CHANNEL_CONFIG_DL(15, "QMI", 32, 0),
475 MHI_CHANNEL_CONFIG_UL(32, "DUN", 32, 0),
476 MHI_CHANNEL_CONFIG_DL(33, "DUN", 32, 0),
477 MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0", 512, 1),
478 MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0", 512, 2),
479 };
480
481 static struct mhi_event_config modem_sierra_em919x_mhi_events[] = {
482 /* first ring is control+data and DIAG ring */
483 MHI_EVENT_CONFIG_CTRL(0, 2048),
484 /* Hardware channels request dedicated hardware event rings */
485 MHI_EVENT_CONFIG_HW_DATA(1, 2048, 100),
486 MHI_EVENT_CONFIG_HW_DATA(2, 2048, 101)
487 };
488
489 static const struct mhi_controller_config modem_sierra_em919x_config = {
490 .max_channels = 128,
491 .timeout_ms = 24000,
492 .num_channels = ARRAY_SIZE(mhi_sierra_em919x_channels),
493 .ch_cfg = mhi_sierra_em919x_channels,
494 .num_events = ARRAY_SIZE(modem_sierra_em919x_mhi_events),
495 .event_cfg = modem_sierra_em919x_mhi_events,
496 };
497
498 static const struct mhi_pci_dev_info mhi_sierra_em919x_info = {
499 .name = "sierra-em919x",
500 .config = &modem_sierra_em919x_config,
501 .bar_num = MHI_PCI_DEFAULT_BAR_NUM,
502 .dma_data_width = 32,
503 .sideband_wake = false,
504 };
505
506 static const struct mhi_channel_config mhi_telit_fn980_hw_v1_channels[] = {
507 MHI_CHANNEL_CONFIG_UL(14, "QMI", 32, 0),
508 MHI_CHANNEL_CONFIG_DL(15, "QMI", 32, 0),
509 MHI_CHANNEL_CONFIG_UL(20, "IPCR", 16, 0),
510 MHI_CHANNEL_CONFIG_DL_AUTOQUEUE(21, "IPCR", 16, 0),
511 MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0", 128, 1),
512 MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0", 128, 2),
513 };
514
515 static struct mhi_event_config mhi_telit_fn980_hw_v1_events[] = {
516 MHI_EVENT_CONFIG_CTRL(0, 128),
517 MHI_EVENT_CONFIG_HW_DATA(1, 1024, 100),
518 MHI_EVENT_CONFIG_HW_DATA(2, 2048, 101)
519 };
520
521 static struct mhi_controller_config modem_telit_fn980_hw_v1_config = {
522 .max_channels = 128,
523 .timeout_ms = 20000,
524 .num_channels = ARRAY_SIZE(mhi_telit_fn980_hw_v1_channels),
525 .ch_cfg = mhi_telit_fn980_hw_v1_channels,
526 .num_events = ARRAY_SIZE(mhi_telit_fn980_hw_v1_events),
527 .event_cfg = mhi_telit_fn980_hw_v1_events,
528 };
529
530 static const struct mhi_pci_dev_info mhi_telit_fn980_hw_v1_info = {
531 .name = "telit-fn980-hwv1",
532 .fw = "qcom/sdx55m/sbl1.mbn",
533 .edl = "qcom/sdx55m/edl.mbn",
534 .config = &modem_telit_fn980_hw_v1_config,
535 .bar_num = MHI_PCI_DEFAULT_BAR_NUM,
536 .dma_data_width = 32,
537 .mru_default = 32768,
538 .sideband_wake = false,
539 };
540
541 static const struct mhi_channel_config mhi_telit_fn990_channels[] = {
542 MHI_CHANNEL_CONFIG_UL_SBL(2, "SAHARA", 32, 0),
543 MHI_CHANNEL_CONFIG_DL_SBL(3, "SAHARA", 32, 0),
544 MHI_CHANNEL_CONFIG_UL(4, "DIAG", 64, 1),
545 MHI_CHANNEL_CONFIG_DL(5, "DIAG", 64, 1),
546 MHI_CHANNEL_CONFIG_UL(12, "MBIM", 32, 0),
547 MHI_CHANNEL_CONFIG_DL(13, "MBIM", 32, 0),
548 MHI_CHANNEL_CONFIG_UL(32, "DUN", 32, 0),
549 MHI_CHANNEL_CONFIG_DL(33, "DUN", 32, 0),
550 MHI_CHANNEL_CONFIG_UL(92, "DUN2", 32, 1),
551 MHI_CHANNEL_CONFIG_DL(93, "DUN2", 32, 1),
552 MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0_MBIM", 128, 2),
553 MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0_MBIM", 128, 3),
554 };
555
556 static struct mhi_event_config mhi_telit_fn990_events[] = {
557 MHI_EVENT_CONFIG_CTRL(0, 128),
558 MHI_EVENT_CONFIG_DATA(1, 128),
559 MHI_EVENT_CONFIG_HW_DATA(2, 1024, 100),
560 MHI_EVENT_CONFIG_HW_DATA(3, 2048, 101)
561 };
562
563 static const struct mhi_controller_config modem_telit_fn990_config = {
564 .max_channels = 128,
565 .timeout_ms = 20000,
566 .num_channels = ARRAY_SIZE(mhi_telit_fn990_channels),
567 .ch_cfg = mhi_telit_fn990_channels,
568 .num_events = ARRAY_SIZE(mhi_telit_fn990_events),
569 .event_cfg = mhi_telit_fn990_events,
570 };
571
572 static const struct mhi_pci_dev_info mhi_telit_fn990_info = {
573 .name = "telit-fn990",
574 .config = &modem_telit_fn990_config,
575 .bar_num = MHI_PCI_DEFAULT_BAR_NUM,
576 .dma_data_width = 32,
577 .sideband_wake = false,
578 .mru_default = 32768,
579 };
580
581 static const struct mhi_pci_dev_info mhi_telit_fe990a_info = {
582 .name = "telit-fe990a",
583 .config = &modem_telit_fn990_config,
584 .bar_num = MHI_PCI_DEFAULT_BAR_NUM,
585 .dma_data_width = 32,
586 .sideband_wake = false,
587 .mru_default = 32768,
588 };
589
590 /* Keep the list sorted based on the PID. New VID should be added as the last entry */
591 static const struct pci_device_id mhi_pci_id_table[] = {
592 { PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0304),
593 .driver_data = (kernel_ulong_t) &mhi_qcom_sdx24_info },
594 { PCI_DEVICE_SUB(PCI_VENDOR_ID_QCOM, 0x0306, PCI_VENDOR_ID_QCOM, 0x010c),
595 .driver_data = (kernel_ulong_t) &mhi_foxconn_sdx55_info },
596 /* EM919x (sdx55), use the same vid:pid as qcom-sdx55m */
597 { PCI_DEVICE_SUB(PCI_VENDOR_ID_QCOM, 0x0306, 0x18d7, 0x0200),
598 .driver_data = (kernel_ulong_t) &mhi_sierra_em919x_info },
599 /* Telit FN980 hardware revision v1 */
600 { PCI_DEVICE_SUB(PCI_VENDOR_ID_QCOM, 0x0306, 0x1C5D, 0x2000),
601 .driver_data = (kernel_ulong_t) &mhi_telit_fn980_hw_v1_info },
602 { PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0306),
603 .driver_data = (kernel_ulong_t) &mhi_qcom_sdx55_info },
604 /* Telit FN990 */
605 { PCI_DEVICE_SUB(PCI_VENDOR_ID_QCOM, 0x0308, 0x1c5d, 0x2010),
606 .driver_data = (kernel_ulong_t) &mhi_telit_fn990_info },
607 /* Telit FE990A */
608 { PCI_DEVICE_SUB(PCI_VENDOR_ID_QCOM, 0x0308, 0x1c5d, 0x2015),
609 .driver_data = (kernel_ulong_t) &mhi_telit_fe990a_info },
610 { PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0308),
611 .driver_data = (kernel_ulong_t) &mhi_qcom_sdx65_info },
612 { PCI_DEVICE(PCI_VENDOR_ID_QUECTEL, 0x1001), /* EM120R-GL (sdx24) */
613 .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info },
614 { PCI_DEVICE(PCI_VENDOR_ID_QUECTEL, 0x1002), /* EM160R-GL (sdx24) */
615 .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info },
616 /* RM520N-GL (sdx6x), eSIM */
617 { PCI_DEVICE(PCI_VENDOR_ID_QUECTEL, 0x1004),
618 .driver_data = (kernel_ulong_t) &mhi_quectel_rm5xx_info },
619 /* RM520N-GL (sdx6x), Lenovo variant */
620 { PCI_DEVICE(PCI_VENDOR_ID_QUECTEL, 0x1007),
621 .driver_data = (kernel_ulong_t) &mhi_quectel_rm5xx_info },
622 { PCI_DEVICE(PCI_VENDOR_ID_QUECTEL, 0x100d), /* EM160R-GL (sdx24) */
623 .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info },
624 { PCI_DEVICE(PCI_VENDOR_ID_QUECTEL, 0x2001), /* EM120R-GL for FCCL (sdx24) */
625 .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info },
626 /* T99W175 (sdx55), Both for eSIM and Non-eSIM */
627 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0ab),
628 .driver_data = (kernel_ulong_t) &mhi_foxconn_sdx55_info },
629 /* DW5930e (sdx55), With eSIM, It's also T99W175 */
630 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0b0),
631 .driver_data = (kernel_ulong_t) &mhi_foxconn_sdx55_info },
632 /* DW5930e (sdx55), Non-eSIM, It's also T99W175 */
633 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0b1),
634 .driver_data = (kernel_ulong_t) &mhi_foxconn_sdx55_info },
635 /* T99W175 (sdx55), Based on Qualcomm new baseline */
636 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0bf),
637 .driver_data = (kernel_ulong_t) &mhi_foxconn_sdx55_info },
638 /* T99W175 (sdx55) */
639 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0c3),
640 .driver_data = (kernel_ulong_t) &mhi_foxconn_sdx55_info },
641 /* T99W368 (sdx65) */
642 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0d8),
643 .driver_data = (kernel_ulong_t) &mhi_foxconn_sdx65_info },
644 /* T99W373 (sdx62) */
645 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0d9),
646 .driver_data = (kernel_ulong_t) &mhi_foxconn_sdx65_info },
647 /* T99W510 (sdx24), variant 1 */
648 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0f0),
649 .driver_data = (kernel_ulong_t) &mhi_foxconn_sdx24_info },
650 /* T99W510 (sdx24), variant 2 */
651 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0f1),
652 .driver_data = (kernel_ulong_t) &mhi_foxconn_sdx24_info },
653 /* T99W510 (sdx24), variant 3 */
654 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0f2),
655 .driver_data = (kernel_ulong_t) &mhi_foxconn_sdx24_info },
656 /* DW5932e-eSIM (sdx62), With eSIM */
657 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0f5),
658 .driver_data = (kernel_ulong_t) &mhi_foxconn_sdx65_info },
659 /* DW5932e (sdx62), Non-eSIM */
660 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0f9),
661 .driver_data = (kernel_ulong_t) &mhi_foxconn_sdx65_info },
662 /* MV31-W (Cinterion) */
663 { PCI_DEVICE(PCI_VENDOR_ID_THALES, 0x00b3),
664 .driver_data = (kernel_ulong_t) &mhi_mv31_info },
665 /* MV31-W (Cinterion), based on new baseline */
666 { PCI_DEVICE(PCI_VENDOR_ID_THALES, 0x00b4),
667 .driver_data = (kernel_ulong_t) &mhi_mv31_info },
668 /* MV32-WA (Cinterion) */
669 { PCI_DEVICE(PCI_VENDOR_ID_THALES, 0x00ba),
670 .driver_data = (kernel_ulong_t) &mhi_mv32_info },
671 /* MV32-WB (Cinterion) */
672 { PCI_DEVICE(PCI_VENDOR_ID_THALES, 0x00bb),
673 .driver_data = (kernel_ulong_t) &mhi_mv32_info },
674 /* T99W175 (sdx55), HP variant */
675 { PCI_DEVICE(0x03f0, 0x0a6c),
676 .driver_data = (kernel_ulong_t) &mhi_foxconn_sdx55_info },
677 { }
678 };
679 MODULE_DEVICE_TABLE(pci, mhi_pci_id_table);
680
681 enum mhi_pci_device_status {
682 MHI_PCI_DEV_STARTED,
683 MHI_PCI_DEV_SUSPENDED,
684 };
685
686 struct mhi_pci_device {
687 struct mhi_controller mhi_cntrl;
688 struct pci_saved_state *pci_state;
689 struct work_struct recovery_work;
690 struct timer_list health_check_timer;
691 unsigned long status;
692 };
693
mhi_pci_read_reg(struct mhi_controller * mhi_cntrl,void __iomem * addr,u32 * out)694 static int mhi_pci_read_reg(struct mhi_controller *mhi_cntrl,
695 void __iomem *addr, u32 *out)
696 {
697 *out = readl(addr);
698 return 0;
699 }
700
mhi_pci_write_reg(struct mhi_controller * mhi_cntrl,void __iomem * addr,u32 val)701 static void mhi_pci_write_reg(struct mhi_controller *mhi_cntrl,
702 void __iomem *addr, u32 val)
703 {
704 writel(val, addr);
705 }
706
mhi_pci_status_cb(struct mhi_controller * mhi_cntrl,enum mhi_callback cb)707 static void mhi_pci_status_cb(struct mhi_controller *mhi_cntrl,
708 enum mhi_callback cb)
709 {
710 struct pci_dev *pdev = to_pci_dev(mhi_cntrl->cntrl_dev);
711
712 /* Nothing to do for now */
713 switch (cb) {
714 case MHI_CB_FATAL_ERROR:
715 case MHI_CB_SYS_ERROR:
716 dev_warn(&pdev->dev, "firmware crashed (%u)\n", cb);
717 pm_runtime_forbid(&pdev->dev);
718 break;
719 case MHI_CB_EE_MISSION_MODE:
720 pm_runtime_allow(&pdev->dev);
721 break;
722 default:
723 break;
724 }
725 }
726
mhi_pci_wake_get_nop(struct mhi_controller * mhi_cntrl,bool force)727 static void mhi_pci_wake_get_nop(struct mhi_controller *mhi_cntrl, bool force)
728 {
729 /* no-op */
730 }
731
mhi_pci_wake_put_nop(struct mhi_controller * mhi_cntrl,bool override)732 static void mhi_pci_wake_put_nop(struct mhi_controller *mhi_cntrl, bool override)
733 {
734 /* no-op */
735 }
736
mhi_pci_wake_toggle_nop(struct mhi_controller * mhi_cntrl)737 static void mhi_pci_wake_toggle_nop(struct mhi_controller *mhi_cntrl)
738 {
739 /* no-op */
740 }
741
mhi_pci_is_alive(struct mhi_controller * mhi_cntrl)742 static bool mhi_pci_is_alive(struct mhi_controller *mhi_cntrl)
743 {
744 struct pci_dev *pdev = to_pci_dev(mhi_cntrl->cntrl_dev);
745 u16 vendor = 0;
746
747 if (pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor))
748 return false;
749
750 if (vendor == (u16) ~0 || vendor == 0)
751 return false;
752
753 return true;
754 }
755
mhi_pci_claim(struct mhi_controller * mhi_cntrl,unsigned int bar_num,u64 dma_mask)756 static int mhi_pci_claim(struct mhi_controller *mhi_cntrl,
757 unsigned int bar_num, u64 dma_mask)
758 {
759 struct pci_dev *pdev = to_pci_dev(mhi_cntrl->cntrl_dev);
760 int err;
761
762 err = pci_assign_resource(pdev, bar_num);
763 if (err)
764 return err;
765
766 err = pcim_enable_device(pdev);
767 if (err) {
768 dev_err(&pdev->dev, "failed to enable pci device: %d\n", err);
769 return err;
770 }
771
772 err = pcim_iomap_regions(pdev, 1 << bar_num, pci_name(pdev));
773 if (err) {
774 dev_err(&pdev->dev, "failed to map pci region: %d\n", err);
775 return err;
776 }
777 mhi_cntrl->regs = pcim_iomap_table(pdev)[bar_num];
778 mhi_cntrl->reg_len = pci_resource_len(pdev, bar_num);
779
780 err = dma_set_mask_and_coherent(&pdev->dev, dma_mask);
781 if (err) {
782 dev_err(&pdev->dev, "Cannot set proper DMA mask\n");
783 return err;
784 }
785
786 pci_set_master(pdev);
787
788 return 0;
789 }
790
mhi_pci_get_irqs(struct mhi_controller * mhi_cntrl,const struct mhi_controller_config * mhi_cntrl_config)791 static int mhi_pci_get_irqs(struct mhi_controller *mhi_cntrl,
792 const struct mhi_controller_config *mhi_cntrl_config)
793 {
794 struct pci_dev *pdev = to_pci_dev(mhi_cntrl->cntrl_dev);
795 int nr_vectors, i;
796 int *irq;
797
798 /*
799 * Alloc one MSI vector for BHI + one vector per event ring, ideally...
800 * No explicit pci_free_irq_vectors required, done by pcim_release.
801 */
802 mhi_cntrl->nr_irqs = 1 + mhi_cntrl_config->num_events;
803
804 nr_vectors = pci_alloc_irq_vectors(pdev, 1, mhi_cntrl->nr_irqs, PCI_IRQ_MSI);
805 if (nr_vectors < 0) {
806 dev_err(&pdev->dev, "Error allocating MSI vectors %d\n",
807 nr_vectors);
808 return nr_vectors;
809 }
810
811 if (nr_vectors < mhi_cntrl->nr_irqs) {
812 dev_warn(&pdev->dev, "using shared MSI\n");
813
814 /* Patch msi vectors, use only one (shared) */
815 for (i = 0; i < mhi_cntrl_config->num_events; i++)
816 mhi_cntrl_config->event_cfg[i].irq = 0;
817 mhi_cntrl->nr_irqs = 1;
818 }
819
820 irq = devm_kcalloc(&pdev->dev, mhi_cntrl->nr_irqs, sizeof(int), GFP_KERNEL);
821 if (!irq)
822 return -ENOMEM;
823
824 for (i = 0; i < mhi_cntrl->nr_irqs; i++) {
825 int vector = i >= nr_vectors ? (nr_vectors - 1) : i;
826
827 irq[i] = pci_irq_vector(pdev, vector);
828 }
829
830 mhi_cntrl->irq = irq;
831
832 return 0;
833 }
834
mhi_pci_runtime_get(struct mhi_controller * mhi_cntrl)835 static int mhi_pci_runtime_get(struct mhi_controller *mhi_cntrl)
836 {
837 /* The runtime_get() MHI callback means:
838 * Do whatever is requested to leave M3.
839 */
840 return pm_runtime_get(mhi_cntrl->cntrl_dev);
841 }
842
mhi_pci_runtime_put(struct mhi_controller * mhi_cntrl)843 static void mhi_pci_runtime_put(struct mhi_controller *mhi_cntrl)
844 {
845 /* The runtime_put() MHI callback means:
846 * Device can be moved in M3 state.
847 */
848 pm_runtime_mark_last_busy(mhi_cntrl->cntrl_dev);
849 pm_runtime_put(mhi_cntrl->cntrl_dev);
850 }
851
mhi_pci_recovery_work(struct work_struct * work)852 static void mhi_pci_recovery_work(struct work_struct *work)
853 {
854 struct mhi_pci_device *mhi_pdev = container_of(work, struct mhi_pci_device,
855 recovery_work);
856 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl;
857 struct pci_dev *pdev = to_pci_dev(mhi_cntrl->cntrl_dev);
858 int err;
859
860 dev_warn(&pdev->dev, "device recovery started\n");
861
862 del_timer(&mhi_pdev->health_check_timer);
863 pm_runtime_forbid(&pdev->dev);
864
865 /* Clean up MHI state */
866 if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) {
867 mhi_power_down(mhi_cntrl, false);
868 mhi_unprepare_after_power_down(mhi_cntrl);
869 }
870
871 pci_set_power_state(pdev, PCI_D0);
872 pci_load_saved_state(pdev, mhi_pdev->pci_state);
873 pci_restore_state(pdev);
874
875 if (!mhi_pci_is_alive(mhi_cntrl))
876 goto err_try_reset;
877
878 err = mhi_prepare_for_power_up(mhi_cntrl);
879 if (err)
880 goto err_try_reset;
881
882 err = mhi_sync_power_up(mhi_cntrl);
883 if (err)
884 goto err_unprepare;
885
886 dev_dbg(&pdev->dev, "Recovery completed\n");
887
888 set_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status);
889 mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD);
890 return;
891
892 err_unprepare:
893 mhi_unprepare_after_power_down(mhi_cntrl);
894 err_try_reset:
895 if (pci_reset_function(pdev))
896 dev_err(&pdev->dev, "Recovery failed\n");
897 }
898
health_check(struct timer_list * t)899 static void health_check(struct timer_list *t)
900 {
901 struct mhi_pci_device *mhi_pdev = from_timer(mhi_pdev, t, health_check_timer);
902 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl;
903
904 if (!test_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status) ||
905 test_bit(MHI_PCI_DEV_SUSPENDED, &mhi_pdev->status))
906 return;
907
908 if (!mhi_pci_is_alive(mhi_cntrl)) {
909 dev_err(mhi_cntrl->cntrl_dev, "Device died\n");
910 queue_work(system_long_wq, &mhi_pdev->recovery_work);
911 return;
912 }
913
914 /* reschedule in two seconds */
915 mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD);
916 }
917
mhi_pci_probe(struct pci_dev * pdev,const struct pci_device_id * id)918 static int mhi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
919 {
920 const struct mhi_pci_dev_info *info = (struct mhi_pci_dev_info *) id->driver_data;
921 const struct mhi_controller_config *mhi_cntrl_config;
922 struct mhi_pci_device *mhi_pdev;
923 struct mhi_controller *mhi_cntrl;
924 int err;
925
926 dev_info(&pdev->dev, "MHI PCI device found: %s\n", info->name);
927
928 /* mhi_pdev.mhi_cntrl must be zero-initialized */
929 mhi_pdev = devm_kzalloc(&pdev->dev, sizeof(*mhi_pdev), GFP_KERNEL);
930 if (!mhi_pdev)
931 return -ENOMEM;
932
933 INIT_WORK(&mhi_pdev->recovery_work, mhi_pci_recovery_work);
934 timer_setup(&mhi_pdev->health_check_timer, health_check, 0);
935
936 mhi_cntrl_config = info->config;
937 mhi_cntrl = &mhi_pdev->mhi_cntrl;
938
939 mhi_cntrl->cntrl_dev = &pdev->dev;
940 mhi_cntrl->iova_start = 0;
941 mhi_cntrl->iova_stop = (dma_addr_t)DMA_BIT_MASK(info->dma_data_width);
942 mhi_cntrl->fw_image = info->fw;
943 mhi_cntrl->edl_image = info->edl;
944
945 mhi_cntrl->read_reg = mhi_pci_read_reg;
946 mhi_cntrl->write_reg = mhi_pci_write_reg;
947 mhi_cntrl->status_cb = mhi_pci_status_cb;
948 mhi_cntrl->runtime_get = mhi_pci_runtime_get;
949 mhi_cntrl->runtime_put = mhi_pci_runtime_put;
950 mhi_cntrl->mru = info->mru_default;
951
952 if (info->sideband_wake) {
953 mhi_cntrl->wake_get = mhi_pci_wake_get_nop;
954 mhi_cntrl->wake_put = mhi_pci_wake_put_nop;
955 mhi_cntrl->wake_toggle = mhi_pci_wake_toggle_nop;
956 }
957
958 err = mhi_pci_claim(mhi_cntrl, info->bar_num, DMA_BIT_MASK(info->dma_data_width));
959 if (err)
960 return err;
961
962 err = mhi_pci_get_irqs(mhi_cntrl, mhi_cntrl_config);
963 if (err)
964 return err;
965
966 pci_set_drvdata(pdev, mhi_pdev);
967
968 /* Have stored pci confspace at hand for restore in sudden PCI error.
969 * cache the state locally and discard the PCI core one.
970 */
971 pci_save_state(pdev);
972 mhi_pdev->pci_state = pci_store_saved_state(pdev);
973 pci_load_saved_state(pdev, NULL);
974
975 err = mhi_register_controller(mhi_cntrl, mhi_cntrl_config);
976 if (err)
977 return err;
978
979 /* MHI bus does not power up the controller by default */
980 err = mhi_prepare_for_power_up(mhi_cntrl);
981 if (err) {
982 dev_err(&pdev->dev, "failed to prepare MHI controller\n");
983 goto err_unregister;
984 }
985
986 err = mhi_sync_power_up(mhi_cntrl);
987 if (err) {
988 dev_err(&pdev->dev, "failed to power up MHI controller\n");
989 goto err_unprepare;
990 }
991
992 set_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status);
993
994 /* start health check */
995 mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD);
996
997 /* Only allow runtime-suspend if PME capable (for wakeup) */
998 if (pci_pme_capable(pdev, PCI_D3hot)) {
999 pm_runtime_set_autosuspend_delay(&pdev->dev, 2000);
1000 pm_runtime_use_autosuspend(&pdev->dev);
1001 pm_runtime_mark_last_busy(&pdev->dev);
1002 pm_runtime_put_noidle(&pdev->dev);
1003 }
1004
1005 return 0;
1006
1007 err_unprepare:
1008 mhi_unprepare_after_power_down(mhi_cntrl);
1009 err_unregister:
1010 mhi_unregister_controller(mhi_cntrl);
1011
1012 return err;
1013 }
1014
mhi_pci_remove(struct pci_dev * pdev)1015 static void mhi_pci_remove(struct pci_dev *pdev)
1016 {
1017 struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev);
1018 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl;
1019
1020 del_timer_sync(&mhi_pdev->health_check_timer);
1021 cancel_work_sync(&mhi_pdev->recovery_work);
1022
1023 if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) {
1024 mhi_power_down(mhi_cntrl, true);
1025 mhi_unprepare_after_power_down(mhi_cntrl);
1026 }
1027
1028 /* balancing probe put_noidle */
1029 if (pci_pme_capable(pdev, PCI_D3hot))
1030 pm_runtime_get_noresume(&pdev->dev);
1031
1032 mhi_unregister_controller(mhi_cntrl);
1033 }
1034
mhi_pci_shutdown(struct pci_dev * pdev)1035 static void mhi_pci_shutdown(struct pci_dev *pdev)
1036 {
1037 mhi_pci_remove(pdev);
1038 pci_set_power_state(pdev, PCI_D3hot);
1039 }
1040
mhi_pci_reset_prepare(struct pci_dev * pdev)1041 static void mhi_pci_reset_prepare(struct pci_dev *pdev)
1042 {
1043 struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev);
1044 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl;
1045
1046 dev_info(&pdev->dev, "reset\n");
1047
1048 del_timer(&mhi_pdev->health_check_timer);
1049
1050 /* Clean up MHI state */
1051 if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) {
1052 mhi_power_down(mhi_cntrl, false);
1053 mhi_unprepare_after_power_down(mhi_cntrl);
1054 }
1055
1056 /* cause internal device reset */
1057 mhi_soc_reset(mhi_cntrl);
1058
1059 /* Be sure device reset has been executed */
1060 msleep(MHI_POST_RESET_DELAY_MS);
1061 }
1062
mhi_pci_reset_done(struct pci_dev * pdev)1063 static void mhi_pci_reset_done(struct pci_dev *pdev)
1064 {
1065 struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev);
1066 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl;
1067 int err;
1068
1069 /* Restore initial known working PCI state */
1070 pci_load_saved_state(pdev, mhi_pdev->pci_state);
1071 pci_restore_state(pdev);
1072
1073 /* Is device status available ? */
1074 if (!mhi_pci_is_alive(mhi_cntrl)) {
1075 dev_err(&pdev->dev, "reset failed\n");
1076 return;
1077 }
1078
1079 err = mhi_prepare_for_power_up(mhi_cntrl);
1080 if (err) {
1081 dev_err(&pdev->dev, "failed to prepare MHI controller\n");
1082 return;
1083 }
1084
1085 err = mhi_sync_power_up(mhi_cntrl);
1086 if (err) {
1087 dev_err(&pdev->dev, "failed to power up MHI controller\n");
1088 mhi_unprepare_after_power_down(mhi_cntrl);
1089 return;
1090 }
1091
1092 set_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status);
1093 mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD);
1094 }
1095
mhi_pci_error_detected(struct pci_dev * pdev,pci_channel_state_t state)1096 static pci_ers_result_t mhi_pci_error_detected(struct pci_dev *pdev,
1097 pci_channel_state_t state)
1098 {
1099 struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev);
1100 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl;
1101
1102 dev_err(&pdev->dev, "PCI error detected, state = %u\n", state);
1103
1104 if (state == pci_channel_io_perm_failure)
1105 return PCI_ERS_RESULT_DISCONNECT;
1106
1107 /* Clean up MHI state */
1108 if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) {
1109 mhi_power_down(mhi_cntrl, false);
1110 mhi_unprepare_after_power_down(mhi_cntrl);
1111 } else {
1112 /* Nothing to do */
1113 return PCI_ERS_RESULT_RECOVERED;
1114 }
1115
1116 pci_disable_device(pdev);
1117
1118 return PCI_ERS_RESULT_NEED_RESET;
1119 }
1120
mhi_pci_slot_reset(struct pci_dev * pdev)1121 static pci_ers_result_t mhi_pci_slot_reset(struct pci_dev *pdev)
1122 {
1123 if (pci_enable_device(pdev)) {
1124 dev_err(&pdev->dev, "Cannot re-enable PCI device after reset.\n");
1125 return PCI_ERS_RESULT_DISCONNECT;
1126 }
1127
1128 return PCI_ERS_RESULT_RECOVERED;
1129 }
1130
mhi_pci_io_resume(struct pci_dev * pdev)1131 static void mhi_pci_io_resume(struct pci_dev *pdev)
1132 {
1133 struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev);
1134
1135 dev_err(&pdev->dev, "PCI slot reset done\n");
1136
1137 queue_work(system_long_wq, &mhi_pdev->recovery_work);
1138 }
1139
1140 static const struct pci_error_handlers mhi_pci_err_handler = {
1141 .error_detected = mhi_pci_error_detected,
1142 .slot_reset = mhi_pci_slot_reset,
1143 .resume = mhi_pci_io_resume,
1144 .reset_prepare = mhi_pci_reset_prepare,
1145 .reset_done = mhi_pci_reset_done,
1146 };
1147
mhi_pci_runtime_suspend(struct device * dev)1148 static int __maybe_unused mhi_pci_runtime_suspend(struct device *dev)
1149 {
1150 struct pci_dev *pdev = to_pci_dev(dev);
1151 struct mhi_pci_device *mhi_pdev = dev_get_drvdata(dev);
1152 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl;
1153 int err;
1154
1155 if (test_and_set_bit(MHI_PCI_DEV_SUSPENDED, &mhi_pdev->status))
1156 return 0;
1157
1158 del_timer(&mhi_pdev->health_check_timer);
1159 cancel_work_sync(&mhi_pdev->recovery_work);
1160
1161 if (!test_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status) ||
1162 mhi_cntrl->ee != MHI_EE_AMSS)
1163 goto pci_suspend; /* Nothing to do at MHI level */
1164
1165 /* Transition to M3 state */
1166 err = mhi_pm_suspend(mhi_cntrl);
1167 if (err) {
1168 dev_err(&pdev->dev, "failed to suspend device: %d\n", err);
1169 clear_bit(MHI_PCI_DEV_SUSPENDED, &mhi_pdev->status);
1170 return -EBUSY;
1171 }
1172
1173 pci_suspend:
1174 pci_disable_device(pdev);
1175 pci_wake_from_d3(pdev, true);
1176
1177 return 0;
1178 }
1179
mhi_pci_runtime_resume(struct device * dev)1180 static int __maybe_unused mhi_pci_runtime_resume(struct device *dev)
1181 {
1182 struct pci_dev *pdev = to_pci_dev(dev);
1183 struct mhi_pci_device *mhi_pdev = dev_get_drvdata(dev);
1184 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl;
1185 int err;
1186
1187 if (!test_and_clear_bit(MHI_PCI_DEV_SUSPENDED, &mhi_pdev->status))
1188 return 0;
1189
1190 err = pci_enable_device(pdev);
1191 if (err)
1192 goto err_recovery;
1193
1194 pci_set_master(pdev);
1195 pci_wake_from_d3(pdev, false);
1196
1197 if (!test_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status) ||
1198 mhi_cntrl->ee != MHI_EE_AMSS)
1199 return 0; /* Nothing to do at MHI level */
1200
1201 /* Exit M3, transition to M0 state */
1202 err = mhi_pm_resume(mhi_cntrl);
1203 if (err) {
1204 dev_err(&pdev->dev, "failed to resume device: %d\n", err);
1205 goto err_recovery;
1206 }
1207
1208 /* Resume health check */
1209 mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD);
1210
1211 /* It can be a remote wakeup (no mhi runtime_get), update access time */
1212 pm_runtime_mark_last_busy(dev);
1213
1214 return 0;
1215
1216 err_recovery:
1217 /* Do not fail to not mess up our PCI device state, the device likely
1218 * lost power (d3cold) and we simply need to reset it from the recovery
1219 * procedure, trigger the recovery asynchronously to prevent system
1220 * suspend exit delaying.
1221 */
1222 queue_work(system_long_wq, &mhi_pdev->recovery_work);
1223 pm_runtime_mark_last_busy(dev);
1224
1225 return 0;
1226 }
1227
mhi_pci_suspend(struct device * dev)1228 static int __maybe_unused mhi_pci_suspend(struct device *dev)
1229 {
1230 pm_runtime_disable(dev);
1231 return mhi_pci_runtime_suspend(dev);
1232 }
1233
mhi_pci_resume(struct device * dev)1234 static int __maybe_unused mhi_pci_resume(struct device *dev)
1235 {
1236 int ret;
1237
1238 /* Depending the platform, device may have lost power (d3cold), we need
1239 * to resume it now to check its state and recover when necessary.
1240 */
1241 ret = mhi_pci_runtime_resume(dev);
1242 pm_runtime_enable(dev);
1243
1244 return ret;
1245 }
1246
mhi_pci_freeze(struct device * dev)1247 static int __maybe_unused mhi_pci_freeze(struct device *dev)
1248 {
1249 struct mhi_pci_device *mhi_pdev = dev_get_drvdata(dev);
1250 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl;
1251
1252 /* We want to stop all operations, hibernation does not guarantee that
1253 * device will be in the same state as before freezing, especially if
1254 * the intermediate restore kernel reinitializes MHI device with new
1255 * context.
1256 */
1257 flush_work(&mhi_pdev->recovery_work);
1258 if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) {
1259 mhi_power_down(mhi_cntrl, true);
1260 mhi_unprepare_after_power_down(mhi_cntrl);
1261 }
1262
1263 return 0;
1264 }
1265
mhi_pci_restore(struct device * dev)1266 static int __maybe_unused mhi_pci_restore(struct device *dev)
1267 {
1268 struct mhi_pci_device *mhi_pdev = dev_get_drvdata(dev);
1269
1270 /* Reinitialize the device */
1271 queue_work(system_long_wq, &mhi_pdev->recovery_work);
1272
1273 return 0;
1274 }
1275
1276 static const struct dev_pm_ops mhi_pci_pm_ops = {
1277 SET_RUNTIME_PM_OPS(mhi_pci_runtime_suspend, mhi_pci_runtime_resume, NULL)
1278 #ifdef CONFIG_PM_SLEEP
1279 .suspend = mhi_pci_suspend,
1280 .resume = mhi_pci_resume,
1281 .freeze = mhi_pci_freeze,
1282 .thaw = mhi_pci_restore,
1283 .poweroff = mhi_pci_freeze,
1284 .restore = mhi_pci_restore,
1285 #endif
1286 };
1287
1288 static struct pci_driver mhi_pci_driver = {
1289 .name = "mhi-pci-generic",
1290 .id_table = mhi_pci_id_table,
1291 .probe = mhi_pci_probe,
1292 .remove = mhi_pci_remove,
1293 .shutdown = mhi_pci_shutdown,
1294 .err_handler = &mhi_pci_err_handler,
1295 .driver.pm = &mhi_pci_pm_ops
1296 };
1297 module_pci_driver(mhi_pci_driver);
1298
1299 MODULE_AUTHOR("Loic Poulain <loic.poulain@linaro.org>");
1300 MODULE_DESCRIPTION("Modem Host Interface (MHI) PCI controller driver");
1301 MODULE_LICENSE("GPL");
1302