1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2021 Linaro Ltd.
4 * Author: Sam Protsenko <semen.protsenko@linaro.org>
5 *
6 * Common Clock Framework support for Exynos850 SoC.
7 */
8
9 #include <linux/clk.h>
10 #include <linux/clk-provider.h>
11 #include <linux/of.h>
12 #include <linux/platform_device.h>
13
14 #include <dt-bindings/clock/exynos850.h>
15
16 #include "clk.h"
17 #include "clk-exynos-arm64.h"
18
19 /* NOTE: Must be equal to the last clock ID increased by one */
20 #define CLKS_NR_TOP (CLK_DOUT_G3D_SWITCH + 1)
21 #define CLKS_NR_APM (CLK_GOUT_SYSREG_APM_PCLK + 1)
22 #define CLKS_NR_AUD (CLK_GOUT_AUD_CMU_AUD_PCLK + 1)
23 #define CLKS_NR_CMGP (CLK_GOUT_SYSREG_CMGP_PCLK + 1)
24 #define CLKS_NR_G3D (CLK_GOUT_G3D_SYSREG_PCLK + 1)
25 #define CLKS_NR_HSI (CLK_GOUT_HSI_CMU_HSI_PCLK + 1)
26 #define CLKS_NR_IS (CLK_GOUT_IS_SYSREG_PCLK + 1)
27 #define CLKS_NR_MFCMSCL (CLK_GOUT_MFCMSCL_SYSREG_PCLK + 1)
28 #define CLKS_NR_PERI (CLK_GOUT_WDT1_PCLK + 1)
29 #define CLKS_NR_CORE (CLK_GOUT_SYSREG_CORE_PCLK + 1)
30 #define CLKS_NR_DPU (CLK_GOUT_DPU_SYSREG_PCLK + 1)
31
32 /* ---- CMU_TOP ------------------------------------------------------------- */
33
34 /* Register Offset definitions for CMU_TOP (0x120e0000) */
35 #define PLL_LOCKTIME_PLL_MMC 0x0000
36 #define PLL_LOCKTIME_PLL_SHARED0 0x0004
37 #define PLL_LOCKTIME_PLL_SHARED1 0x0008
38 #define PLL_CON0_PLL_MMC 0x0100
39 #define PLL_CON3_PLL_MMC 0x010c
40 #define PLL_CON0_PLL_SHARED0 0x0140
41 #define PLL_CON3_PLL_SHARED0 0x014c
42 #define PLL_CON0_PLL_SHARED1 0x0180
43 #define PLL_CON3_PLL_SHARED1 0x018c
44 #define CLK_CON_MUX_MUX_CLKCMU_APM_BUS 0x1000
45 #define CLK_CON_MUX_MUX_CLKCMU_AUD 0x1004
46 #define CLK_CON_MUX_MUX_CLKCMU_CORE_BUS 0x1014
47 #define CLK_CON_MUX_MUX_CLKCMU_CORE_CCI 0x1018
48 #define CLK_CON_MUX_MUX_CLKCMU_CORE_MMC_EMBD 0x101c
49 #define CLK_CON_MUX_MUX_CLKCMU_CORE_SSS 0x1020
50 #define CLK_CON_MUX_MUX_CLKCMU_DPU 0x1034
51 #define CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH 0x1038
52 #define CLK_CON_MUX_MUX_CLKCMU_HSI_BUS 0x103c
53 #define CLK_CON_MUX_MUX_CLKCMU_HSI_MMC_CARD 0x1040
54 #define CLK_CON_MUX_MUX_CLKCMU_HSI_USB20DRD 0x1044
55 #define CLK_CON_MUX_MUX_CLKCMU_IS_BUS 0x1048
56 #define CLK_CON_MUX_MUX_CLKCMU_IS_GDC 0x104c
57 #define CLK_CON_MUX_MUX_CLKCMU_IS_ITP 0x1050
58 #define CLK_CON_MUX_MUX_CLKCMU_IS_VRA 0x1054
59 #define CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_JPEG 0x1058
60 #define CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_M2M 0x105c
61 #define CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_MCSC 0x1060
62 #define CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_MFC 0x1064
63 #define CLK_CON_MUX_MUX_CLKCMU_PERI_BUS 0x1070
64 #define CLK_CON_MUX_MUX_CLKCMU_PERI_IP 0x1074
65 #define CLK_CON_MUX_MUX_CLKCMU_PERI_UART 0x1078
66 #define CLK_CON_DIV_CLKCMU_APM_BUS 0x180c
67 #define CLK_CON_DIV_CLKCMU_AUD 0x1810
68 #define CLK_CON_DIV_CLKCMU_CORE_BUS 0x1820
69 #define CLK_CON_DIV_CLKCMU_CORE_CCI 0x1824
70 #define CLK_CON_DIV_CLKCMU_CORE_MMC_EMBD 0x1828
71 #define CLK_CON_DIV_CLKCMU_CORE_SSS 0x182c
72 #define CLK_CON_DIV_CLKCMU_DPU 0x1840
73 #define CLK_CON_DIV_CLKCMU_G3D_SWITCH 0x1844
74 #define CLK_CON_DIV_CLKCMU_HSI_BUS 0x1848
75 #define CLK_CON_DIV_CLKCMU_HSI_MMC_CARD 0x184c
76 #define CLK_CON_DIV_CLKCMU_HSI_USB20DRD 0x1850
77 #define CLK_CON_DIV_CLKCMU_IS_BUS 0x1854
78 #define CLK_CON_DIV_CLKCMU_IS_GDC 0x1858
79 #define CLK_CON_DIV_CLKCMU_IS_ITP 0x185c
80 #define CLK_CON_DIV_CLKCMU_IS_VRA 0x1860
81 #define CLK_CON_DIV_CLKCMU_MFCMSCL_JPEG 0x1864
82 #define CLK_CON_DIV_CLKCMU_MFCMSCL_M2M 0x1868
83 #define CLK_CON_DIV_CLKCMU_MFCMSCL_MCSC 0x186c
84 #define CLK_CON_DIV_CLKCMU_MFCMSCL_MFC 0x1870
85 #define CLK_CON_DIV_CLKCMU_PERI_BUS 0x187c
86 #define CLK_CON_DIV_CLKCMU_PERI_IP 0x1880
87 #define CLK_CON_DIV_CLKCMU_PERI_UART 0x1884
88 #define CLK_CON_DIV_PLL_SHARED0_DIV2 0x188c
89 #define CLK_CON_DIV_PLL_SHARED0_DIV3 0x1890
90 #define CLK_CON_DIV_PLL_SHARED0_DIV4 0x1894
91 #define CLK_CON_DIV_PLL_SHARED1_DIV2 0x1898
92 #define CLK_CON_DIV_PLL_SHARED1_DIV3 0x189c
93 #define CLK_CON_DIV_PLL_SHARED1_DIV4 0x18a0
94 #define CLK_CON_GAT_GATE_CLKCMU_APM_BUS 0x2008
95 #define CLK_CON_GAT_GATE_CLKCMU_AUD 0x200c
96 #define CLK_CON_GAT_GATE_CLKCMU_CORE_BUS 0x201c
97 #define CLK_CON_GAT_GATE_CLKCMU_CORE_CCI 0x2020
98 #define CLK_CON_GAT_GATE_CLKCMU_CORE_MMC_EMBD 0x2024
99 #define CLK_CON_GAT_GATE_CLKCMU_CORE_SSS 0x2028
100 #define CLK_CON_GAT_GATE_CLKCMU_DPU 0x203c
101 #define CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH 0x2040
102 #define CLK_CON_GAT_GATE_CLKCMU_HSI_BUS 0x2044
103 #define CLK_CON_GAT_GATE_CLKCMU_HSI_MMC_CARD 0x2048
104 #define CLK_CON_GAT_GATE_CLKCMU_HSI_USB20DRD 0x204c
105 #define CLK_CON_GAT_GATE_CLKCMU_IS_BUS 0x2050
106 #define CLK_CON_GAT_GATE_CLKCMU_IS_GDC 0x2054
107 #define CLK_CON_GAT_GATE_CLKCMU_IS_ITP 0x2058
108 #define CLK_CON_GAT_GATE_CLKCMU_IS_VRA 0x205c
109 #define CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_JPEG 0x2060
110 #define CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_M2M 0x2064
111 #define CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_MCSC 0x2068
112 #define CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_MFC 0x206c
113 #define CLK_CON_GAT_GATE_CLKCMU_PERI_BUS 0x2080
114 #define CLK_CON_GAT_GATE_CLKCMU_PERI_IP 0x2084
115 #define CLK_CON_GAT_GATE_CLKCMU_PERI_UART 0x2088
116
117 static const unsigned long top_clk_regs[] __initconst = {
118 PLL_LOCKTIME_PLL_MMC,
119 PLL_LOCKTIME_PLL_SHARED0,
120 PLL_LOCKTIME_PLL_SHARED1,
121 PLL_CON0_PLL_MMC,
122 PLL_CON3_PLL_MMC,
123 PLL_CON0_PLL_SHARED0,
124 PLL_CON3_PLL_SHARED0,
125 PLL_CON0_PLL_SHARED1,
126 PLL_CON3_PLL_SHARED1,
127 CLK_CON_MUX_MUX_CLKCMU_APM_BUS,
128 CLK_CON_MUX_MUX_CLKCMU_AUD,
129 CLK_CON_MUX_MUX_CLKCMU_CORE_BUS,
130 CLK_CON_MUX_MUX_CLKCMU_CORE_CCI,
131 CLK_CON_MUX_MUX_CLKCMU_CORE_MMC_EMBD,
132 CLK_CON_MUX_MUX_CLKCMU_CORE_SSS,
133 CLK_CON_MUX_MUX_CLKCMU_DPU,
134 CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH,
135 CLK_CON_MUX_MUX_CLKCMU_HSI_BUS,
136 CLK_CON_MUX_MUX_CLKCMU_HSI_MMC_CARD,
137 CLK_CON_MUX_MUX_CLKCMU_HSI_USB20DRD,
138 CLK_CON_MUX_MUX_CLKCMU_IS_BUS,
139 CLK_CON_MUX_MUX_CLKCMU_IS_GDC,
140 CLK_CON_MUX_MUX_CLKCMU_IS_ITP,
141 CLK_CON_MUX_MUX_CLKCMU_IS_VRA,
142 CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_JPEG,
143 CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_M2M,
144 CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_MCSC,
145 CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_MFC,
146 CLK_CON_MUX_MUX_CLKCMU_PERI_BUS,
147 CLK_CON_MUX_MUX_CLKCMU_PERI_IP,
148 CLK_CON_MUX_MUX_CLKCMU_PERI_UART,
149 CLK_CON_DIV_CLKCMU_APM_BUS,
150 CLK_CON_DIV_CLKCMU_AUD,
151 CLK_CON_DIV_CLKCMU_CORE_BUS,
152 CLK_CON_DIV_CLKCMU_CORE_CCI,
153 CLK_CON_DIV_CLKCMU_CORE_MMC_EMBD,
154 CLK_CON_DIV_CLKCMU_CORE_SSS,
155 CLK_CON_DIV_CLKCMU_DPU,
156 CLK_CON_DIV_CLKCMU_G3D_SWITCH,
157 CLK_CON_DIV_CLKCMU_HSI_BUS,
158 CLK_CON_DIV_CLKCMU_HSI_MMC_CARD,
159 CLK_CON_DIV_CLKCMU_HSI_USB20DRD,
160 CLK_CON_DIV_CLKCMU_IS_BUS,
161 CLK_CON_DIV_CLKCMU_IS_GDC,
162 CLK_CON_DIV_CLKCMU_IS_ITP,
163 CLK_CON_DIV_CLKCMU_IS_VRA,
164 CLK_CON_DIV_CLKCMU_MFCMSCL_JPEG,
165 CLK_CON_DIV_CLKCMU_MFCMSCL_M2M,
166 CLK_CON_DIV_CLKCMU_MFCMSCL_MCSC,
167 CLK_CON_DIV_CLKCMU_MFCMSCL_MFC,
168 CLK_CON_DIV_CLKCMU_PERI_BUS,
169 CLK_CON_DIV_CLKCMU_PERI_IP,
170 CLK_CON_DIV_CLKCMU_PERI_UART,
171 CLK_CON_DIV_PLL_SHARED0_DIV2,
172 CLK_CON_DIV_PLL_SHARED0_DIV3,
173 CLK_CON_DIV_PLL_SHARED0_DIV4,
174 CLK_CON_DIV_PLL_SHARED1_DIV2,
175 CLK_CON_DIV_PLL_SHARED1_DIV3,
176 CLK_CON_DIV_PLL_SHARED1_DIV4,
177 CLK_CON_GAT_GATE_CLKCMU_APM_BUS,
178 CLK_CON_GAT_GATE_CLKCMU_AUD,
179 CLK_CON_GAT_GATE_CLKCMU_CORE_BUS,
180 CLK_CON_GAT_GATE_CLKCMU_CORE_CCI,
181 CLK_CON_GAT_GATE_CLKCMU_CORE_MMC_EMBD,
182 CLK_CON_GAT_GATE_CLKCMU_CORE_SSS,
183 CLK_CON_GAT_GATE_CLKCMU_DPU,
184 CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH,
185 CLK_CON_GAT_GATE_CLKCMU_HSI_BUS,
186 CLK_CON_GAT_GATE_CLKCMU_HSI_MMC_CARD,
187 CLK_CON_GAT_GATE_CLKCMU_HSI_USB20DRD,
188 CLK_CON_GAT_GATE_CLKCMU_IS_BUS,
189 CLK_CON_GAT_GATE_CLKCMU_IS_GDC,
190 CLK_CON_GAT_GATE_CLKCMU_IS_ITP,
191 CLK_CON_GAT_GATE_CLKCMU_IS_VRA,
192 CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_JPEG,
193 CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_M2M,
194 CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_MCSC,
195 CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_MFC,
196 CLK_CON_GAT_GATE_CLKCMU_PERI_BUS,
197 CLK_CON_GAT_GATE_CLKCMU_PERI_IP,
198 CLK_CON_GAT_GATE_CLKCMU_PERI_UART,
199 };
200
201 /*
202 * Do not provide PLL tables to core PLLs, as MANUAL_PLL_CTRL bit is not set
203 * for those PLLs by default, so set_rate operation would fail.
204 */
205 static const struct samsung_pll_clock top_pll_clks[] __initconst = {
206 /* CMU_TOP_PURECLKCOMP */
207 PLL(pll_0822x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk",
208 PLL_LOCKTIME_PLL_SHARED0, PLL_CON3_PLL_SHARED0,
209 NULL),
210 PLL(pll_0822x, CLK_FOUT_SHARED1_PLL, "fout_shared1_pll", "oscclk",
211 PLL_LOCKTIME_PLL_SHARED1, PLL_CON3_PLL_SHARED1,
212 NULL),
213 PLL(pll_0831x, CLK_FOUT_MMC_PLL, "fout_mmc_pll", "oscclk",
214 PLL_LOCKTIME_PLL_MMC, PLL_CON3_PLL_MMC, NULL),
215 };
216
217 /* List of parent clocks for Muxes in CMU_TOP */
218 PNAME(mout_shared0_pll_p) = { "oscclk", "fout_shared0_pll" };
219 PNAME(mout_shared1_pll_p) = { "oscclk", "fout_shared1_pll" };
220 PNAME(mout_mmc_pll_p) = { "oscclk", "fout_mmc_pll" };
221 /* List of parent clocks for Muxes in CMU_TOP: for CMU_APM */
222 PNAME(mout_clkcmu_apm_bus_p) = { "dout_shared0_div4", "pll_shared1_div4" };
223 /* List of parent clocks for Muxes in CMU_TOP: for CMU_AUD */
224 PNAME(mout_aud_p) = { "fout_shared1_pll", "dout_shared0_div2",
225 "dout_shared1_div2", "dout_shared0_div3" };
226 /* List of parent clocks for Muxes in CMU_TOP: for CMU_CORE */
227 PNAME(mout_core_bus_p) = { "dout_shared1_div2", "dout_shared0_div3",
228 "dout_shared1_div3", "dout_shared0_div4" };
229 PNAME(mout_core_cci_p) = { "dout_shared0_div2", "dout_shared1_div2",
230 "dout_shared0_div3", "dout_shared1_div3" };
231 PNAME(mout_core_mmc_embd_p) = { "oscclk", "dout_shared0_div2",
232 "dout_shared1_div2", "dout_shared0_div3",
233 "dout_shared1_div3", "mout_mmc_pll",
234 "oscclk", "oscclk" };
235 PNAME(mout_core_sss_p) = { "dout_shared0_div3", "dout_shared1_div3",
236 "dout_shared0_div4", "dout_shared1_div4" };
237 /* List of parent clocks for Muxes in CMU_TOP: for CMU_G3D */
238 PNAME(mout_g3d_switch_p) = { "dout_shared0_div2", "dout_shared1_div2",
239 "dout_shared0_div3", "dout_shared1_div3" };
240 /* List of parent clocks for Muxes in CMU_TOP: for CMU_HSI */
241 PNAME(mout_hsi_bus_p) = { "dout_shared0_div2", "dout_shared1_div2" };
242 PNAME(mout_hsi_mmc_card_p) = { "oscclk", "dout_shared0_div2",
243 "dout_shared1_div2", "dout_shared0_div3",
244 "dout_shared1_div3", "mout_mmc_pll",
245 "oscclk", "oscclk" };
246 PNAME(mout_hsi_usb20drd_p) = { "oscclk", "dout_shared0_div4",
247 "dout_shared1_div4", "oscclk" };
248 /* List of parent clocks for Muxes in CMU_TOP: for CMU_IS */
249 PNAME(mout_is_bus_p) = { "dout_shared0_div2", "dout_shared1_div2",
250 "dout_shared0_div3", "dout_shared1_div3" };
251 PNAME(mout_is_itp_p) = { "dout_shared0_div2", "dout_shared1_div2",
252 "dout_shared0_div3", "dout_shared1_div3" };
253 PNAME(mout_is_vra_p) = { "dout_shared0_div2", "dout_shared1_div2",
254 "dout_shared0_div3", "dout_shared1_div3" };
255 PNAME(mout_is_gdc_p) = { "dout_shared0_div2", "dout_shared1_div2",
256 "dout_shared0_div3", "dout_shared1_div3" };
257 /* List of parent clocks for Muxes in CMU_TOP: for CMU_MFCMSCL */
258 PNAME(mout_mfcmscl_mfc_p) = { "dout_shared1_div2", "dout_shared0_div3",
259 "dout_shared1_div3", "dout_shared0_div4" };
260 PNAME(mout_mfcmscl_m2m_p) = { "dout_shared1_div2", "dout_shared0_div3",
261 "dout_shared1_div3", "dout_shared0_div4" };
262 PNAME(mout_mfcmscl_mcsc_p) = { "dout_shared1_div2", "dout_shared0_div3",
263 "dout_shared1_div3", "dout_shared0_div4" };
264 PNAME(mout_mfcmscl_jpeg_p) = { "dout_shared0_div3", "dout_shared1_div3",
265 "dout_shared0_div4", "dout_shared1_div4" };
266 /* List of parent clocks for Muxes in CMU_TOP: for CMU_PERI */
267 PNAME(mout_peri_bus_p) = { "dout_shared0_div4", "dout_shared1_div4" };
268 PNAME(mout_peri_uart_p) = { "oscclk", "dout_shared0_div4",
269 "dout_shared1_div4", "oscclk" };
270 PNAME(mout_peri_ip_p) = { "oscclk", "dout_shared0_div4",
271 "dout_shared1_div4", "oscclk" };
272 /* List of parent clocks for Muxes in CMU_TOP: for CMU_DPU */
273 PNAME(mout_dpu_p) = { "dout_shared0_div3", "dout_shared1_div3",
274 "dout_shared0_div4", "dout_shared1_div4" };
275
276 static const struct samsung_mux_clock top_mux_clks[] __initconst = {
277 /* CMU_TOP_PURECLKCOMP */
278 MUX(CLK_MOUT_SHARED0_PLL, "mout_shared0_pll", mout_shared0_pll_p,
279 PLL_CON0_PLL_SHARED0, 4, 1),
280 MUX(CLK_MOUT_SHARED1_PLL, "mout_shared1_pll", mout_shared1_pll_p,
281 PLL_CON0_PLL_SHARED1, 4, 1),
282 MUX(CLK_MOUT_MMC_PLL, "mout_mmc_pll", mout_mmc_pll_p,
283 PLL_CON0_PLL_MMC, 4, 1),
284
285 /* APM */
286 MUX(CLK_MOUT_CLKCMU_APM_BUS, "mout_clkcmu_apm_bus",
287 mout_clkcmu_apm_bus_p, CLK_CON_MUX_MUX_CLKCMU_APM_BUS, 0, 1),
288
289 /* AUD */
290 MUX(CLK_MOUT_AUD, "mout_aud", mout_aud_p,
291 CLK_CON_MUX_MUX_CLKCMU_AUD, 0, 2),
292
293 /* CORE */
294 MUX(CLK_MOUT_CORE_BUS, "mout_core_bus", mout_core_bus_p,
295 CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 0, 2),
296 MUX(CLK_MOUT_CORE_CCI, "mout_core_cci", mout_core_cci_p,
297 CLK_CON_MUX_MUX_CLKCMU_CORE_CCI, 0, 2),
298 MUX(CLK_MOUT_CORE_MMC_EMBD, "mout_core_mmc_embd", mout_core_mmc_embd_p,
299 CLK_CON_MUX_MUX_CLKCMU_CORE_MMC_EMBD, 0, 3),
300 MUX(CLK_MOUT_CORE_SSS, "mout_core_sss", mout_core_sss_p,
301 CLK_CON_MUX_MUX_CLKCMU_CORE_SSS, 0, 2),
302
303 /* DPU */
304 MUX(CLK_MOUT_DPU, "mout_dpu", mout_dpu_p,
305 CLK_CON_MUX_MUX_CLKCMU_DPU, 0, 2),
306
307 /* G3D */
308 MUX(CLK_MOUT_G3D_SWITCH, "mout_g3d_switch", mout_g3d_switch_p,
309 CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH, 0, 2),
310
311 /* HSI */
312 MUX(CLK_MOUT_HSI_BUS, "mout_hsi_bus", mout_hsi_bus_p,
313 CLK_CON_MUX_MUX_CLKCMU_HSI_BUS, 0, 1),
314 MUX(CLK_MOUT_HSI_MMC_CARD, "mout_hsi_mmc_card", mout_hsi_mmc_card_p,
315 CLK_CON_MUX_MUX_CLKCMU_HSI_MMC_CARD, 0, 3),
316 MUX(CLK_MOUT_HSI_USB20DRD, "mout_hsi_usb20drd", mout_hsi_usb20drd_p,
317 CLK_CON_MUX_MUX_CLKCMU_HSI_USB20DRD, 0, 2),
318
319 /* IS */
320 MUX(CLK_MOUT_IS_BUS, "mout_is_bus", mout_is_bus_p,
321 CLK_CON_MUX_MUX_CLKCMU_IS_BUS, 0, 2),
322 MUX(CLK_MOUT_IS_ITP, "mout_is_itp", mout_is_itp_p,
323 CLK_CON_MUX_MUX_CLKCMU_IS_ITP, 0, 2),
324 MUX(CLK_MOUT_IS_VRA, "mout_is_vra", mout_is_vra_p,
325 CLK_CON_MUX_MUX_CLKCMU_IS_VRA, 0, 2),
326 MUX(CLK_MOUT_IS_GDC, "mout_is_gdc", mout_is_gdc_p,
327 CLK_CON_MUX_MUX_CLKCMU_IS_GDC, 0, 2),
328
329 /* MFCMSCL */
330 MUX(CLK_MOUT_MFCMSCL_MFC, "mout_mfcmscl_mfc", mout_mfcmscl_mfc_p,
331 CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_MFC, 0, 2),
332 MUX(CLK_MOUT_MFCMSCL_M2M, "mout_mfcmscl_m2m", mout_mfcmscl_m2m_p,
333 CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_M2M, 0, 2),
334 MUX(CLK_MOUT_MFCMSCL_MCSC, "mout_mfcmscl_mcsc", mout_mfcmscl_mcsc_p,
335 CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_MCSC, 0, 2),
336 MUX(CLK_MOUT_MFCMSCL_JPEG, "mout_mfcmscl_jpeg", mout_mfcmscl_jpeg_p,
337 CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_JPEG, 0, 2),
338
339 /* PERI */
340 MUX(CLK_MOUT_PERI_BUS, "mout_peri_bus", mout_peri_bus_p,
341 CLK_CON_MUX_MUX_CLKCMU_PERI_BUS, 0, 1),
342 MUX(CLK_MOUT_PERI_UART, "mout_peri_uart", mout_peri_uart_p,
343 CLK_CON_MUX_MUX_CLKCMU_PERI_UART, 0, 2),
344 MUX(CLK_MOUT_PERI_IP, "mout_peri_ip", mout_peri_ip_p,
345 CLK_CON_MUX_MUX_CLKCMU_PERI_IP, 0, 2),
346 };
347
348 static const struct samsung_div_clock top_div_clks[] __initconst = {
349 /* CMU_TOP_PURECLKCOMP */
350 DIV(CLK_DOUT_SHARED0_DIV3, "dout_shared0_div3", "mout_shared0_pll",
351 CLK_CON_DIV_PLL_SHARED0_DIV3, 0, 2),
352 DIV(CLK_DOUT_SHARED0_DIV2, "dout_shared0_div2", "mout_shared0_pll",
353 CLK_CON_DIV_PLL_SHARED0_DIV2, 0, 1),
354 DIV(CLK_DOUT_SHARED1_DIV3, "dout_shared1_div3", "mout_shared1_pll",
355 CLK_CON_DIV_PLL_SHARED1_DIV3, 0, 2),
356 DIV(CLK_DOUT_SHARED1_DIV2, "dout_shared1_div2", "mout_shared1_pll",
357 CLK_CON_DIV_PLL_SHARED1_DIV2, 0, 1),
358 DIV(CLK_DOUT_SHARED0_DIV4, "dout_shared0_div4", "dout_shared0_div2",
359 CLK_CON_DIV_PLL_SHARED0_DIV4, 0, 1),
360 DIV(CLK_DOUT_SHARED1_DIV4, "dout_shared1_div4", "dout_shared1_div2",
361 CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1),
362
363 /* APM */
364 DIV(CLK_DOUT_CLKCMU_APM_BUS, "dout_clkcmu_apm_bus",
365 "gout_clkcmu_apm_bus", CLK_CON_DIV_CLKCMU_APM_BUS, 0, 3),
366
367 /* AUD */
368 DIV(CLK_DOUT_AUD, "dout_aud", "gout_aud",
369 CLK_CON_DIV_CLKCMU_AUD, 0, 4),
370
371 /* CORE */
372 DIV(CLK_DOUT_CORE_BUS, "dout_core_bus", "gout_core_bus",
373 CLK_CON_DIV_CLKCMU_CORE_BUS, 0, 4),
374 DIV(CLK_DOUT_CORE_CCI, "dout_core_cci", "gout_core_cci",
375 CLK_CON_DIV_CLKCMU_CORE_CCI, 0, 4),
376 DIV(CLK_DOUT_CORE_MMC_EMBD, "dout_core_mmc_embd", "gout_core_mmc_embd",
377 CLK_CON_DIV_CLKCMU_CORE_MMC_EMBD, 0, 9),
378 DIV(CLK_DOUT_CORE_SSS, "dout_core_sss", "gout_core_sss",
379 CLK_CON_DIV_CLKCMU_CORE_SSS, 0, 4),
380
381 /* DPU */
382 DIV(CLK_DOUT_DPU, "dout_dpu", "gout_dpu",
383 CLK_CON_DIV_CLKCMU_DPU, 0, 4),
384
385 /* G3D */
386 DIV(CLK_DOUT_G3D_SWITCH, "dout_g3d_switch", "gout_g3d_switch",
387 CLK_CON_DIV_CLKCMU_G3D_SWITCH, 0, 3),
388
389 /* HSI */
390 DIV(CLK_DOUT_HSI_BUS, "dout_hsi_bus", "gout_hsi_bus",
391 CLK_CON_DIV_CLKCMU_HSI_BUS, 0, 4),
392 DIV(CLK_DOUT_HSI_MMC_CARD, "dout_hsi_mmc_card", "gout_hsi_mmc_card",
393 CLK_CON_DIV_CLKCMU_HSI_MMC_CARD, 0, 9),
394 DIV(CLK_DOUT_HSI_USB20DRD, "dout_hsi_usb20drd", "gout_hsi_usb20drd",
395 CLK_CON_DIV_CLKCMU_HSI_USB20DRD, 0, 4),
396
397 /* IS */
398 DIV(CLK_DOUT_IS_BUS, "dout_is_bus", "gout_is_bus",
399 CLK_CON_DIV_CLKCMU_IS_BUS, 0, 4),
400 DIV(CLK_DOUT_IS_ITP, "dout_is_itp", "gout_is_itp",
401 CLK_CON_DIV_CLKCMU_IS_ITP, 0, 4),
402 DIV(CLK_DOUT_IS_VRA, "dout_is_vra", "gout_is_vra",
403 CLK_CON_DIV_CLKCMU_IS_VRA, 0, 4),
404 DIV(CLK_DOUT_IS_GDC, "dout_is_gdc", "gout_is_gdc",
405 CLK_CON_DIV_CLKCMU_IS_GDC, 0, 4),
406
407 /* MFCMSCL */
408 DIV(CLK_DOUT_MFCMSCL_MFC, "dout_mfcmscl_mfc", "gout_mfcmscl_mfc",
409 CLK_CON_DIV_CLKCMU_MFCMSCL_MFC, 0, 4),
410 DIV(CLK_DOUT_MFCMSCL_M2M, "dout_mfcmscl_m2m", "gout_mfcmscl_m2m",
411 CLK_CON_DIV_CLKCMU_MFCMSCL_M2M, 0, 4),
412 DIV(CLK_DOUT_MFCMSCL_MCSC, "dout_mfcmscl_mcsc", "gout_mfcmscl_mcsc",
413 CLK_CON_DIV_CLKCMU_MFCMSCL_MCSC, 0, 4),
414 DIV(CLK_DOUT_MFCMSCL_JPEG, "dout_mfcmscl_jpeg", "gout_mfcmscl_jpeg",
415 CLK_CON_DIV_CLKCMU_MFCMSCL_JPEG, 0, 4),
416
417 /* PERI */
418 DIV(CLK_DOUT_PERI_BUS, "dout_peri_bus", "gout_peri_bus",
419 CLK_CON_DIV_CLKCMU_PERI_BUS, 0, 4),
420 DIV(CLK_DOUT_PERI_UART, "dout_peri_uart", "gout_peri_uart",
421 CLK_CON_DIV_CLKCMU_PERI_UART, 0, 4),
422 DIV(CLK_DOUT_PERI_IP, "dout_peri_ip", "gout_peri_ip",
423 CLK_CON_DIV_CLKCMU_PERI_IP, 0, 4),
424 };
425
426 static const struct samsung_gate_clock top_gate_clks[] __initconst = {
427 /* CORE */
428 GATE(CLK_GOUT_CORE_BUS, "gout_core_bus", "mout_core_bus",
429 CLK_CON_GAT_GATE_CLKCMU_CORE_BUS, 21, 0, 0),
430 GATE(CLK_GOUT_CORE_CCI, "gout_core_cci", "mout_core_cci",
431 CLK_CON_GAT_GATE_CLKCMU_CORE_CCI, 21, 0, 0),
432 GATE(CLK_GOUT_CORE_MMC_EMBD, "gout_core_mmc_embd", "mout_core_mmc_embd",
433 CLK_CON_GAT_GATE_CLKCMU_CORE_MMC_EMBD, 21, 0, 0),
434 GATE(CLK_GOUT_CORE_SSS, "gout_core_sss", "mout_core_sss",
435 CLK_CON_GAT_GATE_CLKCMU_CORE_SSS, 21, 0, 0),
436
437 /* APM */
438 GATE(CLK_GOUT_CLKCMU_APM_BUS, "gout_clkcmu_apm_bus",
439 "mout_clkcmu_apm_bus", CLK_CON_GAT_GATE_CLKCMU_APM_BUS, 21, 0, 0),
440
441 /* AUD */
442 GATE(CLK_GOUT_AUD, "gout_aud", "mout_aud",
443 CLK_CON_GAT_GATE_CLKCMU_AUD, 21, 0, 0),
444
445 /* DPU */
446 GATE(CLK_GOUT_DPU, "gout_dpu", "mout_dpu",
447 CLK_CON_GAT_GATE_CLKCMU_DPU, 21, 0, 0),
448
449 /* G3D */
450 GATE(CLK_GOUT_G3D_SWITCH, "gout_g3d_switch", "mout_g3d_switch",
451 CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH, 21, 0, 0),
452
453 /* HSI */
454 GATE(CLK_GOUT_HSI_BUS, "gout_hsi_bus", "mout_hsi_bus",
455 CLK_CON_GAT_GATE_CLKCMU_HSI_BUS, 21, 0, 0),
456 GATE(CLK_GOUT_HSI_MMC_CARD, "gout_hsi_mmc_card", "mout_hsi_mmc_card",
457 CLK_CON_GAT_GATE_CLKCMU_HSI_MMC_CARD, 21, 0, 0),
458 GATE(CLK_GOUT_HSI_USB20DRD, "gout_hsi_usb20drd", "mout_hsi_usb20drd",
459 CLK_CON_GAT_GATE_CLKCMU_HSI_USB20DRD, 21, 0, 0),
460
461 /* IS */
462 /* TODO: These clocks have to be always enabled to access CMU_IS regs */
463 GATE(CLK_GOUT_IS_BUS, "gout_is_bus", "mout_is_bus",
464 CLK_CON_GAT_GATE_CLKCMU_IS_BUS, 21, CLK_IS_CRITICAL, 0),
465 GATE(CLK_GOUT_IS_ITP, "gout_is_itp", "mout_is_itp",
466 CLK_CON_GAT_GATE_CLKCMU_IS_ITP, 21, CLK_IS_CRITICAL, 0),
467 GATE(CLK_GOUT_IS_VRA, "gout_is_vra", "mout_is_vra",
468 CLK_CON_GAT_GATE_CLKCMU_IS_VRA, 21, CLK_IS_CRITICAL, 0),
469 GATE(CLK_GOUT_IS_GDC, "gout_is_gdc", "mout_is_gdc",
470 CLK_CON_GAT_GATE_CLKCMU_IS_GDC, 21, CLK_IS_CRITICAL, 0),
471
472 /* MFCMSCL */
473 /* TODO: These have to be always enabled to access CMU_MFCMSCL regs */
474 GATE(CLK_GOUT_MFCMSCL_MFC, "gout_mfcmscl_mfc", "mout_mfcmscl_mfc",
475 CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_MFC, 21, CLK_IS_CRITICAL, 0),
476 GATE(CLK_GOUT_MFCMSCL_M2M, "gout_mfcmscl_m2m", "mout_mfcmscl_m2m",
477 CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_M2M, 21, CLK_IS_CRITICAL, 0),
478 GATE(CLK_GOUT_MFCMSCL_MCSC, "gout_mfcmscl_mcsc", "mout_mfcmscl_mcsc",
479 CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_MCSC, 21, CLK_IS_CRITICAL, 0),
480 GATE(CLK_GOUT_MFCMSCL_JPEG, "gout_mfcmscl_jpeg", "mout_mfcmscl_jpeg",
481 CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_JPEG, 21, CLK_IS_CRITICAL, 0),
482
483 /* PERI */
484 GATE(CLK_GOUT_PERI_BUS, "gout_peri_bus", "mout_peri_bus",
485 CLK_CON_GAT_GATE_CLKCMU_PERI_BUS, 21, 0, 0),
486 GATE(CLK_GOUT_PERI_UART, "gout_peri_uart", "mout_peri_uart",
487 CLK_CON_GAT_GATE_CLKCMU_PERI_UART, 21, 0, 0),
488 GATE(CLK_GOUT_PERI_IP, "gout_peri_ip", "mout_peri_ip",
489 CLK_CON_GAT_GATE_CLKCMU_PERI_IP, 21, 0, 0),
490 };
491
492 static const struct samsung_cmu_info top_cmu_info __initconst = {
493 .pll_clks = top_pll_clks,
494 .nr_pll_clks = ARRAY_SIZE(top_pll_clks),
495 .mux_clks = top_mux_clks,
496 .nr_mux_clks = ARRAY_SIZE(top_mux_clks),
497 .div_clks = top_div_clks,
498 .nr_div_clks = ARRAY_SIZE(top_div_clks),
499 .gate_clks = top_gate_clks,
500 .nr_gate_clks = ARRAY_SIZE(top_gate_clks),
501 .nr_clk_ids = CLKS_NR_TOP,
502 .clk_regs = top_clk_regs,
503 .nr_clk_regs = ARRAY_SIZE(top_clk_regs),
504 };
505
exynos850_cmu_top_init(struct device_node * np)506 static void __init exynos850_cmu_top_init(struct device_node *np)
507 {
508 exynos_arm64_register_cmu(NULL, np, &top_cmu_info);
509 }
510
511 /* Register CMU_TOP early, as it's a dependency for other early domains */
512 CLK_OF_DECLARE(exynos850_cmu_top, "samsung,exynos850-cmu-top",
513 exynos850_cmu_top_init);
514
515 /* ---- CMU_APM ------------------------------------------------------------- */
516
517 /* Register Offset definitions for CMU_APM (0x11800000) */
518 #define PLL_CON0_MUX_CLKCMU_APM_BUS_USER 0x0600
519 #define PLL_CON0_MUX_CLK_RCO_APM_I3C_USER 0x0610
520 #define PLL_CON0_MUX_CLK_RCO_APM_USER 0x0620
521 #define PLL_CON0_MUX_DLL_USER 0x0630
522 #define CLK_CON_MUX_MUX_CLKCMU_CHUB_BUS 0x1000
523 #define CLK_CON_MUX_MUX_CLK_APM_BUS 0x1004
524 #define CLK_CON_MUX_MUX_CLK_APM_I3C 0x1008
525 #define CLK_CON_DIV_CLKCMU_CHUB_BUS 0x1800
526 #define CLK_CON_DIV_DIV_CLK_APM_BUS 0x1804
527 #define CLK_CON_DIV_DIV_CLK_APM_I3C 0x1808
528 #define CLK_CON_GAT_CLKCMU_CMGP_BUS 0x2000
529 #define CLK_CON_GAT_GATE_CLKCMU_CHUB_BUS 0x2014
530 #define CLK_CON_GAT_GOUT_APM_APBIF_GPIO_ALIVE_PCLK 0x2018
531 #define CLK_CON_GAT_GOUT_APM_APBIF_PMU_ALIVE_PCLK 0x2020
532 #define CLK_CON_GAT_GOUT_APM_APBIF_RTC_PCLK 0x2024
533 #define CLK_CON_GAT_GOUT_APM_APBIF_TOP_RTC_PCLK 0x2028
534 #define CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_PCLK 0x2034
535 #define CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_SCLK 0x2038
536 #define CLK_CON_GAT_GOUT_APM_SPEEDY_APM_PCLK 0x20bc
537 #define CLK_CON_GAT_GOUT_APM_SYSREG_APM_PCLK 0x20c0
538
539 static const unsigned long apm_clk_regs[] __initconst = {
540 PLL_CON0_MUX_CLKCMU_APM_BUS_USER,
541 PLL_CON0_MUX_CLK_RCO_APM_I3C_USER,
542 PLL_CON0_MUX_CLK_RCO_APM_USER,
543 PLL_CON0_MUX_DLL_USER,
544 CLK_CON_MUX_MUX_CLKCMU_CHUB_BUS,
545 CLK_CON_MUX_MUX_CLK_APM_BUS,
546 CLK_CON_MUX_MUX_CLK_APM_I3C,
547 CLK_CON_DIV_CLKCMU_CHUB_BUS,
548 CLK_CON_DIV_DIV_CLK_APM_BUS,
549 CLK_CON_DIV_DIV_CLK_APM_I3C,
550 CLK_CON_GAT_CLKCMU_CMGP_BUS,
551 CLK_CON_GAT_GATE_CLKCMU_CHUB_BUS,
552 CLK_CON_GAT_GOUT_APM_APBIF_GPIO_ALIVE_PCLK,
553 CLK_CON_GAT_GOUT_APM_APBIF_PMU_ALIVE_PCLK,
554 CLK_CON_GAT_GOUT_APM_APBIF_RTC_PCLK,
555 CLK_CON_GAT_GOUT_APM_APBIF_TOP_RTC_PCLK,
556 CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_PCLK,
557 CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_SCLK,
558 CLK_CON_GAT_GOUT_APM_SPEEDY_APM_PCLK,
559 CLK_CON_GAT_GOUT_APM_SYSREG_APM_PCLK,
560 };
561
562 /* List of parent clocks for Muxes in CMU_APM */
563 PNAME(mout_apm_bus_user_p) = { "oscclk_rco_apm", "dout_clkcmu_apm_bus" };
564 PNAME(mout_rco_apm_i3c_user_p) = { "oscclk_rco_apm", "clk_rco_i3c_pmic" };
565 PNAME(mout_rco_apm_user_p) = { "oscclk_rco_apm", "clk_rco_apm__alv" };
566 PNAME(mout_dll_user_p) = { "oscclk_rco_apm", "clk_dll_dco" };
567 PNAME(mout_clkcmu_chub_bus_p) = { "mout_apm_bus_user", "mout_dll_user" };
568 PNAME(mout_apm_bus_p) = { "mout_rco_apm_user", "mout_apm_bus_user",
569 "mout_dll_user", "oscclk_rco_apm" };
570 PNAME(mout_apm_i3c_p) = { "dout_apm_i3c", "mout_rco_apm_i3c_user" };
571
572 static const struct samsung_fixed_rate_clock apm_fixed_clks[] __initconst = {
573 FRATE(CLK_RCO_I3C_PMIC, "clk_rco_i3c_pmic", NULL, 0, 491520000),
574 FRATE(OSCCLK_RCO_APM, "oscclk_rco_apm", NULL, 0, 24576000),
575 FRATE(CLK_RCO_APM__ALV, "clk_rco_apm__alv", NULL, 0, 49152000),
576 FRATE(CLK_DLL_DCO, "clk_dll_dco", NULL, 0, 360000000),
577 };
578
579 static const struct samsung_mux_clock apm_mux_clks[] __initconst = {
580 MUX(CLK_MOUT_APM_BUS_USER, "mout_apm_bus_user", mout_apm_bus_user_p,
581 PLL_CON0_MUX_CLKCMU_APM_BUS_USER, 4, 1),
582 MUX(CLK_MOUT_RCO_APM_I3C_USER, "mout_rco_apm_i3c_user",
583 mout_rco_apm_i3c_user_p, PLL_CON0_MUX_CLK_RCO_APM_I3C_USER, 4, 1),
584 MUX(CLK_MOUT_RCO_APM_USER, "mout_rco_apm_user", mout_rco_apm_user_p,
585 PLL_CON0_MUX_CLK_RCO_APM_USER, 4, 1),
586 MUX(CLK_MOUT_DLL_USER, "mout_dll_user", mout_dll_user_p,
587 PLL_CON0_MUX_DLL_USER, 4, 1),
588 MUX(CLK_MOUT_CLKCMU_CHUB_BUS, "mout_clkcmu_chub_bus",
589 mout_clkcmu_chub_bus_p, CLK_CON_MUX_MUX_CLKCMU_CHUB_BUS, 0, 1),
590 MUX(CLK_MOUT_APM_BUS, "mout_apm_bus", mout_apm_bus_p,
591 CLK_CON_MUX_MUX_CLK_APM_BUS, 0, 2),
592 MUX(CLK_MOUT_APM_I3C, "mout_apm_i3c", mout_apm_i3c_p,
593 CLK_CON_MUX_MUX_CLK_APM_I3C, 0, 1),
594 };
595
596 static const struct samsung_div_clock apm_div_clks[] __initconst = {
597 DIV(CLK_DOUT_CLKCMU_CHUB_BUS, "dout_clkcmu_chub_bus",
598 "gout_clkcmu_chub_bus",
599 CLK_CON_DIV_CLKCMU_CHUB_BUS, 0, 3),
600 DIV(CLK_DOUT_APM_BUS, "dout_apm_bus", "mout_apm_bus",
601 CLK_CON_DIV_DIV_CLK_APM_BUS, 0, 3),
602 DIV(CLK_DOUT_APM_I3C, "dout_apm_i3c", "mout_apm_bus",
603 CLK_CON_DIV_DIV_CLK_APM_I3C, 0, 3),
604 };
605
606 static const struct samsung_gate_clock apm_gate_clks[] __initconst = {
607 GATE(CLK_GOUT_CLKCMU_CMGP_BUS, "gout_clkcmu_cmgp_bus", "dout_apm_bus",
608 CLK_CON_GAT_CLKCMU_CMGP_BUS, 21, CLK_SET_RATE_PARENT, 0),
609 GATE(CLK_GOUT_CLKCMU_CHUB_BUS, "gout_clkcmu_chub_bus",
610 "mout_clkcmu_chub_bus",
611 CLK_CON_GAT_GATE_CLKCMU_CHUB_BUS, 21, 0, 0),
612 GATE(CLK_GOUT_RTC_PCLK, "gout_rtc_pclk", "dout_apm_bus",
613 CLK_CON_GAT_GOUT_APM_APBIF_RTC_PCLK, 21, 0, 0),
614 GATE(CLK_GOUT_TOP_RTC_PCLK, "gout_top_rtc_pclk", "dout_apm_bus",
615 CLK_CON_GAT_GOUT_APM_APBIF_TOP_RTC_PCLK, 21, 0, 0),
616 GATE(CLK_GOUT_I3C_PCLK, "gout_i3c_pclk", "dout_apm_bus",
617 CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_PCLK, 21, 0, 0),
618 GATE(CLK_GOUT_I3C_SCLK, "gout_i3c_sclk", "mout_apm_i3c",
619 CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_SCLK, 21, 0, 0),
620 GATE(CLK_GOUT_SPEEDY_PCLK, "gout_speedy_pclk", "dout_apm_bus",
621 CLK_CON_GAT_GOUT_APM_SPEEDY_APM_PCLK, 21, 0, 0),
622 /* TODO: Should be enabled in GPIO driver (or made CLK_IS_CRITICAL) */
623 GATE(CLK_GOUT_GPIO_ALIVE_PCLK, "gout_gpio_alive_pclk", "dout_apm_bus",
624 CLK_CON_GAT_GOUT_APM_APBIF_GPIO_ALIVE_PCLK, 21, CLK_IGNORE_UNUSED,
625 0),
626 GATE(CLK_GOUT_PMU_ALIVE_PCLK, "gout_pmu_alive_pclk", "dout_apm_bus",
627 CLK_CON_GAT_GOUT_APM_APBIF_PMU_ALIVE_PCLK, 21, CLK_IS_CRITICAL, 0),
628 GATE(CLK_GOUT_SYSREG_APM_PCLK, "gout_sysreg_apm_pclk", "dout_apm_bus",
629 CLK_CON_GAT_GOUT_APM_SYSREG_APM_PCLK, 21, 0, 0),
630 };
631
632 static const struct samsung_cmu_info apm_cmu_info __initconst = {
633 .mux_clks = apm_mux_clks,
634 .nr_mux_clks = ARRAY_SIZE(apm_mux_clks),
635 .div_clks = apm_div_clks,
636 .nr_div_clks = ARRAY_SIZE(apm_div_clks),
637 .gate_clks = apm_gate_clks,
638 .nr_gate_clks = ARRAY_SIZE(apm_gate_clks),
639 .fixed_clks = apm_fixed_clks,
640 .nr_fixed_clks = ARRAY_SIZE(apm_fixed_clks),
641 .nr_clk_ids = CLKS_NR_APM,
642 .clk_regs = apm_clk_regs,
643 .nr_clk_regs = ARRAY_SIZE(apm_clk_regs),
644 .clk_name = "dout_clkcmu_apm_bus",
645 };
646
647 /* ---- CMU_AUD ------------------------------------------------------------- */
648
649 #define PLL_LOCKTIME_PLL_AUD 0x0000
650 #define PLL_CON0_PLL_AUD 0x0100
651 #define PLL_CON3_PLL_AUD 0x010c
652 #define PLL_CON0_MUX_CLKCMU_AUD_CPU_USER 0x0600
653 #define PLL_CON0_MUX_TICK_USB_USER 0x0610
654 #define CLK_CON_MUX_MUX_CLK_AUD_CPU 0x1000
655 #define CLK_CON_MUX_MUX_CLK_AUD_CPU_HCH 0x1004
656 #define CLK_CON_MUX_MUX_CLK_AUD_FM 0x1008
657 #define CLK_CON_MUX_MUX_CLK_AUD_UAIF0 0x100c
658 #define CLK_CON_MUX_MUX_CLK_AUD_UAIF1 0x1010
659 #define CLK_CON_MUX_MUX_CLK_AUD_UAIF2 0x1014
660 #define CLK_CON_MUX_MUX_CLK_AUD_UAIF3 0x1018
661 #define CLK_CON_MUX_MUX_CLK_AUD_UAIF4 0x101c
662 #define CLK_CON_MUX_MUX_CLK_AUD_UAIF5 0x1020
663 #define CLK_CON_MUX_MUX_CLK_AUD_UAIF6 0x1024
664 #define CLK_CON_DIV_DIV_CLK_AUD_MCLK 0x1800
665 #define CLK_CON_DIV_DIV_CLK_AUD_AUDIF 0x1804
666 #define CLK_CON_DIV_DIV_CLK_AUD_BUSD 0x1808
667 #define CLK_CON_DIV_DIV_CLK_AUD_BUSP 0x180c
668 #define CLK_CON_DIV_DIV_CLK_AUD_CNT 0x1810
669 #define CLK_CON_DIV_DIV_CLK_AUD_CPU 0x1814
670 #define CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK 0x1818
671 #define CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG 0x181c
672 #define CLK_CON_DIV_DIV_CLK_AUD_FM 0x1820
673 #define CLK_CON_DIV_DIV_CLK_AUD_FM_SPDY 0x1824
674 #define CLK_CON_DIV_DIV_CLK_AUD_UAIF0 0x1828
675 #define CLK_CON_DIV_DIV_CLK_AUD_UAIF1 0x182c
676 #define CLK_CON_DIV_DIV_CLK_AUD_UAIF2 0x1830
677 #define CLK_CON_DIV_DIV_CLK_AUD_UAIF3 0x1834
678 #define CLK_CON_DIV_DIV_CLK_AUD_UAIF4 0x1838
679 #define CLK_CON_DIV_DIV_CLK_AUD_UAIF5 0x183c
680 #define CLK_CON_DIV_DIV_CLK_AUD_UAIF6 0x1840
681 #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_CNT 0x2000
682 #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF0 0x2004
683 #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF1 0x2008
684 #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF2 0x200c
685 #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF3 0x2010
686 #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF4 0x2014
687 #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF5 0x2018
688 #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF6 0x201c
689 #define CLK_CON_GAT_CLK_AUD_CMU_AUD_PCLK 0x2020
690 #define CLK_CON_GAT_GOUT_AUD_ABOX_ACLK 0x2048
691 #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_SPDY 0x204c
692 #define CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_ASB 0x2050
693 #define CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_CA32 0x2054
694 #define CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_DAP 0x2058
695 #define CLK_CON_GAT_GOUT_AUD_CODEC_MCLK 0x206c
696 #define CLK_CON_GAT_GOUT_AUD_TZPC_PCLK 0x2070
697 #define CLK_CON_GAT_GOUT_AUD_GPIO_PCLK 0x2074
698 #define CLK_CON_GAT_GOUT_AUD_PPMU_ACLK 0x2088
699 #define CLK_CON_GAT_GOUT_AUD_PPMU_PCLK 0x208c
700 #define CLK_CON_GAT_GOUT_AUD_SYSMMU_CLK_S1 0x20b4
701 #define CLK_CON_GAT_GOUT_AUD_SYSREG_PCLK 0x20b8
702 #define CLK_CON_GAT_GOUT_AUD_WDT_PCLK 0x20bc
703
704 static const unsigned long aud_clk_regs[] __initconst = {
705 PLL_LOCKTIME_PLL_AUD,
706 PLL_CON0_PLL_AUD,
707 PLL_CON3_PLL_AUD,
708 PLL_CON0_MUX_CLKCMU_AUD_CPU_USER,
709 PLL_CON0_MUX_TICK_USB_USER,
710 CLK_CON_MUX_MUX_CLK_AUD_CPU,
711 CLK_CON_MUX_MUX_CLK_AUD_CPU_HCH,
712 CLK_CON_MUX_MUX_CLK_AUD_FM,
713 CLK_CON_MUX_MUX_CLK_AUD_UAIF0,
714 CLK_CON_MUX_MUX_CLK_AUD_UAIF1,
715 CLK_CON_MUX_MUX_CLK_AUD_UAIF2,
716 CLK_CON_MUX_MUX_CLK_AUD_UAIF3,
717 CLK_CON_MUX_MUX_CLK_AUD_UAIF4,
718 CLK_CON_MUX_MUX_CLK_AUD_UAIF5,
719 CLK_CON_MUX_MUX_CLK_AUD_UAIF6,
720 CLK_CON_DIV_DIV_CLK_AUD_MCLK,
721 CLK_CON_DIV_DIV_CLK_AUD_AUDIF,
722 CLK_CON_DIV_DIV_CLK_AUD_BUSD,
723 CLK_CON_DIV_DIV_CLK_AUD_BUSP,
724 CLK_CON_DIV_DIV_CLK_AUD_CNT,
725 CLK_CON_DIV_DIV_CLK_AUD_CPU,
726 CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK,
727 CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG,
728 CLK_CON_DIV_DIV_CLK_AUD_FM,
729 CLK_CON_DIV_DIV_CLK_AUD_FM_SPDY,
730 CLK_CON_DIV_DIV_CLK_AUD_UAIF0,
731 CLK_CON_DIV_DIV_CLK_AUD_UAIF1,
732 CLK_CON_DIV_DIV_CLK_AUD_UAIF2,
733 CLK_CON_DIV_DIV_CLK_AUD_UAIF3,
734 CLK_CON_DIV_DIV_CLK_AUD_UAIF4,
735 CLK_CON_DIV_DIV_CLK_AUD_UAIF5,
736 CLK_CON_DIV_DIV_CLK_AUD_UAIF6,
737 CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_CNT,
738 CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF0,
739 CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF1,
740 CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF2,
741 CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF3,
742 CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF4,
743 CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF5,
744 CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF6,
745 CLK_CON_GAT_CLK_AUD_CMU_AUD_PCLK,
746 CLK_CON_GAT_GOUT_AUD_ABOX_ACLK,
747 CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_SPDY,
748 CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_ASB,
749 CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_CA32,
750 CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_DAP,
751 CLK_CON_GAT_GOUT_AUD_CODEC_MCLK,
752 CLK_CON_GAT_GOUT_AUD_TZPC_PCLK,
753 CLK_CON_GAT_GOUT_AUD_GPIO_PCLK,
754 CLK_CON_GAT_GOUT_AUD_PPMU_ACLK,
755 CLK_CON_GAT_GOUT_AUD_PPMU_PCLK,
756 CLK_CON_GAT_GOUT_AUD_SYSMMU_CLK_S1,
757 CLK_CON_GAT_GOUT_AUD_SYSREG_PCLK,
758 CLK_CON_GAT_GOUT_AUD_WDT_PCLK,
759 };
760
761 /* List of parent clocks for Muxes in CMU_AUD */
762 PNAME(mout_aud_pll_p) = { "oscclk", "fout_aud_pll" };
763 PNAME(mout_aud_cpu_user_p) = { "oscclk", "dout_aud" };
764 PNAME(mout_aud_cpu_p) = { "dout_aud_cpu", "mout_aud_cpu_user" };
765 PNAME(mout_aud_cpu_hch_p) = { "mout_aud_cpu", "oscclk" };
766 PNAME(mout_aud_uaif0_p) = { "dout_aud_uaif0", "ioclk_audiocdclk0" };
767 PNAME(mout_aud_uaif1_p) = { "dout_aud_uaif1", "ioclk_audiocdclk1" };
768 PNAME(mout_aud_uaif2_p) = { "dout_aud_uaif2", "ioclk_audiocdclk2" };
769 PNAME(mout_aud_uaif3_p) = { "dout_aud_uaif3", "ioclk_audiocdclk3" };
770 PNAME(mout_aud_uaif4_p) = { "dout_aud_uaif4", "ioclk_audiocdclk4" };
771 PNAME(mout_aud_uaif5_p) = { "dout_aud_uaif5", "ioclk_audiocdclk5" };
772 PNAME(mout_aud_uaif6_p) = { "dout_aud_uaif6", "ioclk_audiocdclk6" };
773 PNAME(mout_aud_tick_usb_user_p) = { "oscclk", "tick_usb" };
774 PNAME(mout_aud_fm_p) = { "oscclk", "dout_aud_fm_spdy" };
775
776 /*
777 * Do not provide PLL table to PLL_AUD, as MANUAL_PLL_CTRL bit is not set
778 * for that PLL by default, so set_rate operation would fail.
779 */
780 static const struct samsung_pll_clock aud_pll_clks[] __initconst = {
781 PLL(pll_0831x, CLK_FOUT_AUD_PLL, "fout_aud_pll", "oscclk",
782 PLL_LOCKTIME_PLL_AUD, PLL_CON3_PLL_AUD, NULL),
783 };
784
785 static const struct samsung_fixed_rate_clock aud_fixed_clks[] __initconst = {
786 FRATE(IOCLK_AUDIOCDCLK0, "ioclk_audiocdclk0", NULL, 0, 25000000),
787 FRATE(IOCLK_AUDIOCDCLK1, "ioclk_audiocdclk1", NULL, 0, 25000000),
788 FRATE(IOCLK_AUDIOCDCLK2, "ioclk_audiocdclk2", NULL, 0, 25000000),
789 FRATE(IOCLK_AUDIOCDCLK3, "ioclk_audiocdclk3", NULL, 0, 25000000),
790 FRATE(IOCLK_AUDIOCDCLK4, "ioclk_audiocdclk4", NULL, 0, 25000000),
791 FRATE(IOCLK_AUDIOCDCLK5, "ioclk_audiocdclk5", NULL, 0, 25000000),
792 FRATE(IOCLK_AUDIOCDCLK6, "ioclk_audiocdclk6", NULL, 0, 25000000),
793 FRATE(TICK_USB, "tick_usb", NULL, 0, 60000000),
794 };
795
796 static const struct samsung_mux_clock aud_mux_clks[] __initconst = {
797 MUX(CLK_MOUT_AUD_PLL, "mout_aud_pll", mout_aud_pll_p,
798 PLL_CON0_PLL_AUD, 4, 1),
799 MUX(CLK_MOUT_AUD_CPU_USER, "mout_aud_cpu_user", mout_aud_cpu_user_p,
800 PLL_CON0_MUX_CLKCMU_AUD_CPU_USER, 4, 1),
801 MUX(CLK_MOUT_AUD_TICK_USB_USER, "mout_aud_tick_usb_user",
802 mout_aud_tick_usb_user_p,
803 PLL_CON0_MUX_TICK_USB_USER, 4, 1),
804 MUX(CLK_MOUT_AUD_CPU, "mout_aud_cpu", mout_aud_cpu_p,
805 CLK_CON_MUX_MUX_CLK_AUD_CPU, 0, 1),
806 MUX(CLK_MOUT_AUD_CPU_HCH, "mout_aud_cpu_hch", mout_aud_cpu_hch_p,
807 CLK_CON_MUX_MUX_CLK_AUD_CPU_HCH, 0, 1),
808 MUX(CLK_MOUT_AUD_UAIF0, "mout_aud_uaif0", mout_aud_uaif0_p,
809 CLK_CON_MUX_MUX_CLK_AUD_UAIF0, 0, 1),
810 MUX(CLK_MOUT_AUD_UAIF1, "mout_aud_uaif1", mout_aud_uaif1_p,
811 CLK_CON_MUX_MUX_CLK_AUD_UAIF1, 0, 1),
812 MUX(CLK_MOUT_AUD_UAIF2, "mout_aud_uaif2", mout_aud_uaif2_p,
813 CLK_CON_MUX_MUX_CLK_AUD_UAIF2, 0, 1),
814 MUX(CLK_MOUT_AUD_UAIF3, "mout_aud_uaif3", mout_aud_uaif3_p,
815 CLK_CON_MUX_MUX_CLK_AUD_UAIF3, 0, 1),
816 MUX(CLK_MOUT_AUD_UAIF4, "mout_aud_uaif4", mout_aud_uaif4_p,
817 CLK_CON_MUX_MUX_CLK_AUD_UAIF4, 0, 1),
818 MUX(CLK_MOUT_AUD_UAIF5, "mout_aud_uaif5", mout_aud_uaif5_p,
819 CLK_CON_MUX_MUX_CLK_AUD_UAIF5, 0, 1),
820 MUX(CLK_MOUT_AUD_UAIF6, "mout_aud_uaif6", mout_aud_uaif6_p,
821 CLK_CON_MUX_MUX_CLK_AUD_UAIF6, 0, 1),
822 MUX(CLK_MOUT_AUD_FM, "mout_aud_fm", mout_aud_fm_p,
823 CLK_CON_MUX_MUX_CLK_AUD_FM, 0, 1),
824 };
825
826 static const struct samsung_div_clock aud_div_clks[] __initconst = {
827 DIV(CLK_DOUT_AUD_CPU, "dout_aud_cpu", "mout_aud_pll",
828 CLK_CON_DIV_DIV_CLK_AUD_CPU, 0, 4),
829 DIV(CLK_DOUT_AUD_BUSD, "dout_aud_busd", "mout_aud_pll",
830 CLK_CON_DIV_DIV_CLK_AUD_BUSD, 0, 4),
831 DIV(CLK_DOUT_AUD_BUSP, "dout_aud_busp", "mout_aud_pll",
832 CLK_CON_DIV_DIV_CLK_AUD_BUSP, 0, 4),
833 DIV(CLK_DOUT_AUD_AUDIF, "dout_aud_audif", "mout_aud_pll",
834 CLK_CON_DIV_DIV_CLK_AUD_AUDIF, 0, 9),
835 DIV(CLK_DOUT_AUD_CPU_ACLK, "dout_aud_cpu_aclk", "mout_aud_cpu_hch",
836 CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK, 0, 3),
837 DIV(CLK_DOUT_AUD_CPU_PCLKDBG, "dout_aud_cpu_pclkdbg",
838 "mout_aud_cpu_hch",
839 CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG, 0, 3),
840 DIV(CLK_DOUT_AUD_MCLK, "dout_aud_mclk", "dout_aud_audif",
841 CLK_CON_DIV_DIV_CLK_AUD_MCLK, 0, 2),
842 DIV(CLK_DOUT_AUD_CNT, "dout_aud_cnt", "dout_aud_audif",
843 CLK_CON_DIV_DIV_CLK_AUD_CNT, 0, 10),
844 DIV(CLK_DOUT_AUD_UAIF0, "dout_aud_uaif0", "dout_aud_audif",
845 CLK_CON_DIV_DIV_CLK_AUD_UAIF0, 0, 10),
846 DIV(CLK_DOUT_AUD_UAIF1, "dout_aud_uaif1", "dout_aud_audif",
847 CLK_CON_DIV_DIV_CLK_AUD_UAIF1, 0, 10),
848 DIV(CLK_DOUT_AUD_UAIF2, "dout_aud_uaif2", "dout_aud_audif",
849 CLK_CON_DIV_DIV_CLK_AUD_UAIF2, 0, 10),
850 DIV(CLK_DOUT_AUD_UAIF3, "dout_aud_uaif3", "dout_aud_audif",
851 CLK_CON_DIV_DIV_CLK_AUD_UAIF3, 0, 10),
852 DIV(CLK_DOUT_AUD_UAIF4, "dout_aud_uaif4", "dout_aud_audif",
853 CLK_CON_DIV_DIV_CLK_AUD_UAIF4, 0, 10),
854 DIV(CLK_DOUT_AUD_UAIF5, "dout_aud_uaif5", "dout_aud_audif",
855 CLK_CON_DIV_DIV_CLK_AUD_UAIF5, 0, 10),
856 DIV(CLK_DOUT_AUD_UAIF6, "dout_aud_uaif6", "dout_aud_audif",
857 CLK_CON_DIV_DIV_CLK_AUD_UAIF6, 0, 10),
858 DIV(CLK_DOUT_AUD_FM_SPDY, "dout_aud_fm_spdy", "mout_aud_tick_usb_user",
859 CLK_CON_DIV_DIV_CLK_AUD_FM_SPDY, 0, 1),
860 DIV(CLK_DOUT_AUD_FM, "dout_aud_fm", "mout_aud_fm",
861 CLK_CON_DIV_DIV_CLK_AUD_FM, 0, 10),
862 };
863
864 static const struct samsung_gate_clock aud_gate_clks[] __initconst = {
865 GATE(CLK_GOUT_AUD_CMU_AUD_PCLK, "gout_aud_cmu_aud_pclk",
866 "dout_aud_busd",
867 CLK_CON_GAT_CLK_AUD_CMU_AUD_PCLK, 21, CLK_IGNORE_UNUSED, 0),
868 GATE(CLK_GOUT_AUD_CA32_CCLK, "gout_aud_ca32_cclk", "mout_aud_cpu_hch",
869 CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_CA32, 21, 0, 0),
870 GATE(CLK_GOUT_AUD_ASB_CCLK, "gout_aud_asb_cclk", "dout_aud_cpu_aclk",
871 CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_ASB, 21, 0, 0),
872 GATE(CLK_GOUT_AUD_DAP_CCLK, "gout_aud_dap_cclk", "dout_aud_cpu_pclkdbg",
873 CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_DAP, 21, 0, 0),
874 /* TODO: Should be enabled in ABOX driver (or made CLK_IS_CRITICAL) */
875 GATE(CLK_GOUT_AUD_ABOX_ACLK, "gout_aud_abox_aclk", "dout_aud_busd",
876 CLK_CON_GAT_GOUT_AUD_ABOX_ACLK, 21, CLK_IGNORE_UNUSED, 0),
877 GATE(CLK_GOUT_AUD_GPIO_PCLK, "gout_aud_gpio_pclk", "dout_aud_busd",
878 CLK_CON_GAT_GOUT_AUD_GPIO_PCLK, 21, 0, 0),
879 GATE(CLK_GOUT_AUD_PPMU_ACLK, "gout_aud_ppmu_aclk", "dout_aud_busd",
880 CLK_CON_GAT_GOUT_AUD_PPMU_ACLK, 21, 0, 0),
881 GATE(CLK_GOUT_AUD_PPMU_PCLK, "gout_aud_ppmu_pclk", "dout_aud_busd",
882 CLK_CON_GAT_GOUT_AUD_PPMU_PCLK, 21, 0, 0),
883 GATE(CLK_GOUT_AUD_SYSMMU_CLK, "gout_aud_sysmmu_clk", "dout_aud_busd",
884 CLK_CON_GAT_GOUT_AUD_SYSMMU_CLK_S1, 21, 0, 0),
885 GATE(CLK_GOUT_AUD_SYSREG_PCLK, "gout_aud_sysreg_pclk", "dout_aud_busd",
886 CLK_CON_GAT_GOUT_AUD_SYSREG_PCLK, 21, 0, 0),
887 GATE(CLK_GOUT_AUD_WDT_PCLK, "gout_aud_wdt_pclk", "dout_aud_busd",
888 CLK_CON_GAT_GOUT_AUD_WDT_PCLK, 21, 0, 0),
889 GATE(CLK_GOUT_AUD_TZPC_PCLK, "gout_aud_tzpc_pclk", "dout_aud_busp",
890 CLK_CON_GAT_GOUT_AUD_TZPC_PCLK, 21, 0, 0),
891 GATE(CLK_GOUT_AUD_CODEC_MCLK, "gout_aud_codec_mclk", "dout_aud_mclk",
892 CLK_CON_GAT_GOUT_AUD_CODEC_MCLK, 21, 0, 0),
893 GATE(CLK_GOUT_AUD_CNT_BCLK, "gout_aud_cnt_bclk", "dout_aud_cnt",
894 CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_CNT, 21, 0, 0),
895 GATE(CLK_GOUT_AUD_UAIF0_BCLK, "gout_aud_uaif0_bclk", "mout_aud_uaif0",
896 CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF0, 21, 0, 0),
897 GATE(CLK_GOUT_AUD_UAIF1_BCLK, "gout_aud_uaif1_bclk", "mout_aud_uaif1",
898 CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF1, 21, 0, 0),
899 GATE(CLK_GOUT_AUD_UAIF2_BCLK, "gout_aud_uaif2_bclk", "mout_aud_uaif2",
900 CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF2, 21, 0, 0),
901 GATE(CLK_GOUT_AUD_UAIF3_BCLK, "gout_aud_uaif3_bclk", "mout_aud_uaif3",
902 CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF3, 21, 0, 0),
903 GATE(CLK_GOUT_AUD_UAIF4_BCLK, "gout_aud_uaif4_bclk", "mout_aud_uaif4",
904 CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF4, 21, 0, 0),
905 GATE(CLK_GOUT_AUD_UAIF5_BCLK, "gout_aud_uaif5_bclk", "mout_aud_uaif5",
906 CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF5, 21, 0, 0),
907 GATE(CLK_GOUT_AUD_UAIF6_BCLK, "gout_aud_uaif6_bclk", "mout_aud_uaif6",
908 CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF6, 21, 0, 0),
909 GATE(CLK_GOUT_AUD_SPDY_BCLK, "gout_aud_spdy_bclk", "dout_aud_fm",
910 CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_SPDY, 21, 0, 0),
911 };
912
913 static const struct samsung_cmu_info aud_cmu_info __initconst = {
914 .pll_clks = aud_pll_clks,
915 .nr_pll_clks = ARRAY_SIZE(aud_pll_clks),
916 .mux_clks = aud_mux_clks,
917 .nr_mux_clks = ARRAY_SIZE(aud_mux_clks),
918 .div_clks = aud_div_clks,
919 .nr_div_clks = ARRAY_SIZE(aud_div_clks),
920 .gate_clks = aud_gate_clks,
921 .nr_gate_clks = ARRAY_SIZE(aud_gate_clks),
922 .fixed_clks = aud_fixed_clks,
923 .nr_fixed_clks = ARRAY_SIZE(aud_fixed_clks),
924 .nr_clk_ids = CLKS_NR_AUD,
925 .clk_regs = aud_clk_regs,
926 .nr_clk_regs = ARRAY_SIZE(aud_clk_regs),
927 .clk_name = "dout_aud",
928 };
929
930 /* ---- CMU_CMGP ------------------------------------------------------------ */
931
932 /* Register Offset definitions for CMU_CMGP (0x11c00000) */
933 #define CLK_CON_MUX_CLK_CMGP_ADC 0x1000
934 #define CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP0 0x1004
935 #define CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP1 0x1008
936 #define CLK_CON_DIV_DIV_CLK_CMGP_ADC 0x1800
937 #define CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP0 0x1804
938 #define CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP1 0x1808
939 #define CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S0 0x200c
940 #define CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S1 0x2010
941 #define CLK_CON_GAT_GOUT_CMGP_GPIO_PCLK 0x2018
942 #define CLK_CON_GAT_GOUT_CMGP_SYSREG_CMGP_PCLK 0x2040
943 #define CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_IPCLK 0x2044
944 #define CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_PCLK 0x2048
945 #define CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_IPCLK 0x204c
946 #define CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_PCLK 0x2050
947
948 static const unsigned long cmgp_clk_regs[] __initconst = {
949 CLK_CON_MUX_CLK_CMGP_ADC,
950 CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP0,
951 CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP1,
952 CLK_CON_DIV_DIV_CLK_CMGP_ADC,
953 CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP0,
954 CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP1,
955 CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S0,
956 CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S1,
957 CLK_CON_GAT_GOUT_CMGP_GPIO_PCLK,
958 CLK_CON_GAT_GOUT_CMGP_SYSREG_CMGP_PCLK,
959 CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_IPCLK,
960 CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_PCLK,
961 CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_IPCLK,
962 CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_PCLK,
963 };
964
965 /* List of parent clocks for Muxes in CMU_CMGP */
966 PNAME(mout_cmgp_usi0_p) = { "clk_rco_cmgp", "gout_clkcmu_cmgp_bus" };
967 PNAME(mout_cmgp_usi1_p) = { "clk_rco_cmgp", "gout_clkcmu_cmgp_bus" };
968 PNAME(mout_cmgp_adc_p) = { "oscclk", "dout_cmgp_adc" };
969
970 static const struct samsung_fixed_rate_clock cmgp_fixed_clks[] __initconst = {
971 FRATE(CLK_RCO_CMGP, "clk_rco_cmgp", NULL, 0, 49152000),
972 };
973
974 static const struct samsung_mux_clock cmgp_mux_clks[] __initconst = {
975 MUX(CLK_MOUT_CMGP_ADC, "mout_cmgp_adc", mout_cmgp_adc_p,
976 CLK_CON_MUX_CLK_CMGP_ADC, 0, 1),
977 MUX_F(CLK_MOUT_CMGP_USI0, "mout_cmgp_usi0", mout_cmgp_usi0_p,
978 CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP0, 0, 1, CLK_SET_RATE_PARENT, 0),
979 MUX_F(CLK_MOUT_CMGP_USI1, "mout_cmgp_usi1", mout_cmgp_usi1_p,
980 CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP1, 0, 1, CLK_SET_RATE_PARENT, 0),
981 };
982
983 static const struct samsung_div_clock cmgp_div_clks[] __initconst = {
984 DIV(CLK_DOUT_CMGP_ADC, "dout_cmgp_adc", "gout_clkcmu_cmgp_bus",
985 CLK_CON_DIV_DIV_CLK_CMGP_ADC, 0, 4),
986 DIV_F(CLK_DOUT_CMGP_USI0, "dout_cmgp_usi0", "mout_cmgp_usi0",
987 CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP0, 0, 5, CLK_SET_RATE_PARENT, 0),
988 DIV_F(CLK_DOUT_CMGP_USI1, "dout_cmgp_usi1", "mout_cmgp_usi1",
989 CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP1, 0, 5, CLK_SET_RATE_PARENT, 0),
990 };
991
992 static const struct samsung_gate_clock cmgp_gate_clks[] __initconst = {
993 GATE(CLK_GOUT_CMGP_ADC_S0_PCLK, "gout_adc_s0_pclk",
994 "gout_clkcmu_cmgp_bus",
995 CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S0, 21, 0, 0),
996 GATE(CLK_GOUT_CMGP_ADC_S1_PCLK, "gout_adc_s1_pclk",
997 "gout_clkcmu_cmgp_bus",
998 CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S1, 21, 0, 0),
999 /* TODO: Should be enabled in GPIO driver (or made CLK_IS_CRITICAL) */
1000 GATE(CLK_GOUT_CMGP_GPIO_PCLK, "gout_gpio_cmgp_pclk",
1001 "gout_clkcmu_cmgp_bus",
1002 CLK_CON_GAT_GOUT_CMGP_GPIO_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1003 GATE(CLK_GOUT_CMGP_USI0_IPCLK, "gout_cmgp_usi0_ipclk", "dout_cmgp_usi0",
1004 CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_IPCLK, 21, CLK_SET_RATE_PARENT, 0),
1005 GATE(CLK_GOUT_CMGP_USI0_PCLK, "gout_cmgp_usi0_pclk",
1006 "gout_clkcmu_cmgp_bus",
1007 CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_PCLK, 21, 0, 0),
1008 GATE(CLK_GOUT_CMGP_USI1_IPCLK, "gout_cmgp_usi1_ipclk", "dout_cmgp_usi1",
1009 CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_IPCLK, 21, CLK_SET_RATE_PARENT, 0),
1010 GATE(CLK_GOUT_CMGP_USI1_PCLK, "gout_cmgp_usi1_pclk",
1011 "gout_clkcmu_cmgp_bus",
1012 CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_PCLK, 21, 0, 0),
1013 GATE(CLK_GOUT_SYSREG_CMGP_PCLK, "gout_sysreg_cmgp_pclk",
1014 "gout_clkcmu_cmgp_bus",
1015 CLK_CON_GAT_GOUT_CMGP_SYSREG_CMGP_PCLK, 21, 0, 0),
1016 };
1017
1018 static const struct samsung_cmu_info cmgp_cmu_info __initconst = {
1019 .mux_clks = cmgp_mux_clks,
1020 .nr_mux_clks = ARRAY_SIZE(cmgp_mux_clks),
1021 .div_clks = cmgp_div_clks,
1022 .nr_div_clks = ARRAY_SIZE(cmgp_div_clks),
1023 .gate_clks = cmgp_gate_clks,
1024 .nr_gate_clks = ARRAY_SIZE(cmgp_gate_clks),
1025 .fixed_clks = cmgp_fixed_clks,
1026 .nr_fixed_clks = ARRAY_SIZE(cmgp_fixed_clks),
1027 .nr_clk_ids = CLKS_NR_CMGP,
1028 .clk_regs = cmgp_clk_regs,
1029 .nr_clk_regs = ARRAY_SIZE(cmgp_clk_regs),
1030 .clk_name = "gout_clkcmu_cmgp_bus",
1031 };
1032
1033 /* ---- CMU_G3D ------------------------------------------------------------- */
1034
1035 /* Register Offset definitions for CMU_G3D (0x11400000) */
1036 #define PLL_LOCKTIME_PLL_G3D 0x0000
1037 #define PLL_CON0_PLL_G3D 0x0100
1038 #define PLL_CON3_PLL_G3D 0x010c
1039 #define PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER 0x0600
1040 #define CLK_CON_MUX_MUX_CLK_G3D_BUSD 0x1000
1041 #define CLK_CON_DIV_DIV_CLK_G3D_BUSP 0x1804
1042 #define CLK_CON_GAT_CLK_G3D_CMU_G3D_PCLK 0x2000
1043 #define CLK_CON_GAT_CLK_G3D_GPU_CLK 0x2004
1044 #define CLK_CON_GAT_GOUT_G3D_TZPC_PCLK 0x200c
1045 #define CLK_CON_GAT_GOUT_G3D_GRAY2BIN_CLK 0x2010
1046 #define CLK_CON_GAT_GOUT_G3D_BUSD_CLK 0x2024
1047 #define CLK_CON_GAT_GOUT_G3D_BUSP_CLK 0x2028
1048 #define CLK_CON_GAT_GOUT_G3D_SYSREG_PCLK 0x202c
1049
1050 static const unsigned long g3d_clk_regs[] __initconst = {
1051 PLL_LOCKTIME_PLL_G3D,
1052 PLL_CON0_PLL_G3D,
1053 PLL_CON3_PLL_G3D,
1054 PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER,
1055 CLK_CON_MUX_MUX_CLK_G3D_BUSD,
1056 CLK_CON_DIV_DIV_CLK_G3D_BUSP,
1057 CLK_CON_GAT_CLK_G3D_CMU_G3D_PCLK,
1058 CLK_CON_GAT_CLK_G3D_GPU_CLK,
1059 CLK_CON_GAT_GOUT_G3D_TZPC_PCLK,
1060 CLK_CON_GAT_GOUT_G3D_GRAY2BIN_CLK,
1061 CLK_CON_GAT_GOUT_G3D_BUSD_CLK,
1062 CLK_CON_GAT_GOUT_G3D_BUSP_CLK,
1063 CLK_CON_GAT_GOUT_G3D_SYSREG_PCLK,
1064 };
1065
1066 /* List of parent clocks for Muxes in CMU_G3D */
1067 PNAME(mout_g3d_pll_p) = { "oscclk", "fout_g3d_pll" };
1068 PNAME(mout_g3d_switch_user_p) = { "oscclk", "dout_g3d_switch" };
1069 PNAME(mout_g3d_busd_p) = { "mout_g3d_pll", "mout_g3d_switch_user" };
1070
1071 /*
1072 * Do not provide PLL table to PLL_G3D, as MANUAL_PLL_CTRL bit is not set
1073 * for that PLL by default, so set_rate operation would fail.
1074 */
1075 static const struct samsung_pll_clock g3d_pll_clks[] __initconst = {
1076 PLL(pll_0818x, CLK_FOUT_G3D_PLL, "fout_g3d_pll", "oscclk",
1077 PLL_LOCKTIME_PLL_G3D, PLL_CON3_PLL_G3D, NULL),
1078 };
1079
1080 static const struct samsung_mux_clock g3d_mux_clks[] __initconst = {
1081 MUX(CLK_MOUT_G3D_PLL, "mout_g3d_pll", mout_g3d_pll_p,
1082 PLL_CON0_PLL_G3D, 4, 1),
1083 MUX(CLK_MOUT_G3D_SWITCH_USER, "mout_g3d_switch_user",
1084 mout_g3d_switch_user_p,
1085 PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER, 4, 1),
1086 MUX(CLK_MOUT_G3D_BUSD, "mout_g3d_busd", mout_g3d_busd_p,
1087 CLK_CON_MUX_MUX_CLK_G3D_BUSD, 0, 1),
1088 };
1089
1090 static const struct samsung_div_clock g3d_div_clks[] __initconst = {
1091 DIV(CLK_DOUT_G3D_BUSP, "dout_g3d_busp", "mout_g3d_busd",
1092 CLK_CON_DIV_DIV_CLK_G3D_BUSP, 0, 3),
1093 };
1094
1095 static const struct samsung_gate_clock g3d_gate_clks[] __initconst = {
1096 GATE(CLK_GOUT_G3D_CMU_G3D_PCLK, "gout_g3d_cmu_g3d_pclk",
1097 "dout_g3d_busp",
1098 CLK_CON_GAT_CLK_G3D_CMU_G3D_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1099 GATE(CLK_GOUT_G3D_GPU_CLK, "gout_g3d_gpu_clk", "mout_g3d_busd",
1100 CLK_CON_GAT_CLK_G3D_GPU_CLK, 21, 0, 0),
1101 GATE(CLK_GOUT_G3D_TZPC_PCLK, "gout_g3d_tzpc_pclk", "dout_g3d_busp",
1102 CLK_CON_GAT_GOUT_G3D_TZPC_PCLK, 21, 0, 0),
1103 GATE(CLK_GOUT_G3D_GRAY2BIN_CLK, "gout_g3d_gray2bin_clk",
1104 "mout_g3d_busd",
1105 CLK_CON_GAT_GOUT_G3D_GRAY2BIN_CLK, 21, 0, 0),
1106 GATE(CLK_GOUT_G3D_BUSD_CLK, "gout_g3d_busd_clk", "mout_g3d_busd",
1107 CLK_CON_GAT_GOUT_G3D_BUSD_CLK, 21, 0, 0),
1108 GATE(CLK_GOUT_G3D_BUSP_CLK, "gout_g3d_busp_clk", "dout_g3d_busp",
1109 CLK_CON_GAT_GOUT_G3D_BUSP_CLK, 21, 0, 0),
1110 GATE(CLK_GOUT_G3D_SYSREG_PCLK, "gout_g3d_sysreg_pclk", "dout_g3d_busp",
1111 CLK_CON_GAT_GOUT_G3D_SYSREG_PCLK, 21, 0, 0),
1112 };
1113
1114 static const struct samsung_cmu_info g3d_cmu_info __initconst = {
1115 .pll_clks = g3d_pll_clks,
1116 .nr_pll_clks = ARRAY_SIZE(g3d_pll_clks),
1117 .mux_clks = g3d_mux_clks,
1118 .nr_mux_clks = ARRAY_SIZE(g3d_mux_clks),
1119 .div_clks = g3d_div_clks,
1120 .nr_div_clks = ARRAY_SIZE(g3d_div_clks),
1121 .gate_clks = g3d_gate_clks,
1122 .nr_gate_clks = ARRAY_SIZE(g3d_gate_clks),
1123 .nr_clk_ids = CLKS_NR_G3D,
1124 .clk_regs = g3d_clk_regs,
1125 .nr_clk_regs = ARRAY_SIZE(g3d_clk_regs),
1126 .clk_name = "dout_g3d_switch",
1127 };
1128
1129 /* ---- CMU_HSI ------------------------------------------------------------- */
1130
1131 /* Register Offset definitions for CMU_HSI (0x13400000) */
1132 #define PLL_CON0_MUX_CLKCMU_HSI_BUS_USER 0x0600
1133 #define PLL_CON0_MUX_CLKCMU_HSI_MMC_CARD_USER 0x0610
1134 #define PLL_CON0_MUX_CLKCMU_HSI_USB20DRD_USER 0x0620
1135 #define CLK_CON_MUX_MUX_CLK_HSI_RTC 0x1000
1136 #define CLK_CON_GAT_CLK_HSI_CMU_HSI_PCLK 0x2000
1137 #define CLK_CON_GAT_HSI_USB20DRD_TOP_I_RTC_CLK__ALV 0x2008
1138 #define CLK_CON_GAT_HSI_USB20DRD_TOP_I_REF_CLK_50 0x200c
1139 #define CLK_CON_GAT_HSI_USB20DRD_TOP_I_PHY_REFCLK_26 0x2010
1140 #define CLK_CON_GAT_GOUT_HSI_GPIO_HSI_PCLK 0x2018
1141 #define CLK_CON_GAT_GOUT_HSI_MMC_CARD_I_ACLK 0x2024
1142 #define CLK_CON_GAT_GOUT_HSI_MMC_CARD_SDCLKIN 0x2028
1143 #define CLK_CON_GAT_GOUT_HSI_PPMU_ACLK 0x202c
1144 #define CLK_CON_GAT_GOUT_HSI_PPMU_PCLK 0x2030
1145 #define CLK_CON_GAT_GOUT_HSI_SYSREG_HSI_PCLK 0x2038
1146 #define CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_ACLK_PHYCTRL_20 0x203c
1147 #define CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_BUS_CLK_EARLY 0x2040
1148
1149 static const unsigned long hsi_clk_regs[] __initconst = {
1150 PLL_CON0_MUX_CLKCMU_HSI_BUS_USER,
1151 PLL_CON0_MUX_CLKCMU_HSI_MMC_CARD_USER,
1152 PLL_CON0_MUX_CLKCMU_HSI_USB20DRD_USER,
1153 CLK_CON_MUX_MUX_CLK_HSI_RTC,
1154 CLK_CON_GAT_CLK_HSI_CMU_HSI_PCLK,
1155 CLK_CON_GAT_HSI_USB20DRD_TOP_I_RTC_CLK__ALV,
1156 CLK_CON_GAT_HSI_USB20DRD_TOP_I_REF_CLK_50,
1157 CLK_CON_GAT_HSI_USB20DRD_TOP_I_PHY_REFCLK_26,
1158 CLK_CON_GAT_GOUT_HSI_GPIO_HSI_PCLK,
1159 CLK_CON_GAT_GOUT_HSI_MMC_CARD_I_ACLK,
1160 CLK_CON_GAT_GOUT_HSI_MMC_CARD_SDCLKIN,
1161 CLK_CON_GAT_GOUT_HSI_PPMU_ACLK,
1162 CLK_CON_GAT_GOUT_HSI_PPMU_PCLK,
1163 CLK_CON_GAT_GOUT_HSI_SYSREG_HSI_PCLK,
1164 CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_ACLK_PHYCTRL_20,
1165 CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_BUS_CLK_EARLY,
1166 };
1167
1168 /* List of parent clocks for Muxes in CMU_HSI */
1169 PNAME(mout_hsi_bus_user_p) = { "oscclk", "dout_hsi_bus" };
1170 PNAME(mout_hsi_mmc_card_user_p) = { "oscclk", "dout_hsi_mmc_card" };
1171 PNAME(mout_hsi_usb20drd_user_p) = { "oscclk", "dout_hsi_usb20drd" };
1172 PNAME(mout_hsi_rtc_p) = { "rtcclk", "oscclk" };
1173
1174 static const struct samsung_mux_clock hsi_mux_clks[] __initconst = {
1175 MUX(CLK_MOUT_HSI_BUS_USER, "mout_hsi_bus_user", mout_hsi_bus_user_p,
1176 PLL_CON0_MUX_CLKCMU_HSI_BUS_USER, 4, 1),
1177 MUX_F(CLK_MOUT_HSI_MMC_CARD_USER, "mout_hsi_mmc_card_user",
1178 mout_hsi_mmc_card_user_p, PLL_CON0_MUX_CLKCMU_HSI_MMC_CARD_USER,
1179 4, 1, CLK_SET_RATE_PARENT, 0),
1180 MUX(CLK_MOUT_HSI_USB20DRD_USER, "mout_hsi_usb20drd_user",
1181 mout_hsi_usb20drd_user_p, PLL_CON0_MUX_CLKCMU_HSI_USB20DRD_USER,
1182 4, 1),
1183 MUX(CLK_MOUT_HSI_RTC, "mout_hsi_rtc", mout_hsi_rtc_p,
1184 CLK_CON_MUX_MUX_CLK_HSI_RTC, 0, 1),
1185 };
1186
1187 static const struct samsung_gate_clock hsi_gate_clks[] __initconst = {
1188 /* TODO: Should be enabled in corresponding driver */
1189 GATE(CLK_GOUT_HSI_CMU_HSI_PCLK, "gout_hsi_cmu_hsi_pclk",
1190 "mout_hsi_bus_user",
1191 CLK_CON_GAT_CLK_HSI_CMU_HSI_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1192 GATE(CLK_GOUT_USB_RTC_CLK, "gout_usb_rtc", "mout_hsi_rtc",
1193 CLK_CON_GAT_HSI_USB20DRD_TOP_I_RTC_CLK__ALV, 21, 0, 0),
1194 GATE(CLK_GOUT_USB_REF_CLK, "gout_usb_ref", "mout_hsi_usb20drd_user",
1195 CLK_CON_GAT_HSI_USB20DRD_TOP_I_REF_CLK_50, 21, 0, 0),
1196 GATE(CLK_GOUT_USB_PHY_REF_CLK, "gout_usb_phy_ref", "oscclk",
1197 CLK_CON_GAT_HSI_USB20DRD_TOP_I_PHY_REFCLK_26, 21, 0, 0),
1198 /* TODO: Should be enabled in GPIO driver (or made CLK_IS_CRITICAL) */
1199 GATE(CLK_GOUT_GPIO_HSI_PCLK, "gout_gpio_hsi_pclk", "mout_hsi_bus_user",
1200 CLK_CON_GAT_GOUT_HSI_GPIO_HSI_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1201 GATE(CLK_GOUT_MMC_CARD_ACLK, "gout_mmc_card_aclk", "mout_hsi_bus_user",
1202 CLK_CON_GAT_GOUT_HSI_MMC_CARD_I_ACLK, 21, 0, 0),
1203 GATE(CLK_GOUT_MMC_CARD_SDCLKIN, "gout_mmc_card_sdclkin",
1204 "mout_hsi_mmc_card_user",
1205 CLK_CON_GAT_GOUT_HSI_MMC_CARD_SDCLKIN, 21, CLK_SET_RATE_PARENT, 0),
1206 GATE(CLK_GOUT_HSI_PPMU_ACLK, "gout_hsi_ppmu_aclk", "mout_hsi_bus_user",
1207 CLK_CON_GAT_GOUT_HSI_PPMU_ACLK, 21, 0, 0),
1208 GATE(CLK_GOUT_HSI_PPMU_PCLK, "gout_hsi_ppmu_pclk", "mout_hsi_bus_user",
1209 CLK_CON_GAT_GOUT_HSI_PPMU_PCLK, 21, 0, 0),
1210 GATE(CLK_GOUT_SYSREG_HSI_PCLK, "gout_sysreg_hsi_pclk",
1211 "mout_hsi_bus_user",
1212 CLK_CON_GAT_GOUT_HSI_SYSREG_HSI_PCLK, 21, 0, 0),
1213 GATE(CLK_GOUT_USB_PHY_ACLK, "gout_usb_phy_aclk", "mout_hsi_bus_user",
1214 CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_ACLK_PHYCTRL_20, 21, 0, 0),
1215 GATE(CLK_GOUT_USB_BUS_EARLY_CLK, "gout_usb_bus_early",
1216 "mout_hsi_bus_user",
1217 CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_BUS_CLK_EARLY, 21, 0, 0),
1218 };
1219
1220 static const struct samsung_cmu_info hsi_cmu_info __initconst = {
1221 .mux_clks = hsi_mux_clks,
1222 .nr_mux_clks = ARRAY_SIZE(hsi_mux_clks),
1223 .gate_clks = hsi_gate_clks,
1224 .nr_gate_clks = ARRAY_SIZE(hsi_gate_clks),
1225 .nr_clk_ids = CLKS_NR_HSI,
1226 .clk_regs = hsi_clk_regs,
1227 .nr_clk_regs = ARRAY_SIZE(hsi_clk_regs),
1228 .clk_name = "dout_hsi_bus",
1229 };
1230
1231 /* ---- CMU_IS -------------------------------------------------------------- */
1232
1233 #define PLL_CON0_MUX_CLKCMU_IS_BUS_USER 0x0600
1234 #define PLL_CON0_MUX_CLKCMU_IS_GDC_USER 0x0610
1235 #define PLL_CON0_MUX_CLKCMU_IS_ITP_USER 0x0620
1236 #define PLL_CON0_MUX_CLKCMU_IS_VRA_USER 0x0630
1237 #define CLK_CON_DIV_DIV_CLK_IS_BUSP 0x1800
1238 #define CLK_CON_GAT_CLK_IS_CMU_IS_PCLK 0x2000
1239 #define CLK_CON_GAT_GOUT_IS_CSIS0_ACLK 0x2040
1240 #define CLK_CON_GAT_GOUT_IS_CSIS1_ACLK 0x2044
1241 #define CLK_CON_GAT_GOUT_IS_CSIS2_ACLK 0x2048
1242 #define CLK_CON_GAT_GOUT_IS_TZPC_PCLK 0x204c
1243 #define CLK_CON_GAT_GOUT_IS_CLK_CSIS_DMA 0x2050
1244 #define CLK_CON_GAT_GOUT_IS_CLK_GDC 0x2054
1245 #define CLK_CON_GAT_GOUT_IS_CLK_IPP 0x2058
1246 #define CLK_CON_GAT_GOUT_IS_CLK_ITP 0x205c
1247 #define CLK_CON_GAT_GOUT_IS_CLK_MCSC 0x2060
1248 #define CLK_CON_GAT_GOUT_IS_CLK_VRA 0x2064
1249 #define CLK_CON_GAT_GOUT_IS_PPMU_IS0_ACLK 0x2074
1250 #define CLK_CON_GAT_GOUT_IS_PPMU_IS0_PCLK 0x2078
1251 #define CLK_CON_GAT_GOUT_IS_PPMU_IS1_ACLK 0x207c
1252 #define CLK_CON_GAT_GOUT_IS_PPMU_IS1_PCLK 0x2080
1253 #define CLK_CON_GAT_GOUT_IS_SYSMMU_IS0_CLK_S1 0x2098
1254 #define CLK_CON_GAT_GOUT_IS_SYSMMU_IS1_CLK_S1 0x209c
1255 #define CLK_CON_GAT_GOUT_IS_SYSREG_PCLK 0x20a0
1256
1257 static const unsigned long is_clk_regs[] __initconst = {
1258 PLL_CON0_MUX_CLKCMU_IS_BUS_USER,
1259 PLL_CON0_MUX_CLKCMU_IS_GDC_USER,
1260 PLL_CON0_MUX_CLKCMU_IS_ITP_USER,
1261 PLL_CON0_MUX_CLKCMU_IS_VRA_USER,
1262 CLK_CON_DIV_DIV_CLK_IS_BUSP,
1263 CLK_CON_GAT_CLK_IS_CMU_IS_PCLK,
1264 CLK_CON_GAT_GOUT_IS_CSIS0_ACLK,
1265 CLK_CON_GAT_GOUT_IS_CSIS1_ACLK,
1266 CLK_CON_GAT_GOUT_IS_CSIS2_ACLK,
1267 CLK_CON_GAT_GOUT_IS_TZPC_PCLK,
1268 CLK_CON_GAT_GOUT_IS_CLK_CSIS_DMA,
1269 CLK_CON_GAT_GOUT_IS_CLK_GDC,
1270 CLK_CON_GAT_GOUT_IS_CLK_IPP,
1271 CLK_CON_GAT_GOUT_IS_CLK_ITP,
1272 CLK_CON_GAT_GOUT_IS_CLK_MCSC,
1273 CLK_CON_GAT_GOUT_IS_CLK_VRA,
1274 CLK_CON_GAT_GOUT_IS_PPMU_IS0_ACLK,
1275 CLK_CON_GAT_GOUT_IS_PPMU_IS0_PCLK,
1276 CLK_CON_GAT_GOUT_IS_PPMU_IS1_ACLK,
1277 CLK_CON_GAT_GOUT_IS_PPMU_IS1_PCLK,
1278 CLK_CON_GAT_GOUT_IS_SYSMMU_IS0_CLK_S1,
1279 CLK_CON_GAT_GOUT_IS_SYSMMU_IS1_CLK_S1,
1280 CLK_CON_GAT_GOUT_IS_SYSREG_PCLK,
1281 };
1282
1283 /* List of parent clocks for Muxes in CMU_IS */
1284 PNAME(mout_is_bus_user_p) = { "oscclk", "dout_is_bus" };
1285 PNAME(mout_is_itp_user_p) = { "oscclk", "dout_is_itp" };
1286 PNAME(mout_is_vra_user_p) = { "oscclk", "dout_is_vra" };
1287 PNAME(mout_is_gdc_user_p) = { "oscclk", "dout_is_gdc" };
1288
1289 static const struct samsung_mux_clock is_mux_clks[] __initconst = {
1290 MUX(CLK_MOUT_IS_BUS_USER, "mout_is_bus_user", mout_is_bus_user_p,
1291 PLL_CON0_MUX_CLKCMU_IS_BUS_USER, 4, 1),
1292 MUX(CLK_MOUT_IS_ITP_USER, "mout_is_itp_user", mout_is_itp_user_p,
1293 PLL_CON0_MUX_CLKCMU_IS_ITP_USER, 4, 1),
1294 MUX(CLK_MOUT_IS_VRA_USER, "mout_is_vra_user", mout_is_vra_user_p,
1295 PLL_CON0_MUX_CLKCMU_IS_VRA_USER, 4, 1),
1296 MUX(CLK_MOUT_IS_GDC_USER, "mout_is_gdc_user", mout_is_gdc_user_p,
1297 PLL_CON0_MUX_CLKCMU_IS_GDC_USER, 4, 1),
1298 };
1299
1300 static const struct samsung_div_clock is_div_clks[] __initconst = {
1301 DIV(CLK_DOUT_IS_BUSP, "dout_is_busp", "mout_is_bus_user",
1302 CLK_CON_DIV_DIV_CLK_IS_BUSP, 0, 2),
1303 };
1304
1305 static const struct samsung_gate_clock is_gate_clks[] __initconst = {
1306 /* TODO: Should be enabled in IS driver */
1307 GATE(CLK_GOUT_IS_CMU_IS_PCLK, "gout_is_cmu_is_pclk", "dout_is_busp",
1308 CLK_CON_GAT_CLK_IS_CMU_IS_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1309 GATE(CLK_GOUT_IS_CSIS0_ACLK, "gout_is_csis0_aclk", "mout_is_bus_user",
1310 CLK_CON_GAT_GOUT_IS_CSIS0_ACLK, 21, 0, 0),
1311 GATE(CLK_GOUT_IS_CSIS1_ACLK, "gout_is_csis1_aclk", "mout_is_bus_user",
1312 CLK_CON_GAT_GOUT_IS_CSIS1_ACLK, 21, 0, 0),
1313 GATE(CLK_GOUT_IS_CSIS2_ACLK, "gout_is_csis2_aclk", "mout_is_bus_user",
1314 CLK_CON_GAT_GOUT_IS_CSIS2_ACLK, 21, 0, 0),
1315 GATE(CLK_GOUT_IS_TZPC_PCLK, "gout_is_tzpc_pclk", "dout_is_busp",
1316 CLK_CON_GAT_GOUT_IS_TZPC_PCLK, 21, 0, 0),
1317 GATE(CLK_GOUT_IS_CSIS_DMA_CLK, "gout_is_csis_dma_clk",
1318 "mout_is_bus_user",
1319 CLK_CON_GAT_GOUT_IS_CLK_CSIS_DMA, 21, 0, 0),
1320 GATE(CLK_GOUT_IS_GDC_CLK, "gout_is_gdc_clk", "mout_is_gdc_user",
1321 CLK_CON_GAT_GOUT_IS_CLK_GDC, 21, 0, 0),
1322 GATE(CLK_GOUT_IS_IPP_CLK, "gout_is_ipp_clk", "mout_is_bus_user",
1323 CLK_CON_GAT_GOUT_IS_CLK_IPP, 21, 0, 0),
1324 GATE(CLK_GOUT_IS_ITP_CLK, "gout_is_itp_clk", "mout_is_itp_user",
1325 CLK_CON_GAT_GOUT_IS_CLK_ITP, 21, 0, 0),
1326 GATE(CLK_GOUT_IS_MCSC_CLK, "gout_is_mcsc_clk", "mout_is_itp_user",
1327 CLK_CON_GAT_GOUT_IS_CLK_MCSC, 21, 0, 0),
1328 GATE(CLK_GOUT_IS_VRA_CLK, "gout_is_vra_clk", "mout_is_vra_user",
1329 CLK_CON_GAT_GOUT_IS_CLK_VRA, 21, 0, 0),
1330 GATE(CLK_GOUT_IS_PPMU_IS0_ACLK, "gout_is_ppmu_is0_aclk",
1331 "mout_is_bus_user",
1332 CLK_CON_GAT_GOUT_IS_PPMU_IS0_ACLK, 21, 0, 0),
1333 GATE(CLK_GOUT_IS_PPMU_IS0_PCLK, "gout_is_ppmu_is0_pclk", "dout_is_busp",
1334 CLK_CON_GAT_GOUT_IS_PPMU_IS0_PCLK, 21, 0, 0),
1335 GATE(CLK_GOUT_IS_PPMU_IS1_ACLK, "gout_is_ppmu_is1_aclk",
1336 "mout_is_itp_user",
1337 CLK_CON_GAT_GOUT_IS_PPMU_IS1_ACLK, 21, 0, 0),
1338 GATE(CLK_GOUT_IS_PPMU_IS1_PCLK, "gout_is_ppmu_is1_pclk", "dout_is_busp",
1339 CLK_CON_GAT_GOUT_IS_PPMU_IS1_PCLK, 21, 0, 0),
1340 GATE(CLK_GOUT_IS_SYSMMU_IS0_CLK, "gout_is_sysmmu_is0_clk",
1341 "mout_is_bus_user",
1342 CLK_CON_GAT_GOUT_IS_SYSMMU_IS0_CLK_S1, 21, 0, 0),
1343 GATE(CLK_GOUT_IS_SYSMMU_IS1_CLK, "gout_is_sysmmu_is1_clk",
1344 "mout_is_itp_user",
1345 CLK_CON_GAT_GOUT_IS_SYSMMU_IS1_CLK_S1, 21, 0, 0),
1346 GATE(CLK_GOUT_IS_SYSREG_PCLK, "gout_is_sysreg_pclk", "dout_is_busp",
1347 CLK_CON_GAT_GOUT_IS_SYSREG_PCLK, 21, 0, 0),
1348 };
1349
1350 static const struct samsung_cmu_info is_cmu_info __initconst = {
1351 .mux_clks = is_mux_clks,
1352 .nr_mux_clks = ARRAY_SIZE(is_mux_clks),
1353 .div_clks = is_div_clks,
1354 .nr_div_clks = ARRAY_SIZE(is_div_clks),
1355 .gate_clks = is_gate_clks,
1356 .nr_gate_clks = ARRAY_SIZE(is_gate_clks),
1357 .nr_clk_ids = CLKS_NR_IS,
1358 .clk_regs = is_clk_regs,
1359 .nr_clk_regs = ARRAY_SIZE(is_clk_regs),
1360 .clk_name = "dout_is_bus",
1361 };
1362
1363 /* ---- CMU_MFCMSCL --------------------------------------------------------- */
1364
1365 #define PLL_CON0_MUX_CLKCMU_MFCMSCL_JPEG_USER 0x0600
1366 #define PLL_CON0_MUX_CLKCMU_MFCMSCL_M2M_USER 0x0610
1367 #define PLL_CON0_MUX_CLKCMU_MFCMSCL_MCSC_USER 0x0620
1368 #define PLL_CON0_MUX_CLKCMU_MFCMSCL_MFC_USER 0x0630
1369 #define CLK_CON_DIV_DIV_CLK_MFCMSCL_BUSP 0x1800
1370 #define CLK_CON_GAT_CLK_MFCMSCL_CMU_MFCMSCL_PCLK 0x2000
1371 #define CLK_CON_GAT_GOUT_MFCMSCL_TZPC_PCLK 0x2038
1372 #define CLK_CON_GAT_GOUT_MFCMSCL_JPEG_ACLK 0x203c
1373 #define CLK_CON_GAT_GOUT_MFCMSCL_M2M_ACLK 0x2048
1374 #define CLK_CON_GAT_GOUT_MFCMSCL_MCSC_I_CLK 0x204c
1375 #define CLK_CON_GAT_GOUT_MFCMSCL_MFC_ACLK 0x2050
1376 #define CLK_CON_GAT_GOUT_MFCMSCL_PPMU_ACLK 0x2054
1377 #define CLK_CON_GAT_GOUT_MFCMSCL_PPMU_PCLK 0x2058
1378 #define CLK_CON_GAT_GOUT_MFCMSCL_SYSMMU_CLK_S1 0x2074
1379 #define CLK_CON_GAT_GOUT_MFCMSCL_SYSREG_PCLK 0x2078
1380
1381 static const unsigned long mfcmscl_clk_regs[] __initconst = {
1382 PLL_CON0_MUX_CLKCMU_MFCMSCL_JPEG_USER,
1383 PLL_CON0_MUX_CLKCMU_MFCMSCL_M2M_USER,
1384 PLL_CON0_MUX_CLKCMU_MFCMSCL_MCSC_USER,
1385 PLL_CON0_MUX_CLKCMU_MFCMSCL_MFC_USER,
1386 CLK_CON_DIV_DIV_CLK_MFCMSCL_BUSP,
1387 CLK_CON_GAT_CLK_MFCMSCL_CMU_MFCMSCL_PCLK,
1388 CLK_CON_GAT_GOUT_MFCMSCL_TZPC_PCLK,
1389 CLK_CON_GAT_GOUT_MFCMSCL_JPEG_ACLK,
1390 CLK_CON_GAT_GOUT_MFCMSCL_M2M_ACLK,
1391 CLK_CON_GAT_GOUT_MFCMSCL_MCSC_I_CLK,
1392 CLK_CON_GAT_GOUT_MFCMSCL_MFC_ACLK,
1393 CLK_CON_GAT_GOUT_MFCMSCL_PPMU_ACLK,
1394 CLK_CON_GAT_GOUT_MFCMSCL_PPMU_PCLK,
1395 CLK_CON_GAT_GOUT_MFCMSCL_SYSMMU_CLK_S1,
1396 CLK_CON_GAT_GOUT_MFCMSCL_SYSREG_PCLK,
1397 };
1398
1399 /* List of parent clocks for Muxes in CMU_MFCMSCL */
1400 PNAME(mout_mfcmscl_mfc_user_p) = { "oscclk", "dout_mfcmscl_mfc" };
1401 PNAME(mout_mfcmscl_m2m_user_p) = { "oscclk", "dout_mfcmscl_m2m" };
1402 PNAME(mout_mfcmscl_mcsc_user_p) = { "oscclk", "dout_mfcmscl_mcsc" };
1403 PNAME(mout_mfcmscl_jpeg_user_p) = { "oscclk", "dout_mfcmscl_jpeg" };
1404
1405 static const struct samsung_mux_clock mfcmscl_mux_clks[] __initconst = {
1406 MUX(CLK_MOUT_MFCMSCL_MFC_USER, "mout_mfcmscl_mfc_user",
1407 mout_mfcmscl_mfc_user_p,
1408 PLL_CON0_MUX_CLKCMU_MFCMSCL_MFC_USER, 4, 1),
1409 MUX(CLK_MOUT_MFCMSCL_M2M_USER, "mout_mfcmscl_m2m_user",
1410 mout_mfcmscl_m2m_user_p,
1411 PLL_CON0_MUX_CLKCMU_MFCMSCL_M2M_USER, 4, 1),
1412 MUX(CLK_MOUT_MFCMSCL_MCSC_USER, "mout_mfcmscl_mcsc_user",
1413 mout_mfcmscl_mcsc_user_p,
1414 PLL_CON0_MUX_CLKCMU_MFCMSCL_MCSC_USER, 4, 1),
1415 MUX(CLK_MOUT_MFCMSCL_JPEG_USER, "mout_mfcmscl_jpeg_user",
1416 mout_mfcmscl_jpeg_user_p,
1417 PLL_CON0_MUX_CLKCMU_MFCMSCL_JPEG_USER, 4, 1),
1418 };
1419
1420 static const struct samsung_div_clock mfcmscl_div_clks[] __initconst = {
1421 DIV(CLK_DOUT_MFCMSCL_BUSP, "dout_mfcmscl_busp", "mout_mfcmscl_mfc_user",
1422 CLK_CON_DIV_DIV_CLK_MFCMSCL_BUSP, 0, 3),
1423 };
1424
1425 static const struct samsung_gate_clock mfcmscl_gate_clks[] __initconst = {
1426 /* TODO: Should be enabled in MFC driver */
1427 GATE(CLK_GOUT_MFCMSCL_CMU_MFCMSCL_PCLK, "gout_mfcmscl_cmu_mfcmscl_pclk",
1428 "dout_mfcmscl_busp", CLK_CON_GAT_CLK_MFCMSCL_CMU_MFCMSCL_PCLK,
1429 21, CLK_IGNORE_UNUSED, 0),
1430 GATE(CLK_GOUT_MFCMSCL_TZPC_PCLK, "gout_mfcmscl_tzpc_pclk",
1431 "dout_mfcmscl_busp", CLK_CON_GAT_GOUT_MFCMSCL_TZPC_PCLK,
1432 21, 0, 0),
1433 GATE(CLK_GOUT_MFCMSCL_JPEG_ACLK, "gout_mfcmscl_jpeg_aclk",
1434 "mout_mfcmscl_jpeg_user", CLK_CON_GAT_GOUT_MFCMSCL_JPEG_ACLK,
1435 21, 0, 0),
1436 GATE(CLK_GOUT_MFCMSCL_M2M_ACLK, "gout_mfcmscl_m2m_aclk",
1437 "mout_mfcmscl_m2m_user", CLK_CON_GAT_GOUT_MFCMSCL_M2M_ACLK,
1438 21, 0, 0),
1439 GATE(CLK_GOUT_MFCMSCL_MCSC_CLK, "gout_mfcmscl_mcsc_clk",
1440 "mout_mfcmscl_mcsc_user", CLK_CON_GAT_GOUT_MFCMSCL_MCSC_I_CLK,
1441 21, 0, 0),
1442 GATE(CLK_GOUT_MFCMSCL_MFC_ACLK, "gout_mfcmscl_mfc_aclk",
1443 "mout_mfcmscl_mfc_user", CLK_CON_GAT_GOUT_MFCMSCL_MFC_ACLK,
1444 21, 0, 0),
1445 GATE(CLK_GOUT_MFCMSCL_PPMU_ACLK, "gout_mfcmscl_ppmu_aclk",
1446 "mout_mfcmscl_mfc_user", CLK_CON_GAT_GOUT_MFCMSCL_PPMU_ACLK,
1447 21, 0, 0),
1448 GATE(CLK_GOUT_MFCMSCL_PPMU_PCLK, "gout_mfcmscl_ppmu_pclk",
1449 "dout_mfcmscl_busp", CLK_CON_GAT_GOUT_MFCMSCL_PPMU_PCLK,
1450 21, 0, 0),
1451 GATE(CLK_GOUT_MFCMSCL_SYSMMU_CLK, "gout_mfcmscl_sysmmu_clk",
1452 "mout_mfcmscl_mfc_user", CLK_CON_GAT_GOUT_MFCMSCL_SYSMMU_CLK_S1,
1453 21, 0, 0),
1454 GATE(CLK_GOUT_MFCMSCL_SYSREG_PCLK, "gout_mfcmscl_sysreg_pclk",
1455 "dout_mfcmscl_busp", CLK_CON_GAT_GOUT_MFCMSCL_SYSREG_PCLK,
1456 21, 0, 0),
1457 };
1458
1459 static const struct samsung_cmu_info mfcmscl_cmu_info __initconst = {
1460 .mux_clks = mfcmscl_mux_clks,
1461 .nr_mux_clks = ARRAY_SIZE(mfcmscl_mux_clks),
1462 .div_clks = mfcmscl_div_clks,
1463 .nr_div_clks = ARRAY_SIZE(mfcmscl_div_clks),
1464 .gate_clks = mfcmscl_gate_clks,
1465 .nr_gate_clks = ARRAY_SIZE(mfcmscl_gate_clks),
1466 .nr_clk_ids = CLKS_NR_MFCMSCL,
1467 .clk_regs = mfcmscl_clk_regs,
1468 .nr_clk_regs = ARRAY_SIZE(mfcmscl_clk_regs),
1469 .clk_name = "dout_mfcmscl_mfc",
1470 };
1471
1472 /* ---- CMU_PERI ------------------------------------------------------------ */
1473
1474 /* Register Offset definitions for CMU_PERI (0x10030000) */
1475 #define PLL_CON0_MUX_CLKCMU_PERI_BUS_USER 0x0600
1476 #define PLL_CON0_MUX_CLKCMU_PERI_HSI2C_USER 0x0610
1477 #define PLL_CON0_MUX_CLKCMU_PERI_SPI_USER 0x0620
1478 #define PLL_CON0_MUX_CLKCMU_PERI_UART_USER 0x0630
1479 #define CLK_CON_DIV_DIV_CLK_PERI_HSI2C_0 0x1800
1480 #define CLK_CON_DIV_DIV_CLK_PERI_HSI2C_1 0x1804
1481 #define CLK_CON_DIV_DIV_CLK_PERI_HSI2C_2 0x1808
1482 #define CLK_CON_DIV_DIV_CLK_PERI_SPI_0 0x180c
1483 #define CLK_CON_GAT_GATE_CLK_PERI_HSI2C_0 0x200c
1484 #define CLK_CON_GAT_GATE_CLK_PERI_HSI2C_1 0x2010
1485 #define CLK_CON_GAT_GATE_CLK_PERI_HSI2C_2 0x2014
1486 #define CLK_CON_GAT_GOUT_PERI_GPIO_PERI_PCLK 0x2020
1487 #define CLK_CON_GAT_GOUT_PERI_HSI2C_0_IPCLK 0x2024
1488 #define CLK_CON_GAT_GOUT_PERI_HSI2C_0_PCLK 0x2028
1489 #define CLK_CON_GAT_GOUT_PERI_HSI2C_1_IPCLK 0x202c
1490 #define CLK_CON_GAT_GOUT_PERI_HSI2C_1_PCLK 0x2030
1491 #define CLK_CON_GAT_GOUT_PERI_HSI2C_2_IPCLK 0x2034
1492 #define CLK_CON_GAT_GOUT_PERI_HSI2C_2_PCLK 0x2038
1493 #define CLK_CON_GAT_GOUT_PERI_I2C_0_PCLK 0x203c
1494 #define CLK_CON_GAT_GOUT_PERI_I2C_1_PCLK 0x2040
1495 #define CLK_CON_GAT_GOUT_PERI_I2C_2_PCLK 0x2044
1496 #define CLK_CON_GAT_GOUT_PERI_I2C_3_PCLK 0x2048
1497 #define CLK_CON_GAT_GOUT_PERI_I2C_4_PCLK 0x204c
1498 #define CLK_CON_GAT_GOUT_PERI_I2C_5_PCLK 0x2050
1499 #define CLK_CON_GAT_GOUT_PERI_I2C_6_PCLK 0x2054
1500 #define CLK_CON_GAT_GOUT_PERI_MCT_PCLK 0x205c
1501 #define CLK_CON_GAT_GOUT_PERI_PWM_MOTOR_PCLK 0x2064
1502 #define CLK_CON_GAT_GOUT_PERI_SPI_0_IPCLK 0x209c
1503 #define CLK_CON_GAT_GOUT_PERI_SPI_0_PCLK 0x20a0
1504 #define CLK_CON_GAT_GOUT_PERI_SYSREG_PERI_PCLK 0x20a4
1505 #define CLK_CON_GAT_GOUT_PERI_UART_IPCLK 0x20a8
1506 #define CLK_CON_GAT_GOUT_PERI_UART_PCLK 0x20ac
1507 #define CLK_CON_GAT_GOUT_PERI_WDT_0_PCLK 0x20b0
1508 #define CLK_CON_GAT_GOUT_PERI_WDT_1_PCLK 0x20b4
1509
1510 static const unsigned long peri_clk_regs[] __initconst = {
1511 PLL_CON0_MUX_CLKCMU_PERI_BUS_USER,
1512 PLL_CON0_MUX_CLKCMU_PERI_HSI2C_USER,
1513 PLL_CON0_MUX_CLKCMU_PERI_SPI_USER,
1514 PLL_CON0_MUX_CLKCMU_PERI_UART_USER,
1515 CLK_CON_DIV_DIV_CLK_PERI_HSI2C_0,
1516 CLK_CON_DIV_DIV_CLK_PERI_HSI2C_1,
1517 CLK_CON_DIV_DIV_CLK_PERI_HSI2C_2,
1518 CLK_CON_DIV_DIV_CLK_PERI_SPI_0,
1519 CLK_CON_GAT_GATE_CLK_PERI_HSI2C_0,
1520 CLK_CON_GAT_GATE_CLK_PERI_HSI2C_1,
1521 CLK_CON_GAT_GATE_CLK_PERI_HSI2C_2,
1522 CLK_CON_GAT_GOUT_PERI_GPIO_PERI_PCLK,
1523 CLK_CON_GAT_GOUT_PERI_HSI2C_0_IPCLK,
1524 CLK_CON_GAT_GOUT_PERI_HSI2C_0_PCLK,
1525 CLK_CON_GAT_GOUT_PERI_HSI2C_1_IPCLK,
1526 CLK_CON_GAT_GOUT_PERI_HSI2C_1_PCLK,
1527 CLK_CON_GAT_GOUT_PERI_HSI2C_2_IPCLK,
1528 CLK_CON_GAT_GOUT_PERI_HSI2C_2_PCLK,
1529 CLK_CON_GAT_GOUT_PERI_I2C_0_PCLK,
1530 CLK_CON_GAT_GOUT_PERI_I2C_1_PCLK,
1531 CLK_CON_GAT_GOUT_PERI_I2C_2_PCLK,
1532 CLK_CON_GAT_GOUT_PERI_I2C_3_PCLK,
1533 CLK_CON_GAT_GOUT_PERI_I2C_4_PCLK,
1534 CLK_CON_GAT_GOUT_PERI_I2C_5_PCLK,
1535 CLK_CON_GAT_GOUT_PERI_I2C_6_PCLK,
1536 CLK_CON_GAT_GOUT_PERI_MCT_PCLK,
1537 CLK_CON_GAT_GOUT_PERI_PWM_MOTOR_PCLK,
1538 CLK_CON_GAT_GOUT_PERI_SPI_0_IPCLK,
1539 CLK_CON_GAT_GOUT_PERI_SPI_0_PCLK,
1540 CLK_CON_GAT_GOUT_PERI_SYSREG_PERI_PCLK,
1541 CLK_CON_GAT_GOUT_PERI_UART_IPCLK,
1542 CLK_CON_GAT_GOUT_PERI_UART_PCLK,
1543 CLK_CON_GAT_GOUT_PERI_WDT_0_PCLK,
1544 CLK_CON_GAT_GOUT_PERI_WDT_1_PCLK,
1545 };
1546
1547 /* List of parent clocks for Muxes in CMU_PERI */
1548 PNAME(mout_peri_bus_user_p) = { "oscclk", "dout_peri_bus" };
1549 PNAME(mout_peri_uart_user_p) = { "oscclk", "dout_peri_uart" };
1550 PNAME(mout_peri_hsi2c_user_p) = { "oscclk", "dout_peri_ip" };
1551 PNAME(mout_peri_spi_user_p) = { "oscclk", "dout_peri_ip" };
1552
1553 static const struct samsung_mux_clock peri_mux_clks[] __initconst = {
1554 MUX(CLK_MOUT_PERI_BUS_USER, "mout_peri_bus_user", mout_peri_bus_user_p,
1555 PLL_CON0_MUX_CLKCMU_PERI_BUS_USER, 4, 1),
1556 MUX(CLK_MOUT_PERI_UART_USER, "mout_peri_uart_user",
1557 mout_peri_uart_user_p, PLL_CON0_MUX_CLKCMU_PERI_UART_USER, 4, 1),
1558 MUX(CLK_MOUT_PERI_HSI2C_USER, "mout_peri_hsi2c_user",
1559 mout_peri_hsi2c_user_p, PLL_CON0_MUX_CLKCMU_PERI_HSI2C_USER, 4, 1),
1560 MUX_F(CLK_MOUT_PERI_SPI_USER, "mout_peri_spi_user",
1561 mout_peri_spi_user_p, PLL_CON0_MUX_CLKCMU_PERI_SPI_USER, 4, 1,
1562 CLK_SET_RATE_PARENT, 0),
1563 };
1564
1565 static const struct samsung_div_clock peri_div_clks[] __initconst = {
1566 DIV(CLK_DOUT_PERI_HSI2C0, "dout_peri_hsi2c0", "gout_peri_hsi2c0",
1567 CLK_CON_DIV_DIV_CLK_PERI_HSI2C_0, 0, 5),
1568 DIV(CLK_DOUT_PERI_HSI2C1, "dout_peri_hsi2c1", "gout_peri_hsi2c1",
1569 CLK_CON_DIV_DIV_CLK_PERI_HSI2C_1, 0, 5),
1570 DIV(CLK_DOUT_PERI_HSI2C2, "dout_peri_hsi2c2", "gout_peri_hsi2c2",
1571 CLK_CON_DIV_DIV_CLK_PERI_HSI2C_2, 0, 5),
1572 DIV_F(CLK_DOUT_PERI_SPI0, "dout_peri_spi0", "mout_peri_spi_user",
1573 CLK_CON_DIV_DIV_CLK_PERI_SPI_0, 0, 5, CLK_SET_RATE_PARENT, 0),
1574 };
1575
1576 static const struct samsung_gate_clock peri_gate_clks[] __initconst = {
1577 GATE(CLK_GOUT_PERI_HSI2C0, "gout_peri_hsi2c0", "mout_peri_hsi2c_user",
1578 CLK_CON_GAT_GATE_CLK_PERI_HSI2C_0, 21, 0, 0),
1579 GATE(CLK_GOUT_PERI_HSI2C1, "gout_peri_hsi2c1", "mout_peri_hsi2c_user",
1580 CLK_CON_GAT_GATE_CLK_PERI_HSI2C_1, 21, 0, 0),
1581 GATE(CLK_GOUT_PERI_HSI2C2, "gout_peri_hsi2c2", "mout_peri_hsi2c_user",
1582 CLK_CON_GAT_GATE_CLK_PERI_HSI2C_2, 21, 0, 0),
1583 GATE(CLK_GOUT_HSI2C0_IPCLK, "gout_hsi2c0_ipclk", "dout_peri_hsi2c0",
1584 CLK_CON_GAT_GOUT_PERI_HSI2C_0_IPCLK, 21, 0, 0),
1585 GATE(CLK_GOUT_HSI2C0_PCLK, "gout_hsi2c0_pclk", "mout_peri_bus_user",
1586 CLK_CON_GAT_GOUT_PERI_HSI2C_0_PCLK, 21, 0, 0),
1587 GATE(CLK_GOUT_HSI2C1_IPCLK, "gout_hsi2c1_ipclk", "dout_peri_hsi2c1",
1588 CLK_CON_GAT_GOUT_PERI_HSI2C_1_IPCLK, 21, 0, 0),
1589 GATE(CLK_GOUT_HSI2C1_PCLK, "gout_hsi2c1_pclk", "mout_peri_bus_user",
1590 CLK_CON_GAT_GOUT_PERI_HSI2C_1_PCLK, 21, 0, 0),
1591 GATE(CLK_GOUT_HSI2C2_IPCLK, "gout_hsi2c2_ipclk", "dout_peri_hsi2c2",
1592 CLK_CON_GAT_GOUT_PERI_HSI2C_2_IPCLK, 21, 0, 0),
1593 GATE(CLK_GOUT_HSI2C2_PCLK, "gout_hsi2c2_pclk", "mout_peri_bus_user",
1594 CLK_CON_GAT_GOUT_PERI_HSI2C_2_PCLK, 21, 0, 0),
1595 GATE(CLK_GOUT_I2C0_PCLK, "gout_i2c0_pclk", "mout_peri_bus_user",
1596 CLK_CON_GAT_GOUT_PERI_I2C_0_PCLK, 21, 0, 0),
1597 GATE(CLK_GOUT_I2C1_PCLK, "gout_i2c1_pclk", "mout_peri_bus_user",
1598 CLK_CON_GAT_GOUT_PERI_I2C_1_PCLK, 21, 0, 0),
1599 GATE(CLK_GOUT_I2C2_PCLK, "gout_i2c2_pclk", "mout_peri_bus_user",
1600 CLK_CON_GAT_GOUT_PERI_I2C_2_PCLK, 21, 0, 0),
1601 GATE(CLK_GOUT_I2C3_PCLK, "gout_i2c3_pclk", "mout_peri_bus_user",
1602 CLK_CON_GAT_GOUT_PERI_I2C_3_PCLK, 21, 0, 0),
1603 GATE(CLK_GOUT_I2C4_PCLK, "gout_i2c4_pclk", "mout_peri_bus_user",
1604 CLK_CON_GAT_GOUT_PERI_I2C_4_PCLK, 21, 0, 0),
1605 GATE(CLK_GOUT_I2C5_PCLK, "gout_i2c5_pclk", "mout_peri_bus_user",
1606 CLK_CON_GAT_GOUT_PERI_I2C_5_PCLK, 21, 0, 0),
1607 GATE(CLK_GOUT_I2C6_PCLK, "gout_i2c6_pclk", "mout_peri_bus_user",
1608 CLK_CON_GAT_GOUT_PERI_I2C_6_PCLK, 21, 0, 0),
1609 GATE(CLK_GOUT_MCT_PCLK, "gout_mct_pclk", "mout_peri_bus_user",
1610 CLK_CON_GAT_GOUT_PERI_MCT_PCLK, 21, 0, 0),
1611 GATE(CLK_GOUT_PWM_MOTOR_PCLK, "gout_pwm_motor_pclk",
1612 "mout_peri_bus_user",
1613 CLK_CON_GAT_GOUT_PERI_PWM_MOTOR_PCLK, 21, 0, 0),
1614 GATE(CLK_GOUT_SPI0_IPCLK, "gout_spi0_ipclk", "dout_peri_spi0",
1615 CLK_CON_GAT_GOUT_PERI_SPI_0_IPCLK, 21, CLK_SET_RATE_PARENT, 0),
1616 GATE(CLK_GOUT_SPI0_PCLK, "gout_spi0_pclk", "mout_peri_bus_user",
1617 CLK_CON_GAT_GOUT_PERI_SPI_0_PCLK, 21, 0, 0),
1618 GATE(CLK_GOUT_SYSREG_PERI_PCLK, "gout_sysreg_peri_pclk",
1619 "mout_peri_bus_user",
1620 CLK_CON_GAT_GOUT_PERI_SYSREG_PERI_PCLK, 21, 0, 0),
1621 GATE(CLK_GOUT_UART_IPCLK, "gout_uart_ipclk", "mout_peri_uart_user",
1622 CLK_CON_GAT_GOUT_PERI_UART_IPCLK, 21, 0, 0),
1623 GATE(CLK_GOUT_UART_PCLK, "gout_uart_pclk", "mout_peri_bus_user",
1624 CLK_CON_GAT_GOUT_PERI_UART_PCLK, 21, 0, 0),
1625 GATE(CLK_GOUT_WDT0_PCLK, "gout_wdt0_pclk", "mout_peri_bus_user",
1626 CLK_CON_GAT_GOUT_PERI_WDT_0_PCLK, 21, 0, 0),
1627 GATE(CLK_GOUT_WDT1_PCLK, "gout_wdt1_pclk", "mout_peri_bus_user",
1628 CLK_CON_GAT_GOUT_PERI_WDT_1_PCLK, 21, 0, 0),
1629 /* TODO: Should be enabled in GPIO driver (or made CLK_IS_CRITICAL) */
1630 GATE(CLK_GOUT_GPIO_PERI_PCLK, "gout_gpio_peri_pclk",
1631 "mout_peri_bus_user",
1632 CLK_CON_GAT_GOUT_PERI_GPIO_PERI_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1633 };
1634
1635 static const struct samsung_cmu_info peri_cmu_info __initconst = {
1636 .mux_clks = peri_mux_clks,
1637 .nr_mux_clks = ARRAY_SIZE(peri_mux_clks),
1638 .div_clks = peri_div_clks,
1639 .nr_div_clks = ARRAY_SIZE(peri_div_clks),
1640 .gate_clks = peri_gate_clks,
1641 .nr_gate_clks = ARRAY_SIZE(peri_gate_clks),
1642 .nr_clk_ids = CLKS_NR_PERI,
1643 .clk_regs = peri_clk_regs,
1644 .nr_clk_regs = ARRAY_SIZE(peri_clk_regs),
1645 .clk_name = "dout_peri_bus",
1646 };
1647
exynos850_cmu_peri_init(struct device_node * np)1648 static void __init exynos850_cmu_peri_init(struct device_node *np)
1649 {
1650 exynos_arm64_register_cmu(NULL, np, &peri_cmu_info);
1651 }
1652
1653 /* Register CMU_PERI early, as it's needed for MCT timer */
1654 CLK_OF_DECLARE(exynos850_cmu_peri, "samsung,exynos850-cmu-peri",
1655 exynos850_cmu_peri_init);
1656
1657 /* ---- CMU_CORE ------------------------------------------------------------ */
1658
1659 /* Register Offset definitions for CMU_CORE (0x12000000) */
1660 #define PLL_CON0_MUX_CLKCMU_CORE_BUS_USER 0x0600
1661 #define PLL_CON0_MUX_CLKCMU_CORE_CCI_USER 0x0610
1662 #define PLL_CON0_MUX_CLKCMU_CORE_MMC_EMBD_USER 0x0620
1663 #define PLL_CON0_MUX_CLKCMU_CORE_SSS_USER 0x0630
1664 #define CLK_CON_MUX_MUX_CLK_CORE_GIC 0x1000
1665 #define CLK_CON_DIV_DIV_CLK_CORE_BUSP 0x1800
1666 #define CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK 0x2038
1667 #define CLK_CON_GAT_GOUT_CORE_GIC_CLK 0x2040
1668 #define CLK_CON_GAT_GOUT_CORE_GPIO_CORE_PCLK 0x2044
1669 #define CLK_CON_GAT_GOUT_CORE_MMC_EMBD_I_ACLK 0x20e8
1670 #define CLK_CON_GAT_GOUT_CORE_MMC_EMBD_SDCLKIN 0x20ec
1671 #define CLK_CON_GAT_GOUT_CORE_SSS_I_ACLK 0x2128
1672 #define CLK_CON_GAT_GOUT_CORE_SSS_I_PCLK 0x212c
1673 #define CLK_CON_GAT_GOUT_CORE_SYSREG_CORE_PCLK 0x2130
1674
1675 static const unsigned long core_clk_regs[] __initconst = {
1676 PLL_CON0_MUX_CLKCMU_CORE_BUS_USER,
1677 PLL_CON0_MUX_CLKCMU_CORE_CCI_USER,
1678 PLL_CON0_MUX_CLKCMU_CORE_MMC_EMBD_USER,
1679 PLL_CON0_MUX_CLKCMU_CORE_SSS_USER,
1680 CLK_CON_MUX_MUX_CLK_CORE_GIC,
1681 CLK_CON_DIV_DIV_CLK_CORE_BUSP,
1682 CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK,
1683 CLK_CON_GAT_GOUT_CORE_GIC_CLK,
1684 CLK_CON_GAT_GOUT_CORE_GPIO_CORE_PCLK,
1685 CLK_CON_GAT_GOUT_CORE_MMC_EMBD_I_ACLK,
1686 CLK_CON_GAT_GOUT_CORE_MMC_EMBD_SDCLKIN,
1687 CLK_CON_GAT_GOUT_CORE_SSS_I_ACLK,
1688 CLK_CON_GAT_GOUT_CORE_SSS_I_PCLK,
1689 CLK_CON_GAT_GOUT_CORE_SYSREG_CORE_PCLK,
1690 };
1691
1692 /* List of parent clocks for Muxes in CMU_CORE */
1693 PNAME(mout_core_bus_user_p) = { "oscclk", "dout_core_bus" };
1694 PNAME(mout_core_cci_user_p) = { "oscclk", "dout_core_cci" };
1695 PNAME(mout_core_mmc_embd_user_p) = { "oscclk", "dout_core_mmc_embd" };
1696 PNAME(mout_core_sss_user_p) = { "oscclk", "dout_core_sss" };
1697 PNAME(mout_core_gic_p) = { "dout_core_busp", "oscclk" };
1698
1699 static const struct samsung_mux_clock core_mux_clks[] __initconst = {
1700 MUX(CLK_MOUT_CORE_BUS_USER, "mout_core_bus_user", mout_core_bus_user_p,
1701 PLL_CON0_MUX_CLKCMU_CORE_BUS_USER, 4, 1),
1702 MUX(CLK_MOUT_CORE_CCI_USER, "mout_core_cci_user", mout_core_cci_user_p,
1703 PLL_CON0_MUX_CLKCMU_CORE_CCI_USER, 4, 1),
1704 MUX_F(CLK_MOUT_CORE_MMC_EMBD_USER, "mout_core_mmc_embd_user",
1705 mout_core_mmc_embd_user_p, PLL_CON0_MUX_CLKCMU_CORE_MMC_EMBD_USER,
1706 4, 1, CLK_SET_RATE_PARENT, 0),
1707 MUX(CLK_MOUT_CORE_SSS_USER, "mout_core_sss_user", mout_core_sss_user_p,
1708 PLL_CON0_MUX_CLKCMU_CORE_SSS_USER, 4, 1),
1709 MUX(CLK_MOUT_CORE_GIC, "mout_core_gic", mout_core_gic_p,
1710 CLK_CON_MUX_MUX_CLK_CORE_GIC, 0, 1),
1711 };
1712
1713 static const struct samsung_div_clock core_div_clks[] __initconst = {
1714 DIV(CLK_DOUT_CORE_BUSP, "dout_core_busp", "mout_core_bus_user",
1715 CLK_CON_DIV_DIV_CLK_CORE_BUSP, 0, 2),
1716 };
1717
1718 static const struct samsung_gate_clock core_gate_clks[] __initconst = {
1719 /* CCI (interconnect) clock must be always running */
1720 GATE(CLK_GOUT_CCI_ACLK, "gout_cci_aclk", "mout_core_cci_user",
1721 CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK, 21, CLK_IS_CRITICAL, 0),
1722 /* GIC (interrupt controller) clock must be always running */
1723 GATE(CLK_GOUT_GIC_CLK, "gout_gic_clk", "mout_core_gic",
1724 CLK_CON_GAT_GOUT_CORE_GIC_CLK, 21, CLK_IS_CRITICAL, 0),
1725 GATE(CLK_GOUT_MMC_EMBD_ACLK, "gout_mmc_embd_aclk", "dout_core_busp",
1726 CLK_CON_GAT_GOUT_CORE_MMC_EMBD_I_ACLK, 21, 0, 0),
1727 GATE(CLK_GOUT_MMC_EMBD_SDCLKIN, "gout_mmc_embd_sdclkin",
1728 "mout_core_mmc_embd_user", CLK_CON_GAT_GOUT_CORE_MMC_EMBD_SDCLKIN,
1729 21, CLK_SET_RATE_PARENT, 0),
1730 GATE(CLK_GOUT_SSS_ACLK, "gout_sss_aclk", "mout_core_sss_user",
1731 CLK_CON_GAT_GOUT_CORE_SSS_I_ACLK, 21, 0, 0),
1732 GATE(CLK_GOUT_SSS_PCLK, "gout_sss_pclk", "dout_core_busp",
1733 CLK_CON_GAT_GOUT_CORE_SSS_I_PCLK, 21, 0, 0),
1734 /* TODO: Should be enabled in GPIO driver (or made CLK_IS_CRITICAL) */
1735 GATE(CLK_GOUT_GPIO_CORE_PCLK, "gout_gpio_core_pclk", "dout_core_busp",
1736 CLK_CON_GAT_GOUT_CORE_GPIO_CORE_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1737 GATE(CLK_GOUT_SYSREG_CORE_PCLK, "gout_sysreg_core_pclk",
1738 "dout_core_busp",
1739 CLK_CON_GAT_GOUT_CORE_SYSREG_CORE_PCLK, 21, 0, 0),
1740 };
1741
1742 static const struct samsung_cmu_info core_cmu_info __initconst = {
1743 .mux_clks = core_mux_clks,
1744 .nr_mux_clks = ARRAY_SIZE(core_mux_clks),
1745 .div_clks = core_div_clks,
1746 .nr_div_clks = ARRAY_SIZE(core_div_clks),
1747 .gate_clks = core_gate_clks,
1748 .nr_gate_clks = ARRAY_SIZE(core_gate_clks),
1749 .nr_clk_ids = CLKS_NR_CORE,
1750 .clk_regs = core_clk_regs,
1751 .nr_clk_regs = ARRAY_SIZE(core_clk_regs),
1752 .clk_name = "dout_core_bus",
1753 };
1754
1755 /* ---- CMU_DPU ------------------------------------------------------------- */
1756
1757 /* Register Offset definitions for CMU_DPU (0x13000000) */
1758 #define PLL_CON0_MUX_CLKCMU_DPU_USER 0x0600
1759 #define CLK_CON_DIV_DIV_CLK_DPU_BUSP 0x1800
1760 #define CLK_CON_GAT_CLK_DPU_CMU_DPU_PCLK 0x2004
1761 #define CLK_CON_GAT_GOUT_DPU_ACLK_DECON0 0x2010
1762 #define CLK_CON_GAT_GOUT_DPU_ACLK_DMA 0x2014
1763 #define CLK_CON_GAT_GOUT_DPU_ACLK_DPP 0x2018
1764 #define CLK_CON_GAT_GOUT_DPU_PPMU_ACLK 0x2028
1765 #define CLK_CON_GAT_GOUT_DPU_PPMU_PCLK 0x202c
1766 #define CLK_CON_GAT_GOUT_DPU_SMMU_CLK 0x2038
1767 #define CLK_CON_GAT_GOUT_DPU_SYSREG_PCLK 0x203c
1768
1769 static const unsigned long dpu_clk_regs[] __initconst = {
1770 PLL_CON0_MUX_CLKCMU_DPU_USER,
1771 CLK_CON_DIV_DIV_CLK_DPU_BUSP,
1772 CLK_CON_GAT_CLK_DPU_CMU_DPU_PCLK,
1773 CLK_CON_GAT_GOUT_DPU_ACLK_DECON0,
1774 CLK_CON_GAT_GOUT_DPU_ACLK_DMA,
1775 CLK_CON_GAT_GOUT_DPU_ACLK_DPP,
1776 CLK_CON_GAT_GOUT_DPU_PPMU_ACLK,
1777 CLK_CON_GAT_GOUT_DPU_PPMU_PCLK,
1778 CLK_CON_GAT_GOUT_DPU_SMMU_CLK,
1779 CLK_CON_GAT_GOUT_DPU_SYSREG_PCLK,
1780 };
1781
1782 /* List of parent clocks for Muxes in CMU_DPU */
1783 PNAME(mout_dpu_user_p) = { "oscclk", "dout_dpu" };
1784
1785 static const struct samsung_mux_clock dpu_mux_clks[] __initconst = {
1786 MUX(CLK_MOUT_DPU_USER, "mout_dpu_user", mout_dpu_user_p,
1787 PLL_CON0_MUX_CLKCMU_DPU_USER, 4, 1),
1788 };
1789
1790 static const struct samsung_div_clock dpu_div_clks[] __initconst = {
1791 DIV(CLK_DOUT_DPU_BUSP, "dout_dpu_busp", "mout_dpu_user",
1792 CLK_CON_DIV_DIV_CLK_DPU_BUSP, 0, 3),
1793 };
1794
1795 static const struct samsung_gate_clock dpu_gate_clks[] __initconst = {
1796 /* TODO: Should be enabled in DSIM driver */
1797 GATE(CLK_GOUT_DPU_CMU_DPU_PCLK, "gout_dpu_cmu_dpu_pclk",
1798 "dout_dpu_busp",
1799 CLK_CON_GAT_CLK_DPU_CMU_DPU_PCLK, 21, CLK_IGNORE_UNUSED, 0),
1800 GATE(CLK_GOUT_DPU_DECON0_ACLK, "gout_dpu_decon0_aclk", "mout_dpu_user",
1801 CLK_CON_GAT_GOUT_DPU_ACLK_DECON0, 21, 0, 0),
1802 GATE(CLK_GOUT_DPU_DMA_ACLK, "gout_dpu_dma_aclk", "mout_dpu_user",
1803 CLK_CON_GAT_GOUT_DPU_ACLK_DMA, 21, 0, 0),
1804 GATE(CLK_GOUT_DPU_DPP_ACLK, "gout_dpu_dpp_aclk", "mout_dpu_user",
1805 CLK_CON_GAT_GOUT_DPU_ACLK_DPP, 21, 0, 0),
1806 GATE(CLK_GOUT_DPU_PPMU_ACLK, "gout_dpu_ppmu_aclk", "mout_dpu_user",
1807 CLK_CON_GAT_GOUT_DPU_PPMU_ACLK, 21, 0, 0),
1808 GATE(CLK_GOUT_DPU_PPMU_PCLK, "gout_dpu_ppmu_pclk", "dout_dpu_busp",
1809 CLK_CON_GAT_GOUT_DPU_PPMU_PCLK, 21, 0, 0),
1810 GATE(CLK_GOUT_DPU_SMMU_CLK, "gout_dpu_smmu_clk", "mout_dpu_user",
1811 CLK_CON_GAT_GOUT_DPU_SMMU_CLK, 21, 0, 0),
1812 GATE(CLK_GOUT_DPU_SYSREG_PCLK, "gout_dpu_sysreg_pclk", "dout_dpu_busp",
1813 CLK_CON_GAT_GOUT_DPU_SYSREG_PCLK, 21, 0, 0),
1814 };
1815
1816 static const struct samsung_cmu_info dpu_cmu_info __initconst = {
1817 .mux_clks = dpu_mux_clks,
1818 .nr_mux_clks = ARRAY_SIZE(dpu_mux_clks),
1819 .div_clks = dpu_div_clks,
1820 .nr_div_clks = ARRAY_SIZE(dpu_div_clks),
1821 .gate_clks = dpu_gate_clks,
1822 .nr_gate_clks = ARRAY_SIZE(dpu_gate_clks),
1823 .nr_clk_ids = CLKS_NR_DPU,
1824 .clk_regs = dpu_clk_regs,
1825 .nr_clk_regs = ARRAY_SIZE(dpu_clk_regs),
1826 .clk_name = "dout_dpu",
1827 };
1828
1829 /* ---- platform_driver ----------------------------------------------------- */
1830
exynos850_cmu_probe(struct platform_device * pdev)1831 static int __init exynos850_cmu_probe(struct platform_device *pdev)
1832 {
1833 const struct samsung_cmu_info *info;
1834 struct device *dev = &pdev->dev;
1835
1836 info = of_device_get_match_data(dev);
1837 exynos_arm64_register_cmu(dev, dev->of_node, info);
1838
1839 return 0;
1840 }
1841
1842 static const struct of_device_id exynos850_cmu_of_match[] = {
1843 {
1844 .compatible = "samsung,exynos850-cmu-apm",
1845 .data = &apm_cmu_info,
1846 }, {
1847 .compatible = "samsung,exynos850-cmu-aud",
1848 .data = &aud_cmu_info,
1849 }, {
1850 .compatible = "samsung,exynos850-cmu-cmgp",
1851 .data = &cmgp_cmu_info,
1852 }, {
1853 .compatible = "samsung,exynos850-cmu-g3d",
1854 .data = &g3d_cmu_info,
1855 }, {
1856 .compatible = "samsung,exynos850-cmu-hsi",
1857 .data = &hsi_cmu_info,
1858 }, {
1859 .compatible = "samsung,exynos850-cmu-is",
1860 .data = &is_cmu_info,
1861 }, {
1862 .compatible = "samsung,exynos850-cmu-mfcmscl",
1863 .data = &mfcmscl_cmu_info,
1864 }, {
1865 .compatible = "samsung,exynos850-cmu-core",
1866 .data = &core_cmu_info,
1867 }, {
1868 .compatible = "samsung,exynos850-cmu-dpu",
1869 .data = &dpu_cmu_info,
1870 }, {
1871 },
1872 };
1873
1874 static struct platform_driver exynos850_cmu_driver __refdata = {
1875 .driver = {
1876 .name = "exynos850-cmu",
1877 .of_match_table = exynos850_cmu_of_match,
1878 .suppress_bind_attrs = true,
1879 },
1880 .probe = exynos850_cmu_probe,
1881 };
1882
exynos850_cmu_init(void)1883 static int __init exynos850_cmu_init(void)
1884 {
1885 return platform_driver_register(&exynos850_cmu_driver);
1886 }
1887 core_initcall(exynos850_cmu_init);
1888