1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Amlogic Meson Video Processing Unit driver
4  *
5  * Copyright (c) 2018 BayLibre, SAS.
6  * Author: Neil Armstrong <narmstrong@baylibre.com>
7  */
8 
9 #include "meson_vpu.h"
10 
11 /* OSDx_BLKx_CFG */
12 #define OSD_CANVAS_SEL		16
13 
14 #define OSD_ENDIANNESS_LE	BIT(15)
15 #define OSD_ENDIANNESS_BE	(0)
16 
17 #define OSD_BLK_MODE_422	(0x03 << 8)
18 #define OSD_BLK_MODE_16		(0x04 << 8)
19 #define OSD_BLK_MODE_32		(0x05 << 8)
20 #define OSD_BLK_MODE_24		(0x07 << 8)
21 
22 #define OSD_OUTPUT_COLOR_RGB	BIT(7)
23 #define OSD_OUTPUT_COLOR_YUV	(0)
24 
25 #define OSD_COLOR_MATRIX_32_RGBA	(0x00 << 2)
26 #define OSD_COLOR_MATRIX_32_ARGB	(0x01 << 2)
27 #define OSD_COLOR_MATRIX_32_ABGR	(0x02 << 2)
28 #define OSD_COLOR_MATRIX_32_BGRA	(0x03 << 2)
29 
30 #define OSD_COLOR_MATRIX_24_RGB		(0x00 << 2)
31 
32 #define OSD_COLOR_MATRIX_16_RGB655	(0x00 << 2)
33 #define OSD_COLOR_MATRIX_16_RGB565	(0x04 << 2)
34 
35 #define OSD_INTERLACE_ENABLED	BIT(1)
36 #define OSD_INTERLACE_ODD	BIT(0)
37 #define OSD_INTERLACE_EVEN	(0)
38 
39 /* OSDx_CTRL_STAT */
40 #define OSD_ENABLE		BIT(21)
41 #define OSD_BLK0_ENABLE		BIT(0)
42 
43 #define OSD_GLOBAL_ALPHA_SHIFT	12
44 
45 /* OSDx_CTRL_STAT2 */
46 #define OSD_REPLACE_EN		BIT(14)
47 #define OSD_REPLACE_SHIFT	6
48 
49 /*
50  * When the output is interlaced, the OSD must switch between
51  * each field using the INTERLACE_SEL_ODD (0) of VIU_OSD1_BLK0_CFG_W0
52  * at each vsync.
53  * But the vertical scaler can provide such funtionnality if
54  * is configured for 2:1 scaling with interlace options enabled.
55  */
meson_vpp_setup_interlace_vscaler_osd1(struct meson_vpu_priv * priv,struct video_priv * uc_priv)56 static void meson_vpp_setup_interlace_vscaler_osd1(struct meson_vpu_priv *priv,
57 						   struct video_priv *uc_priv)
58 {
59 	writel(BIT(3) /* Enable scaler */ |
60 	       BIT(2), /* Select OSD1 */
61 	       priv->io_base + _REG(VPP_OSD_SC_CTRL0));
62 
63 	writel(((uc_priv->xsize - 1) << 16) | (uc_priv->ysize - 1),
64 	       priv->io_base + _REG(VPP_OSD_SCI_WH_M1));
65 	/* 2:1 scaling */
66 	writel((0 << 16) | uc_priv->xsize,
67 	       priv->io_base + _REG(VPP_OSD_SCO_H_START_END));
68 	writel(((0 >> 1) << 16) | (uc_priv->ysize >> 1),
69 	       priv->io_base + _REG(VPP_OSD_SCO_V_START_END));
70 
71 	/* 2:1 scaling values */
72 	writel(BIT(16), priv->io_base + _REG(VPP_OSD_VSC_INI_PHASE));
73 	writel(BIT(25), priv->io_base + _REG(VPP_OSD_VSC_PHASE_STEP));
74 
75 	writel(0, priv->io_base + _REG(VPP_OSD_HSC_CTRL0));
76 
77 	writel((4 << 0)  /* osd_vsc_bank_length */ |
78 	       (4 << 3)  /* osd_vsc_top_ini_rcv_num0 */ |
79 	       (1 << 8)  /* osd_vsc_top_rpt_p0_num0 */ |
80 	       (6 << 11) /* osd_vsc_bot_ini_rcv_num0 */ |
81 	       (2 << 16) /* osd_vsc_bot_rpt_p0_num0 */ |
82 	       BIT(23)	 /* osd_prog_interlace */ |
83 	       BIT(24),  /* Enable vertical scaler */
84 	       priv->io_base + _REG(VPP_OSD_VSC_CTRL0));
85 }
86 
87 static void
meson_vpp_disable_interlace_vscaler_osd1(struct meson_vpu_priv * priv)88 meson_vpp_disable_interlace_vscaler_osd1(struct meson_vpu_priv *priv)
89 {
90 	writel(0, priv->io_base + _REG(VPP_OSD_SC_CTRL0));
91 	writel(0, priv->io_base + _REG(VPP_OSD_VSC_CTRL0));
92 	writel(0, priv->io_base + _REG(VPP_OSD_HSC_CTRL0));
93 }
94 
meson_vpu_setup_plane(struct udevice * dev,bool is_interlaced)95 void meson_vpu_setup_plane(struct udevice *dev, bool is_interlaced)
96 {
97 	struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev);
98 	struct video_priv *uc_priv = dev_get_uclass_priv(dev);
99 	struct meson_vpu_priv *priv = dev_get_priv(dev);
100 	u32 osd1_ctrl_stat;
101 	u32 osd1_blk0_cfg[5];
102 	bool osd1_interlace;
103 	unsigned int src_x1, src_x2, src_y1, src_y2;
104 	unsigned int dest_x1, dest_x2, dest_y1, dest_y2;
105 
106 	dest_x1 = src_x1 = 0;
107 	dest_x2 = src_x2 = uc_priv->xsize;
108 	dest_y1 = src_y1 = 0;
109 	dest_y2 = src_y2 = uc_priv->ysize;
110 
111 	/* Enable VPP Postblend */
112 	writel(uc_priv->xsize,
113 	       priv->io_base + _REG(VPP_POSTBLEND_H_SIZE));
114 
115 	writel_bits(VPP_POSTBLEND_ENABLE, VPP_POSTBLEND_ENABLE,
116 		    priv->io_base + _REG(VPP_MISC));
117 
118 	/* uc_plat->base is the framebuffer */
119 
120 	/* Enable OSD and BLK0, set max global alpha */
121 	osd1_ctrl_stat = OSD_ENABLE | (0xFF << OSD_GLOBAL_ALPHA_SHIFT) |
122 			 OSD_BLK0_ENABLE;
123 
124 	/* Set up BLK0 to point to the right canvas */
125 	osd1_blk0_cfg[0] = ((MESON_CANVAS_ID_OSD1 << OSD_CANVAS_SEL) |
126 			   OSD_ENDIANNESS_LE);
127 
128 	/* On GXBB, Use the old non-HDR RGB2YUV converter */
129 	if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB))
130 		osd1_blk0_cfg[0] |= OSD_OUTPUT_COLOR_RGB;
131 
132 	/* For XRGB, replace the pixel's alpha by 0xFF */
133 	writel_bits(OSD_REPLACE_EN, OSD_REPLACE_EN,
134 		    priv->io_base + _REG(VIU_OSD1_CTRL_STAT2));
135 	osd1_blk0_cfg[0] |= OSD_BLK_MODE_32 |
136 		OSD_COLOR_MATRIX_32_ARGB;
137 
138 	if (is_interlaced) {
139 		osd1_interlace = true;
140 		dest_y1 /= 2;
141 		dest_y2 /= 2;
142 	} else {
143 		osd1_interlace = false;
144 	}
145 
146 	/*
147 	 * The format of these registers is (x2 << 16 | x1),
148 	 * where x2 is exclusive.
149 	 * e.g. +30x1920 would be (1919 << 16) | 30
150 	 */
151 	osd1_blk0_cfg[1] = ((src_x2 - 1) << 16) | src_x1;
152 	osd1_blk0_cfg[2] = ((src_y2 - 1) << 16) | src_y1;
153 	osd1_blk0_cfg[3] = ((dest_x2 - 1) << 16) | dest_x1;
154 	osd1_blk0_cfg[4] = ((dest_y2 - 1) << 16) | dest_y1;
155 
156 	writel(osd1_ctrl_stat, priv->io_base + _REG(VIU_OSD1_CTRL_STAT));
157 	writel(osd1_blk0_cfg[0], priv->io_base + _REG(VIU_OSD1_BLK0_CFG_W0));
158 	writel(osd1_blk0_cfg[1], priv->io_base + _REG(VIU_OSD1_BLK0_CFG_W1));
159 	writel(osd1_blk0_cfg[2], priv->io_base + _REG(VIU_OSD1_BLK0_CFG_W2));
160 	writel(osd1_blk0_cfg[3], priv->io_base + _REG(VIU_OSD1_BLK0_CFG_W3));
161 	writel(osd1_blk0_cfg[4], priv->io_base + _REG(VIU_OSD1_BLK0_CFG_W4));
162 
163 	/* If output is interlace, make use of the Scaler */
164 	if (osd1_interlace)
165 		meson_vpp_setup_interlace_vscaler_osd1(priv, uc_priv);
166 	else
167 		meson_vpp_disable_interlace_vscaler_osd1(priv);
168 
169 	meson_canvas_setup(priv, MESON_CANVAS_ID_OSD1,
170 			   uc_plat->base, uc_priv->xsize * 4,
171 			   uc_priv->ysize, MESON_CANVAS_WRAP_NONE,
172 			   MESON_CANVAS_BLKMODE_LINEAR);
173 
174 	/* Enable OSD1 */
175 	writel_bits(VPP_OSD1_POSTBLEND, VPP_OSD1_POSTBLEND,
176 		    priv->io_base + _REG(VPP_MISC));
177 }
178